Add Virtex-7 (xc7vx485t) family support

Port prjxray to the Virtex-7 family, modelled on Kintex-7, targeting
xc7vx485tffg1761-2 (vc707). Non-breaking for the existing families.

Family registration:
- settings/virtex7.sh, settings/virtex7/devices.yaml
- Makefile: virtex7 in DATABASES/XRAY_PARTS + db-extras-virtex7 targets
- utils/update_parts.py, update_resources.py: virtex7 choice
- CI matrix (Pipeline.yml), Vivado edition (xilinx.sh), README

Architecture adaptations for the HP-bank-only VX part (verified non-breaking):
- update_resources.tcl: fall back to HP banks when no HR banks exist
- XRAY_IOSTANDARD env (default LVCMOS33; LVCMOS18 for virtex7), parameterised
  across the fuzzer generate.tcl files
- fuzzers: enable HP-bank (iob18/ioi18) + IOI/HCLK handling for virtex7;
  GTX skipped (ffg1761 bonds only ~7 of 14 GTX quads)
- 005-tilegrid: HP/HR bank tile handling; iob18_int INT offset 3->2;
  ioi18 AUTO_FRAME; cfg PDRC-2 DRC disable; add_tdb skips unsolved edge tiles;
  per-specimen retry for transient FlexLM SIGSEGV under concurrency
- per-family Vivado version gate (virtex7 -> v2020.1.1)
- XRAY_ROI and XRAY_ROI_GRID tuned to a compact CLBLL+CLBLM region

General fixes:
- tools/bitread.cc: fix use-after-free of the mmap'd bitstream (exposed by the
  larger Virtex-7 bitstream)
- utils/environment.python.sh: add repo root to PYTHONPATH (PEP 660 editable
  install doesn't expose the repo-root utils/ package)

Co-Authored-By: Claude Opus 4.7 <[email protected]>

.github/scripts/xilinx.sh

@@ -32,7 +32,7 @@ echo "----------------------------------------"
 (
 	set -e
 	cd /opt
-	if [ x"$XRAY_SETTINGS" = x"kintex7" ]; then
+	if [ x"$XRAY_SETTINGS" = x"kintex7" ] || [ x"$XRAY_SETTINGS" = x"virtex7" ]; then
 		echo "Using Xilinx Vivado Design Edition for $XRAY_SETTINGS build."
 		echo
 		ln -s /mnt/aux/Xilinx-design /opt/Xilinx