From 32feed66405c34e50de9ff7a8c42e2fc0373ef2b Mon Sep 17 00:00:00 2001 From: Maciej Kurc Date: Tue, 24 Sep 2019 10:45:09 +0200 Subject: [PATCH] Removed BUFR and BUFMR, clock division implemented on logic. Signed-off-by: Maciej Kurc --- minitests/plle2_adv/src/plle2_test.v | 31 +++++++++++++++------------- 1 file changed, 17 insertions(+), 14 deletions(-) diff --git a/minitests/plle2_adv/src/plle2_test.v b/minitests/plle2_adv/src/plle2_test.v index 2eef55e8..dd70b52a 100644 --- a/minitests/plle2_adv/src/plle2_test.v +++ b/minitests/plle2_adv/src/plle2_test.v @@ -13,24 +13,27 @@ output wire [5:0] O_CNT // ============================================================================ // Input clock divider (to get different clkins) wire clk100; -wire clk50; +reg clk50; assign clk100 = CLK; -wire clkbuf; -BUFMR mr_buf (.I(CLK), .O(clkbuf)); +always @(posedge clk100) + clk50 <= !clk50; -BUFR # -( -.BUFR_DIVIDE ("2") -) -bufr -( -.I (clkbuf), -.CLR (RST), -.CE (1'b1), -.O (clk50) -); +//wire clkbuf; +//BUFMR mr_buf (.I(CLK), .O(clkbuf)); + +//BUFR # +//( +//.BUFR_DIVIDE ("2") +//) +//bufr +//( +//.I (clkbuf), +//.CLR (RST), +//.CE (1'b1), +//.O (clk50) +//); // ============================================================================ // The PLL