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Hotfix tiles_wires_pips/runme.tcl 

Signed-off-by: Clifford Wolf <clifford@clifford.at>
Signed-off-by: Tim 'mithro' Ansell <mithro@mithis.com>
This commit is contained in:
Clifford Wolf 2017-11-16 20:29:08 +01:00 committed by Tim 'mithro' Ansell
parent b209cd0e9e
commit 2d7a635085
1 changed files with 0 additions and 2 deletions
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2
minitests/tiles_wires_pips/runme.tcl
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@ -1,4 +1,3 @@
if 0 {
create_project -force -part $::env(XRAY_PART) design design create_project -force -part $::env(XRAY_PART) design design
read_verilog top.v read_verilog top.v
@ -21,7 +20,6 @@ write_checkpoint -force design.dcp
write_bitstream -force design.bit write_bitstream -force design.bit
source ../../utils/utils.tcl source ../../utils/utils.tcl
}
proc print_tile_info {tile} { proc print_tile_info {tile} {
puts "Dumping wires and PIPs for tile $tile." puts "Dumping wires and PIPs for tile $tile."