From 2d7a635085543761e37c98be78d808909cb692da Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 16 Nov 2017 20:29:08 +0100
Subject: [PATCH] Hotfix tiles_wires_pips/runme.tcl

Signed-off-by: Clifford Wolf <clifford@clifford.at>
Signed-off-by: Tim 'mithro' Ansell <mithro@mithis.com>
---
 minitests/tiles_wires_pips/runme.tcl | 2 --
 1 file changed, 2 deletions(-)

diff --git a/minitests/tiles_wires_pips/runme.tcl b/minitests/tiles_wires_pips/runme.tcl
index c51f0fac..585f47d4 100644
--- a/minitests/tiles_wires_pips/runme.tcl
+++ b/minitests/tiles_wires_pips/runme.tcl
@@ -1,4 +1,3 @@
-if 0 {
 create_project -force -part $::env(XRAY_PART) design design
 
 read_verilog top.v
@@ -21,7 +20,6 @@ write_checkpoint -force design.dcp
 write_bitstream -force design.bit
 
 source ../../utils/utils.tcl
-}
 
 proc print_tile_info {tile} {
 	puts "Dumping wires and PIPs for tile $tile."