mirror of https://github.com/openXC7/prjxray.git
Add draft 011-ffconfig fuzzer
Signed-off-by: Clifford Wolf <clifford@clifford.at> Signed-off-by: Tim 'mithro' Ansell <mithro@mithis.com>
This commit is contained in:
Clifford Wolf
Tim 'mithro' Ansell
parent
778905ff09
commit
246e343ff1
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@ -0,0 +1,26 @@
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N := 1
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SPECIMENS := $(addprefix specimen_,$(shell seq -f '%03.0f' $(N)))
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SPECIMENS_OK := $(addsuffix /OK,$(SPECIMENS))
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database: database/clbll database/clblm
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pushdb: pushdb/clbll pushdb/clblm
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database/%: $(SPECIMENS_OK)
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../../tools/segmatch -o seg_$(notdir $@).segbits \
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$(addsuffix /segdata_$(notdir $@)_[0-9].txt,$(SPECIMENS))
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pushdb/%:
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bash ../../utils/mergedb.sh seg_$(notdir $@).segbits \
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../../database/$(XRAY_DATABASE)/seg_$(notdir $@).segbits
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$(SPECIMENS_OK):
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bash generate.sh $(subst /OK,,$@)
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touch $@
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clean:
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rm -rf $(SPECIMENS) seg_clbll.segbits seg_clblm.segbits
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.PHONY: database pushdb clean
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@ -0,0 +1,122 @@
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#!/usr/bin/env python3
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import os, sys, json, re
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#################################################
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# Loading Raw Source Data
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grid = None
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bits = dict()
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data = dict()
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print("Loading grid.")
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with open("../../../database/%s/tilegrid.json" % os.getenv("XRAY_DATABASE"), "r") as f:
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grid = json.load(f)
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print("Loading bits.")
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with open("design_%s.bits" % sys.argv[1], "r") as f:
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for line in f:
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line = line.split("_")
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bit_frame = int(line[1], 16)
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bit_wordidx = int(line[2], 16)
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bit_bitidx = int(line[3], 16)
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base_frame = bit_frame & ~0x7f
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if base_frame not in bits:
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bits[base_frame] = dict()
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if bit_wordidx not in bits[base_frame]:
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bits[base_frame][bit_wordidx] = set()
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bits[base_frame][bit_wordidx].add((bit_frame, bit_wordidx, bit_bitidx))
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print("Loading text data.")
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with open("design_%s.txt" % sys.argv[1], "r") as f:
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for line in f:
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line = line.split()
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site = line[0]
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bel = line[1]
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init = int(line[2][3])
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cinv = int(line[3][3])
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dinv = int(line[4][3])
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rinv = int(line[5][3])
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if site not in data:
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data[site] = dict()
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data[site]["%s.INIT" % bel] = init
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data[site]["%s.CINV" % bel] = cinv
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data[site]["%s.DINV" % bel] = dinv
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data[site]["%s.RINV" % bel] = rinv
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#################################################
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# Group per Segment
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print("Compile segment data.")
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segments_by_type = dict()
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for tilename, tiledata in grid["tiles"].items():
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if "segment" not in tiledata:
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continue
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segdata = grid["segments"][tiledata["segment"]]
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if segdata["type"] not in segments_by_type:
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segments_by_type[segdata["type"]] = dict()
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segments = segments_by_type[segdata["type"]]
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tile_type = tiledata["type"]
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segname = "%s_%02x" % (segdata["baseaddr"][0][2:], segdata["baseaddr"][1])
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if not segname in segments:
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segments[segname] = { "bits": list(), "tags": dict() }
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for site in tiledata["sites"]:
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if site not in data:
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continue
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if re.match(r"SLICE_X[0-9]*[02468]Y", site):
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sitekey = "SLICE_X0"
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elif re.match(r"SLICE_X[0-9]*[13579]Y", site):
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sitekey = "SLICE_X1"
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else:
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assert 0
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for name, value in data[site].items():
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tag = "%s.%s.%s" % (re.sub("_[LR]$", "", tile_type), sitekey, name)
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tag = tag.replace("SLICE_X0.SLICEM", "SLICEM_X0")
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tag = tag.replace("SLICE_X1.SLICEM", "SLICEM_X1")
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tag = tag.replace("SLICE_X0.SLICEL", "SLICEL_X0")
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tag = tag.replace("SLICE_X1.SLICEL", "SLICEL_X1")
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segments[segname]["tags"][tag] = value
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base_frame = int(segdata["baseaddr"][0][2:], 16)
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for wordidx in range(segdata["baseaddr"][1], segdata["baseaddr"][1]+2):
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if base_frame not in bits:
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continue
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if wordidx not in bits[base_frame]:
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continue
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for bit_frame, bit_wordidx, bit_bitidx in bits[base_frame][wordidx]:
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segments[segname]["bits"].append("%02x_%02x_%02x" % (bit_frame - base_frame, bit_wordidx - segdata["baseaddr"][1], bit_bitidx))
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segments[segname]["bits"].sort()
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#################################################
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# Print
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print("Write segment data.")
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for segtype in segments_by_type.keys():
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with open("segdata_%s_%s.txt" % (segtype, sys.argv[1]), "w") as f:
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segments = segments_by_type[segtype]
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for segname, segdata in sorted(segments.items()):
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print("seg %s" % segname, file=f)
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for bitname in sorted(segdata["bits"]):
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print("bit %s" % bitname, file=f)
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for tagname, tagval in sorted(segdata["tags"].items()):
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print("tag %s %d" % (tagname, tagval), file=f)
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@ -0,0 +1,11 @@
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#!/bin/bash
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. ../../utils/genheader.sh
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vivado -mode batch -source ../generate.tcl
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for i in {0..9}; do
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../../../tools/bitread -F $XRAY_ROI_FRAMES -o design_$i.bits -zy design_$i.bit
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python3 ../generate.py $i
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done
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@ -0,0 +1,65 @@
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create_project -force -part $::env(XRAY_PART) design design
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read_verilog ../top.v
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synth_design -top top
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports di]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports do]
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create_pblock roi
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add_cells_to_pblock [get_pblocks roi] [get_cells roi]
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resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"
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set_property CFGBVS VCCO [current_design]
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
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set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF]
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place_design
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route_design
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write_checkpoint -force design.dcp
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########################################
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# Unmodified design with random LUTs
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proc write_txtdata {filename} {
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puts "Writing $filename."
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set fp [open $filename w]
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foreach cell [get_cells -hierarchical -filter {REF_NAME == FDRE}] {
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set loc [get_property LOC $cell]
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set bel [get_property BEL $cell]
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set init [get_property INIT $cell]
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set cinv [get_property IS_C_INVERTED $cell]
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set dinv [get_property IS_D_INVERTED $cell]
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set rinv [get_property IS_R_INVERTED $cell]
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puts $fp "$loc $bel $init $cinv $dinv $rinv"
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}
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close $fp
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}
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write_bitstream -force design_0.bit
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write_txtdata design_0.txt
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########################################
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# Create versions with random bit changes
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proc change_design_randomly {} {
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foreach cell [get_cells -hierarchical -filter {REF_NAME == FDRE}] {
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set_property INIT 1'b[expr int(rand()*2)] $cell
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# set_property IS_C_INVERTED 1'b[expr int(rand()*2)] $cell
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# set_property IS_D_INVERTED 1'b[expr int(rand()*2)] $cell
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# set_property IS_R_INVERTED 1'b[expr int(rand()*2)] $cell
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}
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}
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for {set i 1} {$i < 10} {incr i} {
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change_design_randomly
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write_bitstream -force design_$i.bit
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write_txtdata design_$i.txt
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}
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@ -0,0 +1,29 @@
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module top(input clk, di, output do);
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roi roi (
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.clk(clk),
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.din(di),
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.dout(do)
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);
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endmodule
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module roi(input clk, input din, output dout);
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localparam integer N = 500;
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wire [N:0] nets;
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assign nets[0] = din;
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assign dout = nets[N];
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genvar i;
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generate
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for (i = 0; i < N; i = i+1) begin:ffs
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FDRE ff (
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.C(clk),
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.D(nets[i]),
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.Q(nets[i+1]),
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.R(1'b0),
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.CE(1'b1)
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);
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end
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endgenerate
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endmodule
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