From 246e343ff17de87d3efb6dc01f81bb9ff5c9fb7e Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 18 Oct 2017 16:28:10 +0200 Subject: [PATCH] Add draft 011-ffconfig fuzzer Signed-off-by: Clifford Wolf Signed-off-by: Tim 'mithro' Ansell --- fuzzers/011-ffconfig/Makefile | 26 +++++++ fuzzers/011-ffconfig/generate.py | 122 ++++++++++++++++++++++++++++++ fuzzers/011-ffconfig/generate.sh | 11 +++ fuzzers/011-ffconfig/generate.tcl | 65 ++++++++++++++++ fuzzers/011-ffconfig/top.v | 29 +++++++ 5 files changed, 253 insertions(+) create mode 100644 fuzzers/011-ffconfig/Makefile create mode 100644 fuzzers/011-ffconfig/generate.py create mode 100644 fuzzers/011-ffconfig/generate.sh create mode 100644 fuzzers/011-ffconfig/generate.tcl create mode 100644 fuzzers/011-ffconfig/top.v diff --git a/fuzzers/011-ffconfig/Makefile b/fuzzers/011-ffconfig/Makefile new file mode 100644 index 00000000..7dff61f3 --- /dev/null +++ b/fuzzers/011-ffconfig/Makefile @@ -0,0 +1,26 @@ + +N := 1 +SPECIMENS := $(addprefix specimen_,$(shell seq -f '%03.0f' $(N))) +SPECIMENS_OK := $(addsuffix /OK,$(SPECIMENS)) + +database: database/clbll database/clblm + +pushdb: pushdb/clbll pushdb/clblm + +database/%: $(SPECIMENS_OK) + ../../tools/segmatch -o seg_$(notdir $@).segbits \ + $(addsuffix /segdata_$(notdir $@)_[0-9].txt,$(SPECIMENS)) + +pushdb/%: + bash ../../utils/mergedb.sh seg_$(notdir $@).segbits \ + ../../database/$(XRAY_DATABASE)/seg_$(notdir $@).segbits + +$(SPECIMENS_OK): + bash generate.sh $(subst /OK,,$@) + touch $@ + +clean: + rm -rf $(SPECIMENS) seg_clbll.segbits seg_clblm.segbits + +.PHONY: database pushdb clean + diff --git a/fuzzers/011-ffconfig/generate.py b/fuzzers/011-ffconfig/generate.py new file mode 100644 index 00000000..04700fa2 --- /dev/null +++ b/fuzzers/011-ffconfig/generate.py @@ -0,0 +1,122 @@ +#!/usr/bin/env python3 + +import os, sys, json, re + + +################################################# +# Loading Raw Source Data + +grid = None +bits = dict() +data = dict() + +print("Loading grid.") +with open("../../../database/%s/tilegrid.json" % os.getenv("XRAY_DATABASE"), "r") as f: + grid = json.load(f) + +print("Loading bits.") +with open("design_%s.bits" % sys.argv[1], "r") as f: + for line in f: + line = line.split("_") + bit_frame = int(line[1], 16) + bit_wordidx = int(line[2], 16) + bit_bitidx = int(line[3], 16) + base_frame = bit_frame & ~0x7f + + if base_frame not in bits: + bits[base_frame] = dict() + + if bit_wordidx not in bits[base_frame]: + bits[base_frame][bit_wordidx] = set() + + bits[base_frame][bit_wordidx].add((bit_frame, bit_wordidx, bit_bitidx)) + +print("Loading text data.") +with open("design_%s.txt" % sys.argv[1], "r") as f: + for line in f: + line = line.split() + site = line[0] + bel = line[1] + init = int(line[2][3]) + cinv = int(line[3][3]) + dinv = int(line[4][3]) + rinv = int(line[5][3]) + + if site not in data: + data[site] = dict() + + data[site]["%s.INIT" % bel] = init + data[site]["%s.CINV" % bel] = cinv + data[site]["%s.DINV" % bel] = dinv + data[site]["%s.RINV" % bel] = rinv + + +################################################# +# Group per Segment + +print("Compile segment data.") + +segments_by_type = dict() + +for tilename, tiledata in grid["tiles"].items(): + if "segment" not in tiledata: + continue + + segdata = grid["segments"][tiledata["segment"]] + + if segdata["type"] not in segments_by_type: + segments_by_type[segdata["type"]] = dict() + segments = segments_by_type[segdata["type"]] + + tile_type = tiledata["type"] + segname = "%s_%02x" % (segdata["baseaddr"][0][2:], segdata["baseaddr"][1]) + + if not segname in segments: + segments[segname] = { "bits": list(), "tags": dict() } + + for site in tiledata["sites"]: + if site not in data: + continue + + if re.match(r"SLICE_X[0-9]*[02468]Y", site): + sitekey = "SLICE_X0" + elif re.match(r"SLICE_X[0-9]*[13579]Y", site): + sitekey = "SLICE_X1" + else: + assert 0 + + for name, value in data[site].items(): + tag = "%s.%s.%s" % (re.sub("_[LR]$", "", tile_type), sitekey, name) + tag = tag.replace("SLICE_X0.SLICEM", "SLICEM_X0") + tag = tag.replace("SLICE_X1.SLICEM", "SLICEM_X1") + tag = tag.replace("SLICE_X0.SLICEL", "SLICEL_X0") + tag = tag.replace("SLICE_X1.SLICEL", "SLICEL_X1") + segments[segname]["tags"][tag] = value + + base_frame = int(segdata["baseaddr"][0][2:], 16) + for wordidx in range(segdata["baseaddr"][1], segdata["baseaddr"][1]+2): + if base_frame not in bits: + continue + if wordidx not in bits[base_frame]: + continue + for bit_frame, bit_wordidx, bit_bitidx in bits[base_frame][wordidx]: + segments[segname]["bits"].append("%02x_%02x_%02x" % (bit_frame - base_frame, bit_wordidx - segdata["baseaddr"][1], bit_bitidx)) + + segments[segname]["bits"].sort() + + +################################################# +# Print + +print("Write segment data.") + +for segtype in segments_by_type.keys(): + with open("segdata_%s_%s.txt" % (segtype, sys.argv[1]), "w") as f: + segments = segments_by_type[segtype] + for segname, segdata in sorted(segments.items()): + print("seg %s" % segname, file=f) + for bitname in sorted(segdata["bits"]): + print("bit %s" % bitname, file=f) + for tagname, tagval in sorted(segdata["tags"].items()): + print("tag %s %d" % (tagname, tagval), file=f) + diff --git a/fuzzers/011-ffconfig/generate.sh b/fuzzers/011-ffconfig/generate.sh new file mode 100644 index 00000000..ca8b6648 --- /dev/null +++ b/fuzzers/011-ffconfig/generate.sh @@ -0,0 +1,11 @@ +#!/bin/bash + +. ../../utils/genheader.sh + +vivado -mode batch -source ../generate.tcl + +for i in {0..9}; do + ../../../tools/bitread -F $XRAY_ROI_FRAMES -o design_$i.bits -zy design_$i.bit + python3 ../generate.py $i +done + diff --git a/fuzzers/011-ffconfig/generate.tcl b/fuzzers/011-ffconfig/generate.tcl new file mode 100644 index 00000000..72f2a821 --- /dev/null +++ b/fuzzers/011-ffconfig/generate.tcl @@ -0,0 +1,65 @@ +create_project -force -part $::env(XRAY_PART) design design + +read_verilog ../top.v +synth_design -top top + +set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] +set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports di] +set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports do] + +create_pblock roi +add_cells_to_pblock [get_pblocks roi] [get_cells roi] +resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)" + +set_property CFGBVS VCCO [current_design] +set_property CONFIG_VOLTAGE 3.3 [current_design] +set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] + +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] + +place_design +route_design + +write_checkpoint -force design.dcp + + +######################################## +# Unmodified design with random LUTs + +proc write_txtdata {filename} { + puts "Writing $filename." + set fp [open $filename w] + foreach cell [get_cells -hierarchical -filter {REF_NAME == FDRE}] { + set loc [get_property LOC $cell] + set bel [get_property BEL $cell] + set init [get_property INIT $cell] + set cinv [get_property IS_C_INVERTED $cell] + set dinv [get_property IS_D_INVERTED $cell] + set rinv [get_property IS_R_INVERTED $cell] + puts $fp "$loc $bel $init $cinv $dinv $rinv" + } + close $fp +} + +write_bitstream -force design_0.bit +write_txtdata design_0.txt + + +######################################## +# Create versions with random bit changes + +proc change_design_randomly {} { + foreach cell [get_cells -hierarchical -filter {REF_NAME == FDRE}] { + set_property INIT 1'b[expr int(rand()*2)] $cell + # set_property IS_C_INVERTED 1'b[expr int(rand()*2)] $cell + # set_property IS_D_INVERTED 1'b[expr int(rand()*2)] $cell + # set_property IS_R_INVERTED 1'b[expr int(rand()*2)] $cell + } +} + +for {set i 1} {$i < 10} {incr i} { + change_design_randomly + write_bitstream -force design_$i.bit + write_txtdata design_$i.txt +} + diff --git a/fuzzers/011-ffconfig/top.v b/fuzzers/011-ffconfig/top.v new file mode 100644 index 00000000..50986a05 --- /dev/null +++ b/fuzzers/011-ffconfig/top.v @@ -0,0 +1,29 @@ +module top(input clk, di, output do); + roi roi ( + .clk(clk), + .din(di), + .dout(do) + ); +endmodule + +module roi(input clk, input din, output dout); + localparam integer N = 500; + + wire [N:0] nets; + + assign nets[0] = din; + assign dout = nets[N]; + + genvar i; + generate + for (i = 0; i < N; i = i+1) begin:ffs + FDRE ff ( + .C(clk), + .D(nets[i]), + .Q(nets[i+1]), + .R(1'b0), + .CE(1'b1) + ); + end + endgenerate +endmodule