mirror of https://github.com/openXC7/prjxray.git
Add initial BUFG config bits.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
This commit is contained in:
Keith Rothman
parent
5bebeb6c0d
commit
2311f25149
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@ -0,0 +1,22 @@
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N ?= 50
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include ../fuzzer.mk
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database: build/segbits_clk_bufg.db
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build/segbits_clk_bufg.rdb: $(SPECIMENS_OK)
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${XRAY_SEGMATCH} -o build/segbits_clk_bufg.rdb $(addsuffix /segdata_clk_bufg_top_r.txt,$(SPECIMENS)) $(addsuffix /segdata_clk_bufg_bot_r.txt,$(SPECIMENS))
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build/segbits_clk_bufg.db: build/segbits_clk_bufg.rdb
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${XRAY_DBFIXUP} --db-root build --zero-db bits.dbf \
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--seg-fn-in build/segbits_clk_bufg.rdb \
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--seg-fn-out build/segbits_clk_bufg.db
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${XRAY_MASKMERGE} build/mask_clk_bufg.db $(addsuffix /segdata_clk_bufg_top_r.txt,$(SPECIMENS)) $(addsuffix /segdata_clk_bufg_bot_r.txt,$(SPECIMENS))
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pushdb: database
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${XRAY_MERGEDB} clk_bufg_bot_r build/segbits_clk_bufg.db
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${XRAY_MERGEDB} clk_bufg_top_r build/segbits_clk_bufg.db
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${XRAY_MERGEDB} mask_clk_bufg_bot_r build/mask_clk_bufg.db
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${XRAY_MERGEDB} mask_clk_bufg_top_r build/mask_clk_bufg.db
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.PHONY: database pushdb
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@ -0,0 +1,67 @@
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#!/usr/bin/env python3
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import json
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from prjxray.segmaker import Segmaker
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def main():
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segmk = Segmaker("design.bits")
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print("Loading tags")
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with open('params.json') as f:
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params = json.load(f)
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for row in params:
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base_name = 'BUFGCTRL_X{}Y{}'.format(row['x'], row['y'])
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segmk.add_site_tag(
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row['site'], '{}.IN_USE'.format(base_name), row['IN_USE'])
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if not row['IN_USE']:
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continue
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for param in (
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'INIT_OUT',
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'IS_IGNORE0_INVERTED',
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'IS_IGNORE1_INVERTED',
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):
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segmk.add_site_tag(
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row['site'], '{}.{}'.format(base_name, param), row[param])
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if row['connect0'] and row['connect1']:
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for param in (
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'PRESELECT_I0',
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):
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segmk.add_site_tag(
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row['site'], '{}.Z{}'.format(base_name, param), 1 ^ row[param])
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for param in (
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'PRESELECT_I1',
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):
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segmk.add_site_tag(
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row['site'], '{}.{}'.format(base_name, param), row[param])
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if row['connect0']:
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for param, tag in (
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('IS_CE0_INVERTED', 'ZINV_CE0'),
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('IS_S0_INVERTED', 'ZINV_S0')
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):
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segmk.add_site_tag(
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row['site'], '{}.{}'.format(base_name, tag), 1 ^ row[param])
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if row['connect1']:
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for param, tag in (
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('IS_CE1_INVERTED', 'ZINV_CE1'),
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('IS_S1_INVERTED', 'ZINV_S1')
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):
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segmk.add_site_tag(
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row['site'], '{}.{}'.format(base_name, tag), 1 ^ row[param])
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segmk.compile()
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segmk.write()
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if __name__ == '__main__':
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main()
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@ -0,0 +1,17 @@
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proc run {} {
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create_project -force -part $::env(XRAY_PART) design design
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read_verilog top.v
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synth_design -top top
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set_property CFGBVS VCCO [current_design]
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
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place_design
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route_design
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write_checkpoint -force design.dcp
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write_bitstream -force design.bit
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}
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run
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@ -0,0 +1,148 @@
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import json
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import os
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import re
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import random
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random.seed(int(os.getenv("SEED"), 16))
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from prjxray import util
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from prjxray import verilog
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from prjxray.db import Database
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XY_RE = re.compile('^BUFGCTRL_X([0-9]+)Y([0-9]+)$')
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def gen_sites():
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db = Database(util.get_db_root())
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grid = db.grid()
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db = Database(util.get_db_root())
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grid = db.grid()
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for tile_name in sorted(grid.tiles()):
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loc = grid.loc_of_tilename(tile_name)
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gridinfo = grid.gridinfo_at_loc(loc)
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sites = []
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xs = []
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ys = []
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for site, site_type in gridinfo.sites.items():
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if site_type == 'BUFGCTRL':
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m = re.match(XY_RE, site)
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assert m, site
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x = int(m.group(1))
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y = int(m.group(2))
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xs.append(x)
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ys.append(y)
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sites.append((site, x, y))
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if sites:
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yield tile_name, min(xs), min(ys), sorted(sites)
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def main():
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print('''
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module top();
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''')
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params_list = []
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for tile_name, x_min, y_min, sites in gen_sites():
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for site, x, y in sites:
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params = {}
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params['tile'] = tile_name
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params['site'] = site
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params['x'] = x - x_min
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params['y'] = y - y_min
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params['IN_USE'] = random.random() > .1
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if params['IN_USE']:
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params['INIT_OUT'] = random.randint(0, 1)
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params['IS_CE0_INVERTED'] = random.randint(0, 1)
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params['IS_CE1_INVERTED'] = random.randint(0, 1)
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params['IS_S0_INVERTED'] = random.randint(0, 1)
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params['IS_S1_INVERTED'] = random.randint(0, 1)
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params['IS_IGNORE0_INVERTED'] = random.randint(0, 1)
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params['IS_IGNORE1_INVERTED'] = random.randint(0, 1)
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params['PRESELECT_I0'] = 0
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params['PRESELECT_I1'] = 0
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params['connect0'] = random.randint(0, 1)
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if params['connect0']:
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params['connect1'] = random.randint(0, 1)
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else:
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params['connect1'] = 1
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if params['connect0'] and params['connect1']:
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params['PRESELECT_I0'] = random.randint(0, 1)
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if not params['PRESELECT_I0']:
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params['PRESELECT_I1'] = random.randint(0, 1)
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else:
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params['PRESELECT_I1'] = 0
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params['connections'] = """
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.CE0(ce0_{site}),
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.S0(s0_{site}),
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.CE1(ce1_{site}),
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.S1(s1_{site})
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""".format(site=site)
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elif params['connect0']:
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params['connections'] = """
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.CE0(ce0_{site}),
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.S0(s0_{site})
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""".format(site=site)
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elif params['connect1']:
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params['connections'] = """
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.CE1(ce1_{site}),
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.S1(s1_{site})
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""".format(site=site)
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print(
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'''
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wire ce0_{site};
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wire s0_{site};
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(* KEEP, DONT_TOUCH *)
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LUT6 l0_{site} (
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.O(ce0_{site})
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);
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(* KEEP, DONT_TOUCH *)
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LUT6 l1_{site} (
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.O(s0_{site})
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);
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wire ce1_{site};
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wire s1_{site};
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(* KEEP, DONT_TOUCH *)
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LUT6 l2_{site} (
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.O(ce1_{site})
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);
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(* KEEP, DONT_TOUCH *)
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LUT6 l3_{site} (
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.O(s1_{site})
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);
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(* KEEP, DONT_TOUCH, LOC = "{site}" *)
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BUFGCTRL #(
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.INIT_OUT({INIT_OUT}),
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.PRESELECT_I0({PRESELECT_I0}),
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.PRESELECT_I1({PRESELECT_I1}),
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.IS_CE0_INVERTED({IS_CE0_INVERTED}),
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.IS_CE1_INVERTED({IS_CE1_INVERTED}),
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.IS_S0_INVERTED({IS_S0_INVERTED}),
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.IS_S1_INVERTED({IS_S1_INVERTED}),
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.IS_IGNORE0_INVERTED({IS_IGNORE0_INVERTED}),
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.IS_IGNORE1_INVERTED({IS_IGNORE1_INVERTED})
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) buf_{site} (
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{connections}
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);
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'''.format(**params))
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params_list.append(params)
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print("endmodule")
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with open('params.json', 'w') as f:
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json.dump(params_list, f, indent=2)
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if __name__ == '__main__':
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main()
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@ -72,6 +72,8 @@ $(eval $(call fuzzer,028-fifo-config,005-tilegrid))
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$(eval $(call fuzzer,029-bram-fifo-config,005-tilegrid))
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$(eval $(call fuzzer,040-clk-hrow-config,005-tilegrid))
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$(eval $(call fuzzer,041-clk-hrow-pips,005-tilegrid))
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$(eval $(call fuzzer,042-clk-bufg-config,005-tilegrid))
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$(eval $(call fuzzer,043-clk-rebuf-pips,005-tilegrid))
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$(eval $(call fuzzer,050-pip-seed,005-tilegrid))
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$(eval $(call fuzzer,051-pip-imuxlout-bypalts,050-pip-seed))
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$(eval $(call fuzzer,052-pip-clkin,050-pip-seed))
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@ -78,6 +78,11 @@ case "$1" in
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clk_hrow_top_r)
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sed < "$2" > "$tmp1" -e 's/^CLK_HROW\./CLK_HROW_TOP_R./' ;;
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clk_bufg_bot_r)
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sed < "$2" > "$tmp1" -e 's/^CLK_BUFG\./CLK_BUFG_BOT_R./' ;;
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clk_bufg_top_r)
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sed < "$2" > "$tmp1" -e 's/^CLK_BUFG\./CLK_BUFG_TOP_R./' ;;
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liob33)
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cp "$2" "$tmp1" ;;
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