Merge pull request #96 from unixb0y/master

Fixed Bullet Point Lists in README.md files

fuzzers/005-tilegrid/README.md

@@ -23,10 +23,11 @@ If you don't know where your ROI is, just set to to include all values (0x000000
 
 ### XRAY_ROI_GRID_*  
 Optionally these as a small performance optimization:  
--XRAY_ROI_GRID_X1  
--XRAY_ROI_GRID_X2  
--XRAY_ROI_GRID_Y1  
--XRAY_ROI_GRID_Y2  
+- XRAY_ROI_GRID_X1  
+- XRAY_ROI_GRID_X2  
+- XRAY_ROI_GRID_Y1  
+- XRAY_ROI_GRID_Y2  
+
 Which should, if unused, be set to -1, with this caveat:  
 WARNING: CLB test generates this based on CLBs but implicitly includes INT  
 Therefore, if you don't set an explicit XRAY_ROI_GRID_* it may fail  

fuzzers/011-ffconfig/README.md

@@ -1,9 +1,9 @@
 # FFConfig Fuzzer
 
 Documents the following:  
--FF clock inversion  
--FF primitive mapping  
--FF initialization value  
+- FF clock inversion  
+- FF primitive mapping  
+- FF initialization value  
 
 Clock inversion is per slice (as BEL CLKINV)  
 Vivado GUI is misleading as it often shows it per FF, which is not actually true  

fuzzers/018-clbram/README.md

@@ -2,10 +2,10 @@
 
 ## Purpose  
 Solves SLICEM specific bits:  
--Shift register LUT (SRL)  
--Memory size  
--RAM vs LUT  
--Related muxes  
+- Shift register LUT (SRL)  
+- Memory size  
+- RAM vs LUT  
+- Related muxes  
 
 ## Algorithm  
   

minitests/clb_muxf8/README.md

@@ -5,9 +5,9 @@ This tests an issue related to Vivado 2017.2 vs 2017.3 changing MUXF8 behavior
 The general issue is the LUT6_2 cannot be used with a MUXF8 (even if O5 is unused)  
 
 ## General notes:
--2017.2: LUT6_2 works with MUXF8  
--2017.3: LUT6_2 does not work with MUXF8  
--All: LUT6 works with MUXF8  
--All: MUXF8 (even with MUXF7) can be instantiated unconnected  
--2017.4 seems to behave like 2017.3  
+- 2017.2: LUT6_2 works with MUXF8  
+- 2017.3: LUT6_2 does not work with MUXF8  
+- All: LUT6 works with MUXF8  
+- All: MUXF8 (even with MUXF7) can be instantiated unconnected  
+- 2017.4 seems to behave like 2017.3  
 

minitests/roi_harness/README.md

@@ -4,10 +4,10 @@
 Creates an ROI with clk, inputs, and outputs to use as a partial reconfiguration test harness  
 
 Basic idea:  
--LOC LUTs in the ROI to terminate input and output routing  
--Let Vivado LOC the rest of the logic  
--Manually route signals in and out of the ROI enough to avoid routing loops into the ROI  
--Let Vivado finish the rest of the routes  
+- LOC LUTs in the ROI to terminate input and output routing  
+- Let Vivado LOC the rest of the logic  
+- Manually route signals in and out of the ROI enough to avoid routing loops into the ROI  
+- Let Vivado finish the rest of the routes  
 
 There is no logic outside of the ROI in order to keep IOB to ROI delays short  
 Its expected the end user will rip out everything inside the ROI