From 7e47ae4a51cf2e676f41465027c8e06ea90b306b Mon Sep 17 00:00:00 2001 From: Davide Date: Sun, 18 Feb 2018 03:02:33 +0100 Subject: [PATCH] Fixed Bullet Point Lists in README.md files Signed-off-by: Davide --- fuzzers/005-tilegrid/README.md | 9 +++++---- fuzzers/011-ffconfig/README.md | 6 +++--- fuzzers/018-clbram/README.md | 8 ++++---- minitests/clb_muxf8/README.md | 10 +++++----- minitests/roi_harness/README.md | 8 ++++---- 5 files changed, 21 insertions(+), 20 deletions(-) diff --git a/fuzzers/005-tilegrid/README.md b/fuzzers/005-tilegrid/README.md index 9aa806bc..53fa9c5d 100644 --- a/fuzzers/005-tilegrid/README.md +++ b/fuzzers/005-tilegrid/README.md @@ -23,10 +23,11 @@ If you don't know where your ROI is, just set to to include all values (0x000000 ### XRAY_ROI_GRID_* Optionally these as a small performance optimization: --XRAY_ROI_GRID_X1 --XRAY_ROI_GRID_X2 --XRAY_ROI_GRID_Y1 --XRAY_ROI_GRID_Y2 +- XRAY_ROI_GRID_X1 +- XRAY_ROI_GRID_X2 +- XRAY_ROI_GRID_Y1 +- XRAY_ROI_GRID_Y2 + Which should, if unused, be set to -1, with this caveat: WARNING: CLB test generates this based on CLBs but implicitly includes INT Therefore, if you don't set an explicit XRAY_ROI_GRID_* it may fail diff --git a/fuzzers/011-ffconfig/README.md b/fuzzers/011-ffconfig/README.md index f1f53b41..76874055 100644 --- a/fuzzers/011-ffconfig/README.md +++ b/fuzzers/011-ffconfig/README.md @@ -1,9 +1,9 @@ # FFConfig Fuzzer Documents the following: --FF clock inversion --FF primitive mapping --FF initialization value +- FF clock inversion +- FF primitive mapping +- FF initialization value Clock inversion is per slice (as BEL CLKINV) Vivado GUI is misleading as it often shows it per FF, which is not actually true diff --git a/fuzzers/018-clbram/README.md b/fuzzers/018-clbram/README.md index 50d7e839..5bfd8e73 100644 --- a/fuzzers/018-clbram/README.md +++ b/fuzzers/018-clbram/README.md @@ -2,10 +2,10 @@ ## Purpose Solves SLICEM specific bits: --Shift register LUT (SRL) --Memory size --RAM vs LUT --Related muxes +- Shift register LUT (SRL) +- Memory size +- RAM vs LUT +- Related muxes ## Algorithm diff --git a/minitests/clb_muxf8/README.md b/minitests/clb_muxf8/README.md index 48476953..bf3dd25a 100644 --- a/minitests/clb_muxf8/README.md +++ b/minitests/clb_muxf8/README.md @@ -5,9 +5,9 @@ This tests an issue related to Vivado 2017.2 vs 2017.3 changing MUXF8 behavior The general issue is the LUT6_2 cannot be used with a MUXF8 (even if O5 is unused) ## General notes: --2017.2: LUT6_2 works with MUXF8 --2017.3: LUT6_2 does not work with MUXF8 --All: LUT6 works with MUXF8 --All: MUXF8 (even with MUXF7) can be instantiated unconnected --2017.4 seems to behave like 2017.3 +- 2017.2: LUT6_2 works with MUXF8 +- 2017.3: LUT6_2 does not work with MUXF8 +- All: LUT6 works with MUXF8 +- All: MUXF8 (even with MUXF7) can be instantiated unconnected +- 2017.4 seems to behave like 2017.3 diff --git a/minitests/roi_harness/README.md b/minitests/roi_harness/README.md index efdf4d2e..2dfde7ae 100644 --- a/minitests/roi_harness/README.md +++ b/minitests/roi_harness/README.md @@ -4,10 +4,10 @@ Creates an ROI with clk, inputs, and outputs to use as a partial reconfiguration test harness Basic idea: --LOC LUTs in the ROI to terminate input and output routing --Let Vivado LOC the rest of the logic --Manually route signals in and out of the ROI enough to avoid routing loops into the ROI --Let Vivado finish the rest of the routes +- LOC LUTs in the ROI to terminate input and output routing +- Let Vivado LOC the rest of the logic +- Manually route signals in and out of the ROI enough to avoid routing loops into the ROI +- Let Vivado finish the rest of the routes There is no logic outside of the ROI in order to keep IOB to ROI delays short Its expected the end user will rip out everything inside the ROI