mirror of https://github.com/openXC7/prjxray.git
017-clbprecyinit fuzzer basic version
Signed-off-by: John McMaster <JohnDMcMaster@gmail.com> Signed-off-by: Tim 'mithro' Ansell <mithro@mithis.com>
This commit is contained in:
John McMaster
Tim 'mithro' Ansell
parent
6abb5547b8
commit
151b44a902
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/specimen_*/
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/*.segbits
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/vivado.log
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/vivado.jou
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@ -0,0 +1,23 @@
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N := 1
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SPECIMENS := $(addprefix specimen_,$(shell seq -f '%03.0f' $(N)))
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SPECIMENS_OK := $(addsuffix /OK,$(SPECIMENS))
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database: $(SPECIMENS_OK)
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${XRAY_SEGMATCH} -o seg_clblx.segbits $(addsuffix /segdata_clbl[lm]_[lr].txt,$(SPECIMENS))
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pushdb:
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${XRAY_MERGEDB} clbll_l seg_clblx.segbits
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${XRAY_MERGEDB} clbll_r seg_clblx.segbits
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${XRAY_MERGEDB} clblm_l seg_clblx.segbits
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${XRAY_MERGEDB} clblm_r seg_clblx.segbits
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${$XRAY_DBFIXUP}
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$(SPECIMENS_OK):
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bash generate.sh $(subst /OK,,$@)
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touch $@
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clean:
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rm -rf specimen_[0-9][0-9][0-9]/ seg_clblx.segbits vivado*.log vivado_*.str vivado*.jou design *.bits *.dcp *.bit top.v
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.PHONY: database pushdb clean
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Purpose:
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Document PRECYINIT mux
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Algorithm:
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Outcome:
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CLB.SLICE_X0.PRECYINIT.0 <0 candidates>
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CLB.SLICE_X0.PRECYINIT.1 00_12
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CLB.SLICE_X0.PRECYINIT.AX 30_14
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CLB.SLICE_X0.PRECYINIT.CIN 30_13
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CLB.SLICE_X1.PRECYINIT.0 <0 candidates>
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CLB.SLICE_X1.PRECYINIT.1 01_11
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CLB.SLICE_X1.PRECYINIT.AX 31_13
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CLB.SLICE_X1.PRECYINIT.CIN 31_12
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#!/usr/bin/env python3
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import sys, os, re
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sys.path.append("../../../utils/")
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from segmaker import segmaker
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segmk = segmaker("design.bits")
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print("Loading tags")
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f = open('params.csv', 'r')
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f.readline()
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for l in f:
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module,loc,loc2 = l.split(',')
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# clb_PRECYINIT_AX => AX
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src = module.replace('clb_PRECYINIT_', '')
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print(src, src == '0')
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#if src == 'CIN':
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# continue
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'''
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PRECYINIT
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00_12 30_14 30_13
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1 0 1 0
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AX 1 0 0
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CIN 0 0 1
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0 0 0 0
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'''
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srcs = ('0', '1', 'AX', 'CIN')
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for asrc in srcs:
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segmk.addtag(loc, "PRECYINIT.%s" % asrc, int(src == asrc))
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segmk.compile()
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segmk.write()
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#!/bin/bash
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set -ex
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. ../../utils/genheader.sh
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#echo '`define SEED 32'"'h$(echo $1 | md5sum | cut -c1-8)" > setseed.vh
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python3 ../top.py >top.v
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vivado -mode batch -source ../generate.tcl
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test -z "$(fgrep CRITICAL vivado.log)"
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for x in design*.bit; do
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../../../build/tools/bitread -F $XRAY_ROI_FRAMES -o ${x}s -z -y $x
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done
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python3 ../generate.py
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create_project -force -part $::env(XRAY_PART) design design
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read_verilog top.v
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synth_design -top top
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do]
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create_pblock roi
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set_property EXCLUDE_PLACEMENT 1 [get_pblocks roi]
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add_cells_to_pblock [get_pblocks roi] [get_cells roi]
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resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"
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set_property CFGBVS VCCO [current_design]
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
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set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF]
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place_design
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route_design
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write_checkpoint -force design.dcp
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write_bitstream -force design.bit
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@ -0,0 +1,137 @@
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import random
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random.seed(0)
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import os
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import re
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def slice_xy():
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'''Return (X1, X2), (Y1, Y2) from XRAY_ROI, exclusive end (for xrange)'''
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# SLICE_X12Y100:SLICE_X27Y149
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# Note XRAY_ROI_GRID_* is something else
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m = re.match(r'SLICE_X(.*)Y(.*):SLICE_X(.*)Y(.*)', os.getenv('XRAY_ROI'))
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ms = [int(m.group(i + 1)) for i in range(4)]
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return ((ms[0], ms[2] + 1), (ms[1], ms[3] + 1))
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CLBN = 400
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SLICEX, SLICEY = slice_xy()
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# 800
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SLICEN = (SLICEY[1] - SLICEY[0]) * (SLICEX[1] - SLICEX[0])
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print('//SLICEX: %s' % str(SLICEX))
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print('//SLICEY: %s' % str(SLICEY))
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print('//SLICEN: %s' % str(SLICEN))
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print('//Requested CLBs: %s' % str(CLBN))
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# Rearranged to sweep Y so that carry logic is easy to allocate
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# XXX: careful...if odd number of Y in ROI will break carry
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def gen_slices():
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for slicex in range(*SLICEX):
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for slicey in range(*SLICEY):
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# caller may reject position if needs more room
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yield ("SLICE_X%dY%d" % (slicex, slicey), (slicex, slicey))
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DIN_N = CLBN * 8
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DOUT_N = CLBN * 8
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print('''
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module top(input clk, stb, di, output do);
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localparam integer DIN_N = %d;
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localparam integer DOUT_N = %d;
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reg [DIN_N-1:0] din;
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wire [DOUT_N-1:0] dout;
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reg [DIN_N-1:0] din_shr;
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reg [DOUT_N-1:0] dout_shr;
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always @(posedge clk) begin
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din_shr <= {din_shr, di};
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dout_shr <= {dout_shr, din_shr[DIN_N-1]};
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if (stb) begin
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din <= din_shr;
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dout_shr <= dout;
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end
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end
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assign do = dout_shr[DOUT_N-1];
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roi roi (
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.clk(clk),
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.din(din),
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.dout(dout)
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);
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endmodule
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''' % (DIN_N, DOUT_N))
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f = open('params.csv', 'w')
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f.write('module,loc,loc2\n')
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slices = gen_slices()
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print('module roi(input clk, input [%d:0] din, output [%d:0] dout);' % (DIN_N - 1, DOUT_N - 1))
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for i in range(CLBN):
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# Don't have an O6 example
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modules = ['clb_PRECYINIT_' + x for x in ['0', '1', 'AX', 'CIN']]
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loc, loc_pos = next(slices)
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while True:
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module = random.choice(modules)
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if module == 'clb_PRECYINIT_CIN':
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# Need at least extra Y for CIN extra CLB
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if loc_pos[1] >= SLICEY[1] - 1:
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continue
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loc_co = loc
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loc_ci, _pos_ci = next(slices)
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params = '.LOC_CO("%s"), .LOC_CI("%s")' % (loc_co, loc_ci)
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# Don't really care about co, but add for completeness
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paramsc = loc_ci + ',' + loc_co
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else:
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params = '.LOC("%s")' % loc
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paramsc = loc + ',' + ''
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break
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print(' %s' % module)
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print(' #(%s)' % (params))
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print(' clb_%d (.clk(clk), .din(din[ %d +: 8]), .dout(dout[ %d +: 8]));' % (i, 8 * i, 8 * i))
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f.write('%s,%s\n' % (module, paramsc))
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f.close()
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print('''endmodule
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// ---------------------------------------------------------------------
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''')
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print('''
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module clb_PRECYINIT_0 (input clk, input [7:0] din, output [7:0] dout);
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parameter LOC="SLICE_FIXME";
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(* LOC=LOC, KEEP, DONT_TOUCH *)
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CARRY4 carry4(.O(), .CO(), .DI(din[3:0]), .S(din[7:4]), .CYINIT(1'b0), .CI());
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endmodule
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module clb_PRECYINIT_1 (input clk, input [7:0] din, output [7:0] dout);
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parameter LOC="SLICE_FIXME";
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(* LOC=LOC, KEEP, DONT_TOUCH *)
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CARRY4 carry4(.O(), .CO(), .DI(din[3:0]), .S(din[7:4]), .CYINIT(1'b1), .CI());
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endmodule
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module clb_PRECYINIT_AX (input clk, input [7:0] din, output [7:0] dout);
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parameter LOC="SLICE_FIXME";
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(* LOC=LOC, KEEP, DONT_TOUCH *)
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CARRY4 carry4(.O(), .CO(), .DI(din[3:0]), .S(din[7:4]), .CYINIT(din[0]), .CI());
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endmodule
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module clb_PRECYINIT_CIN (input clk, input [7:0] din, output [7:0] dout);
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parameter LOC_CO="SLICE_FIXME";
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parameter LOC_CI="SLICE_FIXME";
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wire [3:0] co;
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//Gets CI
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(* LOC=LOC_CI, KEEP, DONT_TOUCH *)
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CARRY4 carry4_co(.O(), .CO(), .DI(din[3:0]), .S(din[7:4]), .CYINIT(co[3]), .CI());
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//Sends CO
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(* LOC=LOC_CO, KEEP, DONT_TOUCH *)
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CARRY4 carry4_ci(.O(), .CO(co), .DI(din[3:0]), .S(din[7:4]), .CYINIT(1'b0), .CI());
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endmodule
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''')
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