From 151b44a902e1556362e94ffab43e2ff5ea8f7dd5 Mon Sep 17 00:00:00 2001 From: John McMaster Date: Fri, 8 Dec 2017 15:55:37 -0800 Subject: [PATCH] 017-clbprecyinit fuzzer basic version Signed-off-by: John McMaster Signed-off-by: Tim 'mithro' Ansell --- fuzzers/017-clbprecyinit/.gitignore | 4 + fuzzers/017-clbprecyinit/Makefile | 23 +++++ fuzzers/017-clbprecyinit/README.txt | 16 +++ fuzzers/017-clbprecyinit/generate.py | 35 +++++++ fuzzers/017-clbprecyinit/generate.sh | 18 ++++ fuzzers/017-clbprecyinit/generate.tcl | 26 +++++ fuzzers/017-clbprecyinit/top.py | 137 ++++++++++++++++++++++++++ 7 files changed, 259 insertions(+) create mode 100644 fuzzers/017-clbprecyinit/.gitignore create mode 100644 fuzzers/017-clbprecyinit/Makefile create mode 100644 fuzzers/017-clbprecyinit/README.txt create mode 100644 fuzzers/017-clbprecyinit/generate.py create mode 100644 fuzzers/017-clbprecyinit/generate.sh create mode 100644 fuzzers/017-clbprecyinit/generate.tcl create mode 100644 fuzzers/017-clbprecyinit/top.py diff --git a/fuzzers/017-clbprecyinit/.gitignore b/fuzzers/017-clbprecyinit/.gitignore new file mode 100644 index 00000000..93b5bef8 --- /dev/null +++ b/fuzzers/017-clbprecyinit/.gitignore @@ -0,0 +1,4 @@ +/specimen_*/ +/*.segbits +/vivado.log +/vivado.jou diff --git a/fuzzers/017-clbprecyinit/Makefile b/fuzzers/017-clbprecyinit/Makefile new file mode 100644 index 00000000..14918675 --- /dev/null +++ b/fuzzers/017-clbprecyinit/Makefile @@ -0,0 +1,23 @@ +N := 1 +SPECIMENS := $(addprefix specimen_,$(shell seq -f '%03.0f' $(N))) +SPECIMENS_OK := $(addsuffix /OK,$(SPECIMENS)) + +database: $(SPECIMENS_OK) + ${XRAY_SEGMATCH} -o seg_clblx.segbits $(addsuffix /segdata_clbl[lm]_[lr].txt,$(SPECIMENS)) + +pushdb: + ${XRAY_MERGEDB} clbll_l seg_clblx.segbits + ${XRAY_MERGEDB} clbll_r seg_clblx.segbits + ${XRAY_MERGEDB} clblm_l seg_clblx.segbits + ${XRAY_MERGEDB} clblm_r seg_clblx.segbits + ${$XRAY_DBFIXUP} + +$(SPECIMENS_OK): + bash generate.sh $(subst /OK,,$@) + touch $@ + +clean: + rm -rf specimen_[0-9][0-9][0-9]/ seg_clblx.segbits vivado*.log vivado_*.str vivado*.jou design *.bits *.dcp *.bit top.v + +.PHONY: database pushdb clean + diff --git a/fuzzers/017-clbprecyinit/README.txt b/fuzzers/017-clbprecyinit/README.txt new file mode 100644 index 00000000..8c2c5a24 --- /dev/null +++ b/fuzzers/017-clbprecyinit/README.txt @@ -0,0 +1,16 @@ +Purpose: +Document PRECYINIT mux + +Algorithm: + +Outcome: + +CLB.SLICE_X0.PRECYINIT.0 <0 candidates> +CLB.SLICE_X0.PRECYINIT.1 00_12 +CLB.SLICE_X0.PRECYINIT.AX 30_14 +CLB.SLICE_X0.PRECYINIT.CIN 30_13 +CLB.SLICE_X1.PRECYINIT.0 <0 candidates> +CLB.SLICE_X1.PRECYINIT.1 01_11 +CLB.SLICE_X1.PRECYINIT.AX 31_13 +CLB.SLICE_X1.PRECYINIT.CIN 31_12 + diff --git a/fuzzers/017-clbprecyinit/generate.py b/fuzzers/017-clbprecyinit/generate.py new file mode 100644 index 00000000..55d9144f --- /dev/null +++ b/fuzzers/017-clbprecyinit/generate.py @@ -0,0 +1,35 @@ +#!/usr/bin/env python3 + +import sys, os, re + +sys.path.append("../../../utils/") +from segmaker import segmaker + +segmk = segmaker("design.bits") + +print("Loading tags") +f = open('params.csv', 'r') +f.readline() +for l in f: + module,loc,loc2 = l.split(',') + # clb_PRECYINIT_AX => AX + src = module.replace('clb_PRECYINIT_', '') + print(src, src == '0') + #if src == 'CIN': + # continue + + ''' + PRECYINIT + 00_12 30_14 30_13 + 1 0 1 0 + AX 1 0 0 + CIN 0 0 1 + 0 0 0 0 + ''' + srcs = ('0', '1', 'AX', 'CIN') + for asrc in srcs: + segmk.addtag(loc, "PRECYINIT.%s" % asrc, int(src == asrc)) + +segmk.compile() +segmk.write() + diff --git a/fuzzers/017-clbprecyinit/generate.sh b/fuzzers/017-clbprecyinit/generate.sh new file mode 100644 index 00000000..35c20d37 --- /dev/null +++ b/fuzzers/017-clbprecyinit/generate.sh @@ -0,0 +1,18 @@ +#!/bin/bash + +set -ex + +. ../../utils/genheader.sh + +#echo '`define SEED 32'"'h$(echo $1 | md5sum | cut -c1-8)" > setseed.vh + +python3 ../top.py >top.v +vivado -mode batch -source ../generate.tcl +test -z "$(fgrep CRITICAL vivado.log)" + +for x in design*.bit; do + ../../../build/tools/bitread -F $XRAY_ROI_FRAMES -o ${x}s -z -y $x +done + +python3 ../generate.py + diff --git a/fuzzers/017-clbprecyinit/generate.tcl b/fuzzers/017-clbprecyinit/generate.tcl new file mode 100644 index 00000000..86162f92 --- /dev/null +++ b/fuzzers/017-clbprecyinit/generate.tcl @@ -0,0 +1,26 @@ +create_project -force -part $::env(XRAY_PART) design design +read_verilog top.v +synth_design -top top + +set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] +set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] +set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] +set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] + +create_pblock roi +set_property EXCLUDE_PLACEMENT 1 [get_pblocks roi] +add_cells_to_pblock [get_pblocks roi] [get_cells roi] +resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)" + +set_property CFGBVS VCCO [current_design] +set_property CONFIG_VOLTAGE 3.3 [current_design] +set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] + +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] + +place_design +route_design + +write_checkpoint -force design.dcp +write_bitstream -force design.bit + diff --git a/fuzzers/017-clbprecyinit/top.py b/fuzzers/017-clbprecyinit/top.py new file mode 100644 index 00000000..0bef994c --- /dev/null +++ b/fuzzers/017-clbprecyinit/top.py @@ -0,0 +1,137 @@ +import random +random.seed(0) +import os +import re + +def slice_xy(): + '''Return (X1, X2), (Y1, Y2) from XRAY_ROI, exclusive end (for xrange)''' + # SLICE_X12Y100:SLICE_X27Y149 + # Note XRAY_ROI_GRID_* is something else + m = re.match(r'SLICE_X(.*)Y(.*):SLICE_X(.*)Y(.*)', os.getenv('XRAY_ROI')) + ms = [int(m.group(i + 1)) for i in range(4)] + return ((ms[0], ms[2] + 1), (ms[1], ms[3] + 1)) + +CLBN = 400 +SLICEX, SLICEY = slice_xy() +# 800 +SLICEN = (SLICEY[1] - SLICEY[0]) * (SLICEX[1] - SLICEX[0]) +print('//SLICEX: %s' % str(SLICEX)) +print('//SLICEY: %s' % str(SLICEY)) +print('//SLICEN: %s' % str(SLICEN)) +print('//Requested CLBs: %s' % str(CLBN)) + +# Rearranged to sweep Y so that carry logic is easy to allocate +# XXX: careful...if odd number of Y in ROI will break carry +def gen_slices(): + for slicex in range(*SLICEX): + for slicey in range(*SLICEY): + # caller may reject position if needs more room + yield ("SLICE_X%dY%d" % (slicex, slicey), (slicex, slicey)) + +DIN_N = CLBN * 8 +DOUT_N = CLBN * 8 + +print(''' +module top(input clk, stb, di, output do); + localparam integer DIN_N = %d; + localparam integer DOUT_N = %d; + + reg [DIN_N-1:0] din; + wire [DOUT_N-1:0] dout; + + reg [DIN_N-1:0] din_shr; + reg [DOUT_N-1:0] dout_shr; + + always @(posedge clk) begin + din_shr <= {din_shr, di}; + dout_shr <= {dout_shr, din_shr[DIN_N-1]}; + if (stb) begin + din <= din_shr; + dout_shr <= dout; + end + end + + assign do = dout_shr[DOUT_N-1]; + + roi roi ( + .clk(clk), + .din(din), + .dout(dout) + ); +endmodule +''' % (DIN_N, DOUT_N)) + +f = open('params.csv', 'w') +f.write('module,loc,loc2\n') +slices = gen_slices() +print('module roi(input clk, input [%d:0] din, output [%d:0] dout);' % (DIN_N - 1, DOUT_N - 1)) +for i in range(CLBN): + # Don't have an O6 example + modules = ['clb_PRECYINIT_' + x for x in ['0', '1', 'AX', 'CIN']] + loc, loc_pos = next(slices) + while True: + module = random.choice(modules) + + if module == 'clb_PRECYINIT_CIN': + # Need at least extra Y for CIN extra CLB + if loc_pos[1] >= SLICEY[1] - 1: + continue + loc_co = loc + loc_ci, _pos_ci = next(slices) + params = '.LOC_CO("%s"), .LOC_CI("%s")' % (loc_co, loc_ci) + # Don't really care about co, but add for completeness + paramsc = loc_ci + ',' + loc_co + else: + params = '.LOC("%s")' % loc + paramsc = loc + ',' + '' + break + + print(' %s' % module) + print(' #(%s)' % (params)) + print(' clb_%d (.clk(clk), .din(din[ %d +: 8]), .dout(dout[ %d +: 8]));' % (i, 8 * i, 8 * i)) + + f.write('%s,%s\n' % (module, paramsc)) +f.close() +print('''endmodule + +// --------------------------------------------------------------------- + +''') + +print(''' +module clb_PRECYINIT_0 (input clk, input [7:0] din, output [7:0] dout); + parameter LOC="SLICE_FIXME"; + + (* LOC=LOC, KEEP, DONT_TOUCH *) + CARRY4 carry4(.O(), .CO(), .DI(din[3:0]), .S(din[7:4]), .CYINIT(1'b0), .CI()); +endmodule + +module clb_PRECYINIT_1 (input clk, input [7:0] din, output [7:0] dout); + parameter LOC="SLICE_FIXME"; + + (* LOC=LOC, KEEP, DONT_TOUCH *) + CARRY4 carry4(.O(), .CO(), .DI(din[3:0]), .S(din[7:4]), .CYINIT(1'b1), .CI()); +endmodule + +module clb_PRECYINIT_AX (input clk, input [7:0] din, output [7:0] dout); + parameter LOC="SLICE_FIXME"; + + (* LOC=LOC, KEEP, DONT_TOUCH *) + CARRY4 carry4(.O(), .CO(), .DI(din[3:0]), .S(din[7:4]), .CYINIT(din[0]), .CI()); +endmodule + +module clb_PRECYINIT_CIN (input clk, input [7:0] din, output [7:0] dout); + parameter LOC_CO="SLICE_FIXME"; + parameter LOC_CI="SLICE_FIXME"; + + wire [3:0] co; + + //Gets CI + (* LOC=LOC_CI, KEEP, DONT_TOUCH *) + CARRY4 carry4_co(.O(), .CO(), .DI(din[3:0]), .S(din[7:4]), .CYINIT(co[3]), .CI()); + //Sends CO + (* LOC=LOC_CO, KEEP, DONT_TOUCH *) + CARRY4 carry4_ci(.O(), .CO(co), .DI(din[3:0]), .S(din[7:4]), .CYINIT(1'b0), .CI()); +endmodule +''') +