luke
/
prjxray
mirror of https://github.com/openXC7/prjxray.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Fixed bug with diff pair loc-ing. 

Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
This commit is contained in:
Maciej Kurc 2019-12-02 10:16:21 +01:00
parent c396b0f9cc
commit 0fb79b8753
4 changed files with 85 additions and 16 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
minitests/iostandard/dump_iobs.tcl
View File

@ -11,11 +11,12 @@ proc dump_iobs {file_name} {
set pin [get_package_pins -of_objects $site] set pin [get_package_pins -of_objects $site]
set bank [get_property BANK $pin] set bank [get_property BANK $pin]
set pkg_pin [get_property NAME $pin]
set is_clock [get_property IS_CLK_CAPABLE $pin] set is_clock [get_property IS_CLK_CAPABLE $pin]
set is_global_clock [get_property IS_GLOBAL_CLK $pin] set is_global_clock [get_property IS_GLOBAL_CLK $pin]
set is_vref [get_property IS_VREF $pin] set is_vref [get_property IS_VREF $pin]
puts $fp "$tile,$site,$site_type,$clock_region,$bank,$is_bonded,$is_clock,$is_global_clock,$is_vref" puts $fp "$tile,$site,$site_type,$clock_region,$bank,$pkg_pin,$is_bonded,$is_clock,$is_global_clock,$is_vref"
} }
} }

1
minitests/iostandard/features/Makefile
View File

@ -14,6 +14,7 @@ all: analysis
clean: clean:
@rm -rf design_*.v @rm -rf design_*.v
@rm -rf design_*.tcl
@rm -rf design_*.json @rm -rf design_*.json
@rm -rf design_*.csv @rm -rf design_*.csv
@rm -rf design_*.fasm @rm -rf design_*.fasm

94
minitests/iostandard/features/generate.py
View File

@ -23,7 +23,7 @@ def load_iob_sites(file_name):
for line in fp: for line in fp:
fields = line.split(",") fields = line.split(",")
if len(fields) != 9: if len(fields) != 10:
continue continue
iob_sites[fields[3]].append( iob_sites[fields[3]].append(
@ -32,10 +32,11 @@ def load_iob_sites(file_name):
"name": fields[1], "name": fields[1],
"type": fields[2], "type": fields[2],
"bank": fields[4], "bank": fields[4],
"is_bonded": bool(int(fields[5])), "pkg_pin": fields[5],
"is_clock": bool(int(fields[6])), "is_bonded": bool(int(fields[6])),
"is_global_clock": bool(int(fields[7])), "is_clock": bool(int(fields[7])),
"is_vref": bool(int(fields[8])), "is_global_clock": bool(int(fields[8])),
"is_vref": bool(int(fields[9])),
}) })
return iob_sites return iob_sites
@ -124,6 +125,23 @@ def run():
# Load IOB data # Load IOB data
iob_sites = load_iob_sites("iobs-{}.csv".format(os.getenv("VIVADO_PART"))) iob_sites = load_iob_sites("iobs-{}.csv".format(os.getenv("VIVADO_PART")))
# Generate IOB site to package pin map and *M site to *S site map.
site_to_pkg_pin = {}
master_to_slave = {}
for region, sites in iob_sites.items():
tiles = defaultdict(lambda: {})
for site in sites:
site_to_pkg_pin[site["name"]] = site["pkg_pin"]
if site["type"] == "IOB33M":
tiles[site["tile"]]["M"] = site
if site["type"] == "IOB33S":
tiles[site["tile"]]["S"] = site
for sites in tiles.values():
master_to_slave[sites["M"]["name"]] = sites["S"]["name"]
# Generate designs # Generate designs
iosettings_gen = gen_iosettings() iosettings_gen = gen_iosettings()
design_index = 0 design_index = 0
@ -202,6 +220,8 @@ module top (
); );
""".format(num_inp=num_inp - 1, num_ino=num_ino - 1, num_out=num_out - 1) """.format(num_inp=num_inp - 1, num_ino=num_ino - 1, num_out=num_out - 1)
tcl = ""
inp_idx = 0 inp_idx = 0
out_idx = 0 out_idx = 0
ino_idx = 0 ino_idx = 0
@ -255,6 +275,18 @@ module top (
# Single ended # Single ended
if not is_diff: if not is_diff:
tcl += "set_property PACKAGE_PIN {} [get_ports inp[{}]]\n".format(
site_to_pkg_pin[keys["ibuf_0_loc"]], keys["inp_0_p"])
tcl += "set_property PACKAGE_PIN {} [get_ports inp[{}]]\n".format(
site_to_pkg_pin[keys["ibuf_1_loc"]], keys["inp_1_p"])
tcl += "set_property PACKAGE_PIN {} [get_ports out[{}]]\n".format(
site_to_pkg_pin[keys["obuf_0_loc"]], keys["inp_0_p"])
tcl += "set_property PACKAGE_PIN {} [get_ports out[{}]]\n".format(
site_to_pkg_pin[keys["obuf_1_loc"]], keys["inp_1_p"])
tcl += "set_property PACKAGE_PIN {} [get_ports ino[{}]]\n".format(
site_to_pkg_pin[keys["iobuf_loc"]], keys["ino_p"])
verilog += """ verilog += """
// {region} // {region}
@ -269,25 +301,25 @@ module top (
""".format(**keys) """.format(**keys)
verilog += """ verilog += """
(* KEEP, DONT_TOUCH, LOC="{ibuf_0_loc}" *) (* KEEP, DONT_TOUCH *)
IBUF # ({ibuf_param_str}) ibuf_0_{region} ( IBUF # ({ibuf_param_str}) ibuf_0_{region} (
.I(inp[{inp_0_p}]), .I(inp[{inp_0_p}]),
.O(inp_0_{region}) .O(inp_0_{region})
); );
(* KEEP, DONT_TOUCH, LOC="{ibuf_1_loc}" *) (* KEEP, DONT_TOUCH *)
IBUF # ({ibuf_param_str}) ibuf_1_{region} ( IBUF # ({ibuf_param_str}) ibuf_1_{region} (
.I(inp[{inp_1_p}]), .I(inp[{inp_1_p}]),
.O(inp_1_{region}) .O(inp_1_{region})
); );
(* KEEP, DONT_TOUCH, LOC="{obuf_0_loc}" *) (* KEEP, DONT_TOUCH *)
OBUF # ({obuf_param_str}) obuf_0_{region} ( OBUF # ({obuf_param_str}) obuf_0_{region} (
.I(out_0_{region}), .I(out_0_{region}),
.O(out[{out_0_p}]) .O(out[{out_0_p}])
); );
(* KEEP, DONT_TOUCH, LOC="{obuf_1_loc}" *) (* KEEP, DONT_TOUCH *)
OBUF # ({obuf_param_str}) obuf_1_{region} ( OBUF # ({obuf_param_str}) obuf_1_{region} (
.I(out_1_{region}), .I(out_1_{region}),
.O(out[{out_1_p}]) .O(out[{out_1_p}])
@ -297,7 +329,7 @@ module top (
if use_ino: if use_ino:
verilog += """ verilog += """
(* KEEP, DONT_TOUCH, LOC="{iobuf_loc}" *) (* KEEP, DONT_TOUCH *)
IOBUF # ({obuf_param_str}) iobuf_{region} ( IOBUF # ({obuf_param_str}) iobuf_{region} (
.I(ino_i_{region}), .I(ino_i_{region}),
.O(ino_o_{region}), .O(ino_o_{region}),
@ -321,6 +353,33 @@ module top (
# Differential # Differential
else: else:
tcl += "set_property PACKAGE_PIN {} [get_ports inp[{}]]\n".format(
site_to_pkg_pin[keys["ibuf_0_loc"]], keys["inp_0_p"])
tcl += "set_property PACKAGE_PIN {} [get_ports inp[{}]]\n".format(
site_to_pkg_pin[master_to_slave[keys["ibuf_0_loc"]]],
keys["inp_0_n"])
tcl += "set_property PACKAGE_PIN {} [get_ports inp[{}]]\n".format(
site_to_pkg_pin[keys["ibuf_1_loc"]], keys["inp_1_p"])
tcl += "set_property PACKAGE_PIN {} [get_ports inp[{}]]\n".format(
site_to_pkg_pin[master_to_slave[keys["ibuf_1_loc"]]],
keys["inp_1_n"])
tcl += "set_property PACKAGE_PIN {} [get_ports out[{}]]\n".format(
site_to_pkg_pin[keys["obuf_0_loc"]], keys["inp_0_p"])
tcl += "set_property PACKAGE_PIN {} [get_ports out[{}]]\n".format(
site_to_pkg_pin[master_to_slave[keys["obuf_0_loc"]]],
keys["inp_0_n"])
tcl += "set_property PACKAGE_PIN {} [get_ports out[{}]]\n".format(
site_to_pkg_pin[keys["obuf_1_loc"]], keys["inp_1_p"])
tcl += "set_property PACKAGE_PIN {} [get_ports out[{}]]\n".format(
site_to_pkg_pin[master_to_slave[keys["obuf_1_loc"]]],
keys["inp_1_n"])
tcl += "set_property PACKAGE_PIN {} [get_ports ino[{}]]\n".format(
site_to_pkg_pin[keys["iobuf_loc"]], keys["ino_p"])
tcl += "set_property PACKAGE_PIN {} [get_ports ino[{}]]\n".format(
site_to_pkg_pin[master_to_slave[keys["iobuf_loc"]]],
keys["ino_n"])
verilog += """ verilog += """
// {region} // {region}
@ -335,28 +394,28 @@ module top (
""".format(**keys) """.format(**keys)
verilog += """ verilog += """
(* KEEP, DONT_TOUCH, LOC="{ibuf_0_loc}" *) (* KEEP, DONT_TOUCH *)
IBUFDS # ({ibuf_param_str}) ibufds_0_{region} ( IBUFDS # ({ibuf_param_str}) ibufds_0_{region} (
.I(inp[{inp_0_p}]), .I(inp[{inp_0_p}]),
.IB(inp[{inp_0_n}]), .IB(inp[{inp_0_n}]),
.O(inp_0_{region}) .O(inp_0_{region})
); );
(* KEEP, DONT_TOUCH, LOC="{ibuf_1_loc}" *) (* KEEP, DONT_TOUCH *)
IBUFDS # ({ibuf_param_str}) ibufds_1_{region} ( IBUFDS # ({ibuf_param_str}) ibufds_1_{region} (
.I(inp[{inp_1_p}]), .I(inp[{inp_1_p}]),
.IB(inp[{inp_1_n}]), .IB(inp[{inp_1_n}]),
.O(inp_1_{region}) .O(inp_1_{region})
); );
(* KEEP, DONT_TOUCH, LOC="{obuf_0_loc}" *) (* KEEP, DONT_TOUCH *)
OBUFDS # ({obuf_param_str}) obufds_0_{region} ( OBUFDS # ({obuf_param_str}) obufds_0_{region} (
.I(out_0_{region}), .I(out_0_{region}),
.O(out[{out_0_p}]), .O(out[{out_0_p}]),
.OB(out[{out_0_n}]) .OB(out[{out_0_n}])
); );
(* KEEP, DONT_TOUCH, LOC="{obuf_1_loc}" *) (* KEEP, DONT_TOUCH *)
OBUFDS # ({obuf_param_str}) obufds_1_{region} ( OBUFDS # ({obuf_param_str}) obufds_1_{region} (
.I(out_1_{region}), .I(out_1_{region}),
.O(out[{out_1_p}]), .O(out[{out_1_p}]),
@ -367,7 +426,7 @@ module top (
if use_ino: if use_ino:
verilog += """ verilog += """
(* KEEP, DONT_TOUCH, LOC="{iobuf_loc}" *) (* KEEP, DONT_TOUCH *)
IOBUFDS # ({obuf_param_str}) iobufds_{region} ( IOBUFDS # ({obuf_param_str}) iobufds_{region} (
.I(ino_i_{region}), .I(ino_i_{region}),
.O(ino_o_{region}), .O(ino_o_{region}),
@ -398,6 +457,11 @@ module top (
with open(fname, "w") as fp: with open(fname, "w") as fp:
fp.write(verilog) fp.write(verilog)
# Write TCL
fname = "design_{:03d}.tcl".format(design_index)
with open(fname, "w") as fp:
fp.write(tcl)
# Write JSON # Write JSON
fname = "design_{:03d}.json".format(design_index) fname = "design_{:03d}.json".format(design_index)

3
minitests/iostandard/syn+par.tcl
View File

@ -5,6 +5,9 @@ set_property SEVERITY {Warning} [get_drc_checks UCIO-1]
read_verilog ../$env(PROJECT_NAME).v read_verilog ../$env(PROJECT_NAME).v
synth_design -top top synth_design -top top
source ../$env(PROJECT_NAME).tcl
place_design place_design
route_design route_design