diff --git a/minitests/iostandard/dump_iobs.tcl b/minitests/iostandard/dump_iobs.tcl
index 951eafdc..e7b71d46 100644
--- a/minitests/iostandard/dump_iobs.tcl
+++ b/minitests/iostandard/dump_iobs.tcl
@@ -11,11 +11,12 @@ proc dump_iobs {file_name} {
 
             set pin [get_package_pins -of_objects $site]
             set bank [get_property BANK $pin]
+            set pkg_pin [get_property NAME $pin]
             set is_clock [get_property IS_CLK_CAPABLE $pin]
             set is_global_clock [get_property IS_GLOBAL_CLK $pin]
             set is_vref [get_property IS_VREF $pin]
 
-            puts $fp "$tile,$site,$site_type,$clock_region,$bank,$is_bonded,$is_clock,$is_global_clock,$is_vref"
+            puts $fp "$tile,$site,$site_type,$clock_region,$bank,$pkg_pin,$is_bonded,$is_clock,$is_global_clock,$is_vref"
         }
     }
 
diff --git a/minitests/iostandard/features/Makefile b/minitests/iostandard/features/Makefile
index 04485600..32c41f07 100644
--- a/minitests/iostandard/features/Makefile
+++ b/minitests/iostandard/features/Makefile
@@ -14,6 +14,7 @@ all: analysis
 
 clean:
 	@rm -rf design_*.v
+	@rm -rf design_*.tcl
 	@rm -rf design_*.json
 	@rm -rf design_*.csv
 	@rm -rf design_*.fasm
diff --git a/minitests/iostandard/features/generate.py b/minitests/iostandard/features/generate.py
index 7c7fd2a4..470257d3 100644
--- a/minitests/iostandard/features/generate.py
+++ b/minitests/iostandard/features/generate.py
@@ -23,7 +23,7 @@ def load_iob_sites(file_name):
         for line in fp:
 
             fields = line.split(",")
-            if len(fields) != 9:
+            if len(fields) != 10:
                 continue
 
             iob_sites[fields[3]].append(
@@ -32,10 +32,11 @@ def load_iob_sites(file_name):
                     "name": fields[1],
                     "type": fields[2],
                     "bank": fields[4],
-                    "is_bonded": bool(int(fields[5])),
-                    "is_clock": bool(int(fields[6])),
-                    "is_global_clock": bool(int(fields[7])),
-                    "is_vref": bool(int(fields[8])),
+                    "pkg_pin": fields[5],
+                    "is_bonded": bool(int(fields[6])),
+                    "is_clock": bool(int(fields[7])),
+                    "is_global_clock": bool(int(fields[8])),
+                    "is_vref": bool(int(fields[9])),
                 })
 
     return iob_sites
@@ -124,6 +125,23 @@ def run():
     # Load IOB data
     iob_sites = load_iob_sites("iobs-{}.csv".format(os.getenv("VIVADO_PART")))
 
+    # Generate IOB site to package pin map and *M site to *S site map.
+    site_to_pkg_pin = {}
+    master_to_slave = {}
+
+    for region, sites in iob_sites.items():
+        tiles = defaultdict(lambda: {})
+
+        for site in sites:
+            site_to_pkg_pin[site["name"]] = site["pkg_pin"]
+            if site["type"] == "IOB33M":
+                tiles[site["tile"]]["M"] = site
+            if site["type"] == "IOB33S":
+                tiles[site["tile"]]["S"] = site
+
+        for sites in tiles.values():
+            master_to_slave[sites["M"]["name"]] = sites["S"]["name"]
+
     # Generate designs
     iosettings_gen = gen_iosettings()
     design_index = 0
@@ -202,6 +220,8 @@ module top (
 );
 """.format(num_inp=num_inp - 1, num_ino=num_ino - 1, num_out=num_out - 1)
 
+        tcl = ""
+
         inp_idx = 0
         out_idx = 0
         ino_idx = 0
@@ -255,6 +275,18 @@ module top (
 
             # Single ended
             if not is_diff:
+
+                tcl += "set_property PACKAGE_PIN {} [get_ports inp[{}]]\n".format(
+                    site_to_pkg_pin[keys["ibuf_0_loc"]], keys["inp_0_p"])
+                tcl += "set_property PACKAGE_PIN {} [get_ports inp[{}]]\n".format(
+                    site_to_pkg_pin[keys["ibuf_1_loc"]], keys["inp_1_p"])
+                tcl += "set_property PACKAGE_PIN {} [get_ports out[{}]]\n".format(
+                    site_to_pkg_pin[keys["obuf_0_loc"]], keys["inp_0_p"])
+                tcl += "set_property PACKAGE_PIN {} [get_ports out[{}]]\n".format(
+                    site_to_pkg_pin[keys["obuf_1_loc"]], keys["inp_1_p"])
+                tcl += "set_property PACKAGE_PIN {} [get_ports ino[{}]]\n".format(
+                    site_to_pkg_pin[keys["iobuf_loc"]], keys["ino_p"])
+
                 verilog += """
 
     // {region}
@@ -269,25 +301,25 @@ module top (
 """.format(**keys)
 
                 verilog += """
-    (* KEEP, DONT_TOUCH, LOC="{ibuf_0_loc}" *)
+    (* KEEP, DONT_TOUCH *)
     IBUF # ({ibuf_param_str}) ibuf_0_{region} (
     .I(inp[{inp_0_p}]),
     .O(inp_0_{region})
     );
 
-    (* KEEP, DONT_TOUCH, LOC="{ibuf_1_loc}" *)
+    (* KEEP, DONT_TOUCH *)
     IBUF # ({ibuf_param_str}) ibuf_1_{region} (
     .I(inp[{inp_1_p}]),
     .O(inp_1_{region})
     );
 
-    (* KEEP, DONT_TOUCH, LOC="{obuf_0_loc}" *)
+    (* KEEP, DONT_TOUCH *)
     OBUF # ({obuf_param_str}) obuf_0_{region} (
     .I(out_0_{region}),
     .O(out[{out_0_p}])
     );
 
-    (* KEEP, DONT_TOUCH, LOC="{obuf_1_loc}" *)
+    (* KEEP, DONT_TOUCH *)
     OBUF # ({obuf_param_str}) obuf_1_{region} (
     .I(out_1_{region}),
     .O(out[{out_1_p}])
@@ -297,7 +329,7 @@ module top (
                 if use_ino:
                     verilog += """
 
-    (* KEEP, DONT_TOUCH, LOC="{iobuf_loc}" *)
+    (* KEEP, DONT_TOUCH *)
     IOBUF # ({obuf_param_str}) iobuf_{region} (
     .I(ino_i_{region}),
     .O(ino_o_{region}),
@@ -321,6 +353,33 @@ module top (
 
             # Differential
             else:
+
+                tcl += "set_property PACKAGE_PIN {} [get_ports inp[{}]]\n".format(
+                    site_to_pkg_pin[keys["ibuf_0_loc"]], keys["inp_0_p"])
+                tcl += "set_property PACKAGE_PIN {} [get_ports inp[{}]]\n".format(
+                    site_to_pkg_pin[master_to_slave[keys["ibuf_0_loc"]]],
+                    keys["inp_0_n"])
+                tcl += "set_property PACKAGE_PIN {} [get_ports inp[{}]]\n".format(
+                    site_to_pkg_pin[keys["ibuf_1_loc"]], keys["inp_1_p"])
+                tcl += "set_property PACKAGE_PIN {} [get_ports inp[{}]]\n".format(
+                    site_to_pkg_pin[master_to_slave[keys["ibuf_1_loc"]]],
+                    keys["inp_1_n"])
+                tcl += "set_property PACKAGE_PIN {} [get_ports out[{}]]\n".format(
+                    site_to_pkg_pin[keys["obuf_0_loc"]], keys["inp_0_p"])
+                tcl += "set_property PACKAGE_PIN {} [get_ports out[{}]]\n".format(
+                    site_to_pkg_pin[master_to_slave[keys["obuf_0_loc"]]],
+                    keys["inp_0_n"])
+                tcl += "set_property PACKAGE_PIN {} [get_ports out[{}]]\n".format(
+                    site_to_pkg_pin[keys["obuf_1_loc"]], keys["inp_1_p"])
+                tcl += "set_property PACKAGE_PIN {} [get_ports out[{}]]\n".format(
+                    site_to_pkg_pin[master_to_slave[keys["obuf_1_loc"]]],
+                    keys["inp_1_n"])
+                tcl += "set_property PACKAGE_PIN {} [get_ports ino[{}]]\n".format(
+                    site_to_pkg_pin[keys["iobuf_loc"]], keys["ino_p"])
+                tcl += "set_property PACKAGE_PIN {} [get_ports ino[{}]]\n".format(
+                    site_to_pkg_pin[master_to_slave[keys["iobuf_loc"]]],
+                    keys["ino_n"])
+
                 verilog += """
 
     // {region}
@@ -335,28 +394,28 @@ module top (
 """.format(**keys)
 
                 verilog += """
-    (* KEEP, DONT_TOUCH, LOC="{ibuf_0_loc}" *)
+    (* KEEP, DONT_TOUCH *)
     IBUFDS # ({ibuf_param_str}) ibufds_0_{region} (
     .I(inp[{inp_0_p}]),
     .IB(inp[{inp_0_n}]),
     .O(inp_0_{region})
     );
 
-    (* KEEP, DONT_TOUCH, LOC="{ibuf_1_loc}" *)
+    (* KEEP, DONT_TOUCH *)
     IBUFDS # ({ibuf_param_str}) ibufds_1_{region} (
     .I(inp[{inp_1_p}]),
     .IB(inp[{inp_1_n}]),
     .O(inp_1_{region})
     );
 
-    (* KEEP, DONT_TOUCH, LOC="{obuf_0_loc}" *)
+    (* KEEP, DONT_TOUCH *)
     OBUFDS # ({obuf_param_str}) obufds_0_{region} (
     .I(out_0_{region}),
     .O(out[{out_0_p}]),
     .OB(out[{out_0_n}])
     );
 
-    (* KEEP, DONT_TOUCH, LOC="{obuf_1_loc}" *)
+    (* KEEP, DONT_TOUCH *)
     OBUFDS # ({obuf_param_str}) obufds_1_{region} (
     .I(out_1_{region}),
     .O(out[{out_1_p}]),
@@ -367,7 +426,7 @@ module top (
                 if use_ino:
                     verilog += """
 
-    (* KEEP, DONT_TOUCH, LOC="{iobuf_loc}" *)
+    (* KEEP, DONT_TOUCH *)
     IOBUFDS # ({obuf_param_str}) iobufds_{region} (
     .I(ino_i_{region}),
     .O(ino_o_{region}),
@@ -398,6 +457,11 @@ module top (
         with open(fname, "w") as fp:
             fp.write(verilog)
 
+        # Write TCL
+        fname = "design_{:03d}.tcl".format(design_index)
+        with open(fname, "w") as fp:
+            fp.write(tcl)
+
         # Write JSON
         fname = "design_{:03d}.json".format(design_index)
 
diff --git a/minitests/iostandard/syn+par.tcl b/minitests/iostandard/syn+par.tcl
index 81fc8254..e75a63c8 100644
--- a/minitests/iostandard/syn+par.tcl
+++ b/minitests/iostandard/syn+par.tcl
@@ -5,6 +5,9 @@ set_property SEVERITY {Warning} [get_drc_checks UCIO-1]
 
 read_verilog ../$env(PROJECT_NAME).v
 synth_design -top top
+
+source ../$env(PROJECT_NAME).tcl
+
 place_design
 route_design