mirror of https://github.com/openXC7/prjxray.git
Updated docs.
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
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@ -12,9 +12,11 @@ provide physical loopbacks of pins of those connectors. The clock is being
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routed internally.
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routed internally.
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The received data is compared against transmitted internally. Errors are
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The received data is compared against transmitted internally. Errors are
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indicated using LEDs.
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indicated using LEDs. The comparator module automatically invokes the bitslip
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feature of ISERDES (by brutaly testing all possible combinations).
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The pinout (out, in):
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The pinout (out, in):
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- JB.1, JB.7 - SDR, WIDTH=2
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- JB.1, JB.7 - SDR, WIDTH=2
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- JB.2, JB.8 - SDR, WIDTH=3
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- JB.2, JB.8 - SDR, WIDTH=3
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- JB.3, JB.9 - SDR, WIDTH=4
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- JB.3, JB.9 - SDR, WIDTH=4
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@ -30,6 +32,7 @@ The pinout (out, in):
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LEDs indicate whether data is being received corectly. When a LED is lit then
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LEDs indicate whether data is being received corectly. When a LED is lit then
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there is correct reception:
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there is correct reception:
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- LED0 - SDR, WIDTH=2
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- LED0 - SDR, WIDTH=2
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- LED1 - SDR, WIDTH=3
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- LED1 - SDR, WIDTH=3
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- LED2 - SDR, WIDTH=4
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- LED2 - SDR, WIDTH=4
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@ -41,3 +44,10 @@ there is correct reception:
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- LED8 - DDR, WIDTH=5
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- LED8 - DDR, WIDTH=5
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- LED9 - DDR, WIDTH=6
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- LED9 - DDR, WIDTH=6
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- LED10 - Blinking
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- LED10 - Blinking
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The switch SW0 is used as reset.
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To build the project run the following command and the bit file will be generated.
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```
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make basys3_top.bit
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```
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@ -1,4 +1,8 @@
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#!/usr/bin/env python3
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#!/usr/bin/env python3
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'''
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This script generates a verilog ROM module that contains data to be transmitted
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and received. The data is random.
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'''
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import random
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import random
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def main():
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def main():
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@ -47,11 +51,6 @@ endmodule
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rom_width = 8
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rom_width = 8
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rom_data = [random.randint(0, 2 ** rom_width - 1) for i in range(rom_size)]
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rom_data = [random.randint(0, 2 ** rom_width - 1) for i in range(rom_size)]
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# rom_data = []
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# for i in range(rom_size // 2):
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# rom_data.extend([0x00, 0xFF])
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rom_data = "\n".join([" rom[%4d] <= %d'd%d;" % (i, rom_width, d) for i, d in enumerate(rom_data)])
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rom_data = "\n".join([" rom[%4d] <= %d'd%d;" % (i, rom_width, d) for i, d in enumerate(rom_data)])
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print(template.format(
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print(template.format(
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