diff --git a/minitests/iserdes.sdr_ddr/README.md b/minitests/iserdes.sdr_ddr/README.md
index 55e4d9db..cb40738a 100644
--- a/minitests/iserdes.sdr_ddr/README.md
+++ b/minitests/iserdes.sdr_ddr/README.md
@@ -12,9 +12,11 @@ provide physical loopbacks of pins of those connectors. The clock is being
 routed internally.
 
 The received data is compared against transmitted internally. Errors are
-indicated using LEDs.
+indicated using LEDs. The comparator module automatically invokes the bitslip
+feature of ISERDES (by brutaly testing all possible combinations).
 
 The pinout (out, in):
+
 - JB.1,  JB.7  - SDR, WIDTH=2
 - JB.2,  JB.8  - SDR, WIDTH=3
 - JB.3,  JB.9  - SDR, WIDTH=4
@@ -30,6 +32,7 @@ The pinout (out, in):
 
 LEDs indicate whether data is being received corectly. When a LED is lit then
 there is correct reception:
+
 - LED0  - SDR, WIDTH=2
 - LED1  - SDR, WIDTH=3
 - LED2  - SDR, WIDTH=4
@@ -41,3 +44,10 @@ there is correct reception:
 - LED8  - DDR, WIDTH=5
 - LED9  - DDR, WIDTH=6
 - LED10 - Blinking
+
+The switch SW0 is used as reset.
+
+To build the project run the following command and the bit file will be generated.
+```
+make basys3_top.bit
+```
diff --git a/minitests/iserdes.sdr_ddr/src/gen_rom.py b/minitests/iserdes.sdr_ddr/src/gen_rom.py
index d3849c70..22a4bf4c 100755
--- a/minitests/iserdes.sdr_ddr/src/gen_rom.py
+++ b/minitests/iserdes.sdr_ddr/src/gen_rom.py
@@ -1,4 +1,8 @@
 #!/usr/bin/env python3
+'''
+This script generates a verilog ROM module that contains data to be transmitted
+and received. The data is random.
+'''
 import random
 
 def main():
@@ -47,11 +51,6 @@ endmodule
     rom_width = 8
 
     rom_data = [random.randint(0, 2 ** rom_width - 1) for i in range(rom_size)]
-
-#    rom_data = []
-#    for i in range(rom_size // 2):
-#        rom_data.extend([0x00, 0xFF])
-
     rom_data = "\n".join(["  rom[%4d] <= %d'd%d;" % (i, rom_width, d) for i, d in enumerate(rom_data)])
 
     print(template.format(