From 0deee961eb0afef25137254543b6be4db898e01b Mon Sep 17 00:00:00 2001 From: Keith Rothman <537074+litghost@users.noreply.github.com> Date: Thu, 22 Oct 2020 17:20:36 -0700 Subject: [PATCH] Add BRAM36_IN_USE feature. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com> --- fuzzers/027-bram36-config/Makefile | 2 +- fuzzers/027-bram36-config/generate.py | 16 +- fuzzers/027-bram36-config/top.py | 218 +++++++++++++++++++------- 3 files changed, 169 insertions(+), 67 deletions(-) diff --git a/fuzzers/027-bram36-config/Makefile b/fuzzers/027-bram36-config/Makefile index 71b797a9..98141f96 100644 --- a/fuzzers/027-bram36-config/Makefile +++ b/fuzzers/027-bram36-config/Makefile @@ -7,7 +7,7 @@ # SPDX-License-Identifier: ISC # read/write width is relatively slow to resolve # Even slower with multi bit masks... -N ?= 2 +N ?= 10 include ../fuzzer.mk diff --git a/fuzzers/027-bram36-config/generate.py b/fuzzers/027-bram36-config/generate.py index 6628dd0a..2d679d32 100644 --- a/fuzzers/027-bram36-config/generate.py +++ b/fuzzers/027-bram36-config/generate.py @@ -21,7 +21,7 @@ def write_ram_ext_tags(segmk, tile_param): segmk.add_site_tag( tile_param['site'], "{}_{}".format(param, opt), set_val == opt) segmk.add_site_tag( - tile_param['site'], "{}_NONE_OR_UPPER".format(param, opt), + tile_param['site'], "{}_NONE_OR_UPPER".format(param), set_val != "LOWER") @@ -33,12 +33,16 @@ def main(): params = json.load(f) for tile_param in params: - write_ram_ext_tags(segmk, tile_param) + if tile_param['BRAM36_IN_USE']: + write_ram_ext_tags(segmk, tile_param) - segmk.add_site_tag( - tile_param['site'], 'EN_ECC_READ', tile_param['EN_ECC_READ']) - segmk.add_site_tag( - tile_param['site'], 'EN_ECC_WRITE', tile_param['EN_ECC_WRITE']) + segmk.add_site_tag(tile_param['site'], 'BRAM36_IN_USE', 1) + segmk.add_site_tag( + tile_param['site'], 'EN_ECC_READ', tile_param['EN_ECC_READ']) + segmk.add_site_tag( + tile_param['site'], 'EN_ECC_WRITE', tile_param['EN_ECC_WRITE']) + else: + segmk.add_site_tag(tile_param['site'], 'BRAM36_IN_USE', 0) segmk.compile() segmk.write() diff --git a/fuzzers/027-bram36-config/top.py b/fuzzers/027-bram36-config/top.py index 1dad2d5f..26ce066f 100644 --- a/fuzzers/027-bram36-config/top.py +++ b/fuzzers/027-bram36-config/top.py @@ -12,14 +12,33 @@ import os import random import json random.seed(int(os.getenv("SEED"), 16)) +from prjxray.db import Database from prjxray import util from prjxray import verilog -def gen_bram36(): - for tile_name, site_name, _site_type in util.get_roi().gen_sites( - ['RAMBFIFO36E1']): - yield tile_name, site_name +def gen_bram36(grid): + for tile_name in grid.tiles(): + loc = grid.loc_of_tilename(tile_name) + + gridinfo = grid.gridinfo_at_loc(loc) + + found = False + for site_name, site_type in gridinfo.sites.items(): + if site_type == 'RAMBFIFO36E1': + found = True + break + + if found: + bram36_site_name = site_name + for site_name, site_type in gridinfo.sites.items(): + if site_type == 'RAMB18E1': + bram18_site_name = site_name + + if site_type == 'FIFO18E1': + fifo18_site_name = site_name + + yield tile_name, bram36_site_name, bram18_site_name, fifo18_site_name RAM_EXTENSION_OPTS = [ @@ -30,69 +49,148 @@ RAM_EXTENSION_OPTS = [ def main(): + db = Database(util.get_db_root(), util.get_part()) + grid = db.grid() + print(''' module top(); ''') params = [] - for tile_name, site_name in gen_bram36(): - ram_extension_a = random.choice(RAM_EXTENSION_OPTS) - ram_extension_b = random.choice(RAM_EXTENSION_OPTS) - en_ecc_read = random.randint(0, 1) - en_ecc_write = random.randint(0, 1) + for tile_name, bram36_site_name, bram18_site_name, fifo18_site_name in gen_bram36( + grid): + if random.random() < .8: + ram_extension_a = random.choice(RAM_EXTENSION_OPTS) + ram_extension_b = random.choice(RAM_EXTENSION_OPTS) + en_ecc_read = random.randint(0, 1) + en_ecc_write = random.randint(0, 1) - print( - ''' - (* KEEP, DONT_TOUCH, LOC = "{site}" *) - RAMB36E1 #( - .READ_WIDTH_A(1), - .WRITE_WIDTH_A(1), - .READ_WIDTH_B(1), - .WRITE_WIDTH_B(1), - .RAM_EXTENSION_A({ram_extension_a}), - .RAM_EXTENSION_B({ram_extension_b}), - .EN_ECC_READ({en_ecc_read}), - .EN_ECC_WRITE({en_ecc_write}) - ) bram_{site} ( - .CLKARDCLK(), - .CLKBWRCLK(), - .ENARDEN(), - .ENBWREN(), - .REGCEAREGCE(), - .REGCEB(), - .RSTRAMARSTRAM(), - .RSTRAMB(), - .RSTREGARSTREG(), - .RSTREGB(), - .ADDRARDADDR(), - .ADDRBWRADDR(), - .DIADI(), - .DIBDI(), - .DIPADIP(), - .DIPBDIP(), - .WEA(), - .WEBWE(), - .DOADO(), - .DOBDO(), - .DOPADOP(), - .DOPBDOP()); - '''.format( - site=site_name, - ram_extension_a=verilog.quote(ram_extension_a), - ram_extension_b=verilog.quote(ram_extension_b), - en_ecc_read=en_ecc_read, - en_ecc_write=en_ecc_write, - )) + print( + ''' + (* KEEP, DONT_TOUCH, LOC = "{site}" *) + RAMB36E1 #( + .READ_WIDTH_A(1), + .WRITE_WIDTH_A(1), + .READ_WIDTH_B(1), + .WRITE_WIDTH_B(1), + .RAM_EXTENSION_A({ram_extension_a}), + .RAM_EXTENSION_B({ram_extension_b}), + .EN_ECC_READ({en_ecc_read}), + .EN_ECC_WRITE({en_ecc_write}) + ) bram_{site} ( + .CLKARDCLK(), + .CLKBWRCLK(), + .ENARDEN(), + .ENBWREN(), + .REGCEAREGCE(), + .REGCEB(), + .RSTRAMARSTRAM(), + .RSTRAMB(), + .RSTREGARSTREG(), + .RSTREGB(), + .ADDRARDADDR(), + .ADDRBWRADDR(), + .DIADI(), + .DIBDI(), + .DIPADIP(), + .DIPBDIP(), + .WEA(), + .WEBWE(), + .DOADO(), + .DOBDO(), + .DOPADOP(), + .DOPBDOP()); + '''.format( + site=bram36_site_name, + ram_extension_a=verilog.quote(ram_extension_a), + ram_extension_b=verilog.quote(ram_extension_b), + en_ecc_read=en_ecc_read, + en_ecc_write=en_ecc_write, + )) - params.append( - { - 'tile': tile_name, - 'site': site_name, - 'RAM_EXTENSION_A': ram_extension_a, - 'RAM_EXTENSION_B': ram_extension_b, - 'EN_ECC_READ': en_ecc_read, - 'EN_ECC_WRITE': en_ecc_write, - }) + params.append( + { + 'tile': tile_name, + 'BRAM36_IN_USE': True, + 'site': bram36_site_name, + 'RAM_EXTENSION_A': ram_extension_a, + 'RAM_EXTENSION_B': ram_extension_b, + 'EN_ECC_READ': en_ecc_read, + 'EN_ECC_WRITE': en_ecc_write, + }) + else: + print( + ''' + (* KEEP, DONT_TOUCH, LOC = "{bram18}" *) + RAMB18E1 #( + .READ_WIDTH_A(1), + .WRITE_WIDTH_A(1), + .READ_WIDTH_B(1), + .WRITE_WIDTH_B(1) + ) bram_{bram18} ( + .CLKARDCLK(), + .CLKBWRCLK(), + .ENARDEN(), + .ENBWREN(), + .REGCEAREGCE(), + .REGCEB(), + .RSTRAMARSTRAM(), + .RSTRAMB(), + .RSTREGARSTREG(), + .RSTREGB(), + .ADDRARDADDR(), + .ADDRBWRADDR(), + .DIADI(), + .DIBDI(), + .DIPADIP(), + .DIPBDIP(), + .WEA(), + .WEBWE(), + .DOADO(), + .DOBDO(), + .DOPADOP(), + .DOPBDOP()); + + (* KEEP, DONT_TOUCH, LOC = "{fifo18}" *) + RAMB18E1 #( + .READ_WIDTH_A(1), + .WRITE_WIDTH_A(1), + .READ_WIDTH_B(1), + .WRITE_WIDTH_B(1) + ) bram_{fifo18} ( + .CLKARDCLK(), + .CLKBWRCLK(), + .ENARDEN(), + .ENBWREN(), + .REGCEAREGCE(), + .REGCEB(), + .RSTRAMARSTRAM(), + .RSTRAMB(), + .RSTREGARSTREG(), + .RSTREGB(), + .ADDRARDADDR(), + .ADDRBWRADDR(), + .DIADI(), + .DIBDI(), + .DIPADIP(), + .DIPBDIP(), + .WEA(), + .WEBWE(), + .DOADO(), + .DOBDO(), + .DOPADOP(), + .DOPBDOP()); + '''.format( + bram18=bram18_site_name, + fifo18=fifo18_site_name, + )) + + params.append( + { + 'tile': tile_name, + 'BRAM36_IN_USE': False, + 'site': bram36_site_name, + }) print("endmodule")