mirror of https://github.com/openXC7/prjxray.git
Add left and right clock pips.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
This commit is contained in:
Keith Rothman
parent
f58cf6bbda
commit
0b1e8e9974
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@ -1,20 +1,30 @@
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N ?= 50
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N ?= 150
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SPECIMENS_DEPS=build/cmt_regions.csv
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include ../fuzzer.mk
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database: build/segbits_clk_hrow.db
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build/clk_hrow_bot_r.txt: clk_hrow_pip_list.tcl
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mkdir -p build
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cd build/ && ${XRAY_VIVADO} -mode batch -source ${FUZDIR}/clk_hrow_pip_list.tcl
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build/cmt_regions.csv: output_cmt.tcl build/clk_hrow_bot_r.txt
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mkdir -p build
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cd build/ && ${XRAY_VIVADO} -mode batch -source ${FUZDIR}/output_cmt.tcl
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build/segbits_clk_hrow.rdb: $(SPECIMENS_OK)
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${XRAY_SEGMATCH} -o build/segbits_clk_hrow.rdb \
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$(addsuffix /segdata_clk_hrow_top_r.txt,$(SPECIMENS)) \
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$(addsuffix /segdata_clk_hrow_bot_r.txt,$(SPECIMENS))
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build/segbits_clk_hrow.db: build/segbits_clk_hrow.rdb
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build/segbits_clk_hrow.db: build/segbits_clk_hrow.rdb build/clk_hrow_bot_r.txt
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${XRAY_DBFIXUP} --db-root build --zero-db bits.dbf \
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--seg-fn-in build/segbits_clk_hrow.rdb \
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--seg-fn-out build/segbits_clk_hrow_rc.db
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python3 merge_gclk_entries.py \
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python3 merge_clk_entries.py \
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build/segbits_clk_hrow_rc.db \
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build/clk_hrow_bot_r.txt \
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build/segbits_clk_hrow.db
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${XRAY_MASKMERGE} build/mask_clk_hrow.db \
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@ -0,0 +1,34 @@
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HCLKS = 24
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GCLKS = 32
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SIDE_CLK_INPUTS = 14
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CLK_TABLE = {}
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CLK_TABLE_NUM_ROWS = 8
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CLK_TABLE_NUM_COLS = 8
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for gclk in range(GCLKS):
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gclk_name = 'CLK_HROW_R_CK_GCLK{}'.format(gclk)
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row = gclk % 8
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column = int(gclk / 8)
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CLK_TABLE[gclk_name] = (row, column)
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for lr in ['L', 'R']:
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for side_inputs in range(SIDE_CLK_INPUTS):
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side_clk_name = 'CLK_HROW_CK_IN_{}{}'.format(lr, side_inputs)
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for row in range(8):
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CLK_TABLE['CLK_HROW_CK_IN_L{}'.format(row)] = (row, 4)
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for row in range(6):
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CLK_TABLE['CLK_HROW_CK_IN_L{}'.format(row+8)] = (row, 5)
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for row in range(8):
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CLK_TABLE['CLK_HROW_CK_IN_R{}'.format(row)] = (row, 6)
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for row in range(6):
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CLK_TABLE['CLK_HROW_CK_IN_R{}'.format(row+8)] = (row, 7)
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# HROW_CK_INT_<X>_<Y>, Y == Y share the same bits, and only X = 0 or X = 1 are
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# present on a particular HROW.
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for y in range(2):
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for x in range(2):
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int_clk_name = 'CLK_HROW_CK_INT_{}_{}'.format(x, y)
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CLK_TABLE[int_clk_name] = (y+6, 7)
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@ -1,7 +1,7 @@
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#!/usr/bin/env python3
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from prjxray.segmaker import Segmaker
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import re
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import clk_table
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def main():
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@ -21,27 +21,23 @@ def main():
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_, src = src.split("/")
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_, dst = dst.split("/")
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rows = set(range(8))
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columns = set(range(4))
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rows = set(range(clk_table.CLK_TABLE_NUM_ROWS))
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columns = set(range(clk_table.CLK_TABLE_NUM_COLS))
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m = re.match('^CLK_HROW_R_CK_GCLK([0-9]+)$', src)
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if m:
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gclk = int(m.group(1))
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row = gclk % 8
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column = int(gclk / 8)
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if src in clk_table.CLK_TABLE:
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row, column = clk_table.CLK_TABLE[src]
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segmk.add_tile_tag(tile, '{}.GCLK_ENABLE_ROW{}'.format(dst, row), 1)
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segmk.add_tile_tag(tile, '{}.GCLK_ENABLE_COLUMN{}'.format(dst, column), 1)
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segmk.add_tile_tag(tile, '{}.HCLK_ENABLE_ROW{}'.format(dst, row), 1)
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segmk.add_tile_tag(tile, '{}.HCLK_ENABLE_COLUMN{}'.format(dst, column), 1)
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rows.remove(row)
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columns.remove(column)
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for row in rows:
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segmk.add_tile_tag(tile, '{}.GCLK_ENABLE_ROW{}'.format(dst, row), 0)
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segmk.add_tile_tag(tile, '{}.HCLK_ENABLE_ROW{}'.format(dst, row), 0)
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for column in columns:
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segmk.add_tile_tag(tile, '{}.GCLK_ENABLE_COLUMN{}'.format(dst, column), 0)
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segmk.add_tile_tag(tile, '{}.HCLK_ENABLE_COLUMN{}'.format(dst, column), 0)
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segmk.compile()
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segmk.write()
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@ -30,6 +30,8 @@ proc run {} {
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
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set_property IS_ENABLED 0 [get_drc_checks {REQP-161}]
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set_property IS_ENABLED 0 [get_drc_checks {REQP-123}]
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set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets]
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place_design
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@ -1,10 +1,10 @@
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import argparse
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GCLKS = 32
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import clk_table
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def main():
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parser = argparse.ArgumentParser(description="Convert GCLK ROW/COLUMN definitions into GCLK pips.")
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parser = argparse.ArgumentParser(description="Convert HCLK ROW/COLUMN definitions into HCLK pips.")
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parser.add_argument('in_segbit')
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parser.add_argument('piplist')
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parser.add_argument('out_segbit')
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args = parser.parse_args()
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@ -37,16 +37,34 @@ def main():
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assert src[-7:-1] == 'COLUMN', src
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hrow_outs[dst]['columns'][n] = bits
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with open(args.out_segbit, 'w') as f:
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for dst in hrow_outs:
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for gclk in range(GCLKS):
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row = gclk % 8
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column = int(gclk / 8)
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piplists = {}
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with open(args.piplist) as f:
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for l in f:
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tile, dst, src = l.strip().split('.')
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assert tile == 'CLK_HROW_BOT_R', tile
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print('{tile}.{dst}.CLK_HROW_R_CK_GCLK{gclk} {row_bits} {column_bits}'.format(
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tile=tile,
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if dst not in piplists:
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piplists[dst] = []
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piplists[dst].append(src)
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with open(args.out_segbit, 'w') as f:
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for dst in sorted(hrow_outs):
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for src in sorted(piplists[dst]):
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if src not in clk_table.CLK_TABLE:
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continue
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row, column = clk_table.CLK_TABLE[src]
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if row not in hrow_outs[dst]['rows']:
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continue
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if column not in hrow_outs[dst]['columns']:
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continue
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print('CLK_HROW.{dst}.{inclk} {row_bits} {column_bits}'.format(
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dst=dst,
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gclk=gclk,
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inclk=src,
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row_bits=hrow_outs[dst]['rows'][row],
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column_bits=hrow_outs[dst]['columns'][column],
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), file=f)
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@ -63,17 +63,22 @@ class ClockSources(object):
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def __init__(self):
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self.sources = {}
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self.merged_sources = {}
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self.source_to_cmt = {}
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self.used_sources_from_cmt = {}
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def add_clock_source(self, source, cmt):
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if cmt not in self.sources:
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self.sources[cmt] = []
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self.sources[cmt].append(source)
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assert source not in self.source_to_cmt or self.source_to_cmt[source] == cmt, source
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self.source_to_cmt[source] = cmt
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def get_random_source(self, cmt):
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if cmt not in self.merged_sources:
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choices = []
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choices.extend(self.sources['ANY'])
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if 'ANY' in self.sources:
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choices.extend(self.sources['ANY'])
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if cmt in self.sources:
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choices.extend(self.sources[cmt])
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@ -94,15 +99,49 @@ class ClockSources(object):
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self.merged_sources[cmt] = choices
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return random.choice(self.merged_sources[cmt])
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if self.merged_sources[cmt]:
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source = random.choice(self.merged_sources[cmt])
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source_cmt = self.source_to_cmt[source]
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if source_cmt not in self.used_sources_from_cmt:
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self.used_sources_from_cmt[source_cmt] = set()
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self.used_sources_from_cmt[source_cmt].add(source)
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if source_cmt != 'ANY' and len(self.used_sources_from_cmt[source_cmt]) > 14:
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print('//', self.used_sources_from_cmt)
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self.used_sources_from_cmt[source_cmt].remove(source)
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return None
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else:
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return source
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def other_sources():
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def check_allowed(mmcm_pll_dir, cmt):
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if mmcm_pll_dir == 'BOTH':
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return True
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elif mmcm_pll_dir == 'ODD':
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return (int(CMT_RE.match(cmt).group(1)) & 1) == 1
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elif mmcm_pll_dir == 'EVEN':
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return (int(CMT_RE.match(cmt).group(1)) & 1) == 0
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else:
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assert False, mmcm_pll_dir
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def main():
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print('''
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module top();
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''')
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site_to_cmt = dict(read_site_to_cmt())
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clock_sources = ClockSources()
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clock_sources.add_clock_source('one', 'ANY')
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clock_sources.add_clock_source('zero', 'ANY')
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mmcm_pll_only = random.randint(0, 1)
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mmcm_pll_dir = random.choice(('ODD', 'EVEN', 'BOTH'))
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if not mmcm_pll_only:
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for _ in range(2):
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clock_sources.add_clock_source('one', 'ANY')
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clock_sources.add_clock_source('zero', 'ANY')
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print("""
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wire zero = 0;
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@ -110,7 +149,7 @@ def other_sources():
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for idx in range(1):
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wire_name = "lut_wire_{}".format(idx)
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clock_sources.add_clock_source(wire_name, 'ANY')
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#clock_sources.add_clock_source(wire_name, 'ANY')
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print("""
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(* KEEP, DONT_TOUCH *)
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wire {wire_name};
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@ -121,11 +160,59 @@ def other_sources():
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wire_name=wire_name,
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))
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for site in gen_sites('MMCME2_ADV'):
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mmcm_clocks = ['mmcm_clock_{site}_{idx}'.format(site=site, idx=idx) for
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idx in range(13)]
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if not check_allowed(mmcm_pll_dir, site_to_cmt[site]):
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continue
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for clk in mmcm_clocks:
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clock_sources.add_clock_source(clk, site_to_cmt[site])
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print("""
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wire {c0}, {c1}, {c2}, {c3}, {c4}, {c5};
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(* KEEP, DONT_TOUCH, LOC = "{site}" *)
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MMCME2_ADV pll_{site} (
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.CLKOUT0({c0}),
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.CLKOUT0B({c1}),
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.CLKOUT1({c2}),
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.CLKOUT1B({c3}),
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.CLKOUT2({c4}),
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.CLKOUT2B({c5}),
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.CLKOUT3({c6}),
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.CLKOUT3B({c7}),
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.CLKOUT4({c8}),
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.CLKOUT5({c9}),
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.CLKOUT6({c10}),
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.CLKFBOUT({c11}),
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.CLKFBOUTB({c12})
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);
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""".format(
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site=site,
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c0=mmcm_clocks[0],
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c1=mmcm_clocks[1],
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c2=mmcm_clocks[2],
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c3=mmcm_clocks[3],
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c4=mmcm_clocks[4],
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c5=mmcm_clocks[5],
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c6=mmcm_clocks[6],
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c7=mmcm_clocks[7],
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c8=mmcm_clocks[8],
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c9=mmcm_clocks[9],
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c10=mmcm_clocks[10],
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c11=mmcm_clocks[11],
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c12=mmcm_clocks[12],
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))
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for site in gen_sites('PLLE2_ADV'):
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pll_clocks = ['pll_clock_{site}_{idx}'.format(site=site, idx=idx) for
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idx in range(6)]
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for clk in pll_clocks[:2]:
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if not check_allowed(mmcm_pll_dir, site_to_cmt[site]):
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continue
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for clk in pll_clocks:
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clock_sources.add_clock_source(clk, site_to_cmt[site])
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print("""
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@ -149,16 +236,11 @@ def other_sources():
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c5=pll_clocks[5],
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))
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def main():
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print('''
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module top();
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''')
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gclks = []
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for site in sorted(gen_sites("BUFGCTRL"), key=get_xy):
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wire_name = 'clk_{}'.format(site)
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gclks.append(wire_name)
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if not mmcm_pll_only:
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clock_sources.add_clock_source(wire_name, 'ANY')
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print("""
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wire {wire_name};
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@ -174,14 +256,18 @@ module top();
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bufhce_sites = list(gen_bufhce_sites())
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for tile_name, sites in bufhce_sites:
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for site in sites:
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wire_name = clock_sources.get_random_source(site_to_cmt[site])
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if wire_name is None:
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continue
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print("""
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(* KEEP, DONT_TOUCH, LOC = "{site}" *)
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BUFHCE buf_{site} (
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.I({wire_name})
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);
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(* KEEP, DONT_TOUCH, LOC = "{site}" *)
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BUFHCE buf_{site} (
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.I({wire_name})
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);
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""".format(
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site=site,
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wire_name=random.choice(gclks),
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wire_name=wire_name,
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))
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print("endmodule")
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@ -2,13 +2,14 @@ N ?= 1
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SPECIMENS := $(addprefix build/specimen_,$(shell seq -f '%03.0f' $(N)))
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SPECIMENS_OK := $(addsuffix /OK,$(SPECIMENS))
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ENV_VAR ?=
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SPECIMENS_DEPS ?=
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FUZDIR ?= ${PWD}
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all: database
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# generate.sh / top_generate.sh call make, hence the command must
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# have a + before it.
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$(SPECIMENS_OK):
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$(SPECIMENS_OK): $(SPECIMENS_DEPS)
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mkdir -p build
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+if [ -f $(FUZDIR)/generate.sh ]; then \
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export $(ENV_VAR); \
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