mirror of https://github.com/openXC7/prjxray.git
277 lines
7.3 KiB
Python
277 lines
7.3 KiB
Python
import os
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import re
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import random
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random.seed(int(os.getenv("SEED"), 16))
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from prjxray import util
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from prjxray.db import Database
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XY_RE = re.compile('^BUFHCE_X([0-9]+)Y([0-9]+)$')
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BUFGCTRL_XY_RE = re.compile('^BUFGCTRL_X([0-9]+)Y([0-9]+)$')
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"""
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BUFHCE's can be driven from:
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MMCME2_ADV
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BUFHCE
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PLLE2_ADV
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BUFGCTRL
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"""
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def get_xy(s):
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m = BUFGCTRL_XY_RE.match(s)
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x = int(m.group(1))
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y = int(m.group(2))
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return x, y
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def gen_sites(desired_site_type):
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db = Database(util.get_db_root())
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grid = db.grid()
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for tile_name in sorted(grid.tiles()):
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loc = grid.loc_of_tilename(tile_name)
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gridinfo = grid.gridinfo_at_loc(loc)
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for site, site_type in gridinfo.sites.items():
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if site_type == desired_site_type:
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yield site
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def gen_bufhce_sites():
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db = Database(util.get_db_root())
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grid = db.grid()
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for tile_name in sorted(grid.tiles()):
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loc = grid.loc_of_tilename(tile_name)
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gridinfo = grid.gridinfo_at_loc(loc)
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sites = []
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for site, site_type in gridinfo.sites.items():
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if site_type == 'BUFHCE':
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sites.append(site)
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if sites:
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yield tile_name, sorted(sites)
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def read_site_to_cmt():
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with open(os.path.join(os.getenv('FUZDIR'), 'build', 'cmt_regions.csv')) as f:
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for l in f:
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site, cmt = l.strip().split(',')
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yield (site, cmt)
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CMT_RE = re.compile('X([0-9]+)Y([0-9]+)')
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class ClockSources(object):
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def __init__(self):
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self.sources = {}
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self.merged_sources = {}
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self.source_to_cmt = {}
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self.used_sources_from_cmt = {}
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def add_clock_source(self, source, cmt):
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if cmt not in self.sources:
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self.sources[cmt] = []
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self.sources[cmt].append(source)
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assert source not in self.source_to_cmt or self.source_to_cmt[source] == cmt, source
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self.source_to_cmt[source] = cmt
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def get_random_source(self, cmt):
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if cmt not in self.merged_sources:
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choices = []
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if 'ANY' in self.sources:
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choices.extend(self.sources['ANY'])
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if cmt in self.sources:
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choices.extend(self.sources[cmt])
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m = CMT_RE.match(cmt)
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x = int(m.group(1))
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y = int(m.group(2))
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if x % 2 == 0:
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x += 1
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else:
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x -= 1
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paired_cmt = 'X{}Y{}'.format(x, y)
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if paired_cmt in self.sources:
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choices.extend(self.sources[paired_cmt])
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self.merged_sources[cmt] = choices
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if self.merged_sources[cmt]:
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source = random.choice(self.merged_sources[cmt])
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source_cmt = self.source_to_cmt[source]
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if source_cmt not in self.used_sources_from_cmt:
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self.used_sources_from_cmt[source_cmt] = set()
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self.used_sources_from_cmt[source_cmt].add(source)
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if source_cmt != 'ANY' and len(self.used_sources_from_cmt[source_cmt]) > 14:
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print('//', self.used_sources_from_cmt)
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self.used_sources_from_cmt[source_cmt].remove(source)
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return None
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else:
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return source
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def check_allowed(mmcm_pll_dir, cmt):
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if mmcm_pll_dir == 'BOTH':
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return True
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elif mmcm_pll_dir == 'ODD':
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return (int(CMT_RE.match(cmt).group(1)) & 1) == 1
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elif mmcm_pll_dir == 'EVEN':
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return (int(CMT_RE.match(cmt).group(1)) & 1) == 0
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else:
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assert False, mmcm_pll_dir
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def main():
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print('''
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module top();
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''')
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site_to_cmt = dict(read_site_to_cmt())
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clock_sources = ClockSources()
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mmcm_pll_only = random.randint(0, 1)
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mmcm_pll_dir = random.choice(('ODD', 'EVEN', 'BOTH'))
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if not mmcm_pll_only:
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for _ in range(2):
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clock_sources.add_clock_source('one', 'ANY')
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clock_sources.add_clock_source('zero', 'ANY')
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print("""
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wire zero = 0;
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wire one = 1;""")
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for idx in range(1):
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wire_name = "lut_wire_{}".format(idx)
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#clock_sources.add_clock_source(wire_name, 'ANY')
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print("""
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(* KEEP, DONT_TOUCH *)
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wire {wire_name};
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LUT6 lut{idx} (
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.O({wire_name})
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);""".format(
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idx=idx,
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wire_name=wire_name,
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))
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for site in gen_sites('MMCME2_ADV'):
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mmcm_clocks = ['mmcm_clock_{site}_{idx}'.format(site=site, idx=idx) for
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idx in range(13)]
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if not check_allowed(mmcm_pll_dir, site_to_cmt[site]):
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continue
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for clk in mmcm_clocks:
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clock_sources.add_clock_source(clk, site_to_cmt[site])
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print("""
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wire {c0}, {c1}, {c2}, {c3}, {c4}, {c5};
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(* KEEP, DONT_TOUCH, LOC = "{site}" *)
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MMCME2_ADV pll_{site} (
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.CLKOUT0({c0}),
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.CLKOUT0B({c1}),
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.CLKOUT1({c2}),
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.CLKOUT1B({c3}),
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.CLKOUT2({c4}),
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.CLKOUT2B({c5}),
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.CLKOUT3({c6}),
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.CLKOUT3B({c7}),
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.CLKOUT4({c8}),
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.CLKOUT5({c9}),
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.CLKOUT6({c10}),
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.CLKFBOUT({c11}),
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.CLKFBOUTB({c12})
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);
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""".format(
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site=site,
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c0=mmcm_clocks[0],
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c1=mmcm_clocks[1],
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c2=mmcm_clocks[2],
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c3=mmcm_clocks[3],
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c4=mmcm_clocks[4],
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c5=mmcm_clocks[5],
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c6=mmcm_clocks[6],
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c7=mmcm_clocks[7],
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c8=mmcm_clocks[8],
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c9=mmcm_clocks[9],
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c10=mmcm_clocks[10],
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c11=mmcm_clocks[11],
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c12=mmcm_clocks[12],
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))
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for site in gen_sites('PLLE2_ADV'):
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pll_clocks = ['pll_clock_{site}_{idx}'.format(site=site, idx=idx) for
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idx in range(6)]
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if not check_allowed(mmcm_pll_dir, site_to_cmt[site]):
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continue
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for clk in pll_clocks:
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clock_sources.add_clock_source(clk, site_to_cmt[site])
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print("""
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wire {c0}, {c1}, {c2}, {c3}, {c4}, {c5};
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(* KEEP, DONT_TOUCH, LOC = "{site}" *)
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PLLE2_ADV pll_{site} (
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.CLKOUT0({c0}),
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.CLKOUT1({c1}),
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.CLKOUT2({c2}),
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.CLKOUT3({c3}),
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.CLKOUT4({c4}),
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.CLKOUT5({c5})
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);
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""".format(
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site=site,
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c0=pll_clocks[0],
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c1=pll_clocks[1],
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c2=pll_clocks[2],
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c3=pll_clocks[3],
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c4=pll_clocks[4],
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c5=pll_clocks[5],
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))
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for site in sorted(gen_sites("BUFGCTRL"), key=get_xy):
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wire_name = 'clk_{}'.format(site)
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if not mmcm_pll_only:
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clock_sources.add_clock_source(wire_name, 'ANY')
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print("""
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wire {wire_name};
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(* KEEP, DONT_TOUCH, LOC = "{site}" *)
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BUFG bufg_{site} (
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.O({wire_name})
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);
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""".format(
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site=site,
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wire_name=wire_name,
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))
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bufhce_sites = list(gen_bufhce_sites())
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for tile_name, sites in bufhce_sites:
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for site in sites:
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wire_name = clock_sources.get_random_source(site_to_cmt[site])
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if wire_name is None:
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continue
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print("""
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(* KEEP, DONT_TOUCH, LOC = "{site}" *)
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BUFHCE buf_{site} (
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.I({wire_name})
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);
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""".format(
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site=site,
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wire_name=wire_name,
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))
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print("endmodule")
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if __name__ == '__main__':
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main()
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