mirror of https://github.com/openXC7/prjxray.git
Merge pull request #75 from kc8apf/arch_docs
Start of 7-series architecture documentation
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_build
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# Minimal makefile for Sphinx documentation
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#
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# You can set these variables from the command line.
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SPHINXOPTS =
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SPHINXBUILD = sphinx-build
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SPHINXPROJ = ProjectX-Ray
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SOURCEDIR = .
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BUILDDIR = _build
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# Put it first so that "make" without argument is like "make help".
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help:
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@$(SPHINXBUILD) -M help "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O)
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.PHONY: help Makefile
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# Catch-all target: route all unknown targets to Sphinx using the new
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# "make mode" option. $(O) is meant as a shortcut for $(SPHINXOPTS).
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%: Makefile
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@$(SPHINXBUILD) -M $@ "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O)
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Glossary
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========================
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.. glossary::
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basic element
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BEL
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basic logic element
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BLE
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For example a LUT5, LUT6, CARRY4, or MUX, but not PIPs.
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BELs come in two types:
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* Basic BEL - A logic unit which does things.
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* Routing BEL - A unit which is statically configured at the routing time.
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bitstream
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Binary data that is directly loaded into an FPGA to perform configuration.
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Contains configuration :term:`frames <frame>` as well as programming
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sequences and other commands required to load and activate same.
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column
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Collection of :term:`tiles <tile>` physically organized as a vertical line.
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configurable logic block
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CLB
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Basic building block of logic.
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frame
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Fundamental unit of configuration data consisting of 101 :term:`words <word>`.
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half
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Portion of a device defined by a virtual line dividing the two sets of global
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clock buffers present in a device. The two halves are simply referred to as
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the top and bottom halves.
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node
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Collection of :term:`wires <wire>` spanning one or more tiles.
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programmable interconnect point
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PIP
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Connection point between two wires in a tile that may be enabled or
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disabled by the configuration.
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horizontal clock row
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Portion of a device including 12 horizontal clocks and the 50 interconnect
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and function tiles associated with them. A :term:`half` contains one or
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more horizontal clock rows and each half may have a different number of
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rows.
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site
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Portion of a tile where :term:`BELs <BEL>` can be placed. :term:`Slices
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<slice>` in a :term:`CLB` tile are sites.
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slice
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Portion of a :term:`CLB` tile that contains :term:`BELs <BEL>`.
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tile
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Fundamental unit of physical structure containing a single type of
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resource or function.
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wire
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Physical wire within a :term:`tile`.
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word
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32-bits stored in big-endian order. Fundamental unit of :term:`bitstream` format.
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.. _architecture_overview-label:
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Overview
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========
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.. todo:: add diagrams.
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Xilinx 7-Series architecture utilizes a hierarchical design of chainable
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structures to scale across the Spartan, Artix, Kintex, and Virtex product
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lines. This documentation focuses on the Artix and Kintex devices and omits
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some concepts introduced in Virtex devices.
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At the top-level, 7-Series devices are divided into two :term:`halves <half>`
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by a virtual horizontal line separating two sets of global clock buffers
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(BUFGs). While global clocks can be connected such that they span both sets of
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BUFGs, the two halves defined by this division are treated as separate entities
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as related to configuration. The halves are referred to simply as the top and
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bottom halves.
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Each halves is next divided vertically into one or more :term:`horizontal clock
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rows <horizontal clock row>`, numbered outward from the global clock buffer
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dividing line. Each horizontal clock row contains 12 clock lines that extend
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across the device perpendicular to the global clock spine. Similar to the
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global clock spine, each horizontal clock row is divided into two halves by two
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sets of horizontal clock buffers (BUFHs), one on each side of the global clock
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spine, yielding two :term:`clock domains <clock domain>`. Horizontal clocks
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may be used within a single clock domain, connected to span both clock domains
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in a horizontal clock row, or connected to global clocks.
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Clock domains have a fixed height of 50 :term:`interconnect tiles
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<interconnect tile>` centered around the horizontal clock lines (25 above, 25
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below). Various function tiles, such as :term:`CLBs <CLB>`, are attached to interconnect
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tiles.
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# -*- coding: utf-8 -*-
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#
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# Project X-Ray documentation build configuration file, created by
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# sphinx-quickstart on Mon Feb 5 11:04:37 2018.
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#
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# This file is execfile()d with the current directory set to its
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# containing dir.
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#
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# Note that not all possible configuration values are present in this
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# autogenerated file.
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#
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# All configuration values have a default; values that are commented out
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# serve to show the default.
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import os
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import re
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# If extensions (or modules to document with autodoc) are in another directory,
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# add these directories to sys.path here. If the directory is relative to the
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# documentation root, use os.path.abspath to make it absolute, like shown here.
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#
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# import os
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# import sys
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# sys.path.insert(0, os.path.abspath('.'))
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# -- General configuration ------------------------------------------------
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# If your documentation needs a minimal Sphinx version, state it here.
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#
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# needs_sphinx = '1.0'
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# Add any Sphinx extension module names here, as strings. They can be
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# extensions coming with Sphinx (named 'sphinx.ext.*') or your custom
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# ones.
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extensions = [
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'sphinx.ext.imgmath', 'sphinx.ext.autodoc', 'sphinx.ext.doctest',
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'sphinx.ext.autosummary', 'sphinx.ext.napoleon', 'sphinx.ext.todo'
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]
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# Add any paths that contain templates here, relative to this directory.
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templates_path = ['_templates']
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# The suffix(es) of source filenames.
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# You can specify multiple suffix as a list of string:
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#
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# source_suffix = ['.rst', '.md']
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source_suffix = '.rst'
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# The master toctree document.
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master_doc = 'index'
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# General information about the project.
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project = u'Project X-Ray'
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copyright = u'2018, SymbiFlow Team'
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author = u'SymbiFlow Team'
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# The version info for the project you're documenting, acts as replacement for
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# |version| and |release|, also used in various other places throughout the
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# built documents.
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#
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# The full version, including alpha/beta/rc tags.
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release = re.sub('^v', '', os.popen('git describe ').read().strip())
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# The short X.Y version.
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version = release
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# The language for content autogenerated by Sphinx. Refer to documentation
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# for a list of supported languages.
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#
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# This is also used if you do content translation via gettext catalogs.
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# Usually you set "language" from the command line for these cases.
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language = None
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# List of patterns, relative to source directory, that match files and
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# directories to ignore when looking for source files.
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# This patterns also effect to html_static_path and html_extra_path
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exclude_patterns = ['_build', 'Thumbs.db', '.DS_Store']
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# The name of the Pygments (syntax highlighting) style to use.
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pygments_style = 'sphinx'
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# If true, `todo` and `todoList` produce output, else they produce nothing.
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todo_include_todos = True
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# -- Options for HTML output ----------------------------------------------
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# The theme to use for HTML and HTML Help pages. See the documentation for
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# a list of builtin themes.
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#
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html_theme = 'sphinx_rtd_theme'
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# Theme options are theme-specific and customize the look and feel of a theme
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# further. For a list of options available for each theme, see the
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# documentation.
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#
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# html_theme_options = {}
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# Enable github links when not on readthedocs
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on_rtd = os.environ.get('READTHEDOCS', None) == 'True'
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if not on_rtd:
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html_context = {
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"display_github": True, # Integrate GitHub
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"github_user": "symbiflow", # Username
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"github_repo": "prjxray", # Repo name
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"github_version": "master", # Version
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"conf_py_path": "/doc/",
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}
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# Add any paths that contain custom static files (such as style sheets) here,
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# relative to this directory. They are copied after the builtin static files,
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# so a file named "default.css" will overwrite the builtin "default.css".
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html_static_path = ['_static']
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# Custom sidebar templates, must be a dictionary that maps document names
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# to template names.
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#
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# This is required for the alabaster theme
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# refs: http://alabaster.readthedocs.io/en/latest/installation.html#sidebars
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html_sidebars = {
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'**': [
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'relations.html', # needs 'show_related': True theme option to display
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'searchbox.html',
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]
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}
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# -- Options for HTMLHelp output ------------------------------------------
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# Output file base name for HTML help builder.
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htmlhelp_basename = 'prjxray'
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# -- Options for LaTeX output ---------------------------------------------
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latex_elements = {
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# The paper size ('letterpaper' or 'a4paper').
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#
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# 'papersize': 'letterpaper',
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# The font size ('10pt', '11pt' or '12pt').
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#
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# 'pointsize': '10pt',
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# Additional stuff for the LaTeX preamble.
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#
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# 'preamble': '',
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# Latex figure (float) alignment
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#
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# 'figure_align': 'htbp',
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}
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# Grouping the document tree into LaTeX files. List of tuples
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# (source start file, target name, title,
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# author, documentclass [howto, manual, or own class]).
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latex_documents = [
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(
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master_doc, 'ProjectX-Ray.tex', u'Project X-Ray Documentation',
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u'SymbiFlow Team', 'manual'),
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]
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# -- Options for manual page output ---------------------------------------
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# One entry per manual page. List of tuples
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# (source start file, name, description, authors, manual section).
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man_pages = [
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(master_doc, 'projectx-ray', u'Project X-Ray Documentation', [author], 1)
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]
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# -- Options for Texinfo output -------------------------------------------
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# Grouping the document tree into Texinfo files. List of tuples
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# (source start file, target name, title, author,
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# dir menu entry, description, category)
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texinfo_documents = [
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(
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master_doc, 'ProjectX-Ray', u'Project X-Ray Documentation', author,
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'ProjectX-Ray', 'One line description of project.', 'Miscellaneous'),
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]
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# Example configuration for intersphinx: refer to the Python standard library.
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intersphinx_mapping = {'https://docs.python.org/': None}
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.. Project X-Ray documentation master file, created by
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sphinx-quickstart on Mon Feb 5 11:04:37 2018.
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You can adapt this file completely to your liking, but it should at least
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contain the root `toctree` directive.
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Welcome to Project X-Ray
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=========================================
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`Project X-Ray`_ documents the `Xilinx`_ 7-Series FPGA architecture to enable
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development of open-source tools. Our goal is to provide sufficient information
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to develop a free and open Verilog to bitstream toolchain for these devices.
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.. _Project X-Ray: https://github.com/SymbiFlow/prjxray
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.. _Xilinx: http://www.xilinx.com/
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.. toctree::
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:maxdepth: 2
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:caption: Xilinx 7-series Architecture
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architecture/overview
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architecture/glossary
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