mirror of https://github.com/openXC7/prjxray.git
Merge pull request #71 from mcmasterg/demoscene
roi_harness Basys3 demo
This commit is contained in:
Rick Altherr
GitHub
commit
ea3aa0fa70
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@ -7,3 +7,7 @@
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/vivado*
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/design.txt
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/out_*
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/*.fasm
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/*.bit
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/*.bin
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/*.frm
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@ -17,3 +17,7 @@ To build the baseline harness:
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To build a sample Vivado design using the harness:
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XRAY_ROIV=roi_inv.v XRAY_FIXED_XDC=out_xc7a35tcpg236-1_BASYS3-SWBUT_roi_basev/fixed_noclk.xdc ./runme.sh
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Note: this was intended for verification only and not as an end user flow (they should use SymbiFlow)
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To use the harness for the basys3 demo, do something like:
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python3 demo_sw_led.py out_xc7a35tcpg236-1_BASYS3-SWBUT_roi_basev 3 2
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This example connects switch 3 to LED 2
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@ -0,0 +1,42 @@
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#!/usr/bin/env python3
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import subprocess
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import demo_sw_led_fasm
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import os
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def run(roi_dir, swn, ledn):
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design_txt_fn = roi_dir + '/design.txt'
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bit_ref_fn = roi_dir + '/design.bit'
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fasm_fn = 'demo_sw_led.fasm'
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bit_out_fn = 'demo_sw_led.bit'
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ocd_cfg = os.getenv(
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'XRAY_DIR') + '/utils/openocd/board-digilent-basys3.cfg'
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# Clean up old tmp files to be sure we are generating them fresh
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subprocess.call('rm -f %s %s' % (fasm_fn, bit_out_fn), shell=True)
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# subprocess.shell("python3 demo_sw_led.py out_xc7a35tcpg236-1_BASYS3-SWBUT_roi_basev/design.txt 0 0 demo.fasm")
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demo_sw_led_fasm.run(
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open(design_txt_fn, 'r'), swn, ledn, open(fasm_fn, 'w'))
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subprocess.check_call(
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"./fasm2bit.sh %s %s %s" % (fasm_fn, bit_ref_fn, bit_out_fn),
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shell=True)
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subprocess.check_call(
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'openocd -f %s -c "init; pld load 0 %s; exit"' % (ocd_cfg, bit_out_fn),
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shell=True)
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if __name__ == '__main__':
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import argparse
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parser = argparse.ArgumentParser(
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description=
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'Basys3 switch to LED interconnect demo. Compiles and programs')
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parser.add_argument(
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'roi_dir', help='ROI project dir for harness .bit and metadata.txt')
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parser.add_argument('sw', type=int, help='Switch to use')
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parser.add_argument('led', type=int, help='LED to use')
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args = parser.parse_args()
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run(args.roi_dir, args.sw, args.led)
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@ -0,0 +1,65 @@
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#!/usr/bin/env python3
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import sys
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import os
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sys.path.append(os.getenv("XRAY_DIR") + "/tools")
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import simpleroute
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print()
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print('ready')
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def load_design(f):
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'''
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name node pin wire
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clk CLK_HROW_TOP_R_X60Y130/CLK_HROW_CK_BUFHCLK_L0 W5 HCLK_VBRK_X34Y130/HCLK_VBRK_CK_BUFHCLK0
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din[0] INT_R_X9Y100/NE2BEG3 V17 VBRK_X29Y106/VBRK_NE2A3
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'''
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ret = {}
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f.readline()
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for l in f:
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l = l.strip()
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name, node, pin, wire = l.split(' ')
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ret[name] = wire
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return ret
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def route2fasm(route, out_f):
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pips = simpleroute.route(route)
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for pip in pips:
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# INT_L_X10Y122.NL1BEG2.NE2END3
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# to
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# INT_L_X10Y122.NL1BEG2 NE2END3
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doti = pip.rfind('.')
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pip = pip[0:doti] + ' ' + pip[doti + 1:]
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out_f.write(pip + '\n')
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def run(design_f, swn, ledn, out_f):
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name2wire = load_design(design_f)
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led_name = 'dout[%d]' % ledn
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sw_name = 'din[%d]' % swn
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led_wire = name2wire[led_name]
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sw_wire = name2wire[sw_name]
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print(
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'Routing %s (%s) => %s (%s)' % (sw_wire, sw_name, led_wire, led_name))
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route2fasm((sw_wire, led_wire), out_f)
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# XXX: terminate LEDs so they are off?
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if __name__ == '__main__':
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import argparse
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parser = argparse.ArgumentParser(
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description='Switch to LED interconnect demo: FASM generator')
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parser.add_argument('design_txt', help='ROI metadata file')
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parser.add_argument('sw', type=int, help='Switch to use')
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parser.add_argument('led', type=int, help='LED to use')
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# For now can't use stdout since simpleroute is spewing out prints
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parser.add_argument('out_fasm', help='Output .fasm file')
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args = parser.parse_args()
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run(
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open(args.design_txt, 'r'), args.sw, args.led, open(
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args.out_fasm, 'w'))
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@ -0,0 +1,57 @@
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# Example pre-req
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# ./runme.sh
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# XRAY_ROIV=roi_inv.v XRAY_FIXED_XDC=out_xc7a35tcpg236-1_BASYS3-SWBUT_roi_basev/fixed_noclk.xdc ./runme.sh
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set -ex
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fasm_in=$1
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if [ -z "$fasm_in" ] ; then
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echo "need .fasm arg"
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exit
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fi
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bit_in=$2
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if [ -z "$bit_in" ] ; then
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echo "need .bit arg"
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exit
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fi
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bit_out=$3
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if [ -z "$bit_out" ] ; then
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bit_out=$(echo $fasm_in |sed s/.fasm/.bit/)
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if [ "$bit_out" = "$fasm_in" ] ; then
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echo "Expected fasm file"
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exit 1
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fi
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fi
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echo "Design .fasm: $fasm_in"
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echo "Harness .bit: $bit_in"
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echo "Out .bit: $bit_out"
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${XRAY_DIR}/tools/fasm2frame.py $fasm_in roi_partial.frm
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${XRAY_TOOLS_DIR}/xc7patch \
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--part_file ${XRAY_PART_YAML} \
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--bitstream_file $bit_in \
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--frm_file roi_partial.frm \
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--output_file patched.bin
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# WARNING: these values need to be tweaked if anything about the
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# Vivado-generated design changes.
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xxd -p -l 0x147 $bit_in | xxd -r -p - init_sequence.bit
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# WARNING: these values need to be tweaked if anything about the
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# Vivado-generated design changes.
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xxd -p -s 0x18 patched.bin | xxd -r -p - no_headers.bin
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# WARNING: these values need to be tweaked if anything about the
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# Vivado-generated design changes.
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xxd -p -s 0x216abf $bit_in | \
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tr -d '\n' | \
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sed -e 's/30000001.\{8\}/3000800100000007/g' | \
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fold -w 40 | \
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xxd -r -p - final_sequence.bin
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cat init_sequence.bit no_headers.bin final_sequence.bin >$bit_out
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#openocd -f $XRAY_DIR/utils/openocd/board-digilent-basys3.cfg -c "init; pld load 0 $bit_out; exit"
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@ -0,0 +1,149 @@
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//See README and tcl for more info
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`default_nettype none
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`include "defines.v"
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module roi(input wire clk,
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input wire [DIN_N-1:0] din, output wire [DOUT_N-1:0] dout);
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parameter DIN_N = `DIN_N;
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parameter DOUT_N = `DOUT_N;
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wire [DIN_N-1:0] din_lut;
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wire [DOUT_N-1:0] dout_lut;
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genvar i;
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generate
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//CLK
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(* KEEP, DONT_TOUCH *)
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reg clk_reg;
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always @(posedge clk) begin
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clk_reg <= clk_reg;
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end
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//DIN
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for (i = 0; i < DIN_N; i = i+1) begin:ins
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(* KEEP, DONT_TOUCH *)
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LUT6 #(
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.INIT(64'b01)
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) lut (
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.I0(din[i]),
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.I1(1'b0),
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.I2(1'b0),
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.I3(1'b0),
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.I4(1'b0),
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.I5(1'b0),
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.O(din_lut[i]));
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end
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//DOUT
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for (i = 0; i < DOUT_N; i = i+1) begin:outs
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(* KEEP, DONT_TOUCH *)
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LUT6 #(
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.INIT(64'b01)
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) lut (
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.I0(dout_lut[i]),
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.I1(1'b0),
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.I2(1'b0),
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.I3(1'b0),
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.I4(1'b0),
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.I5(1'b0),
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.O(dout[i]));
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end
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endgenerate
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demoscene demoscene(.clk(clk), .din(din_lut), .dout(dout_lut));
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endmodule
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module demoscene(input wire clk,
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input wire [DIN_N-1:0] din, output wire [DOUT_N-1:0] dout);
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parameter DIN_N = `DIN_N;
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parameter DOUT_N = `DOUT_N;
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//assign dout = 8'b10101010;
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demoscene_scroll dut(.clk(clk), .din(din), .dout(dout));
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endmodule
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/*
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Leftmost LED counts at one second
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*/
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module demoscene_counter(input wire clk,
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input wire [DIN_N-1:0] din, output wire [DOUT_N-1:0] dout);
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parameter DIN_N = `DIN_N;
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parameter DOUT_N = `DOUT_N;
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/*
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100 MHz clock
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Lets get MSB to 1 second
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Need 27 bits
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In [3]: math.log(100e6, 2)
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Out[3]: 26.5754247590989
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*/
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reg [26:0] div;
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always @(posedge clk) begin
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div <= div + 1'b1;
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end
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assign dout = div[26:19];
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endmodule
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//Loosely based on http://www.asic-world.com/code/hdl_models/lfsr.v
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module lfsr(input wire clk, output wire dout);
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reg [7:0] out = 8'hAA;
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wire feedback = !(out[7] ^ out[3]);
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always @(posedge clk) begin
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out <= {out[6],out[5],
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out[4],out[3],
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out[2],out[1],
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out[0], feedback};
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end
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assign dout = out[0];
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endmodule
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// http://www.fpga4fun.com/Counters3.html
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module lfsr2(input wire clk, output wire dout);
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reg [7:0] LFSR = 255;
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wire feedback = LFSR[7];
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assign dout = LFSR[0];
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always @(posedge clk) begin
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LFSR[0] <= feedback;
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LFSR[1] <= LFSR[0];
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LFSR[2] <= LFSR[1] ^ feedback;
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LFSR[3] <= LFSR[2] ^ feedback;
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LFSR[4] <= LFSR[3] ^ feedback;
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LFSR[5] <= LFSR[4];
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LFSR[6] <= LFSR[5];
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LFSR[7] <= LFSR[6];
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end
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endmodule
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/*
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Scrolls an LSFR across
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*/
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module demoscene_scroll(input wire clk,
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input wire [DIN_N-1:0] din, output wire [DOUT_N-1:0] dout);
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parameter DIN_N = `DIN_N;
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parameter DOUT_N = `DOUT_N;
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reg [26:0] div;
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always @(posedge clk) begin
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div <= div + 1'b1;
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end
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wire randbit;
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lfsr2 lfsr(.clk(clk), .dout(randbit));
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reg [7:0] leds = 8'hCC;
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reg last;
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reg tick;
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always @(posedge clk) begin
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last <= div[23];
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tick <= div[23] ^ last;
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if (tick) begin
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leds = {leds, randbit};
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end
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end
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assign dout = leds;
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endmodule
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@ -23,7 +23,7 @@ set X_BASE $XRAY_ROI_X0
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set Y_BASE $XRAY_ROI_Y0
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# set Y_DIN_BASE 100
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set Y_CLK_BASE $Y_BASE
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set Y_CLK_BASE $Y_BASE
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# Clock lut in middle
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set Y_DIN_BASE [expr "$Y_CLK_BASE + 1"]
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# Sequential
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@ -199,7 +199,7 @@ if {$fixed_xdc eq ""} {
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set_property CFGBVS VCCO [current_design]
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
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#set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
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set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF]
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@ -306,52 +306,59 @@ proc route_via2 {net nodes} {
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# net: net as string
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# nodes: string list of one or more intermediate routing nodes to visit
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set net [get_nets $net]
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# Start at the net source
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set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]]
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# End at the net destination
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# For sone reason this doesn't always show up
|
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set site_pins [get_site_pins -filter {DIRECTION == IN} -of_objects $net]
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set net [get_nets $net]
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# Start at the net source
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set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]]
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# End at the net destination
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# For sone reason this doesn't always show up
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set site_pins [get_site_pins -filter {DIRECTION == IN} -of_objects $net]
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if {$site_pins eq ""} {
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puts "WARNING: could not find end node"
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#error "Could not find end node"
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} else {
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set end_node [get_nodes -of_objects]
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lappend nodes [$end_node]
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}
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set end_node [get_nodes -of_objects]
|
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lappend nodes [$end_node]
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}
|
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puts ""
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puts "Routing net $net:"
|
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puts ""
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puts "Routing net $net:"
|
||||
|
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foreach to_node $nodes {
|
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foreach to_node $nodes {
|
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if {$to_node eq ""} {
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error "Empty node"
|
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}
|
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|
||||
# Node string to object
|
||||
set to_node [get_nodes -of_objects [get_wires $to_node]]
|
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# Start at last routed position
|
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set from_node [lindex $fixed_route end]
|
||||
# Let vivado do heavy liftin in between
|
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set route [find_routing_path -quiet -from $from_node -to $to_node]
|
||||
if {$route == ""} {
|
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# Some errors print a huge route
|
||||
puts [concat [string range " $from_node -> $to_node" 0 1000] ": no route found - assuming direct PIP"]
|
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lappend fixed_route $to_node
|
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} {
|
||||
puts [concat [string range " $from_node -> $to_node: $route" 0 1000] "routed"]
|
||||
set fixed_route [concat $fixed_route [lrange $route 1 end]]
|
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}
|
||||
set_property -quiet FIXED_ROUTE $fixed_route $net
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}
|
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# Node string to object
|
||||
set to_node [get_nodes -of_objects [get_wires $to_node]]
|
||||
# Start at last routed position
|
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set from_node [lindex $fixed_route end]
|
||||
# Let vivado do heavy liftin in between
|
||||
set route [find_routing_path -quiet -from $from_node -to $to_node]
|
||||
if {$route == ""} {
|
||||
# Some errors print a huge route
|
||||
puts [concat [string range " $from_node -> $to_node" 0 1000] ": no route found - assuming direct PIP"]
|
||||
lappend fixed_route $to_node
|
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} {
|
||||
puts [concat [string range " $from_node -> $to_node: $route" 0 1000] "routed"]
|
||||
set fixed_route [concat $fixed_route [lrange $route 1 end]]
|
||||
}
|
||||
set_property -quiet FIXED_ROUTE $fixed_route $net
|
||||
}
|
||||
|
||||
set_property -quiet FIXED_ROUTE $fixed_route $net
|
||||
puts ""
|
||||
set_property -quiet FIXED_ROUTE $fixed_route $net
|
||||
puts ""
|
||||
}
|
||||
|
||||
# Return the wire on the ROI boundary
|
||||
proc node2wire {node} {
|
||||
set wires [get_wires -of_objects [get_nodes $node]]
|
||||
set wire [lsearch -inline $wires *VBRK*]
|
||||
return $wire
|
||||
}
|
||||
|
||||
# XXX: maybe add IOB?
|
||||
set fp [open "design.txt" w]
|
||||
puts $fp "name node pin"
|
||||
set fp [open "$outdir/design.txt" w]
|
||||
puts $fp "name node pin wire"
|
||||
# Manual routing
|
||||
if {$fixed_xdc eq ""} {
|
||||
set x $X_BASE
|
||||
|
|
@ -361,10 +368,11 @@ if {$fixed_xdc eq ""} {
|
|||
# But we still need to record something, so lets force a route
|
||||
# FIXME: very ROI specific
|
||||
set node "CLK_HROW_TOP_R_X60Y130/CLK_HROW_CK_BUFHCLK_L0"
|
||||
set wire [node2wire $node]
|
||||
route_via2 "clk_IBUF_BUFG" "$node"
|
||||
set net "clk"
|
||||
set pin "$net2pin($net)"
|
||||
puts $fp "$net $node $pin"
|
||||
puts $fp "$net $node $pin $wire"
|
||||
|
||||
puts "Routing ROI inputs"
|
||||
# Arbitrary offset as observed
|
||||
|
|
@ -378,7 +386,8 @@ if {$fixed_xdc eq ""} {
|
|||
route_via2 "din_IBUF[$i]" "INT_R_X${x_EE2BEG3}Y${y}/EE2BEG3 $node"
|
||||
set net "din[$i]"
|
||||
set pin "$net2pin($net)"
|
||||
puts $fp "$net $node $pin"
|
||||
set wire [node2wire $node]
|
||||
puts $fp "$net $node $pin $wire"
|
||||
set y [expr {$y + $PITCH}]
|
||||
}
|
||||
|
||||
|
|
@ -409,7 +418,8 @@ if {$fixed_xdc eq ""} {
|
|||
}
|
||||
set net "dout[$i]"
|
||||
set pin "$net2pin($net)"
|
||||
puts $fp "$net $node $pin"
|
||||
set wire [node2wire $node]
|
||||
puts $fp "$net $node $pin $wire"
|
||||
set y [expr {$y + $PITCH}]
|
||||
}
|
||||
}
|
||||
|
|
@ -428,6 +438,6 @@ if {$fixed_xdc eq ""} {
|
|||
}
|
||||
|
||||
write_checkpoint -force $outdir/design.dcp
|
||||
set_property BITSTREAM.GENERAL.DEBUGBITSTREAM YES [current_design]
|
||||
#set_property BITSTREAM.GENERAL.DEBUGBITSTREAM YES [current_design]
|
||||
write_bitstream -force $outdir/design.bit
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,18 @@
|
|||
#!/usr/bin/env python3
|
||||
|
||||
import unittest
|
||||
import demo_sw_led
|
||||
|
||||
|
||||
class TestStringMethods(unittest.TestCase):
|
||||
def test_all(self):
|
||||
for i in range(8):
|
||||
print()
|
||||
print()
|
||||
print()
|
||||
print(i)
|
||||
demo_sw_led.run('out_xc7a35tcpg236-1_BASYS3-SWBUT_roi_basev', i, i)
|
||||
|
||||
|
||||
if __name__ == '__main__':
|
||||
unittest.main()
|
||||
|
|
@ -226,7 +226,7 @@ def run(f_in, f_out, sparse=False, debug=False):
|
|||
except KeyError:
|
||||
raise FASMSyntaxError(
|
||||
"Segment DB %s, key %s not found from line '%s'" %
|
||||
(segj['type'], db_k, l))
|
||||
(segj['type'], db_k, l)) from None
|
||||
|
||||
if not value:
|
||||
# If its binary, allow omitted value default to 1
|
||||
|
|
|
|||
|
|
@ -1,16 +1,7 @@
|
|||
#!/usr/bin/env python3
|
||||
|
||||
import getopt, sys, os, json, re
|
||||
|
||||
if len(sys.argv) == 1 or (len(sys.argv) % 2) != 1:
|
||||
print()
|
||||
print("Usage: %s src1 dst1 [src2 dst2 [...]]" % sys.argv[0])
|
||||
print()
|
||||
print(
|
||||
"Example: %s VBRK_X29Y140/VBRK_ER1BEG2 VFRAME_X47Y113/VFRAME_EL1BEG2" %
|
||||
sys.argv[0])
|
||||
print()
|
||||
sys.exit(1)
|
||||
import sys, os, json
|
||||
import pickle
|
||||
|
||||
|
||||
class MergeFind:
|
||||
|
|
@ -31,134 +22,178 @@ class MergeFind:
|
|||
return a
|
||||
|
||||
|
||||
print("Reading database..")
|
||||
def db_gen():
|
||||
print("Reading database..")
|
||||
|
||||
with open("%s/%s/tilegrid.json" % (os.getenv("XRAY_DATABASE_DIR"),
|
||||
os.getenv("XRAY_DATABASE")), "r") as f:
|
||||
tiles = json.load(f)["tiles"]
|
||||
with open("%s/%s/tilegrid.json" % (os.getenv("XRAY_DATABASE_DIR"),
|
||||
os.getenv("XRAY_DATABASE")), "r") as f:
|
||||
tiles = json.load(f)["tiles"]
|
||||
|
||||
with open("%s/%s/tileconn.json" % (os.getenv("XRAY_DATABASE_DIR"),
|
||||
os.getenv("XRAY_DATABASE")), "r") as f:
|
||||
tileconn = json.load(f)
|
||||
with open("%s/%s/tileconn.json" % (os.getenv("XRAY_DATABASE_DIR"),
|
||||
os.getenv("XRAY_DATABASE")), "r") as f:
|
||||
tileconn = json.load(f)
|
||||
|
||||
type_to_tiles = dict()
|
||||
grid_to_tile = dict()
|
||||
nodes = MergeFind()
|
||||
type_to_tiles = dict()
|
||||
grid_to_tile = dict()
|
||||
nodes = MergeFind()
|
||||
|
||||
for tile, tiledata in tiles.items():
|
||||
if tiledata["type"] not in type_to_tiles:
|
||||
type_to_tiles[tiledata["type"]] = list()
|
||||
type_to_tiles[tiledata["type"]].append(tile)
|
||||
grid_to_tile[(tiledata["grid_x"], tiledata["grid_y"])] = tile
|
||||
for tile, tiledata in tiles.items():
|
||||
if tiledata["type"] not in type_to_tiles:
|
||||
type_to_tiles[tiledata["type"]] = list()
|
||||
type_to_tiles[tiledata["type"]].append(tile)
|
||||
grid_to_tile[(tiledata["grid_x"], tiledata["grid_y"])] = tile
|
||||
|
||||
print("Processing tileconn..")
|
||||
print("Processing tileconn..")
|
||||
|
||||
for entry in tileconn:
|
||||
type_a, type_b = entry["tile_types"]
|
||||
for tile_a in type_to_tiles[type_a]:
|
||||
tiledata_a = tiles[tile_a]
|
||||
grid_a = (tiledata_a["grid_x"], tiledata_a["grid_y"])
|
||||
grid_b = (
|
||||
grid_a[0] + entry["grid_deltas"][0],
|
||||
grid_a[1] + entry["grid_deltas"][1])
|
||||
for entry in tileconn:
|
||||
type_a, type_b = entry["tile_types"]
|
||||
for tile_a in type_to_tiles[type_a]:
|
||||
tiledata_a = tiles[tile_a]
|
||||
grid_a = (tiledata_a["grid_x"], tiledata_a["grid_y"])
|
||||
grid_b = (
|
||||
grid_a[0] + entry["grid_deltas"][0],
|
||||
grid_a[1] + entry["grid_deltas"][1])
|
||||
|
||||
if grid_b not in grid_to_tile:
|
||||
continue
|
||||
|
||||
tile_b = grid_to_tile[grid_b]
|
||||
tiledata_b = tiles[tile_b]
|
||||
|
||||
if tiledata_b["type"] != type_b:
|
||||
continue
|
||||
|
||||
for pair in entry["wire_pairs"]:
|
||||
nodes.merge((tile_a, pair[0]), (tile_b, pair[1]))
|
||||
|
||||
print("Processing PIPs..")
|
||||
|
||||
node_node_pip = dict()
|
||||
reverse_node_node = dict()
|
||||
blocked_nodes = set()
|
||||
active_pips = set()
|
||||
|
||||
for tile_type in ["int_l", "int_r"]:
|
||||
with open("%s/%s/segbits_%s.db" % (os.getenv("XRAY_DATABASE_DIR"),
|
||||
os.getenv("XRAY_DATABASE"), tile_type),
|
||||
"r") as f:
|
||||
for line in f:
|
||||
_, dst, src = line.split()[0].split(".")
|
||||
for tile in type_to_tiles[tile_type.upper()]:
|
||||
src_node = nodes.find((tile, src))
|
||||
dst_node = nodes.find((tile, dst))
|
||||
if src_node not in node_node_pip:
|
||||
node_node_pip[src_node] = dict()
|
||||
if dst_node not in reverse_node_node:
|
||||
reverse_node_node[dst_node] = set()
|
||||
node_node_pip[src_node][dst_node] = "%s.%s.%s" % (
|
||||
tile, dst, src)
|
||||
reverse_node_node[dst_node].add(src_node)
|
||||
|
||||
for argidx in range((len(sys.argv) - 1) // 2):
|
||||
src_tile, src_wire = sys.argv[2 * argidx + 1].split("/")
|
||||
dst_tile, dst_wire = sys.argv[2 * argidx + 2].split("/")
|
||||
|
||||
src_node = nodes.find((src_tile, src_wire))
|
||||
dst_node = nodes.find((dst_tile, dst_wire))
|
||||
|
||||
print("Routing %s -> %s:" % (src_node, dst_node))
|
||||
|
||||
node_scores = dict()
|
||||
|
||||
def write_scores(nodes, count):
|
||||
next_nodes = set()
|
||||
for n in nodes:
|
||||
if n in node_scores:
|
||||
if grid_b not in grid_to_tile:
|
||||
continue
|
||||
node_scores[n] = count
|
||||
if n == src_node:
|
||||
return
|
||||
if n in reverse_node_node:
|
||||
for nn in reverse_node_node[n]:
|
||||
if nn not in node_scores and nn not in blocked_nodes:
|
||||
next_nodes.add(nn)
|
||||
write_scores(next_nodes, count + 1)
|
||||
|
||||
write_scores(set([dst_node]), 1)
|
||||
print(" route length: %d" % node_scores[src_node])
|
||||
tile_b = grid_to_tile[grid_b]
|
||||
tiledata_b = tiles[tile_b]
|
||||
|
||||
count = 0
|
||||
c = src_node
|
||||
blocked_nodes.add(c)
|
||||
print(" %4d: %s" % (count, c))
|
||||
if tiledata_b["type"] != type_b:
|
||||
continue
|
||||
|
||||
score = node_scores[src_node]
|
||||
while c != dst_node:
|
||||
nn = None
|
||||
for n in node_node_pip[c].keys():
|
||||
if n in node_scores and node_scores[n] < score:
|
||||
nn, score = n, node_scores[n]
|
||||
for pair in entry["wire_pairs"]:
|
||||
nodes.merge((tile_a, pair[0]), (tile_b, pair[1]))
|
||||
|
||||
pip = node_node_pip[c][nn]
|
||||
active_pips.add(pip)
|
||||
print(" %s" % pip)
|
||||
print("Processing PIPs..")
|
||||
|
||||
count += 1
|
||||
c = nn
|
||||
node_node_pip = dict()
|
||||
reverse_node_node = dict()
|
||||
|
||||
for tile_type in ["int_l", "int_r"]:
|
||||
with open("%s/%s/segbits_%s.db" %
|
||||
(os.getenv("XRAY_DATABASE_DIR"), os.getenv("XRAY_DATABASE"),
|
||||
tile_type), "r") as f:
|
||||
for line in f:
|
||||
_, dst, src = line.split()[0].split(".")
|
||||
for tile in type_to_tiles[tile_type.upper()]:
|
||||
src_node = nodes.find((tile, src))
|
||||
dst_node = nodes.find((tile, dst))
|
||||
if src_node not in node_node_pip:
|
||||
node_node_pip[src_node] = dict()
|
||||
if dst_node not in reverse_node_node:
|
||||
reverse_node_node[dst_node] = set()
|
||||
node_node_pip[src_node][dst_node] = "%s.%s.%s" % (
|
||||
tile, dst, src)
|
||||
reverse_node_node[dst_node].add(src_node)
|
||||
|
||||
return type_to_tiles, grid_to_tile, nodes, node_node_pip, reverse_node_node
|
||||
|
||||
|
||||
def db_load():
|
||||
# Takes a while. Speed things up
|
||||
picklef = os.getenv('XRAY_DIR') + '/tools/simpleroute.p'
|
||||
if os.path.exists(picklef):
|
||||
#print('Pickle: load')
|
||||
db_res = pickle.load(open(picklef, 'rb'))
|
||||
else:
|
||||
#print('Pickle: rebuilding')
|
||||
db_res = db_gen()
|
||||
#print('Pickle: save')
|
||||
pickle.dump(db_res, open(picklef, 'wb'))
|
||||
return db_res
|
||||
|
||||
|
||||
type_to_tiles, grid_to_tile, nodes, node_node_pip, reverse_node_node = db_load(
|
||||
)
|
||||
|
||||
|
||||
def route(args):
|
||||
active_pips = set()
|
||||
blocked_nodes = set()
|
||||
|
||||
for argidx in range((len(args)) // 2):
|
||||
src_tile, src_wire = args[2 * argidx].split("/")
|
||||
dst_tile, dst_wire = args[2 * argidx + 1].split("/")
|
||||
|
||||
src_node = nodes.find((src_tile, src_wire))
|
||||
dst_node = nodes.find((dst_tile, dst_wire))
|
||||
|
||||
print("Routing %s -> %s:" % (src_node, dst_node))
|
||||
|
||||
node_scores = dict()
|
||||
|
||||
def write_scores(nodes, count):
|
||||
next_nodes = set()
|
||||
for n in nodes:
|
||||
if n in node_scores:
|
||||
continue
|
||||
node_scores[n] = count
|
||||
if n == src_node:
|
||||
return
|
||||
if n in reverse_node_node:
|
||||
for nn in reverse_node_node[n]:
|
||||
if nn not in node_scores and nn not in blocked_nodes:
|
||||
next_nodes.add(nn)
|
||||
write_scores(next_nodes, count + 1)
|
||||
|
||||
try:
|
||||
write_scores(set([dst_node]), 1)
|
||||
except RecursionError as e:
|
||||
raise Exception("Could not find route for node %s" %
|
||||
(dst_node, )) from None
|
||||
print(" route length: %d" % node_scores[src_node])
|
||||
|
||||
count = 0
|
||||
c = src_node
|
||||
blocked_nodes.add(c)
|
||||
print(" %4d: %s" % (count, c))
|
||||
|
||||
print("====")
|
||||
pipnames = list()
|
||||
score = node_scores[src_node]
|
||||
while c != dst_node:
|
||||
nn = None
|
||||
for n in node_node_pip[c].keys():
|
||||
if n in node_scores and node_scores[n] < score:
|
||||
nn, score = n, node_scores[n]
|
||||
|
||||
for pip in sorted(active_pips):
|
||||
tile, dst, src = pip.split(".")
|
||||
pipnames.append("%s/%s.%s->>%s" % (tile, tile[0:5], src, dst))
|
||||
pip = node_node_pip[c][nn]
|
||||
active_pips.add(pip)
|
||||
print(" %s" % pip)
|
||||
|
||||
print(
|
||||
"highlight_objects -color orange [get_nodes -of_objects [get_wires {%s}]]"
|
||||
% " ".join(["%s/%s" % n for n in sorted(blocked_nodes)]))
|
||||
print("highlight_objects -color orange [get_pips {%s}]" % " ".join(pipnames))
|
||||
count += 1
|
||||
c = nn
|
||||
blocked_nodes.add(c)
|
||||
print(" %4d: %s" % (count, c))
|
||||
|
||||
print("====")
|
||||
for pip in sorted(active_pips):
|
||||
print(pip)
|
||||
print("====")
|
||||
pipnames = list()
|
||||
|
||||
for pip in sorted(active_pips):
|
||||
tile, dst, src = pip.split(".")
|
||||
pipnames.append("%s/%s.%s->>%s" % (tile, tile[0:5], src, dst))
|
||||
|
||||
print(
|
||||
"highlight_objects -color orange [get_nodes -of_objects [get_wires {%s}]]"
|
||||
% " ".join(["%s/%s" % n for n in sorted(blocked_nodes)]))
|
||||
print(
|
||||
"highlight_objects -color orange [get_pips {%s}]" % " ".join(pipnames))
|
||||
|
||||
print("====")
|
||||
for pip in sorted(active_pips):
|
||||
print(pip)
|
||||
return active_pips
|
||||
|
||||
|
||||
if __name__ == '__main__':
|
||||
if len(sys.argv) == 1 or (len(sys.argv) % 2) != 1:
|
||||
print()
|
||||
print("Usage: %s src1 dst1 [src2 dst2 [...]]" % sys.argv[0])
|
||||
print("Where entires as tile/wire")
|
||||
print()
|
||||
print(
|
||||
"Example: %s VBRK_X29Y140/VBRK_ER1BEG2 VFRAME_X47Y113/VFRAME_EL1BEG2"
|
||||
% sys.argv[0])
|
||||
print()
|
||||
sys.exit(1)
|
||||
route(sys.argv[1:])
|
||||
|
|
|
|||
Loading…
Reference in New Issue