mirror of https://github.com/openXC7/prjxray.git
Merge pull request #821 from litghost/timing_model_objects
Add objects and docstrings for timing model.
This commit is contained in:
litghost
GitHub
commit
02026c2d8b
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@ -0,0 +1,65 @@
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""" Math models are used to represent abstract operations for the timing models.
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This is useful for creating excel workbooks that can update dynamically, or
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generating a model with symbolic constants to be backsolved.
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"""
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class ExcelMathModel(object):
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""" Math model used for outputting to an dyanmic Excel sheet. """
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def __init__(self):
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pass
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def sum(self, elems):
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sum_val = '(' + ' + '.join(elems) + ')'
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if sum_val == '()':
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return '0'
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else:
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return sum_val
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def product(self, elems):
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sum_val = '(' + ' * '.join(elems) + ')'
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if sum_val == '()':
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return '1'
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else:
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return sum_val
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def plus(self, a, b):
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return self.sum((a, b))
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def divide(self, a, b):
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return '({}/{})'.format(a, b)
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def multiply(self, a, b):
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return '({}*{})'.format(a, b)
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def eval(self, elem):
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return '=' + elem
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def PythonMathModel(object):
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""" Math model used for outputting values equalated immediately. """
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def __init__(self):
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pass
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def sum(self, elems):
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return sum(elems)
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def product(self, elems):
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v = 1.0
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for elem in elems:
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v *= elem
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return v
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def divide(self, a, b):
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return a / b
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def plus(self, a, b):
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return a + b
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def multiply(self, a, b):
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return a * b
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def eval(self, elem):
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return elem
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285
prjxray/tile.py
285
prjxray/tile.py
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@ -1,38 +1,251 @@
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""" Database files available for a tile type. """
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from collections import namedtuple
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import json
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from prjxray import lib
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""" Database files available for a tile """
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from prjxray.timing import fast_slow_tuple_to_corners, RcElement
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TileDbs = namedtuple(
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'TileDbs', 'segbits block_ram_segbits ppips mask tile_type')
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Pip = namedtuple(
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'Pip', 'name net_to net_from can_invert is_directional is_pseudo')
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""" Site - Represents an instance of a site within a tile.
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name - Name of site within tile, instance specific.
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prefix - Prefix of site naming in Xilinx parlance.
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type - What type of slice this instance presents.
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pins - Instaces of site pins within this site and tile. This is an tuple of
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SitePin tuples, and is specific to this instance of the site within
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the tile.
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class OutPinTiming(namedtuple('OutPinTiming', 'delays drive_resistance')):
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""" Timing for site output pins.
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"""
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Site = namedtuple('Site', 'name prefix x y type site_pins')
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""" SitePin - Tuple representing a site pin within a tile.
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Attributes
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----------
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delays : dicts of PvtCorner to IntristicDelay
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Intristic delay of output pin.
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drive_resistance : float
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Resistance of drive output pin (milliOhms).
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Sites are generic based on type, however sites are instanced
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within a tile 1 or more times. The SitePin contains both site type generic
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information and tile type specific information.
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"""
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pass
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name - Site type specific name. This name is expected to be the same for all
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sites of the same type.
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wire - Wire name within the tile. This name is site instance specific.
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"""
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SitePin = namedtuple('SitePin', 'name wire')
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class InPinTiming(namedtuple('InPinTiming', 'delays capacitance')):
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""" Timing for site input pins.
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Attributes
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----------
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delays : dicts of PvtCorner to IntristicDelay
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Intristic delay of input pin.
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capacitance : float
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Capacitance of input pints (microFarads).
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"""
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pass
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class PipTiming(namedtuple('PipTiming',
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'delays drive_resistance internal_capacitance')):
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""" Timing for pips.
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Attributes
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----------
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delays : dicts of PvtCorner to IntristicDelay
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Intristic delay of pip.
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internal_capacitance : float
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Capacitance (microFarads) of pip (which is only seen if pip is used).
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drive_resistance : float
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Resistance of drive output pin (milliOhms).
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"""
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pass
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class Pip(namedtuple(
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'Pip',
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('name', 'net_to', 'net_from', 'can_invert', 'is_directional', 'is_pseudo',
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'is_pass_transistor', 'timing', 'backward_timing'))):
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""" Pip information.
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Attributes
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----------
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name : str
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Name of pip
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net_to : str
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Name of output tile wire when pip is unidirectional.
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net_from: str
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Name of input tile wire when pip is unidirectional.
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can_invert : bool
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Can this pip invert the signal.
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is_directional : bool
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True if this pip is unidirectional, False if this pip is
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unidirectional.
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is_pseudo : bool
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True if this pip is mark as a pseudo-pip.
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is_pass_transistor : bool
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True if this pip is non-isolating.
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timing : PipTiming
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Timing used when connecting net_from to net_to. This is the only
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timing used when a pip is unidirectional.
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May be None if timing information is not present in the database.
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backward_timing : PipTiming
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Timing used when connecting net_to to net_from. This is only used
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if the pip is bidirectional.
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May be None if timing information is not present in the database.
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"""
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pass
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class Site(namedtuple('Site', 'name prefix x y type site_pins')):
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""" Represents an instance of a site within a tile.
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Attributes
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----------
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name : str
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Name of site within tile, instance specific.
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prefix : str
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Prefix of site naming in Xilinx parlance.
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type : str
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What type of slice this instance presents.
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site_pins : list of SitePin
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Instaces of site pins within this site and tile. This is an tuple of
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SitePin tuples, and is specific to this instance of the site within
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the tile.
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"""
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class SitePin(namedtuple('SitePin', 'name wire timing')):
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""" Tuple representing a site pin within a tile.
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Sites are generic based on type, however sites are instanced
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within a tile 1 or more times. The SitePin contains both site type generic
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information and tile type specific information.
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Attributes
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----------
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name : str
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Site type specific name. This name is expected to be the same for
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all sites of the same type.
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wire : str
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Wire name within the tile. This name is site instance specific.
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timing : Either InPinTiming or OutPinTiming
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Timing of site pin. May be None if database lacks timing information.
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"""
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WireInfo = namedtuple('WireInfo', 'pips sites')
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# Conversion factor from database to internal units.
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RESISTANCE_FACTOR = 1
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CAPACITANCE_FACTOR = 1e3
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def get_pip_timing(pip_timing_json):
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""" Convert pip_timing_json JSON into PipTiming object.
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Returns
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-------
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If timing information is not present for this pip, returns None.
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If timing information is present, returns PipTiming. Some fields may be
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None if the pip type lacks that field.
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"""
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if pip_timing_json is None:
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return None
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delays = None
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if pip_timing_json.get('delay') is not None:
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delays = fast_slow_tuple_to_corners(pip_timing_json.get('delay'))
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in_cap = pip_timing_json.get('in_cap')
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if in_cap is not None:
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in_cap = float(in_cap) / CAPACITANCE_FACTOR
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else:
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in_cap = 0
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res = pip_timing_json.get('res')
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if res is not None:
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res = float(res) / RESISTANCE_FACTOR
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else:
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res = 0
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return PipTiming(
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delays=delays,
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drive_resistance=res,
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internal_capacitance=in_cap,
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)
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def get_site_pin_timing(site_pin_info):
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""" Convert site_pin_info JSON into InPinTiming or OutPinTiming object.
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Returns
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-------
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If timing information is not present for this site pin, returns None.
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If this is an output pin, returns OutPinTiming.
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If this is an input pin, returns InPinTiming.
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"""
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if isinstance(site_pin_info, str):
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return site_pin_info, None
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wire = site_pin_info['wire']
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if 'delay' not in site_pin_info:
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return None
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delays = fast_slow_tuple_to_corners(site_pin_info['delay'])
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if 'cap' in site_pin_info:
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assert 'res' not in site_pin_info
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return wire, InPinTiming(
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delays=delays,
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capacitance=float(site_pin_info['cap']) / CAPACITANCE_FACTOR,
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)
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else:
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assert 'res' in site_pin_info
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return wire, OutPinTiming(
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delays=delays,
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drive_resistance=float(site_pin_info['res']) / RESISTANCE_FACTOR,
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)
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def get_wires(wires):
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""" Converts database input to dictionary of tile wires to wire timing.
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Returns dictionary of tile wire name to RcElement or None. """
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if isinstance(wires, list):
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# Handle old database gracefully.
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return {wire: None for wire in wires}
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output = {}
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for wire, rc_json in wires.items():
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if rc_json is None:
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output[wire] = RcElement(
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resistance=0,
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capacitance=0,
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)
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else:
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output[wire] = RcElement(
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resistance=float(rc_json['res']) / RESISTANCE_FACTOR,
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capacitance=float(rc_json['cap']) / CAPACITANCE_FACTOR,
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)
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return output
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def is_pass_transistor(pip_json):
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""" Returns boolean if pip JSON indicates pip is a pass transistor.
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Always returns False if database lacks this information.
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"""
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if 'is_pass_transistor' in pip_json:
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return bool(int(pip_json['is_pass_transistor']))
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else:
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return False
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class Tile(object):
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""" Provides abstration of a tile in the database. """
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@ -49,17 +262,32 @@ class Tile(object):
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def yield_sites(sites):
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for site in sites:
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site_pins = []
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for name, site_pin_info in site['site_pins'].items():
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if site_pin_info is not None:
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wire, timing = get_site_pin_timing(site_pin_info)
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site_pins.append(
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SitePin(
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name=name,
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wire=wire,
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timing=timing,
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))
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else:
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site_pins.append(
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SitePin(
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name=name,
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wire=None,
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timing=None,
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))
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yield Site(
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name=site['name'],
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prefix=site['prefix'],
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type=site['type'],
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x=site['x_coord'],
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y=site['y_coord'],
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site_pins=tuple(
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SitePin(
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name=name,
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wire=wire,
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) for name, wire in site['site_pins'].items()))
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site_pins=site_pins,
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)
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def yield_pips(pips):
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for name, pip in pips.items():
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@ -70,12 +298,15 @@ class Tile(object):
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can_invert=bool(int(pip['can_invert'])),
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is_directional=bool(int(pip['is_directional'])),
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is_pseudo=bool(int(pip['is_pseudo'])),
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is_pass_transistor=is_pass_transistor(pip),
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timing=get_pip_timing(pip.get('src_to_dst')),
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backward_timing=get_pip_timing(pip.get('dst_to_src')),
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)
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with open(self.tile_dbs.tile_type) as f:
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tile_type = json.load(f)
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assert self.tilename_upper == tile_type['tile_type']
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self.wires = tile_type['wires']
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self.wires = get_wires(tile_type['wires'])
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self.sites = tuple(yield_sites(tile_type['sites']))
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self.pips = tuple(yield_pips(tile_type['pips']))
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|
|
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|
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@ -0,0 +1,550 @@
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""" Route timing delay definitions.
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Routing delay is formed from two parts in this model:
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- Intristic delay of the element
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- Capactive loading delay of the net
|
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Intristic delay is a time value (e.g. nanoseconds), does not vary based on
|
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routing fanout. It does vary based on the PVT (process, voltage, temperature)
|
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corner. PvtCorner and IntristicDelay objects are used to model intristic
|
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delay of elements.
|
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|
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Capactive loading is the elmore delay from the RC tree formed by interconnect.
|
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The RC tree is made up of 5 types of RC nodes:
|
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|
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|
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|Element type |Object |Intrinsic delays?|Output resistance?|Capacitance type |
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|----------------------|--------------|-----------------|------------------|--------------------|
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||||
|Site output pin |Outpin |Yes |Yes |N/A |
|
||||
|Buffered switch |Buffer |Yes |Yes |Internal capacitance|
|
||||
|Pass-transistor switch|PassTransistor|Yes |Yes |N/A |
|
||||
|Wire |Wire |No |Yes |Pi model |
|
||||
|Site input pin |Inpin |Yes |No |Input capacitance |
|
||||
|
||||
The elmore delay is the RC tree formed by these 5 components. Out pins and
|
||||
buffer switches are the roots of the elmore tree. Buffer switches
|
||||
and inpins are leafs of the elmore tree. Wires and pass-transistor switches are
|
||||
nodes in the tree. Wires share their capacitance upstream and downstream using
|
||||
a pi-model.
|
||||
|
||||
Example timing tree:
|
||||
|
||||
+------+
|
||||
|Outpin|
|
||||
+--+---+
|
||||
|
|
||||
|
|
||||
v
|
||||
+--+--+
|
||||
|Wire |
|
||||
+--+--+
|
||||
|
|
||||
+-----------------+
|
||||
| |
|
||||
+--+---+ +-------+------+
|
||||
|Buffer| |PassTransistor|
|
||||
+--+---+ +------+-------+
|
||||
| |
|
||||
v v
|
||||
+--+-+ +--+-+
|
||||
|Wire| |Wire|
|
||||
+--+-+ +--+-+
|
||||
| |
|
||||
v v
|
||||
+--+--+ +--+--+
|
||||
|Inpin| |Inpin|
|
||||
+-----+ +-----+
|
||||
|
||||
Note on units:
|
||||
|
||||
The timing model operates on the following types of units:
|
||||
- Time
|
||||
- Resistance
|
||||
- Capacitance
|
||||
|
||||
For a consistent unit set, the following equation must be satisfied:
|
||||
|
||||
1 Resistance unit * 1 Capacitance unit = 1 Time unit
|
||||
|
||||
The SI unit set would be:
|
||||
- Time = seconds
|
||||
- Resistance = Ohms
|
||||
- Capacitance = Farads
|
||||
|
||||
However as long as the scale factors are consistent, the model will work
|
||||
with other unit combinations. For example:
|
||||
- Time = nanoseconds (1e-9 seconds)
|
||||
- Resistance = milliOhms (1e-3 Ohms)
|
||||
- Capacitance = microFarads (1e-6 Farads)
|
||||
|
||||
(1e-3 * 1e-6) (Ohms * Farads) does equal (1e-9) seconds.
|
||||
|
||||
"""
|
||||
import enum
|
||||
from collections import namedtuple
|
||||
|
||||
|
||||
class PvtCorner(enum.Enum):
|
||||
""" Process/voltage/temperature corner definitions. """
|
||||
|
||||
# Corner where device operates with fastest intristic delays.
|
||||
FAST = "FAST"
|
||||
|
||||
# Corner where device operates with slowest intristic delays.
|
||||
SLOW = "SLOW"
|
||||
|
||||
|
||||
class IntristicDelay(namedtuple('IntristicDelay', 'min max')):
|
||||
""" An intristic delay instance.
|
||||
|
||||
Represents is the intristic delay through an element (e.g. a site pin or
|
||||
interconnect pip).
|
||||
|
||||
The intristic delay of an element is generally modelled at a particular
|
||||
"corner" of a design. The "corner" generally speaking is modelled over
|
||||
process, voltage and temperature PVT. The IntristicDelay object
|
||||
reperesents the minimum or maximum delay through all instances of the
|
||||
element at 1 corner.
|
||||
|
||||
Attributes
|
||||
----------
|
||||
|
||||
min : float
|
||||
Minimum instrinsic delay (nsec)
|
||||
|
||||
max : float
|
||||
Maximum instrinsic delay (nsec)
|
||||
"""
|
||||
|
||||
|
||||
class RcElement(namedtuple('RcElement', 'resistance capacitance')):
|
||||
""" One part of an RcNode, embedded within an RcTree.
|
||||
|
||||
Attributes
|
||||
----------
|
||||
|
||||
resistance : float
|
||||
Resistance of element
|
||||
|
||||
capacitance : float
|
||||
Capacitance of element
|
||||
|
||||
"""
|
||||
pass
|
||||
|
||||
|
||||
def fast_slow_tuple_to_corners(arr):
|
||||
""" Convert delay 4-tuple into two IntristicDelay objects.
|
||||
|
||||
Returns
|
||||
-------
|
||||
|
||||
corners : dict of PvtCorner to IntristicDelay
|
||||
Dictionary keys of FAST and SLOW, mapping to the instrinsic delay
|
||||
for each corner.
|
||||
|
||||
"""
|
||||
|
||||
fast_min, fast_max, slow_min, slow_max = map(float, arr)
|
||||
|
||||
return {
|
||||
PvtCorner.FAST: IntristicDelay(
|
||||
min=fast_min,
|
||||
max=fast_max,
|
||||
),
|
||||
PvtCorner.SLOW: IntristicDelay(
|
||||
min=slow_min,
|
||||
max=slow_max,
|
||||
),
|
||||
}
|
||||
|
||||
|
||||
class TimingNode(object):
|
||||
""" Base class for timing node models.
|
||||
"""
|
||||
|
||||
def get_intrinsic_delays(self):
|
||||
""" Returns Intristic delays (if any) timing node.
|
||||
|
||||
Returns
|
||||
-------
|
||||
|
||||
Dictionary of PvtCorner to Intristic. Is None if node has no intristic
|
||||
delay.
|
||||
"""
|
||||
|
||||
pass
|
||||
|
||||
def get_rc_delay(self):
|
||||
""" Return portion of net delay due to elmore (RC) delay at this node.
|
||||
|
||||
Must be called after propigate_delays has been called on the Outpin
|
||||
object of this tree.
|
||||
|
||||
"""
|
||||
pass
|
||||
|
||||
def get_downstream_cap(self):
|
||||
""" Returns downstream capacitance at this node.
|
||||
|
||||
Must be called after propigate_delays has been called on the Outpin
|
||||
object of this tree.
|
||||
|
||||
"""
|
||||
pass
|
||||
|
||||
def propigate_downstream_capacitance(self, math):
|
||||
""" Returns capacitance visible to parent of this node.
|
||||
|
||||
Must call propigate_downstream_capacitance on all children of this node.
|
||||
Should save downstream capacitance visible to this node's output
|
||||
(if any) to be returned in the get_downstream_cap method.
|
||||
"""
|
||||
pass
|
||||
|
||||
|
||||
class DownstreamNode(TimingNode):
|
||||
""" All non-root TimingNode's are DownstreamNode's.
|
||||
|
||||
"""
|
||||
|
||||
def propigate_delays(self, elements, math):
|
||||
""" Propigates upstream delay elements to children of the tree.
|
||||
|
||||
Must call propigated_delays on all children of this node, and add this
|
||||
node to elements.
|
||||
|
||||
Arguments
|
||||
---------
|
||||
elements : list of TimingNode's
|
||||
List of delay nodes between root of this tree and this node.
|
||||
math : MathModel
|
||||
Math model to use to compute delays
|
||||
"""
|
||||
pass
|
||||
|
||||
|
||||
class Outpin(TimingNode):
|
||||
""" Represents a site output pin.
|
||||
|
||||
Outpin object is the root of the timing tree. Once tree is built with
|
||||
set_sink_wire and Wire.add_child methods, propigate_delays should be
|
||||
invoked to estabilish model.
|
||||
|
||||
Arguments
|
||||
---------
|
||||
|
||||
resistance
|
||||
Drive resistance in elmore delay model
|
||||
delays
|
||||
Intristic delays on output pin.
|
||||
|
||||
"""
|
||||
|
||||
def __init__(self, resistance, delays):
|
||||
self.resistance = resistance
|
||||
self.delays = delays
|
||||
self.sink_wire = None
|
||||
|
||||
self.downstream_cap = None
|
||||
self.rc_delay = None
|
||||
|
||||
def set_sink_wire(self, wire):
|
||||
""" Sets sink wire for this output pin.
|
||||
|
||||
An output pin always sinks to exactly 1 wire.
|
||||
|
||||
This method must be called prior to calling propigate_delays method
|
||||
on this object.
|
||||
|
||||
Arguments
|
||||
---------
|
||||
wire : Wire object
|
||||
Sink wire for this output pin.
|
||||
|
||||
"""
|
||||
self.sink_wire = wire
|
||||
|
||||
def propigate_downstream_capacitance(self, math):
|
||||
assert self.sink_wire is not None
|
||||
self.downstream_cap = self.sink_wire.propigate_downstream_capacitance(
|
||||
math)
|
||||
self.rc_delay = math.multiply(self.downstream_cap, self.resistance)
|
||||
|
||||
def propigate_delays(self, math):
|
||||
""" Propigate delays throughout tree using specified math model.
|
||||
|
||||
Must be called after elmore tree is estabilished.
|
||||
|
||||
Arguments
|
||||
---------
|
||||
math : MathModel object
|
||||
Math model used when doing timing computations.
|
||||
|
||||
"""
|
||||
self.propigate_downstream_capacitance(math)
|
||||
self.sink_wire.propigate_delays([self], math)
|
||||
self.rc_delay = math.multiply(self.resistance, self.downstream_cap)
|
||||
|
||||
def get_intrinsic_delays(self):
|
||||
return self.delays
|
||||
|
||||
def get_rc_delay(self):
|
||||
assert self.rc_delay is not None
|
||||
return self.rc_delay
|
||||
|
||||
def get_downstream_cap(self):
|
||||
assert self.downstream_cap is not None
|
||||
return self.downstream_cap
|
||||
|
||||
|
||||
class Inpin(DownstreamNode):
|
||||
""" Represents a site input pin.
|
||||
|
||||
Represents leaf of timing model. Once model is connected and delays
|
||||
are propigate (by calling Outpin,propigated_delays), get_delays will
|
||||
correctly return the list of delay elements from the root to this leaf.
|
||||
|
||||
Arguments
|
||||
---------
|
||||
|
||||
capacitance
|
||||
Pin capacitance for input pin.
|
||||
delays
|
||||
Intristic delays on input pin.
|
||||
|
||||
"""
|
||||
|
||||
def __init__(self, capacitance, delays, name=None):
|
||||
self.capacitance = capacitance
|
||||
self.delays = delays
|
||||
self.propigated_delays = None
|
||||
self.name = name
|
||||
|
||||
def get_intrinsic_delays(self):
|
||||
return self.delays
|
||||
|
||||
def get_rc_delay(self):
|
||||
return None
|
||||
|
||||
def get_downstream_cap(self):
|
||||
return None
|
||||
|
||||
def propigate_downstream_capacitance(self, math):
|
||||
return self.capacitance
|
||||
|
||||
def propigate_delays(self, elements, math):
|
||||
self.propigated_delays = list(elements)
|
||||
|
||||
def get_delays(self):
|
||||
""" Return list of delay models that make up the delay for this pin.
|
||||
|
||||
The sum of all delay elements (both intristic and RC) is the net
|
||||
delay from the output pin to this input pin.
|
||||
|
||||
"""
|
||||
return self.propigated_delays + [self]
|
||||
|
||||
|
||||
class Wire(DownstreamNode):
|
||||
""" Represents a wire in the timing model.
|
||||
|
||||
Wires must be connected to an upstream driver model (Outpin, Buffer,
|
||||
PassTransistor objects) with set_sink_wire, and add_child must be called
|
||||
attaching output nodes (Buffer, PassTransistor, Inpin objects).
|
||||
|
||||
Arguments
|
||||
---------
|
||||
rc_elements : List of RcElement
|
||||
Resistance and capacitance of this wire.
|
||||
math : MathModel
|
||||
Math model used to compute lumped resistance and capacitance.
|
||||
|
||||
"""
|
||||
|
||||
def __init__(self, rc_elements, math):
|
||||
self.resistance = math.sum(elem.resistance for elem in rc_elements)
|
||||
self.capacitance = math.sum(elem.capacitance for elem in rc_elements)
|
||||
self.children = []
|
||||
|
||||
self.downstream_cap = None
|
||||
self.propigated_delays = None
|
||||
self.rc_delay = None
|
||||
|
||||
def add_child(self, child):
|
||||
""" Add a child node to this wire.
|
||||
|
||||
Call this method as needed prior to calling propigate_delays on the
|
||||
root Outpin object.
|
||||
|
||||
Arguments
|
||||
---------
|
||||
child : Buffer or PassTransistor or Inpin
|
||||
Adds child load to this wire.
|
||||
|
||||
"""
|
||||
self.children.append(child)
|
||||
|
||||
def propigate_downstream_capacitance(self, math):
|
||||
downstream_cap = math.sum(
|
||||
child.propigate_downstream_capacitance(math)
|
||||
for child in self.children)
|
||||
|
||||
# Pi-model is definied such that wire resistance only sees half of the
|
||||
# wire capacitance.
|
||||
self.downstream_cap = math.plus(
|
||||
math.divide(self.capacitance, 2), downstream_cap)
|
||||
|
||||
# Upstream seems all of the wires capacitance
|
||||
return math.plus(downstream_cap, self.capacitance)
|
||||
|
||||
def propigate_delays(self, elements, math):
|
||||
self.propigated_delays = list(elements)
|
||||
|
||||
for child in self.children:
|
||||
child.propigate_delays(self.propigated_delays + [self], math)
|
||||
|
||||
self.rc_delay = math.multiply(self.resistance, self.downstream_cap)
|
||||
|
||||
def get_intrinsic_delays(self):
|
||||
return None
|
||||
|
||||
def get_rc_delay(self):
|
||||
assert self.rc_delay is not None
|
||||
return self.rc_delay
|
||||
|
||||
def get_downstream_cap(self):
|
||||
assert self.downstream_cap is not None
|
||||
return self.downstream_cap
|
||||
|
||||
|
||||
class Buffer(DownstreamNode):
|
||||
""" Represents an isolating switch.
|
||||
|
||||
The internal_capacitance model is such that the upstream node only sees
|
||||
the capacitance of this node when the switch is enabled. Therefore, only
|
||||
active buffers should be included in the model.
|
||||
|
||||
Arguments
|
||||
---------
|
||||
internal_capacitance
|
||||
Capacitance seen by upstream node when this buffer is enabled.
|
||||
drive_resistance
|
||||
Driver resistance used for computing elmore delay.
|
||||
delays : Dictionary of PvtCorner to IntristicDelay
|
||||
Delay through switch
|
||||
|
||||
"""
|
||||
|
||||
def __init__(self, internal_capacitance, drive_resistance, delays):
|
||||
self.internal_capacitance = internal_capacitance
|
||||
self.drive_resistance = drive_resistance
|
||||
self.delays = delays
|
||||
|
||||
self.downstream_cap = None
|
||||
self.rc_delay = None
|
||||
|
||||
def set_sink_wire(self, wire):
|
||||
""" Sets sink wire for this output pin.
|
||||
|
||||
An output pin always sinks to exactly 1 wire.
|
||||
|
||||
This method must be called prior to calling propigate_delays method
|
||||
on the root Outpin object of this tree.
|
||||
|
||||
Arguments
|
||||
---------
|
||||
wire : Wire object
|
||||
Sink wire for this output pin.
|
||||
|
||||
"""
|
||||
self.sink_wire = wire
|
||||
|
||||
def propigate_downstream_capacitance(self, math):
|
||||
assert self.sink_wire is not None
|
||||
self.downstream_cap = self.sink_wire.propigate_downstream_capacitance(
|
||||
math)
|
||||
return self.internal_capacitance
|
||||
|
||||
def propigate_delays(self, elements, math):
|
||||
self.propigated_delays = list(elements)
|
||||
|
||||
assert self.sink_wire is not None
|
||||
self.sink_wire.propigate_delays(self.propigated_delays + [self], math)
|
||||
self.rc_delay = math.multiply(
|
||||
self.downstream_cap, self.drive_resistance)
|
||||
|
||||
def get_intrinsic_delays(self):
|
||||
return self.delays
|
||||
|
||||
def get_rc_delay(self):
|
||||
assert self.rc_delay is not None
|
||||
return self.rc_delay
|
||||
|
||||
def get_downstream_cap(self):
|
||||
assert self.downstream_cap is not None
|
||||
return self.downstream_cap
|
||||
|
||||
|
||||
class PassTransistor(DownstreamNode):
|
||||
""" Represents a non-isolating switch.
|
||||
|
||||
Arguments
|
||||
---------
|
||||
drive_resistance
|
||||
Driver resistance used for computing elmore delay.
|
||||
delays : Dictionary of PvtCorner to IntristicDelay
|
||||
Delay through switch.
|
||||
|
||||
"""
|
||||
|
||||
def __init__(self, drive_resistance, delays):
|
||||
self.drive_resistance = drive_resistance
|
||||
self.delays = delays
|
||||
self.sink_wire = None
|
||||
|
||||
self.downstream_cap = None
|
||||
self.rc_delay = None
|
||||
|
||||
def set_sink_wire(self, wire):
|
||||
""" Sets sink wire for this output pin.
|
||||
|
||||
An output pin always sinks to exactly 1 wire.
|
||||
|
||||
This method must be called prior to calling propigate_delays method
|
||||
on the root Outpin object of this tree.
|
||||
|
||||
Arguments
|
||||
---------
|
||||
wire : Wire object
|
||||
Sink wire for this output pin.
|
||||
|
||||
"""
|
||||
self.sink_wire = wire
|
||||
|
||||
def propigate_downstream_capacitance(self, math):
|
||||
assert self.sink_wire is not None
|
||||
self.downstream_cap = self.sink_wire.propigate_downstream_capacitance(
|
||||
math)
|
||||
|
||||
return self.downstream_cap
|
||||
|
||||
def propigate_delays(self, elements, math):
|
||||
self.propigated_delays = list(elements)
|
||||
|
||||
assert self.sink_wire is not None
|
||||
self.sink_wire.propigate_delays(self.propigated_delays + [self], math)
|
||||
self.rc_delay = math.multiply(
|
||||
self.downstream_cap, self.drive_resistance)
|
||||
|
||||
def get_intrinsic_delays(self):
|
||||
return self.delays
|
||||
|
||||
def get_rc_delay(self):
|
||||
assert self.rc_delay is not None
|
||||
return self.rc_delay
|
||||
|
||||
def get_downstream_cap(self):
|
||||
assert self.downstream_cap is not None
|
||||
return self.downstream_cap
|
||||
Loading…
Reference in New Issue