mirror of https://github.com/openXC7/prjxray.git
Merge pull request #493 from mithro/fuzzers2testxml
Make most of the fasm2frames.py tests pass again.
This commit is contained in:
Tomasz Michalak
GitHub
commit
fbeb731562
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@ -0,0 +1,96 @@
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CLBLM_L.SLICEM_X0.A5FF.ZINI 31_06
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CLBLM_L.SLICEM_X0.A5FF.ZRST 01_07
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CLBLM_L.SLICEM_X0.A5FFMUX.IN_A 30_09
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CLBLM_L.SLICEM_X0.A5FFMUX.IN_B 30_10
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CLBLM_L.SLICEM_X0.AFF.ZINI 31_03
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CLBLM_L.SLICEM_X0.AFF.ZRST 30_12
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CLBLM_L.SLICEM_X0.AFFMUX.AX !30_00 !30_02 !30_03 30_01
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CLBLM_L.SLICEM_X0.AFFMUX.CY !30_01 !30_03 30_00 30_02
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CLBLM_L.SLICEM_X0.AFFMUX.F7 !30_02 !30_03 30_00 30_01
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CLBLM_L.SLICEM_X0.AFFMUX.O5 !30_01 !30_02 30_00 30_03
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CLBLM_L.SLICEM_X0.AFFMUX.O6 !30_00 !30_01 !30_02 30_03
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CLBLM_L.SLICEM_X0.AFFMUX.XOR !30_00 !30_01 !30_03 30_02
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CLBLM_L.SLICEM_X0.ALUT.DI1MUX.AI 00_00
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CLBLM_L.SLICEM_X0.ALUT.INIT[00] 34_15
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CLBLM_L.SLICEM_X0.ALUT.INIT[01] 35_15
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CLBLM_L.SLICEM_X0.ALUT.INIT[02] 34_14
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CLBLM_L.SLICEM_X0.ALUT.INIT[03] 35_14
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CLBLM_L.SLICEM_X0.ALUT.INIT[04] 34_13
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CLBLM_L.SLICEM_X0.ALUT.INIT[05] 35_13
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CLBLM_L.SLICEM_X0.ALUT.INIT[06] 34_12
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CLBLM_L.SLICEM_X0.ALUT.INIT[07] 35_12
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CLBLM_L.SLICEM_X0.ALUT.INIT[08] 32_15
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CLBLM_L.SLICEM_X0.ALUT.INIT[09] 33_15
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CLBLM_L.SLICEM_X0.ALUT.INIT[10] 32_14
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CLBLM_L.SLICEM_X0.ALUT.INIT[11] 33_14
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CLBLM_L.SLICEM_X0.ALUT.INIT[12] 32_13
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CLBLM_L.SLICEM_X0.ALUT.INIT[13] 33_13
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CLBLM_L.SLICEM_X0.ALUT.INIT[14] 32_12
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CLBLM_L.SLICEM_X0.ALUT.INIT[15] 33_12
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CLBLM_L.SLICEM_X0.ALUT.INIT[16] 34_11
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CLBLM_L.SLICEM_X0.ALUT.INIT[17] 35_11
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CLBLM_L.SLICEM_X0.ALUT.INIT[18] 34_10
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CLBLM_L.SLICEM_X0.ALUT.INIT[19] 35_10
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CLBLM_L.SLICEM_X0.ALUT.INIT[20] 34_09
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CLBLM_L.SLICEM_X0.ALUT.INIT[21] 35_09
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CLBLM_L.SLICEM_X0.ALUT.INIT[22] 34_08
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CLBLM_L.SLICEM_X0.ALUT.INIT[23] 35_08
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CLBLM_L.SLICEM_X0.ALUT.INIT[24] 32_11
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CLBLM_L.SLICEM_X0.ALUT.INIT[25] 33_11
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CLBLM_L.SLICEM_X0.ALUT.INIT[26] 32_10
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CLBLM_L.SLICEM_X0.ALUT.INIT[27] 33_10
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CLBLM_L.SLICEM_X0.ALUT.INIT[28] 32_09
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CLBLM_L.SLICEM_X0.ALUT.INIT[29] 33_09
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CLBLM_L.SLICEM_X0.ALUT.INIT[30] 32_08
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CLBLM_L.SLICEM_X0.ALUT.INIT[31] 33_08
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CLBLM_L.SLICEM_X0.ALUT.INIT[32] 34_07
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CLBLM_L.SLICEM_X0.ALUT.INIT[33] 35_07
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CLBLM_L.SLICEM_X0.ALUT.INIT[34] 34_06
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CLBLM_L.SLICEM_X0.ALUT.INIT[35] 35_06
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CLBLM_L.SLICEM_X0.ALUT.INIT[36] 34_05
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CLBLM_L.SLICEM_X0.ALUT.INIT[37] 35_05
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CLBLM_L.SLICEM_X0.ALUT.INIT[38] 34_04
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CLBLM_L.SLICEM_X0.ALUT.INIT[39] 35_04
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CLBLM_L.SLICEM_X0.ALUT.INIT[40] 32_07
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CLBLM_L.SLICEM_X0.ALUT.INIT[41] 33_07
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CLBLM_L.SLICEM_X0.ALUT.INIT[42] 32_06
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CLBLM_L.SLICEM_X0.ALUT.INIT[43] 33_06
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CLBLM_L.SLICEM_X0.ALUT.INIT[44] 32_05
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CLBLM_L.SLICEM_X0.ALUT.INIT[45] 33_05
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CLBLM_L.SLICEM_X0.ALUT.INIT[46] 32_04
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CLBLM_L.SLICEM_X0.ALUT.INIT[47] 33_04
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CLBLM_L.SLICEM_X0.ALUT.INIT[48] 34_03
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CLBLM_L.SLICEM_X0.ALUT.INIT[49] 35_03
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CLBLM_L.SLICEM_X0.ALUT.INIT[50] 34_02
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CLBLM_L.SLICEM_X0.ALUT.INIT[51] 35_02
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CLBLM_L.SLICEM_X0.ALUT.INIT[52] 34_01
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CLBLM_L.SLICEM_X0.ALUT.INIT[53] 35_01
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CLBLM_L.SLICEM_X0.ALUT.INIT[54] 34_00
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CLBLM_L.SLICEM_X0.ALUT.INIT[55] 35_00
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CLBLM_L.SLICEM_X0.ALUT.INIT[56] 32_03
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CLBLM_L.SLICEM_X0.ALUT.INIT[57] 33_03
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CLBLM_L.SLICEM_X0.ALUT.INIT[58] 32_02
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CLBLM_L.SLICEM_X0.ALUT.INIT[59] 33_02
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CLBLM_L.SLICEM_X0.ALUT.INIT[60] 32_01
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CLBLM_L.SLICEM_X0.ALUT.INIT[61] 33_01
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CLBLM_L.SLICEM_X0.ALUT.INIT[62] 32_00
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CLBLM_L.SLICEM_X0.ALUT.INIT[63] 33_00
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CLBLM_L.SLICEM_X0.ALUT.RAM 31_16
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CLBLM_L.SLICEM_X0.ALUT.SMALL 00_04
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CLBLM_L.SLICEM_X0.ALUT.SRL 30_16
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CLBLM_L.SLICEM_X0.AOUTMUX.A5Q !30_06 !30_08 !30_11 30_07
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CLBLM_L.SLICEM_X0.AOUTMUX.CY !30_07 !30_11 30_06 30_08
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CLBLM_L.SLICEM_X0.AOUTMUX.F7 !30_08 !30_11 30_06 30_07
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CLBLM_L.SLICEM_X0.AOUTMUX.O5 !30_07 !30_08 30_06 30_11
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CLBLM_L.SLICEM_X0.AOUTMUX.O6 !30_06 !30_07 !30_08 30_11
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CLBLM_L.SLICEM_X0.AOUTMUX.XOR !30_06 !30_07 !30_11 30_08
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CLBLM_L.SLICEM_X0.CEUSEDMUX 01_39
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CLBLM_L.SLICEM_X0.FFSYNC 00_48
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CLBLM_L.SLICEM_X0.LATCH 30_32
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CLBLM_L.SLICEM_X0.PRECYINIT.C1 !30_13 !30_14 00_12
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CLBLM_L.SLICEM_X0.PRECYINIT.AX !00_12 !30_13 30_14
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CLBLM_L.SLICEM_X0.PRECYINIT.CIN !00_12 !30_14 30_13
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CLBLM_L.SLICEM_X0.SRUSEDMUX 01_35
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CLBLM_L.SLICEM_X0.WA7USED 00_40
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CLBLM_L.SLICEM_X0.WA8USED 01_27
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CLBLM_L.SLICEM_X0.WEMUX.CE 01_23
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@ -0,0 +1,2 @@
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HCLK_L.ENABLE_BUFFER.HCLK_CK_BUFHCLK8 00_14
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HCLK_L.HCLK_LEAF_CLK_B_BOTL5.HCLK_CK_BUFHCLK8 02_20 04_22
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@ -0,0 +1,13 @@
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INT_L.IMUX_L1.EE2END0 !22_09 !23_09 !25_09 18_08 24_09
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INT_L.IMUX_L2.EE2END1 !22_17 !23_17 !25_17 17_17 24_17
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INT_L.IMUX_L4.EE2END2 !22_33 !23_33 !25_33 17_33 24_33
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INT_L.IMUX_L7.EE2END3 !22_57 !23_57 !25_57 18_56 24_57
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INT_L.IMUX_L8.EL1END0 !22_02 18_03 23_02 24_02 25_02
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INT_L.IMUX_L11.EL1END1 !22_26 17_26 23_26 24_26 25_26
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INT_L.WW2BEG0.LOGIC_OUTS_L12 11_14 12_14
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INT_L.BYP_ALT0.EE2END0 !22_07 !23_07 !25_07 18_06 24_07
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INT_L.BYP_ALT1.EL1END1 !23_15 17_15 22_15 24_15 25_15
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INT_L.CLK_L1.GCLK_L_B11_WEST !00_29 00_27 01_25 01_26 01_29
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INT_L.CTRL_L1.ER1END2 !00_37 !01_36 !01_41 00_33 00_42
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INT_L.FAN_ALT7.BYP_BOUNCE0 !22_32 !23_32 !24_32 20_32 25_32
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INT_L.WW2BEG0.LOGIC_OUTS_L4 09_14 15_14
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@ -0,0 +1,2 @@
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{
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}
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@ -0,0 +1,2 @@
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{
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}
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@ -0,0 +1,2 @@
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{
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}
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@ -0,0 +1,58 @@
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{
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"CLBLM_L_X10Y102": {
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"bits": {
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"CLB_IO_CLK": {
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"baseaddr": "0x00020500",
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"frames": 36,
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"height": 2,
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"offset": 4,
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"words": 2
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}
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},
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"grid_x": 30,
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"grid_y": 49,
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"segment": "SEG_CLBLM_L_X10Y102",
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"segment_type": "clblm_l",
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"sites": {
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"SLICE_X12Y102": "SLICEM",
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"SLICE_X13Y102": "SLICEL"
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},
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"type": "CLBLM_L"
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},
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"HCLK_L_X31Y130": {
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"bits": {
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"CLB_IO_CLK": {
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"baseaddr": "0x00020500",
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"frames": 26,
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"height": 1,
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"offset": 50,
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"words": 1
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}
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},
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"grid_x": 31,
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"grid_y": 26,
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"segment": "SEG_HCLK_L_X31Y130",
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"segment_type": "hclk_l",
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"sites": {},
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"type": "HCLK_L"
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},
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"INT_L_X10Y102": {
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"bits": {
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"CLB_IO_CLK": {
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"baseaddr": "0x00020500",
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"frames": 28,
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"height": 2,
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"offset": 4,
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"words": 2
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}
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},
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"grid_x": 31,
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"grid_y": 49,
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"segment": "SEG_CLBLM_L_X10Y102",
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"segment_type": "clblm_l",
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"sites": {
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"TIEOFF_X11Y102": "TIEOFF"
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},
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"type": "INT_L"
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}
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}
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@ -1,23 +1,23 @@
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# Loosely based on
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# segprint -zd test_data/clb_ff/design.bits
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# ./utils/bits2fasm.py --db-root database/artix7 --canonical utils/test_data/ff_int/design.bits
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# FF as LDCE
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CLBLM_L_X10Y102.SLICEM_X0.AFF.DMUX AX
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CLBLM_L_X10Y102.SLICEM_X0.AFF.ZINI 1
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CLBLM_L_X10Y102.SLICEM_X0.AFF.ZRST 1
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CLBLM_L_X10Y102.SLICEM_X0.CEUSEDMUX 1
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# CLBLM_L_X10Y102.SLICEM_X0.SRUSEDMUX 1
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CLBLM_L_X10Y102.SLICEM_X0.SRUSEDMUX 1
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CLBLM_L_X10Y102.SLICEM_X0.AFFMUX.AX
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CLBLM_L_X10Y102.SLICEM_X0.AFF.ZINI
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CLBLM_L_X10Y102.SLICEM_X0.AFF.ZRST
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CLBLM_L_X10Y102.SLICEM_X0.CEUSEDMUX
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# CLBLM_L_X10Y102.SLICEM_X0.SRUSEDMUX
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CLBLM_L_X10Y102.SLICEM_X0.SRUSEDMUX
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# Note: a number of pseudo pips here
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# Omitted
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INT_L_X10Y102.BYP_ALT0 EE2END0
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INT_L_X10Y102.BYP_ALT1 EL1END1
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INT_L_X10Y102.CLK_L1 GCLK_L_B11_WEST
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INT_L_X10Y102.CTRL_L1 ER1END2
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INT_L_X10Y102.FAN_ALT7 BYP_BOUNCE0
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INT_L_X10Y102.WW2BEG0 LOGIC_OUTS_L4
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INT_L_X10Y102.BYP_ALT0.EE2END0
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INT_L_X10Y102.BYP_ALT1.EL1END1
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INT_L_X10Y102.CLK_L1.GCLK_L_B11_WEST
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INT_L_X10Y102.CTRL_L1.ER1END2
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INT_L_X10Y102.FAN_ALT7.BYP_BOUNCE0
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INT_L_X10Y102.WW2BEG0.LOGIC_OUTS_L4
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HCLK_L_X31Y130.ENABLE_BUFFER.HCLK_CK_BUFHCLK8 1
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HCLK_L_X31Y130.HCLK_LEAF_CLK_B_BOTL5 HCLK_CK_BUFHCLK8
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HCLK_L_X31Y130.ENABLE_BUFFER.HCLK_CK_BUFHCLK8
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HCLK_L_X31Y130.HCLK_LEAF_CLK_B_BOTL5.HCLK_CK_BUFHCLK8
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|
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@ -1,25 +1,25 @@
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# Loosely based on
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# segprint -zd test_data/clb_ff/design.bits
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# ./utils/bits2fasm.py --db-root database/artix7 --canonical utils/test_data/ff_int/design.bits
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# FF as LDCE
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CLBLM_L_X10Y102.SLICEM_X0.AFF.DMUX AX
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CLBLM_L_X10Y102.SLICEM_X0.AFF.ZINI 1
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CLBLM_L_X10Y102.SLICEM_X0.AFF.ZRST 1
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CLBLM_L_X10Y102.SLICEM_X0.CEUSEDMUX 1
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CLBLM_L_X10Y102.SLICEM_X0.SRUSEDMUX 1
|
||||
CLBLM_L_X10Y102.SLICEM_X0.AFFMUX.AX
|
||||
CLBLM_L_X10Y102.SLICEM_X0.AFF.ZINI
|
||||
CLBLM_L_X10Y102.SLICEM_X0.AFF.ZRST
|
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CLBLM_L_X10Y102.SLICEM_X0.CEUSEDMUX
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CLBLM_L_X10Y102.SLICEM_X0.SRUSEDMUX
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# Unused bits explicitly set to 0
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CLBLM_L_X10Y102.SLICEM_X0.FFSYNC 0
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CLBLM_L_X10Y102.SLICEM_X0.LATCH 0
|
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CLBLM_L_X10Y102.SLICEM_X0.FFSYNC = 0
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CLBLM_L_X10Y102.SLICEM_X0.LATCH = 0
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|
||||
# Note: a number of pseudo pips here
|
||||
# Omitted
|
||||
INT_L_X10Y102.BYP_ALT0 EE2END0
|
||||
INT_L_X10Y102.BYP_ALT1 EL1END1
|
||||
INT_L_X10Y102.CLK_L1 GCLK_L_B11_WEST
|
||||
INT_L_X10Y102.CTRL_L1 ER1END2
|
||||
INT_L_X10Y102.FAN_ALT7 BYP_BOUNCE0
|
||||
INT_L_X10Y102.WW2BEG0 LOGIC_OUTS_L4
|
||||
INT_L_X10Y102.BYP_ALT0.EE2END0
|
||||
INT_L_X10Y102.BYP_ALT1.EL1END1
|
||||
INT_L_X10Y102.CLK_L1.GCLK_L_B11_WEST
|
||||
INT_L_X10Y102.CTRL_L1.ER1END2
|
||||
INT_L_X10Y102.FAN_ALT7.BYP_BOUNCE0
|
||||
INT_L_X10Y102.WW2BEG0.LOGIC_OUTS_L4
|
||||
|
||||
HCLK_L_X31Y130.ENABLE_BUFFER.HCLK_CK_BUFHCLK8 1
|
||||
HCLK_L_X31Y130.HCLK_LEAF_CLK_B_BOTL5 HCLK_CK_BUFHCLK8
|
||||
HCLK_L_X31Y130.ENABLE_BUFFER.HCLK_CK_BUFHCLK8
|
||||
HCLK_L_X31Y130.HCLK_LEAF_CLK_B_BOTL5.HCLK_CK_BUFHCLK8
|
||||
|
||||
|
|
|
|||
|
|
@ -1,24 +1,24 @@
|
|||
# Loosely based on
|
||||
# segprint -zd test_data/clb_ff/design.bits
|
||||
# ./utils/bits2fasm.py --db-root database/artix7 --canonical utils/test_data/ff_int/design.bits
|
||||
|
||||
# FF as LDCE
|
||||
CLBLM_L_X10Y102.SLICEM_X0.AFF.DMUX AX
|
||||
CLBLM_L_X10Y102.SLICEM_X0.AFF.ZINI 1
|
||||
CLBLM_L_X10Y102.SLICEM_X0.AFF.ZRST 1
|
||||
CLBLM_L_X10Y102.SLICEM_X0.CEUSEDMUX 1
|
||||
CLBLM_L_X10Y102.SLICEM_X0.AFFMUX.AX
|
||||
CLBLM_L_X10Y102.SLICEM_X0.AFF.ZINI
|
||||
CLBLM_L_X10Y102.SLICEM_X0.AFF.ZRST
|
||||
CLBLM_L_X10Y102.SLICEM_X0.CEUSEDMUX
|
||||
# CLBLM_L_X10Y102.SLICEM_X0.SRUSEDMUX 1
|
||||
# Optional entry
|
||||
CLBLM_L_X10Y102.SLICEM_X0.SRUSEDMUX
|
||||
#CLBLM_L_X10Y102.SLICEM_X0.SRUSEDMUX
|
||||
|
||||
# Note: a number of pseudo pips here
|
||||
# Omitted
|
||||
INT_L_X10Y102.BYP_ALT0 EE2END0
|
||||
INT_L_X10Y102.BYP_ALT1 EL1END1
|
||||
INT_L_X10Y102.CLK_L1 GCLK_L_B11_WEST
|
||||
INT_L_X10Y102.CTRL_L1 ER1END2
|
||||
INT_L_X10Y102.FAN_ALT7 BYP_BOUNCE0
|
||||
INT_L_X10Y102.WW2BEG0 LOGIC_OUTS_L4
|
||||
INT_L_X10Y102.BYP_ALT0.EE2END0
|
||||
INT_L_X10Y102.BYP_ALT1.EL1END1
|
||||
INT_L_X10Y102.CLK_L1.GCLK_L_B11_WEST
|
||||
INT_L_X10Y102.CTRL_L1.ER1END2
|
||||
INT_L_X10Y102.FAN_ALT7.BYP_BOUNCE0
|
||||
INT_L_X10Y102.WW2BEG0.LOGIC_OUTS_L4
|
||||
|
||||
HCLK_L_X31Y130.ENABLE_BUFFER.HCLK_CK_BUFHCLK8 1
|
||||
HCLK_L_X31Y130.HCLK_LEAF_CLK_B_BOTL5 HCLK_CK_BUFHCLK8
|
||||
HCLK_L_X31Y130.ENABLE_BUFFER.HCLK_CK_BUFHCLK8
|
||||
HCLK_L_X31Y130.HCLK_LEAF_CLK_B_BOTL5.HCLK_CK_BUFHCLK8
|
||||
|
||||
|
|
|
|||
|
|
@ -1,15 +1,18 @@
|
|||
# LUT
|
||||
CLBLM_L_X10Y102.SLICEM_X0.ALUT.INIT[00] 1
|
||||
CLBLM_L_X10Y102.SLICEM_X0.ALUT.INIT[08] 1
|
||||
CLBLM_L_X10Y102.SLICEM_X0.ALUT.INIT[10] 1
|
||||
CLBLM_L_X10Y102.SLICEM_X0.ALUT.INIT[11] 1
|
||||
CLBLM_L_X10Y102.SLICEM_X0.ALUT.INIT[13] 1
|
||||
CLBLM_L_X10Y102.SLICEM_X0.ALUT.INIT[14] 1
|
||||
CLBLM_L_X10Y102.SLICEM_X0.ALUT.INIT[15] 1
|
||||
CLBLM_L_X10Y102.SLICEM_X0.ALUT.INIT[41] 1
|
||||
CLBLM_L_X10Y102.SLICEM_X0.ALUT.INIT[43] 1
|
||||
CLBLM_L_X10Y102.SLICEM_X0.ALUT.INIT[44] 1
|
||||
CLBLM_L_X10Y102.SLICEM_X0.ALUT.INIT[46] 1
|
||||
CLBLM_L_X10Y102.SLICEM_X0.ALUT.INIT[47] 1
|
||||
CLBLM_L_X10Y102.SLICEM_X0.ALUT.INIT[63] 1
|
||||
# Loosely based on
|
||||
# ./utils/bits2fasm.py --db-root database/artix7 --canonical utils/test_data/lut_int/design.bits
|
||||
|
||||
# LUT
|
||||
CLBLM_L_X10Y102.SLICEM_X0.ALUT.INIT[00]
|
||||
CLBLM_L_X10Y102.SLICEM_X0.ALUT.INIT[08]
|
||||
CLBLM_L_X10Y102.SLICEM_X0.ALUT.INIT[10]
|
||||
CLBLM_L_X10Y102.SLICEM_X0.ALUT.INIT[11]
|
||||
CLBLM_L_X10Y102.SLICEM_X0.ALUT.INIT[13]
|
||||
CLBLM_L_X10Y102.SLICEM_X0.ALUT.INIT[14]
|
||||
CLBLM_L_X10Y102.SLICEM_X0.ALUT.INIT[15]
|
||||
CLBLM_L_X10Y102.SLICEM_X0.ALUT.INIT[41]
|
||||
CLBLM_L_X10Y102.SLICEM_X0.ALUT.INIT[43]
|
||||
CLBLM_L_X10Y102.SLICEM_X0.ALUT.INIT[44]
|
||||
CLBLM_L_X10Y102.SLICEM_X0.ALUT.INIT[46]
|
||||
CLBLM_L_X10Y102.SLICEM_X0.ALUT.INIT[47]
|
||||
CLBLM_L_X10Y102.SLICEM_X0.ALUT.INIT[63]
|
||||
|
||||
|
|
|
|||
|
|
@ -1,35 +1,35 @@
|
|||
# Loosely based on
|
||||
# segprint -zd test_data/clb_lut/design.bits
|
||||
# ./utils/bits2fasm.py --db-root database/artix7 --canonical utils/test_data/lut_int/design.bits
|
||||
|
||||
# LUT
|
||||
CLBLM_L_X10Y102.SLICEM_X0.ALUT.INIT[00] 1
|
||||
CLBLM_L_X10Y102.SLICEM_X0.ALUT.INIT[08] 1
|
||||
CLBLM_L_X10Y102.SLICEM_X0.ALUT.INIT[10] 1
|
||||
CLBLM_L_X10Y102.SLICEM_X0.ALUT.INIT[11] 1
|
||||
CLBLM_L_X10Y102.SLICEM_X0.ALUT.INIT[13] 1
|
||||
CLBLM_L_X10Y102.SLICEM_X0.ALUT.INIT[14] 1
|
||||
CLBLM_L_X10Y102.SLICEM_X0.ALUT.INIT[15] 1
|
||||
CLBLM_L_X10Y102.SLICEM_X0.ALUT.INIT[41] 1
|
||||
CLBLM_L_X10Y102.SLICEM_X0.ALUT.INIT[43] 1
|
||||
CLBLM_L_X10Y102.SLICEM_X0.ALUT.INIT[44] 1
|
||||
CLBLM_L_X10Y102.SLICEM_X0.ALUT.INIT[46] 1
|
||||
CLBLM_L_X10Y102.SLICEM_X0.ALUT.INIT[47] 1
|
||||
CLBLM_L_X10Y102.SLICEM_X0.ALUT.INIT[63] 1
|
||||
CLBLM_L_X10Y102.SLICEM_X0.ALUT.INIT[00]
|
||||
CLBLM_L_X10Y102.SLICEM_X0.ALUT.INIT[08]
|
||||
CLBLM_L_X10Y102.SLICEM_X0.ALUT.INIT[10]
|
||||
CLBLM_L_X10Y102.SLICEM_X0.ALUT.INIT[11]
|
||||
CLBLM_L_X10Y102.SLICEM_X0.ALUT.INIT[13]
|
||||
CLBLM_L_X10Y102.SLICEM_X0.ALUT.INIT[14]
|
||||
CLBLM_L_X10Y102.SLICEM_X0.ALUT.INIT[15]
|
||||
CLBLM_L_X10Y102.SLICEM_X0.ALUT.INIT[41]
|
||||
CLBLM_L_X10Y102.SLICEM_X0.ALUT.INIT[43]
|
||||
CLBLM_L_X10Y102.SLICEM_X0.ALUT.INIT[44]
|
||||
CLBLM_L_X10Y102.SLICEM_X0.ALUT.INIT[46]
|
||||
CLBLM_L_X10Y102.SLICEM_X0.ALUT.INIT[47]
|
||||
CLBLM_L_X10Y102.SLICEM_X0.ALUT.INIT[63]
|
||||
|
||||
# din bus
|
||||
# din[0]
|
||||
INT_L_X10Y102.IMUX_L1 EE2END0
|
||||
INT_L_X10Y102.IMUX_L1.EE2END0
|
||||
# din[1]
|
||||
INT_L_X10Y102.IMUX_L2 EE2END1
|
||||
INT_L_X10Y102.IMUX_L2.EE2END1
|
||||
# din[2]
|
||||
INT_L_X10Y102.IMUX_L4 EE2END2
|
||||
INT_L_X10Y102.IMUX_L4.EE2END2
|
||||
# din[3]
|
||||
INT_L_X10Y102.IMUX_L7 EE2END3
|
||||
INT_L_X10Y102.IMUX_L7.EE2END3
|
||||
# din[4]
|
||||
INT_L_X10Y102.IMUX_L8 EL1END0
|
||||
INT_L_X10Y102.IMUX_L8.EL1END0
|
||||
# din[5]
|
||||
INT_L_X10Y102.IMUX_L11 EL1END1
|
||||
INT_L_X10Y102.IMUX_L11.EL1END1
|
||||
|
||||
# dout[0]
|
||||
INT_L_X10Y102.WW2BEG0 LOGIC_OUTS_L12
|
||||
INT_L_X10Y102.WW2BEG0.LOGIC_OUTS_L12
|
||||
|
||||
|
|
|
|||
|
|
@ -1,11 +1,17 @@
|
|||
#!/usr/bin/env python3
|
||||
# TODO: need better coverage for different tile types
|
||||
|
||||
from io import StringIO
|
||||
import os
|
||||
import os.path
|
||||
import re
|
||||
import unittest
|
||||
import tempfile
|
||||
|
||||
import prjxray
|
||||
import fasm2frames
|
||||
|
||||
import unittest
|
||||
from io import StringIO
|
||||
import re
|
||||
from textx.exceptions import TextXSyntaxError
|
||||
|
||||
|
||||
def frm2bits(txt):
|
||||
|
|
@ -49,105 +55,108 @@ def bitread2bits(txt):
|
|||
return bits_ref
|
||||
|
||||
|
||||
# FIXME: These functions are currently broken.
|
||||
@unittest.skip
|
||||
class TestStringMethods(unittest.TestCase):
|
||||
def filename_test_data(self, fname):
|
||||
return os.path.join(os.path.dirname(__file__), 'test_data', fname)
|
||||
|
||||
def get_test_data(self, fname):
|
||||
with open(self.filename_test_data(fname)) as f:
|
||||
return f.read()
|
||||
|
||||
def fasm2frames(self, fin_data, **kw):
|
||||
with tempfile.NamedTemporaryFile(suffix='.fasm') as fin:
|
||||
fin.write(fin_data.encode('utf-8'))
|
||||
fin.flush()
|
||||
|
||||
fout = StringIO()
|
||||
fasm2frames.run(
|
||||
self.filename_test_data('db'), fin.name, fout, **kw)
|
||||
|
||||
return fout.getvalue()
|
||||
|
||||
def test_lut(self):
|
||||
'''Simple smoke test on just the LUTs'''
|
||||
fout = StringIO()
|
||||
fasm2frames.run(open('test_data/lut.fasm', 'r'), fout)
|
||||
self.fasm2frames(self.get_test_data('lut.fasm'))
|
||||
|
||||
def bitread_frm_equals(self, frm_fn, bitread_fn):
|
||||
fout = StringIO()
|
||||
fasm2frames.run(open(frm_fn, 'r'), fout)
|
||||
fout = self.fasm2frames(self.get_test_data(frm_fn))
|
||||
|
||||
# Build a list of output used bits
|
||||
bits_out = frm2bits(fout.getvalue())
|
||||
bits_out = frm2bits(fout)
|
||||
|
||||
# Build a list of reference used bits
|
||||
bits_ref = bitread2bits(open(bitread_fn, 'r').read())
|
||||
bits_ref = bitread2bits(self.get_test_data(bitread_fn))
|
||||
|
||||
# Now check for equivilence vs reference design
|
||||
self.assertEquals(len(bits_ref), len(bits_out))
|
||||
self.assertEquals(bits_ref, bits_out)
|
||||
self.assertEqual(len(bits_ref), len(bits_out))
|
||||
self.assertEqual(bits_ref, bits_out)
|
||||
|
||||
def test_lut_int(self):
|
||||
self.bitread_frm_equals(
|
||||
'test_data/lut_int.fasm', 'test_data/lut_int/design.bits')
|
||||
self.bitread_frm_equals('lut_int.fasm', 'lut_int/design.bits')
|
||||
|
||||
def test_ff_int(self):
|
||||
self.bitread_frm_equals(
|
||||
'test_data/ff_int.fasm', 'test_data/ff_int/design.bits')
|
||||
self.bitread_frm_equals('ff_int.fasm', 'ff_int/design.bits')
|
||||
|
||||
@unittest.skip
|
||||
def test_ff_int_op1(self):
|
||||
'''Omitted key set to '''
|
||||
self.bitread_frm_equals(
|
||||
'test_data/ff_int_op1.fasm', 'test_data/ff_int/design.bits')
|
||||
self.bitread_frm_equals('ff_int_op1.fasm', 'ff_int/design.bits')
|
||||
|
||||
# Same check as above, but isolated test case
|
||||
def test_opkey_01_default(self):
|
||||
'''Optional key with binary omitted value should produce valid result'''
|
||||
fin = StringIO("CLBLM_L_X10Y102.SLICEM_X0.SRUSEDMUX")
|
||||
fout = StringIO()
|
||||
fasm2frames.run(fin, fout)
|
||||
self.fasm2frames("CLBLM_L_X10Y102.SLICEM_X0.SRUSEDMUX")
|
||||
|
||||
@unittest.skip
|
||||
def test_opkey_01_1(self):
|
||||
fin = StringIO("CLBLM_L_X10Y102.SLICEM_X0.SRUSEDMUX 1")
|
||||
fout = StringIO()
|
||||
fasm2frames.run(fin, fout)
|
||||
self.fasm2frames("CLBLM_L_X10Y102.SLICEM_X0.SRUSEDMUX 1")
|
||||
|
||||
@unittest.skip
|
||||
def test_opkey_enum(self):
|
||||
'''Optional key with enumerated value should produce syntax error'''
|
||||
# CLBLM_L.SLICEM_X0.AMUX.O6 !30_06 !30_07 !30_08 30_11
|
||||
fin = StringIO("CLBLM_L_X10Y102.SLICEM_X0.AMUX.O6")
|
||||
fout = StringIO()
|
||||
try:
|
||||
fasm2frames.run(fin, fout)
|
||||
# CLBLM_L.SLICEM_X0.AMUXFF.O6 !30_06 !30_07 !30_08 30_11
|
||||
self.fasm2frames("CLBLM_L_X10Y102.SLICEM_X0.AFFMUX.O6")
|
||||
self.fail("Expected syntax error")
|
||||
except fasm2frames.FASMSyntaxError:
|
||||
except TextXSyntaxError:
|
||||
pass
|
||||
|
||||
def test_ff_int_0s(self):
|
||||
'''Explicit 0 entries'''
|
||||
self.bitread_frm_equals(
|
||||
'test_data/ff_int_0s.fasm', 'test_data/ff_int/design.bits')
|
||||
self.bitread_frm_equals('ff_int_0s.fasm', 'ff_int/design.bits')
|
||||
|
||||
def test_badkey(self):
|
||||
'''Bad key should throw syntax error'''
|
||||
fin = StringIO("CLBLM_L_X10Y102.SLICEM_X0.SRUSEDMUX 2")
|
||||
fout = StringIO()
|
||||
try:
|
||||
fasm2frames.run(fin, fout)
|
||||
self.fasm2frames("CLBLM_L_X10Y102.SLICEM_X0.SRUSEDMUX 2")
|
||||
self.fail("Expected syntax error")
|
||||
except fasm2frames.FASMSyntaxError:
|
||||
except TextXSyntaxError:
|
||||
pass
|
||||
|
||||
@unittest.skip
|
||||
def test_dupkey(self):
|
||||
'''Duplicate key should throw syntax error'''
|
||||
fin = StringIO(
|
||||
"""\
|
||||
try:
|
||||
self.fasm2frames(
|
||||
"""\
|
||||
CLBLM_L_X10Y102.SLICEM_X0.SRUSEDMUX 0
|
||||
CLBLM_L_X10Y102.SLICEM_X0.SRUSEDMUX 1
|
||||
""")
|
||||
fout = StringIO()
|
||||
try:
|
||||
fasm2frames.run(fin, fout)
|
||||
self.fail("Expected syntax error")
|
||||
except fasm2frames.FASMSyntaxError:
|
||||
except TextXSyntaxError:
|
||||
pass
|
||||
|
||||
@unittest.skip
|
||||
def test_sparse(self):
|
||||
'''Verify sparse equivilent to normal encoding'''
|
||||
frm_fn = 'test_data/lut_int.fasm'
|
||||
'''Verify sparse equivalent to normal encoding'''
|
||||
frm_fn = 'lut_int.fasm'
|
||||
|
||||
fout_sparse = StringIO()
|
||||
fasm2frames.run(open(frm_fn, 'r'), fout_sparse, sparse=True)
|
||||
fout_sparse_txt = fout_sparse.getvalue()
|
||||
fout_sparse_txt = self.fasm2frames(
|
||||
self.get_test_data(frm_fn), sparse=True)
|
||||
bits_sparse = frm2bits(fout_sparse_txt)
|
||||
|
||||
fout_full = StringIO()
|
||||
fasm2frames.run(open(frm_fn, 'r'), fout_full, sparse=False)
|
||||
fout_full_txt = fout_full.getvalue()
|
||||
fout_full_txt = self.fasm2frames(
|
||||
self.get_test_data(frm_fn), sparse=False)
|
||||
bits_full = frm2bits(fout_full_txt)
|
||||
|
||||
# Now check for equivilence vs reference design
|
||||
|
|
|
|||
Loading…
Reference in New Issue