mirror of https://github.com/openXC7/prjxray.git
Add CLK_HROW config fuzzer, and adjust tilegrid definition.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
This commit is contained in:
parent
5e9cb60917
commit
00d9e1f314
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@ -84,7 +84,7 @@ def run(fn_in, fn_out, verbose=False):
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("bram_block/build/segbits_tilegrid.tdb", 128, 10),
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("bram_block/build/segbits_tilegrid.tdb", 128, 10),
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("clb/build/segbits_tilegrid.tdb", 36, 2),
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("clb/build/segbits_tilegrid.tdb", 36, 2),
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("dsp/build/segbits_tilegrid.tdb", 28, 10),
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("dsp/build/segbits_tilegrid.tdb", 28, 10),
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("clk_hrow/build/segbits_tilegrid.tdb", 26, 1),
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("clk_hrow/build/segbits_tilegrid.tdb", 30, 7),
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("clb_int/build/segbits_tilegrid.tdb", int_frames, int_words),
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("clb_int/build/segbits_tilegrid.tdb", int_frames, int_words),
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("iob_int/build/segbits_tilegrid.tdb", int_frames, int_words),
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("iob_int/build/segbits_tilegrid.tdb", int_frames, int_words),
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("bram_int/build/segbits_tilegrid.tdb", int_frames, int_words),
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("bram_int/build/segbits_tilegrid.tdb", int_frames, int_words),
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@ -1,4 +1,4 @@
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N ?= 5
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N ?= 5
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GENERATE_ARGS?="--oneval 1 --design params.csv --dword 0 --dframe 1A"
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GENERATE_ARGS?="--oneval 1 --design params.csv --dword 1 --dframe 1A"
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include ../fuzzaddr/common.mk
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include ../fuzzaddr/common.mk
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@ -0,0 +1,22 @@
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N ?= 15
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include ../fuzzer.mk
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database: build/segbits_clk_hrow.db
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build/segbits_clk_hrow.rdb: $(SPECIMENS_OK)
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${XRAY_SEGMATCH} -o build/segbits_clk_hrow.rdb $(addsuffix /segdata_clk_hrow_top_r.txt,$(SPECIMENS)) $(addsuffix /segdata_clk_hrow_bot_r.txt,$(SPECIMENS))
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build/segbits_clk_hrow.db: build/segbits_clk_hrow.rdb
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${XRAY_DBFIXUP} --db-root build --zero-db bits.dbf \
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--seg-fn-in build/segbits_clk_hrow.rdb \
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--seg-fn-out build/segbits_clk_hrow.db
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${XRAY_MASKMERGE} build/mask_clk_hrow.db $(addsuffix /segdata_clk_hrow_top_r.txt,$(SPECIMENS)) $(addsuffix /segdata_clk_hrow_bot_r.txt,$(SPECIMENS))
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pushdb: database
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${XRAY_MERGEDB} clk_hrow_bot_r build/segbits_clk_hrow.db
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${XRAY_MERGEDB} clk_hrow_top_r build/segbits_clk_hrow.db
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${XRAY_MERGEDB} mask_clk_hrow_bot_r build/mask_clk_hrow.db
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${XRAY_MERGEDB} mask_clk_hrow_top_r build/mask_clk_hrow.db
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.PHONY: database pushdb
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@ -0,0 +1,35 @@
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#!/usr/bin/env python3
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import json
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from prjxray.segmaker import Segmaker
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from prjxray import verilog
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def main():
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segmk = Segmaker("design.bits")
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print("Loading tags")
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with open('params.json') as f:
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params = json.load(f)
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for row in params:
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base_name = 'BUFHCE_X{}Y{}'.format(row['x'], row['y'])
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segmk.add_site_tag(row['site'], '{}.IN_USE'.format(base_name), row['IN_USE'])
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if not row['IN_USE']:
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continue
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segmk.add_site_tag(row['site'], '{}.INIT_OUT'.format(base_name), row['INIT_OUT'])
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# SYNC is a zero pattern
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for opt in ['ASYNC']:
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segmk.add_site_tag(row['site'], '{}.CE_TYPE.'.format(base_name) + opt, verilog.unquote(row['CE_TYPE']) == opt)
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segmk.compile()
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segmk.write()
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if __name__ == '__main__':
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main()
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@ -0,0 +1,17 @@
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proc run {} {
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create_project -force -part $::env(XRAY_PART) design design
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read_verilog top.v
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synth_design -top top
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set_property CFGBVS VCCO [current_design]
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
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place_design
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route_design
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write_checkpoint -force design.dcp
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write_bitstream -force design.bit
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}
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run
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@ -0,0 +1,76 @@
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import json
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import os
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import re
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import random
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random.seed(int(os.getenv("SEED"), 16))
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from prjxray import util
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from prjxray import verilog
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from prjxray.db import Database
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XY_RE = re.compile('^BUFHCE_X([0-9]+)Y([0-9]+)$')
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def gen_sites():
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db = Database(util.get_db_root())
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grid = db.grid()
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db = Database(util.get_db_root())
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grid = db.grid()
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for tile_name in sorted(grid.tiles()):
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loc = grid.loc_of_tilename(tile_name)
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gridinfo = grid.gridinfo_at_loc(loc)
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sites = []
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xs = []
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ys = []
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for site, site_type in gridinfo.sites.items():
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if site_type == 'BUFHCE':
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m = re.match(XY_RE, site)
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assert m, site
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x = int(m.group(1))
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y = int(m.group(2))
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xs.append(x)
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ys.append(y)
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sites.append((site, x, y))
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if sites:
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yield tile_name, min(xs), min(ys), sorted(sites)
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def main():
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print('''
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module top();
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''')
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params_list = []
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for tile_name, x_min, y_min, sites in gen_sites():
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for site, x, y in sites:
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params = {}
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params['tile'] = tile_name
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params['site'] = site
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params['x'] = x - x_min
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params['y'] = y - y_min
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params['IN_USE'] = random.randint(0, 1)
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if params['IN_USE']:
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params['INIT_OUT'] = random.randint(0, 1)
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params['CE_TYPE'] = verilog.quote(random.choice(('SYNC', 'ASYNC')))
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print('''
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(* KEEP, DONT_TOUCH, LOC = "{site}" *)
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BUFHCE #(
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.INIT_OUT({INIT_OUT}),
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.CE_TYPE({CE_TYPE})
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) buf_{site} ();
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'''.format(**params))
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params_list.append(params)
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print("endmodule")
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with open('params.json', 'w') as f:
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json.dump(params_list, f, indent=2)
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if __name__ == '__main__':
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main()
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@ -335,8 +335,9 @@ class Segmaker:
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Simplify names by simplifying like:
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Simplify names by simplifying like:
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-CLBLM_L => CLB
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-CLBLM_L => CLB
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-CENTER_INTER_R => CENTER_INTER
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-CENTER_INTER_R => CENTER_INTER
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-CLK_HROW_TOP_R => CLK_HROW
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'''
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'''
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tile_type_norm = re.sub("(LL|LM)?_[LR]$", "", tile_type)
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tile_type_norm = re.sub("(_TOP|_BOT|LL|LM)?_[LR]$", "", tile_type)
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# ignore dummy tiles (ex: VBRK)
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# ignore dummy tiles (ex: VBRK)
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if len(tiledata['bits']) == 0:
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if len(tiledata['bits']) == 0:
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@ -1,6 +1,5 @@
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#!/usr/bin/env python3
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#!/usr/bin/env python3
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import sys, re
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import os
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import os
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from prjxray import util
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from prjxray import util
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@ -73,6 +73,11 @@ case "$1" in
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hclk_r)
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hclk_r)
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sed < "$2" > "$tmp1" -e 's/^HCLK\./HCLK_R./' ;;
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sed < "$2" > "$tmp1" -e 's/^HCLK\./HCLK_R./' ;;
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clk_hrow_bot_r)
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sed < "$2" > "$tmp1" -e 's/^CLK_HROW\./CLK_HROW_BOT_R./' ;;
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clk_hrow_top_r)
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sed < "$2" > "$tmp1" -e 's/^CLK_HROW\./CLK_HROW_TOP_R./' ;;
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liob33)
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liob33)
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cp "$2" "$tmp1" ;;
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cp "$2" "$tmp1" ;;
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