diff --git a/fuzzers/005-tilegrid/add_tdb.py b/fuzzers/005-tilegrid/add_tdb.py
index 0f09e0e4..b27d5960 100644
--- a/fuzzers/005-tilegrid/add_tdb.py
+++ b/fuzzers/005-tilegrid/add_tdb.py
@@ -84,7 +84,7 @@ def run(fn_in, fn_out, verbose=False):
         ("bram_block/build/segbits_tilegrid.tdb", 128, 10),
         ("clb/build/segbits_tilegrid.tdb", 36, 2),
         ("dsp/build/segbits_tilegrid.tdb", 28, 10),
-        ("clk_hrow/build/segbits_tilegrid.tdb", 26, 1),
+        ("clk_hrow/build/segbits_tilegrid.tdb", 30, 7),
         ("clb_int/build/segbits_tilegrid.tdb", int_frames, int_words),
         ("iob_int/build/segbits_tilegrid.tdb", int_frames, int_words),
         ("bram_int/build/segbits_tilegrid.tdb", int_frames, int_words),
diff --git a/fuzzers/005-tilegrid/clk_hrow/Makefile b/fuzzers/005-tilegrid/clk_hrow/Makefile
index 24713793..17297e84 100644
--- a/fuzzers/005-tilegrid/clk_hrow/Makefile
+++ b/fuzzers/005-tilegrid/clk_hrow/Makefile
@@ -1,4 +1,4 @@
 N ?= 5
-GENERATE_ARGS?="--oneval 1 --design params.csv --dword 0 --dframe 1A"
+GENERATE_ARGS?="--oneval 1 --design params.csv --dword 1 --dframe 1A"
 include ../fuzzaddr/common.mk
 
diff --git a/fuzzers/040-clk_hrow_config/Makefile b/fuzzers/040-clk_hrow_config/Makefile
new file mode 100644
index 00000000..c815d293
--- /dev/null
+++ b/fuzzers/040-clk_hrow_config/Makefile
@@ -0,0 +1,22 @@
+N ?= 15
+
+include ../fuzzer.mk
+
+database: build/segbits_clk_hrow.db
+
+build/segbits_clk_hrow.rdb: $(SPECIMENS_OK)
+	${XRAY_SEGMATCH} -o build/segbits_clk_hrow.rdb $(addsuffix /segdata_clk_hrow_top_r.txt,$(SPECIMENS)) $(addsuffix /segdata_clk_hrow_bot_r.txt,$(SPECIMENS))
+
+build/segbits_clk_hrow.db: build/segbits_clk_hrow.rdb
+	${XRAY_DBFIXUP} --db-root build --zero-db bits.dbf \
+		--seg-fn-in build/segbits_clk_hrow.rdb \
+		--seg-fn-out build/segbits_clk_hrow.db
+	${XRAY_MASKMERGE} build/mask_clk_hrow.db $(addsuffix /segdata_clk_hrow_top_r.txt,$(SPECIMENS)) $(addsuffix /segdata_clk_hrow_bot_r.txt,$(SPECIMENS))
+
+pushdb: database
+	${XRAY_MERGEDB} clk_hrow_bot_r build/segbits_clk_hrow.db
+	${XRAY_MERGEDB} clk_hrow_top_r build/segbits_clk_hrow.db
+	${XRAY_MERGEDB} mask_clk_hrow_bot_r build/mask_clk_hrow.db
+	${XRAY_MERGEDB} mask_clk_hrow_top_r build/mask_clk_hrow.db
+
+.PHONY: database pushdb
diff --git a/fuzzers/040-clk_hrow_config/bits.dbf b/fuzzers/040-clk_hrow_config/bits.dbf
new file mode 100644
index 00000000..e69de29b
diff --git a/fuzzers/040-clk_hrow_config/generate.py b/fuzzers/040-clk_hrow_config/generate.py
new file mode 100644
index 00000000..d3a07f0a
--- /dev/null
+++ b/fuzzers/040-clk_hrow_config/generate.py
@@ -0,0 +1,35 @@
+#!/usr/bin/env python3
+
+import json
+
+from prjxray.segmaker import Segmaker
+from prjxray import verilog
+
+
+def main():
+    segmk = Segmaker("design.bits")
+
+    print("Loading tags")
+    with open('params.json') as f:
+        params = json.load(f)
+
+    for row in params:
+        base_name = 'BUFHCE_X{}Y{}'.format(row['x'], row['y'])
+
+
+        segmk.add_site_tag(row['site'], '{}.IN_USE'.format(base_name), row['IN_USE'])
+        if not row['IN_USE']:
+            continue
+
+        segmk.add_site_tag(row['site'], '{}.INIT_OUT'.format(base_name), row['INIT_OUT'])
+
+        # SYNC is a zero pattern
+        for opt in ['ASYNC']:
+            segmk.add_site_tag(row['site'], '{}.CE_TYPE.'.format(base_name) + opt, verilog.unquote(row['CE_TYPE']) == opt)
+
+    segmk.compile()
+    segmk.write()
+
+
+if __name__ == '__main__':
+    main()
diff --git a/fuzzers/040-clk_hrow_config/generate.tcl b/fuzzers/040-clk_hrow_config/generate.tcl
new file mode 100644
index 00000000..3044e100
--- /dev/null
+++ b/fuzzers/040-clk_hrow_config/generate.tcl
@@ -0,0 +1,17 @@
+proc run {} {
+    create_project -force -part $::env(XRAY_PART) design design
+    read_verilog top.v
+    synth_design -top top
+
+    set_property CFGBVS VCCO [current_design]
+    set_property CONFIG_VOLTAGE 3.3 [current_design]
+    set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
+
+    place_design
+    route_design
+
+    write_checkpoint -force design.dcp
+    write_bitstream -force design.bit
+}
+
+run
diff --git a/fuzzers/040-clk_hrow_config/top.py b/fuzzers/040-clk_hrow_config/top.py
new file mode 100644
index 00000000..b19e936f
--- /dev/null
+++ b/fuzzers/040-clk_hrow_config/top.py
@@ -0,0 +1,76 @@
+import json
+import os
+import re
+import random
+random.seed(int(os.getenv("SEED"), 16))
+from prjxray import util
+from prjxray import verilog
+from prjxray.db import Database
+
+XY_RE = re.compile('^BUFHCE_X([0-9]+)Y([0-9]+)$')
+
+def gen_sites():
+    db = Database(util.get_db_root())
+    grid = db.grid()
+    db = Database(util.get_db_root())
+    grid = db.grid()
+    for tile_name in sorted(grid.tiles()):
+        loc = grid.loc_of_tilename(tile_name)
+        gridinfo = grid.gridinfo_at_loc(loc)
+        sites = []
+
+        xs = []
+        ys = []
+        for site, site_type in gridinfo.sites.items():
+            if site_type == 'BUFHCE':
+                m = re.match(XY_RE, site)
+                assert m, site
+                x = int(m.group(1))
+                y = int(m.group(2))
+                xs.append(x)
+                ys.append(y)
+
+                sites.append((site, x, y))
+
+        if sites:
+            yield tile_name, min(xs), min(ys), sorted(sites)
+
+
+def main():
+    print('''
+module top();
+    ''')
+
+    params_list = []
+    for tile_name, x_min, y_min, sites in gen_sites():
+
+        for site, x, y in sites:
+            params = {}
+            params['tile'] = tile_name
+            params['site'] = site
+            params['x'] = x - x_min
+            params['y'] = y - y_min
+            params['IN_USE'] = random.randint(0, 1)
+
+            if params['IN_USE']:
+                params['INIT_OUT'] = random.randint(0, 1)
+                params['CE_TYPE'] = verilog.quote(random.choice(('SYNC', 'ASYNC')))
+
+                print('''
+    (* KEEP, DONT_TOUCH, LOC = "{site}" *)
+    BUFHCE #(
+        .INIT_OUT({INIT_OUT}),
+        .CE_TYPE({CE_TYPE})
+        ) buf_{site} ();
+                    '''.format(**params))
+
+            params_list.append(params)
+
+    print("endmodule")
+
+    with open('params.json', 'w') as f:
+        json.dump(params_list, f, indent=2)
+
+
+if __name__ == '__main__':
+    main()
diff --git a/prjxray/segmaker.py b/prjxray/segmaker.py
index 5fccbf57..559556a1 100644
--- a/prjxray/segmaker.py
+++ b/prjxray/segmaker.py
@@ -335,8 +335,9 @@ class Segmaker:
             Simplify names by simplifying like:
             -CLBLM_L => CLB
             -CENTER_INTER_R => CENTER_INTER
+            -CLK_HROW_TOP_R => CLK_HROW
             '''
-            tile_type_norm = re.sub("(LL|LM)?_[LR]$", "", tile_type)
+            tile_type_norm = re.sub("(_TOP|_BOT|LL|LM)?_[LR]$", "", tile_type)
 
             # ignore dummy tiles (ex: VBRK)
             if len(tiledata['bits']) == 0:
diff --git a/utils/mergedb.py b/utils/mergedb.py
index 70088dda..af9b5e4e 100755
--- a/utils/mergedb.py
+++ b/utils/mergedb.py
@@ -1,6 +1,5 @@
 #!/usr/bin/env python3
 
-import sys, re
 import os
 from prjxray import util
 
diff --git a/utils/mergedb.sh b/utils/mergedb.sh
index 93011e51..2f955c88 100755
--- a/utils/mergedb.sh
+++ b/utils/mergedb.sh
@@ -73,6 +73,11 @@ case "$1" in
 	hclk_r)
 		sed < "$2" > "$tmp1" -e 's/^HCLK\./HCLK_R./' ;;
 
+	clk_hrow_bot_r)
+		sed < "$2" > "$tmp1" -e 's/^CLK_HROW\./CLK_HROW_BOT_R./' ;;
+	clk_hrow_top_r)
+		sed < "$2" > "$tmp1" -e 's/^CLK_HROW\./CLK_HROW_TOP_R./' ;;
+
 	liob33)
 		cp "$2" "$tmp1" ;;