2019-01-11 05:51:25 +01:00
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# Loosely based on
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# ./utils/bits2fasm.py --db-root database/artix7 --canonical utils/test_data/lut_int/design.bits
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2018-01-17 23:39:37 +01:00
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# LUT
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2019-01-11 05:51:25 +01:00
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CLBLM_L_X10Y102.SLICEM_X0.ALUT.INIT[00]
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CLBLM_L_X10Y102.SLICEM_X0.ALUT.INIT[08]
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CLBLM_L_X10Y102.SLICEM_X0.ALUT.INIT[10]
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CLBLM_L_X10Y102.SLICEM_X0.ALUT.INIT[11]
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CLBLM_L_X10Y102.SLICEM_X0.ALUT.INIT[13]
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CLBLM_L_X10Y102.SLICEM_X0.ALUT.INIT[14]
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CLBLM_L_X10Y102.SLICEM_X0.ALUT.INIT[15]
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CLBLM_L_X10Y102.SLICEM_X0.ALUT.INIT[41]
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CLBLM_L_X10Y102.SLICEM_X0.ALUT.INIT[43]
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CLBLM_L_X10Y102.SLICEM_X0.ALUT.INIT[44]
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CLBLM_L_X10Y102.SLICEM_X0.ALUT.INIT[46]
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CLBLM_L_X10Y102.SLICEM_X0.ALUT.INIT[47]
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CLBLM_L_X10Y102.SLICEM_X0.ALUT.INIT[63]
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2018-01-17 23:39:37 +01:00
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