mirror of https://github.com/openXC7/prjxray.git
26 lines
319 B
Verilog
26 lines
319 B
Verilog
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module top
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(
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(* clock_buffer_type = "NONE" *)
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input wire CLK,
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input wire CE,
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input wire D,
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input wire [4:0] A,
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output wire Q
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);
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(* LOC="SLICE_X2Y0", BEL="A6LUT" *)
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SRLC32E #
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(
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.INIT(32'hF0F01030)
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)
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srl_a
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(
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.CLK (CLK),
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.CE (CE),
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.D (D),
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.A (A),
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.Q (Q)
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);
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endmodule
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