mirror of https://github.com/openXC7/prjxray.git
31 lines
1.3 KiB
Markdown
31 lines
1.3 KiB
Markdown
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# Minitests for IDELAY
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## 1. basys3_idelay_ext
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A design for Basys3 board.
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### Description
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This test generates a 50MHz square wave on an output pin which is then fed back to the FPGA IDELAY bel through another input pin. The delayed signal is then routed to yet another output pin which allows it to be compared with the input signal using an oscilloscope. The IDELAY is calibrated using 100MHz clock hence delays from 0 to 5ns can be achieved.
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The switch `SW0` acts as reset. The switch `SW1` allows to change the delay value. One toggle of that switch increases the delay counter by one.
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The `LED0` blinks continuously. The `LED1` indicates that the calibration of IDELAY has been completed (the `RDY` signal from IDELAYCTRL bel). Leds `LED11` through `LED15` indicate current delay setting (the `CNTVALUEOUT` of IDELAY bel).
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### Physical loopback
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Consider the `JXADC` connector on the Basys3 board as seen when looking at the board edge:
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```
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-- -- -- -- -- --
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| 6| 5| 4| 3| 2| 1|
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-- -- -- -- -- --
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|12|11|10| 9| 8| 7|
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-- -- -- -- -- --
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```
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- Pin1 - Signal output. Connect to CH1 of the oscilloscope.
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- Pin2 - Delayed signal output. Connect to CH2 of the oscilloscope.
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- Pin7 - Delay signal input, connect to Pin8.
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- Pin8 - Signal output. Connect to Pin7.
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**The oscilloscope must have bandwidth of at least 100MHz.**
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