mirror of https://github.com/openXC7/prjxray.git
IDELAY minitest with variable (preloaded) delay value.
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
This commit is contained in:
Maciej Kurc
parent
1f41082937
commit
d3891f41d3
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@ -0,0 +1,43 @@
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SYNTH ?= vivado
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YOSYS = $(XRAY_DIR)/third_party/yosys/yosys
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PART = xc7a35tcsg324-1
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VERILOG_FILES = $(wildcard *.v)
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BIT_FILES = $(VERILOG_FILES:.v=.bit)
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all: $(BIT_FILES)
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clean:
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@find . -name "build-par.*" | xargs rm -rf
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@find . -name "build-syn.*" | xargs rm -rf
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@rm -f *.edif
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@rm -f *.bit
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@rm -f *.bin
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@rm -f *.log
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@rm -f *.dcp
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help:
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@echo "Usage: make all [SYNTH=<vivado/yosys>]"
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.PHONY: all clean help
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$(YOSYS):
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cd $(XRAY_DIR)/third_party/yosys && make config-gcc && make -j$(shell nproc)
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ifeq ($(SYNTH), yosys)
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%.edif: %.v $(YOSYS)
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$(YOSYS) -p "read_verilog $< ; synth_xilinx -flatten -nosrl; write_edif -pvector bra -attrprop $@" -l $@.log
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else ifeq ($(SYNTH), vivado)
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%.edif: %.v tcl/syn.tcl basys3.xdc
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mkdir -p build-syn.$(basename $@)
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cd build-syn.$(basename $@) && env PROJECT_NAME=$(basename $@) $(XRAY_VIVADO) -mode batch -source ../tcl/syn.tcl -nojournal -log ../$@.log
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rm -rf *.backup.log
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endif
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%.bit: %.edif tcl/par.tcl basys3.xdc
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mkdir -p build-par.$(basename $@)
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cd build-par.$(basename $@) && env PROJECT_NAME=$(basename $@) $(XRAY_VIVADO) -mode batch -source ../tcl/par.tcl -nojournal -log ../$@.log
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rm -rf *.backup.log
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@ -0,0 +1,31 @@
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# Minitests for IDELAY
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## 1. basys3_idelay_ext
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A design for Basys3 board.
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### Description
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This test generates a 50MHz square wave on an output pin which is then fed back to the FPGA IDELAY bel through another input pin. The delayed signal is then routed to yet another output pin which allows it to be compared with the input signal using an oscilloscope. The IDELAY is calibrated using 100MHz clock hence delays from 0 to 5ns can be achieved.
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The switch `SW0` acts as reset. The switch `SW1` allows to change the delay value. One toggle of that switch increases the delay counter by one.
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The `LED0` blinks continuously. The `LED1` indicates that the calibration of IDELAY has been completed (the `RDY` signal from IDELAYCTRL bel). Leds `LED11` through `LED15` indicate current delay setting (the `CNTVALUEOUT` of IDELAY bel).
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### Physical loopback
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Consider the `JXADC` connector on the Basys3 board as seen when looking at the board edge:
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```
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-- -- -- -- -- --
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| 6| 5| 4| 3| 2| 1|
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-- -- -- -- -- --
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|12|11|10| 9| 8| 7|
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-- -- -- -- -- --
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```
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- Pin1 - Signal output. Connect to CH1 of the oscilloscope.
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- Pin2 - Delayed signal output. Connect to CH2 of the oscilloscope.
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- Pin7 - Delay signal input, connect to Pin8.
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- Pin8 - Signal output. Connect to Pin7.
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**The oscilloscope must have bandwidth of at least 100MHz.**
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@ -0,0 +1,82 @@
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create_clock -period 10.000 -name clk [get_ports clk]
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set_property PACKAGE_PIN W5 [get_ports clk]
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set_property PACKAGE_PIN B18 [get_ports rx]
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set_property PACKAGE_PIN A18 [get_ports tx]
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set_property PACKAGE_PIN V17 [get_ports sw[ 0]]
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set_property PACKAGE_PIN V16 [get_ports sw[ 1]]
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set_property PACKAGE_PIN W16 [get_ports sw[ 2]]
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set_property PACKAGE_PIN W17 [get_ports sw[ 3]]
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set_property PACKAGE_PIN W15 [get_ports sw[ 4]]
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set_property PACKAGE_PIN V15 [get_ports sw[ 5]]
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set_property PACKAGE_PIN W14 [get_ports sw[ 6]]
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set_property PACKAGE_PIN W13 [get_ports sw[ 7]]
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set_property PACKAGE_PIN V2 [get_ports sw[ 8]]
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set_property PACKAGE_PIN T3 [get_ports sw[ 9]]
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set_property PACKAGE_PIN T2 [get_ports sw[10]]
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set_property PACKAGE_PIN R3 [get_ports sw[11]]
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set_property PACKAGE_PIN W2 [get_ports sw[12]]
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set_property PACKAGE_PIN U1 [get_ports sw[13]]
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set_property PACKAGE_PIN T1 [get_ports sw[14]]
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set_property PACKAGE_PIN R2 [get_ports sw[15]]
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set_property PACKAGE_PIN U16 [get_ports led[ 0]]
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set_property PACKAGE_PIN E19 [get_ports led[ 1]]
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set_property PACKAGE_PIN U19 [get_ports led[ 2]]
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set_property PACKAGE_PIN V19 [get_ports led[ 3]]
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set_property PACKAGE_PIN W18 [get_ports led[ 4]]
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set_property PACKAGE_PIN U15 [get_ports led[ 5]]
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set_property PACKAGE_PIN U14 [get_ports led[ 6]]
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set_property PACKAGE_PIN V14 [get_ports led[ 7]]
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set_property PACKAGE_PIN V13 [get_ports led[ 8]]
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set_property PACKAGE_PIN V3 [get_ports led[ 9]]
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set_property PACKAGE_PIN W3 [get_ports led[10]]
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set_property PACKAGE_PIN U3 [get_ports led[11]]
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set_property PACKAGE_PIN P3 [get_ports led[12]]
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set_property PACKAGE_PIN N3 [get_ports led[13]]
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set_property PACKAGE_PIN P1 [get_ports led[14]]
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set_property PACKAGE_PIN L1 [get_ports led[15]]
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set_property PACKAGE_PIN J1 [get_ports ja1]
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set_property PACKAGE_PIN L2 [get_ports ja2]
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set_property PACKAGE_PIN J2 [get_ports ja3]
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set_property PACKAGE_PIN G2 [get_ports ja4]
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set_property PACKAGE_PIN H1 [get_ports ja7]
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set_property PACKAGE_PIN K2 [get_ports ja8]
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set_property PACKAGE_PIN H2 [get_ports ja9]
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set_property PACKAGE_PIN G3 [get_ports ja10]
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set_property PACKAGE_PIN A14 [get_ports jb1]
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set_property PACKAGE_PIN A16 [get_ports jb2]
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set_property PACKAGE_PIN B15 [get_ports jb3]
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set_property PACKAGE_PIN B16 [get_ports jb4]
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set_property PACKAGE_PIN A15 [get_ports jb7]
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set_property PACKAGE_PIN A17 [get_ports jb8]
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set_property PACKAGE_PIN C15 [get_ports jb9]
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set_property PACKAGE_PIN C16 [get_ports jb10]
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set_property PACKAGE_PIN K17 [get_ports jc1]
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set_property PACKAGE_PIN M18 [get_ports jc2]
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set_property PACKAGE_PIN N17 [get_ports jc3]
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set_property PACKAGE_PIN P18 [get_ports jc4]
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set_property PACKAGE_PIN L17 [get_ports jc7]
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set_property PACKAGE_PIN M19 [get_ports jc8]
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set_property PACKAGE_PIN P17 [get_ports jc9]
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set_property PACKAGE_PIN R18 [get_ports jc10]
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set_property PACKAGE_PIN J3 [get_ports xadc1_p]
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set_property PACKAGE_PIN L3 [get_ports xadc2_p]
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#set_property PACKAGE_PIN M2 [get_ports xadc3_p]
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#set_property PACKAGE_PIN N2 [get_ports xadc4_p]
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set_property PACKAGE_PIN K3 [get_ports xadc1_n]
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set_property PACKAGE_PIN M3 [get_ports xadc2_n]
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#set_property PACKAGE_PIN M1 [get_ports xadc3_n]
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#set_property PACKAGE_PIN N1 [get_ports xadc4_n]
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foreach port [get_ports] {
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set_property IOSTANDARD LVTTL $port
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set_property SLEW FAST $port
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set_property DRIVE 24 $port
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}
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@ -0,0 +1,188 @@
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`include "src/idelay_calibrator.v"
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`default_nettype none
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// ============================================================================
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module top
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(
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input wire clk,
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input wire rx,
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output wire tx,
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input wire [15:0] sw,
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output wire [15:0] led,
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output wire ja1,
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output wire ja2,
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output wire ja3,
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output wire ja4,
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input wire ja7,
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input wire ja8,
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input wire ja9,
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input wire ja10,
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output wire jb1,
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output wire jb2,
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output wire jb3,
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output wire jb4,
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input wire jb7,
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input wire jb8,
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input wire jb9,
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input wire jb10,
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output wire jc1,
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output wire jc2,
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output wire jc3,
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output wire jc4,
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input wire jc7,
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input wire jc8,
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input wire jc9,
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input wire jc10,
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output wire xadc1_p,
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input wire xadc1_n,
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output wire xadc2_p,
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output wire xadc2_n
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);
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// ============================================================================
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// Clock & reset
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reg [3:0] rst_sr;
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initial rst_sr <= 4'hF;
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always @(posedge clk)
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if (sw[0])
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rst_sr <= 4'hF;
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else
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rst_sr <= rst_sr >> 1;
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wire CLK = clk;
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wire RST = rst_sr[0];
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// ============================================================================
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// IDELAY calibrator
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wire cal_rdy;
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idelay_calibrator cal
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(
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.refclk (CLK),
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.rst (RST),
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.rdy (cal_rdy)
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);
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// ============================================================================
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// Delay selector
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wire btn_in = sw[1];
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reg [3:0] btn_sr;
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wire btn_edge;
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reg [16:0] btn_cnt;
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always @(posedge CLK)
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if (RST)
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btn_sr <= (btn_in) ? 4'hF : 4'h0;
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else
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btn_sr <= (btn_sr >> 1) | (btn_in << 3);
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assign btn_edge = btn_sr[1] ^ btn_sr[0];
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always @(posedge CLK)
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if (RST)
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btn_cnt <= -1;
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else if (btn_edge)
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btn_cnt <= 1000000 - 1;
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else if (!btn_cnt[15])
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btn_cnt <= btn_cnt - 1;
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wire dly_ld_req = btn_edge && btn_cnt[15];
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// ============================================================================
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// IDELAY path
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reg dly_ld;
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wire dly_out;
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reg [4:0] dly_delay_in;
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wire [4:0] dly_delay_out;
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always @(posedge CLK)
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if (RST || !cal_rdy)
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dly_ld <= 0;
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else if ( dly_ld)
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dly_ld <= 0;
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else if (!dly_ld && dly_ld_req)
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dly_ld <= 1;
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always @(posedge CLK)
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if (RST || !cal_rdy)
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dly_delay_in <= 0;
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else if (!dly_ld && dly_ld_req)
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dly_delay_in <= dly_delay_in + 1;
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(* KEEP, DONT_TOUCH *)
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IDELAYE2 #
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(
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.IDELAY_TYPE ("VAR_LOAD"),
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.DELAY_SRC ("IDATAIN")
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)
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idelay
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(
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.IDATAIN (xadc1_n),
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.DATAOUT (dly_out),
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.REGRST (RST),
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.C (CLK),
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.LD (dly_ld),
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.CNTVALUEIN (dly_delay_in),
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.CNTVALUEOUT (dly_delay_out)
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);
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// ============================================================================
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// I/O connections
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reg O;
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always @(posedge CLK)
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if (RST) O <= 0;
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else O <= ~O;
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reg [23:0] heartbeat_cnt;
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always @(posedge CLK)
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heartbeat_cnt <= heartbeat_cnt + 1;
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assign led[ 0] = heartbeat_cnt[23];
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assign led[ 1] = cal_rdy;
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assign led[ 2] = 1'b0;
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assign led[ 3] = 1'b0;
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assign led[ 4] = 1'b0;
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assign led[ 5] = 1'b0;
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assign led[ 6] = 1'b0;
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assign led[ 7] = 1'b0;
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assign led[ 8] = 1'b0;
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assign led[ 9] = 1'b0;
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assign led[10] = 1'b0;
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assign led[11] = dly_delay_out[0];
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assign led[12] = dly_delay_out[1];
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assign led[13] = dly_delay_out[2];
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assign led[14] = dly_delay_out[3];
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assign led[15] = dly_delay_out[4];
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assign ja1 = 1'b0;
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assign ja2 = 1'b0;
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assign ja3 = 1'b0;
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assign ja4 = 1'b0;
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assign jb1 = 1'b0;
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assign jb2 = 1'b0;
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assign jb3 = 1'b0;
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assign jb4 = 1'b0;
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assign jc1 = 1'b0;
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assign jc2 = 1'b0;
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assign jc3 = 1'b0;
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assign jc4 = 1'b0;
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assign xadc2_p = O;
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assign xadc2_n = O;
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assign xadc1_p = dly_out;
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endmodule
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Binary file not shown.
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@ -0,0 +1,43 @@
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`default_nettype none
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// ============================================================================
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module idelay_calibrator #
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(
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parameter SITE_LOC = ""
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)
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(
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input wire refclk, // REFCLK for IDELAYCTRL
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input wire rst, // External reset
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output wire rdy // Output ready signal
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);
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// ============================================================================
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// Long reset generator (~60ns for Artix 7 according to the datasheet)
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reg [6:0] r_cnt;
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wire r_rst;
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initial r_cnt <= 0;
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always @(posedge refclk)
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if (rst)
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r_cnt <= 0;
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else if (r_rst)
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r_cnt <= r_cnt + 1;
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assign r_rst = !r_cnt[6];
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// ============================================================================
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// IDELAYCTRL
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(* KEEP, DONT_TOUCH, LOC = SITE_LOC *)
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IDELAYCTRL idelayctlr
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(
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.REFCLK (refclk),
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.RST (r_rst),
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.RDY (rdy)
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);
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endmodule
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@ -0,0 +1,36 @@
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create_project -force -name $env(PROJECT_NAME) -part xc7a35tcpg236-1
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read_edif ../$env(PROJECT_NAME).edif
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link_design -part xc7a35tcpg236-1
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source ../basys3.xdc
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report_timing_summary -file top_timing_synth.rpt
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report_utilization -hierarchical -file top_utilization_hierarchical_synth.rpt
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report_utilization -file top_utilization_synth.rpt
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opt_design
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place_design
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report_utilization -hierarchical -file top_utilization_hierarchical_place.rpt
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report_utilization -file top_utilization_place.rpt
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report_io -file top_io.rpt
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report_control_sets -verbose -file top_control_sets.rpt
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report_clock_utilization -file top_clock_utilization.rpt
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route_design
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#phys_opt_design
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report_timing_summary -no_header -no_detailed_paths
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write_checkpoint -force ../$env(PROJECT_NAME).dcp
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set_property SEVERITY {Warning} [get_drc_checks UCIO-1]
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set_property SEVERITY {Warning} [get_drc_checks NSTD-1]
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report_route_status -file top_route_status.rpt
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report_drc -file top_drc.rpt
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report_timing_summary -datasheet -max_paths 10 -file top_timing.rpt
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report_power -file top_power.rpt
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write_bitstream -force ../$env(PROJECT_NAME).bit
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@ -0,0 +1,11 @@
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create_project -force -name $env(PROJECT_NAME) -part xc7a35tcpg236-1
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read_verilog ../$env(PROJECT_NAME).v
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synth_design -top top
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report_timing_summary -file top_timing_synth.rpt
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report_utilization -hierarchical -file top_utilization_hierarchical_synth.rpt
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report_utilization -file top_utilization_synth.rpt
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write_edif -force ../$env(PROJECT_NAME).edif
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