2018-02-14 12:24:18 +01:00
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# CLB_nDI1MUX Minitest
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2017-12-11 22:41:28 +01:00
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2018-02-14 12:24:18 +01:00
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## Purpose
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2019-10-24 22:51:47 +02:00
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Trying to set SLICEM LUT DI1 inputs
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These exist for LUTA, LUTB, and LUTC only
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Can either be an external signal, another LUT's data input, or another LUT's carry
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Note: mux input pattern is irregular
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2018-02-14 12:24:18 +01:00
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## Result
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2019-10-24 22:51:47 +02:00
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The following bits are set for NI but not NMC31:
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2018-02-14 12:24:18 +01:00
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```
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2017-12-19 04:05:53 +01:00
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bit 00_00 ADI1MUX.AI
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bit 00_20 BDI1MUX.BI
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bit 01_43 BDI1MUX.CI
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2018-02-14 12:24:18 +01:00
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```
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2019-10-24 22:51:47 +02:00
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Additionally, test with unknown DI mux bits don't appear near NI bits
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There is something strange going on
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2017-12-11 22:41:28 +01:00
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