mirror of https://github.com/openXC7/prjxray.git
91 lines
3.5 KiB
Markdown
91 lines
3.5 KiB
Markdown
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# LiteX UART DDR minitest
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This test aims at providing a minimal DDR design.
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The design is tested with a python script that provides memory control signals to the DDR controller
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using an UART bridge.
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The script performs the calbiration process, therfore it looks for the bitslip as well as the delay values.
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### Implementation
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There are two different ways to test this design:
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1. Vivado: the flow is entirely managed by Vivado, including Synthesis. To make use of this flow do the following:
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```
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cd src.vivado
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make
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```
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2. Yosys + Vivado: the flow is divided in two steps. Yosys handles synthesys, while Vivado handles P&R and bitstream generation. To make use of this flow do the following:
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```
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cd src.yosys
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make
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```
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### Testing
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To test the implemented design, load the bitstream produced in the previous step, and do the following:
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1. Open the litex server:
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```
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lxserver --uart --uart-port=/dev/ttyUSBX
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```
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2. On a different terminal, connect to the server through the client script
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```
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cd scripts
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make test_sdram
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```
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#### Output
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Depending on the clock frequency selected during the gateware generation, different outputs are generated:
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- 50 MHz sysytem clock:
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```
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Minimal Arty DDR3 Design for tests with Project X-Ray 2020-02-03 11:30:24
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Release reset
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Bring CKE high
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Load Mode Register 2, CWL=5
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Load Mode Register 3
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Load Mode Register 1
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Load Mode Register 0, CL=6, BL=8
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ZQ Calibration
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bitslip 0: |..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|31|
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bitslip 1: |..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|
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bitslip 2: |..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|
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bitslip 3: |..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|
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bitslip 4: |..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|
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bitslip 5: |..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|
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bitslip 6: |..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|
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bitslip 7: |..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|
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```
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- 100 MHz system clock:
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```
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Minimal Arty DDR3 Design for tests with Project X-Ray 2020-01-31 15:41:14
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Release reset
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Bring CKE high
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Load Mode Register 2, CWL=5
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Load Mode Register 3
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Load Mode Register 1
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Load Mode Register 0, CL=6, BL=8
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ZQ Calibration
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bitslip 0: |00|01|02|03|04|05|06|07|08|09|10|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|
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bitslip 1: |..|..|..|..|..|..|..|..|..|..|..|..|..|13|14|15|16|17|18|19|20|21|22|23|24|25|..|..|..|..|..|..|
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bitslip 2: |..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|29|30|31|
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bitslip 3: |..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|
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bitslip 4: |..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|
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bitslip 5: |..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|
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bitslip 6: |..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|
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bitslip 7: |..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|
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```
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