mirror of https://github.com/openXC7/prjxray.git
57 lines
1.5 KiB
Bash
57 lines
1.5 KiB
Bash
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#!/bin/bash
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set -ex
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source ../settings.sh
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cat > design.xdc << EOT
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set_property -dict {PACKAGE_PIN $XRAY_PIN_00 IOSTANDARD LVCMOS33} [get_ports I[0]]
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set_property -dict {PACKAGE_PIN $XRAY_PIN_01 IOSTANDARD LVCMOS33} [get_ports I[1]]
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set_property -dict {PACKAGE_PIN $XRAY_PIN_02 IOSTANDARD LVCMOS33} [get_ports I[2]]
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set_property -dict {PACKAGE_PIN $XRAY_PIN_03 IOSTANDARD LVCMOS33} [get_ports I[3]]
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set_property -dict {PACKAGE_PIN $XRAY_PIN_04 IOSTANDARD LVCMOS33} [get_ports I[4]]
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set_property -dict {PACKAGE_PIN $XRAY_PIN_05 IOSTANDARD LVCMOS33} [get_ports I[5]]
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set_property -dict {PACKAGE_PIN $XRAY_PIN_06 IOSTANDARD LVCMOS33} [get_ports O]
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set_property LOCK_PINS {I0:A1 I1:A2 I2:A3 I3:A4 I4:A5 I5:A6} [get_cells lut]
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set_property -dict {IS_LOC_FIXED 1 IS_BEL_FIXED 1 BEL SLICEL.A6LUT} [get_cells lut]
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set_property CFGBVS VCCO [current_design]
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
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EOT
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cat > design.v << EOT
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module top(input [5:0] I, output O);
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LUT6 #(.INIT(64'h8000000000000000)) lut (
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.I0(I[0]),
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.I1(I[1]),
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.I2(I[2]),
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.I3(I[3]),
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.I4(I[4]),
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.I5(I[5]),
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.O(O)
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);
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endmodule
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EOT
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cat > design.tcl << EOT
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create_project -force -part $XRAY_PART design design
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read_xdc design.xdc
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read_verilog design.v
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synth_design -top top
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place_design
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route_design
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write_checkpoint -force design.dcp
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source logicframes.tcl
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source tiledata.tcl
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EOT
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rm -f design.log
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vivado -nojournal -log design.log -mode batch -source design.tcl
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