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Documenting the Xilinx 7-series bit-stream format.
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Verilog 20.2%
Tcl 13.5%
C++ 10.6%
Makefile 5.5%
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Clifford Wolf 858f50d9bb Initial import 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Signed-off-by: Tim 'mithro' Ansell <mithro@mithis.com>
 		2017-07-20 09:57:10 +02:00
gridinfo Initial import 2017-07-20 09:57:10 +02:00
settings.sh Initial import 2017-07-20 09:57:10 +02:00