mirror of https://github.com/openXC7/prjxray.git
21 lines
775 B
Tcl
21 lines
775 B
Tcl
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# Create a simple design with a few IOs
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create_project -force -part $::env(XRAY_PART) design design
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read_verilog $::env(TOP_V)
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synth_design -top top -flatten_hierarchy none
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do]
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set_property CFGBVS VCCO [current_design]
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
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set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF]
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place_design
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route_design
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