2018-02-14 12:24:18 +01:00
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# CLB_RAM Minitest
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2017-12-11 20:02:09 +01:00
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2018-02-14 12:24:18 +01:00
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## Purpose
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SLICEM RAM test
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LUT6 => 64 bits
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Focus on 64 bit
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32 probably uses same O5/O6 stuff
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128 probably uses same MUX stuff
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Why isn't there a 256?
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## Result
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```
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2017-12-11 20:02:09 +01:00
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RAM128X1D 128-Deep by 1-Wide Dual Port Random Access Memory (Select RAM)
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RAM128X1S 128-Deep by 1-Wide Random Access Memory (Select RAM)
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RAM256X1S 256-Deep by 1-Wide Random Access Memory (Select RAM)
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RAM32M 32-Deep by 8-bit Wide Multi Port Random Access Memory (Select RAM)
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RAM32X1D 32-Deep by 1-Wide Static Dual Port Synchronous RAM
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RAM32X1S 32-Deep by 1-Wide Static Synchronous RAM
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RAM32X1S_1 32-Deep by 1-Wide Static Synchronous RAM with Negative-Edge Clock
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RAM32X2S 32-Deep by 2-Wide Static Synchronous RAM
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RAM64M 64-Deep by 4-bit Wide Multi Port Random Access Memory (Select RAM)
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RAM64X1D 64-Deep by 1-Wide Dual Port Static Synchronous RAM
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RAM64X1S 64-Deep by 1-Wide Static Synchronous RAM
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RAM64X1S_1 64-Deep by 1-Wide Static Synchronous RAM with Negative-Edge Clock
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2018-02-14 12:24:18 +01:00
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```
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