2017-11-11 04:55:59 +01:00
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create_project -force -part $::env(XRAY_PART) design design
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read_verilog ../top.v
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read_verilog ../picorv32.v
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synth_design -top top
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports din]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports dout]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports stb]
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create_pblock roi
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add_cells_to_pblock [get_pblocks roi] [get_cells roi]
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resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"
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set_property CFGBVS VCCO [current_design]
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
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set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF]
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2017-12-21 20:56:15 +01:00
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set_param tcl.collectionResultDisplayLimit 0
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2017-11-11 04:55:59 +01:00
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2017-11-11 07:37:02 +01:00
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source ../../../utils/utils.tcl
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randplace_pblock 100 roi
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2017-11-11 04:55:59 +01:00
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place_design
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route_design
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write_checkpoint -force design.dcp
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proc write_txtdata {filename} {
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puts "Writing $filename."
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set fp [open $filename w]
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2017-11-15 21:27:45 +01:00
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set all_pips [lsort -unique [get_pips -of_objects [get_nets -hierarchical]]]
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2017-11-11 04:55:59 +01:00
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foreach tile [get_tiles [regsub -all {CLBL[LM]} [get_tiles -of_objects [get_sites -of_objects [get_pblocks roi]]] INT]] {
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puts "Dumping pips from tile $tile"
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2017-11-15 21:27:45 +01:00
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foreach pip [filter $all_pips "TILE == $tile"] {
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set src_wire [get_wires -uphill -of_objects $pip]
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set dst_wire [get_wires -downhill -of_objects $pip]
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set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]]
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set dir_prop [get_property IS_DIRECTIONAL $pip]
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puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop"
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2017-11-11 04:55:59 +01:00
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}
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}
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close $fp
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}
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write_bitstream -force design.bit
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write_txtdata design.txt
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