Add intpips experiment

Signed-off-by: Clifford Wolf <clifford@clifford.at>
Signed-off-by: Tim 'mithro' Ansell <mithro@mithis.com>

experiments/clbpips/README

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+
+Experiment looking into the CLB PIPs
+====================================
+
+None of the CLB PIPs are "real". I.e. all those PIPs are in fact implemented
+using other resources. E.g. the PIPs that select which net is routed to which
+LUT input pin is implemented by permutating the LUT INIT bits accordingly.
+

experiments/intpips/.gitignore

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+/specimen_[0-9][0-9][0-9]/
+/seg_clbl[lm].segbits

experiments/intpips/Makefile

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+
+N := 1
+SPECIMENS := $(addprefix specimen_,$(shell seq -f '%03.0f' $(N)))
+SPECIMENS_OK := $(addsuffix /OK,$(SPECIMENS))
+
+database: database/clbll database/clblm
+
+pushdb: pushdb/clbll pushdb/clblm
+
+database/%: $(SPECIMENS_OK)
+	../../tools/segmatch -o seg_$(notdir $@).segbits \
+			$(addsuffix /segdata_$(notdir $@).txt,$(SPECIMENS))
+
+pushdb/%:
+	bash ../../utils/mergedb.sh seg_$(notdir $@).segbits \
+			../../database/$(XRAY_DATABASE)/seg_$(notdir $@).segbits
+
+$(SPECIMENS_OK):
+	bash generate.sh $(subst /OK,,$@)
+	touch $@
+
+clean:
+	rm -rf specimen_[0-9][0-9][0-9]/ seg_clbll.segbits seg_clblm.segbits
+
+.PHONY: database pushdb clean
+

experiments/intpips/README

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+
+Experiment looking into the INT PIPs
+====================================
+
+Results: ???
+

experiments/intpips/generate.py

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+#!/usr/bin/env python3
+
+import sys, re
+
+sys.path.append("../../../utils/")
+from segmaker import segmaker
+
+segmk = segmaker("design.bits")
+
+tiledata = dict()
+pipdata = dict()
+
+print("Loading tags from design.txt.")
+with open("design.txt", "r") as f:
+    for line in f:
+        tile, pip, src, dst = line.split()
+        _, pip = pip.split(".")
+        _, src = src.split("/")
+        _, dst = dst.split("/")
+
+        if tile not in tiledata:
+            tiledata[tile] = {
+                "pips": set(),
+                "srcs": set(),
+                "dsts": set()
+            }
+
+        if pip in pipdata:
+            assert pipdata[pip] == (src, dst)
+        else:
+            pipdata[pip] = (src, dst)
+
+        tiledata[tile]["pips"].add(pip)
+        tiledata[tile]["srcs"].add(src)
+        tiledata[tile]["dsts"].add(dst)
+
+for tile, pips_srcs_dsts in tiledata.items():
+    pips = pips_srcs_dsts["pips"]
+    srcs = pips_srcs_dsts["srcs"]
+    dsts = pips_srcs_dsts["dsts"]
+
+    for pip, src_dst in pipdata.items():
+        if pip in pips:
+            segmk.addtag(tile, pip, 1)
+        else:
+            src, dst = src_dst
+            if (src not in srcs) and (dst not in dsts):
+                segmk.addtag(tile, pip, 0)
+
+segmk.compile()
+segmk.write()
+

experiments/intpips/generate.sh

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+#!/bin/bash
+
+. ../../utils/genheader.sh
+
+echo '`define SEED 32'"'h$(echo $1 | md5sum | cut -c1-8)" > setseed.vh
+
+vivado -mode batch -source ../generate.tcl
+
+../../../tools/bitread -F $XRAY_ROI_FRAMES -o design.bits -zy design.bit
+python3 ../generate.py
+

experiments/intpips/generate.tcl

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+create_project -force -part $::env(XRAY_PART) design design
+
+read_verilog ../top.v
+read_verilog ../picorv32.v
+synth_design -top top
+
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports din]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports dout]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports stb]
+
+create_pblock roi
+add_cells_to_pblock [get_pblocks roi] [get_cells roi]
+resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"
+
+set_property CFGBVS VCCO [current_design]
+set_property CONFIG_VOLTAGE 3.3 [current_design]
+set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
+
+set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF]
+
+place_design
+route_design
+
+write_checkpoint -force design.dcp
+
+proc write_txtdata {filename} {
+	puts "Writing $filename."
+	set fp [open $filename w]
+	foreach tile [get_tiles [regsub -all {CLBL[LM]} [get_tiles -of_objects [get_sites -of_objects [get_pblocks roi]]] INT]] {
+		puts "Dumping pips from tile $tile"
+		foreach pip [get_pips -of_objects $tile] {
+			if {[get_nets -quiet -of_objects $pip] != {}} {
+				set src_wire [get_wires -uphill -of_objects $pip]
+				set dst_wire [get_wires -downhill -of_objects $pip]
+				puts $fp "$tile $pip $src_wire $dst_wire"
+			}
+		}
+	}
+	close $fp
+}
+
+write_bitstream -force design.bit
+write_txtdata design.txt
+

experiments/intpips/top.v

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+`include "setseed.vh"
+
+module top(input clk, din, stb, output dout);
+	reg [41:0] din_bits;
+	wire [78:0] dout_bits;
+
+	reg [41:0] din_shr;
+	reg [78:0] dout_shr;
+
+	always @(posedge clk) begin
+		if (stb) begin
+			din_bits <= din_shr;
+			dout_shr <= dout_bits;
+		end else begin
+			din_shr <= {din_shr, din};
+			dout_shr <= {dout_shr, din_shr[41]};
+		end
+	end
+
+	assign dout = dout_shr[78];
+
+	roi roi (
+		.clk(clk),
+		.din_bits(din_bits),
+		.dout_bits(dout_bits)
+	);
+endmodule
+
+module roi(input clk, input [41:0] din_bits, output [78:0] dout_bits);
+	picorv32 picorv32 (
+		.clk(clk),
+		.resetn(din_bits[0]),
+		.mem_valid(dout_bits[0]),
+		.mem_instr(dout_bits[1]),
+		.mem_ready(din_bits[1]),
+		.mem_addr(dout_bits[33:2]),
+		.mem_wdata(dout_bits[66:34]),
+		.mem_wstrb(dout_bits[70:67]),
+		.mem_rdata(din_bits[33:2])
+	);
+
+	randluts randluts (
+		.din(din_bits[41:34]),
+		.dout(dout_bits[78:71])
+	);
+endmodule
+
+module randluts(input [7:0] din, output [7:0] dout);
+	localparam integer N = 250;
+
+	function [31:0] xorshift32(input [31:0] xorin);
+		begin
+			xorshift32 = xorin;
+			xorshift32 = xorshift32 ^ (xorshift32 << 13);
+			xorshift32 = xorshift32 ^ (xorshift32 >> 17);
+			xorshift32 = xorshift32 ^ (xorshift32 <<  5);
+		end
+	endfunction
+
+	function [63:0] lutinit(input [7:0] a, b);
+		begin
+			lutinit[63:32] = xorshift32(xorshift32(xorshift32(xorshift32({a, b} ^ `SEED))));
+			lutinit[31: 0] = xorshift32(xorshift32(xorshift32(xorshift32({b, a} ^ `SEED))));
+		end
+	endfunction
+
+	wire [(N+1)*8-1:0] nets;
+
+	assign nets[7:0] = din;
+	assign dout = nets[(N+1)*8-1:N*8];
+
+	genvar i, j;
+	generate
+		for (i = 0; i < N; i = i+1) begin:is
+			for (j = 0; j < 8; j = j+1) begin:js
+				localparam integer k = xorshift32(xorshift32(xorshift32(xorshift32((i << 20) ^ (j << 10) ^ `SEED)))) & 255;
+				LUT6 #(
+					.INIT(lutinit(i, j))
+				) lut (
+					.I0(nets[8*i+(k+0)%8]),
+					.I1(nets[8*i+(k+1)%8]),
+					.I2(nets[8*i+(k+2)%8]),
+					.I3(nets[8*i+(k+3)%8]),
+					.I4(nets[8*i+(k+4)%8]),
+					.I5(nets[8*i+(k+5)%8]),
+					.O(nets[8*i+8+j])
+				);
+			end
+		end
+	endgenerate
+endmodule