luke
/
prjxray
mirror of https://github.com/openXC7/prjxray.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
prjxray/minitests/litex/min/arty/src.yosys/mem.init

1 line
19 B
Plaintext
Raw Permalink Normal View History

minitests: Add minimal Litex configuration for Arty Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
2019-11-21 09:33:47 +01:00
../verilog/mem.init