Updating DB based on "Remove 070-tileconn fuzzer from top level Makefile.".
See [Info File](Info.md) for details. Signed-off-by: Tim 'mithro' Ansell <me@mith.ro>
This commit is contained in:
Tim 'mithro' Ansell
parent
e90d75eb4f
commit
ef74779839
332
Info.md
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Info.md
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@ -37,24 +37,26 @@ These files are released under the very permissive [CC0 1.0 Universal](COPYING).
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# Details
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Last updated on Mon Oct 22 16:06:34 UTC 2018 (2018-10-22T16:06:34+00:00).
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Last updated on Tue Oct 23 16:01:05 UTC 2018 (2018-10-23T16:01:05+00:00).
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Created using [Project X-Ray](https://github.com/SymbiFlow/prjxray) version [v0.0-774-gbba5c89](https://github.com/SymbiFlow/prjxray/commit/bba5c899ddb7917fe5d34675a05abfb9c4db8f51).
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Created using [Project X-Ray](https://github.com/SymbiFlow/prjxray) version [v0.0-836-gfeb1a2c](https://github.com/SymbiFlow/prjxray/commit/feb1a2ca7b137befa1e4e1fe65ab1f70f2b8fcfe).
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Latest commit was;
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```
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commit bba5c899ddb7917fe5d34675a05abfb9c4db8f51
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commit feb1a2ca7b137befa1e4e1fe65ab1f70f2b8fcfe
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Author: Tim 'mithro' Ansell <me@mith.ro>
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Date: Wed Oct 17 23:09:04 2018 +0000
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Date: Mon Oct 22 16:14:29 2018 +0000
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Expanded ROI causes these asserts to fail.
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Remove 070-tileconn fuzzer from top level Makefile.
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Signed-off-by: Tim 'mithro' Ansell <me@mith.ro>
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```
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## Database for [artix7](artix7/)
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### Settings
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Created using following [settings.sh (sha256: a215bd6ad72742d242ed4d9e6712f393f57341577f9c5197e84c7d61635b9e18)](https://github.com/SymbiFlow/prjxray/blob/bba5c899ddb7917fe5d34675a05abfb9c4db8f51/database/artix7/settings.sh)
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Created using following [settings.sh (sha256: a215bd6ad72742d242ed4d9e6712f393f57341577f9c5197e84c7d61635b9e18)](https://github.com/SymbiFlow/prjxray/blob/feb1a2ca7b137befa1e4e1fe65ab1f70f2b8fcfe/database/artix7/settings.sh)
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```shell
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export XRAY_DATABASE="artix7"
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export XRAY_PART="xc7a50tfgg484-1"
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@ -99,8 +101,8 @@ Results have checksums;
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* [`3955d590e8ee64c843bb80f911a08781c1bac63e71b577436ae1f44195a88e22 ./artix7/ppips_clbll_r.db`](./artix7/ppips_clbll_r.db)
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* [`29f175153821dc13989eb580676ff0007e108d911275a74e7ebe45e819c14eaf ./artix7/ppips_clblm_l.db`](./artix7/ppips_clblm_l.db)
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* [`52b53ae735d40632403283ab720db2172794a22c5245b3da7693b264d69a122d ./artix7/ppips_clblm_r.db`](./artix7/ppips_clblm_r.db)
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* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./artix7/ppips_hclk_l.db`](./artix7/ppips_hclk_l.db)
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* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./artix7/ppips_hclk_r.db`](./artix7/ppips_hclk_r.db)
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* [`6d35b568a51f9b6761da2470a71738b2477ef72c16068a529ae8eb52b65bf17a ./artix7/ppips_hclk_l.db`](./artix7/ppips_hclk_l.db)
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* [`81e0696179a33bdf8d2279a53b406911a403d50224355e9ad29eccee01a70305 ./artix7/ppips_hclk_r.db`](./artix7/ppips_hclk_r.db)
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* [`be617c15d1ec311b6249791414bbd69380fe90b476353cbb2fc2a7cb06f5029d ./artix7/ppips_int_l.db`](./artix7/ppips_int_l.db)
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* [`a1423859c97a82dcfb114644f50b991db4ca7e0996e6d1ae4d2c97bfdfcb723d ./artix7/ppips_int_r.db`](./artix7/ppips_int_r.db)
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* [`8aba20247656e287de5d0033bfaf31f2514cff0d041bd438719116673dc5e815 ./artix7/segbits_clbll_l.db`](./artix7/segbits_clbll_l.db)
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@ -112,164 +114,164 @@ Results have checksums;
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* [`08dee581e565abbd09db559f9226139ba5a253f8aec4f3492152d8df8a87bbab ./artix7/segbits_int_l.db`](./artix7/segbits_int_l.db)
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* [`be5f0c64ee17ad010dfea5125200216b2c69a558477a80133d043ed466e565be ./artix7/segbits_int_r.db`](./artix7/segbits_int_r.db)
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* [`a215bd6ad72742d242ed4d9e6712f393f57341577f9c5197e84c7d61635b9e18 ./artix7/settings.sh`](./artix7/settings.sh)
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* [`6e06cb20258401bb5fdf87fb01fdcebf75f3f7211cadd89b485c21be8eb7f852 ./artix7/site_type_BSCAN.json`](./artix7/site_type_BSCAN.json)
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* [`d88f7d6166556e1a059fef6136a078252575e50feeb3e1bfc6e10c1d25aabf02 ./artix7/site_type_BUFGCTRL.json`](./artix7/site_type_BUFGCTRL.json)
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* [`dfc738eefd3f5f71ff6f39bb921708b81ae49e9a280a82c896c3a66bfefb8e58 ./artix7/site_type_BUFHCE.json`](./artix7/site_type_BUFHCE.json)
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* [`444ab7c3176130e6f08a1b00f43de4a7be085fae27f3cc47330f2c939f2d84dd ./artix7/site_type_BUFIO.json`](./artix7/site_type_BUFIO.json)
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* [`0e5088865d6cb5f795ee85ee96000d74acfebedcd07f7dd7a0f276033e4add2a ./artix7/site_type_BUFMRCE.json`](./artix7/site_type_BUFMRCE.json)
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* [`548366a566791e5d0d2bf6be4e8b4a96ec5893b4e108b9c92323f32710714bb8 ./artix7/site_type_BUFR.json`](./artix7/site_type_BUFR.json)
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* [`3a57071763e617312ef771029537a9ac29774b0aa757e77489fecb2f30971327 ./artix7/site_type_CAPTURE.json`](./artix7/site_type_CAPTURE.json)
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* [`5bb9dc6b888ef106dd6c56849ab2856b9b4e5988467672cf4966f3108c130a26 ./artix7/site_type_DCIRESET.json`](./artix7/site_type_DCIRESET.json)
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* [`fbe70221478cf4568f062ae6d039d349faba2c56cc76516b829887ae100b8915 ./artix7/site_type_DNA_PORT.json`](./artix7/site_type_DNA_PORT.json)
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* [`5c22c33d2185b4103ab60191e459d52b10ca43aa7cf069e8a8a15477ef5f95d8 ./artix7/site_type_DSP48E1.json`](./artix7/site_type_DSP48E1.json)
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* [`2a7e9bbe8bd61dbe085098ffadbe228a2a965b98198016baa8593615cba7408e ./artix7/site_type_EFUSE_USR.json`](./artix7/site_type_EFUSE_USR.json)
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* [`44da7fa75c6fb7b0f2f2be9e0b6e464631f143b2b6be3a867d3a004bac4b413e ./artix7/site_type_FIFO18E1.json`](./artix7/site_type_FIFO18E1.json)
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* [`1b9235a8849c1812886050948bb0cf1b287feea46ee303d8c9dd3b3ccc8957ba ./artix7/site_type_FRAME_ECC.json`](./artix7/site_type_FRAME_ECC.json)
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* [`a65074a1581355e1950ab39bf8ac5b13b7050d3f3b221b2f7ecf26cc1d984155 ./artix7/site_type_GTPE2_CHANNEL.json`](./artix7/site_type_GTPE2_CHANNEL.json)
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* [`f5b3a1e66bd974bcfeacdf7416837ff422fbf7dc3597518044e934d80718322b ./artix7/site_type_GTPE2_COMMON.json`](./artix7/site_type_GTPE2_COMMON.json)
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* [`d47a9d38e5c2e3111581214aebb2d870078fd2c091a163bf97e0a566e05688de ./artix7/site_type_IBUFDS_GTE2.json`](./artix7/site_type_IBUFDS_GTE2.json)
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* [`69d78ced4cf721f89e674f38a6c49eb1ff71afa1e589adae11581d3912721769 ./artix7/site_type_ICAP.json`](./artix7/site_type_ICAP.json)
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* [`a19bf15832620c26bcdaee163233ff1ce494de24bf345aae0614e2247601105e ./artix7/site_type_IDELAYCTRL.json`](./artix7/site_type_IDELAYCTRL.json)
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* [`969e58b5b790ef8cfb4ee2012baebef3a39e1641868a377e1a46d522acd6f7b4 ./artix7/site_type_IDELAYE2.json`](./artix7/site_type_IDELAYE2.json)
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* [`15badbd4e07896d3ea37b8b82bd82b74566302ee3ca7f1b66de6ef30c76ee3a0 ./artix7/site_type_ILOGICE3.json`](./artix7/site_type_ILOGICE3.json)
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* [`8005263511ad2099529bfadce9d0fd26b325ff08cc26c3e453bef26feec16f16 ./artix7/site_type_IN_FIFO.json`](./artix7/site_type_IN_FIFO.json)
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* [`98f08f89f011fe4a771b13bc62dba8e00e13186dcbe7b28ca6d2f3fe02c6ff58 ./artix7/site_type_IOB33.json`](./artix7/site_type_IOB33.json)
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* [`5942ca033249bcea32b252c912242bded0deb76d1175eba4e25396071c081995 ./artix7/site_type_IOB33M.json`](./artix7/site_type_IOB33M.json)
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* [`8d78bbf83cf8d8b3aa991d8f264d37636a8b9325791da95a914305606b946bb8 ./artix7/site_type_IOB33S.json`](./artix7/site_type_IOB33S.json)
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* [`2aebf9864f4098079d92ffa96240a18b2000b33dc04c956a4923828ed76f1a1a ./artix7/site_type_IPAD.json`](./artix7/site_type_IPAD.json)
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* [`05f7828421936f9e19de05d74716ef05bf77bb45c465014f458156b5d3335a05 ./artix7/site_type_MMCME2_ADV.json`](./artix7/site_type_MMCME2_ADV.json)
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* [`fe0943b7dc522a8df20a9ee3be5630ace77e041bd8669a1decb0664c82e61eca ./artix7/site_type_OLOGICE3.json`](./artix7/site_type_OLOGICE3.json)
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* [`d7bfe04a1abfb90fd1df4177c299229f981a036b63dd3f0be3677691b11ce66d ./artix7/site_type_OPAD.json`](./artix7/site_type_OPAD.json)
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* [`4cbd4bc0abc0c443003f96c17ddc8d3d2478546dd72f6e27473f12236841efc9 ./artix7/site_type_OUT_FIFO.json`](./artix7/site_type_OUT_FIFO.json)
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* [`0dd1a141a8bbb557e4ecd87b99901b4fd3cd1736e9e9aec7e00547a1f4b710cd ./artix7/site_type_PCIE_2_1.json`](./artix7/site_type_PCIE_2_1.json)
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* [`b234738303731a015f58fade2face8c4c885e8fb2e3de2250099e81e2d0f2821 ./artix7/site_type_PHASER_IN_PHY.json`](./artix7/site_type_PHASER_IN_PHY.json)
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* [`69c4ea774cfadfd7fa09bb35af1705a2733a3d07766e6e42c14667bff4c9fe35 ./artix7/site_type_PHASER_OUT_PHY.json`](./artix7/site_type_PHASER_OUT_PHY.json)
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* [`faba56326335ae03eccaf32a432a3a85051981057f38a348c3fee195e0b05c5c ./artix7/site_type_PHASER_REF.json`](./artix7/site_type_PHASER_REF.json)
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* [`d6cdfb4118627eac3cab985a95fa694e98389915352173e7564ad2571e510fe5 ./artix7/site_type_PHY_CONTROL.json`](./artix7/site_type_PHY_CONTROL.json)
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* [`52d56538d2113f810ec7a47f7439a9dbf9d7f6c4de40d981193af96634050845 ./artix7/site_type_PLLE2_ADV.json`](./artix7/site_type_PLLE2_ADV.json)
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* [`462191edfc3612812231c8fa64e788cfdcc23ea4de1f775e0ceed5b08fce4296 ./artix7/site_type_PMV2.json`](./artix7/site_type_PMV2.json)
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* [`e3073519cf2423ca2218ff0e60cc77a21c490ffa36032f5ec1b0760b02b8f2f2 ./artix7/site_type_RAMB18E1.json`](./artix7/site_type_RAMB18E1.json)
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* [`808ec16777af9a53a65f1669c56be3431247188b2381f7133ef6dc8ce797c466 ./artix7/site_type_RAMBFIFO36E1.json`](./artix7/site_type_RAMBFIFO36E1.json)
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* [`bb2fd61165fb0c50cd9ef622c1dc630044c3dd639754a613d8d9444505cb24d2 ./artix7/site_type_SLICEL.json`](./artix7/site_type_SLICEL.json)
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* [`0c5f1e1e92a453d193c5b49d1ec25d6da108bc3616965a8c437b6b16a30c4553 ./artix7/site_type_SLICEM.json`](./artix7/site_type_SLICEM.json)
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* [`1fe58f3068e4ba6b12dc75c1d187ba4ce829ae817f3924b1724f261ea569dcd3 ./artix7/site_type_STARTUP.json`](./artix7/site_type_STARTUP.json)
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* [`b246bc35a9bba6216fcc13a782361339a7b648e55cffb588a2393e0349003363 ./artix7/site_type_TIEOFF.json`](./artix7/site_type_TIEOFF.json)
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* [`6b1d14a3ab0749af2eb8fb6fbddd301f7e9643770521a18a7056ccea1852069d ./artix7/site_type_USR_ACCESS.json`](./artix7/site_type_USR_ACCESS.json)
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* [`b59ace663846a969f38d65d237840b8bfc1ff46d79722ddb3f9612d551036aa5 ./artix7/site_type_XADC.json`](./artix7/site_type_XADC.json)
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* [`907723c538bc8eb3739e894fdcfd82df3c3485f0b1345dc56cc7b0b8bf6c0edb ./artix7/tileconn.json`](./artix7/tileconn.json)
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* [`41df900062b5d42d53530bb7256f32c2d7bf9897b1a37567a80f35e9534e965b ./artix7/tilegrid.json`](./artix7/tilegrid.json)
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* [`6356dd92dc8ad3ec1f1d433a8fe7b353ea9ab5bfc336c0c5ec8f8d1edd7c576d ./artix7/tile_type_BRAM_INT_INTERFACE_L.json`](./artix7/tile_type_BRAM_INT_INTERFACE_L.json)
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* [`f4c47c50a489cd31281f0a70251bc01e94535a00f8ed57d460f8128e7b046b2c ./artix7/tile_type_BRAM_INT_INTERFACE_R.json`](./artix7/tile_type_BRAM_INT_INTERFACE_R.json)
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* [`3d330dae26477da58bfc146bacbbd4093cf6a32cb2c57ba4aebf1a792978a87e ./artix7/tile_type_BRAM_L.json`](./artix7/tile_type_BRAM_L.json)
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* [`37670b787af2fe94fc9117fc9c13eb1220e63d9b164b7671a70b134dfbc04eed ./artix7/tile_type_BRAM_R.json`](./artix7/tile_type_BRAM_R.json)
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* [`133963431bc4ce086281515049ab9686991e3b06833a20d44f9cc0a54beee1ab ./artix7/tile_type_BRKH_BRAM.json`](./artix7/tile_type_BRKH_BRAM.json)
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* [`5d236a4fde8e4d2fa3e8b3ab42c36fed30584538020fe944bcab14ec0cd867e0 ./artix7/tile_type_BRKH_B_TERM_INT.json`](./artix7/tile_type_BRKH_B_TERM_INT.json)
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* [`ccc47c69cac00b32b794d10912213cd29204b74418ddff980839073f6b2669a7 ./artix7/tile_type_BRKH_CLB.json`](./artix7/tile_type_BRKH_CLB.json)
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* [`c5e828e2a3991a145ed3cd270f18605d306aff50636f08a4ce26ac6951569cf3 ./artix7/tile_type_BRKH_CLK.json`](./artix7/tile_type_BRKH_CLK.json)
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* [`3cb8824582eac4d85e245349d82893cd8308ca0983fcb951f22ae94cc38b155e ./artix7/tile_type_BRKH_CMT.json`](./artix7/tile_type_BRKH_CMT.json)
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* [`43d7deb15885c9a4d1000bbcb0da828a2c7e88ca5d2f2ffd2be53e7506cee877 ./artix7/tile_type_BRKH_DSP_L.json`](./artix7/tile_type_BRKH_DSP_L.json)
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* [`26fe1a5dec260f5dc62c1eea8491fb22902e19cb274cc39c3814682bc986e892 ./artix7/tile_type_BRKH_DSP_R.json`](./artix7/tile_type_BRKH_DSP_R.json)
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* [`6dd978f8089f759ec788de1b2ef6aad9e5abdc3c4745fe6c04439fd9953c1b76 ./artix7/tile_type_BRKH_GTX.json`](./artix7/tile_type_BRKH_GTX.json)
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* [`0368e3a2ac3845ace5b9ff358659a647ec77d437bd1c18eb42c2379fa46d906b ./artix7/tile_type_BRKH_INT.json`](./artix7/tile_type_BRKH_INT.json)
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* [`8934e08a1178fb80ac93336ff8f3c10d34b933cf8bcf3788a303c2ec94df23b7 ./artix7/tile_type_BRKH_TERM_INT.json`](./artix7/tile_type_BRKH_TERM_INT.json)
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* [`b7ae936c572bb3c3933717690b2b96c620d6e01bb5f379fc4944bc31c0dba6cd ./artix7/tile_type_B_TERM_INT.json`](./artix7/tile_type_B_TERM_INT.json)
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* [`1af9a9a3b920d1370d1ef8454792975d8f67ae3333fbdddaff924171b2e54605 ./artix7/tile_type_CFG_CENTER_BOT.json`](./artix7/tile_type_CFG_CENTER_BOT.json)
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* [`07121c342f17ab519357852dfc766d6d1acadc4faae232dcf2f6880980e1161a ./artix7/tile_type_CFG_CENTER_MID.json`](./artix7/tile_type_CFG_CENTER_MID.json)
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* [`45ea67079399a2a8cfdf7d72d2923f4175e41b22ef1a8d133ea3fe767a54dd03 ./artix7/tile_type_CFG_CENTER_TOP.json`](./artix7/tile_type_CFG_CENTER_TOP.json)
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* [`580ec91c785cd5b03aced9a8847874ba55684392919d48db4b1978ee4967600b ./artix7/tile_type_CLBLL_L.json`](./artix7/tile_type_CLBLL_L.json)
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* [`c00ca5ec419fadaef8b9821a0942b5e814701857fe7ea8a4473b72c537d0250b ./artix7/tile_type_CLBLL_R.json`](./artix7/tile_type_CLBLL_R.json)
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* [`f3793273d2cc799eeb2e6edad90a8080f578d926999745c21444a5ddc25c73a1 ./artix7/tile_type_CLBLM_L.json`](./artix7/tile_type_CLBLM_L.json)
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* [`e56ab784988141c82a6f77a014e5d14b361ca00f4c475730dd7a045d9ca0eba6 ./artix7/tile_type_CLBLM_R.json`](./artix7/tile_type_CLBLM_R.json)
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* [`4246e4895570060ecb2b8e9b07ccb6812f760ab0cd77b8940a90046b20b5adea ./artix7/tile_type_CLK_BUFG_BOT_R.json`](./artix7/tile_type_CLK_BUFG_BOT_R.json)
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* [`cc4b2ba2649cfaabb7cb47ed6b65fcd0d1bd4b219e57d57635e7cb4cb8b0d0ca ./artix7/tile_type_CLK_BUFG_REBUF.json`](./artix7/tile_type_CLK_BUFG_REBUF.json)
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* [`97c1b94fa8cc6100f2d2ef3ff7ac82d8ccc2cf71dbcb47d8d0f8a743ace2a69c ./artix7/tile_type_CLK_BUFG_TOP_R.json`](./artix7/tile_type_CLK_BUFG_TOP_R.json)
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* [`8f6853d4a9b77e55806ab06116639227901b390306704adbca542b62e6914e42 ./artix7/tile_type_CLK_FEED.json`](./artix7/tile_type_CLK_FEED.json)
|
||||
* [`fc157995da3124034ef029a08f78e19633765ee018e9cbf62571fac205573508 ./artix7/tile_type_CLK_HROW_BOT_R.json`](./artix7/tile_type_CLK_HROW_BOT_R.json)
|
||||
* [`0de1f23baabaf73e41ea76ae873174f695763388d49e22e5c9796d25183a4bbf ./artix7/tile_type_CLK_HROW_TOP_R.json`](./artix7/tile_type_CLK_HROW_TOP_R.json)
|
||||
* [`833bdb0d9af9117e448781202bc61c3b00277c91d6e50490c8c8f9e02751ac76 ./artix7/tile_type_CLK_MTBF2.json`](./artix7/tile_type_CLK_MTBF2.json)
|
||||
* [`7182ef530e88cb9ad13b7c586b36c835a6e0b9f1a15e5a7164c2dd40204e2822 ./artix7/tile_type_CLK_PMV2.json`](./artix7/tile_type_CLK_PMV2.json)
|
||||
* [`839aadd33956b87fee5cfdac2e75829e5dbf3a74837de40e7b4ce9f305e635de ./artix7/tile_type_CLK_PMV2_SVT.json`](./artix7/tile_type_CLK_PMV2_SVT.json)
|
||||
* [`5a7c64a08d0e9399a04da58087c0e1ef2ea13bc879efcfc70c68d716781fbead ./artix7/tile_type_CLK_PMVIOB.json`](./artix7/tile_type_CLK_PMVIOB.json)
|
||||
* [`d3c479f6f586d43cfd26ddab08f5a51b15c882c0c72075dc9423392d232d17ae ./artix7/tile_type_CLK_PMV.json`](./artix7/tile_type_CLK_PMV.json)
|
||||
* [`67d0b147735439607eb0facca9b73df19173a3985bfd18d06826e9404a85f286 ./artix7/tile_type_CLK_TERM.json`](./artix7/tile_type_CLK_TERM.json)
|
||||
* [`36e91b08239972628f8d807fcc62469fe5d5c64e385ca6bfbcc8d8ceaae3a396 ./artix7/tile_type_CMT_FIFO_L.json`](./artix7/tile_type_CMT_FIFO_L.json)
|
||||
* [`816c98fa7b2fb9e4e797ba79d00b0ac77d85fa900f041aeb08676936a7ef9a08 ./artix7/tile_type_CMT_FIFO_R.json`](./artix7/tile_type_CMT_FIFO_R.json)
|
||||
* [`ae4f0edb9d3a2041fd00a3eebdd466bff555315486310cfb7f6c8d0954a0e812 ./artix7/tile_type_CMT_PMV.json`](./artix7/tile_type_CMT_PMV.json)
|
||||
* [`e015952fc06a5f7bd7daa9fcbb149881d96de31fcfd87bce8225216c2ba77370 ./artix7/tile_type_CMT_PMV_L.json`](./artix7/tile_type_CMT_PMV_L.json)
|
||||
* [`d488d4c336d73b1c3f876e94e32f5cec85c2c65036018df4d2af10f7b0c7da18 ./artix7/tile_type_CMT_TOP_L_LOWER_B.json`](./artix7/tile_type_CMT_TOP_L_LOWER_B.json)
|
||||
* [`f55ba22266c49bb2792ce81b90e2f221384065e1ec10a02a390695ea2ec6a83f ./artix7/tile_type_CMT_TOP_L_LOWER_T.json`](./artix7/tile_type_CMT_TOP_L_LOWER_T.json)
|
||||
* [`68be7fc8a5f5b5e7e4a2c93e919ae3bc00a692589b7b0d95997d80de60a04275 ./artix7/tile_type_CMT_TOP_L_UPPER_B.json`](./artix7/tile_type_CMT_TOP_L_UPPER_B.json)
|
||||
* [`175f10cc9e689c13a42a680bbe18d37bb5e07f7ef5fcfe1fc17ed45d9dd6f4a3 ./artix7/tile_type_CMT_TOP_L_UPPER_T.json`](./artix7/tile_type_CMT_TOP_L_UPPER_T.json)
|
||||
* [`7a13fe99e2c202da444123e300692bcb324fd9c10aac9b2d0dadd527a6c6731f ./artix7/tile_type_CMT_TOP_R_LOWER_B.json`](./artix7/tile_type_CMT_TOP_R_LOWER_B.json)
|
||||
* [`686116b0a5f38a5f0b46083608eda6c0d134198058b4837624037909264bf519 ./artix7/tile_type_CMT_TOP_R_LOWER_T.json`](./artix7/tile_type_CMT_TOP_R_LOWER_T.json)
|
||||
* [`f2343f190fe4e9ae1383115113e68b2b7e771b4a84869de9691b5cc522892222 ./artix7/tile_type_CMT_TOP_R_UPPER_B.json`](./artix7/tile_type_CMT_TOP_R_UPPER_B.json)
|
||||
* [`56758e082ded7986405779e89d0289f02b7f7bce4db9334defe5b1f43275faa3 ./artix7/tile_type_CMT_TOP_R_UPPER_T.json`](./artix7/tile_type_CMT_TOP_R_UPPER_T.json)
|
||||
* [`96f878723ba2388e9dad84fd814290fffad65ca5364750369788978606874378 ./artix7/tile_type_DSP_L.json`](./artix7/tile_type_DSP_L.json)
|
||||
* [`b06477da1adad00b2de65b615c6a55f4538169f93a409095c0c963f172969543 ./artix7/tile_type_DSP_R.json`](./artix7/tile_type_DSP_R.json)
|
||||
* [`c366ecc3619a2e578b0d2823cf6ed88b1e78d216196a06cbcc02793ee782cfca ./artix7/tile_type_GTP_CHANNEL_0.json`](./artix7/tile_type_GTP_CHANNEL_0.json)
|
||||
* [`7bf0277080473beebc905e4fe35d8f4342b5bd38cd95e31d0e291a4efc499d8d ./artix7/tile_type_GTP_CHANNEL_1.json`](./artix7/tile_type_GTP_CHANNEL_1.json)
|
||||
* [`d54dab3a77a24af47ae1e0e91f12c7e0d188fb20ffeb12cc6b0e9234d48fd3b3 ./artix7/tile_type_GTP_CHANNEL_2.json`](./artix7/tile_type_GTP_CHANNEL_2.json)
|
||||
* [`5e341fa5b0ff19d4ebb48279a36f6817b2cda45c15b6da0a29da79e9b8c8ca86 ./artix7/tile_type_GTP_CHANNEL_3.json`](./artix7/tile_type_GTP_CHANNEL_3.json)
|
||||
* [`1226a9185be15fbe197e024ca1f3df67a4ad21cf855b519a2a706928ec5dc0d1 ./artix7/tile_type_GTP_COMMON.json`](./artix7/tile_type_GTP_COMMON.json)
|
||||
* [`92ebe3a0813a866ca7eb4e39b2b959bc2bcd14b20ce76961e9e31674140ca80a ./artix7/tile_type_GTP_INT_INTERFACE.json`](./artix7/tile_type_GTP_INT_INTERFACE.json)
|
||||
* [`2103859c8eab4c32a335592cb3a009e036238d98642664b4cc21bab71f299b78 ./artix7/tile_type_HCLK_BRAM.json`](./artix7/tile_type_HCLK_BRAM.json)
|
||||
* [`147fa108c950b89ad0c5f86983239dcbc2f4c9ac7126499b2e2d4026d7686bfe ./artix7/tile_type_HCLK_CLB.json`](./artix7/tile_type_HCLK_CLB.json)
|
||||
* [`937444c2e4b8f3df717eadd832cf973474d7e97eecf4f21b7a70417ec75a4e81 ./artix7/tile_type_HCLK_CMT.json`](./artix7/tile_type_HCLK_CMT.json)
|
||||
* [`819ee4728cfed0daef54ce4594028e4dd718887ce5058b4b5e121cda6d6481e4 ./artix7/tile_type_HCLK_CMT_L.json`](./artix7/tile_type_HCLK_CMT_L.json)
|
||||
* [`916fc0a327bf43dc2a3f12ae6969bc7ebe80384a5a2f5a3eca55675eb5adc88a ./artix7/tile_type_HCLK_DSP_L.json`](./artix7/tile_type_HCLK_DSP_L.json)
|
||||
* [`d614d7b300cf0edffd5956b0e7559f25bdf04118ea04c286a80bef7fa486cc91 ./artix7/tile_type_HCLK_DSP_R.json`](./artix7/tile_type_HCLK_DSP_R.json)
|
||||
* [`0ce351c5aecb49f1f24d9eee219cabeb72febbb5c5d09fb371e0e255f2ad09c4 ./artix7/tile_type_HCLK_FEEDTHRU_1.json`](./artix7/tile_type_HCLK_FEEDTHRU_1.json)
|
||||
* [`5797792a339615dacccda4c1e5a52d5b7b34f391beffa19024d86aad3ce88cd5 ./artix7/tile_type_HCLK_FEEDTHRU_2.json`](./artix7/tile_type_HCLK_FEEDTHRU_2.json)
|
||||
* [`a772601f527ba7be10d32404995d0f5426bb8e78a8d6b3f081526a22560ae712 ./artix7/tile_type_HCLK_FIFO_L.json`](./artix7/tile_type_HCLK_FIFO_L.json)
|
||||
* [`9e421a5a9145b46b21e106827d6668575e993bd5f21c4afb46dcf3c8b170b09f ./artix7/tile_type_HCLK_GTX.json`](./artix7/tile_type_HCLK_GTX.json)
|
||||
* [`e83dd138edc732989b7a98769b8fb40d0035d02c036bf9326faf9e92ec2b3838 ./artix7/tile_type_HCLK_INT_INTERFACE.json`](./artix7/tile_type_HCLK_INT_INTERFACE.json)
|
||||
* [`0fae33b58ec0697b8fc8290484a88eabe768cfcc849924166a0e10d97fe775a4 ./artix7/tile_type_HCLK_IOB.json`](./artix7/tile_type_HCLK_IOB.json)
|
||||
* [`994e7f7b016d690357bff6c2603b53e10a68df8e8d3996edbb4b1bd7a0934107 ./artix7/tile_type_HCLK_IOI3.json`](./artix7/tile_type_HCLK_IOI3.json)
|
||||
* [`d743ebc6d7f0b21eac6d440bfc14b709012167d4534c0ce12323d332975721a0 ./artix7/tile_type_HCLK_L_BOT_UTURN.json`](./artix7/tile_type_HCLK_L_BOT_UTURN.json)
|
||||
* [`df7f40d36ccc7e747aadce47160719c15dfa5185f5833c0ba75a4ea402530864 ./artix7/tile_type_HCLK_L.json`](./artix7/tile_type_HCLK_L.json)
|
||||
* [`28492670f4e6ec07178c16bb3781dca7740a5a386daab4d22ae1f5c19a688a67 ./artix7/tile_type_HCLK_R_BOT_UTURN.json`](./artix7/tile_type_HCLK_R_BOT_UTURN.json)
|
||||
* [`a55fa19083d178a580e013f7434698cc379541de843e3203aa23a8b0c74824a3 ./artix7/tile_type_HCLK_R.json`](./artix7/tile_type_HCLK_R.json)
|
||||
* [`8166f2b9660d099930ef5295d8cf865952164e41c803dbad65d08268afd7abb3 ./artix7/tile_type_HCLK_TERM_GTX.json`](./artix7/tile_type_HCLK_TERM_GTX.json)
|
||||
* [`dab5572a041a5783fc7e71a735209dee881400f9ee79cc93c3624200d0454706 ./artix7/tile_type_HCLK_TERM.json`](./artix7/tile_type_HCLK_TERM.json)
|
||||
* [`fae6daec23c58a0bccb223052c4f9b36e37f4c3ace67b5e8189566d366006ba7 ./artix7/tile_type_HCLK_VBRK.json`](./artix7/tile_type_HCLK_VBRK.json)
|
||||
* [`c6099ae4a5e0154de6ef1d219b70c8612017dc3465d6958e6eccb3fdd0c12805 ./artix7/tile_type_HCLK_VFRAME.json`](./artix7/tile_type_HCLK_VFRAME.json)
|
||||
* [`b600208dd374c8059c89b757770eca2392262b638a49e67bba21e6323112da06 ./artix7/tile_type_INT_FEEDTHRU_1.json`](./artix7/tile_type_INT_FEEDTHRU_1.json)
|
||||
* [`aced5f852446d59b79f27aee4ec475908a81dac0353566de51ffb7ef68b5745d ./artix7/tile_type_INT_FEEDTHRU_2.json`](./artix7/tile_type_INT_FEEDTHRU_2.json)
|
||||
* [`7f992ab27ef35aded6066064690baa80299280d02dfa911f94a4e7b1a4a54b42 ./artix7/tile_type_INT_INTERFACE_L.json`](./artix7/tile_type_INT_INTERFACE_L.json)
|
||||
* [`1ead2b9f6c42fccaf6a8ee461cb3e6779547fe0802811377591f54b40ce2cbf3 ./artix7/tile_type_INT_INTERFACE_R.json`](./artix7/tile_type_INT_INTERFACE_R.json)
|
||||
* [`335a1441fbdae94463f27b548f1ad43bf0576013fa9fd1dd59f56f699c6cd959 ./artix7/tile_type_INT_L.json`](./artix7/tile_type_INT_L.json)
|
||||
* [`f48b15a421b553c5a5a7b07cd13d85c6ba9281c416d2ef3c3d82225b3aeb1e7e ./artix7/tile_type_INT_R.json`](./artix7/tile_type_INT_R.json)
|
||||
* [`bf4eadb5aaed8794d7a6d924913eacb4e1246b7deb831a76de357d2200ef4ba8 ./artix7/tile_type_IO_INT_INTERFACE_L.json`](./artix7/tile_type_IO_INT_INTERFACE_L.json)
|
||||
* [`73b411ab0c6a64f99e89419d8e4dbd43008642cdc2a5c808cee181b0a78362c5 ./artix7/tile_type_IO_INT_INTERFACE_R.json`](./artix7/tile_type_IO_INT_INTERFACE_R.json)
|
||||
* [`4cabd902bb0c365a5f73517614fb7f6cba68795618dbc2ac8faf89a576a68d14 ./artix7/tile_type_LIOB33.json`](./artix7/tile_type_LIOB33.json)
|
||||
* [`cb9f409f31747dab0dd2e223cd94c0f6cb8bcc42d9e86307d9514fbae9f531a9 ./artix7/tile_type_LIOB33_SING.json`](./artix7/tile_type_LIOB33_SING.json)
|
||||
* [`7b309379d9f838a16267f0ec169f81bacc10c56d34585bdda8c08a0a15ad5206 ./artix7/tile_type_LIOI3.json`](./artix7/tile_type_LIOI3.json)
|
||||
* [`4eff79aab044ef13040f7faa3f58ca142f5d14070c625ec23d0d6246d0c9959c ./artix7/tile_type_LIOI3_SING.json`](./artix7/tile_type_LIOI3_SING.json)
|
||||
* [`151c56730a8a9ab5ec9b647d12e99be6797427e4ee83b0298bb64c7dd180cf6b ./artix7/tile_type_LIOI3_TBYTESRC.json`](./artix7/tile_type_LIOI3_TBYTESRC.json)
|
||||
* [`dbf7d9e7a0037c00cd0293e6179a888061ec3f4de471a739f160b06b35f2d183 ./artix7/tile_type_LIOI3_TBYTETERM.json`](./artix7/tile_type_LIOI3_TBYTETERM.json)
|
||||
* [`c4fcf212d0da1576a4b7592baac2991770b8efa970698f7ee86fa64e7df5850f ./artix7/tile_type_L_TERM_INT.json`](./artix7/tile_type_L_TERM_INT.json)
|
||||
* [`9f1fb838d0ef958ed8ae1f645821efd17490ae905f8bb9c6f4a31e56bf5a260a ./artix7/tile_type_MONITOR_BOT.json`](./artix7/tile_type_MONITOR_BOT.json)
|
||||
* [`8d9ebbe2124c95c29e434669a9f235bb3172342f9954a389c493d5b90de9d2a8 ./artix7/tile_type_MONITOR_MID.json`](./artix7/tile_type_MONITOR_MID.json)
|
||||
* [`e5c8f860810967712fc9bca81b6507b4b745a4097c7a167197cb7e2c32221b79 ./artix7/tile_type_MONITOR_TOP.json`](./artix7/tile_type_MONITOR_TOP.json)
|
||||
* [`ce6b7525f841dc0c345a47509ade7c2e63e501f15375f13ae45ab68d5a963a48 ./artix7/site_type_BSCAN.json`](./artix7/site_type_BSCAN.json)
|
||||
* [`4af72f95cdd44ac39ba343800b34f1fea766de38173fe9683c137e09b9da538e ./artix7/site_type_BUFGCTRL.json`](./artix7/site_type_BUFGCTRL.json)
|
||||
* [`44ac2616c6bd02df6c767b4d75103d20e2afe933b7bf9468c0665cc475d9aaac ./artix7/site_type_BUFHCE.json`](./artix7/site_type_BUFHCE.json)
|
||||
* [`b8fba943d1daba4bf68b60662ecd54d15d2e420844b3c365fccbbf540397e04f ./artix7/site_type_BUFIO.json`](./artix7/site_type_BUFIO.json)
|
||||
* [`a3faa1fa985bb5ee8473992735ee4eb1137d65716e76ca382c8db5679b7e1c0a ./artix7/site_type_BUFMRCE.json`](./artix7/site_type_BUFMRCE.json)
|
||||
* [`d9c702eb3efe272eaccdbac71f132397a8dc2bebb9957ac501c12191d229a415 ./artix7/site_type_BUFR.json`](./artix7/site_type_BUFR.json)
|
||||
* [`918f7d1fa92e0781305ce37ec4a4803efbb19472b165b7a56fa78f254f5df8dc ./artix7/site_type_CAPTURE.json`](./artix7/site_type_CAPTURE.json)
|
||||
* [`74c501f8de850d82eb3f3c9b1e50dfb0c29ead2449b03d85378bef0483219e0f ./artix7/site_type_DCIRESET.json`](./artix7/site_type_DCIRESET.json)
|
||||
* [`7b99edd1b5bfe05ee855348b380647a288355e731f3c91b242f52d821db34d6a ./artix7/site_type_DNA_PORT.json`](./artix7/site_type_DNA_PORT.json)
|
||||
* [`0f07ecfc6e124097bbdd9c2619b190d18f81e1c5903fed2970d6659f488737c7 ./artix7/site_type_DSP48E1.json`](./artix7/site_type_DSP48E1.json)
|
||||
* [`c74665236aca328cc4de4959cbb1727b7a08f13aa01b2870179e3867eb6aaf5d ./artix7/site_type_EFUSE_USR.json`](./artix7/site_type_EFUSE_USR.json)
|
||||
* [`70141a9433b6dd32954f23ae076d92d586453582789ddcd66a5755ef622cb988 ./artix7/site_type_FIFO18E1.json`](./artix7/site_type_FIFO18E1.json)
|
||||
* [`e1b663d21680ca7c4a0e6a3b20f66b836a8a9d1f3da4816aafd2061c9881ecdc ./artix7/site_type_FRAME_ECC.json`](./artix7/site_type_FRAME_ECC.json)
|
||||
* [`84afea9b88a7ed8e799893849e2c46dcdc2a9b783ce8150efebb15e13f8f7b6a ./artix7/site_type_GTPE2_CHANNEL.json`](./artix7/site_type_GTPE2_CHANNEL.json)
|
||||
* [`5599e5df43aea8ab3d18adb1a411ac7c1ceea42801f85122b2c49f71de2d0242 ./artix7/site_type_GTPE2_COMMON.json`](./artix7/site_type_GTPE2_COMMON.json)
|
||||
* [`97f68051d25c4c7a090ba151aa7682d4235677dc8eb7e84fe6577352bbc2eda5 ./artix7/site_type_IBUFDS_GTE2.json`](./artix7/site_type_IBUFDS_GTE2.json)
|
||||
* [`3835f1bfbe1df674a972b133520aa0381ce3f7d076535935d7a6a90be0c6ec3c ./artix7/site_type_ICAP.json`](./artix7/site_type_ICAP.json)
|
||||
* [`ab7bbac6fcb133918525355ef4fa4571cf3ffd43ce0d5adac6b3e93161e205d4 ./artix7/site_type_IDELAYCTRL.json`](./artix7/site_type_IDELAYCTRL.json)
|
||||
* [`9d8f8a7f5374aeb7ecbcb930159e1f7d21d83f3015bb5bb3d3aa444f11b2123c ./artix7/site_type_IDELAYE2.json`](./artix7/site_type_IDELAYE2.json)
|
||||
* [`2420d7e698aaf21ad65d74eb93cd0b944f5ac533dd600378fa626eedd0876abe ./artix7/site_type_ILOGICE3.json`](./artix7/site_type_ILOGICE3.json)
|
||||
* [`81856766758a3b5a1ecec5a27512fbb591e2ddb9021c5aaeca71ddc4e9a6b286 ./artix7/site_type_IN_FIFO.json`](./artix7/site_type_IN_FIFO.json)
|
||||
* [`618e38cee78dc8250a844e2e9fbcf59ad21ecdb7b4c361a7a621642d7dc15917 ./artix7/site_type_IOB33.json`](./artix7/site_type_IOB33.json)
|
||||
* [`2dc8c4858b34913cb2e46141b25f39022b1dafb2b271ef769a3fbc328209543e ./artix7/site_type_IOB33M.json`](./artix7/site_type_IOB33M.json)
|
||||
* [`e0e70aa2e7daf98a8d7d9dc9fca081753ba353bab9955a993edc0acf99331635 ./artix7/site_type_IOB33S.json`](./artix7/site_type_IOB33S.json)
|
||||
* [`6922af5e94c020bf330e088a74c09ad7be09b4264756154dea5769d5631e22bf ./artix7/site_type_IPAD.json`](./artix7/site_type_IPAD.json)
|
||||
* [`56628765dbeb552cb6e1131b47f5cec56cdb1d17abd07f62e1721adbc76d69d3 ./artix7/site_type_MMCME2_ADV.json`](./artix7/site_type_MMCME2_ADV.json)
|
||||
* [`c1d5e2087d3f643f1699659fdb07ffade805f80406193c361ff2cb66f999a8f3 ./artix7/site_type_OLOGICE3.json`](./artix7/site_type_OLOGICE3.json)
|
||||
* [`26a864898c5fccc0713e6c50cc1d979b85c7f80ef283ad7f4bebc390b272a0a0 ./artix7/site_type_OPAD.json`](./artix7/site_type_OPAD.json)
|
||||
* [`79495b1ef561bfaf7046681be864de8b108b00007d2232b600b8fb2b9bd5e8f9 ./artix7/site_type_OUT_FIFO.json`](./artix7/site_type_OUT_FIFO.json)
|
||||
* [`b05d25b6344a6a12efa4ec5ac3daa6715a10c5766d505b2d2920d02cdb8cdd71 ./artix7/site_type_PCIE_2_1.json`](./artix7/site_type_PCIE_2_1.json)
|
||||
* [`a4260d6f3314deff82afb8ff1293a73132302ef22398fb24bed1dc7b1d086b72 ./artix7/site_type_PHASER_IN_PHY.json`](./artix7/site_type_PHASER_IN_PHY.json)
|
||||
* [`5bf9c6cde3fb0e3054fc3b4a3d39a234c0dbddcfc6f70458aa9f3014c7752166 ./artix7/site_type_PHASER_OUT_PHY.json`](./artix7/site_type_PHASER_OUT_PHY.json)
|
||||
* [`c98a21b4d4f832432629982f0595fe503aca5479ecf8f85526308ef1ffa8f681 ./artix7/site_type_PHASER_REF.json`](./artix7/site_type_PHASER_REF.json)
|
||||
* [`0580134f137cf6f0195dd6df59ad63e8bf858a25af2de000742c0140438c5bbf ./artix7/site_type_PHY_CONTROL.json`](./artix7/site_type_PHY_CONTROL.json)
|
||||
* [`9da8e5576ed978fd0796491c16d36853253d58463a04f6697f13bf24df22fe6a ./artix7/site_type_PLLE2_ADV.json`](./artix7/site_type_PLLE2_ADV.json)
|
||||
* [`854c6355e4623de12b3c5fecadfcadbe56ee6909fdcca50e12d541c4d2b34cba ./artix7/site_type_PMV2.json`](./artix7/site_type_PMV2.json)
|
||||
* [`a8ab8f75cf4c5b906de35b7f8cd6f56e22a026d7e8e3dccf368147d182fc6dc2 ./artix7/site_type_RAMB18E1.json`](./artix7/site_type_RAMB18E1.json)
|
||||
* [`a268e5868691d7889be21a12b73761f8904ec2da9011e721da1118f1a768feb0 ./artix7/site_type_RAMBFIFO36E1.json`](./artix7/site_type_RAMBFIFO36E1.json)
|
||||
* [`a172cd5740420c65d891d2a0cfeb2683d6357c30debb14a9e2c97aced3fc814c ./artix7/site_type_SLICEL.json`](./artix7/site_type_SLICEL.json)
|
||||
* [`3810abcfb6b49fc50bd46db80edd07267e4febe54fec261d15f2dc124104c374 ./artix7/site_type_SLICEM.json`](./artix7/site_type_SLICEM.json)
|
||||
* [`0851f78f9189764d7a2598cf596aca27b9bfec59386e9ca8a3e437300e8d17bd ./artix7/site_type_STARTUP.json`](./artix7/site_type_STARTUP.json)
|
||||
* [`7329766c3d005888d7c26e2971eede01b5868561ebf3a2fd79418ede9b8eea7e ./artix7/site_type_TIEOFF.json`](./artix7/site_type_TIEOFF.json)
|
||||
* [`9878d53bf8ee5edaefca55f6f2fbc4688c892d3ee733055b37457f427a1f0d84 ./artix7/site_type_USR_ACCESS.json`](./artix7/site_type_USR_ACCESS.json)
|
||||
* [`2d05c8f9d59638153cc69fdb858b9b0a4ece6827fa47ff3d8022991e0b389776 ./artix7/site_type_XADC.json`](./artix7/site_type_XADC.json)
|
||||
* [`f27c7a1c94c45ffc45db1f743fc36900a946ae6f9bfaf6c192647e48b988073a ./artix7/tileconn.json`](./artix7/tileconn.json)
|
||||
* [`5753b8d2271890815cf886ea46ac71e8023e323ac95bd61ce52d1c87a2c4cfe8 ./artix7/tilegrid.json`](./artix7/tilegrid.json)
|
||||
* [`23cbdbf81c66dc42a59144fd7c528e957ef90e8af2238a762bccf03155126639 ./artix7/tile_type_BRAM_INT_INTERFACE_L.json`](./artix7/tile_type_BRAM_INT_INTERFACE_L.json)
|
||||
* [`398d6be7e17c3983246e6bb63a9ab10d07450efcb826ea9309bac9794ec2105a ./artix7/tile_type_BRAM_INT_INTERFACE_R.json`](./artix7/tile_type_BRAM_INT_INTERFACE_R.json)
|
||||
* [`c374353f2b0dea34b09d506fc0e86f7880530ffb5b5f7b6ffc7e078f9e7f7b00 ./artix7/tile_type_BRAM_L.json`](./artix7/tile_type_BRAM_L.json)
|
||||
* [`4ba88e04247ade6a0c755c67ca13e40f5a4f5c86943250b1ac855fe653924a09 ./artix7/tile_type_BRAM_R.json`](./artix7/tile_type_BRAM_R.json)
|
||||
* [`58dff08cf299ed766fc6653c8c3e4671d7b484ff6e94bbbb4e5eca4512f15a4f ./artix7/tile_type_BRKH_BRAM.json`](./artix7/tile_type_BRKH_BRAM.json)
|
||||
* [`8d554352d645b0d7f006960e05d98d1dd02d235542ae478ca419a3b0ea141475 ./artix7/tile_type_BRKH_B_TERM_INT.json`](./artix7/tile_type_BRKH_B_TERM_INT.json)
|
||||
* [`7db1384b047b106a88e0767a171fd373294bc429e2921c3a5eb3a154eb3f2863 ./artix7/tile_type_BRKH_CLB.json`](./artix7/tile_type_BRKH_CLB.json)
|
||||
* [`68e723c013899559164e2d263eadf3a37e0831cfe48756848958f2266e0f7af3 ./artix7/tile_type_BRKH_CLK.json`](./artix7/tile_type_BRKH_CLK.json)
|
||||
* [`b70653a436820415dc00f8cfead944608b51c4c81a19e22077bb2cfd15ba2945 ./artix7/tile_type_BRKH_CMT.json`](./artix7/tile_type_BRKH_CMT.json)
|
||||
* [`3ae1b790c11f7b2352d6b4bc116b103d9095a463c20593dc9072666b0998279e ./artix7/tile_type_BRKH_DSP_L.json`](./artix7/tile_type_BRKH_DSP_L.json)
|
||||
* [`e6bda5554eb630e2d499ced9f437cdcf03b5d04d8b8922bd3a0261d693e10ac1 ./artix7/tile_type_BRKH_DSP_R.json`](./artix7/tile_type_BRKH_DSP_R.json)
|
||||
* [`4e8527fcc4b2cfc4f56e07c470bdd16770a2917b1054efaf244115549471dd2d ./artix7/tile_type_BRKH_GTX.json`](./artix7/tile_type_BRKH_GTX.json)
|
||||
* [`692353c7c69045023ec316a28c9ebb9d0c5bffe448053b49ab560b1251104e48 ./artix7/tile_type_BRKH_INT.json`](./artix7/tile_type_BRKH_INT.json)
|
||||
* [`0db75fcd5482f6882ba2dad8d6905a6720ba123f62207fc1248b13b5351ef84b ./artix7/tile_type_BRKH_TERM_INT.json`](./artix7/tile_type_BRKH_TERM_INT.json)
|
||||
* [`c7d4179bb2ee3cbe84134395b035a5a380ea4cb872c3b603886903ae290918f8 ./artix7/tile_type_B_TERM_INT.json`](./artix7/tile_type_B_TERM_INT.json)
|
||||
* [`c62ecc3b04de188050b8cc0d0239294915bbf1c08f5f840e44b4e36cfa8206d3 ./artix7/tile_type_CFG_CENTER_BOT.json`](./artix7/tile_type_CFG_CENTER_BOT.json)
|
||||
* [`7ad3733b8b2acaceec349fa2dc82cda1451cb3ccbdddf4145aaf99146faf3f91 ./artix7/tile_type_CFG_CENTER_MID.json`](./artix7/tile_type_CFG_CENTER_MID.json)
|
||||
* [`88a6dc6071e4e5ba712acd3c1b87f9fac4ee11bcc4adfc1540a87a8b912ed96a ./artix7/tile_type_CFG_CENTER_TOP.json`](./artix7/tile_type_CFG_CENTER_TOP.json)
|
||||
* [`3dc931d3d3c1b416201a77c9ae24ddc4c3e6b5542f969d05e31453301874be44 ./artix7/tile_type_CLBLL_L.json`](./artix7/tile_type_CLBLL_L.json)
|
||||
* [`4ce0644191f3576c18c8ef0b748b1161a7e2b1685f5f8cdfb7357dd1b1a1e0be ./artix7/tile_type_CLBLL_R.json`](./artix7/tile_type_CLBLL_R.json)
|
||||
* [`43635bed6f425a5014f224ea1c8cf79b71e77a75201c2b3b2d010731aa04366e ./artix7/tile_type_CLBLM_L.json`](./artix7/tile_type_CLBLM_L.json)
|
||||
* [`d1bb7931139e2122dad06ab1a9b5bd38fc94e1215030ba88a9630dd7f6439ce5 ./artix7/tile_type_CLBLM_R.json`](./artix7/tile_type_CLBLM_R.json)
|
||||
* [`ff795e0ce7fd5411d581ea080530f93cc3eaff304cb5d3abba61ee15a4e63d31 ./artix7/tile_type_CLK_BUFG_BOT_R.json`](./artix7/tile_type_CLK_BUFG_BOT_R.json)
|
||||
* [`d6eb7190dec7b173db34979729b1051312aad5bb768e2f48db147499de4f4bdc ./artix7/tile_type_CLK_BUFG_REBUF.json`](./artix7/tile_type_CLK_BUFG_REBUF.json)
|
||||
* [`e70253892aaf28cbd15c26ea6882121267fd205524e383e2368c9bf1ea40ba45 ./artix7/tile_type_CLK_BUFG_TOP_R.json`](./artix7/tile_type_CLK_BUFG_TOP_R.json)
|
||||
* [`53c5abb08ea6155d5e04365c1c61475d39972ab1aadfcd2164c3e6b16adae9a1 ./artix7/tile_type_CLK_FEED.json`](./artix7/tile_type_CLK_FEED.json)
|
||||
* [`0473ca7e14c9ebaa721a5f8b9a8cea0557dfe9c1049b34ea49e5c95364043f8c ./artix7/tile_type_CLK_HROW_BOT_R.json`](./artix7/tile_type_CLK_HROW_BOT_R.json)
|
||||
* [`2cafe25a81ef45d27de3da007ab8d1210a931fb9162a7bcba64b31d0061c6d8c ./artix7/tile_type_CLK_HROW_TOP_R.json`](./artix7/tile_type_CLK_HROW_TOP_R.json)
|
||||
* [`ac497f9fe63fd1861cbcf5c246ae040f88dd1928b8ef4c26a8f1b8390b80de3c ./artix7/tile_type_CLK_MTBF2.json`](./artix7/tile_type_CLK_MTBF2.json)
|
||||
* [`99f6b806b0052ccb51eea9ad7ed16eceeadf0121b7024e9708831b39b4e45c83 ./artix7/tile_type_CLK_PMV2.json`](./artix7/tile_type_CLK_PMV2.json)
|
||||
* [`3a7a0140dcdd3b88763f2560518ab271851cbac1e774c5ad51ee7ec46d8b3a7b ./artix7/tile_type_CLK_PMV2_SVT.json`](./artix7/tile_type_CLK_PMV2_SVT.json)
|
||||
* [`61a3b4046747c43e348336d26308ffadde05ff912fe223d0580cb177ad998df9 ./artix7/tile_type_CLK_PMVIOB.json`](./artix7/tile_type_CLK_PMVIOB.json)
|
||||
* [`084ad856f296c2789da3da7e1c1e1d73e5f6a6492e94cb501c5ad240f51da5c6 ./artix7/tile_type_CLK_PMV.json`](./artix7/tile_type_CLK_PMV.json)
|
||||
* [`6ce10a4f95906b172604498bf084063a2578b8cb66bd03a898c3e578a036d2ed ./artix7/tile_type_CLK_TERM.json`](./artix7/tile_type_CLK_TERM.json)
|
||||
* [`8d695ca4e0ad360369e74c524ac33858ea2279620b0cd3b9f4776c1fb3820500 ./artix7/tile_type_CMT_FIFO_L.json`](./artix7/tile_type_CMT_FIFO_L.json)
|
||||
* [`ca326fcf734b97a79a830d96926411405c9dcca60dce9fe4ee7e4f95ab343ca0 ./artix7/tile_type_CMT_FIFO_R.json`](./artix7/tile_type_CMT_FIFO_R.json)
|
||||
* [`8d8a67418b747bbe174da118b646df39112870afda50105f9063debb2a1a7a11 ./artix7/tile_type_CMT_PMV.json`](./artix7/tile_type_CMT_PMV.json)
|
||||
* [`54754d5c4a7a88417edeef6d8fe4c551e7e4eca9557f4166b8114ead8841af13 ./artix7/tile_type_CMT_PMV_L.json`](./artix7/tile_type_CMT_PMV_L.json)
|
||||
* [`fb63c41888c6cd33bb5e49c40e1b03d97c2d624d615b1aaf66cda0f83c1c6553 ./artix7/tile_type_CMT_TOP_L_LOWER_B.json`](./artix7/tile_type_CMT_TOP_L_LOWER_B.json)
|
||||
* [`64091aa4168180ea71a264edf76474958ee9e434346a026c6929318e53e7b62e ./artix7/tile_type_CMT_TOP_L_LOWER_T.json`](./artix7/tile_type_CMT_TOP_L_LOWER_T.json)
|
||||
* [`92e8d6f7fed3ebfcdfd0d024e07d1bb3b023f7fb6d838c90627459c569b5e5d1 ./artix7/tile_type_CMT_TOP_L_UPPER_B.json`](./artix7/tile_type_CMT_TOP_L_UPPER_B.json)
|
||||
* [`cc46d63359e743e01ed64ff6200bdf8574a2bbd3840e43ad11e42e86c838e7c0 ./artix7/tile_type_CMT_TOP_L_UPPER_T.json`](./artix7/tile_type_CMT_TOP_L_UPPER_T.json)
|
||||
* [`1cc221de8d0a9ff45291bce1f0a9450ea7992d9b7f1f814ea07e777eef694a85 ./artix7/tile_type_CMT_TOP_R_LOWER_B.json`](./artix7/tile_type_CMT_TOP_R_LOWER_B.json)
|
||||
* [`3da4fb7ae07d374bb165a041b298c012edd0657af3c05bcd1fa22420a23c0b2b ./artix7/tile_type_CMT_TOP_R_LOWER_T.json`](./artix7/tile_type_CMT_TOP_R_LOWER_T.json)
|
||||
* [`4d88b80efa4d8ac8c477de8c078469f98d352643ec1b1faafb5006ee6830320c ./artix7/tile_type_CMT_TOP_R_UPPER_B.json`](./artix7/tile_type_CMT_TOP_R_UPPER_B.json)
|
||||
* [`7a2a6004457b3828aa3d2f31b65b87e6b74b4500f19482ef15305ab2f75d8616 ./artix7/tile_type_CMT_TOP_R_UPPER_T.json`](./artix7/tile_type_CMT_TOP_R_UPPER_T.json)
|
||||
* [`0fb92c622d4d7b7b7bc3461452d8d2d1a650ad58d6c4528b517fe73489ff209c ./artix7/tile_type_DSP_L.json`](./artix7/tile_type_DSP_L.json)
|
||||
* [`8d9c404edad111e9592a9cce0ee4cdcfb7a68685fc025c7da3f717a4fd685281 ./artix7/tile_type_DSP_R.json`](./artix7/tile_type_DSP_R.json)
|
||||
* [`1641dac319b5a3156198998d4e72bbbc4b74f481fd1a162d5ab35e50ba38a5dd ./artix7/tile_type_GTP_CHANNEL_0.json`](./artix7/tile_type_GTP_CHANNEL_0.json)
|
||||
* [`105fb1227f5af2fb252f96c4c356fb4bf46bff8647173ed3873e45cca5bb2206 ./artix7/tile_type_GTP_CHANNEL_1.json`](./artix7/tile_type_GTP_CHANNEL_1.json)
|
||||
* [`1af7d5cdc6db523d7a4a22b3f51d8264c70442cef641cca20394e8061fd70701 ./artix7/tile_type_GTP_CHANNEL_2.json`](./artix7/tile_type_GTP_CHANNEL_2.json)
|
||||
* [`4d017ee89d56b4d2fe22186e5e8c253a8bdf15c52ef530fb5d975e7e4d407fe3 ./artix7/tile_type_GTP_CHANNEL_3.json`](./artix7/tile_type_GTP_CHANNEL_3.json)
|
||||
* [`414ba97182006f141d62f568305fcbd2d240010a952e0638f9a3ee7fb779d500 ./artix7/tile_type_GTP_COMMON.json`](./artix7/tile_type_GTP_COMMON.json)
|
||||
* [`ce0bba53fc3feef5d61d7556702334631488155f8b4d40ae9b182f3bd69b0c70 ./artix7/tile_type_GTP_INT_INTERFACE.json`](./artix7/tile_type_GTP_INT_INTERFACE.json)
|
||||
* [`e5bd0bb1b66d2e130723e02fdaa7074a4ea712afa27c9a650cfb4f6774694cd9 ./artix7/tile_type_HCLK_BRAM.json`](./artix7/tile_type_HCLK_BRAM.json)
|
||||
* [`ddc3572bbbf2372400d570e2c47f9b4cc52dda1703b19685c5670f891d989513 ./artix7/tile_type_HCLK_CLB.json`](./artix7/tile_type_HCLK_CLB.json)
|
||||
* [`0463384162afc69a33beb85f5e7f31756a5e5374eca5ea6083ebd3007dab1821 ./artix7/tile_type_HCLK_CMT.json`](./artix7/tile_type_HCLK_CMT.json)
|
||||
* [`7ca0b55ef0c69b203e63d68a4c9ce9f9547b76ab472c7ef7728b24a8f27ad86c ./artix7/tile_type_HCLK_CMT_L.json`](./artix7/tile_type_HCLK_CMT_L.json)
|
||||
* [`0259b574ac3aea85521a3f3a8a81f4a3690267fff4732becfae86002b6c230ff ./artix7/tile_type_HCLK_DSP_L.json`](./artix7/tile_type_HCLK_DSP_L.json)
|
||||
* [`f189edadd53ac962b40bfd3bb590afb002988c9ab2e2dc4d40e3e46bcd20d19b ./artix7/tile_type_HCLK_DSP_R.json`](./artix7/tile_type_HCLK_DSP_R.json)
|
||||
* [`a0bb7bb3de64bf59b4c94fbfa965548dd0541804e88dae44e1ee838417fe9f5b ./artix7/tile_type_HCLK_FEEDTHRU_1.json`](./artix7/tile_type_HCLK_FEEDTHRU_1.json)
|
||||
* [`2fb27ee87a8e7c479fab639f1e6f152c798400a6d867353c578f65bc052cc39c ./artix7/tile_type_HCLK_FEEDTHRU_2.json`](./artix7/tile_type_HCLK_FEEDTHRU_2.json)
|
||||
* [`b907b961ecf05df2bad676048dda29df7849428e11295c13dacf9295047c944f ./artix7/tile_type_HCLK_FIFO_L.json`](./artix7/tile_type_HCLK_FIFO_L.json)
|
||||
* [`af83da793077a964cd35ec8c41f368d6524e89f54afbf1638cd9934dc101c3c3 ./artix7/tile_type_HCLK_GTX.json`](./artix7/tile_type_HCLK_GTX.json)
|
||||
* [`cf6479d8fb961c1b1bd8162ffd06b0dc68b6a1df8c9569e03776f99fd98b32a6 ./artix7/tile_type_HCLK_INT_INTERFACE.json`](./artix7/tile_type_HCLK_INT_INTERFACE.json)
|
||||
* [`d31da1db21ce8db5e196c490771f91b4a5b23f8571bcde45951ad4be43985f8d ./artix7/tile_type_HCLK_IOB.json`](./artix7/tile_type_HCLK_IOB.json)
|
||||
* [`e54cb4db56c4a16f65ad1b0668ca4b5e534fe16bfc9eb9be3acf023bb6512d9a ./artix7/tile_type_HCLK_IOI3.json`](./artix7/tile_type_HCLK_IOI3.json)
|
||||
* [`10fb0192948ceeeeac7ad53b4650c4e1a2b41da86c18aba4713d3c03bd0e793d ./artix7/tile_type_HCLK_L_BOT_UTURN.json`](./artix7/tile_type_HCLK_L_BOT_UTURN.json)
|
||||
* [`68c48d5e08bb96be35cc5f33d8d4810bbb9bb19edcc4a5c004d3951c7d2ce048 ./artix7/tile_type_HCLK_L.json`](./artix7/tile_type_HCLK_L.json)
|
||||
* [`dd66164144a01916fc9dd745bf26aa6b98b5cd6e763ba8746d6cc4bc7edf9c15 ./artix7/tile_type_HCLK_R_BOT_UTURN.json`](./artix7/tile_type_HCLK_R_BOT_UTURN.json)
|
||||
* [`2466b03f83efb51ecc71a3a9965d0766a5c6bfcf2e1a16c81435bcda3a994d2e ./artix7/tile_type_HCLK_R.json`](./artix7/tile_type_HCLK_R.json)
|
||||
* [`81334d3a3c651cf9855d53d306fdb6bfa97c11f2c79965b12b4dcc229a5515b5 ./artix7/tile_type_HCLK_TERM_GTX.json`](./artix7/tile_type_HCLK_TERM_GTX.json)
|
||||
* [`6c49e725a68dbb0154d66196e9f5ca4d6b3cfef9dd8474a2bc0a13f8e0e064bd ./artix7/tile_type_HCLK_TERM.json`](./artix7/tile_type_HCLK_TERM.json)
|
||||
* [`fb599f521e49420293df721bdc0229a9311e1af1bac57beeb7014450eac7b83e ./artix7/tile_type_HCLK_VBRK.json`](./artix7/tile_type_HCLK_VBRK.json)
|
||||
* [`6e90a5edd781fc302bcea34e87a662dc956ca686f055b6a058411f5fc32a4b00 ./artix7/tile_type_HCLK_VFRAME.json`](./artix7/tile_type_HCLK_VFRAME.json)
|
||||
* [`25132353de6d4eabcb794574f435de7f020f8dc845f4cadf0fae68069a9fec64 ./artix7/tile_type_INT_FEEDTHRU_1.json`](./artix7/tile_type_INT_FEEDTHRU_1.json)
|
||||
* [`65170f7966fdc840c19ccc79022f2f5e243e42962e07045fb234b79c0c7d1372 ./artix7/tile_type_INT_FEEDTHRU_2.json`](./artix7/tile_type_INT_FEEDTHRU_2.json)
|
||||
* [`b98fb0ac50a29ac7abe305f8c5e59472559fb0ee74a99bbcca5f3066b897dca7 ./artix7/tile_type_INT_INTERFACE_L.json`](./artix7/tile_type_INT_INTERFACE_L.json)
|
||||
* [`736f7f9daa4aa44fb0bb4310718f60e6e12eb06baf708fb9c66115c0fee7ae94 ./artix7/tile_type_INT_INTERFACE_R.json`](./artix7/tile_type_INT_INTERFACE_R.json)
|
||||
* [`78df816d81ee1674dbf68a48512bc51907a5f331c125687c084342084b884671 ./artix7/tile_type_INT_L.json`](./artix7/tile_type_INT_L.json)
|
||||
* [`2ef4700cd57a203491513b99649e3fba4bb59452e7cd4dbdbc1527270d0ac300 ./artix7/tile_type_INT_R.json`](./artix7/tile_type_INT_R.json)
|
||||
* [`503a07ab48e8db8b1a80593493fbf2983649d05574de7d666544600277173060 ./artix7/tile_type_IO_INT_INTERFACE_L.json`](./artix7/tile_type_IO_INT_INTERFACE_L.json)
|
||||
* [`89f00874a8243f5118047aa3cf4b917a3f671960e51e66d5e949e328f0a53cd6 ./artix7/tile_type_IO_INT_INTERFACE_R.json`](./artix7/tile_type_IO_INT_INTERFACE_R.json)
|
||||
* [`6a372d07581a12adcea94225f89e87918615fba41b5123d5f4e3a50244105aec ./artix7/tile_type_LIOB33.json`](./artix7/tile_type_LIOB33.json)
|
||||
* [`104a22e87af4862f9f273c794b2a70c3fea707691bbad5e21c27ca2003b3da53 ./artix7/tile_type_LIOB33_SING.json`](./artix7/tile_type_LIOB33_SING.json)
|
||||
* [`4e18efec126df85ec3ba82f3c5c6c2367838771fa295d5cc58c2d5be783ac457 ./artix7/tile_type_LIOI3.json`](./artix7/tile_type_LIOI3.json)
|
||||
* [`6cdba229c0f794bbb18feef681295f42ccc17ba2bfd93c6aba1598b17d91ab3f ./artix7/tile_type_LIOI3_SING.json`](./artix7/tile_type_LIOI3_SING.json)
|
||||
* [`22d5284a63ab825b835fd7390bdb7b7e75058c70421c06c1d031009d2e36a595 ./artix7/tile_type_LIOI3_TBYTESRC.json`](./artix7/tile_type_LIOI3_TBYTESRC.json)
|
||||
* [`560c24b9e273bb10bb1714a8c36fe94d7c7338ad03682fce44b5b231a6b95892 ./artix7/tile_type_LIOI3_TBYTETERM.json`](./artix7/tile_type_LIOI3_TBYTETERM.json)
|
||||
* [`2edaca72962c5fdee5ebeacc864983f37b4b27d1ecaf578579ecd50ffea5533b ./artix7/tile_type_L_TERM_INT.json`](./artix7/tile_type_L_TERM_INT.json)
|
||||
* [`d01adebf326e7fe131103aaf3b96144d29ed08c83744beba2d359728fa0033f1 ./artix7/tile_type_MONITOR_BOT.json`](./artix7/tile_type_MONITOR_BOT.json)
|
||||
* [`cacd78ff41b890185a3711546d735fcbcb6d292bda9a5df229334468b620ea9e ./artix7/tile_type_MONITOR_MID.json`](./artix7/tile_type_MONITOR_MID.json)
|
||||
* [`5ca3d726acf565d981e8cd13dd556150fc9c7590d9168e2254485fadead62de1 ./artix7/tile_type_MONITOR_TOP.json`](./artix7/tile_type_MONITOR_TOP.json)
|
||||
* [`6b16e9202757be322b72cdcd73f45a1e61252444ef4ee6557272fc8361d87557 ./artix7/tile_type_NULL.json`](./artix7/tile_type_NULL.json)
|
||||
* [`3c1d65f24e5a14adf1fad58418d9d80a0fc501767c7c57ae6b03c761d9e6ec49 ./artix7/tile_type_PCIE_BOT.json`](./artix7/tile_type_PCIE_BOT.json)
|
||||
* [`e88f6157dd103e57fb6a09ad61e08e3390491f3e2e680ed158851761b416b297 ./artix7/tile_type_PCIE_INT_INTERFACE_L.json`](./artix7/tile_type_PCIE_INT_INTERFACE_L.json)
|
||||
* [`1ba5597c9b4759001c507d6cde338b8ce6ffeba1cd303b3332a34a909eae6ada ./artix7/tile_type_PCIE_INT_INTERFACE_R.json`](./artix7/tile_type_PCIE_INT_INTERFACE_R.json)
|
||||
* [`8416c9dbcf405e6570fa2f50cc8e10f25f38017297e59f2170d2dbdbb2d75cb4 ./artix7/tile_type_PCIE_BOT.json`](./artix7/tile_type_PCIE_BOT.json)
|
||||
* [`1d68ae227a82698f42ae74c5f653fc0440089a69a1fe06fd9fc2919515f27a5a ./artix7/tile_type_PCIE_INT_INTERFACE_L.json`](./artix7/tile_type_PCIE_INT_INTERFACE_L.json)
|
||||
* [`03edb2ba1c12c0066e22db0e61a70291be274520d1867a15091736592915da96 ./artix7/tile_type_PCIE_INT_INTERFACE_R.json`](./artix7/tile_type_PCIE_INT_INTERFACE_R.json)
|
||||
* [`e39fb1e8b8c9d0d9da3307a260fee2bf05ad0f6dfa9456b90a031893b7131e2e ./artix7/tile_type_PCIE_NULL.json`](./artix7/tile_type_PCIE_NULL.json)
|
||||
* [`6916ac8353f91f6ef993cde1accb0f4c23e4f0530864a211b09e2dc002ec8f07 ./artix7/tile_type_PCIE_TOP.json`](./artix7/tile_type_PCIE_TOP.json)
|
||||
* [`08e94d8c944671afa5fb5f3ba934b94d455213ecb8f0561f74b01a4579307ca9 ./artix7/tile_type_RIOB33.json`](./artix7/tile_type_RIOB33.json)
|
||||
* [`630e9e7920452cbb1bb3be49ca3cc4d2df84c55376891319d718bb73a1a44560 ./artix7/tile_type_RIOB33_SING.json`](./artix7/tile_type_RIOB33_SING.json)
|
||||
* [`dee0eac7b1fd18fdafe9b6707f17e3aaaafdf3d114e975751842824043413f79 ./artix7/tile_type_RIOI3.json`](./artix7/tile_type_RIOI3.json)
|
||||
* [`e9a298be79752276ff2bc65aacf0a772e46eab6ef97993181dbd1468ee4bfffa ./artix7/tile_type_RIOI3_SING.json`](./artix7/tile_type_RIOI3_SING.json)
|
||||
* [`811820d57f2b09a2da967f27721e2fae0067ce1ed48e00e84082aa909f279177 ./artix7/tile_type_RIOI3_TBYTESRC.json`](./artix7/tile_type_RIOI3_TBYTESRC.json)
|
||||
* [`071c62417007e1c5769a1e094da3e3920051e222066248a3a496af471f11a4e3 ./artix7/tile_type_RIOI3_TBYTETERM.json`](./artix7/tile_type_RIOI3_TBYTETERM.json)
|
||||
* [`1b0a39d14effc60a06ad9b395c2a5991fd961a12c029b62864d8d3cff89ba9a6 ./artix7/tile_type_R_TERM_INT_GTX.json`](./artix7/tile_type_R_TERM_INT_GTX.json)
|
||||
* [`f2ad48f977bf23568f1e46b19c71bf92307199ef674a948804e35b3f5ebd586a ./artix7/tile_type_R_TERM_INT.json`](./artix7/tile_type_R_TERM_INT.json)
|
||||
* [`84fae385439211f2c3020e7fda6bcafdf8173d5a7d40493c3bb2e8145eb13474 ./artix7/tile_type_TERM_CMT.json`](./artix7/tile_type_TERM_CMT.json)
|
||||
* [`45b4dd6d5936e5d8e554417006bef838a5dcc93fca9e1a1928a5fc57ffc4498c ./artix7/tile_type_T_TERM_INT.json`](./artix7/tile_type_T_TERM_INT.json)
|
||||
* [`27efff498583b8a2d6a488a28036f907e0849e8ed7b28c9bb19df5376016815a ./artix7/tile_type_VBRK_EXT.json`](./artix7/tile_type_VBRK_EXT.json)
|
||||
* [`fd0b5a76321e846df69abd82062db6ee6c0ebace89c9c3d0bb09722ef2de999e ./artix7/tile_type_VBRK.json`](./artix7/tile_type_VBRK.json)
|
||||
* [`3b1f73177e0f162741cd791b01da13b9d5baf1d16bac36bdcbec1ea3047f388f ./artix7/tile_type_VFRAME.json`](./artix7/tile_type_VFRAME.json)
|
||||
* [`32813a6587869bfb8d46bb75c175629cab27fd143735dce1c88407c104127c37 ./artix7/tile_type_PCIE_TOP.json`](./artix7/tile_type_PCIE_TOP.json)
|
||||
* [`0a97051287ba6720dbd7d44d8b74f57bfd7b9cef6a700681a3800c7300959442 ./artix7/tile_type_RIOB33.json`](./artix7/tile_type_RIOB33.json)
|
||||
* [`e74682cd2638d8e6a476bc49d2a0177734cade73dfe00ccb923469a782187e14 ./artix7/tile_type_RIOB33_SING.json`](./artix7/tile_type_RIOB33_SING.json)
|
||||
* [`33295c871056be2412111a7c6eaffb66bcf44fb7deb331d2f4d4d98904a83971 ./artix7/tile_type_RIOI3.json`](./artix7/tile_type_RIOI3.json)
|
||||
* [`f60bb64d60ebe92ccf03a033ff7d9d49007d31fafb3e4e8b1f44f375b0889ef4 ./artix7/tile_type_RIOI3_SING.json`](./artix7/tile_type_RIOI3_SING.json)
|
||||
* [`e0c9d75e9b9d535e026e5eecd2f86e54437fe2c1d6c3a3f888167c13c2e1d9be ./artix7/tile_type_RIOI3_TBYTESRC.json`](./artix7/tile_type_RIOI3_TBYTESRC.json)
|
||||
* [`ed9a123faa8c318f58f61188224e585cdbf999a82a0a25859fa0720a746da585 ./artix7/tile_type_RIOI3_TBYTETERM.json`](./artix7/tile_type_RIOI3_TBYTETERM.json)
|
||||
* [`d6d448dd7318d2cb0f7abb0e4e1b8b9a159d68c827b2351a558a7fe43130c3eb ./artix7/tile_type_R_TERM_INT_GTX.json`](./artix7/tile_type_R_TERM_INT_GTX.json)
|
||||
* [`9eff91d226a28e236925be86626f9040f26dbbe23823126165746d7a6d894ce2 ./artix7/tile_type_R_TERM_INT.json`](./artix7/tile_type_R_TERM_INT.json)
|
||||
* [`a270ef5c8ba5f93ff7c9497eabb4dd7c728b699097b475c542412866a1ba3f98 ./artix7/tile_type_TERM_CMT.json`](./artix7/tile_type_TERM_CMT.json)
|
||||
* [`ba446c62c285707a6d6ea5c0a448c87e397610cea7c4cd4dc6178ed76e67dc0b ./artix7/tile_type_T_TERM_INT.json`](./artix7/tile_type_T_TERM_INT.json)
|
||||
* [`515d30eeb5f0f56f388e1506f5e14027ddca3a77b1c1e4cb718a9d632c3b7968 ./artix7/tile_type_VBRK_EXT.json`](./artix7/tile_type_VBRK_EXT.json)
|
||||
* [`c12400cade94c3aa53745dd7b0c4d2deade5f4e490551590599c7a956d0a96f5 ./artix7/tile_type_VBRK.json`](./artix7/tile_type_VBRK.json)
|
||||
* [`dc74eb4a4bb808cf1fea364b4d37f67bca26f39a4a064f1b821200aa861e34d4 ./artix7/tile_type_VFRAME.json`](./artix7/tile_type_VFRAME.json)
|
||||
* [`ef0724733da87455426a0f833642d96e9d206d047f4eb97072c3093f80c40d7d ./artix7/xc7a35tcpg236-1.yaml`](./artix7/xc7a35tcpg236-1.yaml)
|
||||
* [`41c360b1e2f7e08b9051f1160a34954ce4c05a445a07f226f1f4059caf1fa1d3 ./artix7/xc7a50tfgg484-1.yaml`](./artix7/xc7a50tfgg484-1.yaml)
|
||||
|
||||
|
|
@ -277,7 +279,7 @@ Results have checksums;
|
|||
|
||||
### Settings
|
||||
|
||||
Created using following [settings.sh (sha256: 2daf6a69dd6d20df7b1273ff43c5c340abe36f8229d297646865edcfd91eff18)](https://github.com/SymbiFlow/prjxray/blob/bba5c899ddb7917fe5d34675a05abfb9c4db8f51/database/kintex7/settings.sh)
|
||||
Created using following [settings.sh (sha256: 2daf6a69dd6d20df7b1273ff43c5c340abe36f8229d297646865edcfd91eff18)](https://github.com/SymbiFlow/prjxray/blob/feb1a2ca7b137befa1e4e1fe65ab1f70f2b8fcfe/database/kintex7/settings.sh)
|
||||
```shell
|
||||
export XRAY_DATABASE="kintex7"
|
||||
export XRAY_PART="xc7k70tfbg676-2"
|
||||
|
|
|
|||
|
|
@ -0,0 +1,8 @@
|
|||
HCLK.HCLK_CK_INOUT_L0.HCLK_CK_BUFHCLK8 always
|
||||
HCLK.HCLK_CK_INOUT_L1.HCLK_CK_BUFHCLK9 always
|
||||
HCLK.HCLK_CK_INOUT_L2.HCLK_CK_BUFHCLK10 always
|
||||
HCLK.HCLK_CK_INOUT_L3.HCLK_CK_BUFHCLK11 always
|
||||
HCLK.HCLK_CK_INOUT_L4.HCLK_CK_BUFRCLK0 always
|
||||
HCLK.HCLK_CK_INOUT_L5.HCLK_CK_BUFRCLK1 always
|
||||
HCLK.HCLK_CK_INOUT_L6.HCLK_CK_BUFRCLK2 always
|
||||
HCLK.HCLK_CK_INOUT_L7.HCLK_CK_BUFRCLK3 always
|
||||
|
|
@ -0,0 +1,8 @@
|
|||
HCLK.HCLK_CK_INOUT_R0.HCLK_CK_BUFHCLK0 always
|
||||
HCLK.HCLK_CK_INOUT_R1.HCLK_CK_BUFHCLK1 always
|
||||
HCLK.HCLK_CK_INOUT_R2.HCLK_CK_BUFHCLK2 always
|
||||
HCLK.HCLK_CK_INOUT_R3.HCLK_CK_BUFHCLK3 always
|
||||
HCLK.HCLK_CK_INOUT_R4.HCLK_CK_BUFHCLK4 always
|
||||
HCLK.HCLK_CK_INOUT_R5.HCLK_CK_BUFHCLK5 always
|
||||
HCLK.HCLK_CK_INOUT_R6.HCLK_CK_BUFHCLK6 always
|
||||
HCLK.HCLK_CK_INOUT_R7.HCLK_CK_BUFHCLK7 always
|
||||
|
|
@ -1,39 +1,39 @@
|
|||
{
|
||||
"type": "BSCAN",
|
||||
"site_pips": {},
|
||||
"site_pins": {
|
||||
"UPDATE": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DRCK": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TCK": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"RESET": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SHIFT": {
|
||||
"RUNTEST": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TMS": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"RUNTEST": {
|
||||
"TDO": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CAPTURE": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"RESET": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TDI": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DRCK": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"UPDATE": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SHIFT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SEL": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TDO": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TDI": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CAPTURE": {
|
||||
"TCK": {
|
||||
"direction": "OUT"
|
||||
}
|
||||
},
|
||||
"site_pips": {}
|
||||
}
|
||||
}
|
||||
|
|
@ -1,37 +1,12 @@
|
|||
{
|
||||
"type": "BUFGCTRL",
|
||||
"site_pins": {
|
||||
"IGNORE1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CE0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"S0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"I1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"IGNORE0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"I0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CE1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"S1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O": {
|
||||
"direction": "OUT"
|
||||
}
|
||||
},
|
||||
"site_pips": {
|
||||
"S1INV:S1_B": {
|
||||
"from_pin": "S1_B",
|
||||
"IGNORE0INV:IGNORE0": {
|
||||
"from_pin": "IGNORE0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"S0INV:S0": {
|
||||
"from_pin": "S0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"CE0INV:CE0_B": {
|
||||
|
|
@ -42,6 +17,22 @@
|
|||
"from_pin": "S0_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"IGNORE0INV:IGNORE0_B": {
|
||||
"from_pin": "IGNORE0_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"CE0INV:CE0": {
|
||||
"from_pin": "CE0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"S1INV:S1_B": {
|
||||
"from_pin": "S1_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"CE1INV:CE1_B": {
|
||||
"from_pin": "CE1_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"CE1INV:CE1": {
|
||||
"from_pin": "CE1",
|
||||
"to_pin": "OUT"
|
||||
|
|
@ -50,33 +41,42 @@
|
|||
"from_pin": "S1",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"IGNORE0INV:IGNORE0": {
|
||||
"from_pin": "IGNORE0",
|
||||
"IGNORE1INV:IGNORE1": {
|
||||
"from_pin": "IGNORE1",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"IGNORE1INV:IGNORE1_B": {
|
||||
"from_pin": "IGNORE1_B",
|
||||
"to_pin": "OUT"
|
||||
}
|
||||
},
|
||||
"site_pins": {
|
||||
"CE0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"S0INV:S0": {
|
||||
"from_pin": "S0",
|
||||
"to_pin": "OUT"
|
||||
"CE1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"IGNORE0INV:IGNORE0_B": {
|
||||
"from_pin": "IGNORE0_B",
|
||||
"to_pin": "OUT"
|
||||
"I0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"IGNORE1INV:IGNORE1": {
|
||||
"from_pin": "IGNORE1",
|
||||
"to_pin": "OUT"
|
||||
"I1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CE1INV:CE1_B": {
|
||||
"from_pin": "CE1_B",
|
||||
"to_pin": "OUT"
|
||||
"IGNORE0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CE0INV:CE0": {
|
||||
"from_pin": "CE0",
|
||||
"to_pin": "OUT"
|
||||
"S1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"IGNORE1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"S0": {
|
||||
"direction": "IN"
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -1,16 +1,5 @@
|
|||
{
|
||||
"type": "BUFHCE",
|
||||
"site_pins": {
|
||||
"CE": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"I": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O": {
|
||||
"direction": "OUT"
|
||||
}
|
||||
},
|
||||
"site_pips": {
|
||||
"CEINV:CE": {
|
||||
"from_pin": "CE",
|
||||
|
|
@ -20,5 +9,16 @@
|
|||
"from_pin": "CE_B",
|
||||
"to_pin": "OUT"
|
||||
}
|
||||
},
|
||||
"site_pins": {
|
||||
"I": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CE": {
|
||||
"direction": "IN"
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -1,5 +1,6 @@
|
|||
{
|
||||
"type": "BUFIO",
|
||||
"site_pips": {},
|
||||
"site_pins": {
|
||||
"I": {
|
||||
"direction": "IN"
|
||||
|
|
@ -7,6 +8,5 @@
|
|||
"O": {
|
||||
"direction": "OUT"
|
||||
}
|
||||
},
|
||||
"site_pips": {}
|
||||
}
|
||||
}
|
||||
|
|
@ -1,16 +1,5 @@
|
|||
{
|
||||
"type": "BUFMRCE",
|
||||
"site_pins": {
|
||||
"CE": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"I": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O": {
|
||||
"direction": "OUT"
|
||||
}
|
||||
},
|
||||
"site_pips": {
|
||||
"CEINV:CE": {
|
||||
"from_pin": "CE",
|
||||
|
|
@ -20,5 +9,16 @@
|
|||
"from_pin": "CE_B",
|
||||
"to_pin": "OUT"
|
||||
}
|
||||
},
|
||||
"site_pins": {
|
||||
"I": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CE": {
|
||||
"direction": "IN"
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -1,18 +1,18 @@
|
|||
{
|
||||
"type": "BUFR",
|
||||
"site_pips": {},
|
||||
"site_pins": {
|
||||
"CLR": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CE": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"I": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CLR": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CE": {
|
||||
"direction": "IN"
|
||||
}
|
||||
},
|
||||
"site_pips": {}
|
||||
}
|
||||
}
|
||||
|
|
@ -1,5 +1,6 @@
|
|||
{
|
||||
"type": "CAPTURE",
|
||||
"site_pips": {},
|
||||
"site_pins": {
|
||||
"CLK": {
|
||||
"direction": "IN"
|
||||
|
|
@ -7,6 +8,5 @@
|
|||
"CAP": {
|
||||
"direction": "IN"
|
||||
}
|
||||
},
|
||||
"site_pips": {}
|
||||
}
|
||||
}
|
||||
|
|
@ -1,12 +1,12 @@
|
|||
{
|
||||
"type": "DCIRESET",
|
||||
"site_pips": {},
|
||||
"site_pins": {
|
||||
"LOCKED": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"RST": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"LOCKED": {
|
||||
"direction": "OUT"
|
||||
}
|
||||
},
|
||||
"site_pips": {}
|
||||
}
|
||||
}
|
||||
|
|
@ -1,21 +1,21 @@
|
|||
{
|
||||
"type": "DNA_PORT",
|
||||
"site_pips": {},
|
||||
"site_pins": {
|
||||
"READ": {
|
||||
"CLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DOUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SHIFT": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CLK": {
|
||||
"READ": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SHIFT": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DOUT": {
|
||||
"direction": "OUT"
|
||||
}
|
||||
},
|
||||
"site_pips": {}
|
||||
}
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,102 +1,102 @@
|
|||
{
|
||||
"type": "EFUSE_USR",
|
||||
"site_pips": {},
|
||||
"site_pins": {
|
||||
"EFUSEUSR13": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR17": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR31": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR29": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR30": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR26": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR22": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR11": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR8": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR27": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR15": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR25": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR7": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR24": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR18": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR5": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR16": {
|
||||
"EFUSEUSR19": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR12": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR11": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR15": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR5": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR21": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR10": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR14": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR28": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR18": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR22": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR28": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR27": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR20": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR24": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR30": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR7": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR16": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR8": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR31": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR25": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR6": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR13": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR14": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR26": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR23": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR19": {
|
||||
"EFUSEUSR10": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR9": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR6": {
|
||||
"EFUSEUSR29": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR17": {
|
||||
"direction": "OUT"
|
||||
}
|
||||
},
|
||||
"site_pips": {}
|
||||
}
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,171 +1,171 @@
|
|||
{
|
||||
"type": "FRAME_ECC",
|
||||
"site_pips": {},
|
||||
"site_pins": {
|
||||
"FAR10": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR12": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNWORD1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNWORD5": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR24": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR7": {
|
||||
"FAR20": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR22": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNDROME7": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR17": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR23": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNBIT4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNDROME5": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR8": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"ECCERRORSINGLE": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR21": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNDROME3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNDROME4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNDROME8": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNDROME2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNWORD2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNDROME1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNDROME9": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNBIT2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR15": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNWORD4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR13": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR14": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNDROME11": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNDROME0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNBIT0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNDROME6": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNWORD6": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNWORD3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"ECCERROR": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR11": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNWORD0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR5": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNBIT3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR9": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR19": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR16": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNDROMEVALID": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR20": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNDROME12": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CRCERROR": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNDROME10": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR18": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNBIT1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR25": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNDROME0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR24": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CRCERROR": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNBIT4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNDROME3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR8": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNBIT0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNBIT1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR17": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNDROME9": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"ECCERRORSINGLE": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR15": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR6": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNDROMEVALID": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR10": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR16": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNBIT2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNWORD0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNWORD6": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNWORD2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR12": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNDROME6": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNDROME10": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR23": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR19": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR11": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNBIT3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNDROME1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR9": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR7": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR18": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNDROME4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNDROME2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNDROME11": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNWORD1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNDROME12": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNDROME8": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNWORD3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR5": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNDROME7": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"ECCERROR": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNDROME5": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNWORD5": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR14": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR21": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNWORD4": {
|
||||
"direction": "OUT"
|
||||
}
|
||||
},
|
||||
"site_pips": {}
|
||||
}
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -1,25 +1,5 @@
|
|||
{
|
||||
"type": "IBUFDS_GTE2",
|
||||
"site_pins": {
|
||||
"IB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ODIV2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CEB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"I": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CLKTESTSIG": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O": {
|
||||
"direction": "OUT"
|
||||
}
|
||||
},
|
||||
"site_pips": {
|
||||
"CLKTESTSIGINV:CLKTESTSIG_B": {
|
||||
"from_pin": "CLKTESTSIG_B",
|
||||
|
|
@ -29,5 +9,25 @@
|
|||
"from_pin": "CLKTESTSIG",
|
||||
"to_pin": "OUT"
|
||||
}
|
||||
},
|
||||
"site_pins": {
|
||||
"I": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ODIV2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CLKTESTSIG": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CEB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"IB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O": {
|
||||
"direction": "OUT"
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -1,55 +1,59 @@
|
|||
{
|
||||
"type": "ICAP",
|
||||
"site_pips": {},
|
||||
"site_pins": {
|
||||
"O11": {
|
||||
"I4": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O16": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"I22": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O23": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"I24": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"I21": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"I20": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O28": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"O25": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"I17": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"I3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O12": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"I1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CSIB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"I12": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O8": {
|
||||
"O7": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"I19": {
|
||||
"I14": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O24": {
|
||||
"I13": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"I26": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O10": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"I30": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"I7": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O13": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"O27": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"I5": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"I22": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"I16": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O21": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"I31": {
|
||||
|
|
@ -58,150 +62,146 @@
|
|||
"I11": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O9": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"I28": {
|
||||
"I15": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O13": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O20": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"I4": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"O10": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"I10": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"I7": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"I16": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"I9": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O27": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"I13": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O17": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"I25": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"I29": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"I8": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O29": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"O26": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"I23": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O21": {
|
||||
"O24": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"RDWRB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"I18": {
|
||||
"I29": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O5": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"I5": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"I27": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O2": {
|
||||
"O28": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"I0": {
|
||||
"I12": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O7": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"O15": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"I30": {
|
||||
"I17": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"I15": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O14": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"O30": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"I6": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"I26": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O16": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"O22": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"I2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O31": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"O3": {
|
||||
"O23": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"O6": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"O29": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"I9": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"I24": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O19": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"I14": {
|
||||
"I27": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O31": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"I25": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"I21": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O17": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"I6": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"I3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"I23": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O20": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"I19": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O11": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"O18": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"O25": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"O14": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"I28": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"I8": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O15": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"I2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CSIB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O30": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"O9": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"O4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"I0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"I18": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"I10": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"I20": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"RDWRB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O22": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"O8": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"I1": {
|
||||
"direction": "IN"
|
||||
}
|
||||
},
|
||||
"site_pips": {}
|
||||
}
|
||||
}
|
||||
|
|
@ -1,27 +1,27 @@
|
|||
{
|
||||
"type": "IDELAYCTRL",
|
||||
"site_pips": {},
|
||||
"site_pins": {
|
||||
"OUTN1": {
|
||||
"direction": "OUT"
|
||||
"RST": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"OUTN65": {
|
||||
"OUTN1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"RDY": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"RST": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"REFCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"UPPULSEOUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DNPULSEOUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"OUTN65": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"REFCLK": {
|
||||
"direction": "IN"
|
||||
}
|
||||
},
|
||||
"site_pips": {}
|
||||
}
|
||||
}
|
||||
|
|
@ -1,10 +1,60 @@
|
|||
{
|
||||
"type": "IDELAYE2",
|
||||
"site_pips": {
|
||||
"DATAININV:DATAIN": {
|
||||
"from_pin": "DATAIN",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"CINV:C": {
|
||||
"from_pin": "C",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"IDATAININV:IDATAIN_B": {
|
||||
"from_pin": "IDATAIN_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"IDATAININV:IDATAIN": {
|
||||
"from_pin": "IDATAIN",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"DATAININV:DATAIN_B": {
|
||||
"from_pin": "DATAIN_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"CINV:C_B": {
|
||||
"from_pin": "C_B",
|
||||
"to_pin": "OUT"
|
||||
}
|
||||
},
|
||||
"site_pins": {
|
||||
"C": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"IFDLY0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DATAOUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"IFDLY0": {
|
||||
"CNTVALUEOUT4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"LDPIPEEN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CNTVALUEOUT1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CNTVALUEOUT0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CINVCTRL": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"REGRST": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CNTVALUEIN1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DATAIN": {
|
||||
|
|
@ -13,88 +63,38 @@
|
|||
"IDATAIN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"INC": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"LD": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CNTVALUEIN3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CNTVALUEIN0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"INC": {
|
||||
"CNTVALUEIN4": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CNTVALUEOUT4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CNTVALUEOUT2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"C": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CE": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CNTVALUEOUT0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CNTVALUEIN1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CNTVALUEIN4": {
|
||||
"CNTVALUEIN2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CNTVALUEOUT3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CINVCTRL": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"LDPIPEEN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CNTVALUEOUT1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"IFDLY2": {
|
||||
"CE": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"IFDLY1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"LD": {
|
||||
"IFDLY2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CNTVALUEIN2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"REGRST": {
|
||||
"direction": "IN"
|
||||
}
|
||||
},
|
||||
"site_pips": {
|
||||
"IDATAININV:IDATAIN_B": {
|
||||
"from_pin": "IDATAIN_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"DATAININV:DATAIN": {
|
||||
"from_pin": "DATAIN",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"CINV:C_B": {
|
||||
"from_pin": "C_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"IDATAININV:IDATAIN": {
|
||||
"from_pin": "IDATAIN",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"CINV:C": {
|
||||
"from_pin": "C",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"DATAININV:DATAIN_B": {
|
||||
"from_pin": "DATAIN_B",
|
||||
"to_pin": "OUT"
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -1,7 +1,123 @@
|
|||
{
|
||||
"type": "ILOGICE3",
|
||||
"site_pips": {
|
||||
"IDELMUXE3:1": {
|
||||
"from_pin": "1",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"D2OBYP_SEL:GND": {
|
||||
"from_pin": "GND",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"D2OBYP_SEL:T": {
|
||||
"from_pin": "T",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"ZHOLD_FABRIC_INV:D_B": {
|
||||
"from_pin": "D_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"ZHOLD_IFF_INV:D": {
|
||||
"from_pin": "D",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"CLKBINV:CLKB_B": {
|
||||
"from_pin": "CLKB_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"IMUX:1": {
|
||||
"from_pin": "1",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"D2OFFBYP_SEL:T": {
|
||||
"from_pin": "T",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"CLKINV:CLK_B": {
|
||||
"from_pin": "CLK_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"IDELMUXE3:2": {
|
||||
"from_pin": "2",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"REVUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"IFFMUX:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"IFFDELMUXE3:2": {
|
||||
"from_pin": "2",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"ZHOLD_IFF_INV:D_B": {
|
||||
"from_pin": "D_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"ZHOLD_FABRIC_INV:D": {
|
||||
"from_pin": "D",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"DINV:D": {
|
||||
"from_pin": "D",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"IFFDELMUXE3:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"IDELMUXE3:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"CE1USED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"DINV:D_B": {
|
||||
"from_pin": "D_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"CLKINV:CLK": {
|
||||
"from_pin": "CLK",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"SRUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"IFFMUX:1": {
|
||||
"from_pin": "1",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"CLKBINV:CLKB": {
|
||||
"from_pin": "CLKB",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"D2OFFBYP_SEL:GND": {
|
||||
"from_pin": "GND",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"IMUX:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"IFFDELMUXE3:1": {
|
||||
"from_pin": "1",
|
||||
"to_pin": "OUT"
|
||||
}
|
||||
},
|
||||
"site_pins": {
|
||||
"TFB": {
|
||||
"SR": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q8": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DYNCLKSEL": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DYNCLKDIVSEL": {
|
||||
|
|
@ -10,61 +126,25 @@
|
|||
"CE2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"OFB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"BITSLIP": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SHIFTIN1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CE1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q6": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DYNCLKSEL": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"OCLKB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CLKB": {
|
||||
"DYNCLKDIVPSEL": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CLK": {
|
||||
"SHIFTIN1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"OCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SR": {
|
||||
"TFB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SHIFTOUT1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q8": {
|
||||
"direction": "OUT"
|
||||
"OCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q5": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SHIFTOUT2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DDLY": {
|
||||
"CE1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q7": {
|
||||
|
|
@ -73,136 +153,56 @@
|
|||
"Q1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"OFB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CLKDIV": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DDLY": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SHIFTOUT2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CLKDIVP": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SHIFTIN2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q4": {
|
||||
"direction": "OUT"
|
||||
"CLKB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DYNCLKDIVPSEL": {
|
||||
"OCLKB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"REV": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CLKDIV": {
|
||||
"Q5": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"BITSLIP": {
|
||||
"direction": "IN"
|
||||
}
|
||||
},
|
||||
"site_pips": {
|
||||
"IDELMUXE3:2": {
|
||||
"from_pin": "2",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"SRUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
"Q6": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CE1USED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
"O": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"IDELMUXE3:1": {
|
||||
"from_pin": "1",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"ZHOLD_FABRIC_INV:D": {
|
||||
"from_pin": "D",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"D2OBYP_SEL:T": {
|
||||
"from_pin": "T",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"CLKBINV:CLKB": {
|
||||
"from_pin": "CLKB",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"D2OFFBYP_SEL:T": {
|
||||
"from_pin": "T",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"CLKBINV:CLKB_B": {
|
||||
"from_pin": "CLKB_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"CLKINV:CLK_B": {
|
||||
"from_pin": "CLK_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"ZHOLD_IFF_INV:D_B": {
|
||||
"from_pin": "D_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"DINV:D": {
|
||||
"from_pin": "D",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"DINV:D_B": {
|
||||
"from_pin": "D_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"D2OBYP_SEL:GND": {
|
||||
"from_pin": "GND",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"REVUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"IFFDELMUXE3:1": {
|
||||
"from_pin": "1",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"IMUX:1": {
|
||||
"from_pin": "1",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"D2OFFBYP_SEL:GND": {
|
||||
"from_pin": "GND",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"ZHOLD_FABRIC_INV:D_B": {
|
||||
"from_pin": "D_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"IFFDELMUXE3:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"IFFMUX:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"CLKINV:CLK": {
|
||||
"from_pin": "CLK",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"ZHOLD_IFF_INV:D": {
|
||||
"from_pin": "D",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"IFFMUX:1": {
|
||||
"from_pin": "1",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"IMUX:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"IFFDELMUXE3:2": {
|
||||
"from_pin": "2",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"IDELMUXE3:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
"D": {
|
||||
"direction": "IN"
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -1,151 +1,320 @@
|
|||
{
|
||||
"type": "IN_FIFO",
|
||||
"site_pips": {},
|
||||
"site_pins": {
|
||||
"D81": {
|
||||
"Q03": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q25": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D40": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTREADDISB": {
|
||||
"TESTWRITEDISB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q30": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D91": {
|
||||
"D83": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D51": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D03": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D72": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q43": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q04": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q36": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q71": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q53": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q75": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q47": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SCANOUT0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q42": {
|
||||
"Q20": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q02": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q17": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q84": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q97": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D53": {
|
||||
"WRCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D72": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q81": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FULL": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q83": {
|
||||
"Q15": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q26": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q94": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D63": {
|
||||
"D21": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D30": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q23": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q91": {
|
||||
"Q54": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q22": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q96": {
|
||||
"Q41": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q44": {
|
||||
"Q16": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"RDCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q76": {
|
||||
"Q40": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D32": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q14": {
|
||||
"Q97": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D67": {
|
||||
"direction": "IN"
|
||||
"Q77": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D82": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D31": {
|
||||
"RESET": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q56": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q62": {
|
||||
"Q83": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SCANIN1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SCANENB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q64": {
|
||||
"Q14": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTWRITEDISB": {
|
||||
"Q32": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D03": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q26": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q80": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D22": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q93": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q81": {
|
||||
"Q43": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q71": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q92": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"ALMOSTEMPTY": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D62": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D54": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q27": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D90": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q13": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D65": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q04": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SCANOUT1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q95": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q66": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D11": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q17": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D63": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D82": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D43": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D80": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q84": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q63": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D41": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D55": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q74": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q90": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D92": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D73": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q46": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D67": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q96": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D02": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q94": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q73": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q06": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q65": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q53": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q11": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q24": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D32": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D53": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SCANOUT2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D30": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D51": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q55": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"ALMOSTFULL": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q62": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q01": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q34": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SCANIN2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q57": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q75": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SCANOUT3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D64": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q67": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q21": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D60": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q23": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q85": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D33": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q91": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q47": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q86": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D66": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTMODEB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D71": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"RDEN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D93": {
|
||||
"Q44": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q51": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D61": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q12": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D91": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D20": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SCANENB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D81": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q33": {
|
||||
|
|
@ -154,300 +323,131 @@
|
|||
"Q60": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q45": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D62": {
|
||||
"D00": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q31": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q11": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D02": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D42": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q65": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D66": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D11": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ALMOSTFULL": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D73": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q73": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q12": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q13": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q41": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q35": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D01": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D22": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q32": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q16": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q85": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q03": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q63": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTMODEB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q10": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D70": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q57": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q77": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q74": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q25": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D43": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"RESET": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SCANOUT1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SCANOUT3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q66": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D61": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"WRCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D71": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q07": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q86": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EMPTY": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q55": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D52": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q20": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D92": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q80": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q54": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q27": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q61": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q34": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q72": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q70": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"WREN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D54": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q15": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SCANIN2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D80": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ALMOSTEMPTY": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q00": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D13": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q90": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q67": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SCANIN3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D12": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D56": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q24": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D65": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q21": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D10": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SCANOUT2": {
|
||||
"Q36": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q06": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q51": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q40": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D83": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q87": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D00": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D33": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q52": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D57": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D23": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D21": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q82": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D90": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D20": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D64": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q50": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D50": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D40": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q05": {
|
||||
"Q64": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q37": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q52": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D70": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q72": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EMPTY": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D23": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q00": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D12": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q30": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D50": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SCANOUT0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D42": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q70": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q10": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q76": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"RDCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D52": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q82": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q50": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q05": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q42": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D13": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q31": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D31": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D57": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SCANIN0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D41": {
|
||||
"SCANIN1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D60": {
|
||||
"SCANIN3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q01": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D55": {
|
||||
"TESTREADDISB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q46": {
|
||||
"Q45": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q95": {
|
||||
"D01": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q07": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q92": {
|
||||
"Q35": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D93": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"WREN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q61": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D56": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q87": {
|
||||
"direction": "OUT"
|
||||
}
|
||||
},
|
||||
"site_pips": {}
|
||||
}
|
||||
}
|
||||
|
|
@ -1,87 +1,6 @@
|
|||
{
|
||||
"type": "IOB33",
|
||||
"site_pins": {
|
||||
"PADOUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"O": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O_IN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"T_OUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"O_OUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"I": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DIFFI_IN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PU_INT_EN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"T_IN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIFFO_IN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PD_INT_EN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"IBUFDISABLE": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"T": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"INTERMDISABLE": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIFF_TERM_INT_EN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIFFO_OUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"KEEPER_INT_EN": {
|
||||
"direction": "IN"
|
||||
}
|
||||
},
|
||||
"site_pips": {
|
||||
"IUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"DIFFI_INUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"IBUFDISABLE_SEL:I": {
|
||||
"from_pin": "I",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"TUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"INTERMDISABLE_SEL:I": {
|
||||
"from_pin": "I",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"IBUFDISABLE_SEL:GND": {
|
||||
"from_pin": "GND",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"INTERMDISABLE_SEL:GND": {
|
||||
"from_pin": "GND",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"PADOUTUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
|
|
@ -89,6 +8,87 @@
|
|||
"OUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"IBUFDISABLE_SEL:I": {
|
||||
"from_pin": "I",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"DIFFI_INUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"IBUFDISABLE_SEL:GND": {
|
||||
"from_pin": "GND",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"INTERMDISABLE_SEL:I": {
|
||||
"from_pin": "I",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"INTERMDISABLE_SEL:GND": {
|
||||
"from_pin": "GND",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"TUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"IUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
}
|
||||
},
|
||||
"site_pins": {
|
||||
"O_IN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"I": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DIFFO_OUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PD_INT_EN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PADOUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DIFFO_IN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PU_INT_EN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"T": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O_OUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DIFF_TERM_INT_EN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"INTERMDISABLE": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"T_OUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"IBUFDISABLE": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"T_IN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"KEEPER_INT_EN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIFFI_IN": {
|
||||
"direction": "IN"
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -1,106 +1,106 @@
|
|||
{
|
||||
"type": "IOB33M",
|
||||
"site_pins": {
|
||||
"PADOUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"O_IN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"T_OUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"I": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"O_OUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DIFFI_IN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIFFO_OUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"T_IN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIFFO_IN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PD_INT_EN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"IBUFDISABLE": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"T": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"INTERMDISABLE": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"KEEPER_INT_EN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIFF_TERM_INT_EN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PU_INT_EN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O": {
|
||||
"direction": "IN"
|
||||
}
|
||||
},
|
||||
"site_pips": {
|
||||
"IUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"DIFFI_INUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"IBUFDISABLE_SEL:I": {
|
||||
"from_pin": "I",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"PADOUTUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"O_OUTUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"TUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"OUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"IBUFDISABLE_SEL:I": {
|
||||
"from_pin": "I",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"T_OUTUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"TUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"DIFFI_INUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"O_OUTUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"DIFFO_OUTUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"INTERMDISABLE_SEL:GND": {
|
||||
"from_pin": "GND",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"IUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"IBUFDISABLE_SEL:GND": {
|
||||
"from_pin": "GND",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"INTERMDISABLE_SEL:GND": {
|
||||
"from_pin": "GND",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"DIFFO_OUTUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"INTERMDISABLE_SEL:I": {
|
||||
"from_pin": "I",
|
||||
"to_pin": "OUT"
|
||||
}
|
||||
},
|
||||
"site_pins": {
|
||||
"O_IN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PD_INT_EN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIFFO_OUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"I": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PADOUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DIFFO_IN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PU_INT_EN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"T": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O_OUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DIFF_TERM_INT_EN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"INTERMDISABLE": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"T_OUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"IBUFDISABLE": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"T_IN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"KEEPER_INT_EN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIFFI_IN": {
|
||||
"direction": "IN"
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -1,88 +1,43 @@
|
|||
{
|
||||
"type": "IOB33S",
|
||||
"site_pins": {
|
||||
"PADOUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"O_IN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"T_OUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"I": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"O_OUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DIFFI_IN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIFFO_OUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"T_IN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIFFO_IN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PD_INT_EN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"IBUFDISABLE": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"T": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"INTERMDISABLE": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"KEEPER_INT_EN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIFF_TERM_INT_EN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PU_INT_EN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O": {
|
||||
"direction": "IN"
|
||||
}
|
||||
},
|
||||
"site_pips": {
|
||||
"IUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"DIFFI_INUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"IBUFDISABLE_SEL:I": {
|
||||
"from_pin": "I",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"TINMUX:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"PADOUTUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"OUTMUX:1": {
|
||||
"from_pin": "1",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"TINMUX:1": {
|
||||
"from_pin": "1",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"INTERMDISABLE_SEL:GND": {
|
||||
"from_pin": "GND",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"OINMUX:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"DIFFO_INUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"TINMUX:1": {
|
||||
"from_pin": "1",
|
||||
"OUTMUX:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"OUTMUX:1": {
|
||||
"from_pin": "1",
|
||||
"IBUFDISABLE_SEL:I": {
|
||||
"from_pin": "I",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"OINMUX:0": {
|
||||
"DIFFI_INUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
|
|
@ -90,25 +45,70 @@
|
|||
"from_pin": "1",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"IBUFDISABLE_SEL:GND": {
|
||||
"from_pin": "GND",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"INTERMDISABLE_SEL:GND": {
|
||||
"from_pin": "GND",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"PADOUTUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"INTERMDISABLE_SEL:I": {
|
||||
"from_pin": "I",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"OUTMUX:0": {
|
||||
"IBUFDISABLE_SEL:GND": {
|
||||
"from_pin": "GND",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"IUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
}
|
||||
},
|
||||
"site_pins": {
|
||||
"O_IN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PD_INT_EN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIFFO_OUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"I": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PADOUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DIFFO_IN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PU_INT_EN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"T": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O_OUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DIFF_TERM_INT_EN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"INTERMDISABLE": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"T_OUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"IBUFDISABLE": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"T_IN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"KEEPER_INT_EN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIFFI_IN": {
|
||||
"direction": "IN"
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -1,9 +1,9 @@
|
|||
{
|
||||
"type": "IPAD",
|
||||
"site_pips": {},
|
||||
"site_pins": {
|
||||
"O": {
|
||||
"direction": "OUT"
|
||||
}
|
||||
},
|
||||
"site_pips": {}
|
||||
}
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,121 +1,60 @@
|
|||
{
|
||||
"type": "OLOGICE3",
|
||||
"site_pins": {
|
||||
"TFB": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"T1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D7": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"OFB": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CLKDIVB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SHIFTIN1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D6": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"T3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CLKDIVFB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"T2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TBYTEOUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TQ": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SR": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SHIFTOUT1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"OQ": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D5": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SHIFTOUT2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D8": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D4": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CLKB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"IOCLKGLITCH": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"REV": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TBYTEIN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SHIFTIN2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"OCE": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CLKDIVF": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TCE": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"T4": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CLKDIV": {
|
||||
"direction": "IN"
|
||||
}
|
||||
},
|
||||
"site_pips": {
|
||||
"O1USED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"T1INV:T1_B": {
|
||||
"from_pin": "T1_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"OFBUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"OQUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"TREVUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"OMUX:OUTFF": {
|
||||
"from_pin": "OUTFF",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"TMUX:T1": {
|
||||
"from_pin": "T1",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"T1USED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"TQUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"OSRUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"T1INV:T1": {
|
||||
"from_pin": "T1",
|
||||
"CLKINV:CLK_B": {
|
||||
"from_pin": "CLK_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"TMUX:TFF": {
|
||||
"from_pin": "TFF",
|
||||
"D1INV:D1_B": {
|
||||
"from_pin": "D1_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"D1INV:D1": {
|
||||
"from_pin": "D1",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"TSRUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"T2INV:T2_B": {
|
||||
|
|
@ -126,46 +65,10 @@
|
|||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"D1INV:D1": {
|
||||
"from_pin": "D1",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"CLKINV:CLK_B": {
|
||||
"from_pin": "CLK_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"T1INV:T1_B": {
|
||||
"from_pin": "T1_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"T2INV:T2": {
|
||||
"from_pin": "T2",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"OFBUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"O1USED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"TFBUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"OREVUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"D2INV:D2_B": {
|
||||
"from_pin": "D2_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"TCEUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"OMUX:D1": {
|
||||
"from_pin": "D1",
|
||||
"to_pin": "OUT"
|
||||
|
|
@ -174,37 +77,134 @@
|
|||
"from_pin": "D2",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"T1USED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"D1INV:D1_B": {
|
||||
"from_pin": "D1_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"TREVUSED:0": {
|
||||
"from_pin": "0",
|
||||
"T2INV:T2": {
|
||||
"from_pin": "T2",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"CLKINV:CLK": {
|
||||
"from_pin": "CLK",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"TQUSED:0": {
|
||||
"T1INV:T1": {
|
||||
"from_pin": "T1",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"TMUX:TFF": {
|
||||
"from_pin": "TFF",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"D2INV:D2_B": {
|
||||
"from_pin": "D2_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"TCEUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"TSRUSED:0": {
|
||||
"OREVUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
}
|
||||
},
|
||||
"site_pins": {
|
||||
"SR": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"OQUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
"CLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"OMUX:OUTFF": {
|
||||
"from_pin": "OUTFF",
|
||||
"to_pin": "OUT"
|
||||
"D8": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"T4": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D5": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"IOCLKGLITCH": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TFB": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SHIFTOUT1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SHIFTIN1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SHIFTOUT2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CLKDIVB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"OFB": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"OCE": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CLKDIV": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TQ": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D4": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"T2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TBYTEIN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TCE": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SHIFTIN2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CLKB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"REV": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CLKDIVFB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TBYTEOUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"T1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"OQ": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D6": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D7": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CLKDIVF": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"T3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D1": {
|
||||
"direction": "IN"
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -1,9 +1,9 @@
|
|||
{
|
||||
"type": "OPAD",
|
||||
"site_pips": {},
|
||||
"site_pins": {
|
||||
"I": {
|
||||
"direction": "IN"
|
||||
}
|
||||
},
|
||||
"site_pips": {}
|
||||
}
|
||||
}
|
||||
|
|
@ -1,37 +1,209 @@
|
|||
{
|
||||
"type": "OUT_FIFO",
|
||||
"site_pips": {},
|
||||
"site_pins": {
|
||||
"D81": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTREADDISB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q30": {
|
||||
"Q03": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D91": {
|
||||
"D40": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D51": {
|
||||
"TESTWRITEDISB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q63": {
|
||||
"D16": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D84": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D96": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q20": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q02": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D72": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D54": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q81": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FULL": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D45": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D21": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q54": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q22": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q41": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D66": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D77": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D74": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D37": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SCANOUT0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"ALMOSTFULL": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D43": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"RESET": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q56": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q83": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D86": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q32": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D03": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D72": {
|
||||
"Q80": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D22": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q93": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q13": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D35": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q71": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q92": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"ALMOSTEMPTY": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D27": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D15": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D62": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D81": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q51": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D90": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"EMPTY": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D94": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D65": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SCANOUT1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D83": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D44": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D11": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D63": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D82": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q40": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D80": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q43": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D87": {
|
||||
"D41": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q71": {
|
||||
"D55": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q90": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D13": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D14": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D73": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D67": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D36": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D02": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D20": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"WRCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q65": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q53": {
|
||||
|
|
@ -40,268 +212,34 @@
|
|||
"D97": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SCANOUT0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q42": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q02": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D16": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D26": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D74": {
|
||||
"D32": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D53": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D46": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q03": {
|
||||
"SCANOUT2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q83": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D96": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D63": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D30": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q23": {
|
||||
"Q11": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q91": {
|
||||
"Q55": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q22": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D47": {
|
||||
"D17": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D45": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D32": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D36": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D67": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D82": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D31": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q56": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q62": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SCANIN1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SCANENB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D83": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D37": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTWRITEDISB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q40": {
|
||||
"Q01": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D35": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q81": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q57": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D93": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q33": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q60": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D62": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q31": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q11": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D42": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q65": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D04": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D76": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D11": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D27": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ALMOSTFULL": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D73": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q73": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D66": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q13": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q41": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D75": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D01": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D22": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"RDCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q64": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D34": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTMODEB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q10": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D70": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"RDEN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D24": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D43": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"RESET": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SCANOUT1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SCANOUT3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q66": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SCANIN3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D61": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SCANIN0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D71": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"FULL": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q12": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EMPTY": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D05": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D52": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q20": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D15": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D92": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q80": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q61": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D95": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D25": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q72": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q70": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"WREN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D54": {
|
||||
"D06": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D07": {
|
||||
|
|
@ -310,144 +248,206 @@
|
|||
"SCANIN2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D94": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D80": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ALMOSTEMPTY": {
|
||||
"Q57": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q00": {
|
||||
"SCANOUT3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D13": {
|
||||
"D25": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q90": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q67": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D84": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D12": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D56": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q54": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q21": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D65": {
|
||||
"D60": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D44": {
|
||||
"D51": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q91": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D76": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTMODEB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SCANIN0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"RDEN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D61": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q12": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D85": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D05": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q63": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q73": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SCANENB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D47": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q33": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q60": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D57": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D10": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D06": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q32": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q51": {
|
||||
"Q64": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q52": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D02": {
|
||||
"D70": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D00": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D33": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D57": {
|
||||
"direction": "IN"
|
||||
"Q72": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D23": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D21": {
|
||||
"Q00": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D12": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D85": {
|
||||
"D26": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D75": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q30": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D50": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D42": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D46": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q70": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q10": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D71": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D04": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"RDCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D52": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q82": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D77": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SCANOUT2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D20": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D64": {
|
||||
"D87": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q50": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D86": {
|
||||
"D92": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D50": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D90": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D14": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D40": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D17": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q93": {
|
||||
"Q42": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"WRCLK": {
|
||||
"SCANIN1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D41": {
|
||||
"D33": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D60": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q01": {
|
||||
"Q31": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D55": {
|
||||
"D31": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q55": {
|
||||
"D34": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D64": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D56": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SCANIN3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q23": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q92": {
|
||||
"D24": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D01": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q66": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D00": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D95": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D93": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"WREN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q61": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTREADDISB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D91": {
|
||||
"direction": "IN"
|
||||
}
|
||||
},
|
||||
"site_pips": {}
|
||||
}
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,291 +1,291 @@
|
|||
{
|
||||
"type": "PHASER_IN_PHY",
|
||||
"site_pips": {
|
||||
"RSTINV:RST_B": {
|
||||
"from_pin": "RST_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"RSTINV:RST": {
|
||||
"from_pin": "RST",
|
||||
"to_pin": "OUT"
|
||||
}
|
||||
},
|
||||
"site_pins": {
|
||||
"COUNTERLOADEN": {
|
||||
"TESTIN6": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DQSFOUND": {
|
||||
"direction": "OUT"
|
||||
"COUNTERLOADVAL3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SCANMODEB": {
|
||||
"COUNTERLOADEN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"RANKSELPHY0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ENCALIBPHY1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN9": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SCANCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"STG1REGL0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"STG1REGL1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN5": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COUNTERLOADVAL1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COUNTERLOADVAL0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COUNTERREADVAL1": {
|
||||
"RCLK": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"COUNTERLOADVAL3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"STG1REGR4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"COUNTERREADVAL2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN6": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ENSTG1ADJUSTB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"STG1LOAD": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"FREQREFCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHASELOCKED": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FINEINC": {
|
||||
"SELCALORSTG1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COUNTERLOADVAL4": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"STG1REGR6": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SCANENB": {
|
||||
"ENCALIB1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ICLK": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"STG1READ": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"STG1REGL6": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"STG1REGR1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"COUNTERREADEN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIVIDERST": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"COUNTERREADVAL3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN12": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"EDGEADV": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"STG1REGL8": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN8": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"STG1REGR7": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"ISERDESRST": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"COUNTERREADVAL4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"STG1OVERFLOW": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"RSTDQSFIND": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"RANKSEL1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"MEMREFCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COUNTERREADVAL0": {
|
||||
"COUNTERREADVAL2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"STG1REGL4": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"STG1REGR2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PHASEREFCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SYNCIN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DQSOUTOFRANGE": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FINEOVERFLOW": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN7": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"RCLK": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"STG1REGR5": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FINEENABLE": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"STG1REGL5": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SCANOUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"ENSTG1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SELCALORSTG1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"WRENABLE": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYSCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ENCALIB1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SCANIN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"BURSTPENDINGPHY": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"RST": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"STG1REGL7": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"RANKSEL0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COUNTERLOADVAL2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"STG1REGL3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"RANKSELPHY1": {
|
||||
"DIVIDERST": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ENCALIBPHY0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN0": {
|
||||
"STG1REGL5": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COUNTERLOADVAL5": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SCANCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"STG1REGL6": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SCANENB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ISERDESRST": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FREQREFCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"BURSTPENDING": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN11": {
|
||||
"TESTOUT2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"ENSTG1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COUNTERREADVAL5": {
|
||||
"STG1REGL8": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"STG1REGR2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"STG1REGR0": {
|
||||
"direction": "OUT"
|
||||
"COUNTERLOADVAL1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN13": {
|
||||
"SCANIN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ENCALIB0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"STG1INCDEC": {
|
||||
"WRENABLE": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"STG1REGR7": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"STG1REGL0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN10": {
|
||||
"TESTIN9": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"STG1REGR8": {
|
||||
"TESTIN2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SCANOUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"STG1REGL3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"BURSTPENDINGPHY": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN11": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"STG1REGL4": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"STG1REGR4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"STG1REGL2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ICLKDIV": {
|
||||
"direction": "OUT"
|
||||
"PHASEREFCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"STG1REGR3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"COUNTERLOADVAL5": {
|
||||
"MEMREFCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN4": {
|
||||
"direction": "IN"
|
||||
}
|
||||
},
|
||||
"site_pips": {
|
||||
"RSTINV:RST": {
|
||||
"from_pin": "RST",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"RSTINV:RST_B": {
|
||||
"from_pin": "RST_B",
|
||||
"to_pin": "OUT"
|
||||
"TESTIN13": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"STG1REGL7": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN8": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COUNTERREADVAL5": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"COUNTERREADVAL4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN7": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"STG1REGR1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN5": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DQSFOUND": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FINEINC": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN12": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ENSTG1ADJUSTB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DQSOUTOFRANGE": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FINEENABLE": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SYSCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COUNTERREADEN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COUNTERREADVAL3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SCANMODEB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"EDGEADV": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"FINEOVERFLOW": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"STG1REGR0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PHASELOCKED": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNCIN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"STG1LOAD": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"RSTDQSFIND": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COUNTERREADVAL0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"ICLK": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"STG1INCDEC": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"STG1REGR6": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"RANKSEL0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"STG1REGL1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COUNTERREADVAL1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"RST": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"STG1REGR8": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN10": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COUNTERLOADVAL2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"STG1REGR3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"STG1REGR5": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"RANKSELPHY1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"RANKSEL1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ICLKDIV": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"ENCALIBPHY1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COUNTERLOADVAL0": {
|
||||
"direction": "IN"
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -1,28 +1,101 @@
|
|||
{
|
||||
"type": "PHASER_OUT_PHY",
|
||||
"site_pips": {
|
||||
"RSTINV:RST_B": {
|
||||
"from_pin": "RST_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"RSTINV:RST": {
|
||||
"from_pin": "RST",
|
||||
"to_pin": "OUT"
|
||||
}
|
||||
},
|
||||
"site_pins": {
|
||||
"COUNTERREADVAL5": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"COUNTERREADVAL4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN7": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIVIDERST": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN5": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN6": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COUNTERLOADVAL3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COUNTERLOADEN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"FINEINC": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN12": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"EDGEADV": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"RDENABLE": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"COUNTERREADVAL1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"COUNTERREADVAL8": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FINEENABLE": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SELFINEOCLKDELAY": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COUNTERREADEN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COUNTERLOADVAL4": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHASEREFCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ENCALIB1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COUNTERREADVAL3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DQSBUS1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DTSBUS1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN2": {
|
||||
"SCANMODEB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ENCALIBPHY1": {
|
||||
"COUNTERREADVAL2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"COARSEENABLE": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT1": {
|
||||
"direction": "OUT"
|
||||
"ENCALIBPHY0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"FINEOVERFLOW": {
|
||||
"direction": "OUT"
|
||||
"COUNTERLOADVAL5": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN7": {
|
||||
"SCANENB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SCANCLK": {
|
||||
|
|
@ -31,216 +104,143 @@
|
|||
"TESTIN15": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SCANMODEB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COARSEOVERFLOW": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"COUNTERREADVAL6": {
|
||||
"FINEOVERFLOW": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN5": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SYNCIN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"BURSTPENDINGPHY": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN6": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"FINEENABLE": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COUNTERLOADVAL1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SELFINEOCLKDELAY": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SCANOUT": {
|
||||
"TESTOUT3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"COUNTERLOADVAL0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COUNTERREADVAL1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CTSBUS1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"COUNTERLOADVAL3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DTSBUS0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYSCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"OCLK": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"OCLKDIV": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"ENCALIB1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COUNTERLOADVAL8": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SCANIN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"FREQREFCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COUNTERREADVAL8": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"RST": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"FINEINC": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COUNTERLOADVAL5": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DQSBUS0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"OSERDESRST": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"COUNTERLOADVAL2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COUNTERREADVAL7": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DQSBUS1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN14": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SCANENB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN1": {
|
||||
"FREQREFCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"BURSTPENDING": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COARSEINC": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COARSEENABLE": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COUNTERLOADVAL6": {
|
||||
"direction": "IN"
|
||||
"TESTOUT2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CTSBUS0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN11": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COUNTERREADEN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COUNTERREADVAL5": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DIVIDERST": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COUNTERREADVAL2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"COUNTERREADVAL3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"OCLKDELAYED": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"ENCALIBPHY0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN13": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ENCALIB0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN10": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"EDGEADV": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN9": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN8": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"RDENABLE": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"COUNTERREADVAL4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"COUNTERLOADVAL7": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"COUNTERLOADVAL4": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"MEMREFCLK": {
|
||||
"SYNCIN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COUNTERREADVAL0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN10": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COUNTERLOADVAL1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SCANIN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"OCLK": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"OSERDESRST": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"COUNTERLOADVAL8": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN9": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"OCLKDIV": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SCANOUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN13": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DQSBUS0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN11": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"BURSTPENDINGPHY": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COUNTERLOADVAL6": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"RST": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN14": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COUNTERLOADVAL0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CTSBUS1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"OCLKDELAYED": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYSCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COUNTERLOADVAL2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COUNTERLOADVAL7": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"MEMREFCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ENCALIB0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN4": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHASEREFCLK": {
|
||||
"COARSEINC": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT3": {
|
||||
"direction": "OUT"
|
||||
}
|
||||
},
|
||||
"site_pips": {
|
||||
"RSTINV:RST": {
|
||||
"from_pin": "RST",
|
||||
"to_pin": "OUT"
|
||||
"ENCALIBPHY1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"RSTINV:RST_B": {
|
||||
"from_pin": "RST_B",
|
||||
"to_pin": "OUT"
|
||||
"DTSBUS0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN8": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COUNTERREADVAL6": {
|
||||
"direction": "OUT"
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -1,89 +1,89 @@
|
|||
{
|
||||
"type": "PHASER_REF",
|
||||
"site_pins": {
|
||||
"CLKIN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN7": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"LOCKED": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT5": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PWRDWN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN6": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT7": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CLKOUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TMUXOUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT6": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN5": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"RST": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN4": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT3": {
|
||||
"direction": "OUT"
|
||||
}
|
||||
},
|
||||
"site_pips": {
|
||||
"PWRDWNINV:PWRDWN_B": {
|
||||
"from_pin": "PWRDWN_B",
|
||||
"RSTINV:RST_B": {
|
||||
"from_pin": "RST_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"RSTINV:RST": {
|
||||
"from_pin": "RST",
|
||||
"PWRDWNINV:PWRDWN_B": {
|
||||
"from_pin": "PWRDWN_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"PWRDWNINV:PWRDWN": {
|
||||
"from_pin": "PWRDWN",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"RSTINV:RST_B": {
|
||||
"from_pin": "RST_B",
|
||||
"RSTINV:RST": {
|
||||
"from_pin": "RST",
|
||||
"to_pin": "OUT"
|
||||
}
|
||||
},
|
||||
"site_pins": {
|
||||
"TESTOUT2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN5": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN6": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"LOCKED": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TMUXOUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"RST": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN7": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT6": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PWRDWN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT7": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN4": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CLKOUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CLKIN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT5": {
|
||||
"direction": "OUT"
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -1,172 +1,53 @@
|
|||
{
|
||||
"type": "PHY_CONTROL",
|
||||
"site_pips": {},
|
||||
"site_pins": {
|
||||
"PHYCTLWD4": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD8": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUTPUT8": {
|
||||
"INBURSTPENDING2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PHYCTLWD6": {
|
||||
"TESTINPUT9": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD24": {
|
||||
"PHYCTLWD9": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"OUTBURSTPENDING1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUTPUT3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PHYCTLEMPTY": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PHYCTLWD13": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLMSTREMPTY": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD30": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWRENABLE": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTINPUT4": {
|
||||
"REFDLLLOCK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD20": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SCANENABLEN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTINPUT13": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUTPUT2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"INRANKC0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"READCALIBENABLE": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD10": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD31": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUTPUT5": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PHYCTLWD3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLFULL": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"AUXOUTPUT2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTINPUT6": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUTPUT14": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PCENABLECALIB0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUTPUT0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUTPUT13": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PHYCTLWD7": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"INRANKB1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PHYCTLWD9": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUTPUT15": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PHYCTLWD15": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD18": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"INRANKC1": {
|
||||
"TESTOUTPUT4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTINPUT10": {
|
||||
"INRANKD1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTINPUT0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"INRANKA1": {
|
||||
"TESTINPUT12": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"AUXOUTPUT3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTINPUT8": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTINPUT11": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTINPUT5": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD29": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"MEMREFCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD23": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTINPUT0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTINPUT15": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SYNCIN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTINPUT1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUTPUT10": {
|
||||
"PCENABLECALIB0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"INRANKA0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PHYCTLWD21": {
|
||||
"TESTSELECT1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD14": {
|
||||
"TESTOUTPUT1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"RESET": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD11": {
|
||||
|
|
@ -175,144 +56,263 @@
|
|||
"PHYCTLREADY": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"RESET": {
|
||||
"INRANKB0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTINPUT5": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTINPUT14": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"INBURSTPENDING0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PHYCTLALMOSTFULL": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PHYCTLWD2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD25": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD22": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"INBURSTPENDING1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PCENABLECALIB1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"INRANKD0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTSELECT0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD26": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"AUXOUTPUT3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"INBURSTPENDING2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PHYCTLWD12": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"INBURSTPENDING3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUTPUT9": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"AUXOUTPUT1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUTPUT12": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUTPUT11": {
|
||||
"INRANKB1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTSELECT2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUTPUT6": {
|
||||
"SCANENABLEN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTINPUT11": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLMSTREMPTY": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"INRANKD0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"OUTBURSTPENDING0": {
|
||||
"PHYCTLWD16": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTINPUT13": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD4": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD8": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD26": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLFULL": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUTPUT5": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"AUXOUTPUT0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PHYCTLWD27": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"WRITECALIBENABLE": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD16": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTINPUT12": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUTPUT1": {
|
||||
"TESTOUTPUT0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PHYCTLWD19": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTINPUT7": {
|
||||
"PHYCTLWD23": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"REFDLLLOCK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"OUTBURSTPENDING2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"OUTBURSTPENDING3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"INRANKB0": {
|
||||
"OUTBURSTPENDING0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PHYCTLALMOSTFULL": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PHYCTLEMPTY": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PHYCTLWD30": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD12": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUTPUT3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"MEMREFCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD17": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"AUXOUTPUT2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PHYCTLWD29": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PCENABLECALIB1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUTPUT6": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTINPUT2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"INBURSTPENDING1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTINPUT1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUTPUT11": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"INBURSTPENDING3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUTPUT8": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTINPUT6": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTINPUT7": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"INBURSTPENDING0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTINPUT14": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD21": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD25": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUTPUT2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PHYCTLWD6": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"INRANKA1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTINPUT4": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD14": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUTPUT15": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTINPUT3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTSELECT1": {
|
||||
"PHYCTLWD31": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTINPUT9": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTINPUT2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD28": {
|
||||
"TESTINPUT10": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUTPUT7": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"INRANKD1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUTPUT4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PHYCTLWD17": {
|
||||
"PHYCTLWD22": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD28": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUTPUT12": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUTPUT14": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"WRITECALIBENABLE": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD10": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"OUTBURSTPENDING2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUTPUT10": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"AUXOUTPUT1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"INRANKA0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTSELECT0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"READCALIBENABLE": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"INRANKC1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTINPUT15": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD15": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SYNCIN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUTPUT13": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PHYCTLWRENABLE": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PLLLOCK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD7": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"INRANKC0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PHYCTLWD5": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"AUXOUTPUT0": {
|
||||
"PHYCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD13": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUTPUT9": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PLLLOCK": {
|
||||
"PHYCTLWD24": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"OUTBURSTPENDING1": {
|
||||
"direction": "OUT"
|
||||
}
|
||||
},
|
||||
"site_pips": {}
|
||||
}
|
||||
}
|
||||
|
|
@ -1,493 +1,493 @@
|
|||
{
|
||||
"type": "PLLE2_ADV",
|
||||
"site_pins": {
|
||||
"TESTOUT5": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO12": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DADDR0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT15": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT13": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT49": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CLKIN2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CLKOUT1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT10": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TMUXOUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT14": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT27": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT62": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DI6": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN5": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN31": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN18": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT52": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT17": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT37": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT38": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN6": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DO7": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN22": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DI13": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DADDR6": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DWE": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CLKOUT4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT40": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DI5": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN29": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DI4": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT55": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DI10": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT48": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DO14": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CLKOUT5": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CLKOUT3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CLKIN1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN13": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT41": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO13": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DI9": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"LOCKED": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DADDR2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN12": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN17": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DI14": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT50": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT35": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN8": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DO9": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT57": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CLKOUT2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT16": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT7": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DI12": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN9": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DI15": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT43": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT56": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CLKOUT0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT23": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DI2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DO2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN23": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT22": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CLKFBIN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN7": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT19": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN15": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT46": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO11": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DADDR4": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DO10": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT28": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT20": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT45": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CLKINSEL": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DADDR1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT34": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT47": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DI11": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT42": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN28": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DO5": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN25": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PWRDWN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT58": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN14": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT39": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DI1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT21": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT30": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN26": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DI7": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DO6": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO15": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"RST": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN24": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN16": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DI0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT33": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO8": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DEN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT9": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT31": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN27": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT18": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DI8": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT11": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DADDR3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT29": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT6": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT63": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN11": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT12": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT54": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN30": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN21": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT32": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT36": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT8": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT24": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT51": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN10": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DADDR5": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN19": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT59": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN20": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT53": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CLKFBOUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT60": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DI3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT25": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DRDY": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT44": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT61": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN4": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT26": {
|
||||
"direction": "OUT"
|
||||
}
|
||||
},
|
||||
"site_pips": {
|
||||
"PWRDWNINV:PWRDWN_B": {
|
||||
"from_pin": "PWRDWN_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"CLKINSELINV:CLKINSEL_B": {
|
||||
"from_pin": "CLKINSEL_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"CLKINSELINV:CLKINSEL": {
|
||||
"from_pin": "CLKINSEL",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"RSTINV:RST": {
|
||||
"from_pin": "RST",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"PWRDWNINV:PWRDWN": {
|
||||
"from_pin": "PWRDWN",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"RSTINV:RST_B": {
|
||||
"from_pin": "RST_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"CLKINSELINV:CLKINSEL": {
|
||||
"from_pin": "CLKINSEL",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"CLKINSELINV:CLKINSEL_B": {
|
||||
"from_pin": "CLKINSEL_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"PWRDWNINV:PWRDWN": {
|
||||
"from_pin": "PWRDWN",
|
||||
"to_pin": "OUT"
|
||||
}
|
||||
},
|
||||
"site_pins": {
|
||||
"DO14": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CLKOUT4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT37": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT35": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO12": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DI12": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN6": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DO9": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DADDR3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CLKOUT5": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT28": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN27": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DI6": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT14": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN22": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT63": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN7": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DRDY": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT23": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CLKFBIN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT38": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN30": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN20": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN15": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN17": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT49": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO8": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT51": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO11": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DI0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT13": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT7": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT11": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT27": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT43": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT42": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DI1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DI8": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT17": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN9": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT55": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN11": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DO7": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO6": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT56": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN14": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DO4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT50": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT18": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT8": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DADDR2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT45": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN4": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT15": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT30": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN13": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DI4": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT5": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT25": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DI14": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CLKOUT1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN29": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DEN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DI10": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DI13": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DADDR4": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN5": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT9": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN25": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT62": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT22": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN12": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DADDR0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DO2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT24": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT34": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PWRDWN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DWE": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DADDR5": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT40": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DI11": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN18": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT47": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CLKIN2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT36": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN24": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT60": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT10": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT31": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT39": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT59": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT32": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT33": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT44": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO13": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT21": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT57": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DADDR1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN21": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DI9": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DO5": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT61": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT16": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT46": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT54": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT26": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO10": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DI5": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DI15": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT48": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CLKIN1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN31": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT29": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CLKFBOUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CLKOUT2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN26": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DADDR6": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN19": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"LOCKED": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT41": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TMUXOUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT58": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"RST": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DO15": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN23": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN16": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT6": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CLKOUT3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CLKINSEL": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN8": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DI3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT12": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CLKOUT0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT20": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT19": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DI7": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT52": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT53": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN10": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DI2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN28": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DO3": {
|
||||
"direction": "OUT"
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -1,27 +1,27 @@
|
|||
{
|
||||
"type": "PMV2",
|
||||
"site_pips": {},
|
||||
"site_pins": {
|
||||
"ODIV2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"ODIV4": {
|
||||
"direction": "OUT"
|
||||
"A1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"A2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"ODIV4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"A0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"A1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O": {
|
||||
"direction": "OUT"
|
||||
}
|
||||
},
|
||||
"site_pips": {}
|
||||
}
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -1,45 +1,45 @@
|
|||
{
|
||||
"type": "STARTUP",
|
||||
"site_pips": {},
|
||||
"site_pins": {
|
||||
"CFGMCLK": {
|
||||
"CFGCLK": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PREQ": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"GSR": {
|
||||
"GTS": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"KEYCLEARB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PREQ": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PACK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"EOS": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"USRDONETS": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"USRCCLKO": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CFGCLK": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"USRDONEO": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"USRCCLKTS": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"GTS": {
|
||||
"EOS": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"GSR": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PACK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"USRDONETS": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CFGMCLK": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"USRDONEO": {
|
||||
"direction": "IN"
|
||||
}
|
||||
},
|
||||
"site_pips": {}
|
||||
}
|
||||
}
|
||||
|
|
@ -1,5 +1,6 @@
|
|||
{
|
||||
"type": "TIEOFF",
|
||||
"site_pips": {},
|
||||
"site_pins": {
|
||||
"HARD1": {
|
||||
"direction": "OUT"
|
||||
|
|
@ -7,6 +8,5 @@
|
|||
"HARD0": {
|
||||
"direction": "OUT"
|
||||
}
|
||||
},
|
||||
"site_pips": {}
|
||||
}
|
||||
}
|
||||
|
|
@ -1,61 +1,65 @@
|
|||
{
|
||||
"type": "USR_ACCESS",
|
||||
"site_pips": {},
|
||||
"site_pins": {
|
||||
"DATA3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA18": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA6": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATAVALID": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA23": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA21": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA31": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA28": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA17": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA30": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CFGCLK": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA29": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA22": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA25": {
|
||||
"DATA12": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA27": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA9": {
|
||||
"DATA30": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA11": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA21": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA22": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA18": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA20": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA7": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA13": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA29": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATAVALID": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA19": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA23": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA15": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA28": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA5": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA31": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CFGCLK": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA26": {
|
||||
|
|
@ -64,45 +68,41 @@
|
|||
"DATA10": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA16": {
|
||||
"DATA6": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA11": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA12": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA20": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA13": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA15": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA5": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA14": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA24": {
|
||||
"DATA25": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA8": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA19": {
|
||||
"DATA2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA7": {
|
||||
"DATA14": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA16": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA17": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA9": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA24": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA1": {
|
||||
"direction": "OUT"
|
||||
}
|
||||
},
|
||||
"site_pips": {}
|
||||
}
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,475 +1,475 @@
|
|||
{
|
||||
"pips": {
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B9->>INT_INTERFACE_LOGIC_OUTS_L9": {
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B22->>INT_INTERFACE_LOGIC_OUTS_L22": {
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L22",
|
||||
"is_directional": "1",
|
||||
"can_invert": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B9",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L9",
|
||||
"is_pseudo": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B4->>INT_INTERFACE_LOGIC_OUTS_L4": {
|
||||
"is_directional": "1",
|
||||
"can_invert": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B4",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L4",
|
||||
"is_pseudo": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B2->>INT_INTERFACE_LOGIC_OUTS_L2": {
|
||||
"is_directional": "1",
|
||||
"can_invert": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B2",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L2",
|
||||
"is_pseudo": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B14->>INT_INTERFACE_LOGIC_OUTS_L14": {
|
||||
"is_directional": "1",
|
||||
"can_invert": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B14",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L14",
|
||||
"is_pseudo": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B13->>INT_INTERFACE_LOGIC_OUTS_L13": {
|
||||
"is_directional": "1",
|
||||
"can_invert": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B13",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L13",
|
||||
"is_pseudo": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B6->>INT_INTERFACE_LOGIC_OUTS_L6": {
|
||||
"is_directional": "1",
|
||||
"can_invert": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B6",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L6",
|
||||
"is_pseudo": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B19->>INT_INTERFACE_LOGIC_OUTS_L19": {
|
||||
"is_directional": "1",
|
||||
"can_invert": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B19",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L19",
|
||||
"is_pseudo": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B17->>INT_INTERFACE_LOGIC_OUTS_L17": {
|
||||
"is_directional": "1",
|
||||
"can_invert": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B17",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L17",
|
||||
"is_pseudo": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B0->>INT_INTERFACE_LOGIC_OUTS_L0": {
|
||||
"is_directional": "1",
|
||||
"can_invert": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L0",
|
||||
"is_pseudo": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B8->>INT_INTERFACE_LOGIC_OUTS_L8": {
|
||||
"is_directional": "1",
|
||||
"can_invert": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B8",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L8",
|
||||
"is_pseudo": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B10->>INT_INTERFACE_LOGIC_OUTS_L10": {
|
||||
"is_directional": "1",
|
||||
"can_invert": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B10",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L10",
|
||||
"is_pseudo": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B15->>INT_INTERFACE_LOGIC_OUTS_L15": {
|
||||
"is_directional": "1",
|
||||
"can_invert": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B15",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L15",
|
||||
"is_pseudo": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B1->>INT_INTERFACE_LOGIC_OUTS_L1": {
|
||||
"is_directional": "1",
|
||||
"can_invert": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B1",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L1",
|
||||
"is_pseudo": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B20->>INT_INTERFACE_LOGIC_OUTS_L20": {
|
||||
"is_directional": "1",
|
||||
"can_invert": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B20",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L20",
|
||||
"is_pseudo": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B11->>INT_INTERFACE_LOGIC_OUTS_L11": {
|
||||
"is_directional": "1",
|
||||
"can_invert": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B11",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L11",
|
||||
"is_pseudo": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B5->>INT_INTERFACE_LOGIC_OUTS_L5": {
|
||||
"is_directional": "1",
|
||||
"can_invert": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B5",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L5",
|
||||
"is_pseudo": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B12->>INT_INTERFACE_LOGIC_OUTS_L12": {
|
||||
"is_directional": "1",
|
||||
"can_invert": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B12",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L12",
|
||||
"is_pseudo": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B21->>INT_INTERFACE_LOGIC_OUTS_L21": {
|
||||
"is_directional": "1",
|
||||
"can_invert": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B21",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L21",
|
||||
"is_pseudo": "0"
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B22",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B16->>INT_INTERFACE_LOGIC_OUTS_L16": {
|
||||
"is_directional": "1",
|
||||
"can_invert": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B16",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L16",
|
||||
"is_pseudo": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B7->>INT_INTERFACE_LOGIC_OUTS_L7": {
|
||||
"is_directional": "1",
|
||||
"can_invert": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B7",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L7",
|
||||
"is_pseudo": "0"
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B16",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B18->>INT_INTERFACE_LOGIC_OUTS_L18": {
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B8->>INT_INTERFACE_LOGIC_OUTS_L8": {
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L8",
|
||||
"is_directional": "1",
|
||||
"can_invert": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B18",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L18",
|
||||
"is_pseudo": "0"
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B8",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B11->>INT_INTERFACE_LOGIC_OUTS_L11": {
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L11",
|
||||
"is_directional": "1",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B11",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B2->>INT_INTERFACE_LOGIC_OUTS_L2": {
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L2",
|
||||
"is_directional": "1",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B2",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B12->>INT_INTERFACE_LOGIC_OUTS_L12": {
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L12",
|
||||
"is_directional": "1",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B12",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B20->>INT_INTERFACE_LOGIC_OUTS_L20": {
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L20",
|
||||
"is_directional": "1",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B20",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B23->>INT_INTERFACE_LOGIC_OUTS_L23": {
|
||||
"is_directional": "1",
|
||||
"can_invert": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B23",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L23",
|
||||
"is_pseudo": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B22->>INT_INTERFACE_LOGIC_OUTS_L22": {
|
||||
"is_directional": "1",
|
||||
"can_invert": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B22",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L22",
|
||||
"is_pseudo": "0"
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B23",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B21->>INT_INTERFACE_LOGIC_OUTS_L21": {
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L21",
|
||||
"is_directional": "1",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B21",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B1->>INT_INTERFACE_LOGIC_OUTS_L1": {
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L1",
|
||||
"is_directional": "1",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B1",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B0->>INT_INTERFACE_LOGIC_OUTS_L0": {
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L0",
|
||||
"is_directional": "1",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B0",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B17->>INT_INTERFACE_LOGIC_OUTS_L17": {
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L17",
|
||||
"is_directional": "1",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B17",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B15->>INT_INTERFACE_LOGIC_OUTS_L15": {
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L15",
|
||||
"is_directional": "1",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B15",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B5->>INT_INTERFACE_LOGIC_OUTS_L5": {
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L5",
|
||||
"is_directional": "1",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B5",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B4->>INT_INTERFACE_LOGIC_OUTS_L4": {
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L4",
|
||||
"is_directional": "1",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B4",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B7->>INT_INTERFACE_LOGIC_OUTS_L7": {
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L7",
|
||||
"is_directional": "1",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B7",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B13->>INT_INTERFACE_LOGIC_OUTS_L13": {
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L13",
|
||||
"is_directional": "1",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B13",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B14->>INT_INTERFACE_LOGIC_OUTS_L14": {
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L14",
|
||||
"is_directional": "1",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B14",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B18->>INT_INTERFACE_LOGIC_OUTS_L18": {
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L18",
|
||||
"is_directional": "1",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B18",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B3->>INT_INTERFACE_LOGIC_OUTS_L3": {
|
||||
"is_directional": "1",
|
||||
"can_invert": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B3",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L3",
|
||||
"is_pseudo": "0"
|
||||
"is_directional": "1",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B3",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B6->>INT_INTERFACE_LOGIC_OUTS_L6": {
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L6",
|
||||
"is_directional": "1",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B6",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B9->>INT_INTERFACE_LOGIC_OUTS_L9": {
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L9",
|
||||
"is_directional": "1",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B9",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B10->>INT_INTERFACE_LOGIC_OUTS_L10": {
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L10",
|
||||
"is_directional": "1",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B10",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B19->>INT_INTERFACE_LOGIC_OUTS_L19": {
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L19",
|
||||
"is_directional": "1",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B19",
|
||||
"can_invert": "0"
|
||||
}
|
||||
},
|
||||
"wires": [
|
||||
"INT_INTERFACE_CLK1",
|
||||
"INT_INTERFACE_EE4C2",
|
||||
"INT_INTERFACE_EE4BEG3",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L0",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX21",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX14",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX42",
|
||||
"INT_INTERFACE_BRAM_IMUX17",
|
||||
"INT_INTERFACE_BYP6",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX27",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX13",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX31",
|
||||
"INT_INTERFACE_BRAM_IMUX24",
|
||||
"INT_INTERFACE_FAN0",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L14",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX37",
|
||||
"INT_INTERFACE_NW2A3",
|
||||
"INT_INTERFACE_EE4C1",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX12",
|
||||
"INT_INTERFACE_FAN5",
|
||||
"INT_INTERFACE_EE4BEG0",
|
||||
"INT_INTERFACE_BRAM_IMUX23",
|
||||
"INT_INTERFACE_CTRL1",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX5",
|
||||
"INT_INTERFACE_BYP0",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B16",
|
||||
"L_INT_INTER_DQS_IOTOPHASER",
|
||||
"INT_INTERFACE_SW4END3",
|
||||
"INT_INTERFACE_EE4A0",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX6",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX10",
|
||||
"INT_INTERFACE_BYP2",
|
||||
"INT_INTERFACE_EE4BEG2",
|
||||
"INT_INTERFACE_WW2END1",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B7",
|
||||
"INT_INTERFACE_WW2A3",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX32",
|
||||
"INT_INTERFACE_LH5",
|
||||
"INT_INTERFACE_NE4C2",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L12",
|
||||
"INT_INTERFACE_BRAM_IMUX3",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L13",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B22",
|
||||
"INT_INTERFACE_BRAM_IMUX25",
|
||||
"INT_INTERFACE_LH3",
|
||||
"INT_INTERFACE_BLOCK_OUTS_L_B2",
|
||||
"INT_INTERFACE_NE2A2",
|
||||
"INT_INTERFACE_WW4A3",
|
||||
"INT_INTERFACE_BRAM_IMUX40",
|
||||
"INT_INTERFACE_SE4BEG2",
|
||||
"INT_INTERFACE_WW4END0",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B14",
|
||||
"INT_INTERFACE_BRAM_IMUX19",
|
||||
"INT_INTERFACE_BRAM_IMUX39",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B1",
|
||||
"INT_INTERFACE_FAN3",
|
||||
"INT_INTERFACE_BRAM_IMUX13",
|
||||
"INT_INTERFACE_BRAM_IMUX46",
|
||||
"INT_INTERFACE_WW4END2",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX20",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B5",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX39",
|
||||
"INT_INTERFACE_NW4A2",
|
||||
"INT_INTERFACE_EL1BEG1",
|
||||
"INT_INTERFACE_SW4END0",
|
||||
"INT_INTERFACE_BYP5",
|
||||
"INT_INTERFACE_BRAM_IMUX35",
|
||||
"INT_INTERFACE_BRAM_IMUX37",
|
||||
"INT_INTERFACE_WW4END3",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX33",
|
||||
"INT_INTERFACE_NE4C0",
|
||||
"INT_INTERFACE_WW4B3",
|
||||
"INT_INTERFACE_NW4END3",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L17",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX26",
|
||||
"INT_INTERFACE_WW2A1",
|
||||
"INT_INTERFACE_WL1END2",
|
||||
"INT_INTERFACE_NW4A0",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX30",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B4",
|
||||
"INT_INTERFACE_LH4",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX22",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B23",
|
||||
"INT_INTERFACE_LH11",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B20",
|
||||
"INT_INTERFACE_BRAM_IMUX15",
|
||||
"INT_INTERFACE_EE2A3",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX2",
|
||||
"INT_INTERFACE_NE4C3",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B21",
|
||||
"INT_INTERFACE_BRAM_IMUX28",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L20",
|
||||
"INT_INTERFACE_EE2BEG2",
|
||||
"INT_INTERFACE_WR1END3",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX38",
|
||||
"INT_INTERFACE_NW4END1",
|
||||
"INT_INTERFACE_BRAM_IMUX30",
|
||||
"INT_INTERFACE_PHASER_TO_IO_ICLKDIV",
|
||||
"INT_INTERFACE_PHASER_TO_IO_OCLK",
|
||||
"INT_INTERFACE_SW2A3",
|
||||
"INT_INTERFACE_NW2A1",
|
||||
"INT_INTERFACE_BRAM_IMUX5",
|
||||
"INT_INTERFACE_EE4BEG1",
|
||||
"INT_INTERFACE_WW4C0",
|
||||
"INT_INTERFACE_SW2A0",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L1",
|
||||
"INT_INTERFACE_WW2A0",
|
||||
"INT_INTERFACE_NW2A0",
|
||||
"INT_INTERFACE_WL1END3",
|
||||
"INT_INTERFACE_NW4END2",
|
||||
"INT_INTERFACE_EL1BEG2",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B18",
|
||||
"INT_INTERFACE_BRAM_IMUX11",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX16",
|
||||
"INT_INTERFACE_BLOCK_OUTS_L_B1",
|
||||
"INT_INTERFACE_BRAM_IMUX34",
|
||||
"INT_INTERFACE_BRAM_IMUX18",
|
||||
"INT_INTERFACE_BRAM_IMUX10",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX44",
|
||||
"INT_INTERFACE_FAN2",
|
||||
"INT_INTERFACE_BRAM_IMUX29",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L3",
|
||||
"INT_INTERFACE_BRAM_IMUX1",
|
||||
"INT_INTERFACE_WW4A0",
|
||||
"INT_INTERFACE_EE2BEG1",
|
||||
"INT_INTERFACE_SW4A2",
|
||||
"INT_INTERFACE_PHASER_TO_IO_OCLK1X_90",
|
||||
"INT_INTERFACE_BRAM_IMUX41",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B6",
|
||||
"INT_INTERFACE_EE4A2",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX47",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L15",
|
||||
"INT_INTERFACE_SW4END1",
|
||||
"INT_INTERFACE_SE2A3",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B10",
|
||||
"INT_INTERFACE_EE4B2",
|
||||
"INT_INTERFACE_SE4C2",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B11",
|
||||
"INT_INTERFACE_LH9",
|
||||
"INT_INTERFACE_SW2A1",
|
||||
"INT_INTERFACE_BRAM_IMUX44",
|
||||
"INT_INTERFACE_ER1BEG0",
|
||||
"INT_INTERFACE_NE4BEG0",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX28",
|
||||
"INT_INTERFACE_WL1END1",
|
||||
"INT_INTERFACE_BRAM_IMUX20",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX19",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX17",
|
||||
"INT_INTERFACE_NW4A1",
|
||||
"INT_INTERFACE_LH2",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B12",
|
||||
"INT_INTERFACE_NE4BEG3",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L11",
|
||||
"INT_INTERFACE_BRAM_IMUX27",
|
||||
"INT_INTERFACE_BYP7",
|
||||
"INT_INTERFACE_NW4END0",
|
||||
"INT_INTERFACE_EE4C3",
|
||||
"INT_INTERFACE_BRAM_IMUX6",
|
||||
"INT_INTERFACE_EE2A0",
|
||||
"INT_INTERFACE_BRAM_IMUX26",
|
||||
"INT_INTERFACE_BYP1",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L10",
|
||||
"INT_INTERFACE_CLK0",
|
||||
"INT_INTERFACE_WR1END0",
|
||||
"INT_INTERFACE_WW2END3",
|
||||
"INT_INTERFACE_SE4BEG1",
|
||||
"INT_INTERFACE_FAN1",
|
||||
"INT_INTERFACE_MONITOR_P",
|
||||
"INT_INTERFACE_LH1",
|
||||
"INT_INTERFACE_LH6",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B0",
|
||||
"INT_INTERFACE_FAN4",
|
||||
"INT_INTERFACE_BRAM_IMUX12",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L9",
|
||||
"INT_INTERFACE_EE2BEG3",
|
||||
"INT_INTERFACE_WR1END2",
|
||||
"INT_INTERFACE_MONITOR_N",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX41",
|
||||
"INT_INTERFACE_BRAM_IMUX9",
|
||||
"INT_INTERFACE_EE2A2",
|
||||
"INT_INTERFACE_SE2A2",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L2",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L4",
|
||||
"INT_INTERFACE_NE4C1",
|
||||
"INT_INTERFACE_ER1BEG2",
|
||||
"INT_INTERFACE_SE4BEG3",
|
||||
"INT_INTERFACE_EE4A1",
|
||||
"INT_INTERFACE_NE2A3",
|
||||
"INT_INTERFACE_WW4B1",
|
||||
"INT_INTERFACE_SE2A0",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B9",
|
||||
"INT_INTERFACE_BRAM_IMUX8",
|
||||
"INT_INTERFACE_EE4B3",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L7",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B19",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L21",
|
||||
"INT_INTERFACE_LH8",
|
||||
"INT_INTERFACE_BRAM_IMUX22",
|
||||
"INT_INTERFACE_BRAM_IMUX16",
|
||||
"INT_INTERFACE_EE4B1",
|
||||
"INT_INTERFACE_BYP4",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX11",
|
||||
"INT_INTERFACE_WW4END1",
|
||||
"INT_INTERFACE_SE4BEG0",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX35",
|
||||
"INT_INTERFACE_LH7",
|
||||
"INT_INTERFACE_BRAM_IMUX36",
|
||||
"INT_INTERFACE_BRAM_IMUX47",
|
||||
"INT_INTERFACE_LH10",
|
||||
"INT_INTERFACE_PHASER_TO_IO_ICLK",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L8",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX23",
|
||||
"INT_INTERFACE_PHASER_TO_IO_OCLKDIV",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX18",
|
||||
"INT_INTERFACE_ER1BEG1",
|
||||
"INT_INTERFACE_NE4BEG1",
|
||||
"INT_INTERFACE_BLOCK_OUTS_L_B3",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX0",
|
||||
"INT_INTERFACE_SW4A0",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX9",
|
||||
"INT_INTERFACE_SW4A3",
|
||||
"INT_INTERFACE_WW4B2",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX40",
|
||||
"INT_INTERFACE_FAN7",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L18",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX17",
|
||||
"INT_INTERFACE_SE4C0",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B15",
|
||||
"INT_INTERFACE_EE4BEG1",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX19",
|
||||
"INT_INTERFACE_EL1BEG3",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX12",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX15",
|
||||
"INT_INTERFACE_NE4BEG0",
|
||||
"INT_INTERFACE_BRAM_IMUX12",
|
||||
"INT_INTERFACE_BRAM_IMUX7",
|
||||
"INT_INTERFACE_WW2A0",
|
||||
"INT_INTERFACE_BRAM_IMUX18",
|
||||
"INT_INTERFACE_EE2A3",
|
||||
"INT_INTERFACE_FAN5",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX10",
|
||||
"INT_INTERFACE_WW4C3",
|
||||
"INT_INTERFACE_BRAM_IMUX30",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX28",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX29",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX27",
|
||||
"INT_INTERFACE_BRAM_IMUX10",
|
||||
"INT_INTERFACE_BRAM_IMUX23",
|
||||
"INT_INTERFACE_BLOCK_OUTS_L_B1",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX45",
|
||||
"INT_INTERFACE_WW2END0",
|
||||
"INT_INTERFACE_BRAM_IMUX43",
|
||||
"INT_INTERFACE_WW4A2",
|
||||
"INT_INTERFACE_EE4B0",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX25",
|
||||
"INT_INTERFACE_NE2A1",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L5",
|
||||
"INT_INTERFACE_EE4C0",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L23",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX8",
|
||||
"INT_INTERFACE_SE4C0",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B13",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX4",
|
||||
"INT_INTERFACE_BRAM_IMUX45",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX7",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L16",
|
||||
"INT_INTERFACE_BLOCK_OUTS_L_B0",
|
||||
"INT_INTERFACE_SW2A2",
|
||||
"INT_INTERFACE_BRAM_IMUX31",
|
||||
"INT_INTERFACE_WW4C3",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B15",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L19",
|
||||
"INT_INTERFACE_NE2A0",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B3",
|
||||
"INT_INTERFACE_EE2BEG0",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B8",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B17",
|
||||
"INT_INTERFACE_BRAM_IMUX14",
|
||||
"INT_INTERFACE_WW4B0",
|
||||
"INT_INTERFACE_NW2A2",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX43",
|
||||
"INT_INTERFACE_WW2END2",
|
||||
"INT_INTERFACE_SE2A1",
|
||||
"INT_INTERFACE_BRAM_IMUX32",
|
||||
"INT_INTERFACE_EL1BEG0",
|
||||
"INT_INTERFACE_BRAM_IMUX7",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L18",
|
||||
"INT_INTERFACE_BRAM_IMUX33",
|
||||
"INT_INTERFACE_BRAM_IMUX42",
|
||||
"INT_INTERFACE_WW4C2",
|
||||
"INT_INTERFACE_WW4C1",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX46",
|
||||
"INT_INTERFACE_BRAM_IMUX21",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX24",
|
||||
"INT_INTERFACE_NE4BEG2",
|
||||
"INT_INTERFACE_BRAM_IMUX38",
|
||||
"INT_INTERFACE_EE4A3",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX1",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX34",
|
||||
"INT_INTERFACE_CTRL0",
|
||||
"INT_INTERFACE_BRAM_IMUX0",
|
||||
"INT_INTERFACE_SE4C1",
|
||||
"INT_INTERFACE_WL1END0",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L6",
|
||||
"INT_INTERFACE_WW4A1",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B2",
|
||||
"INT_INTERFACE_NW2A0",
|
||||
"INT_INTERFACE_BRAM_IMUX25",
|
||||
"INT_INTERFACE_BYP3",
|
||||
"INT_INTERFACE_EL1BEG3",
|
||||
"INT_INTERFACE_FAN6",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX15",
|
||||
"INT_INTERFACE_LH12",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX36",
|
||||
"INT_INTERFACE_WR1END1",
|
||||
"INT_INTERFACE_BRAM_IMUX2",
|
||||
"INT_INTERFACE_ER1BEG3",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX3",
|
||||
"INT_INTERFACE_SW4A1",
|
||||
"INT_INTERFACE_EE2A1",
|
||||
"INT_INTERFACE_WW2A2",
|
||||
"INT_INTERFACE_SE4C3",
|
||||
"INT_INTERFACE_NW4A3",
|
||||
"INT_INTERFACE_SW4END2",
|
||||
"INT_INTERFACE_EE4B2",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B2",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L0",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX39",
|
||||
"INT_INTERFACE_NW2A3",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX32",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX25",
|
||||
"INT_INTERFACE_BRAM_IMUX28",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX38",
|
||||
"INT_INTERFACE_BLOCK_OUTS_L_B0",
|
||||
"INT_INTERFACE_EL1BEG1",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B21",
|
||||
"INT_INTERFACE_BRAM_IMUX32",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX24",
|
||||
"INT_INTERFACE_LH11",
|
||||
"INT_INTERFACE_EE4B0",
|
||||
"INT_INTERFACE_BRAM_IMUX34",
|
||||
"INT_INTERFACE_BRAM_IMUX20",
|
||||
"INT_INTERFACE_BRAM_IMUX0",
|
||||
"INT_INTERFACE_BRAM_IMUX9",
|
||||
"INT_INTERFACE_BRAM_IMUX1",
|
||||
"INT_INTERFACE_ER1BEG0",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX6",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B23",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX21",
|
||||
"INT_INTERFACE_WW4B2",
|
||||
"INT_INTERFACE_NE4BEG3",
|
||||
"INT_INTERFACE_BRAM_IMUX43",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L22",
|
||||
"INT_INTERFACE_BYP6",
|
||||
"INT_INTERFACE_WW4B0",
|
||||
"INT_INTERFACE_BRAM_IMUX21",
|
||||
"INT_INTERFACE_LH2",
|
||||
"INT_INTERFACE_BRAM_IMUX4",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX29"
|
||||
"INT_INTERFACE_NE2A3",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L11",
|
||||
"INT_INTERFACE_SE4C1",
|
||||
"INT_INTERFACE_BRAM_IMUX24",
|
||||
"INT_INTERFACE_WL1END1",
|
||||
"INT_INTERFACE_NW4A0",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX35",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B8",
|
||||
"INT_INTERFACE_WW4END2",
|
||||
"INT_INTERFACE_BRAM_IMUX47",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX47",
|
||||
"INT_INTERFACE_NE4C3",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L23",
|
||||
"INT_INTERFACE_EE4C0",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX40",
|
||||
"INT_INTERFACE_BRAM_IMUX38",
|
||||
"INT_INTERFACE_SW4END3",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L13",
|
||||
"INT_INTERFACE_SW4END2",
|
||||
"INT_INTERFACE_BRAM_IMUX13",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX43",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L8",
|
||||
"INT_INTERFACE_FAN6",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L21",
|
||||
"INT_INTERFACE_BRAM_IMUX19",
|
||||
"INT_INTERFACE_EE2A0",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L3",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX8",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L1",
|
||||
"INT_INTERFACE_BRAM_IMUX27",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX11",
|
||||
"INT_INTERFACE_BRAM_IMUX29",
|
||||
"INT_INTERFACE_LH7",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L9",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B3",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B14",
|
||||
"INT_INTERFACE_WW4END3",
|
||||
"INT_INTERFACE_SW4A2",
|
||||
"INT_INTERFACE_SW4A1",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX23",
|
||||
"INT_INTERFACE_BRAM_IMUX16",
|
||||
"INT_INTERFACE_SE2A1",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L20",
|
||||
"INT_INTERFACE_LH6",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX9",
|
||||
"INT_INTERFACE_LH5",
|
||||
"INT_INTERFACE_BRAM_IMUX40",
|
||||
"L_INT_INTER_DQS_IOTOPHASER",
|
||||
"INT_INTERFACE_WW4A0",
|
||||
"INT_INTERFACE_SE4BEG2",
|
||||
"INT_INTERFACE_NW4A2",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B1",
|
||||
"INT_INTERFACE_BRAM_IMUX35",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B20",
|
||||
"INT_INTERFACE_BRAM_IMUX45",
|
||||
"INT_INTERFACE_WR1END3",
|
||||
"INT_INTERFACE_BRAM_IMUX39",
|
||||
"INT_INTERFACE_EE4C1",
|
||||
"INT_INTERFACE_FAN7",
|
||||
"INT_INTERFACE_EE4BEG0",
|
||||
"INT_INTERFACE_BRAM_IMUX15",
|
||||
"INT_INTERFACE_BRAM_IMUX46",
|
||||
"INT_INTERFACE_SW2A1",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX46",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B13",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B16",
|
||||
"INT_INTERFACE_LH8",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX42",
|
||||
"INT_INTERFACE_LH9",
|
||||
"INT_INTERFACE_SE2A2",
|
||||
"INT_INTERFACE_SW4A3",
|
||||
"INT_INTERFACE_SE2A3",
|
||||
"INT_INTERFACE_NW4END2",
|
||||
"INT_INTERFACE_EE4C3",
|
||||
"INT_INTERFACE_EE2A1",
|
||||
"INT_INTERFACE_SE4BEG1",
|
||||
"INT_INTERFACE_NW4END1",
|
||||
"INT_INTERFACE_WL1END3",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L17",
|
||||
"INT_INTERFACE_PHASER_TO_IO_ICLK",
|
||||
"INT_INTERFACE_NE4C0",
|
||||
"INT_INTERFACE_WR1END2",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L4",
|
||||
"INT_INTERFACE_BRAM_IMUX33",
|
||||
"INT_INTERFACE_NW4A3",
|
||||
"INT_INTERFACE_WR1END0",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX18",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX33",
|
||||
"INT_INTERFACE_NE2A0",
|
||||
"INT_INTERFACE_EE4BEG3",
|
||||
"INT_INTERFACE_ER1BEG2",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B0",
|
||||
"INT_INTERFACE_BRAM_IMUX5",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B9",
|
||||
"INT_INTERFACE_WW2END1",
|
||||
"INT_INTERFACE_BRAM_IMUX3",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B22",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX4",
|
||||
"INT_INTERFACE_EE4A1",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B19",
|
||||
"INT_INTERFACE_WW2A1",
|
||||
"INT_INTERFACE_LH3",
|
||||
"INT_INTERFACE_WL1END0",
|
||||
"INT_INTERFACE_WR1END1",
|
||||
"INT_INTERFACE_WW4B1",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX7",
|
||||
"INT_INTERFACE_BYP7",
|
||||
"INT_INTERFACE_PHASER_TO_IO_OCLKDIV",
|
||||
"INT_INTERFACE_WW4C0",
|
||||
"INT_INTERFACE_SW2A0",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B18",
|
||||
"INT_INTERFACE_SE4BEG3",
|
||||
"INT_INTERFACE_LH1",
|
||||
"INT_INTERFACE_WW4B3",
|
||||
"INT_INTERFACE_BRAM_IMUX41",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX22",
|
||||
"INT_INTERFACE_WW4A1",
|
||||
"INT_INTERFACE_BRAM_IMUX31",
|
||||
"INT_INTERFACE_ER1BEG1",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L14",
|
||||
"INT_INTERFACE_SW4A0",
|
||||
"INT_INTERFACE_NW4A1",
|
||||
"INT_INTERFACE_EL1BEG0",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L15",
|
||||
"INT_INTERFACE_LH4",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX34",
|
||||
"INT_INTERFACE_PHASER_TO_IO_OCLK",
|
||||
"INT_INTERFACE_BRAM_IMUX6",
|
||||
"INT_INTERFACE_WW4A3",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B5",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L12",
|
||||
"INT_INTERFACE_NE2A2",
|
||||
"INT_INTERFACE_PHASER_TO_IO_ICLKDIV",
|
||||
"INT_INTERFACE_WW2END2",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B11",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L19",
|
||||
"INT_INTERFACE_WW4A2",
|
||||
"INT_INTERFACE_WL1END2",
|
||||
"INT_INTERFACE_EE4A3",
|
||||
"INT_INTERFACE_BYP2",
|
||||
"INT_INTERFACE_NE4BEG1",
|
||||
"INT_INTERFACE_BYP0",
|
||||
"INT_INTERFACE_EE4BEG2",
|
||||
"INT_INTERFACE_FAN0",
|
||||
"INT_INTERFACE_WW2A3",
|
||||
"INT_INTERFACE_NW4END3",
|
||||
"INT_INTERFACE_LH12",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L10",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX1",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX16",
|
||||
"INT_INTERFACE_SW4END1",
|
||||
"INT_INTERFACE_WW4C2",
|
||||
"INT_INTERFACE_NE4BEG2",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX37",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L2",
|
||||
"INT_INTERFACE_BRAM_IMUX36",
|
||||
"INT_INTERFACE_CTRL0",
|
||||
"INT_INTERFACE_ER1BEG3",
|
||||
"INT_INTERFACE_BRAM_IMUX22",
|
||||
"INT_INTERFACE_BYP5",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B10",
|
||||
"INT_INTERFACE_SW2A2",
|
||||
"INT_INTERFACE_CTRL1",
|
||||
"INT_INTERFACE_NE2A1",
|
||||
"INT_INTERFACE_EE2BEG3",
|
||||
"INT_INTERFACE_NW4END0",
|
||||
"INT_INTERFACE_NW2A2",
|
||||
"INT_INTERFACE_WW2END3",
|
||||
"INT_INTERFACE_BRAM_IMUX42",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX36",
|
||||
"INT_INTERFACE_EE4C2",
|
||||
"INT_INTERFACE_EE2BEG1",
|
||||
"INT_INTERFACE_CLK1",
|
||||
"INT_INTERFACE_FAN3",
|
||||
"INT_INTERFACE_WW4C1",
|
||||
"INT_INTERFACE_BYP1",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L5",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L16",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX31",
|
||||
"INT_INTERFACE_EL1BEG2",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX26",
|
||||
"INT_INTERFACE_BYP4",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B17",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX2",
|
||||
"INT_INTERFACE_MONITOR_P",
|
||||
"INT_INTERFACE_NW2A1",
|
||||
"INT_INTERFACE_WW2A2",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX13",
|
||||
"INT_INTERFACE_SE2A0",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX20",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX14",
|
||||
"INT_INTERFACE_NE4C2",
|
||||
"INT_INTERFACE_FAN1",
|
||||
"INT_INTERFACE_EE4B1",
|
||||
"INT_INTERFACE_SW2A3",
|
||||
"INT_INTERFACE_EE2A2",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B12",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX0",
|
||||
"INT_INTERFACE_SE4C3",
|
||||
"INT_INTERFACE_EE2BEG2",
|
||||
"INT_INTERFACE_BRAM_IMUX26",
|
||||
"INT_INTERFACE_BRAM_IMUX11",
|
||||
"INT_INTERFACE_EE2BEG0",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX41",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L6",
|
||||
"INT_INTERFACE_PHASER_TO_IO_OCLK1X_90",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B4",
|
||||
"INT_INTERFACE_SE4BEG0",
|
||||
"INT_INTERFACE_SE4C2",
|
||||
"INT_INTERFACE_BRAM_IMUX44",
|
||||
"INT_INTERFACE_WW4END1",
|
||||
"INT_INTERFACE_BRAM_IMUX17",
|
||||
"INT_INTERFACE_FAN4",
|
||||
"INT_INTERFACE_BRAM_IMUX2",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX3",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B6",
|
||||
"INT_INTERFACE_BLOCK_OUTS_L_B3",
|
||||
"INT_INTERFACE_MONITOR_N",
|
||||
"INT_INTERFACE_BRAM_IMUX14",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX44",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX30",
|
||||
"INT_INTERFACE_BLOCK_OUTS_L_B2",
|
||||
"INT_INTERFACE_BRAM_IMUX37",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX5",
|
||||
"INT_INTERFACE_SW4END0",
|
||||
"INT_INTERFACE_WW4END0",
|
||||
"INT_INTERFACE_EE4B3",
|
||||
"INT_INTERFACE_EE4A0",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L7",
|
||||
"INT_INTERFACE_CLK0",
|
||||
"INT_INTERFACE_NE4C1",
|
||||
"INT_INTERFACE_FAN2",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B7",
|
||||
"INT_INTERFACE_EE4A2",
|
||||
"INT_INTERFACE_BRAM_IMUX8"
|
||||
],
|
||||
"tile_type": "BRAM_INT_INTERFACE_L",
|
||||
"sites": []
|
||||
|
|
|
|||
|
|
@ -1,475 +1,475 @@
|
|||
{
|
||||
"pips": {
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B4->>INT_INTERFACE_LOGIC_OUTS4": {
|
||||
"is_directional": "1",
|
||||
"can_invert": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B4",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS4",
|
||||
"is_pseudo": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B1->>INT_INTERFACE_LOGIC_OUTS1": {
|
||||
"is_directional": "1",
|
||||
"can_invert": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B1",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS1",
|
||||
"is_pseudo": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B0->>INT_INTERFACE_LOGIC_OUTS0": {
|
||||
"is_directional": "1",
|
||||
"can_invert": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS0",
|
||||
"is_pseudo": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B20->>INT_INTERFACE_LOGIC_OUTS20": {
|
||||
"is_directional": "1",
|
||||
"can_invert": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B20",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS20",
|
||||
"is_pseudo": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B22->>INT_INTERFACE_LOGIC_OUTS22": {
|
||||
"is_directional": "1",
|
||||
"can_invert": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B22",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS22",
|
||||
"is_pseudo": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B23->>INT_INTERFACE_LOGIC_OUTS23": {
|
||||
"is_directional": "1",
|
||||
"can_invert": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B23",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS23",
|
||||
"is_pseudo": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B11->>INT_INTERFACE_LOGIC_OUTS11": {
|
||||
"is_directional": "1",
|
||||
"can_invert": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B11",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS11",
|
||||
"is_pseudo": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B18->>INT_INTERFACE_LOGIC_OUTS18": {
|
||||
"is_directional": "1",
|
||||
"can_invert": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B18",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS18",
|
||||
"is_pseudo": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B3->>INT_INTERFACE_LOGIC_OUTS3": {
|
||||
"is_directional": "1",
|
||||
"can_invert": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B3",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS3",
|
||||
"is_pseudo": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B17->>INT_INTERFACE_LOGIC_OUTS17": {
|
||||
"is_directional": "1",
|
||||
"can_invert": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B17",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS17",
|
||||
"is_pseudo": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B15->>INT_INTERFACE_LOGIC_OUTS15": {
|
||||
"is_directional": "1",
|
||||
"can_invert": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B15",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS15",
|
||||
"is_pseudo": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B12->>INT_INTERFACE_LOGIC_OUTS12": {
|
||||
"is_directional": "1",
|
||||
"can_invert": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B12",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS12",
|
||||
"is_pseudo": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B13->>INT_INTERFACE_LOGIC_OUTS13": {
|
||||
"is_directional": "1",
|
||||
"can_invert": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B13",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS13",
|
||||
"is_pseudo": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B9->>INT_INTERFACE_LOGIC_OUTS9": {
|
||||
"is_directional": "1",
|
||||
"can_invert": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B9",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS9",
|
||||
"is_pseudo": "0"
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B4",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B21->>INT_INTERFACE_LOGIC_OUTS21": {
|
||||
"is_directional": "1",
|
||||
"can_invert": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B21",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS21",
|
||||
"is_pseudo": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B7->>INT_INTERFACE_LOGIC_OUTS7": {
|
||||
"is_directional": "1",
|
||||
"can_invert": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B7",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS7",
|
||||
"is_pseudo": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B5->>INT_INTERFACE_LOGIC_OUTS5": {
|
||||
"is_directional": "1",
|
||||
"can_invert": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B5",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS5",
|
||||
"is_pseudo": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B10->>INT_INTERFACE_LOGIC_OUTS10": {
|
||||
"is_directional": "1",
|
||||
"can_invert": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B10",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS10",
|
||||
"is_pseudo": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B14->>INT_INTERFACE_LOGIC_OUTS14": {
|
||||
"is_directional": "1",
|
||||
"can_invert": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B14",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS14",
|
||||
"is_pseudo": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B16->>INT_INTERFACE_LOGIC_OUTS16": {
|
||||
"is_directional": "1",
|
||||
"can_invert": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B16",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS16",
|
||||
"is_pseudo": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B19->>INT_INTERFACE_LOGIC_OUTS19": {
|
||||
"is_directional": "1",
|
||||
"can_invert": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B19",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS19",
|
||||
"is_pseudo": "0"
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B21",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B2->>INT_INTERFACE_LOGIC_OUTS2": {
|
||||
"is_directional": "1",
|
||||
"can_invert": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B2",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS2",
|
||||
"is_pseudo": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B6->>INT_INTERFACE_LOGIC_OUTS6": {
|
||||
"is_directional": "1",
|
||||
"can_invert": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B6",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS6",
|
||||
"is_pseudo": "0"
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B2",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B10->>INT_INTERFACE_LOGIC_OUTS10": {
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS10",
|
||||
"is_directional": "1",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B10",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B5->>INT_INTERFACE_LOGIC_OUTS5": {
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS5",
|
||||
"is_directional": "1",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B5",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B16->>INT_INTERFACE_LOGIC_OUTS16": {
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS16",
|
||||
"is_directional": "1",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B16",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B13->>INT_INTERFACE_LOGIC_OUTS13": {
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS13",
|
||||
"is_directional": "1",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B13",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B14->>INT_INTERFACE_LOGIC_OUTS14": {
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS14",
|
||||
"is_directional": "1",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B14",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B7->>INT_INTERFACE_LOGIC_OUTS7": {
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS7",
|
||||
"is_directional": "1",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B7",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B11->>INT_INTERFACE_LOGIC_OUTS11": {
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS11",
|
||||
"is_directional": "1",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B11",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B1->>INT_INTERFACE_LOGIC_OUTS1": {
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS1",
|
||||
"is_directional": "1",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B1",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B15->>INT_INTERFACE_LOGIC_OUTS15": {
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS15",
|
||||
"is_directional": "1",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B15",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B23->>INT_INTERFACE_LOGIC_OUTS23": {
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS23",
|
||||
"is_directional": "1",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B23",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B8->>INT_INTERFACE_LOGIC_OUTS8": {
|
||||
"is_directional": "1",
|
||||
"can_invert": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B8",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS8",
|
||||
"is_pseudo": "0"
|
||||
"is_directional": "1",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B8",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B17->>INT_INTERFACE_LOGIC_OUTS17": {
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS17",
|
||||
"is_directional": "1",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B17",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B22->>INT_INTERFACE_LOGIC_OUTS22": {
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS22",
|
||||
"is_directional": "1",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B22",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B19->>INT_INTERFACE_LOGIC_OUTS19": {
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS19",
|
||||
"is_directional": "1",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B19",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B20->>INT_INTERFACE_LOGIC_OUTS20": {
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS20",
|
||||
"is_directional": "1",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B20",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B6->>INT_INTERFACE_LOGIC_OUTS6": {
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS6",
|
||||
"is_directional": "1",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B6",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B9->>INT_INTERFACE_LOGIC_OUTS9": {
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS9",
|
||||
"is_directional": "1",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B9",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B18->>INT_INTERFACE_LOGIC_OUTS18": {
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS18",
|
||||
"is_directional": "1",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B18",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B12->>INT_INTERFACE_LOGIC_OUTS12": {
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS12",
|
||||
"is_directional": "1",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B12",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B0->>INT_INTERFACE_LOGIC_OUTS0": {
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS0",
|
||||
"is_directional": "1",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B0",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B3->>INT_INTERFACE_LOGIC_OUTS3": {
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS3",
|
||||
"is_directional": "1",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B3",
|
||||
"can_invert": "0"
|
||||
}
|
||||
},
|
||||
"wires": [
|
||||
"INT_INTERFACE_CLK1",
|
||||
"INT_INTERFACE_EE4C2",
|
||||
"INT_INTERFACE_EE4BEG3",
|
||||
"INT_INTERFACE_BRAM_IMUX17",
|
||||
"INT_INTERFACE_BYP6",
|
||||
"INT_INTERFACE_BRAM_IMUX24",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX18",
|
||||
"INT_INTERFACE_FAN0",
|
||||
"INT_INTERFACE_LOGIC_OUTS8",
|
||||
"INT_INTERFACE_NW2A3",
|
||||
"INT_INTERFACE_LOGIC_OUTS13",
|
||||
"INT_INTERFACE_EE4C1",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX28",
|
||||
"INT_INTERFACE_FAN5",
|
||||
"INT_INTERFACE_EE4BEG0",
|
||||
"INT_INTERFACE_BRAM_IMUX23",
|
||||
"INT_INTERFACE_CTRL1",
|
||||
"INT_INTERFACE_BYP0",
|
||||
"INT_INTERFACE_LOGIC_OUTS14",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX19",
|
||||
"INT_INTERFACE_SW4END3",
|
||||
"L_INT_INTER_DQS_IOTOPHASER",
|
||||
"INT_INTERFACE_EE4A0",
|
||||
"INT_INTERFACE_BYP2",
|
||||
"INT_INTERFACE_EE4BEG2",
|
||||
"INT_INTERFACE_LOGIC_OUTS2",
|
||||
"INT_INTERFACE_WW2END1",
|
||||
"INT_INTERFACE_WW2A3",
|
||||
"INT_INTERFACE_LH5",
|
||||
"INT_INTERFACE_NE4C2",
|
||||
"INT_INTERFACE_BRAM_IMUX3",
|
||||
"INT_INTERFACE_BLOCK_OUTS_B2",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX14",
|
||||
"INT_INTERFACE_BRAM_IMUX25",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX46",
|
||||
"INT_INTERFACE_LH3",
|
||||
"INT_INTERFACE_LOGIC_OUTS6",
|
||||
"INT_INTERFACE_NE2A2",
|
||||
"INT_INTERFACE_WW4A3",
|
||||
"INT_INTERFACE_BRAM_IMUX40",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX8",
|
||||
"INT_INTERFACE_SE4BEG2",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B6",
|
||||
"INT_INTERFACE_WW4END0",
|
||||
"INT_INTERFACE_BRAM_IMUX19",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B23",
|
||||
"INT_INTERFACE_BRAM_IMUX39",
|
||||
"INT_INTERFACE_LOGIC_OUTS22",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX47",
|
||||
"INT_INTERFACE_FAN3",
|
||||
"INT_INTERFACE_BRAM_IMUX13",
|
||||
"INT_INTERFACE_BRAM_IMUX46",
|
||||
"INT_INTERFACE_BLOCK_OUTS_B1",
|
||||
"INT_INTERFACE_WW4END2",
|
||||
"INT_INTERFACE_LOGIC_OUTS11",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX4",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B1",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX24",
|
||||
"INT_INTERFACE_NW4A2",
|
||||
"INT_INTERFACE_EL1BEG1",
|
||||
"INT_INTERFACE_SW4END0",
|
||||
"INT_INTERFACE_BYP5",
|
||||
"INT_INTERFACE_BRAM_IMUX35",
|
||||
"INT_INTERFACE_BRAM_IMUX37",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B16",
|
||||
"INT_INTERFACE_WW4END3",
|
||||
"INT_INTERFACE_NE4C0",
|
||||
"INT_INTERFACE_WW4B3",
|
||||
"INT_INTERFACE_NW4END3",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B19",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX30",
|
||||
"INT_INTERFACE_LOGIC_OUTS1",
|
||||
"INT_INTERFACE_WW2A1",
|
||||
"INT_INTERFACE_WL1END2",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B21",
|
||||
"INT_INTERFACE_NW4A0",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B17",
|
||||
"INT_INTERFACE_LH4",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX31",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX3",
|
||||
"INT_INTERFACE_LH11",
|
||||
"INT_INTERFACE_BRAM_IMUX15",
|
||||
"INT_INTERFACE_EE2A3",
|
||||
"INT_INTERFACE_NE4C3",
|
||||
"INT_INTERFACE_BRAM_IMUX28",
|
||||
"INT_INTERFACE_EE2BEG2",
|
||||
"INT_INTERFACE_WR1END3",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B14",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B10",
|
||||
"INT_INTERFACE_NW4END1",
|
||||
"INT_INTERFACE_LOGIC_OUTS20",
|
||||
"INT_INTERFACE_BRAM_IMUX30",
|
||||
"INT_INTERFACE_PHASER_TO_IO_ICLKDIV",
|
||||
"INT_INTERFACE_PHASER_TO_IO_OCLK",
|
||||
"INT_INTERFACE_LOGIC_OUTS12",
|
||||
"INT_INTERFACE_SW2A3",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX27",
|
||||
"INT_INTERFACE_NW2A1",
|
||||
"INT_INTERFACE_BRAM_IMUX5",
|
||||
"INT_INTERFACE_WW4C0",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX0",
|
||||
"INT_INTERFACE_SW2A0",
|
||||
"INT_INTERFACE_EE4BEG1",
|
||||
"INT_INTERFACE_WW2A0",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX26",
|
||||
"INT_INTERFACE_NW2A0",
|
||||
"INT_INTERFACE_WL1END3",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B15",
|
||||
"INT_INTERFACE_NW4END2",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX42",
|
||||
"INT_INTERFACE_EL1BEG2",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX23",
|
||||
"INT_INTERFACE_BRAM_IMUX11",
|
||||
"INT_INTERFACE_BRAM_IMUX34",
|
||||
"INT_INTERFACE_BRAM_IMUX18",
|
||||
"INT_INTERFACE_BRAM_IMUX10",
|
||||
"INT_INTERFACE_FAN2",
|
||||
"INT_INTERFACE_LOGIC_OUTS3",
|
||||
"INT_INTERFACE_BRAM_IMUX29",
|
||||
"INT_INTERFACE_BRAM_IMUX1",
|
||||
"INT_INTERFACE_WW4A0",
|
||||
"INT_INTERFACE_EE2BEG1",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX16",
|
||||
"INT_INTERFACE_SW4A2",
|
||||
"INT_INTERFACE_PHASER_TO_IO_OCLK1X_90",
|
||||
"INT_INTERFACE_BRAM_IMUX41",
|
||||
"INT_INTERFACE_EE4A2",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B0",
|
||||
"INT_INTERFACE_SW4END1",
|
||||
"INT_INTERFACE_SE2A3",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B2",
|
||||
"INT_INTERFACE_EE4B2",
|
||||
"INT_INTERFACE_LOGIC_OUTS23",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B13",
|
||||
"INT_INTERFACE_SE4C2",
|
||||
"INT_INTERFACE_LH9",
|
||||
"INT_INTERFACE_SW2A1",
|
||||
"INT_INTERFACE_BRAM_IMUX44",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX40",
|
||||
"INT_INTERFACE_ER1BEG0",
|
||||
"INT_INTERFACE_NE4BEG0",
|
||||
"INT_INTERFACE_WL1END1",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B5",
|
||||
"INT_INTERFACE_BRAM_IMUX20",
|
||||
"INT_INTERFACE_NW4A1",
|
||||
"INT_INTERFACE_LH2",
|
||||
"INT_INTERFACE_NE4BEG3",
|
||||
"INT_INTERFACE_BRAM_IMUX27",
|
||||
"INT_INTERFACE_BYP7",
|
||||
"INT_INTERFACE_NW4END0",
|
||||
"INT_INTERFACE_EE4C3",
|
||||
"INT_INTERFACE_EE2A0",
|
||||
"INT_INTERFACE_BRAM_IMUX6",
|
||||
"INT_INTERFACE_BRAM_IMUX26",
|
||||
"INT_INTERFACE_BYP1",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX43",
|
||||
"INT_INTERFACE_CLK0",
|
||||
"INT_INTERFACE_LOGIC_OUTS7",
|
||||
"INT_INTERFACE_WR1END0",
|
||||
"INT_INTERFACE_WW2END3",
|
||||
"INT_INTERFACE_SE4BEG1",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B4",
|
||||
"INT_INTERFACE_FAN1",
|
||||
"INT_INTERFACE_BLOCK_OUTS_B0",
|
||||
"INT_INTERFACE_MONITOR_P",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B8",
|
||||
"INT_INTERFACE_LH1",
|
||||
"INT_INTERFACE_LH6",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B18",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX9",
|
||||
"INT_INTERFACE_FAN4",
|
||||
"INT_INTERFACE_BRAM_IMUX12",
|
||||
"INT_INTERFACE_EE2BEG3",
|
||||
"INT_INTERFACE_WR1END2",
|
||||
"INT_INTERFACE_MONITOR_N",
|
||||
"INT_INTERFACE_LOGIC_OUTS15",
|
||||
"INT_INTERFACE_BRAM_IMUX9",
|
||||
"INT_INTERFACE_LOGIC_OUTS21",
|
||||
"INT_INTERFACE_EE2A2",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX15",
|
||||
"INT_INTERFACE_SE2A2",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX13",
|
||||
"INT_INTERFACE_NE4C1",
|
||||
"INT_INTERFACE_ER1BEG2",
|
||||
"INT_INTERFACE_LOGIC_OUTS19",
|
||||
"INT_INTERFACE_SE4BEG3",
|
||||
"INT_INTERFACE_EE4A1",
|
||||
"INT_INTERFACE_NE2A3",
|
||||
"INT_INTERFACE_WW4B1",
|
||||
"INT_INTERFACE_SE2A0",
|
||||
"INT_INTERFACE_BRAM_IMUX8",
|
||||
"INT_INTERFACE_EE4B3",
|
||||
"INT_INTERFACE_BLOCK_OUTS_B3",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B7",
|
||||
"INT_INTERFACE_LH8",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX2",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX1",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX44",
|
||||
"INT_INTERFACE_BRAM_IMUX22",
|
||||
"INT_INTERFACE_BRAM_IMUX16",
|
||||
"INT_INTERFACE_EE4B1",
|
||||
"INT_INTERFACE_BYP4",
|
||||
"INT_INTERFACE_WW4END1",
|
||||
"INT_INTERFACE_SE4BEG0",
|
||||
"INT_INTERFACE_LH7",
|
||||
"INT_INTERFACE_BRAM_IMUX36",
|
||||
"INT_INTERFACE_BRAM_IMUX47",
|
||||
"INT_INTERFACE_LH10",
|
||||
"INT_INTERFACE_LOGIC_OUTS10",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX45",
|
||||
"INT_INTERFACE_PHASER_TO_IO_ICLK",
|
||||
"INT_INTERFACE_PHASER_TO_IO_OCLKDIV",
|
||||
"INT_INTERFACE_LOGIC_OUTS0",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX6",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX29",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX34",
|
||||
"INT_INTERFACE_ER1BEG1",
|
||||
"INT_INTERFACE_NE4BEG1",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX37",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX22",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX21",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B20",
|
||||
"INT_INTERFACE_SW4A0",
|
||||
"INT_INTERFACE_SW4A3",
|
||||
"INT_INTERFACE_LOGIC_OUTS18",
|
||||
"INT_INTERFACE_WW4B2",
|
||||
"INT_INTERFACE_FAN7",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX41",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX33",
|
||||
"INT_INTERFACE_WW2END0",
|
||||
"INT_INTERFACE_BRAM_IMUX43",
|
||||
"INT_INTERFACE_WW4A2",
|
||||
"INT_INTERFACE_EE4B0",
|
||||
"INT_INTERFACE_NE2A1",
|
||||
"INT_INTERFACE_EE4C0",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX16",
|
||||
"INT_INTERFACE_BLOCK_OUTS_B0",
|
||||
"INT_INTERFACE_SE4C0",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX39",
|
||||
"INT_INTERFACE_BRAM_IMUX45",
|
||||
"INT_INTERFACE_SW2A2",
|
||||
"INT_INTERFACE_BRAM_IMUX31",
|
||||
"INT_INTERFACE_LOGIC_OUTS5",
|
||||
"INT_INTERFACE_WW4C3",
|
||||
"INT_INTERFACE_NE2A0",
|
||||
"INT_INTERFACE_EE2BEG0",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX32",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX12",
|
||||
"INT_INTERFACE_BRAM_IMUX14",
|
||||
"INT_INTERFACE_WW4B0",
|
||||
"INT_INTERFACE_NW2A2",
|
||||
"INT_INTERFACE_WW2END2",
|
||||
"INT_INTERFACE_SE2A1",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX5",
|
||||
"INT_INTERFACE_BRAM_IMUX32",
|
||||
"INT_INTERFACE_EL1BEG0",
|
||||
"INT_INTERFACE_BRAM_IMUX7",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX36",
|
||||
"INT_INTERFACE_LOGIC_OUTS16",
|
||||
"INT_INTERFACE_BRAM_IMUX33",
|
||||
"INT_INTERFACE_LOGIC_OUTS4",
|
||||
"INT_INTERFACE_BRAM_IMUX42",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B12",
|
||||
"INT_INTERFACE_WW4C2",
|
||||
"INT_INTERFACE_WW4C1",
|
||||
"INT_INTERFACE_BRAM_IMUX21",
|
||||
"INT_INTERFACE_NE4BEG2",
|
||||
"INT_INTERFACE_BRAM_IMUX38",
|
||||
"INT_INTERFACE_EE4A3",
|
||||
"INT_INTERFACE_CTRL0",
|
||||
"INT_INTERFACE_BRAM_IMUX0",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX20",
|
||||
"INT_INTERFACE_SE4C1",
|
||||
"INT_INTERFACE_WL1END0",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX11",
|
||||
"INT_INTERFACE_WW4A1",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B3",
|
||||
"INT_INTERFACE_BYP3",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX37",
|
||||
"INT_INTERFACE_EE4BEG1",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B2",
|
||||
"INT_INTERFACE_EL1BEG3",
|
||||
"INT_INTERFACE_NE4BEG0",
|
||||
"INT_INTERFACE_LOGIC_OUTS4",
|
||||
"INT_INTERFACE_LOGIC_OUTS13",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B18",
|
||||
"INT_INTERFACE_BRAM_IMUX12",
|
||||
"INT_INTERFACE_BRAM_IMUX7",
|
||||
"INT_INTERFACE_WW2A0",
|
||||
"INT_INTERFACE_BRAM_IMUX18",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX35",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX17",
|
||||
"INT_INTERFACE_FAN6",
|
||||
"INT_INTERFACE_LH12",
|
||||
"INT_INTERFACE_WR1END1",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX38",
|
||||
"INT_INTERFACE_BRAM_IMUX2",
|
||||
"INT_INTERFACE_ER1BEG3",
|
||||
"INT_INTERFACE_SW4A1",
|
||||
"INT_INTERFACE_EE2A1",
|
||||
"INT_INTERFACE_LOGIC_OUTS9",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX44",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B19",
|
||||
"INT_INTERFACE_EE2A3",
|
||||
"INT_INTERFACE_FAN5",
|
||||
"INT_INTERFACE_WW4C3",
|
||||
"INT_INTERFACE_BRAM_IMUX30",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX25",
|
||||
"INT_INTERFACE_WW2A2",
|
||||
"INT_INTERFACE_SE4C3",
|
||||
"INT_INTERFACE_NW4A3",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX7",
|
||||
"INT_INTERFACE_LOGIC_OUTS17",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B11",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B22",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX10",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX22",
|
||||
"INT_INTERFACE_LOGIC_OUTS1",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX31",
|
||||
"INT_INTERFACE_LOGIC_OUTS2",
|
||||
"INT_INTERFACE_BRAM_IMUX10",
|
||||
"INT_INTERFACE_BRAM_IMUX23",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX12",
|
||||
"INT_INTERFACE_NW2A0",
|
||||
"INT_INTERFACE_BRAM_IMUX25",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX4",
|
||||
"INT_INTERFACE_BYP3",
|
||||
"INT_INTERFACE_WW2END0",
|
||||
"INT_INTERFACE_EE4B2",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX8",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX0",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX29",
|
||||
"INT_INTERFACE_NW2A3",
|
||||
"INT_INTERFACE_BRAM_IMUX28",
|
||||
"INT_INTERFACE_EL1BEG1",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX43",
|
||||
"INT_INTERFACE_BRAM_IMUX32",
|
||||
"INT_INTERFACE_LH11",
|
||||
"INT_INTERFACE_LOGIC_OUTS9",
|
||||
"INT_INTERFACE_BRAM_IMUX34",
|
||||
"INT_INTERFACE_EE4B0",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B14",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX33",
|
||||
"INT_INTERFACE_BRAM_IMUX20",
|
||||
"INT_INTERFACE_BRAM_IMUX0",
|
||||
"INT_INTERFACE_BRAM_IMUX9",
|
||||
"INT_INTERFACE_BRAM_IMUX1",
|
||||
"INT_INTERFACE_ER1BEG0",
|
||||
"INT_INTERFACE_WW4B2",
|
||||
"INT_INTERFACE_NE4BEG3",
|
||||
"INT_INTERFACE_BRAM_IMUX43",
|
||||
"INT_INTERFACE_LOGIC_OUTS19",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX42",
|
||||
"INT_INTERFACE_BYP6",
|
||||
"INT_INTERFACE_WW4B0",
|
||||
"INT_INTERFACE_BLOCK_OUTS_B3",
|
||||
"INT_INTERFACE_BRAM_IMUX21",
|
||||
"INT_INTERFACE_LH2",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX11",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B21",
|
||||
"INT_INTERFACE_BRAM_IMUX4",
|
||||
"INT_INTERFACE_NE2A3",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B4",
|
||||
"INT_INTERFACE_SE4C1",
|
||||
"INT_INTERFACE_LOGIC_OUTS12",
|
||||
"INT_INTERFACE_BRAM_IMUX24",
|
||||
"INT_INTERFACE_WL1END1",
|
||||
"INT_INTERFACE_NW4A0",
|
||||
"INT_INTERFACE_WW4END2",
|
||||
"INT_INTERFACE_BRAM_IMUX47",
|
||||
"INT_INTERFACE_NE4C3",
|
||||
"INT_INTERFACE_EE4C0",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX26",
|
||||
"INT_INTERFACE_BRAM_IMUX38",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B1",
|
||||
"INT_INTERFACE_SW4END3",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX5",
|
||||
"INT_INTERFACE_SW4END2",
|
||||
"INT_INTERFACE_BRAM_IMUX13",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B16",
|
||||
"INT_INTERFACE_FAN6",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX46",
|
||||
"INT_INTERFACE_BRAM_IMUX19",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX41",
|
||||
"INT_INTERFACE_EE2A0",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX28",
|
||||
"INT_INTERFACE_BRAM_IMUX27",
|
||||
"INT_INTERFACE_BRAM_IMUX29",
|
||||
"INT_INTERFACE_LH7",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX34",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B20",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B6",
|
||||
"INT_INTERFACE_WW4END3",
|
||||
"INT_INTERFACE_LOGIC_OUTS5",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B3",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX17",
|
||||
"INT_INTERFACE_SW4A2",
|
||||
"INT_INTERFACE_SW4A1",
|
||||
"INT_INTERFACE_BRAM_IMUX16",
|
||||
"INT_INTERFACE_LOGIC_OUTS8",
|
||||
"INT_INTERFACE_SE2A1",
|
||||
"INT_INTERFACE_LH6",
|
||||
"INT_INTERFACE_LH5",
|
||||
"INT_INTERFACE_BRAM_IMUX40",
|
||||
"L_INT_INTER_DQS_IOTOPHASER",
|
||||
"INT_INTERFACE_WW4A0",
|
||||
"INT_INTERFACE_SE4BEG2",
|
||||
"INT_INTERFACE_NW4A2",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX7",
|
||||
"INT_INTERFACE_BRAM_IMUX35",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B9",
|
||||
"INT_INTERFACE_BRAM_IMUX4"
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX19",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX13",
|
||||
"INT_INTERFACE_BRAM_IMUX45",
|
||||
"INT_INTERFACE_WR1END3",
|
||||
"INT_INTERFACE_BRAM_IMUX39",
|
||||
"INT_INTERFACE_EE4C1",
|
||||
"INT_INTERFACE_FAN7",
|
||||
"INT_INTERFACE_EE4BEG0",
|
||||
"INT_INTERFACE_LOGIC_OUTS15",
|
||||
"INT_INTERFACE_BRAM_IMUX15",
|
||||
"INT_INTERFACE_BRAM_IMUX46",
|
||||
"INT_INTERFACE_SW2A1",
|
||||
"INT_INTERFACE_LOGIC_OUTS22",
|
||||
"INT_INTERFACE_LH8",
|
||||
"INT_INTERFACE_LH9",
|
||||
"INT_INTERFACE_SE2A2",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B10",
|
||||
"INT_INTERFACE_SW4A3",
|
||||
"INT_INTERFACE_LOGIC_OUTS7",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX6",
|
||||
"INT_INTERFACE_SE2A3",
|
||||
"INT_INTERFACE_NW4END2",
|
||||
"INT_INTERFACE_EE4C3",
|
||||
"INT_INTERFACE_EE2A1",
|
||||
"INT_INTERFACE_SE4BEG1",
|
||||
"INT_INTERFACE_LOGIC_OUTS17",
|
||||
"INT_INTERFACE_NW4END1",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX2",
|
||||
"INT_INTERFACE_WL1END3",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B17",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B8",
|
||||
"INT_INTERFACE_PHASER_TO_IO_ICLK",
|
||||
"INT_INTERFACE_NE4C0",
|
||||
"INT_INTERFACE_WR1END2",
|
||||
"INT_INTERFACE_BRAM_IMUX33",
|
||||
"INT_INTERFACE_NW4A3",
|
||||
"INT_INTERFACE_WR1END0",
|
||||
"INT_INTERFACE_NE2A0",
|
||||
"INT_INTERFACE_EE4BEG3",
|
||||
"INT_INTERFACE_ER1BEG2",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX27",
|
||||
"INT_INTERFACE_BRAM_IMUX5",
|
||||
"INT_INTERFACE_WW2END1",
|
||||
"INT_INTERFACE_LOGIC_OUTS0",
|
||||
"INT_INTERFACE_BRAM_IMUX3",
|
||||
"INT_INTERFACE_EE4A1",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX39",
|
||||
"INT_INTERFACE_WW2A1",
|
||||
"INT_INTERFACE_LH3",
|
||||
"INT_INTERFACE_WL1END0",
|
||||
"INT_INTERFACE_WR1END1",
|
||||
"INT_INTERFACE_WW4B1",
|
||||
"INT_INTERFACE_BYP7",
|
||||
"INT_INTERFACE_PHASER_TO_IO_OCLKDIV",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX38",
|
||||
"INT_INTERFACE_WW4C0",
|
||||
"INT_INTERFACE_SW2A0",
|
||||
"INT_INTERFACE_SE4BEG3",
|
||||
"INT_INTERFACE_LH1",
|
||||
"INT_INTERFACE_WW4B3",
|
||||
"INT_INTERFACE_BRAM_IMUX41",
|
||||
"INT_INTERFACE_WW4A1",
|
||||
"INT_INTERFACE_BRAM_IMUX31",
|
||||
"INT_INTERFACE_ER1BEG1",
|
||||
"INT_INTERFACE_SW4A0",
|
||||
"INT_INTERFACE_NW4A1",
|
||||
"INT_INTERFACE_EL1BEG0",
|
||||
"INT_INTERFACE_LH4",
|
||||
"INT_INTERFACE_PHASER_TO_IO_OCLK",
|
||||
"INT_INTERFACE_BRAM_IMUX6",
|
||||
"INT_INTERFACE_WW4A3",
|
||||
"INT_INTERFACE_LOGIC_OUTS20",
|
||||
"INT_INTERFACE_NE2A2",
|
||||
"INT_INTERFACE_PHASER_TO_IO_ICLKDIV",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX45",
|
||||
"INT_INTERFACE_WW2END2",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX18",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX20",
|
||||
"INT_INTERFACE_WW4A2",
|
||||
"INT_INTERFACE_WL1END2",
|
||||
"INT_INTERFACE_BLOCK_OUTS_B1",
|
||||
"INT_INTERFACE_EE4A3",
|
||||
"INT_INTERFACE_BYP2",
|
||||
"INT_INTERFACE_NE4BEG1",
|
||||
"INT_INTERFACE_BYP0",
|
||||
"INT_INTERFACE_EE4BEG2",
|
||||
"INT_INTERFACE_LOGIC_OUTS6",
|
||||
"INT_INTERFACE_FAN0",
|
||||
"INT_INTERFACE_WW2A3",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B12",
|
||||
"INT_INTERFACE_NW4END3",
|
||||
"INT_INTERFACE_LH12",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX21",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX30",
|
||||
"INT_INTERFACE_SW4END1",
|
||||
"INT_INTERFACE_WW4C2",
|
||||
"INT_INTERFACE_NE4BEG2",
|
||||
"INT_INTERFACE_BRAM_IMUX36",
|
||||
"INT_INTERFACE_CTRL0",
|
||||
"INT_INTERFACE_ER1BEG3",
|
||||
"INT_INTERFACE_BRAM_IMUX22",
|
||||
"INT_INTERFACE_BYP5",
|
||||
"INT_INTERFACE_SW2A2",
|
||||
"INT_INTERFACE_CTRL1",
|
||||
"INT_INTERFACE_NE2A1",
|
||||
"INT_INTERFACE_EE2BEG3",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B23",
|
||||
"INT_INTERFACE_NW4END0",
|
||||
"INT_INTERFACE_NW2A2",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B11",
|
||||
"INT_INTERFACE_WW2END3",
|
||||
"INT_INTERFACE_BRAM_IMUX42",
|
||||
"INT_INTERFACE_LOGIC_OUTS16",
|
||||
"INT_INTERFACE_EE4C2",
|
||||
"INT_INTERFACE_EE2BEG1",
|
||||
"INT_INTERFACE_CLK1",
|
||||
"INT_INTERFACE_LOGIC_OUTS10",
|
||||
"INT_INTERFACE_FAN3",
|
||||
"INT_INTERFACE_WW4C1",
|
||||
"INT_INTERFACE_BYP1",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX15",
|
||||
"INT_INTERFACE_EL1BEG2",
|
||||
"INT_INTERFACE_LOGIC_OUTS3",
|
||||
"INT_INTERFACE_BYP4",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX9",
|
||||
"INT_INTERFACE_MONITOR_P",
|
||||
"INT_INTERFACE_NW2A1",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B5",
|
||||
"INT_INTERFACE_WW2A2",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B13",
|
||||
"INT_INTERFACE_SE2A0",
|
||||
"INT_INTERFACE_FAN1",
|
||||
"INT_INTERFACE_EE4B1",
|
||||
"INT_INTERFACE_LOGIC_OUTS11",
|
||||
"INT_INTERFACE_NE4C2",
|
||||
"INT_INTERFACE_SW2A3",
|
||||
"INT_INTERFACE_EE2A2",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX14",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX23",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX32",
|
||||
"INT_INTERFACE_SE4C3",
|
||||
"INT_INTERFACE_EE2BEG2",
|
||||
"INT_INTERFACE_BRAM_IMUX26",
|
||||
"INT_INTERFACE_BRAM_IMUX11",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX47",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B22",
|
||||
"INT_INTERFACE_EE2BEG0",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX40",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B15",
|
||||
"INT_INTERFACE_PHASER_TO_IO_OCLK1X_90",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX1",
|
||||
"INT_INTERFACE_SE4BEG0",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B7",
|
||||
"INT_INTERFACE_SE4C2",
|
||||
"INT_INTERFACE_BRAM_IMUX44",
|
||||
"INT_INTERFACE_LOGIC_OUTS14",
|
||||
"INT_INTERFACE_WW4END1",
|
||||
"INT_INTERFACE_BRAM_IMUX17",
|
||||
"INT_INTERFACE_FAN4",
|
||||
"INT_INTERFACE_BLOCK_OUTS_B2",
|
||||
"INT_INTERFACE_LOGIC_OUTS23",
|
||||
"INT_INTERFACE_BRAM_IMUX2",
|
||||
"INT_INTERFACE_MONITOR_N",
|
||||
"INT_INTERFACE_BRAM_IMUX14",
|
||||
"INT_INTERFACE_LOGIC_OUTS18",
|
||||
"INT_INTERFACE_BRAM_IMUX37",
|
||||
"INT_INTERFACE_SW4END0",
|
||||
"INT_INTERFACE_WW4END0",
|
||||
"INT_INTERFACE_EE4B3",
|
||||
"INT_INTERFACE_EE4A0",
|
||||
"INT_INTERFACE_NE4C1",
|
||||
"INT_INTERFACE_LOGIC_OUTS21",
|
||||
"INT_INTERFACE_CLK0",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX24",
|
||||
"INT_INTERFACE_FAN2",
|
||||
"INT_INTERFACE_EE4A2",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX10",
|
||||
"INT_INTERFACE_BRAM_IMUX8"
|
||||
],
|
||||
"tile_type": "BRAM_INT_INTERFACE_R",
|
||||
"sites": []
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -1,70 +1,70 @@
|
|||
{
|
||||
"pips": {},
|
||||
"wires": [
|
||||
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU2",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU14",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU2",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU12",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU9",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU11",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU4",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU6",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU9",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU14",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU13",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU8",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU2",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU12",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU3",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU9",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU1",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU0",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU8",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU10",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU7",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU2",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU8",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU6",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU3",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU9",
|
||||
"BRKH_BRAM_CASCADEB_L",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU6",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU8",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU13",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU0",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU10",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU0",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU1",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU12",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU2",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU14",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU8",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU6",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU1",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU7",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU5",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU0",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU8",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU7",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU4",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU5",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU1",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU10",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU0",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU4",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU12",
|
||||
"BRKH_BRAM_CASCADEA_L",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU13",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU14",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU9",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU12",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU9",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU1",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU6",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU0",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU8",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU3",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU1",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU4",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU14",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU11",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU7",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU3",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU10",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU5",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU10",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU5",
|
||||
"BRKH_BRAM_CASCADEB_R",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU14",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU5",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU7",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU4",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU9",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU6",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU11",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU11",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU4",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU3",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU12",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU7",
|
||||
"BRKH_BRAM_CASCADEA_R",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU10",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU2",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU8",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU4",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU9",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU10",
|
||||
"BRKH_BRAM_CASCADEB_R",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU12",
|
||||
"BRKH_BRAM_CASCADEB_L",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU2",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU11",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU14",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU7",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU12",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU13",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU5",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU13"
|
||||
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU10",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU4",
|
||||
"BRKH_BRAM_CASCADEA_L",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU13",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU11",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU5",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU13",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU6",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU0",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU2",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU3",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU13",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU14"
|
||||
],
|
||||
"tile_type": "BRKH_BRAM",
|
||||
"sites": []
|
||||
|
|
|
|||
|
|
@ -1,124 +1,124 @@
|
|||
{
|
||||
"pips": {},
|
||||
"wires": [
|
||||
"B_TERM_UTURN_INT_SE2BEG3",
|
||||
"B_TERM_UTURN_INT_SS6E2",
|
||||
"B_TERM_UTURN_INT_SR1BEG3",
|
||||
"B_TERM_UTURN_INT_SE6A1",
|
||||
"B_TERM_UTURN_INT_SW2BEG1",
|
||||
"B_TERM_UTURN_INT_LVB5",
|
||||
"B_TERM_UTURN_INT_SW6B2",
|
||||
"B_TERM_UTURN_INT_LVB0",
|
||||
"B_TERM_UTURN_INT_LV7",
|
||||
"B_TERM_UTURN_INT_SS2A0",
|
||||
"B_TERM_UTURN_INT_SW6B3",
|
||||
"B_TERM_UTURN_INT_SS6C3",
|
||||
"B_TERM_UTURN_INT_SS2BEG0",
|
||||
"B_TERM_UTURN_INT_SS6E0",
|
||||
"B_TERM_UTURN_INT_SW6END_N0_3",
|
||||
"B_TERM_UTURN_INT_LV_L7",
|
||||
"B_TERM_UTURN_INT_SS6B3",
|
||||
"B_TERM_UTURN_INT_LV2",
|
||||
"B_TERM_UTURN_INT_LV8",
|
||||
"B_TERM_UTURN_INT_SW2BEG3",
|
||||
"B_TERM_UTURN_INT_SS6BEG3",
|
||||
"B_TERM_UTURN_INT_LVB4",
|
||||
"B_TERM_UTURN_INT_LV_L18",
|
||||
"B_TERM_UTURN_INT_LVB_L1",
|
||||
"B_TERM_UTURN_INT_SL1BEG3",
|
||||
"B_TERM_UTURN_INT_SE6A2",
|
||||
"B_TERM_UTURN_INT_ER1BEG0",
|
||||
"B_TERM_UTURN_INT_SW6B0",
|
||||
"B_TERM_UTURN_INT_SE6C3",
|
||||
"B_TERM_UTURN_INT_SS6B2",
|
||||
"B_TERM_UTURN_INT_SE6D1",
|
||||
"B_TERM_UTURN_INT_SS6A1",
|
||||
"B_TERM_UTURN_INT_SE6C1",
|
||||
"B_TERM_UTURN_INT_SS2BEG2",
|
||||
"B_TERM_UTURN_INT_SW2BEG0",
|
||||
"B_TERM_UTURN_INT_SE6D3",
|
||||
"B_TERM_UTURN_INT_SE6D0",
|
||||
"B_TERM_UTURN_INT_SW6B2",
|
||||
"B_TERM_UTURN_INT_LVB_L3",
|
||||
"B_TERM_UTURN_INT_LV_L6",
|
||||
"B_TERM_UTURN_INT_SW6A1",
|
||||
"B_TERM_UTURN_INT_LV_L9",
|
||||
"B_TERM_UTURN_INT_SL1BEG0",
|
||||
"B_TERM_UTURN_INT_LVB5",
|
||||
"B_TERM_UTURN_INT_FAN_BOUNCE2",
|
||||
"B_TERM_UTURN_INT_SS6B1",
|
||||
"B_TERM_UTURN_INT_SW6C3",
|
||||
"B_TERM_UTURN_INT_SS6C1",
|
||||
"B_TERM_UTURN_INT_SS6E3",
|
||||
"B_TERM_UTURN_INT_SS2A1",
|
||||
"B_TERM_UTURN_INT_LV_L8",
|
||||
"B_TERM_UTURN_INT_SW6A2",
|
||||
"B_TERM_UTURN_INT_LVB2",
|
||||
"B_TERM_UTURN_INT_LV9",
|
||||
"B_TERM_UTURN_INT_SE6A0",
|
||||
"B_TERM_UTURN_INT_FAN_BOUNCE0",
|
||||
"B_TERM_UTURN_INT_SW6D3",
|
||||
"B_TERM_UTURN_INT_SS6A2",
|
||||
"B_TERM_UTURN_INT_ER1END_N3_3",
|
||||
"B_TERM_UTURN_INT_WR1END0",
|
||||
"B_TERM_UTURN_INT_SE2BEG3",
|
||||
"B_TERM_UTURN_INT_SS6C0",
|
||||
"B_TERM_UTURN_INT_SE2BEG2",
|
||||
"B_TERM_UTURN_INT_SE6A3",
|
||||
"B_TERM_UTURN_INT_SW6A0",
|
||||
"B_TERM_UTURN_INT_SW2BEG2",
|
||||
"B_TERM_UTURN_INT_SS6BEG1",
|
||||
"B_TERM_UTURN_INT_SS6A3",
|
||||
"B_TERM_UTURN_INT_LV3",
|
||||
"B_TERM_UTURN_INT_LVB1",
|
||||
"B_TERM_UTURN_INT_SE2BEG0",
|
||||
"B_TERM_UTURN_INT_SS6C2",
|
||||
"B_TERM_UTURN_INT_LV_L4",
|
||||
"B_TERM_UTURN_INT_SW6D0",
|
||||
"B_TERM_UTURN_INT_LV_L3",
|
||||
"B_TERM_UTURN_INT_SL1BEG1",
|
||||
"B_TERM_UTURN_INT_SW6B1",
|
||||
"B_TERM_UTURN_INT_LV18",
|
||||
"B_TERM_UTURN_INT_LVB_L0",
|
||||
"B_TERM_UTURN_INT_SS6A0",
|
||||
"B_TERM_UTURN_INT_SE2BEG2",
|
||||
"B_TERM_UTURN_INT_SS6A1",
|
||||
"B_TERM_UTURN_INT_SS6B2",
|
||||
"B_TERM_UTURN_INT_LV_L5",
|
||||
"B_TERM_UTURN_INT_LVB_L3",
|
||||
"B_TERM_UTURN_INT_LVB_L2",
|
||||
"B_TERM_UTURN_INT_ER1END_N3_3",
|
||||
"B_TERM_UTURN_INT_SS2BEG1",
|
||||
"B_TERM_UTURN_INT_SW6A0",
|
||||
"B_TERM_UTURN_INT_LVB2",
|
||||
"B_TERM_UTURN_INT_LV5",
|
||||
"B_TERM_UTURN_INT_SW6C0",
|
||||
"B_TERM_UTURN_INT_SW6D1",
|
||||
"B_TERM_UTURN_INT_SW6C2",
|
||||
"B_TERM_UTURN_INT_SL1BEG2",
|
||||
"B_TERM_UTURN_INT_SE6B3",
|
||||
"B_TERM_UTURN_INT_SR1BEG3",
|
||||
"B_TERM_UTURN_INT_SE6B1",
|
||||
"B_TERM_UTURN_INT_SW6C1",
|
||||
"B_TERM_UTURN_INT_SW2BEG1",
|
||||
"B_TERM_UTURN_INT_SS6BEG2",
|
||||
"B_TERM_UTURN_INT_LV4",
|
||||
"B_TERM_UTURN_INT_SE6C2",
|
||||
"B_TERM_UTURN_INT_SW2BEG0",
|
||||
"B_TERM_UTURN_INT_LVB4",
|
||||
"B_TERM_UTURN_INT_LV6",
|
||||
"B_TERM_UTURN_INT_SR1BEG1",
|
||||
"B_TERM_UTURN_INT_SE6A1",
|
||||
"B_TERM_UTURN_INT_SS6D0",
|
||||
"B_TERM_UTURN_INT_SW6A3",
|
||||
"B_TERM_UTURN_INT_SE6D2",
|
||||
"B_TERM_UTURN_INT_SS2A2",
|
||||
"B_TERM_UTURN_INT_LV_L2",
|
||||
"B_TERM_UTURN_INT_LV5",
|
||||
"B_TERM_UTURN_INT_FAN_BOUNCE6",
|
||||
"B_TERM_UTURN_INT_SS6D2",
|
||||
"B_TERM_UTURN_INT_SS6BEG3",
|
||||
"B_TERM_UTURN_INT_WR1BEG0",
|
||||
"B_TERM_UTURN_INT_SE6B2",
|
||||
"B_TERM_UTURN_INT_SS6E1",
|
||||
"B_TERM_UTURN_INT_SR1BEG2",
|
||||
"B_TERM_UTURN_INT_SS6D1",
|
||||
"B_TERM_UTURN_INT_SW6D2",
|
||||
"B_TERM_UTURN_INT_FAN_BOUNCE4",
|
||||
"B_TERM_UTURN_INT_SS2BEG1",
|
||||
"B_TERM_UTURN_INT_LVB3",
|
||||
"B_TERM_UTURN_INT_SE2BEG1",
|
||||
"B_TERM_UTURN_INT_FAN_BOUNCE0",
|
||||
"B_TERM_UTURN_INT_LV_L3",
|
||||
"B_TERM_UTURN_INT_SE6D2",
|
||||
"B_TERM_UTURN_INT_SS6B0",
|
||||
"B_TERM_UTURN_INT_FAN_BOUNCE6",
|
||||
"B_TERM_UTURN_INT_LV_L2",
|
||||
"B_TERM_UTURN_INT_SS6E0",
|
||||
"B_TERM_UTURN_INT_SE6C0",
|
||||
"B_TERM_UTURN_INT_ER1BEG0",
|
||||
"B_TERM_UTURN_INT_WR1BEG0",
|
||||
"B_TERM_UTURN_INT_SS6A2",
|
||||
"B_TERM_UTURN_INT_LV_L8",
|
||||
"B_TERM_UTURN_INT_SE6B3",
|
||||
"B_TERM_UTURN_INT_LV18",
|
||||
"B_TERM_UTURN_INT_SW6B1",
|
||||
"B_TERM_UTURN_INT_LV_L9",
|
||||
"B_TERM_UTURN_INT_LVB_L1",
|
||||
"B_TERM_UTURN_INT_SE2BEG0",
|
||||
"B_TERM_UTURN_INT_LVB_L5",
|
||||
"B_TERM_UTURN_INT_SS2BEG0",
|
||||
"B_TERM_UTURN_INT_SL1BEG1",
|
||||
"B_TERM_UTURN_INT_SE6C1",
|
||||
"B_TERM_UTURN_INT_SW6D1",
|
||||
"B_TERM_UTURN_INT_FAN_BOUNCE2",
|
||||
"B_TERM_UTURN_INT_SR1BEG2",
|
||||
"B_TERM_UTURN_INT_SW6A1",
|
||||
"B_TERM_UTURN_INT_SS6D1",
|
||||
"B_TERM_UTURN_INT_LVB0",
|
||||
"B_TERM_UTURN_INT_SS6D2",
|
||||
"B_TERM_UTURN_INT_SW6C0",
|
||||
"B_TERM_UTURN_INT_SS6D0",
|
||||
"B_TERM_UTURN_INT_SS6A3",
|
||||
"B_TERM_UTURN_INT_SL1BEG3",
|
||||
"B_TERM_UTURN_INT_LV2",
|
||||
"B_TERM_UTURN_INT_SE6D3",
|
||||
"B_TERM_UTURN_INT_SW6C1",
|
||||
"B_TERM_UTURN_INT_SS2A1",
|
||||
"B_TERM_UTURN_INT_LVB_L4",
|
||||
"B_TERM_UTURN_INT_SS2A2",
|
||||
"B_TERM_UTURN_INT_SW6B0",
|
||||
"B_TERM_UTURN_INT_LV6",
|
||||
"B_TERM_UTURN_INT_SE6B1",
|
||||
"B_TERM_UTURN_INT_SW6D2",
|
||||
"B_TERM_UTURN_INT_SE6D1",
|
||||
"B_TERM_UTURN_INT_FAN_BOUNCE4",
|
||||
"B_TERM_UTURN_INT_SW6D3",
|
||||
"B_TERM_UTURN_INT_SW6END_N0_3",
|
||||
"B_TERM_UTURN_INT_WR1END0",
|
||||
"B_TERM_UTURN_INT_SW6A2",
|
||||
"B_TERM_UTURN_INT_LV7",
|
||||
"B_TERM_UTURN_INT_SE6B2",
|
||||
"B_TERM_UTURN_INT_SE6A0",
|
||||
"B_TERM_UTURN_INT_SE6A2",
|
||||
"B_TERM_UTURN_INT_SS6B1",
|
||||
"B_TERM_UTURN_INT_SS2BEG3",
|
||||
"B_TERM_UTURN_INT_SS6C1",
|
||||
"B_TERM_UTURN_INT_SS6C0",
|
||||
"B_TERM_UTURN_INT_LVB1",
|
||||
"B_TERM_UTURN_INT_LV_L4",
|
||||
"B_TERM_UTURN_INT_LV3",
|
||||
"B_TERM_UTURN_INT_SS2A0",
|
||||
"B_TERM_UTURN_INT_LV4",
|
||||
"B_TERM_UTURN_INT_SE6C3",
|
||||
"B_TERM_UTURN_INT_SS2BEG2",
|
||||
"B_TERM_UTURN_INT_SS6BEG1",
|
||||
"B_TERM_UTURN_INT_LV_L18",
|
||||
"B_TERM_UTURN_INT_LV_L6",
|
||||
"B_TERM_UTURN_INT_SW6D0",
|
||||
"B_TERM_UTURN_INT_SS6B3",
|
||||
"B_TERM_UTURN_INT_SS6C3",
|
||||
"B_TERM_UTURN_INT_SW6C2",
|
||||
"B_TERM_UTURN_INT_SE6A3",
|
||||
"B_TERM_UTURN_INT_LV_L7",
|
||||
"B_TERM_UTURN_INT_SS2A3",
|
||||
"B_TERM_UTURN_INT_SS6C2",
|
||||
"B_TERM_UTURN_INT_LV8",
|
||||
"B_TERM_UTURN_INT_SS6BEG2",
|
||||
"B_TERM_UTURN_INT_SL1BEG0",
|
||||
"B_TERM_UTURN_INT_SS6E3",
|
||||
"B_TERM_UTURN_INT_SS6BEG0",
|
||||
"B_TERM_UTURN_INT_SS6E1",
|
||||
"B_TERM_UTURN_INT_SR1BEG1",
|
||||
"B_TERM_UTURN_INT_SW6B3",
|
||||
"B_TERM_UTURN_INT_SE6D0",
|
||||
"B_TERM_UTURN_INT_SE6B0",
|
||||
"B_TERM_UTURN_INT_LV9",
|
||||
"B_TERM_UTURN_INT_SS6E2",
|
||||
"B_TERM_UTURN_INT_LVB_L2",
|
||||
"B_TERM_UTURN_INT_SS6D3",
|
||||
"B_TERM_UTURN_INT_SL1BEG2"
|
||||
"B_TERM_UTURN_INT_SS2A3",
|
||||
"B_TERM_UTURN_INT_SS6BEG0",
|
||||
"B_TERM_UTURN_INT_SS2BEG3",
|
||||
"B_TERM_UTURN_INT_LVB_L4",
|
||||
"B_TERM_UTURN_INT_LV_L5",
|
||||
"B_TERM_UTURN_INT_SE6B0",
|
||||
"B_TERM_UTURN_INT_SS6B0",
|
||||
"B_TERM_UTURN_INT_SE6C0"
|
||||
],
|
||||
"tile_type": "BRKH_B_TERM_INT",
|
||||
"sites": []
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
{
|
||||
"pips": {},
|
||||
"wires": [
|
||||
"BRKH_CLB_COUT1_R",
|
||||
"BRKH_CLB_COUT0_L",
|
||||
"BRKH_CLB_COUT0_R",
|
||||
"BRKH_CLB_COUT1_L"
|
||||
"BRKH_CLB_COUT1_R",
|
||||
"BRKH_CLB_COUT1_L",
|
||||
"BRKH_CLB_COUT0_R"
|
||||
],
|
||||
"tile_type": "BRKH_CLB",
|
||||
"sites": []
|
||||
|
|
|
|||
|
|
@ -1,134 +1,134 @@
|
|||
{
|
||||
"pips": {},
|
||||
"wires": [
|
||||
"BRKH_CLK_CK_GCLK22",
|
||||
"BRKH_CLK_R_CK_GCLK6",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC24",
|
||||
"BRKH_CLK_CK_GCLK28",
|
||||
"BRKH_CLK_R_CK_GCLK2",
|
||||
"BRKH_CLK_CK_GCLK30",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC19",
|
||||
"BRKH_CLK_CK_GCLK15",
|
||||
"BRKH_CLK_R_CK_GCLK23",
|
||||
"BRKH_CLK_CK_BUFG_CASC22",
|
||||
"BRKH_CLK_CK_BUFG_CASC5",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC2",
|
||||
"BRKH_CLK_CK_GCLK11",
|
||||
"BRKH_CLK_R_CK_GCLK9",
|
||||
"BRKH_CLK_CK_BUFG_CASC20",
|
||||
"BRKH_CLK_R_CK_GCLK18",
|
||||
"BRKH_CLK_R_CK_GCLK21",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC3",
|
||||
"BRKH_CLK_CK_BUFG_CASC7",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC1",
|
||||
"BRKH_CLK_CK_BUFG_CASC16",
|
||||
"BRKH_CLK_CK_BUFG_CASC15",
|
||||
"BRKH_CLK_CK_GCLK14",
|
||||
"BRKH_CLK_CK_GCLK5",
|
||||
"BRKH_CLK_R_CK_GCLK16",
|
||||
"BRKH_CLK_R_CK_GCLK14",
|
||||
"BRKH_CLK_CK_BUFG_CASC13",
|
||||
"BRKH_CLK_R_CK_GCLK22",
|
||||
"BRKH_CLK_R_CK_GCLK0",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC21",
|
||||
"BRKH_CLK_R_CK_GCLK26",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC0",
|
||||
"BRKH_CLK_CK_GCLK8",
|
||||
"BRKH_CLK_CK_BUFG_CASC8",
|
||||
"BRKH_CLK_CK_GCLK24",
|
||||
"BRKH_CLK_CK_BUFG_CASC30",
|
||||
"BRKH_CLK_CK_BUFG_CASC0",
|
||||
"BRKH_CLK_CK_BUFG_CASC24",
|
||||
"BRKH_CLK_CK_BUFG_CASC25",
|
||||
"BRKH_CLK_CK_BUFG_CASC10",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC29",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC14",
|
||||
"BRKH_CLK_CK_GCLK29",
|
||||
"BRKH_CLK_CK_BUFG_CASC18",
|
||||
"BRKH_CLK_CK_GCLK4",
|
||||
"BRKH_CLK_CK_BUFG_CASC4",
|
||||
"BRKH_CLK_CK_GCLK23",
|
||||
"BRKH_CLK_CK_GCLK20",
|
||||
"BRKH_CLK_R_CK_GCLK24",
|
||||
"BRKH_CLK_CK_GCLK1",
|
||||
"BRKH_CLK_R_CK_GCLK25",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC25",
|
||||
"BRKH_CLK_CK_GCLK18",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC7",
|
||||
"BRKH_CLK_R_CK_GCLK3",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC17",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC22",
|
||||
"BRKH_CLK_CK_BUFG_CASC31",
|
||||
"BRKH_CLK_CK_GCLK7",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC4",
|
||||
"BRKH_CLK_CK_GCLK25",
|
||||
"BRKH_CLK_CK_GCLK10",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC20",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC23",
|
||||
"BRKH_CLK_CK_BUFG_CASC23",
|
||||
"BRKH_CLK_CK_GCLK31",
|
||||
"BRKH_CLK_R_CK_GCLK15",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC13",
|
||||
"BRKH_CLK_CK_BUFG_CASC14",
|
||||
"BRKH_CLK_CK_BUFG_CASC27",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC26",
|
||||
"BRKH_CLK_R_CK_GCLK5",
|
||||
"BRKH_CLK_CK_GCLK16",
|
||||
"BRKH_CLK_CK_BUFG_CASC21",
|
||||
"BRKH_CLK_R_CK_GCLK28",
|
||||
"BRKH_CLK_R_CK_GCLK19",
|
||||
"BRKH_CLK_CK_BUFG_CASC11",
|
||||
"BRKH_CLK_R_CK_GCLK31",
|
||||
"BRKH_CLK_R_CK_GCLK12",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC12",
|
||||
"BRKH_CLK_CK_BUFG_CASC2",
|
||||
"BRKH_CLK_R_CK_GCLK4",
|
||||
"BRKH_CLK_R_CK_GCLK30",
|
||||
"BRKH_CLK_CK_GCLK6",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC11",
|
||||
"BRKH_CLK_CK_BUFG_CASC19",
|
||||
"BRKH_CLK_R_CK_GCLK17",
|
||||
"BRKH_CLK_R_CK_GCLK10",
|
||||
"BRKH_CLK_CK_GCLK0",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC27",
|
||||
"BRKH_CLK_CK_BUFG_CASC17",
|
||||
"BRKH_CLK_CK_GCLK17",
|
||||
"BRKH_CLK_CK_GCLK27",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC9",
|
||||
"BRKH_CLK_CK_GCLK2",
|
||||
"BRKH_CLK_CK_BUFG_CASC3",
|
||||
"BRKH_CLK_R_CK_GCLK7",
|
||||
"BRKH_CLK_CK_GCLK19",
|
||||
"BRKH_CLK_CK_BUFG_CASC1",
|
||||
"BRKH_CLK_R_CK_GCLK1",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC5",
|
||||
"BRKH_CLK_CK_GCLK21",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC31",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC30",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC28",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC8",
|
||||
"BRKH_CLK_R_CK_GCLK29",
|
||||
"BRKH_CLK_CK_GCLK13",
|
||||
"BRKH_CLK_CK_GCLK12",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC16",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC18",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC15",
|
||||
"BRKH_CLK_R_CK_GCLK20",
|
||||
"BRKH_CLK_CK_BUFG_CASC9",
|
||||
"BRKH_CLK_CK_BUFG_CASC26",
|
||||
"BRKH_CLK_R_CK_GCLK8",
|
||||
"BRKH_CLK_CK_GCLK26",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC10",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC6",
|
||||
"BRKH_CLK_CK_BUFG_CASC29",
|
||||
"BRKH_CLK_R_CK_GCLK13",
|
||||
"BRKH_CLK_R_CK_GCLK27",
|
||||
"BRKH_CLK_CK_BUFG_CASC6",
|
||||
"BRKH_CLK_CK_BUFG_CASC12",
|
||||
"BRKH_CLK_CK_GCLK9",
|
||||
"BRKH_CLK_CK_GCLK3",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC28",
|
||||
"BRKH_CLK_CK_BUFG_CASC31",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC8",
|
||||
"BRKH_CLK_CK_GCLK14",
|
||||
"BRKH_CLK_CK_GCLK7",
|
||||
"BRKH_CLK_CK_GCLK28",
|
||||
"BRKH_CLK_CK_BUFG_CASC9",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC0",
|
||||
"BRKH_CLK_R_CK_GCLK6",
|
||||
"BRKH_CLK_R_CK_GCLK21",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC13",
|
||||
"BRKH_CLK_CK_BUFG_CASC13",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC21",
|
||||
"BRKH_CLK_R_CK_GCLK31",
|
||||
"BRKH_CLK_CK_BUFG_CASC2",
|
||||
"BRKH_CLK_CK_BUFG_CASC26",
|
||||
"BRKH_CLK_CK_GCLK24",
|
||||
"BRKH_CLK_CK_BUFG_CASC28",
|
||||
"BRKH_CLK_R_CK_GCLK30",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC22",
|
||||
"BRKH_CLK_R_CK_GCLK9",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC1",
|
||||
"BRKH_CLK_CK_GCLK11",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC11",
|
||||
"BRKH_CLK_R_CK_GCLK1",
|
||||
"BRKH_CLK_CK_GCLK4",
|
||||
"BRKH_CLK_CK_BUFG_CASC10",
|
||||
"BRKH_CLK_CK_GCLK18",
|
||||
"BRKH_CLK_CK_GCLK5",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC18",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC16",
|
||||
"BRKH_CLK_CK_BUFG_CASC1",
|
||||
"BRKH_CLK_R_CK_GCLK11",
|
||||
"BRKH_CLK_CK_BUFG_CASC28"
|
||||
"BRKH_CLK_CK_GCLK26",
|
||||
"BRKH_CLK_CK_GCLK17",
|
||||
"BRKH_CLK_CK_GCLK30",
|
||||
"BRKH_CLK_CK_GCLK12",
|
||||
"BRKH_CLK_CK_GCLK23",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC9",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC12",
|
||||
"BRKH_CLK_CK_BUFG_CASC22",
|
||||
"BRKH_CLK_R_CK_GCLK28",
|
||||
"BRKH_CLK_R_CK_GCLK24",
|
||||
"BRKH_CLK_R_CK_GCLK5",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC31",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC19",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC25",
|
||||
"BRKH_CLK_R_CK_GCLK3",
|
||||
"BRKH_CLK_CK_BUFG_CASC20",
|
||||
"BRKH_CLK_R_CK_GCLK27",
|
||||
"BRKH_CLK_R_CK_GCLK19",
|
||||
"BRKH_CLK_CK_GCLK8",
|
||||
"BRKH_CLK_R_CK_GCLK17",
|
||||
"BRKH_CLK_CK_GCLK27",
|
||||
"BRKH_CLK_R_CK_GCLK14",
|
||||
"BRKH_CLK_CK_BUFG_CASC11",
|
||||
"BRKH_CLK_CK_BUFG_CASC15",
|
||||
"BRKH_CLK_CK_GCLK25",
|
||||
"BRKH_CLK_CK_BUFG_CASC18",
|
||||
"BRKH_CLK_R_CK_GCLK4",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC15",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC26",
|
||||
"BRKH_CLK_CK_GCLK21",
|
||||
"BRKH_CLK_CK_BUFG_CASC19",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC7",
|
||||
"BRKH_CLK_CK_GCLK0",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC20",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC2",
|
||||
"BRKH_CLK_CK_BUFG_CASC14",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC30",
|
||||
"BRKH_CLK_CK_GCLK3",
|
||||
"BRKH_CLK_CK_BUFG_CASC29",
|
||||
"BRKH_CLK_R_CK_GCLK25",
|
||||
"BRKH_CLK_CK_GCLK15",
|
||||
"BRKH_CLK_CK_GCLK13",
|
||||
"BRKH_CLK_CK_BUFG_CASC30",
|
||||
"BRKH_CLK_R_CK_GCLK7",
|
||||
"BRKH_CLK_R_CK_GCLK8",
|
||||
"BRKH_CLK_CK_BUFG_CASC17",
|
||||
"BRKH_CLK_CK_BUFG_CASC4",
|
||||
"BRKH_CLK_CK_BUFG_CASC27",
|
||||
"BRKH_CLK_R_CK_GCLK22",
|
||||
"BRKH_CLK_CK_BUFG_CASC16",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC3",
|
||||
"BRKH_CLK_R_CK_GCLK20",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC4",
|
||||
"BRKH_CLK_CK_BUFG_CASC3",
|
||||
"BRKH_CLK_CK_GCLK1",
|
||||
"BRKH_CLK_R_CK_GCLK26",
|
||||
"BRKH_CLK_CK_BUFG_CASC7",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC14",
|
||||
"BRKH_CLK_CK_BUFG_CASC12",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC23",
|
||||
"BRKH_CLK_CK_GCLK16",
|
||||
"BRKH_CLK_CK_GCLK2",
|
||||
"BRKH_CLK_CK_BUFG_CASC21",
|
||||
"BRKH_CLK_CK_GCLK6",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC24",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC6",
|
||||
"BRKH_CLK_CK_GCLK29",
|
||||
"BRKH_CLK_R_CK_GCLK15",
|
||||
"BRKH_CLK_CK_BUFG_CASC0",
|
||||
"BRKH_CLK_CK_BUFG_CASC6",
|
||||
"BRKH_CLK_CK_GCLK31",
|
||||
"BRKH_CLK_CK_GCLK20",
|
||||
"BRKH_CLK_R_CK_GCLK18",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC10",
|
||||
"BRKH_CLK_R_CK_GCLK10",
|
||||
"BRKH_CLK_CK_BUFG_CASC5",
|
||||
"BRKH_CLK_R_CK_GCLK16",
|
||||
"BRKH_CLK_CK_GCLK10",
|
||||
"BRKH_CLK_R_CK_GCLK29",
|
||||
"BRKH_CLK_R_CK_GCLK0",
|
||||
"BRKH_CLK_CK_BUFG_CASC23",
|
||||
"BRKH_CLK_R_CK_GCLK12",
|
||||
"BRKH_CLK_R_CK_GCLK13",
|
||||
"BRKH_CLK_CK_GCLK22",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC27",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC5",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC29",
|
||||
"BRKH_CLK_CK_GCLK19",
|
||||
"BRKH_CLK_CK_BUFG_CASC8",
|
||||
"BRKH_CLK_R_CK_GCLK2",
|
||||
"BRKH_CLK_CK_BUFG_CASC25",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC17",
|
||||
"BRKH_CLK_CK_BUFG_CASC24",
|
||||
"BRKH_CLK_R_CK_GCLK23"
|
||||
],
|
||||
"tile_type": "BRKH_CLK",
|
||||
"sites": []
|
||||
|
|
|
|||
|
|
@ -1,15 +1,15 @@
|
|||
{
|
||||
"pips": {},
|
||||
"wires": [
|
||||
"BRKH_CMT_PHASEREF_BELOW1",
|
||||
"BRKH_CMT_FREQ_REF_NS2",
|
||||
"BRKH_CMT_PHASEREF_BELOW0",
|
||||
"BRKH_CMT_FREQ_REF_NS1",
|
||||
"BRKH_CMT_FREQ_REF_NS3",
|
||||
"BRKH_CMT_PHASEREF1",
|
||||
"BRKH_CMT_PHASEREF_BELOW1",
|
||||
"BRKH_CMT_FREQ_REF_NS0",
|
||||
"BRKH_CMT_PHYCTRL_SYNC_BB",
|
||||
"BRKH_CMT_PHASEREF1",
|
||||
"BRKH_CMT_PHASEREF0"
|
||||
"BRKH_CMT_FREQ_REF_NS3",
|
||||
"BRKH_CMT_PHASEREF0",
|
||||
"BRKH_CMT_FREQ_REF_NS2"
|
||||
],
|
||||
"tile_type": "BRKH_CMT",
|
||||
"sites": []
|
||||
|
|
|
|||
|
|
@ -1,104 +1,104 @@
|
|||
{
|
||||
"pips": {},
|
||||
"wires": [
|
||||
"BRKH_DSP_BCIN2",
|
||||
"BRKH_DSP_PCIN20",
|
||||
"BRKH_DSP_BCIN4",
|
||||
"BRKH_DSP_PCIN29",
|
||||
"BRKH_DSP_PCIN35",
|
||||
"BRKH_DSP_PCIN36",
|
||||
"BRKH_DSP_PCIN37",
|
||||
"BRKH_DSP_PCIN44",
|
||||
"BRKH_DSP_BCIN14",
|
||||
"BRKH_DSP_BCIN13",
|
||||
"BRKH_DSP_PCIN4",
|
||||
"BRKH_DSP_PCIN39",
|
||||
"BRKH_DSP_PCIN19",
|
||||
"BRKH_DSP_PCIN46",
|
||||
"BRKH_DSP_BCIN3",
|
||||
"BRKH_DSP_ACIN26",
|
||||
"BRKH_DSP_BCIN7",
|
||||
"BRKH_DSP_PCIN0",
|
||||
"BRKH_DSP_PCIN43",
|
||||
"BRKH_DSP_ACIN24",
|
||||
"BRKH_DSP_ACIN1",
|
||||
"BRKH_DSP_PCIN12",
|
||||
"BRKH_DSP_PCIN31",
|
||||
"BRKH_DSP_ACIN8",
|
||||
"BRKH_DSP_BCIN0",
|
||||
"BRKH_DSP_PCIN38",
|
||||
"BRKH_DSP_PCIN40",
|
||||
"BRKH_DSP_PCIN28",
|
||||
"BRKH_DSP_ACIN5",
|
||||
"BRKH_DSP_ACIN2",
|
||||
"BRKH_DSP_ACIN20",
|
||||
"BRKH_DSP_MULTSIGNIN",
|
||||
"BRKH_DSP_PCIN1",
|
||||
"BRKH_DSP_ACIN22",
|
||||
"BRKH_DSP_ACIN14",
|
||||
"BRKH_DSP_ACIN15",
|
||||
"BRKH_DSP_BCIN1",
|
||||
"BRKH_DSP_ACIN25",
|
||||
"BRKH_DSP_PCIN24",
|
||||
"BRKH_DSP_PCIN22",
|
||||
"BRKH_DSP_ACIN10",
|
||||
"BRKH_DSP_ACIN23",
|
||||
"BRKH_DSP_PCIN42",
|
||||
"BRKH_DSP_PCIN15",
|
||||
"BRKH_DSP_ACIN9",
|
||||
"BRKH_DSP_ACIN18",
|
||||
"BRKH_DSP_PCIN9",
|
||||
"BRKH_DSP_BCIN16",
|
||||
"BRKH_DSP_ACIN28",
|
||||
"BRKH_DSP_ACIN27",
|
||||
"BRKH_DSP_PCIN47",
|
||||
"BRKH_DSP_PCIN45",
|
||||
"BRKH_DSP_BCIN6",
|
||||
"BRKH_DSP_PCIN34",
|
||||
"BRKH_DSP_BCIN8",
|
||||
"BRKH_DSP_PCIN18",
|
||||
"BRKH_DSP_PCIN16",
|
||||
"BRKH_DSP_PCIN3",
|
||||
"BRKH_DSP_BCIN6",
|
||||
"BRKH_DSP_BCIN0",
|
||||
"BRKH_DSP_PCIN37",
|
||||
"BRKH_DSP_PCIN45",
|
||||
"BRKH_DSP_PCIN34",
|
||||
"BRKH_DSP_ACIN25",
|
||||
"BRKH_DSP_PCIN26",
|
||||
"BRKH_DSP_PCIN7",
|
||||
"BRKH_DSP_PCIN41",
|
||||
"BRKH_DSP_PCIN21",
|
||||
"BRKH_DSP_PCIN5",
|
||||
"BRKH_DSP_PCIN14",
|
||||
"BRKH_DSP_PCIN13",
|
||||
"BRKH_DSP_ACIN12",
|
||||
"BRKH_DSP_PCIN27",
|
||||
"BRKH_DSP_PCIN33",
|
||||
"BRKH_DSP_PCIN18",
|
||||
"BRKH_DSP_ACIN16",
|
||||
"BRKH_DSP_BCIN17",
|
||||
"BRKH_DSP_BCIN7",
|
||||
"BRKH_DSP_ACIN26",
|
||||
"BRKH_DSP_PCIN40",
|
||||
"BRKH_DSP_ACIN23",
|
||||
"BRKH_DSP_PCIN16",
|
||||
"BRKH_DSP_PCIN4",
|
||||
"BRKH_DSP_PCIN43",
|
||||
"BRKH_DSP_PCIN12",
|
||||
"BRKH_DSP_ACIN12",
|
||||
"BRKH_DSP_PCIN47",
|
||||
"BRKH_DSP_PCIN39",
|
||||
"BRKH_DSP_ACIN18",
|
||||
"BRKH_DSP_PCIN15",
|
||||
"BRKH_DSP_ACIN21",
|
||||
"BRKH_DSP_PCIN44",
|
||||
"BRKH_DSP_PCIN29",
|
||||
"BRKH_DSP_PCIN1",
|
||||
"BRKH_DSP_PCIN35",
|
||||
"BRKH_DSP_PCIN20",
|
||||
"BRKH_DSP_ACIN1",
|
||||
"BRKH_DSP_BCIN4",
|
||||
"BRKH_DSP_ACIN13",
|
||||
"BRKH_DSP_ACIN4",
|
||||
"BRKH_DSP_PCIN2",
|
||||
"BRKH_DSP_ACIN27",
|
||||
"BRKH_DSP_ACIN9",
|
||||
"BRKH_DSP_ACIN6",
|
||||
"BRKH_DSP_ACIN5",
|
||||
"BRKH_DSP_ACIN14",
|
||||
"BRKH_DSP_PCIN31",
|
||||
"BRKH_DSP_PCIN7",
|
||||
"BRKH_DSP_PCIN46",
|
||||
"BRKH_DSP_ACIN8",
|
||||
"BRKH_DSP_ACIN15",
|
||||
"BRKH_DSP_ACIN17",
|
||||
"BRKH_DSP_ACIN28",
|
||||
"BRKH_DSP_PCIN19",
|
||||
"BRKH_DSP_BCIN12",
|
||||
"BRKH_DSP_ACIN22",
|
||||
"BRKH_DSP_ACIN19",
|
||||
"BRKH_DSP_CARRYCASCIN",
|
||||
"BRKH_DSP_BCIN5",
|
||||
"BRKH_DSP_PCIN6",
|
||||
"BRKH_DSP_PCIN5",
|
||||
"BRKH_DSP_ACIN2",
|
||||
"BRKH_DSP_PCIN11",
|
||||
"BRKH_DSP_BCIN16",
|
||||
"BRKH_DSP_PCIN21",
|
||||
"BRKH_DSP_PCIN41",
|
||||
"BRKH_DSP_PCIN0",
|
||||
"BRKH_DSP_PCIN38",
|
||||
"BRKH_DSP_BCIN3",
|
||||
"BRKH_DSP_PCIN30",
|
||||
"BRKH_DSP_PCIN32",
|
||||
"BRKH_DSP_PCIN23",
|
||||
"BRKH_DSP_ACIN20",
|
||||
"BRKH_DSP_ACIN29",
|
||||
"BRKH_DSP_PCIN10",
|
||||
"BRKH_DSP_PCIN13",
|
||||
"BRKH_DSP_ACIN3",
|
||||
"BRKH_DSP_BCIN9",
|
||||
"BRKH_DSP_BCIN12",
|
||||
"BRKH_DSP_ACIN17",
|
||||
"BRKH_DSP_ACIN0",
|
||||
"BRKH_DSP_ACIN7",
|
||||
"BRKH_DSP_PCIN30",
|
||||
"BRKH_DSP_ACIN11",
|
||||
"BRKH_DSP_BCIN11",
|
||||
"BRKH_DSP_PCIN6",
|
||||
"BRKH_DSP_PCIN32",
|
||||
"BRKH_DSP_BCIN2",
|
||||
"BRKH_DSP_PCIN17",
|
||||
"BRKH_DSP_PCIN23",
|
||||
"BRKH_DSP_BCIN1",
|
||||
"BRKH_DSP_PCIN14",
|
||||
"BRKH_DSP_BCIN14",
|
||||
"BRKH_DSP_BCIN13",
|
||||
"BRKH_DSP_ACIN0",
|
||||
"BRKH_DSP_BCIN17",
|
||||
"BRKH_DSP_PCIN36",
|
||||
"BRKH_DSP_PCIN9",
|
||||
"BRKH_DSP_PCIN24",
|
||||
"BRKH_DSP_BCIN10",
|
||||
"BRKH_DSP_PCIN28",
|
||||
"BRKH_DSP_PCIN8",
|
||||
"BRKH_DSP_PCIN10",
|
||||
"BRKH_DSP_PCIN25",
|
||||
"BRKH_DSP_ACIN13",
|
||||
"BRKH_DSP_PCIN2",
|
||||
"BRKH_DSP_BCIN5",
|
||||
"BRKH_DSP_ACIN19",
|
||||
"BRKH_DSP_ACIN29",
|
||||
"BRKH_DSP_PCIN11",
|
||||
"BRKH_DSP_ACIN6",
|
||||
"BRKH_DSP_PCIN33",
|
||||
"BRKH_DSP_ACIN7",
|
||||
"BRKH_DSP_PCIN42",
|
||||
"BRKH_DSP_BCIN11",
|
||||
"BRKH_DSP_MULTSIGNIN",
|
||||
"BRKH_DSP_BCIN15",
|
||||
"BRKH_DSP_CARRYCASCIN",
|
||||
"BRKH_DSP_PCIN27",
|
||||
"BRKH_DSP_BCIN10"
|
||||
"BRKH_DSP_BCIN8",
|
||||
"BRKH_DSP_PCIN22",
|
||||
"BRKH_DSP_PCIN25",
|
||||
"BRKH_DSP_ACIN11",
|
||||
"BRKH_DSP_ACIN24",
|
||||
"BRKH_DSP_ACIN10"
|
||||
],
|
||||
"tile_type": "BRKH_DSP_L",
|
||||
"sites": []
|
||||
|
|
|
|||
|
|
@ -1,104 +1,104 @@
|
|||
{
|
||||
"pips": {},
|
||||
"wires": [
|
||||
"BRKH_DSP_BCIN2",
|
||||
"BRKH_DSP_PCIN20",
|
||||
"BRKH_DSP_BCIN4",
|
||||
"BRKH_DSP_PCIN29",
|
||||
"BRKH_DSP_PCIN35",
|
||||
"BRKH_DSP_PCIN36",
|
||||
"BRKH_DSP_PCIN37",
|
||||
"BRKH_DSP_PCIN44",
|
||||
"BRKH_DSP_BCIN14",
|
||||
"BRKH_DSP_BCIN13",
|
||||
"BRKH_DSP_PCIN4",
|
||||
"BRKH_DSP_PCIN39",
|
||||
"BRKH_DSP_PCIN19",
|
||||
"BRKH_DSP_PCIN46",
|
||||
"BRKH_DSP_BCIN3",
|
||||
"BRKH_DSP_ACIN26",
|
||||
"BRKH_DSP_BCIN7",
|
||||
"BRKH_DSP_PCIN0",
|
||||
"BRKH_DSP_PCIN43",
|
||||
"BRKH_DSP_ACIN24",
|
||||
"BRKH_DSP_ACIN1",
|
||||
"BRKH_DSP_PCIN12",
|
||||
"BRKH_DSP_PCIN31",
|
||||
"BRKH_DSP_ACIN8",
|
||||
"BRKH_DSP_BCIN0",
|
||||
"BRKH_DSP_PCIN38",
|
||||
"BRKH_DSP_PCIN40",
|
||||
"BRKH_DSP_PCIN28",
|
||||
"BRKH_DSP_ACIN5",
|
||||
"BRKH_DSP_ACIN2",
|
||||
"BRKH_DSP_ACIN20",
|
||||
"BRKH_DSP_MULTSIGNIN",
|
||||
"BRKH_DSP_PCIN1",
|
||||
"BRKH_DSP_ACIN22",
|
||||
"BRKH_DSP_ACIN14",
|
||||
"BRKH_DSP_ACIN15",
|
||||
"BRKH_DSP_BCIN1",
|
||||
"BRKH_DSP_ACIN25",
|
||||
"BRKH_DSP_PCIN24",
|
||||
"BRKH_DSP_PCIN22",
|
||||
"BRKH_DSP_ACIN10",
|
||||
"BRKH_DSP_ACIN23",
|
||||
"BRKH_DSP_PCIN42",
|
||||
"BRKH_DSP_PCIN15",
|
||||
"BRKH_DSP_ACIN9",
|
||||
"BRKH_DSP_ACIN18",
|
||||
"BRKH_DSP_PCIN9",
|
||||
"BRKH_DSP_BCIN16",
|
||||
"BRKH_DSP_ACIN28",
|
||||
"BRKH_DSP_ACIN27",
|
||||
"BRKH_DSP_PCIN47",
|
||||
"BRKH_DSP_PCIN45",
|
||||
"BRKH_DSP_BCIN6",
|
||||
"BRKH_DSP_PCIN34",
|
||||
"BRKH_DSP_BCIN8",
|
||||
"BRKH_DSP_PCIN18",
|
||||
"BRKH_DSP_PCIN16",
|
||||
"BRKH_DSP_PCIN3",
|
||||
"BRKH_DSP_BCIN6",
|
||||
"BRKH_DSP_BCIN0",
|
||||
"BRKH_DSP_PCIN37",
|
||||
"BRKH_DSP_PCIN45",
|
||||
"BRKH_DSP_PCIN34",
|
||||
"BRKH_DSP_ACIN25",
|
||||
"BRKH_DSP_PCIN26",
|
||||
"BRKH_DSP_PCIN7",
|
||||
"BRKH_DSP_PCIN41",
|
||||
"BRKH_DSP_PCIN21",
|
||||
"BRKH_DSP_PCIN5",
|
||||
"BRKH_DSP_PCIN14",
|
||||
"BRKH_DSP_PCIN13",
|
||||
"BRKH_DSP_ACIN12",
|
||||
"BRKH_DSP_PCIN27",
|
||||
"BRKH_DSP_PCIN33",
|
||||
"BRKH_DSP_PCIN18",
|
||||
"BRKH_DSP_ACIN16",
|
||||
"BRKH_DSP_BCIN17",
|
||||
"BRKH_DSP_BCIN7",
|
||||
"BRKH_DSP_ACIN26",
|
||||
"BRKH_DSP_PCIN40",
|
||||
"BRKH_DSP_ACIN23",
|
||||
"BRKH_DSP_PCIN16",
|
||||
"BRKH_DSP_PCIN4",
|
||||
"BRKH_DSP_PCIN43",
|
||||
"BRKH_DSP_PCIN12",
|
||||
"BRKH_DSP_ACIN12",
|
||||
"BRKH_DSP_PCIN47",
|
||||
"BRKH_DSP_PCIN39",
|
||||
"BRKH_DSP_ACIN18",
|
||||
"BRKH_DSP_PCIN15",
|
||||
"BRKH_DSP_ACIN21",
|
||||
"BRKH_DSP_PCIN44",
|
||||
"BRKH_DSP_PCIN29",
|
||||
"BRKH_DSP_PCIN1",
|
||||
"BRKH_DSP_PCIN35",
|
||||
"BRKH_DSP_PCIN20",
|
||||
"BRKH_DSP_ACIN1",
|
||||
"BRKH_DSP_BCIN4",
|
||||
"BRKH_DSP_ACIN13",
|
||||
"BRKH_DSP_ACIN4",
|
||||
"BRKH_DSP_PCIN2",
|
||||
"BRKH_DSP_ACIN27",
|
||||
"BRKH_DSP_ACIN9",
|
||||
"BRKH_DSP_ACIN6",
|
||||
"BRKH_DSP_ACIN5",
|
||||
"BRKH_DSP_ACIN14",
|
||||
"BRKH_DSP_PCIN31",
|
||||
"BRKH_DSP_PCIN7",
|
||||
"BRKH_DSP_PCIN46",
|
||||
"BRKH_DSP_ACIN8",
|
||||
"BRKH_DSP_ACIN15",
|
||||
"BRKH_DSP_ACIN17",
|
||||
"BRKH_DSP_ACIN28",
|
||||
"BRKH_DSP_PCIN19",
|
||||
"BRKH_DSP_BCIN12",
|
||||
"BRKH_DSP_ACIN22",
|
||||
"BRKH_DSP_ACIN19",
|
||||
"BRKH_DSP_CARRYCASCIN",
|
||||
"BRKH_DSP_BCIN5",
|
||||
"BRKH_DSP_PCIN6",
|
||||
"BRKH_DSP_PCIN5",
|
||||
"BRKH_DSP_ACIN2",
|
||||
"BRKH_DSP_PCIN11",
|
||||
"BRKH_DSP_BCIN16",
|
||||
"BRKH_DSP_PCIN21",
|
||||
"BRKH_DSP_PCIN41",
|
||||
"BRKH_DSP_PCIN0",
|
||||
"BRKH_DSP_PCIN38",
|
||||
"BRKH_DSP_BCIN3",
|
||||
"BRKH_DSP_PCIN30",
|
||||
"BRKH_DSP_PCIN32",
|
||||
"BRKH_DSP_PCIN23",
|
||||
"BRKH_DSP_ACIN20",
|
||||
"BRKH_DSP_ACIN29",
|
||||
"BRKH_DSP_PCIN10",
|
||||
"BRKH_DSP_PCIN13",
|
||||
"BRKH_DSP_ACIN3",
|
||||
"BRKH_DSP_BCIN9",
|
||||
"BRKH_DSP_BCIN12",
|
||||
"BRKH_DSP_ACIN17",
|
||||
"BRKH_DSP_ACIN0",
|
||||
"BRKH_DSP_ACIN7",
|
||||
"BRKH_DSP_PCIN30",
|
||||
"BRKH_DSP_ACIN11",
|
||||
"BRKH_DSP_BCIN11",
|
||||
"BRKH_DSP_PCIN6",
|
||||
"BRKH_DSP_PCIN32",
|
||||
"BRKH_DSP_BCIN2",
|
||||
"BRKH_DSP_PCIN17",
|
||||
"BRKH_DSP_PCIN23",
|
||||
"BRKH_DSP_BCIN1",
|
||||
"BRKH_DSP_PCIN14",
|
||||
"BRKH_DSP_BCIN14",
|
||||
"BRKH_DSP_BCIN13",
|
||||
"BRKH_DSP_ACIN0",
|
||||
"BRKH_DSP_BCIN17",
|
||||
"BRKH_DSP_PCIN36",
|
||||
"BRKH_DSP_PCIN9",
|
||||
"BRKH_DSP_PCIN24",
|
||||
"BRKH_DSP_BCIN10",
|
||||
"BRKH_DSP_PCIN28",
|
||||
"BRKH_DSP_PCIN8",
|
||||
"BRKH_DSP_PCIN10",
|
||||
"BRKH_DSP_PCIN25",
|
||||
"BRKH_DSP_ACIN13",
|
||||
"BRKH_DSP_PCIN2",
|
||||
"BRKH_DSP_BCIN5",
|
||||
"BRKH_DSP_ACIN19",
|
||||
"BRKH_DSP_ACIN29",
|
||||
"BRKH_DSP_PCIN11",
|
||||
"BRKH_DSP_ACIN6",
|
||||
"BRKH_DSP_PCIN33",
|
||||
"BRKH_DSP_ACIN7",
|
||||
"BRKH_DSP_PCIN42",
|
||||
"BRKH_DSP_BCIN11",
|
||||
"BRKH_DSP_MULTSIGNIN",
|
||||
"BRKH_DSP_BCIN15",
|
||||
"BRKH_DSP_CARRYCASCIN",
|
||||
"BRKH_DSP_PCIN27",
|
||||
"BRKH_DSP_BCIN10"
|
||||
"BRKH_DSP_BCIN8",
|
||||
"BRKH_DSP_PCIN22",
|
||||
"BRKH_DSP_PCIN25",
|
||||
"BRKH_DSP_ACIN11",
|
||||
"BRKH_DSP_ACIN24",
|
||||
"BRKH_DSP_ACIN10"
|
||||
],
|
||||
"tile_type": "BRKH_DSP_R",
|
||||
"sites": []
|
||||
|
|
|
|||
|
|
@ -1,103 +1,103 @@
|
|||
{
|
||||
"pips": {
|
||||
"BRKH_GTX.BRKH_GTX_REFCLK1_UPPER->BRKH_GTX_SOUTHREFCLK0_LOWER": {
|
||||
"is_pseudo": "0",
|
||||
"is_directional": "1",
|
||||
"can_invert": "0",
|
||||
"src_wire": "BRKH_GTX_REFCLK1_UPPER",
|
||||
"dst_wire": "BRKH_GTX_SOUTHREFCLK0_LOWER",
|
||||
"is_pseudo": "0"
|
||||
},
|
||||
"BRKH_GTX.BRKH_GTX_REFCLK1_LOWER->BRKH_GTX_NORTHREFCLK1_UPPER": {
|
||||
"is_directional": "1",
|
||||
"can_invert": "0",
|
||||
"src_wire": "BRKH_GTX_REFCLK1_LOWER",
|
||||
"dst_wire": "BRKH_GTX_NORTHREFCLK1_UPPER",
|
||||
"is_pseudo": "0"
|
||||
},
|
||||
"BRKH_GTX.BRKH_GTX_SOUTHREFCLK1_UPPER->BRKH_GTX_SOUTHREFCLK1_LOWER": {
|
||||
"is_directional": "1",
|
||||
"can_invert": "0",
|
||||
"src_wire": "BRKH_GTX_SOUTHREFCLK1_UPPER",
|
||||
"dst_wire": "BRKH_GTX_SOUTHREFCLK1_LOWER",
|
||||
"is_pseudo": "0"
|
||||
"src_wire": "BRKH_GTX_REFCLK1_UPPER",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRKH_GTX.BRKH_GTX_REFCLK0_LOWER->BRKH_GTX_NORTHREFCLK0_UPPER": {
|
||||
"is_pseudo": "0",
|
||||
"is_directional": "1",
|
||||
"can_invert": "0",
|
||||
"src_wire": "BRKH_GTX_REFCLK0_LOWER",
|
||||
"dst_wire": "BRKH_GTX_NORTHREFCLK0_UPPER",
|
||||
"is_pseudo": "0"
|
||||
},
|
||||
"BRKH_GTX.BRKH_GTX_REFCLK1_UPPER->BRKH_GTX_SOUTHREFCLK1_LOWER": {
|
||||
"is_directional": "1",
|
||||
"can_invert": "0",
|
||||
"src_wire": "BRKH_GTX_REFCLK1_UPPER",
|
||||
"dst_wire": "BRKH_GTX_SOUTHREFCLK1_LOWER",
|
||||
"is_pseudo": "0"
|
||||
},
|
||||
"BRKH_GTX.BRKH_GTX_REFCLK0_UPPER->BRKH_GTX_SOUTHREFCLK1_LOWER": {
|
||||
"is_directional": "1",
|
||||
"can_invert": "0",
|
||||
"src_wire": "BRKH_GTX_REFCLK0_UPPER",
|
||||
"dst_wire": "BRKH_GTX_SOUTHREFCLK1_LOWER",
|
||||
"is_pseudo": "0"
|
||||
},
|
||||
"BRKH_GTX.BRKH_GTX_REFCLK0_LOWER->BRKH_GTX_NORTHREFCLK1_UPPER": {
|
||||
"is_directional": "1",
|
||||
"can_invert": "0",
|
||||
"src_wire": "BRKH_GTX_REFCLK0_LOWER",
|
||||
"dst_wire": "BRKH_GTX_NORTHREFCLK1_UPPER",
|
||||
"is_pseudo": "0"
|
||||
},
|
||||
"BRKH_GTX.BRKH_GTX_SOUTHREFCLK0_UPPER->BRKH_GTX_SOUTHREFCLK0_LOWER": {
|
||||
"is_directional": "1",
|
||||
"can_invert": "0",
|
||||
"src_wire": "BRKH_GTX_SOUTHREFCLK0_UPPER",
|
||||
"dst_wire": "BRKH_GTX_SOUTHREFCLK0_LOWER",
|
||||
"is_pseudo": "0"
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRKH_GTX.BRKH_GTX_REFCLK0_UPPER->BRKH_GTX_SOUTHREFCLK0_LOWER": {
|
||||
"is_pseudo": "0",
|
||||
"is_directional": "1",
|
||||
"can_invert": "0",
|
||||
"src_wire": "BRKH_GTX_REFCLK0_UPPER",
|
||||
"dst_wire": "BRKH_GTX_SOUTHREFCLK0_LOWER",
|
||||
"is_pseudo": "0"
|
||||
"src_wire": "BRKH_GTX_REFCLK0_UPPER",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRKH_GTX.BRKH_GTX_NORTHREFCLK1_LOWER->BRKH_GTX_NORTHREFCLK1_UPPER": {
|
||||
"is_pseudo": "0",
|
||||
"is_directional": "1",
|
||||
"can_invert": "0",
|
||||
"src_wire": "BRKH_GTX_NORTHREFCLK1_LOWER",
|
||||
"dst_wire": "BRKH_GTX_NORTHREFCLK1_UPPER",
|
||||
"is_pseudo": "0"
|
||||
},
|
||||
"BRKH_GTX.BRKH_GTX_REFCLK1_LOWER->BRKH_GTX_NORTHREFCLK0_UPPER": {
|
||||
"is_directional": "1",
|
||||
"can_invert": "0",
|
||||
"src_wire": "BRKH_GTX_REFCLK1_LOWER",
|
||||
"dst_wire": "BRKH_GTX_NORTHREFCLK0_UPPER",
|
||||
"is_pseudo": "0"
|
||||
"src_wire": "BRKH_GTX_NORTHREFCLK1_LOWER",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRKH_GTX.BRKH_GTX_NORTHREFCLK0_LOWER->BRKH_GTX_NORTHREFCLK0_UPPER": {
|
||||
"is_pseudo": "0",
|
||||
"is_directional": "1",
|
||||
"can_invert": "0",
|
||||
"src_wire": "BRKH_GTX_NORTHREFCLK0_LOWER",
|
||||
"dst_wire": "BRKH_GTX_NORTHREFCLK0_UPPER",
|
||||
"is_pseudo": "0"
|
||||
"src_wire": "BRKH_GTX_NORTHREFCLK0_LOWER",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRKH_GTX.BRKH_GTX_SOUTHREFCLK0_UPPER->BRKH_GTX_SOUTHREFCLK0_LOWER": {
|
||||
"is_pseudo": "0",
|
||||
"is_directional": "1",
|
||||
"dst_wire": "BRKH_GTX_SOUTHREFCLK0_LOWER",
|
||||
"src_wire": "BRKH_GTX_SOUTHREFCLK0_UPPER",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRKH_GTX.BRKH_GTX_REFCLK1_LOWER->BRKH_GTX_NORTHREFCLK1_UPPER": {
|
||||
"is_pseudo": "0",
|
||||
"is_directional": "1",
|
||||
"dst_wire": "BRKH_GTX_NORTHREFCLK1_UPPER",
|
||||
"src_wire": "BRKH_GTX_REFCLK1_LOWER",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRKH_GTX.BRKH_GTX_SOUTHREFCLK1_UPPER->BRKH_GTX_SOUTHREFCLK1_LOWER": {
|
||||
"is_pseudo": "0",
|
||||
"is_directional": "1",
|
||||
"dst_wire": "BRKH_GTX_SOUTHREFCLK1_LOWER",
|
||||
"src_wire": "BRKH_GTX_SOUTHREFCLK1_UPPER",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRKH_GTX.BRKH_GTX_REFCLK0_UPPER->BRKH_GTX_SOUTHREFCLK1_LOWER": {
|
||||
"is_pseudo": "0",
|
||||
"is_directional": "1",
|
||||
"dst_wire": "BRKH_GTX_SOUTHREFCLK1_LOWER",
|
||||
"src_wire": "BRKH_GTX_REFCLK0_UPPER",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRKH_GTX.BRKH_GTX_REFCLK1_UPPER->BRKH_GTX_SOUTHREFCLK1_LOWER": {
|
||||
"is_pseudo": "0",
|
||||
"is_directional": "1",
|
||||
"dst_wire": "BRKH_GTX_SOUTHREFCLK1_LOWER",
|
||||
"src_wire": "BRKH_GTX_REFCLK1_UPPER",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRKH_GTX.BRKH_GTX_REFCLK0_LOWER->BRKH_GTX_NORTHREFCLK1_UPPER": {
|
||||
"is_pseudo": "0",
|
||||
"is_directional": "1",
|
||||
"dst_wire": "BRKH_GTX_NORTHREFCLK1_UPPER",
|
||||
"src_wire": "BRKH_GTX_REFCLK0_LOWER",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRKH_GTX.BRKH_GTX_REFCLK1_LOWER->BRKH_GTX_NORTHREFCLK0_UPPER": {
|
||||
"is_pseudo": "0",
|
||||
"is_directional": "1",
|
||||
"dst_wire": "BRKH_GTX_NORTHREFCLK0_UPPER",
|
||||
"src_wire": "BRKH_GTX_REFCLK1_LOWER",
|
||||
"can_invert": "0"
|
||||
}
|
||||
},
|
||||
"wires": [
|
||||
"BRKH_GTX_REFCLK0_UPPER",
|
||||
"BRKH_GTX_NORTHREFCLK1_UPPER",
|
||||
"BRKH_GTX_SOUTHREFCLK0_UPPER",
|
||||
"BRKH_GTX_SOUTHREFCLK0_LOWER",
|
||||
"BRKH_GTX_REFCLK1_LOWER",
|
||||
"BRKH_GTX_NORTHREFCLK0_UPPER",
|
||||
"BRKH_GTX_NORTHREFCLK0_LOWER",
|
||||
"BRKH_GTX_SOUTHREFCLK1_LOWER",
|
||||
"BRKH_GTX_SOUTHREFCLK1_UPPER",
|
||||
"BRKH_GTX_NORTHREFCLK1_LOWER",
|
||||
"BRKH_GTX_SOUTHREFCLK0_UPPER",
|
||||
"BRKH_GTX_REFCLK0_UPPER",
|
||||
"BRKH_GTX_SOUTHREFCLK0_LOWER",
|
||||
"BRKH_GTX_NORTHREFCLK0_UPPER",
|
||||
"BRKH_GTX_SOUTHREFCLK1_LOWER",
|
||||
"BRKH_GTX_REFCLK1_LOWER",
|
||||
"BRKH_GTX_REFCLK1_UPPER",
|
||||
"BRKH_GTX_REFCLK0_LOWER"
|
||||
"BRKH_GTX_REFCLK0_LOWER",
|
||||
"BRKH_GTX_NORTHREFCLK1_UPPER",
|
||||
"BRKH_GTX_NORTHREFCLK1_LOWER",
|
||||
"BRKH_GTX_NORTHREFCLK0_LOWER"
|
||||
],
|
||||
"tile_type": "BRKH_GTX",
|
||||
"sites": []
|
||||
|
|
|
|||
|
|
@ -1,366 +1,366 @@
|
|||
{
|
||||
"pips": {
|
||||
"BRKH_INT.BRKH_INT_NL1BEG1->>BRKH_INT_NL1BEG1_SLOW": {
|
||||
"is_directional": "1",
|
||||
"can_invert": "0",
|
||||
"src_wire": "BRKH_INT_NL1BEG1",
|
||||
"dst_wire": "BRKH_INT_NL1BEG1_SLOW",
|
||||
"is_pseudo": "0"
|
||||
},
|
||||
"BRKH_INT.BRKH_INT_SL1END3_SLOW->>BRKH_INT_SL1END3": {
|
||||
"is_directional": "1",
|
||||
"can_invert": "0",
|
||||
"src_wire": "BRKH_INT_SL1END3_SLOW",
|
||||
"dst_wire": "BRKH_INT_SL1END3",
|
||||
"is_pseudo": "0"
|
||||
},
|
||||
"BRKH_INT.BRKH_INT_SR1END1_SLOW->>BRKH_INT_SR1END1": {
|
||||
"is_directional": "1",
|
||||
"can_invert": "0",
|
||||
"src_wire": "BRKH_INT_SR1END1_SLOW",
|
||||
"dst_wire": "BRKH_INT_SR1END1",
|
||||
"is_pseudo": "0"
|
||||
},
|
||||
"BRKH_INT.BRKH_INT_NR1BEG2->>BRKH_INT_NR1BEG2_SLOW": {
|
||||
"is_directional": "1",
|
||||
"can_invert": "0",
|
||||
"src_wire": "BRKH_INT_NR1BEG2",
|
||||
"dst_wire": "BRKH_INT_NR1BEG2_SLOW",
|
||||
"is_pseudo": "0"
|
||||
},
|
||||
"BRKH_INT.BRKH_INT_SL1END0_SLOW->>BRKH_INT_SL1END0": {
|
||||
"is_directional": "1",
|
||||
"can_invert": "0",
|
||||
"src_wire": "BRKH_INT_SL1END0_SLOW",
|
||||
"dst_wire": "BRKH_INT_SL1END0",
|
||||
"is_pseudo": "0"
|
||||
},
|
||||
"BRKH_INT.BRKH_INT_SL1END1_SLOW->>BRKH_INT_SL1END1": {
|
||||
"is_directional": "1",
|
||||
"can_invert": "0",
|
||||
"src_wire": "BRKH_INT_SL1END1_SLOW",
|
||||
"dst_wire": "BRKH_INT_SL1END1",
|
||||
"is_pseudo": "0"
|
||||
},
|
||||
"BRKH_INT.BRKH_INT_NR1BEG1->>BRKH_INT_NR1BEG1_SLOW": {
|
||||
"is_directional": "1",
|
||||
"can_invert": "0",
|
||||
"src_wire": "BRKH_INT_NR1BEG1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "BRKH_INT_NR1BEG1_SLOW",
|
||||
"is_pseudo": "0"
|
||||
},
|
||||
"BRKH_INT.BRKH_INT_NR1BEG0->>BRKH_INT_NR1BEG0_SLOW": {
|
||||
"is_directional": "1",
|
||||
"can_invert": "0",
|
||||
"src_wire": "BRKH_INT_NR1BEG0",
|
||||
"dst_wire": "BRKH_INT_NR1BEG0_SLOW",
|
||||
"is_pseudo": "0"
|
||||
},
|
||||
"BRKH_INT.BRKH_INT_SR1END2_SLOW->>BRKH_INT_SR1END2": {
|
||||
"is_directional": "1",
|
||||
"can_invert": "0",
|
||||
"src_wire": "BRKH_INT_SR1END2_SLOW",
|
||||
"dst_wire": "BRKH_INT_SR1END2",
|
||||
"is_pseudo": "0"
|
||||
},
|
||||
"BRKH_INT.BRKH_INT_NR1BEG3->>BRKH_INT_NR1BEG3_SLOW": {
|
||||
"is_directional": "1",
|
||||
"can_invert": "0",
|
||||
"src_wire": "BRKH_INT_NR1BEG3",
|
||||
"dst_wire": "BRKH_INT_NR1BEG3_SLOW",
|
||||
"is_pseudo": "0"
|
||||
},
|
||||
"BRKH_INT.BRKH_INT_SR1END3_SLOW->>BRKH_INT_SR1END3": {
|
||||
"is_directional": "1",
|
||||
"can_invert": "0",
|
||||
"src_wire": "BRKH_INT_SR1END3_SLOW",
|
||||
"dst_wire": "BRKH_INT_SR1END3",
|
||||
"is_pseudo": "0"
|
||||
},
|
||||
"BRKH_INT.BRKH_INT_SL1END2_SLOW->>BRKH_INT_SL1END2": {
|
||||
"is_directional": "1",
|
||||
"can_invert": "0",
|
||||
"src_wire": "BRKH_INT_SL1END2_SLOW",
|
||||
"dst_wire": "BRKH_INT_SL1END2",
|
||||
"is_pseudo": "0"
|
||||
"src_wire": "BRKH_INT_NR1BEG1",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRKH_INT.BRKH_INT_NL1BEG2->>BRKH_INT_NL1BEG2_SLOW": {
|
||||
"is_directional": "1",
|
||||
"can_invert": "0",
|
||||
"src_wire": "BRKH_INT_NL1BEG2",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "BRKH_INT_NL1BEG2_SLOW",
|
||||
"is_pseudo": "0"
|
||||
"is_directional": "1",
|
||||
"src_wire": "BRKH_INT_NL1BEG2",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRKH_INT.BRKH_INT_SL1END2_SLOW->>BRKH_INT_SL1END2": {
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "BRKH_INT_SL1END2",
|
||||
"is_directional": "1",
|
||||
"src_wire": "BRKH_INT_SL1END2_SLOW",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRKH_INT.BRKH_INT_SR1END2_SLOW->>BRKH_INT_SR1END2": {
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "BRKH_INT_SR1END2",
|
||||
"is_directional": "1",
|
||||
"src_wire": "BRKH_INT_SR1END2_SLOW",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRKH_INT.BRKH_INT_NR1BEG0->>BRKH_INT_NR1BEG0_SLOW": {
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "BRKH_INT_NR1BEG0_SLOW",
|
||||
"is_directional": "1",
|
||||
"src_wire": "BRKH_INT_NR1BEG0",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRKH_INT.BRKH_INT_SR1END1_SLOW->>BRKH_INT_SR1END1": {
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "BRKH_INT_SR1END1",
|
||||
"is_directional": "1",
|
||||
"src_wire": "BRKH_INT_SR1END1_SLOW",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRKH_INT.BRKH_INT_SL1END3_SLOW->>BRKH_INT_SL1END3": {
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "BRKH_INT_SL1END3",
|
||||
"is_directional": "1",
|
||||
"src_wire": "BRKH_INT_SL1END3_SLOW",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRKH_INT.BRKH_INT_NL1BEG0->>BRKH_INT_NL1BEG0_SLOW": {
|
||||
"is_directional": "1",
|
||||
"can_invert": "0",
|
||||
"src_wire": "BRKH_INT_NL1BEG0",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "BRKH_INT_NL1BEG0_SLOW",
|
||||
"is_pseudo": "0"
|
||||
"is_directional": "1",
|
||||
"src_wire": "BRKH_INT_NL1BEG0",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRKH_INT.BRKH_INT_NR1BEG2->>BRKH_INT_NR1BEG2_SLOW": {
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "BRKH_INT_NR1BEG2_SLOW",
|
||||
"is_directional": "1",
|
||||
"src_wire": "BRKH_INT_NR1BEG2",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRKH_INT.BRKH_INT_NL1BEG1->>BRKH_INT_NL1BEG1_SLOW": {
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "BRKH_INT_NL1BEG1_SLOW",
|
||||
"is_directional": "1",
|
||||
"src_wire": "BRKH_INT_NL1BEG1",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRKH_INT.BRKH_INT_SL1END0_SLOW->>BRKH_INT_SL1END0": {
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "BRKH_INT_SL1END0",
|
||||
"is_directional": "1",
|
||||
"src_wire": "BRKH_INT_SL1END0_SLOW",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRKH_INT.BRKH_INT_NR1BEG3->>BRKH_INT_NR1BEG3_SLOW": {
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "BRKH_INT_NR1BEG3_SLOW",
|
||||
"is_directional": "1",
|
||||
"src_wire": "BRKH_INT_NR1BEG3",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRKH_INT.BRKH_INT_SL1END1_SLOW->>BRKH_INT_SL1END1": {
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "BRKH_INT_SL1END1",
|
||||
"is_directional": "1",
|
||||
"src_wire": "BRKH_INT_SL1END1_SLOW",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRKH_INT.BRKH_INT_SR1END3_SLOW->>BRKH_INT_SR1END3": {
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "BRKH_INT_SR1END3",
|
||||
"is_directional": "1",
|
||||
"src_wire": "BRKH_INT_SR1END3_SLOW",
|
||||
"can_invert": "0"
|
||||
}
|
||||
},
|
||||
"wires": [
|
||||
"BRKH_INT_NL1BEG2_SLOW",
|
||||
"BRKH_INT_SS6END1",
|
||||
"BRKH_INT_SE6B2",
|
||||
"BRKH_INT_LV9",
|
||||
"BRKH_INT_WW4END_S0_0",
|
||||
"BRKH_INT_LVB4",
|
||||
"BRKH_INT_NW6D3",
|
||||
"BRKH_INT_NN6D2",
|
||||
"BRKH_INT_NL1BEG2",
|
||||
"BRKH_INT_NR1BEG3_SLOW",
|
||||
"BRKH_INT_NL1BEG1",
|
||||
"BRKH_INT_L_LV16",
|
||||
"BRKH_INT_SS6D3",
|
||||
"BRKH_INT_NE6C1",
|
||||
"BRKH_INT_LV13",
|
||||
"BRKH_INT_LV11",
|
||||
"BRKH_INT_SS6E3",
|
||||
"BRKH_INT_NR1BEG3",
|
||||
"BRKH_INT_NW6D0",
|
||||
"BRKH_INT_SE6B3",
|
||||
"BRKH_INT_L_LV17",
|
||||
"BRKH_INT_FAN_BOUNCE_S3_6",
|
||||
"BRKH_INT_NE6C0",
|
||||
"BRKH_INT_SS6C3",
|
||||
"BRKH_INT_SS2END1",
|
||||
"BRKH_INT_WR1BEG_S0",
|
||||
"BRKH_INT_NL1BEG0_SLOW",
|
||||
"BRKH_INT_BYP_BOUNCE6",
|
||||
"BRKH_INT_SS6E2",
|
||||
"BRKH_INT_SW6E2",
|
||||
"BRKH_INT_LVB_L1",
|
||||
"BRKH_INT_SE6B1",
|
||||
"BRKH_INT_SS6A2",
|
||||
"BRKH_INT_L_LV11",
|
||||
"BRKH_INT_LV12",
|
||||
"BRKH_INT_WL1BEG3",
|
||||
"BRKH_INT_FAN_BOUNCE_S3_0",
|
||||
"BRKH_INT_LV2",
|
||||
"BRKH_INT_WR1END_S1_0",
|
||||
"BRKH_INT_NR1BEG0",
|
||||
"BRKH_INT_LV4",
|
||||
"BRKH_INT_SS6C1",
|
||||
"BRKH_INT_NW2END_S0_0",
|
||||
"BRKH_INT_NN2BEG2",
|
||||
"BRKH_INT_NN6C3",
|
||||
"BRKH_INT_SS6A3",
|
||||
"BRKH_INT_LVB_L9",
|
||||
"BRKH_INT_L_LV8",
|
||||
"BRKH_INT_NW6C0",
|
||||
"BRKH_INT_SW6END3",
|
||||
"BRKH_INT_SS6END0",
|
||||
"BRKH_INT_NE6D2",
|
||||
"BRKH_INT_NL1BEG1_SLOW",
|
||||
"BRKH_INT_NN6A2",
|
||||
"BRKH_INT_NR1BEG1",
|
||||
"BRKH_INT_SW6D0",
|
||||
"BRKH_INT_SS2END_N0_3",
|
||||
"BRKH_INT_SS2END2",
|
||||
"BRKH_INT_LVB_L10",
|
||||
"BRKH_INT_SW2A2",
|
||||
"BRKH_INT_LVB_L9",
|
||||
"BRKH_INT_L_LV15",
|
||||
"BRKH_INT_SL1END2_SLOW",
|
||||
"BRKH_INT_SR1END3_SLOW",
|
||||
"BRKH_INT_NN6B3",
|
||||
"BRKH_INT_SW6E1",
|
||||
"BRKH_INT_SE6C3",
|
||||
"BRKH_INT_NN6A0",
|
||||
"BRKH_INT_NN6B1",
|
||||
"BRKH_INT_NN6E0",
|
||||
"BRKH_INT_NN6D3",
|
||||
"BRKH_INT_SE2A2",
|
||||
"BRKH_INT_NN6C1",
|
||||
"BRKH_INT_SS2END0",
|
||||
"BRKH_INT_NN6E3",
|
||||
"BRKH_INT_SL1END3",
|
||||
"BRKH_INT_NW6B2",
|
||||
"BRKH_INT_NL1END_S3_0",
|
||||
"BRKH_INT_L_LV7",
|
||||
"BRKH_INT_SL1END0",
|
||||
"BRKH_INT_LVB_L7",
|
||||
"BRKH_INT_SS6B3",
|
||||
"BRKH_INT_NE6B1",
|
||||
"BRKH_INT_NN2A1",
|
||||
"BRKH_INT_SS6E0",
|
||||
"BRKH_INT_SE6E2",
|
||||
"BRKH_INT_ER1BEG_S0",
|
||||
"BRKH_INT_SS6END2",
|
||||
"BRKH_INT_SS2A1",
|
||||
"BRKH_INT_LV10",
|
||||
"BRKH_INT_NN6BEG1",
|
||||
"BRKH_INT_NR1BEG1_SLOW",
|
||||
"BRKH_INT_SS2END3",
|
||||
"BRKH_INT_SR1END2",
|
||||
"BRKH_INT_LVB5",
|
||||
"BRKH_INT_NN6BEG2",
|
||||
"BRKH_INT_NE6A2",
|
||||
"BRKH_INT_EL1BEG3",
|
||||
"BRKH_INT_NN6B2",
|
||||
"BRKH_INT_NE6A0",
|
||||
"BRKH_INT_SR1END2_SLOW",
|
||||
"BRKH_INT_LVB_L4",
|
||||
"BRKH_INT_L_LV3",
|
||||
"BRKH_INT_NE6A1",
|
||||
"BRKH_INT_NW6C1",
|
||||
"BRKH_INT_SS6A1",
|
||||
"BRKH_INT_LV17",
|
||||
"BRKH_INT_SR1END_N3_3",
|
||||
"BRKH_INT_NW6C3",
|
||||
"BRKH_INT_NW2BEG0",
|
||||
"BRKH_INT_NW6A2",
|
||||
"BRKH_INT_NL1BEG0",
|
||||
"BRKH_INT_SS6END3",
|
||||
"BRKH_INT_SS6A0",
|
||||
"BRKH_INT_SE6D1",
|
||||
"BRKH_INT_SL1END1",
|
||||
"BRKH_INT_LV0",
|
||||
"BRKH_INT_SL1END3_SLOW",
|
||||
"BRKH_INT_LVB6",
|
||||
"BRKH_INT_NW2BEG1",
|
||||
"BRKH_INT_SE6D0",
|
||||
"BRKH_INT_NN6A1",
|
||||
"BRKH_INT_SE6C0",
|
||||
"BRKH_INT_SR1END1",
|
||||
"BRKH_INT_NN6B0",
|
||||
"BRKH_INT_FAN_BOUNCE_S3_2",
|
||||
"BRKH_INT_NW6B1",
|
||||
"BRKH_INT_NE6C2",
|
||||
"BRKH_INT_WL1END3",
|
||||
"BRKH_INT_EL1END_S3_0",
|
||||
"BRKH_INT_L_LV6",
|
||||
"BRKH_INT_NN2A3",
|
||||
"BRKH_INT_LV1",
|
||||
"BRKH_INT_LV8",
|
||||
"BRKH_INT_NE6B3",
|
||||
"BRKH_INT_SR1END1_SLOW",
|
||||
"BRKH_INT_NE6D3",
|
||||
"BRKH_INT_SS6END_N0_3",
|
||||
"BRKH_INT_NN6D0",
|
||||
"BRKH_INT_LVB_L2",
|
||||
"BRKH_INT_SW6D1",
|
||||
"BRKH_INT_SS2A3",
|
||||
"BRKH_INT_SS2A2",
|
||||
"BRKH_INT_NR1BEG0_SLOW",
|
||||
"BRKH_INT_SL1END1_SLOW",
|
||||
"BRKH_INT_NE6D1",
|
||||
"BRKH_INT_SE2A0",
|
||||
"BRKH_INT_SE2A1",
|
||||
"BRKH_INT_L_LV9",
|
||||
"BRKH_INT_SS6B2",
|
||||
"BRKH_INT_LVB_L5",
|
||||
"BRKH_INT_L_LV10",
|
||||
"BRKH_INT_NE6D0",
|
||||
"BRKH_INT_LVB9",
|
||||
"BRKH_INT_SS6E1",
|
||||
"BRKH_INT_LVB2",
|
||||
"BRKH_INT_LVB8",
|
||||
"BRKH_INT_LVB11",
|
||||
"BRKH_INT_NN2A2",
|
||||
"BRKH_INT_SL1END0_SLOW",
|
||||
"BRKH_INT_NN6BEG0",
|
||||
"BRKH_INT_SW6C2",
|
||||
"BRKH_INT_NN6BEG3",
|
||||
"BRKH_INT_L_LV2",
|
||||
"BRKH_INT_FAN_BOUNCE_S3_4",
|
||||
"BRKH_INT_SW2A3",
|
||||
"BRKH_INT_NE6B0",
|
||||
"BRKH_INT_LVB1",
|
||||
"BRKH_INT_NW6C2",
|
||||
"BRKH_INT_BYP_BOUNCE2",
|
||||
"BRKH_INT_SL1END2",
|
||||
"BRKH_INT_LV7",
|
||||
"BRKH_INT_NN2A0",
|
||||
"BRKH_INT_NW6END_S0_0",
|
||||
"BRKH_INT_SW6C3",
|
||||
"BRKH_INT_SW6B0",
|
||||
"BRKH_INT_NE2BEG3",
|
||||
"BRKH_INT_SW6C0",
|
||||
"BRKH_INT_SS6B1",
|
||||
"BRKH_INT_L_LV12",
|
||||
"BRKH_INT_NW2BEG3",
|
||||
"BRKH_INT_LVB10",
|
||||
"BRKH_INT_LV6",
|
||||
"BRKH_INT_SE6C1",
|
||||
"BRKH_INT_LVB12",
|
||||
"BRKH_INT_NW6A1",
|
||||
"BRKH_INT_SS6B0",
|
||||
"BRKH_INT_LV14",
|
||||
"BRKH_INT_NN6C2",
|
||||
"BRKH_INT_SS6D0",
|
||||
"BRKH_INT_LVB3",
|
||||
"BRKH_INT_NN2END_S2_0",
|
||||
"BRKH_INT_NR1BEG2_SLOW",
|
||||
"BRKH_INT_NN2BEG0",
|
||||
"BRKH_INT_NW6A3",
|
||||
"BRKH_INT_NN6END_S1_0",
|
||||
"BRKH_INT_SE2A3",
|
||||
"BRKH_INT_L_LV14",
|
||||
"BRKH_INT_NE6A3",
|
||||
"BRKH_INT_NE2BEG2",
|
||||
"BRKH_INT_NN6C0",
|
||||
"BRKH_INT_SS6C0",
|
||||
"BRKH_INT_NW6D2",
|
||||
"BRKH_INT_SE6D2",
|
||||
"BRKH_INT_NN6E2",
|
||||
"BRKH_INT_NW6B3",
|
||||
"BRKH_INT_SW6B2",
|
||||
"BRKH_INT_LVB_L8",
|
||||
"BRKH_INT_SE6C2",
|
||||
"BRKH_INT_L_LV5",
|
||||
"BRKH_INT_NN6D1",
|
||||
"BRKH_INT_LVB_L11",
|
||||
"BRKH_INT_SW6B3",
|
||||
"BRKH_INT_SW6B1",
|
||||
"BRKH_INT_NN2BEG3",
|
||||
"BRKH_INT_BYP_BOUNCE7",
|
||||
"BRKH_INT_NW6D1",
|
||||
"BRKH_INT_SW6D3",
|
||||
"BRKH_INT_SW6C1",
|
||||
"BRKH_INT_SW6E0",
|
||||
"BRKH_INT_SS6D2",
|
||||
"BRKH_INT_SW2A1",
|
||||
"BRKH_INT_L_LV13",
|
||||
"BRKH_INT_SE6E3",
|
||||
"BRKH_INT_LVB7",
|
||||
"BRKH_INT_SW2A0",
|
||||
"BRKH_INT_SE6E1",
|
||||
"BRKH_INT_BYP_BOUNCE3",
|
||||
"BRKH_INT_NE2BEG0",
|
||||
"BRKH_INT_ER1END3",
|
||||
"BRKH_INT_SR1END3",
|
||||
"BRKH_INT_LV5",
|
||||
"BRKH_INT_L_LV4",
|
||||
"BRKH_INT_NE6C3",
|
||||
"BRKH_INT_SW6D0",
|
||||
"BRKH_INT_NN6E1",
|
||||
"BRKH_INT_SW6D2",
|
||||
"BRKH_INT_SE6E0",
|
||||
"BRKH_INT_NN2BEG1",
|
||||
"BRKH_INT_LVB_L3",
|
||||
"BRKH_INT_LV15",
|
||||
"BRKH_INT_NE2END_S3_0",
|
||||
"BRKH_INT_SW2END3",
|
||||
"BRKH_INT_WW2END3",
|
||||
"BRKH_INT_LV16",
|
||||
"BRKH_INT_SS2A0",
|
||||
"BRKH_INT_NR1BEG2",
|
||||
"BRKH_INT_SW6E3",
|
||||
"BRKH_INT_NW6A0",
|
||||
"BRKH_INT_SS6D1",
|
||||
"BRKH_INT_LVB_L12",
|
||||
"BRKH_INT_NE2BEG1",
|
||||
"BRKH_INT_SS6C2",
|
||||
"BRKH_INT_L_LV1",
|
||||
"BRKH_INT_SE6B0",
|
||||
"BRKH_INT_NW2BEG2",
|
||||
"BRKH_INT_LVB_L6",
|
||||
"BRKH_INT_NE6B2",
|
||||
"BRKH_INT_L_LV0",
|
||||
"BRKH_INT_SL1END1_SLOW",
|
||||
"BRKH_INT_NN6B1",
|
||||
"BRKH_INT_LV4",
|
||||
"BRKH_INT_SR1END_N3_3",
|
||||
"BRKH_INT_L_LV4",
|
||||
"BRKH_INT_SS6A3",
|
||||
"BRKH_INT_L_LV6",
|
||||
"BRKH_INT_LVB_L5",
|
||||
"BRKH_INT_ER1END3",
|
||||
"BRKH_INT_LVB_L3",
|
||||
"BRKH_INT_SW6E3",
|
||||
"BRKH_INT_BYP_BOUNCE7",
|
||||
"BRKH_INT_NN6A0",
|
||||
"BRKH_INT_SS2A2",
|
||||
"BRKH_INT_SS6D3",
|
||||
"BRKH_INT_SW6D2",
|
||||
"BRKH_INT_LV16",
|
||||
"BRKH_INT_LV10",
|
||||
"BRKH_INT_FAN_BOUNCE_S3_0",
|
||||
"BRKH_INT_BYP_BOUNCE6",
|
||||
"BRKH_INT_NW6B2",
|
||||
"BRKH_INT_SR1END2_SLOW",
|
||||
"BRKH_INT_L_LV17",
|
||||
"BRKH_INT_NN6A3",
|
||||
"BRKH_INT_NN6E0",
|
||||
"BRKH_INT_NN6E3",
|
||||
"BRKH_INT_SE6E1",
|
||||
"BRKH_INT_LVB9",
|
||||
"BRKH_INT_SR1END3",
|
||||
"BRKH_INT_SS2END1",
|
||||
"BRKH_INT_LVB_L12",
|
||||
"BRKH_INT_NN2A0",
|
||||
"BRKH_INT_NN6END_S1_0",
|
||||
"BRKH_INT_EL1END_S3_0",
|
||||
"BRKH_INT_NW6D3",
|
||||
"BRKH_INT_LV8",
|
||||
"BRKH_INT_SE6D2",
|
||||
"BRKH_INT_SL1END2_SLOW",
|
||||
"BRKH_INT_NE6B2",
|
||||
"BRKH_INT_NN6BEG3",
|
||||
"BRKH_INT_L_LV14",
|
||||
"BRKH_INT_SS6C3",
|
||||
"BRKH_INT_NW6C1",
|
||||
"BRKH_INT_L_LV13",
|
||||
"BRKH_INT_SS6END1",
|
||||
"BRKH_INT_SS6A0",
|
||||
"BRKH_INT_SW6C0",
|
||||
"BRKH_INT_LVB5",
|
||||
"BRKH_INT_NE6B3",
|
||||
"BRKH_INT_SW6E1",
|
||||
"BRKH_INT_L_LV10",
|
||||
"BRKH_INT_L_LV11",
|
||||
"BRKH_INT_LVB_L7",
|
||||
"BRKH_INT_SS2A3",
|
||||
"BRKH_INT_ER1BEG_S0",
|
||||
"BRKH_INT_SW2A3",
|
||||
"BRKH_INT_LVB_L10",
|
||||
"BRKH_INT_NE2BEG3",
|
||||
"BRKH_INT_NE6D3",
|
||||
"BRKH_INT_NW6B3",
|
||||
"BRKH_INT_SW6B0",
|
||||
"BRKH_INT_NR1BEG0",
|
||||
"BRKH_INT_NW2BEG3",
|
||||
"BRKH_INT_NW6A0",
|
||||
"BRKH_INT_NN6B0",
|
||||
"BRKH_INT_NW6D0",
|
||||
"BRKH_INT_LVB7",
|
||||
"BRKH_INT_SS6A1",
|
||||
"BRKH_INT_NW6D2",
|
||||
"BRKH_INT_SE6B0",
|
||||
"BRKH_INT_SE6C0",
|
||||
"BRKH_INT_NE6A2",
|
||||
"BRKH_INT_LV6",
|
||||
"BRKH_INT_LV17",
|
||||
"BRKH_INT_LV0",
|
||||
"BRKH_INT_SE6B2",
|
||||
"BRKH_INT_L_LV3",
|
||||
"BRKH_INT_NN6A2",
|
||||
"BRKH_INT_NE6B0",
|
||||
"BRKH_INT_SW6E0",
|
||||
"BRKH_INT_NL1BEG2_SLOW",
|
||||
"BRKH_INT_NN6B3",
|
||||
"BRKH_INT_SW2END3",
|
||||
"BRKH_INT_NL1BEG1_SLOW",
|
||||
"BRKH_INT_NL1BEG0",
|
||||
"BRKH_INT_NW6D1",
|
||||
"BRKH_INT_NW6END_S0_0",
|
||||
"BRKH_INT_SR1END2",
|
||||
"BRKH_INT_SE6E0",
|
||||
"BRKH_INT_NW2END_S0_0",
|
||||
"BRKH_INT_WR1BEG_S0",
|
||||
"BRKH_INT_SE6E2",
|
||||
"BRKH_INT_SW6D1",
|
||||
"BRKH_INT_BYP_BOUNCE3",
|
||||
"BRKH_INT_SE2A2",
|
||||
"BRKH_INT_SS6D0",
|
||||
"BRKH_INT_WR1END_S1_0",
|
||||
"BRKH_INT_SE6C3",
|
||||
"BRKH_INT_NW2BEG0",
|
||||
"BRKH_INT_NW6A3",
|
||||
"BRKH_INT_SE2A3",
|
||||
"BRKH_INT_NN6B2",
|
||||
"BRKH_INT_NE6C1",
|
||||
"BRKH_INT_LVB1",
|
||||
"BRKH_INT_NN2A3",
|
||||
"BRKH_INT_NR1BEG2",
|
||||
"BRKH_INT_NR1BEG2_SLOW",
|
||||
"BRKH_INT_NN6A1",
|
||||
"BRKH_INT_NN6C1",
|
||||
"BRKH_INT_NE6C0",
|
||||
"BRKH_INT_NE6D1",
|
||||
"BRKH_INT_NE6D0",
|
||||
"BRKH_INT_NW6C0",
|
||||
"BRKH_INT_LVB8",
|
||||
"BRKH_INT_NR1BEG3_SLOW",
|
||||
"BRKH_INT_LVB_L8",
|
||||
"BRKH_INT_LV13",
|
||||
"BRKH_INT_WW4END_S0_0",
|
||||
"BRKH_INT_SR1END1",
|
||||
"BRKH_INT_NR1BEG1",
|
||||
"BRKH_INT_SW2A0",
|
||||
"BRKH_INT_NN2BEG2",
|
||||
"BRKH_INT_NN6C2",
|
||||
"BRKH_INT_NE6D2",
|
||||
"BRKH_INT_NW6B1",
|
||||
"BRKH_INT_NW2BEG1",
|
||||
"BRKH_INT_LVB11",
|
||||
"BRKH_INT_NE6B1",
|
||||
"BRKH_INT_LVB6",
|
||||
"BRKH_INT_WL1END3",
|
||||
"BRKH_INT_SS6END2",
|
||||
"BRKH_INT_SS6E0",
|
||||
"BRKH_INT_LVB12",
|
||||
"BRKH_INT_SS2END2",
|
||||
"BRKH_INT_NE6A3",
|
||||
"BRKH_INT_L_LV5",
|
||||
"BRKH_INT_NR1BEG1_SLOW",
|
||||
"BRKH_INT_NN2BEG0",
|
||||
"BRKH_INT_SL1END0_SLOW",
|
||||
"BRKH_INT_SW6B1",
|
||||
"BRKH_INT_LV3",
|
||||
"BRKH_INT_LVB3",
|
||||
"BRKH_INT_LVB_L1",
|
||||
"BRKH_INT_NE2BEG1",
|
||||
"BRKH_INT_LV14",
|
||||
"BRKH_INT_NN2END_S2_0",
|
||||
"BRKH_INT_NN6D2",
|
||||
"BRKH_INT_SS6C2",
|
||||
"BRKH_INT_SR1END3_SLOW",
|
||||
"BRKH_INT_NR1BEG0_SLOW",
|
||||
"BRKH_INT_NN2BEG3",
|
||||
"BRKH_INT_SS6D1",
|
||||
"BRKH_INT_SE6B1",
|
||||
"BRKH_INT_SS6END3",
|
||||
"BRKH_INT_NN6C3",
|
||||
"BRKH_INT_NN2BEG1",
|
||||
"BRKH_INT_SS6C0",
|
||||
"BRKH_INT_SS2A1",
|
||||
"BRKH_INT_SS6B1",
|
||||
"BRKH_INT_L_LV1",
|
||||
"BRKH_INT_L_LV8",
|
||||
"BRKH_INT_SW6C2",
|
||||
"BRKH_INT_SW6B2",
|
||||
"BRKH_INT_NE6A0",
|
||||
"BRKH_INT_LVB2",
|
||||
"BRKH_INT_LV11",
|
||||
"BRKH_INT_WL1BEG3",
|
||||
"BRKH_INT_NW6A1",
|
||||
"BRKH_INT_NW6C3",
|
||||
"BRKH_INT_LV15",
|
||||
"BRKH_INT_SE2A1",
|
||||
"BRKH_INT_FAN_BOUNCE_S3_6",
|
||||
"BRKH_INT_SS6D2",
|
||||
"BRKH_INT_SW6B3",
|
||||
"BRKH_INT_LV1",
|
||||
"BRKH_INT_NN6BEG1",
|
||||
"BRKH_INT_SS6C1",
|
||||
"BRKH_INT_NL1BEG1",
|
||||
"BRKH_INT_NN6BEG0",
|
||||
"BRKH_INT_NE6C2",
|
||||
"BRKH_INT_SS2END0",
|
||||
"BRKH_INT_BYP_BOUNCE2",
|
||||
"BRKH_INT_EL1BEG3",
|
||||
"BRKH_INT_LVB4",
|
||||
"BRKH_INT_LV5",
|
||||
"BRKH_INT_SE6D3",
|
||||
"BRKH_INT_NW6B0"
|
||||
"BRKH_INT_L_LV9",
|
||||
"BRKH_INT_FAN_BOUNCE_S3_4",
|
||||
"BRKH_INT_NL1BEG2",
|
||||
"BRKH_INT_SS6B0",
|
||||
"BRKH_INT_SS2A0",
|
||||
"BRKH_INT_L_LV2",
|
||||
"BRKH_INT_SR1END1_SLOW",
|
||||
"BRKH_INT_SS6E3",
|
||||
"BRKH_INT_NW6A2",
|
||||
"BRKH_INT_SL1END3_SLOW",
|
||||
"BRKH_INT_SW6C3",
|
||||
"BRKH_INT_SW6E2",
|
||||
"BRKH_INT_SW6D3",
|
||||
"BRKH_INT_SS6END_N0_3",
|
||||
"BRKH_INT_NN6C0",
|
||||
"BRKH_INT_NN6BEG2",
|
||||
"BRKH_INT_SE6D0",
|
||||
"BRKH_INT_NE6C3",
|
||||
"BRKH_INT_SS6A2",
|
||||
"BRKH_INT_SS6END0",
|
||||
"BRKH_INT_LV12",
|
||||
"BRKH_INT_L_LV16",
|
||||
"BRKH_INT_SE2A0",
|
||||
"BRKH_INT_LVB_L2",
|
||||
"BRKH_INT_NE2BEG0",
|
||||
"BRKH_INT_NN6E2",
|
||||
"BRKH_INT_L_LV0",
|
||||
"BRKH_INT_L_LV12",
|
||||
"BRKH_INT_NL1END_S3_0",
|
||||
"BRKH_INT_SL1END0",
|
||||
"BRKH_INT_FAN_BOUNCE_S3_2",
|
||||
"BRKH_INT_SL1END1",
|
||||
"BRKH_INT_SW6C1",
|
||||
"BRKH_INT_NE2BEG2",
|
||||
"BRKH_INT_SE6B3",
|
||||
"BRKH_INT_NN6D0",
|
||||
"BRKH_INT_SS2END_N0_3",
|
||||
"BRKH_INT_SS2END3",
|
||||
"BRKH_INT_LV7",
|
||||
"BRKH_INT_SE6D1",
|
||||
"BRKH_INT_SE6C2",
|
||||
"BRKH_INT_NE2END_S3_0",
|
||||
"BRKH_INT_LV9",
|
||||
"BRKH_INT_WW2END3",
|
||||
"BRKH_INT_NN2A2",
|
||||
"BRKH_INT_NW2BEG2",
|
||||
"BRKH_INT_SW2A1",
|
||||
"BRKH_INT_NN6D3",
|
||||
"BRKH_INT_NN2A1",
|
||||
"BRKH_INT_SS6E2",
|
||||
"BRKH_INT_LVB_L11",
|
||||
"BRKH_INT_SE6C1",
|
||||
"BRKH_INT_SL1END2",
|
||||
"BRKH_INT_L_LV7",
|
||||
"BRKH_INT_NE6A1",
|
||||
"BRKH_INT_LVB10",
|
||||
"BRKH_INT_NW6B0",
|
||||
"BRKH_INT_SL1END3",
|
||||
"BRKH_INT_NN6D1",
|
||||
"BRKH_INT_SW6END3",
|
||||
"BRKH_INT_SS6E1",
|
||||
"BRKH_INT_SE6E3",
|
||||
"BRKH_INT_SS6B2",
|
||||
"BRKH_INT_LV2",
|
||||
"BRKH_INT_NR1BEG3",
|
||||
"BRKH_INT_NL1BEG0_SLOW",
|
||||
"BRKH_INT_NW6C2",
|
||||
"BRKH_INT_LVB_L4"
|
||||
],
|
||||
"tile_type": "BRKH_INT",
|
||||
"sites": []
|
||||
|
|
|
|||
|
|
@ -1,123 +1,123 @@
|
|||
{
|
||||
"pips": {},
|
||||
"wires": [
|
||||
"T_TERM_UTURN_INT_SR1END1_SLOW",
|
||||
"T_TERM_UTURN_INT_SS2A2",
|
||||
"T_TERM_UTURN_INT_SW6D1",
|
||||
"T_TERM_UTURN_INT_SR1END2_SLOW",
|
||||
"T_TERM_UTURN_INT_SL1END3_SLOW",
|
||||
"T_TERM_UTURN_INT_FAN_BOUNCE_S3_6",
|
||||
"T_TERM_INT_UTURN_LV_R16",
|
||||
"T_TERM_UTURN_INT_SE2A2",
|
||||
"T_TERM_UTURN_INT_SW6B0",
|
||||
"T_TERM_UTURN_INT_LVB_L4",
|
||||
"T_TERM_UTURN_INT_SL1END2_SLOW",
|
||||
"T_TERM_UTURN_INT_SW2A2",
|
||||
"T_TERM_UTURN_INT_SS6E3",
|
||||
"T_TERM_UTURN_INT_LVB0",
|
||||
"T_TERM_UTURN_INT_SW6E3",
|
||||
"T_TERM_UTURN_INT_SE2A1",
|
||||
"T_TERM_UTURN_INT_SS6D1",
|
||||
"T_TERM_UTURN_INT_SS6A1",
|
||||
"T_TERM_UTURN_INT_SW6D2",
|
||||
"T_TERM_UTURN_INT_SR1END3_SLOW",
|
||||
"T_TERM_UTURN_INT_SE6C0",
|
||||
"T_TERM_UTURN_INT_SE6E0",
|
||||
"T_TERM_UTURN_INT_ER1END3",
|
||||
"T_TERM_UTURN_INT_SL1END1_SLOW",
|
||||
"T_TERM_UTURN_INT_SW6C2",
|
||||
"T_TERM_UTURN_INT_LV_L3",
|
||||
"T_TERM_UTURN_INT_SS6D0",
|
||||
"T_TERM_UTURN_INT_FAN_BOUNCE_S3_4",
|
||||
"T_TERM_UTURN_INT_LVB_L1",
|
||||
"T_TERM_UTURN_INT_SS2A1",
|
||||
"T_TERM_UTURN_INT_SE6B2",
|
||||
"T_TERM_UTURN_INT_LV_L5",
|
||||
"T_TERM_UTURN_INT_SS6B3",
|
||||
"T_TERM_UTURN_INT_SL1END0_SLOW",
|
||||
"T_TERM_UTURN_INT_SW6E0",
|
||||
"T_TERM_UTURN_INT_SE6D2",
|
||||
"T_TERM_UTURN_INT_WR1END_S1_0",
|
||||
"T_TERM_UTURN_INT_FAN_BOUNCE_S3_2",
|
||||
"T_TERM_UTURN_INT_SW6D3",
|
||||
"T_TERM_UTURN_INT_SW6B3",
|
||||
"T_TERM_UTURN_INT_SE6B0",
|
||||
"T_TERM_UTURN_INT_SW2A3",
|
||||
"T_TERM_UTURN_INT_LV_L4",
|
||||
"T_TERM_UTURN_INT_SE2A2",
|
||||
"T_TERM_UTURN_INT_SL1END3_SLOW",
|
||||
"T_TERM_UTURN_INT_SE6E2",
|
||||
"T_TERM_UTURN_INT_LVB2",
|
||||
"T_TERM_INT_UTURN_LV_R6",
|
||||
"T_TERM_UTURN_INT_SS6END3",
|
||||
"T_TERM_UTURN_INT_SS6END0",
|
||||
"T_TERM_UTURN_INT_SS6B1",
|
||||
"T_TERM_UTURN_INT_SE2A0",
|
||||
"T_TERM_UTURN_INT_SS2END3",
|
||||
"T_TERM_UTURN_INT_SS6END2",
|
||||
"T_TERM_UTURN_INT_SE6B3",
|
||||
"T_TERM_INT_UTURN_LV_R4",
|
||||
"T_TERM_UTURN_INT_LV_L16",
|
||||
"T_TERM_UTURN_INT_SS2A0",
|
||||
"T_TERM_UTURN_INT_SE6C3",
|
||||
"T_TERM_UTURN_INT_LVB_L4",
|
||||
"T_TERM_UTURN_INT_SW6D2",
|
||||
"T_TERM_UTURN_INT_LV_L7",
|
||||
"T_TERM_UTURN_INT_SW6C3",
|
||||
"T_TERM_INT_UTURN_LV_R7",
|
||||
"T_TERM_UTURN_INT_LVB_L3",
|
||||
"T_TERM_UTURN_INT_LVB_L2",
|
||||
"T_TERM_UTURN_INT_LV_L17",
|
||||
"T_TERM_UTURN_INT_SS6B1",
|
||||
"T_TERM_INT_UTURN_LV_R3",
|
||||
"T_TERM_UTURN_INT_SS6B0",
|
||||
"T_TERM_UTURN_INT_SS6D1",
|
||||
"T_TERM_UTURN_INT_SE6D0",
|
||||
"T_TERM_UTURN_INT_SS6D2",
|
||||
"T_TERM_UTURN_INT_SS6C3",
|
||||
"T_TERM_UTURN_INT_SE6C1",
|
||||
"T_TERM_UTURN_INT_SS2A2",
|
||||
"T_TERM_UTURN_INT_SS6END3",
|
||||
"T_TERM_UTURN_INT_SE2A3",
|
||||
"T_TERM_UTURN_INT_SS6C1",
|
||||
"T_TERM_UTURN_INT_SS2A3",
|
||||
"T_TERM_UTURN_INT_LVB0",
|
||||
"T_TERM_UTURN_INT_LVB1",
|
||||
"T_TERM_UTURN_INT_SS6A1",
|
||||
"T_TERM_UTURN_INT_FAN_BOUNCE_S3_4",
|
||||
"T_TERM_UTURN_INT_LVB4",
|
||||
"T_TERM_UTURN_INT_LV_L9",
|
||||
"T_TERM_UTURN_INT_SE6B0",
|
||||
"T_TERM_UTURN_INT_SS6E2",
|
||||
"T_TERM_UTURN_INT_SW6B1",
|
||||
"T_TERM_UTURN_INT_SS6E1",
|
||||
"T_TERM_UTURN_INT_SS2END1",
|
||||
"T_TERM_UTURN_INT_LV_L17",
|
||||
"T_TERM_UTURN_INT_SS2A3",
|
||||
"T_TERM_UTURN_INT_SW6E2",
|
||||
"T_TERM_UTURN_INT_LVB3",
|
||||
"T_TERM_UTURN_INT_SE2A3",
|
||||
"T_TERM_UTURN_INT_LV_L16",
|
||||
"T_TERM_UTURN_INT_LV_L2",
|
||||
"T_TERM_UTURN_INT_SW6E1",
|
||||
"T_TERM_UTURN_INT_SS6E0",
|
||||
"T_TERM_UTURN_INT_SW6D3",
|
||||
"T_TERM_UTURN_INT_SS2END2",
|
||||
"T_TERM_UTURN_INT_SS6C0",
|
||||
"T_TERM_UTURN_INT_SS6END2",
|
||||
"T_TERM_UTURN_INT_SE6C3",
|
||||
"T_TERM_UTURN_INT_LV_L4",
|
||||
"T_TERM_UTURN_INT_SW6C0",
|
||||
"T_TERM_INT_UTURN_LV_R9",
|
||||
"T_TERM_INT_UTURN_LV_R5",
|
||||
"T_TERM_UTURN_INT_SS6A0",
|
||||
"T_TERM_UTURN_INT_SS2A0",
|
||||
"T_TERM_UTURN_INT_SS6B2",
|
||||
"T_TERM_INT_UTURN_LV_R17",
|
||||
"T_TERM_UTURN_INT_SL1END0_SLOW",
|
||||
"T_TERM_UTURN_INT_ER1BEG_S0",
|
||||
"T_TERM_UTURN_INT_SE6E3",
|
||||
"T_TERM_UTURN_INT_SS6C3",
|
||||
"T_TERM_UTURN_INT_WR1BEG_S0",
|
||||
"T_TERM_UTURN_INT_SE6D1",
|
||||
"T_TERM_UTURN_INT_SE6B1",
|
||||
"T_TERM_INT_UTURN_LV_R2",
|
||||
"T_TERM_UTURN_INT_SE6D3",
|
||||
"T_TERM_UTURN_INT_FAN_BOUNCE_S3_2",
|
||||
"T_TERM_UTURN_INT_SS6END0",
|
||||
"T_TERM_INT_UTURN_LV_R6",
|
||||
"T_TERM_INT_UTURN_LV_R7",
|
||||
"T_TERM_UTURN_INT_SW2A1",
|
||||
"T_TERM_UTURN_INT_LVB1",
|
||||
"T_TERM_UTURN_INT_FAN_BOUNCE_S3_0",
|
||||
"T_TERM_UTURN_INT_SW6E0",
|
||||
"T_TERM_UTURN_INT_SW6C1",
|
||||
"T_TERM_UTURN_INT_SS6B0",
|
||||
"T_TERM_UTURN_INT_SS6A3",
|
||||
"T_TERM_UTURN_INT_SS2END0",
|
||||
"T_TERM_UTURN_INT_SS6C2",
|
||||
"T_TERM_UTURN_INT_SE6E1",
|
||||
"T_TERM_UTURN_INT_SE6C2",
|
||||
"T_TERM_UTURN_INT_SE6D2",
|
||||
"T_TERM_UTURN_INT_SS6A2",
|
||||
"T_TERM_UTURN_INT_SE6E2",
|
||||
"T_TERM_UTURN_INT_SW2A3",
|
||||
"T_TERM_UTURN_INT_LVB_L0",
|
||||
"T_TERM_UTURN_INT_SE6B3",
|
||||
"T_TERM_UTURN_INT_SS6END1",
|
||||
"T_TERM_UTURN_INT_SS6D2",
|
||||
"T_TERM_INT_UTURN_LV_R3",
|
||||
"T_TERM_UTURN_INT_WR1END_S1_0",
|
||||
"T_TERM_UTURN_INT_SS6B3",
|
||||
"T_TERM_UTURN_INT_LV_L6",
|
||||
"T_TERM_UTURN_INT_LV_L3",
|
||||
"T_TERM_INT_UTURN_LV_R4",
|
||||
"T_TERM_UTURN_INT_SW6E3",
|
||||
"T_TERM_UTURN_INT_SW6B2",
|
||||
"T_TERM_UTURN_INT_SW6B3",
|
||||
"T_TERM_UTURN_INT_SW6D0",
|
||||
"T_TERM_UTURN_INT_SE6C1",
|
||||
"T_TERM_UTURN_INT_SW2A0",
|
||||
"T_TERM_UTURN_INT_LVB_L5",
|
||||
"T_TERM_UTURN_INT_SW2A2",
|
||||
"T_TERM_UTURN_INT_LVB5",
|
||||
"T_TERM_UTURN_INT_LVB3",
|
||||
"T_TERM_UTURN_INT_SE6B2",
|
||||
"T_TERM_UTURN_INT_SS2END0",
|
||||
"T_TERM_UTURN_INT_SW6B1",
|
||||
"T_TERM_UTURN_INT_SS6D3",
|
||||
"T_TERM_UTURN_INT_SS6C1",
|
||||
"T_TERM_UTURN_INT_SE6D0",
|
||||
"T_TERM_UTURN_INT_LVB5"
|
||||
"T_TERM_UTURN_INT_ER1END3",
|
||||
"T_TERM_UTURN_INT_SL1END1_SLOW",
|
||||
"T_TERM_UTURN_INT_SE6C2",
|
||||
"T_TERM_UTURN_INT_SR1END1_SLOW",
|
||||
"T_TERM_UTURN_INT_SW2A0",
|
||||
"T_TERM_UTURN_INT_SW6C1",
|
||||
"T_TERM_INT_UTURN_LV_R16",
|
||||
"T_TERM_UTURN_INT_SE6D3",
|
||||
"T_TERM_UTURN_INT_SW6E1",
|
||||
"T_TERM_UTURN_INT_SS6A3",
|
||||
"T_TERM_UTURN_INT_SW6C0",
|
||||
"T_TERM_UTURN_INT_SR1END3_SLOW",
|
||||
"T_TERM_UTURN_INT_SW6B2",
|
||||
"T_TERM_UTURN_INT_SE6E3",
|
||||
"T_TERM_UTURN_INT_LVB_L3",
|
||||
"T_TERM_UTURN_INT_SS6E3",
|
||||
"T_TERM_UTURN_INT_SW6D1",
|
||||
"T_TERM_UTURN_INT_LVB_L0",
|
||||
"T_TERM_UTURN_INT_SS6E0",
|
||||
"T_TERM_UTURN_INT_SW6C2",
|
||||
"T_TERM_UTURN_INT_SS2END1",
|
||||
"T_TERM_UTURN_INT_SS6C0",
|
||||
"T_TERM_INT_UTURN_LV_R2",
|
||||
"T_TERM_INT_UTURN_LV_R17",
|
||||
"T_TERM_UTURN_INT_SS6END1",
|
||||
"T_TERM_INT_UTURN_LV_R5",
|
||||
"T_TERM_UTURN_INT_LV_L2",
|
||||
"T_TERM_UTURN_INT_FAN_BOUNCE_S3_6",
|
||||
"T_TERM_UTURN_INT_LVB_L1",
|
||||
"T_TERM_UTURN_INT_LVB_L5",
|
||||
"T_TERM_UTURN_INT_SL1END2_SLOW",
|
||||
"T_TERM_UTURN_INT_SW6C3",
|
||||
"T_TERM_UTURN_INT_SS6A0",
|
||||
"T_TERM_INT_UTURN_LV_R9",
|
||||
"T_TERM_UTURN_INT_SE6E1",
|
||||
"T_TERM_UTURN_INT_FAN_BOUNCE_S3_0",
|
||||
"T_TERM_UTURN_INT_SE6C0",
|
||||
"T_TERM_UTURN_INT_SE2A0",
|
||||
"T_TERM_UTURN_INT_LV_L5",
|
||||
"T_TERM_UTURN_INT_SE6B1",
|
||||
"T_TERM_UTURN_INT_SS6C2",
|
||||
"T_TERM_UTURN_INT_SS6E1",
|
||||
"T_TERM_UTURN_INT_LV_L6",
|
||||
"T_TERM_UTURN_INT_SS2END3",
|
||||
"T_TERM_UTURN_INT_SS6B2",
|
||||
"T_TERM_UTURN_INT_SS6E2",
|
||||
"T_TERM_UTURN_INT_WR1BEG_S0",
|
||||
"T_TERM_UTURN_INT_SS2A1",
|
||||
"T_TERM_UTURN_INT_SS2END2",
|
||||
"T_TERM_UTURN_INT_SW6E2",
|
||||
"T_TERM_UTURN_INT_SW6D0",
|
||||
"T_TERM_UTURN_INT_SR1END2_SLOW",
|
||||
"T_TERM_UTURN_INT_SW6B0",
|
||||
"T_TERM_UTURN_INT_LVB_L2",
|
||||
"T_TERM_UTURN_INT_SE6D1",
|
||||
"T_TERM_UTURN_INT_ER1BEG_S0"
|
||||
],
|
||||
"tile_type": "BRKH_TERM_INT",
|
||||
"sites": []
|
||||
|
|
|
|||
|
|
@ -1,124 +1,124 @@
|
|||
{
|
||||
"pips": {},
|
||||
"wires": [
|
||||
"B_TERM_UTURN_INT_SE2BEG3",
|
||||
"B_TERM_UTURN_INT_SS6E2",
|
||||
"B_TERM_UTURN_INT_SR1BEG3",
|
||||
"B_TERM_UTURN_INT_SE6A1",
|
||||
"B_TERM_UTURN_INT_SW2BEG1",
|
||||
"B_TERM_UTURN_INT_LVB5",
|
||||
"B_TERM_UTURN_INT_SW6B2",
|
||||
"B_TERM_UTURN_INT_LVB0",
|
||||
"B_TERM_UTURN_INT_LV7",
|
||||
"B_TERM_UTURN_INT_SS2A0",
|
||||
"B_TERM_UTURN_INT_SW6B3",
|
||||
"B_TERM_UTURN_INT_SS6C3",
|
||||
"B_TERM_UTURN_INT_SS2BEG0",
|
||||
"B_TERM_UTURN_INT_SS6E0",
|
||||
"B_TERM_UTURN_INT_SW6END_N0_3",
|
||||
"B_TERM_UTURN_INT_LV_L7",
|
||||
"B_TERM_UTURN_INT_SS6B3",
|
||||
"B_TERM_UTURN_INT_LV2",
|
||||
"B_TERM_UTURN_INT_LV8",
|
||||
"B_TERM_UTURN_INT_SW2BEG3",
|
||||
"B_TERM_UTURN_INT_SS6BEG3",
|
||||
"B_TERM_UTURN_INT_LVB4",
|
||||
"B_TERM_UTURN_INT_LV_L18",
|
||||
"B_TERM_UTURN_INT_LVB_L1",
|
||||
"B_TERM_UTURN_INT_SL1BEG3",
|
||||
"B_TERM_UTURN_INT_SE6A2",
|
||||
"B_TERM_UTURN_INT_ER1BEG0",
|
||||
"B_TERM_UTURN_INT_SW6B0",
|
||||
"B_TERM_UTURN_INT_SE6C3",
|
||||
"B_TERM_UTURN_INT_SS6B2",
|
||||
"B_TERM_UTURN_INT_SE6D1",
|
||||
"B_TERM_UTURN_INT_SS6A1",
|
||||
"B_TERM_UTURN_INT_SE6C1",
|
||||
"B_TERM_UTURN_INT_SS2BEG2",
|
||||
"B_TERM_UTURN_INT_SW2BEG0",
|
||||
"B_TERM_UTURN_INT_SE6D3",
|
||||
"B_TERM_UTURN_INT_SE6D0",
|
||||
"B_TERM_UTURN_INT_SW6B2",
|
||||
"B_TERM_UTURN_INT_LVB_L3",
|
||||
"B_TERM_UTURN_INT_LV_L6",
|
||||
"B_TERM_UTURN_INT_SW6A1",
|
||||
"B_TERM_UTURN_INT_LV_L9",
|
||||
"B_TERM_UTURN_INT_SL1BEG0",
|
||||
"B_TERM_UTURN_INT_LVB5",
|
||||
"B_TERM_UTURN_INT_FAN_BOUNCE2",
|
||||
"B_TERM_UTURN_INT_SS6B1",
|
||||
"B_TERM_UTURN_INT_SW6C3",
|
||||
"B_TERM_UTURN_INT_SS6C1",
|
||||
"B_TERM_UTURN_INT_SS6E3",
|
||||
"B_TERM_UTURN_INT_SS2A1",
|
||||
"B_TERM_UTURN_INT_LV_L8",
|
||||
"B_TERM_UTURN_INT_SW6A2",
|
||||
"B_TERM_UTURN_INT_LVB2",
|
||||
"B_TERM_UTURN_INT_LV9",
|
||||
"B_TERM_UTURN_INT_SE6A0",
|
||||
"B_TERM_UTURN_INT_FAN_BOUNCE0",
|
||||
"B_TERM_UTURN_INT_SW6D3",
|
||||
"B_TERM_UTURN_INT_SS6A2",
|
||||
"B_TERM_UTURN_INT_ER1END_N3_3",
|
||||
"B_TERM_UTURN_INT_WR1END0",
|
||||
"B_TERM_UTURN_INT_SE2BEG3",
|
||||
"B_TERM_UTURN_INT_SS6C0",
|
||||
"B_TERM_UTURN_INT_SE2BEG2",
|
||||
"B_TERM_UTURN_INT_SE6A3",
|
||||
"B_TERM_UTURN_INT_SW6A0",
|
||||
"B_TERM_UTURN_INT_SW2BEG2",
|
||||
"B_TERM_UTURN_INT_SS6BEG1",
|
||||
"B_TERM_UTURN_INT_SS6A3",
|
||||
"B_TERM_UTURN_INT_LV3",
|
||||
"B_TERM_UTURN_INT_LVB1",
|
||||
"B_TERM_UTURN_INT_SE2BEG0",
|
||||
"B_TERM_UTURN_INT_SS6C2",
|
||||
"B_TERM_UTURN_INT_LV_L4",
|
||||
"B_TERM_UTURN_INT_SW6D0",
|
||||
"B_TERM_UTURN_INT_LV_L3",
|
||||
"B_TERM_UTURN_INT_SL1BEG1",
|
||||
"B_TERM_UTURN_INT_SW6B1",
|
||||
"B_TERM_UTURN_INT_LV18",
|
||||
"B_TERM_UTURN_INT_LVB_L0",
|
||||
"B_TERM_UTURN_INT_SS6A0",
|
||||
"B_TERM_UTURN_INT_SE2BEG2",
|
||||
"B_TERM_UTURN_INT_SS6A1",
|
||||
"B_TERM_UTURN_INT_SS6B2",
|
||||
"B_TERM_UTURN_INT_LV_L5",
|
||||
"B_TERM_UTURN_INT_LVB_L3",
|
||||
"B_TERM_UTURN_INT_LVB_L2",
|
||||
"B_TERM_UTURN_INT_ER1END_N3_3",
|
||||
"B_TERM_UTURN_INT_SS2BEG1",
|
||||
"B_TERM_UTURN_INT_SW6A0",
|
||||
"B_TERM_UTURN_INT_LVB2",
|
||||
"B_TERM_UTURN_INT_LV5",
|
||||
"B_TERM_UTURN_INT_SW6C0",
|
||||
"B_TERM_UTURN_INT_SW6D1",
|
||||
"B_TERM_UTURN_INT_SW6C2",
|
||||
"B_TERM_UTURN_INT_SL1BEG2",
|
||||
"B_TERM_UTURN_INT_SE6B3",
|
||||
"B_TERM_UTURN_INT_SR1BEG3",
|
||||
"B_TERM_UTURN_INT_SE6B1",
|
||||
"B_TERM_UTURN_INT_SW6C1",
|
||||
"B_TERM_UTURN_INT_SW2BEG1",
|
||||
"B_TERM_UTURN_INT_SS6BEG2",
|
||||
"B_TERM_UTURN_INT_LV4",
|
||||
"B_TERM_UTURN_INT_SE6C2",
|
||||
"B_TERM_UTURN_INT_SW2BEG0",
|
||||
"B_TERM_UTURN_INT_LVB4",
|
||||
"B_TERM_UTURN_INT_LV6",
|
||||
"B_TERM_UTURN_INT_SR1BEG1",
|
||||
"B_TERM_UTURN_INT_SE6A1",
|
||||
"B_TERM_UTURN_INT_SS6D0",
|
||||
"B_TERM_UTURN_INT_SW6A3",
|
||||
"B_TERM_UTURN_INT_SE6D2",
|
||||
"B_TERM_UTURN_INT_SS2A2",
|
||||
"B_TERM_UTURN_INT_LV_L2",
|
||||
"B_TERM_UTURN_INT_LV5",
|
||||
"B_TERM_UTURN_INT_FAN_BOUNCE6",
|
||||
"B_TERM_UTURN_INT_SS6D2",
|
||||
"B_TERM_UTURN_INT_SS6BEG3",
|
||||
"B_TERM_UTURN_INT_WR1BEG0",
|
||||
"B_TERM_UTURN_INT_SE6B2",
|
||||
"B_TERM_UTURN_INT_SS6E1",
|
||||
"B_TERM_UTURN_INT_SR1BEG2",
|
||||
"B_TERM_UTURN_INT_SS6D1",
|
||||
"B_TERM_UTURN_INT_SW6D2",
|
||||
"B_TERM_UTURN_INT_FAN_BOUNCE4",
|
||||
"B_TERM_UTURN_INT_SS2BEG1",
|
||||
"B_TERM_UTURN_INT_LVB3",
|
||||
"B_TERM_UTURN_INT_SE2BEG1",
|
||||
"B_TERM_UTURN_INT_FAN_BOUNCE0",
|
||||
"B_TERM_UTURN_INT_LV_L3",
|
||||
"B_TERM_UTURN_INT_SE6D2",
|
||||
"B_TERM_UTURN_INT_SS6B0",
|
||||
"B_TERM_UTURN_INT_FAN_BOUNCE6",
|
||||
"B_TERM_UTURN_INT_LV_L2",
|
||||
"B_TERM_UTURN_INT_SS6E0",
|
||||
"B_TERM_UTURN_INT_SE6C0",
|
||||
"B_TERM_UTURN_INT_ER1BEG0",
|
||||
"B_TERM_UTURN_INT_WR1BEG0",
|
||||
"B_TERM_UTURN_INT_SS6A2",
|
||||
"B_TERM_UTURN_INT_LV_L8",
|
||||
"B_TERM_UTURN_INT_SE6B3",
|
||||
"B_TERM_UTURN_INT_LV18",
|
||||
"B_TERM_UTURN_INT_SW6B1",
|
||||
"B_TERM_UTURN_INT_LV_L9",
|
||||
"B_TERM_UTURN_INT_LVB_L1",
|
||||
"B_TERM_UTURN_INT_SE2BEG0",
|
||||
"B_TERM_UTURN_INT_LVB_L5",
|
||||
"B_TERM_UTURN_INT_SS2BEG0",
|
||||
"B_TERM_UTURN_INT_SL1BEG1",
|
||||
"B_TERM_UTURN_INT_SE6C1",
|
||||
"B_TERM_UTURN_INT_SW6D1",
|
||||
"B_TERM_UTURN_INT_FAN_BOUNCE2",
|
||||
"B_TERM_UTURN_INT_SR1BEG2",
|
||||
"B_TERM_UTURN_INT_SW6A1",
|
||||
"B_TERM_UTURN_INT_SS6D1",
|
||||
"B_TERM_UTURN_INT_LVB0",
|
||||
"B_TERM_UTURN_INT_SS6D2",
|
||||
"B_TERM_UTURN_INT_SW6C0",
|
||||
"B_TERM_UTURN_INT_SS6D0",
|
||||
"B_TERM_UTURN_INT_SS6A3",
|
||||
"B_TERM_UTURN_INT_SL1BEG3",
|
||||
"B_TERM_UTURN_INT_LV2",
|
||||
"B_TERM_UTURN_INT_SE6D3",
|
||||
"B_TERM_UTURN_INT_SW6C1",
|
||||
"B_TERM_UTURN_INT_SS2A1",
|
||||
"B_TERM_UTURN_INT_LVB_L4",
|
||||
"B_TERM_UTURN_INT_SS2A2",
|
||||
"B_TERM_UTURN_INT_SW6B0",
|
||||
"B_TERM_UTURN_INT_LV6",
|
||||
"B_TERM_UTURN_INT_SE6B1",
|
||||
"B_TERM_UTURN_INT_SW6D2",
|
||||
"B_TERM_UTURN_INT_SE6D1",
|
||||
"B_TERM_UTURN_INT_FAN_BOUNCE4",
|
||||
"B_TERM_UTURN_INT_SW6D3",
|
||||
"B_TERM_UTURN_INT_SW6END_N0_3",
|
||||
"B_TERM_UTURN_INT_WR1END0",
|
||||
"B_TERM_UTURN_INT_SW6A2",
|
||||
"B_TERM_UTURN_INT_LV7",
|
||||
"B_TERM_UTURN_INT_SE6B2",
|
||||
"B_TERM_UTURN_INT_SE6A0",
|
||||
"B_TERM_UTURN_INT_SE6A2",
|
||||
"B_TERM_UTURN_INT_SS6B1",
|
||||
"B_TERM_UTURN_INT_SS2BEG3",
|
||||
"B_TERM_UTURN_INT_SS6C1",
|
||||
"B_TERM_UTURN_INT_SS6C0",
|
||||
"B_TERM_UTURN_INT_LVB1",
|
||||
"B_TERM_UTURN_INT_LV_L4",
|
||||
"B_TERM_UTURN_INT_LV3",
|
||||
"B_TERM_UTURN_INT_SS2A0",
|
||||
"B_TERM_UTURN_INT_LV4",
|
||||
"B_TERM_UTURN_INT_SE6C3",
|
||||
"B_TERM_UTURN_INT_SS2BEG2",
|
||||
"B_TERM_UTURN_INT_SS6BEG1",
|
||||
"B_TERM_UTURN_INT_LV_L18",
|
||||
"B_TERM_UTURN_INT_LV_L6",
|
||||
"B_TERM_UTURN_INT_SW6D0",
|
||||
"B_TERM_UTURN_INT_SS6B3",
|
||||
"B_TERM_UTURN_INT_SS6C3",
|
||||
"B_TERM_UTURN_INT_SW6C2",
|
||||
"B_TERM_UTURN_INT_SE6A3",
|
||||
"B_TERM_UTURN_INT_LV_L7",
|
||||
"B_TERM_UTURN_INT_SS2A3",
|
||||
"B_TERM_UTURN_INT_SS6C2",
|
||||
"B_TERM_UTURN_INT_LV8",
|
||||
"B_TERM_UTURN_INT_SS6BEG2",
|
||||
"B_TERM_UTURN_INT_SL1BEG0",
|
||||
"B_TERM_UTURN_INT_SS6E3",
|
||||
"B_TERM_UTURN_INT_SS6BEG0",
|
||||
"B_TERM_UTURN_INT_SS6E1",
|
||||
"B_TERM_UTURN_INT_SR1BEG1",
|
||||
"B_TERM_UTURN_INT_SW6B3",
|
||||
"B_TERM_UTURN_INT_SE6D0",
|
||||
"B_TERM_UTURN_INT_SE6B0",
|
||||
"B_TERM_UTURN_INT_LV9",
|
||||
"B_TERM_UTURN_INT_SS6E2",
|
||||
"B_TERM_UTURN_INT_LVB_L2",
|
||||
"B_TERM_UTURN_INT_SS6D3",
|
||||
"B_TERM_UTURN_INT_SL1BEG2"
|
||||
"B_TERM_UTURN_INT_SS2A3",
|
||||
"B_TERM_UTURN_INT_SS6BEG0",
|
||||
"B_TERM_UTURN_INT_SS2BEG3",
|
||||
"B_TERM_UTURN_INT_LVB_L4",
|
||||
"B_TERM_UTURN_INT_LV_L5",
|
||||
"B_TERM_UTURN_INT_SE6B0",
|
||||
"B_TERM_UTURN_INT_SS6B0",
|
||||
"B_TERM_UTURN_INT_SE6C0"
|
||||
],
|
||||
"tile_type": "B_TERM_INT",
|
||||
"sites": []
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -1,260 +1,260 @@
|
|||
{
|
||||
"pips": {},
|
||||
"wires": [
|
||||
"CLK_FEED_CK_GCLK31",
|
||||
"CLK_FEED_NE2A2",
|
||||
"CLK_FEED_CK_BUFG_CASC9",
|
||||
"CLK_FEED_R_CK_BUFG_CASC23",
|
||||
"CLK_FEED_R_CK_GCLK0",
|
||||
"CLK_FEED_NW4END3",
|
||||
"CLK_FEED_R_CK_BUFG_CASC12",
|
||||
"CLK_FEED_EE4C3",
|
||||
"CLK_FEED_CK_BUFG_CASC31",
|
||||
"CLK_FEED_R_CK_GCLK24",
|
||||
"CLK_FEED_R_CK_BUFG_CASC29",
|
||||
"CLK_FEED_R_CK_BUFG_CASC8",
|
||||
"CLK_FEED_WW4C1",
|
||||
"CLK_FEED_SE2A3",
|
||||
"CLK_FEED_R_CK_GCLK19",
|
||||
"CLK_FEED_R_CK_BUFG_CASC10",
|
||||
"CLK_FEED_WW4A1",
|
||||
"CLK_FEED_EE4A2",
|
||||
"CLK_FEED_R_CK_BUFG_CASC7",
|
||||
"CLK_FEED_R_CK_BUFG_CASC2",
|
||||
"CLK_FEED_R_CK_GCLK9",
|
||||
"CLK_FEED_CK_BUFG_CASC19",
|
||||
"CLK_FEED_EE2BEG2",
|
||||
"CLK_FEED_EE2A2",
|
||||
"CLK_FEED_R_CK_BUFG_CASC5",
|
||||
"CLK_FEED_CK_BUFG_CASC4",
|
||||
"CLK_FEED_CK_GCLK19",
|
||||
"CLK_FEED_R_CK_BUFG_CASC17",
|
||||
"CLK_FEED_SW4A3",
|
||||
"CLK_FEED_WW4C3",
|
||||
"CLK_FEED_LH10",
|
||||
"CLK_FEED_R_CK_GCLK29",
|
||||
"CLK_FEED_CK_GCLK11",
|
||||
"CLK_FEED_CK_GCLK7",
|
||||
"CLK_FEED_WL1END0",
|
||||
"CLK_FEED_WW4END3",
|
||||
"CLK_FEED_R_CK_GCLK6",
|
||||
"CLK_FEED_CK_GCLK12",
|
||||
"CLK_FEED_NE2A3",
|
||||
"CLK_FEED_NW2A3",
|
||||
"CLK_FEED_CK_BUFG_CASC10",
|
||||
"CLK_FEED_R_CK_BUFG_CASC9",
|
||||
"CLK_FEED_SW4A0",
|
||||
"CLK_FEED_SE4BEG1",
|
||||
"CLK_FEED_SE2A2",
|
||||
"CLK_FEED_R_CK_BUFG_CASC27",
|
||||
"CLK_FEED_R_CK_BUFG_CASC11",
|
||||
"CLK_FEED_NE2A0",
|
||||
"CLK_FEED_SW4A3",
|
||||
"CLK_FEED_NW2A0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC19",
|
||||
"CLK_FEED_NE4BEG3",
|
||||
"CLK_FEED_SE4BEG3",
|
||||
"CLK_FEED_CK_BUFG_CASC29",
|
||||
"CLK_FEED_CK_GCLK26",
|
||||
"CLK_FEED_R_CK_GCLK5",
|
||||
"CLK_FEED_R_CK_BUFG_CASC12",
|
||||
"CLK_FEED_LH10",
|
||||
"CLK_FEED_SE4C3",
|
||||
"CLK_FEED_R_CK_BUFG_CASC14",
|
||||
"CLK_FEED_R_CK_GCLK14",
|
||||
"CLK_FEED_NW2A2",
|
||||
"CLK_FEED_NW4END2",
|
||||
"CLK_FEED_R_CK_GCLK17",
|
||||
"CLK_FEED_R_CK_BUFG_CASC17",
|
||||
"CLK_FEED_R_CK_GCLK18",
|
||||
"CLK_FEED_R_CK_BUFG_CASC24",
|
||||
"CLK_FEED_CK_BUFG_CASC4",
|
||||
"CLK_FEED_LH9",
|
||||
"CLK_FEED_CK_BUFG_CASC18",
|
||||
"CLK_FEED_NW4END1",
|
||||
"CLK_FEED_LH4",
|
||||
"CLK_FEED_NW4A2",
|
||||
"CLK_FEED_EE2BEG1",
|
||||
"CLK_FEED_EE4BEG1",
|
||||
"CLK_FEED_CK_GCLK30",
|
||||
"CLK_FEED_CK_GCLK22",
|
||||
"CLK_FEED_CK_GCLK16",
|
||||
"CLK_FEED_R_CK_GCLK2",
|
||||
"CLK_FEED_LH1",
|
||||
"CLK_FEED_R_CK_GCLK23",
|
||||
"CLK_FEED_LH5",
|
||||
"CLK_FEED_EE2A0",
|
||||
"CLK_FEED_WW4B0",
|
||||
"CLK_FEED_SE4BEG2",
|
||||
"CLK_FEED_NW4END3",
|
||||
"CLK_FEED_NE4BEG2",
|
||||
"CLK_FEED_NE4C3",
|
||||
"CLK_FEED_R_CK_GCLK25",
|
||||
"CLK_FEED_EE2BEG2",
|
||||
"CLK_FEED_WL1END2",
|
||||
"CLK_FEED_CK_GCLK0",
|
||||
"CLK_FEED_R_CK_GCLK10",
|
||||
"CLK_FEED_CK_GCLK20",
|
||||
"CLK_FEED_ER1BEG3",
|
||||
"CLK_FEED_WW4A1",
|
||||
"CLK_FEED_CK_BUFG_CASC17",
|
||||
"CLK_FEED_CK_GCLK23",
|
||||
"CLK_FEED_LH2",
|
||||
"CLK_FEED_EE4B1",
|
||||
"CLK_FEED_R_CK_GCLK3",
|
||||
"CLK_FEED_R_CK_GCLK7",
|
||||
"CLK_FEED_NW2A1",
|
||||
"CLK_FEED_LH8",
|
||||
"CLK_FEED_R_CK_BUFG_CASC29",
|
||||
"CLK_FEED_CK_GCLK3",
|
||||
"CLK_FEED_CK_BUFG_CASC5",
|
||||
"CLK_FEED_LH3",
|
||||
"CLK_FEED_LH11",
|
||||
"CLK_FEED_R_CK_BUFG_CASC23",
|
||||
"CLK_FEED_WL1END3",
|
||||
"CLK_FEED_R_CK_BUFG_CASC15",
|
||||
"CLK_FEED_CK_BUFG_CASC30",
|
||||
"CLK_FEED_ER1BEG2",
|
||||
"CLK_FEED_EL1BEG3",
|
||||
"CLK_FEED_CK_GCLK1",
|
||||
"CLK_FEED_NE4C2",
|
||||
"CLK_FEED_CK_BUFG_CASC21",
|
||||
"CLK_FEED_EE4C1",
|
||||
"CLK_FEED_CK_BUFG_CASC12",
|
||||
"CLK_FEED_R_CK_GCLK2",
|
||||
"CLK_FEED_SE2A1",
|
||||
"CLK_FEED_CK_BUFG_CASC14",
|
||||
"CLK_FEED_ER1BEG3",
|
||||
"CLK_FEED_WW4C0",
|
||||
"CLK_FEED_CK_GCLK4",
|
||||
"CLK_FEED_CK_BUFG_CASC23",
|
||||
"CLK_FEED_ER1BEG1",
|
||||
"CLK_FEED_NW4A3",
|
||||
"CLK_FEED_R_CK_BUFG_CASC0",
|
||||
"CLK_FEED_ER1BEG0",
|
||||
"CLK_FEED_CK_GCLK16",
|
||||
"CLK_FEED_CK_GCLK29",
|
||||
"CLK_FEED_R_CK_GCLK26",
|
||||
"CLK_FEED_R_CK_BUFG_CASC4",
|
||||
"CLK_FEED_WW4C2",
|
||||
"CLK_FEED_R_CK_GCLK16",
|
||||
"CLK_FEED_CK_GCLK23",
|
||||
"CLK_FEED_EE4A0",
|
||||
"CLK_FEED_WR1END1",
|
||||
"CLK_FEED_NE4C0",
|
||||
"CLK_FEED_CK_BUFG_CASC16",
|
||||
"CLK_FEED_R_CK_GCLK5",
|
||||
"CLK_FEED_R_CK_BUFG_CASC19",
|
||||
"CLK_FEED_CK_GCLK6",
|
||||
"CLK_FEED_EE4B1",
|
||||
"CLK_FEED_CK_GCLK9",
|
||||
"CLK_FEED_CK_GCLK25",
|
||||
"CLK_FEED_EE4A1",
|
||||
"CLK_FEED_SW4END1",
|
||||
"CLK_FEED_SW4END2",
|
||||
"CLK_FEED_CK_GCLK2",
|
||||
"CLK_FEED_WW2A3",
|
||||
"CLK_FEED_NE2A0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC14",
|
||||
"CLK_FEED_CK_BUFG_CASC7",
|
||||
"CLK_FEED_CK_BUFG_CASC27",
|
||||
"CLK_FEED_R_CK_BUFG_CASC1",
|
||||
"CLK_FEED_WW4A3",
|
||||
"CLK_FEED_SW4A0",
|
||||
"CLK_FEED_EE4C0",
|
||||
"CLK_FEED_CK_BUFG_CASC5",
|
||||
"CLK_FEED_CK_BUFG_CASC13",
|
||||
"CLK_FEED_CK_GCLK21",
|
||||
"CLK_FEED_CK_GCLK28",
|
||||
"CLK_FEED_WW2A2",
|
||||
"CLK_FEED_NE4BEG2",
|
||||
"CLK_FEED_WR1END2",
|
||||
"CLK_FEED_EL1BEG2",
|
||||
"CLK_FEED_CK_BUFG_CASC8",
|
||||
"CLK_FEED_LH1",
|
||||
"CLK_FEED_R_CK_GCLK30",
|
||||
"CLK_FEED_WW2A0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC15",
|
||||
"CLK_FEED_R_CK_GCLK3",
|
||||
"CLK_FEED_WW4A2",
|
||||
"CLK_FEED_EL1BEG1",
|
||||
"CLK_FEED_WL1END0",
|
||||
"CLK_FEED_SE2A2",
|
||||
"CLK_FEED_WW4END3",
|
||||
"CLK_FEED_R_CK_BUFG_CASC28",
|
||||
"CLK_FEED_NW4END0",
|
||||
"CLK_FEED_SW4A2",
|
||||
"CLK_FEED_NW4END1",
|
||||
"CLK_FEED_WW2A1",
|
||||
"CLK_FEED_EE2A0",
|
||||
"CLK_FEED_EE2BEG0",
|
||||
"CLK_FEED_NE4C1",
|
||||
"CLK_FEED_CK_GCLK20",
|
||||
"CLK_FEED_R_CK_GCLK11",
|
||||
"CLK_FEED_LH6",
|
||||
"CLK_FEED_NE4BEG0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC24",
|
||||
"CLK_FEED_NW2A1",
|
||||
"CLK_FEED_CK_GCLK12",
|
||||
"CLK_FEED_CK_BUFG_CASC2",
|
||||
"CLK_FEED_WL1END3",
|
||||
"CLK_FEED_CK_GCLK22",
|
||||
"CLK_FEED_R_CK_GCLK4",
|
||||
"CLK_FEED_LH9",
|
||||
"CLK_FEED_R_CK_GCLK6",
|
||||
"CLK_FEED_CK_GCLK30",
|
||||
"CLK_FEED_NE4BEG3",
|
||||
"CLK_FEED_R_CK_GCLK27",
|
||||
"CLK_FEED_R_CK_GCLK18",
|
||||
"CLK_FEED_CK_BUFG_CASC3",
|
||||
"CLK_FEED_WW2END2",
|
||||
"CLK_FEED_EE2BEG1",
|
||||
"CLK_FEED_WW4END0",
|
||||
"CLK_FEED_CK_BUFG_CASC25",
|
||||
"CLK_FEED_LH2",
|
||||
"CLK_FEED_R_CK_GCLK25",
|
||||
"CLK_FEED_EE4B3",
|
||||
"CLK_FEED_CK_BUFG_CASC24",
|
||||
"CLK_FEED_WW2END1",
|
||||
"CLK_FEED_LH12",
|
||||
"CLK_FEED_LH7",
|
||||
"CLK_FEED_R_CK_GCLK14",
|
||||
"CLK_FEED_SW2A1",
|
||||
"CLK_FEED_NW4A1",
|
||||
"CLK_FEED_R_CK_BUFG_CASC18",
|
||||
"CLK_FEED_CK_GCLK27",
|
||||
"CLK_FEED_MONITOR_P",
|
||||
"CLK_FEED_SE4BEG1",
|
||||
"CLK_FEED_MONITOR_N",
|
||||
"CLK_FEED_CK_BUFG_CASC18",
|
||||
"CLK_FEED_CK_BUFG_CASC15",
|
||||
"CLK_FEED_SW2A0",
|
||||
"CLK_FEED_CK_BUFG_CASC0",
|
||||
"CLK_FEED_WR1END0",
|
||||
"CLK_FEED_CK_BUFG_CASC29",
|
||||
"CLK_FEED_R_CK_BUFG_CASC20",
|
||||
"CLK_FEED_NE4BEG1",
|
||||
"CLK_FEED_WW4B0",
|
||||
"CLK_FEED_NE2A1",
|
||||
"CLK_FEED_SE4C0",
|
||||
"CLK_FEED_R_CK_GCLK22",
|
||||
"CLK_FEED_R_CK_GCLK8",
|
||||
"CLK_FEED_WW2END3",
|
||||
"CLK_FEED_R_CK_BUFG_CASC25",
|
||||
"CLK_FEED_EE2A1",
|
||||
"CLK_FEED_EE4B2",
|
||||
"CLK_FEED_CK_GCLK0",
|
||||
"CLK_FEED_WW4B2",
|
||||
"CLK_FEED_R_CK_BUFG_CASC26",
|
||||
"CLK_FEED_R_CK_BUFG_CASC22",
|
||||
"CLK_FEED_SW2A2",
|
||||
"CLK_FEED_CK_GCLK8",
|
||||
"CLK_FEED_LH11",
|
||||
"CLK_FEED_NW2A0",
|
||||
"CLK_FEED_CK_BUFG_CASC22",
|
||||
"CLK_FEED_CK_GCLK18",
|
||||
"CLK_FEED_CK_GCLK26",
|
||||
"CLK_FEED_CK_BUFG_CASC20",
|
||||
"CLK_FEED_CK_GCLK3",
|
||||
"CLK_FEED_SE4C1",
|
||||
"CLK_FEED_NW4A2",
|
||||
"CLK_FEED_WW2END0",
|
||||
"CLK_FEED_CK_BUFG_CASC6",
|
||||
"CLK_FEED_SE2A0",
|
||||
"CLK_FEED_WW4A0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC7",
|
||||
"CLK_FEED_EE4BEG2",
|
||||
"CLK_FEED_CK_GCLK10",
|
||||
"CLK_FEED_R_CK_BUFG_CASC30",
|
||||
"CLK_FEED_SW4END3",
|
||||
"CLK_FEED_EL1BEG0",
|
||||
"CLK_FEED_EE4BEG0",
|
||||
"CLK_FEED_WR1END3",
|
||||
"CLK_FEED_CK_GCLK5",
|
||||
"CLK_FEED_CK_BUFG_CASC30",
|
||||
"CLK_FEED_SE4BEG0",
|
||||
"CLK_FEED_SE4BEG3",
|
||||
"CLK_FEED_EE4BEG1",
|
||||
"CLK_FEED_R_CK_BUFG_CASC6",
|
||||
"CLK_FEED_CK_GCLK17",
|
||||
"CLK_FEED_SW4A1",
|
||||
"CLK_FEED_R_CK_GCLK23",
|
||||
"CLK_FEED_CK_GCLK19",
|
||||
"CLK_FEED_CK_GCLK11",
|
||||
"CLK_FEED_CK_BUFG_CASC21",
|
||||
"CLK_FEED_EE2BEG3",
|
||||
"CLK_FEED_R_CK_BUFG_CASC16",
|
||||
"CLK_FEED_R_CK_GCLK21",
|
||||
"CLK_FEED_R_CK_GCLK10",
|
||||
"CLK_FEED_NE4C3",
|
||||
"CLK_FEED_R_CK_BUFG_CASC21",
|
||||
"CLK_FEED_NW4A0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC31",
|
||||
"CLK_FEED_SE4BEG2",
|
||||
"CLK_FEED_CK_BUFG_CASC11",
|
||||
"CLK_FEED_R_CK_GCLK20",
|
||||
"CLK_FEED_SW4END0",
|
||||
"CLK_FEED_CK_BUFG_CASC26",
|
||||
"CLK_FEED_LH5",
|
||||
"CLK_FEED_R_CK_GCLK31",
|
||||
"CLK_FEED_WW4B1",
|
||||
"CLK_FEED_R_CK_GCLK17",
|
||||
"CLK_FEED_R_CK_GCLK7",
|
||||
"CLK_FEED_WW4END1",
|
||||
"CLK_FEED_CK_GCLK24",
|
||||
"CLK_FEED_CK_BUFG_CASC28",
|
||||
"CLK_FEED_EE2A3",
|
||||
"CLK_FEED_CK_GCLK14",
|
||||
"CLK_FEED_CK_GCLK13",
|
||||
"CLK_FEED_CK_BUFG_CASC1",
|
||||
"CLK_FEED_R_CK_BUFG_CASC9",
|
||||
"CLK_FEED_LH8",
|
||||
"CLK_FEED_EE4C2",
|
||||
"CLK_FEED_WW4B3",
|
||||
"CLK_FEED_EE4A3",
|
||||
"CLK_FEED_NW2A2",
|
||||
"CLK_FEED_CK_BUFG_CASC10",
|
||||
"CLK_FEED_WL1END1",
|
||||
"CLK_FEED_SE4C3",
|
||||
"CLK_FEED_WL1END2",
|
||||
"CLK_FEED_LH3",
|
||||
"CLK_FEED_R_CK_GCLK13",
|
||||
"CLK_FEED_NW2A3",
|
||||
"CLK_FEED_LH4",
|
||||
"CLK_FEED_EE4B0",
|
||||
"CLK_FEED_SE4C2",
|
||||
"CLK_FEED_SW2A3",
|
||||
"CLK_FEED_EE4BEG3",
|
||||
"CLK_FEED_CK_GCLK15",
|
||||
"CLK_FEED_R_CK_GCLK1",
|
||||
"CLK_FEED_R_CK_GCLK15",
|
||||
"CLK_FEED_R_CK_GCLK12",
|
||||
"CLK_FEED_WL1END1",
|
||||
"CLK_FEED_R_CK_GCLK13",
|
||||
"CLK_FEED_R_CK_BUFG_CASC4",
|
||||
"CLK_FEED_EE4B2",
|
||||
"CLK_FEED_R_CK_GCLK28",
|
||||
"CLK_FEED_CK_BUFG_CASC17",
|
||||
"CLK_FEED_R_CK_BUFG_CASC13",
|
||||
"CLK_FEED_NW4END2",
|
||||
"CLK_FEED_WW4END2",
|
||||
"CLK_FEED_CK_GCLK4",
|
||||
"CLK_FEED_R_CK_BUFG_CASC8",
|
||||
"CLK_FEED_CK_GCLK6",
|
||||
"CLK_FEED_EE4C3",
|
||||
"CLK_FEED_NW4A0",
|
||||
"CLK_FEED_WW2END0",
|
||||
"CLK_FEED_SE2A0",
|
||||
"CLK_FEED_LH6",
|
||||
"CLK_FEED_MONITOR_P",
|
||||
"CLK_FEED_SE4C2",
|
||||
"CLK_FEED_WW2END3",
|
||||
"CLK_FEED_R_CK_BUFG_CASC18",
|
||||
"CLK_FEED_WW4B2",
|
||||
"CLK_FEED_R_CK_GCLK27",
|
||||
"CLK_FEED_WR1END1",
|
||||
"CLK_FEED_R_CK_BUFG_CASC28",
|
||||
"CLK_FEED_WW4END0",
|
||||
"CLK_FEED_CK_BUFG_CASC12",
|
||||
"CLK_FEED_SW2A3",
|
||||
"CLK_FEED_WW4C0",
|
||||
"CLK_FEED_SW4END1",
|
||||
"CLK_FEED_CK_BUFG_CASC7",
|
||||
"CLK_FEED_LH12",
|
||||
"CLK_FEED_R_CK_GCLK9",
|
||||
"CLK_FEED_CK_BUFG_CASC2",
|
||||
"CLK_FEED_CK_BUFG_CASC9",
|
||||
"CLK_FEED_CK_BUFG_CASC28",
|
||||
"CLK_FEED_NW4END0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC5",
|
||||
"CLK_FEED_R_CK_GCLK30",
|
||||
"CLK_FEED_R_CK_GCLK21",
|
||||
"CLK_FEED_R_CK_BUFG_CASC10",
|
||||
"CLK_FEED_CK_BUFG_CASC20",
|
||||
"CLK_FEED_EL1BEG1",
|
||||
"CLK_FEED_NE4C0",
|
||||
"CLK_FEED_WW4END1",
|
||||
"CLK_FEED_CK_BUFG_CASC25",
|
||||
"CLK_FEED_ER1BEG1",
|
||||
"CLK_FEED_CK_BUFG_CASC19",
|
||||
"CLK_FEED_EE4A0",
|
||||
"CLK_FEED_SW2A0",
|
||||
"CLK_FEED_CK_BUFG_CASC22",
|
||||
"CLK_FEED_NW4A3",
|
||||
"CLK_FEED_CK_GCLK25",
|
||||
"CLK_FEED_WR1END0",
|
||||
"CLK_FEED_CK_GCLK5",
|
||||
"CLK_FEED_SW4A2",
|
||||
"CLK_FEED_EE4C0",
|
||||
"CLK_FEED_CK_BUFG_CASC11",
|
||||
"CLK_FEED_EL1BEG2",
|
||||
"CLK_FEED_WR1END3",
|
||||
"CLK_FEED_CK_BUFG_CASC3",
|
||||
"CLK_FEED_CK_GCLK15",
|
||||
"CLK_FEED_MONITOR_N",
|
||||
"CLK_FEED_NE4C2",
|
||||
"CLK_FEED_CK_BUFG_CASC1",
|
||||
"CLK_FEED_EE2A3",
|
||||
"CLK_FEED_WW2A3",
|
||||
"CLK_FEED_WW2END1",
|
||||
"CLK_FEED_R_CK_GCLK12",
|
||||
"CLK_FEED_CK_GCLK18",
|
||||
"CLK_FEED_WW2END2",
|
||||
"CLK_FEED_SW4A1",
|
||||
"CLK_FEED_SE4C1",
|
||||
"CLK_FEED_CK_BUFG_CASC14",
|
||||
"CLK_FEED_R_CK_BUFG_CASC31",
|
||||
"CLK_FEED_R_CK_BUFG_CASC6",
|
||||
"CLK_FEED_EE4B0",
|
||||
"CLK_FEED_R_CK_GCLK0",
|
||||
"CLK_FEED_CK_GCLK10",
|
||||
"CLK_FEED_CK_GCLK27",
|
||||
"CLK_FEED_WW4A2",
|
||||
"CLK_FEED_R_CK_GCLK29",
|
||||
"CLK_FEED_R_CK_GCLK15",
|
||||
"CLK_FEED_R_CK_BUFG_CASC20",
|
||||
"CLK_FEED_R_CK_GCLK31",
|
||||
"CLK_FEED_CK_GCLK29",
|
||||
"CLK_FEED_R_CK_GCLK11",
|
||||
"CLK_FEED_CK_BUFG_CASC27",
|
||||
"CLK_FEED_CK_BUFG_CASC16",
|
||||
"CLK_FEED_CK_BUFG_CASC15",
|
||||
"CLK_FEED_R_CK_BUFG_CASC1",
|
||||
"CLK_FEED_CK_BUFG_CASC26",
|
||||
"CLK_FEED_R_CK_BUFG_CASC3",
|
||||
"CLK_FEED_NE2A3"
|
||||
"CLK_FEED_CK_GCLK21",
|
||||
"CLK_FEED_NE2A2",
|
||||
"CLK_FEED_WW2A0",
|
||||
"CLK_FEED_EE2A2",
|
||||
"CLK_FEED_LH7",
|
||||
"CLK_FEED_R_CK_BUFG_CASC21",
|
||||
"CLK_FEED_EE4A1",
|
||||
"CLK_FEED_CK_GCLK2",
|
||||
"CLK_FEED_WW4B1",
|
||||
"CLK_FEED_R_CK_BUFG_CASC0",
|
||||
"CLK_FEED_NW4A1",
|
||||
"CLK_FEED_SW4END3",
|
||||
"CLK_FEED_R_CK_GCLK24",
|
||||
"CLK_FEED_EE4A2",
|
||||
"CLK_FEED_CK_GCLK28",
|
||||
"CLK_FEED_WW4END2",
|
||||
"CLK_FEED_EL1BEG0",
|
||||
"CLK_FEED_CK_BUFG_CASC0",
|
||||
"CLK_FEED_CK_BUFG_CASC31",
|
||||
"CLK_FEED_SE4BEG0",
|
||||
"CLK_FEED_WW4C2",
|
||||
"CLK_FEED_WR1END2",
|
||||
"CLK_FEED_CK_BUFG_CASC6",
|
||||
"CLK_FEED_CK_GCLK24",
|
||||
"CLK_FEED_ER1BEG0",
|
||||
"CLK_FEED_WW4C1",
|
||||
"CLK_FEED_CK_GCLK8",
|
||||
"CLK_FEED_SW4END2",
|
||||
"CLK_FEED_R_CK_GCLK20",
|
||||
"CLK_FEED_SE2A3",
|
||||
"CLK_FEED_R_CK_GCLK4",
|
||||
"CLK_FEED_EE2A1",
|
||||
"CLK_FEED_EE4A3",
|
||||
"CLK_FEED_R_CK_GCLK19",
|
||||
"CLK_FEED_R_CK_BUFG_CASC13",
|
||||
"CLK_FEED_CK_BUFG_CASC8",
|
||||
"CLK_FEED_CK_GCLK14",
|
||||
"CLK_FEED_WW2A1",
|
||||
"CLK_FEED_CK_GCLK17",
|
||||
"CLK_FEED_R_CK_BUFG_CASC22",
|
||||
"CLK_FEED_EE4B3",
|
||||
"CLK_FEED_NE4C1",
|
||||
"CLK_FEED_R_CK_BUFG_CASC26",
|
||||
"CLK_FEED_SW2A2",
|
||||
"CLK_FEED_EE4C1",
|
||||
"CLK_FEED_SE2A1",
|
||||
"CLK_FEED_CK_GCLK7",
|
||||
"CLK_FEED_CK_GCLK1",
|
||||
"CLK_FEED_CK_GCLK9",
|
||||
"CLK_FEED_WW4C3",
|
||||
"CLK_FEED_R_CK_GCLK22",
|
||||
"CLK_FEED_CK_BUFG_CASC23",
|
||||
"CLK_FEED_EE4BEG0",
|
||||
"CLK_FEED_CK_BUFG_CASC24",
|
||||
"CLK_FEED_WW4A0",
|
||||
"CLK_FEED_WW2A2",
|
||||
"CLK_FEED_NE2A1",
|
||||
"CLK_FEED_CK_GCLK31",
|
||||
"CLK_FEED_NE4BEG1",
|
||||
"CLK_FEED_R_CK_GCLK8",
|
||||
"CLK_FEED_R_CK_BUFG_CASC16",
|
||||
"CLK_FEED_EE4C2",
|
||||
"CLK_FEED_CK_BUFG_CASC13",
|
||||
"CLK_FEED_R_CK_GCLK26",
|
||||
"CLK_FEED_EE4BEG3",
|
||||
"CLK_FEED_WW4B3",
|
||||
"CLK_FEED_NE4BEG0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC30",
|
||||
"CLK_FEED_SE4C0",
|
||||
"CLK_FEED_CK_GCLK13",
|
||||
"CLK_FEED_WW4A3",
|
||||
"CLK_FEED_R_CK_BUFG_CASC25",
|
||||
"CLK_FEED_R_CK_BUFG_CASC2",
|
||||
"CLK_FEED_EE2BEG0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC11",
|
||||
"CLK_FEED_SW2A1"
|
||||
],
|
||||
"tile_type": "CLK_FEED",
|
||||
"sites": []
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -1,364 +1,364 @@
|
|||
{
|
||||
"pips": {},
|
||||
"wires": [
|
||||
"CLK_PMV_IMUX40_0",
|
||||
"CLK_FEED_CK_GCLK31",
|
||||
"CLK_FEED_NE2A2",
|
||||
"CLK_PMV_IMUX43_0",
|
||||
"CLK_FEED_CK_BUFG_CASC9",
|
||||
"CLK_FEED_R_CK_BUFG_CASC23",
|
||||
"CLK_PMV_LOGIC_OUTS17_0",
|
||||
"CLK_FEED_R_CK_GCLK0",
|
||||
"CLK_FEED_NW4END3",
|
||||
"CLK_FEED_R_CK_BUFG_CASC12",
|
||||
"CLK_FEED_EE4C3",
|
||||
"CLK_PMV_LOGIC_OUTS5_0",
|
||||
"CLK_PMV_BYP4_0",
|
||||
"CLK_FEED_CK_BUFG_CASC31",
|
||||
"CLK_FEED_R_CK_GCLK24",
|
||||
"CLK_PMV_LOGIC_OUTS18_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC29",
|
||||
"CLK_FEED_R_CK_BUFG_CASC8",
|
||||
"CLK_FEED_WW4C1",
|
||||
"CLK_FEED_SE2A3",
|
||||
"CLK_PMV_FAN7_0",
|
||||
"CLK_FEED_R_CK_GCLK19",
|
||||
"CLK_FEED_WW4A1",
|
||||
"CLK_FEED_R_CK_BUFG_CASC10",
|
||||
"CLK_PMV_FAN2_0",
|
||||
"CLK_PMV_BYP7_0",
|
||||
"CLK_FEED_EE4A2",
|
||||
"CLK_FEED_R_CK_BUFG_CASC7",
|
||||
"CLK_FEED_R_CK_BUFG_CASC2",
|
||||
"CLK_FEED_R_CK_GCLK9",
|
||||
"CLK_PMV_IMUX10_0",
|
||||
"CLK_FEED_CK_BUFG_CASC19",
|
||||
"CLK_PMV_IMUX5_0",
|
||||
"CLK_FEED_EE2BEG2",
|
||||
"CLK_FEED_EE2A2",
|
||||
"CLK_FEED_R_CK_BUFG_CASC5",
|
||||
"CLK_FEED_CK_BUFG_CASC4",
|
||||
"CLK_FEED_CK_GCLK19",
|
||||
"CLK_FEED_R_CK_BUFG_CASC17",
|
||||
"CLK_FEED_SW4A3",
|
||||
"CLK_PMV_IMUX23_0",
|
||||
"CLK_FEED_WW4C3",
|
||||
"CLK_FEED_LH10",
|
||||
"CLK_FEED_R_CK_GCLK29",
|
||||
"CLK_FEED_CK_GCLK11",
|
||||
"CLK_FEED_CK_GCLK7",
|
||||
"CLK_FEED_R_CK_BUFG_CASC27",
|
||||
"CLK_FEED_R_CK_BUFG_CASC11",
|
||||
"CLK_FEED_ER1BEG2",
|
||||
"CLK_FEED_EL1BEG3",
|
||||
"CLK_FEED_CK_GCLK1",
|
||||
"CLK_FEED_NE4C2",
|
||||
"CLK_FEED_CK_BUFG_CASC21",
|
||||
"CLK_FEED_EE4C1",
|
||||
"CLK_FEED_CK_BUFG_CASC12",
|
||||
"CLK_FEED_R_CK_GCLK2",
|
||||
"CLK_FEED_SE2A1",
|
||||
"CLK_FEED_CK_BUFG_CASC14",
|
||||
"CLK_FEED_ER1BEG3",
|
||||
"CLK_FEED_WW4C0",
|
||||
"CLK_FEED_CK_BUFG_CASC23",
|
||||
"CLK_FEED_CK_GCLK4",
|
||||
"CLK_FEED_ER1BEG1",
|
||||
"CLK_PMV_BYP6_0",
|
||||
"CLK_FEED_NW4A3",
|
||||
"CLK_FEED_R_CK_BUFG_CASC0",
|
||||
"CLK_PMV_FAN0_0",
|
||||
"CLK_FEED_ER1BEG0",
|
||||
"CLK_MTBF2_Q3B",
|
||||
"CLK_PMV_IMUX31_0",
|
||||
"CLK_PMV_LOGIC_OUTS14_0",
|
||||
"CLK_FEED_CK_GCLK16",
|
||||
"CLK_FEED_CK_GCLK29",
|
||||
"CLK_FEED_R_CK_GCLK26",
|
||||
"CLK_PMV_LOGIC_OUTS3_0",
|
||||
"CLK_FEED_WW4C2",
|
||||
"CLK_FEED_R_CK_BUFG_CASC4",
|
||||
"CLK_FEED_R_CK_GCLK16",
|
||||
"CLK_FEED_CK_GCLK23",
|
||||
"CLK_FEED_EE4A0",
|
||||
"CLK_FEED_WR1END1",
|
||||
"CLK_FEED_NE4C0",
|
||||
"CLK_FEED_CK_BUFG_CASC16",
|
||||
"CLK_PMV_FAN1_0",
|
||||
"CLK_FEED_R_CK_GCLK5",
|
||||
"CLK_FEED_R_CK_BUFG_CASC19",
|
||||
"CLK_FEED_CK_GCLK6",
|
||||
"CLK_FEED_EE4B1",
|
||||
"CLK_FEED_CK_GCLK25",
|
||||
"CLK_FEED_EE4A1",
|
||||
"CLK_FEED_CK_GCLK9",
|
||||
"CLK_FEED_SW4END1",
|
||||
"CLK_FEED_SW4END2",
|
||||
"CLK_PMV_LOGIC_OUTS12_0",
|
||||
"CLK_FEED_CK_GCLK2",
|
||||
"CLK_FEED_WW2A3",
|
||||
"CLK_FEED_NE2A0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC14",
|
||||
"CLK_PMV_IMUX44_0",
|
||||
"CLK_FEED_CK_BUFG_CASC7",
|
||||
"CLK_FEED_CK_BUFG_CASC27",
|
||||
"CLK_PMV_IMUX8_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC1",
|
||||
"CLK_FEED_WW4A3",
|
||||
"CLK_PMV_IMUX1_0",
|
||||
"CLK_MTBF2_RESET",
|
||||
"CLK_FEED_SW4A0",
|
||||
"CLK_PMV_LOGIC_OUTS2_0",
|
||||
"CLK_MTBF2_Q2B",
|
||||
"CLK_FEED_EE4C0",
|
||||
"CLK_FEED_CK_BUFG_CASC5",
|
||||
"CLK_FEED_CK_BUFG_CASC13",
|
||||
"CLK_FEED_CK_GCLK21",
|
||||
"CLK_PMV_FAN3_0",
|
||||
"CLK_FEED_CK_GCLK28",
|
||||
"CLK_PMV_IMUX15_0",
|
||||
"CLK_PMV_IMUX26_0",
|
||||
"CLK_PMV_CTRL1_0",
|
||||
"CLK_PMV_FAN5_0",
|
||||
"CLK_FEED_NE4BEG2",
|
||||
"CLK_FEED_WW2A2",
|
||||
"CLK_FEED_WR1END2",
|
||||
"CLK_PMV_CTRL0_0",
|
||||
"CLK_MTBF2_Q7B",
|
||||
"CLK_FEED_EL1BEG2",
|
||||
"CLK_PMV_IMUX30_0",
|
||||
"CLK_FEED_LH1",
|
||||
"CLK_FEED_CK_BUFG_CASC8",
|
||||
"CLK_FEED_R_CK_GCLK30",
|
||||
"CLK_PMV_LOGIC_OUTS9_0",
|
||||
"CLK_FEED_WW2A0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC15",
|
||||
"CLK_FEED_R_CK_GCLK3",
|
||||
"CLK_FEED_WW4A2",
|
||||
"CLK_PMV_IMUX13_0",
|
||||
"CLK_FEED_EL1BEG1",
|
||||
"CLK_FEED_WL1END0",
|
||||
"CLK_FEED_SE2A2",
|
||||
"CLK_PMV_FAN3_0",
|
||||
"CLK_FEED_WW4END3",
|
||||
"CLK_FEED_R_CK_BUFG_CASC28",
|
||||
"CLK_FEED_NW4END0",
|
||||
"CLK_FEED_SW4A2",
|
||||
"CLK_PMV_IMUX22_0",
|
||||
"CLK_PMV_IMUX4_0",
|
||||
"CLK_PMV_BYP3_0",
|
||||
"CLK_FEED_NW4END1",
|
||||
"CLK_PMV_LOGIC_OUTS15_0",
|
||||
"CLK_FEED_WW2A1",
|
||||
"CLK_FEED_EE2A0",
|
||||
"CLK_FEED_EE2BEG0",
|
||||
"CLK_PMV_IMUX20_0",
|
||||
"CLK_PMV_BYP0_0",
|
||||
"CLK_FEED_NE4C1",
|
||||
"CLK_FEED_CK_GCLK20",
|
||||
"CLK_FEED_R_CK_GCLK11",
|
||||
"CLK_FEED_LH6",
|
||||
"CLK_FEED_NE4BEG0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC24",
|
||||
"CLK_FEED_NW2A1",
|
||||
"CLK_FEED_CK_GCLK12",
|
||||
"CLK_FEED_CK_BUFG_CASC2",
|
||||
"CLK_FEED_CK_GCLK22",
|
||||
"CLK_FEED_WL1END3",
|
||||
"CLK_FEED_R_CK_GCLK4",
|
||||
"CLK_PMV_IMUX33_0",
|
||||
"CLK_PMV_IMUX0_0",
|
||||
"CLK_FEED_LH9",
|
||||
"CLK_FEED_R_CK_GCLK6",
|
||||
"CLK_FEED_CK_GCLK30",
|
||||
"CLK_PMV_IMUX24_0",
|
||||
"CLK_MTBF2_Q1B",
|
||||
"CLK_FEED_NE4BEG3",
|
||||
"CLK_PMV_BYP1_0",
|
||||
"CLK_FEED_R_CK_GCLK27",
|
||||
"CLK_FEED_CK_BUFG_CASC3",
|
||||
"CLK_FEED_R_CK_GCLK18",
|
||||
"CLK_FEED_WW2END2",
|
||||
"CLK_FEED_EE2BEG1",
|
||||
"CLK_FEED_WW4END0",
|
||||
"CLK_FEED_CK_BUFG_CASC25",
|
||||
"CLK_MTBF2_Q0B",
|
||||
"CLK_PMV_IMUX16_0",
|
||||
"CLK_FEED_LH2",
|
||||
"CLK_PMV_LOGIC_OUTS6_0",
|
||||
"CLK_FEED_R_CK_GCLK25",
|
||||
"CLK_PMV_CLK0_0",
|
||||
"CLK_PMV_IMUX11_0",
|
||||
"CLK_FEED_EE4B3",
|
||||
"CLK_FEED_CK_BUFG_CASC24",
|
||||
"CLK_FEED_WW2END1",
|
||||
"CLK_PMV_LOGIC_OUTS23_0",
|
||||
"CLK_FEED_LH12",
|
||||
"CLK_FEED_LH7",
|
||||
"CLK_FEED_R_CK_GCLK14",
|
||||
"CLK_FEED_SW2A1",
|
||||
"CLK_PMV_IMUX6_0",
|
||||
"CLK_PMV_LOGIC_OUTS22_0",
|
||||
"CLK_FEED_NW4A1",
|
||||
"CLK_FEED_CK_GCLK27",
|
||||
"CLK_FEED_R_CK_BUFG_CASC18",
|
||||
"CLK_FEED_MONITOR_P",
|
||||
"CLK_FEED_SE4BEG1",
|
||||
"CLK_FEED_MONITOR_N",
|
||||
"CLK_PMV_IMUX47_0",
|
||||
"CLK_PMV_IMUX45_0",
|
||||
"CLK_FEED_CK_BUFG_CASC18",
|
||||
"CLK_PMV_IMUX36_0",
|
||||
"CLK_PMV_LOGIC_OUTS8_0",
|
||||
"CLK_FEED_CK_BUFG_CASC15",
|
||||
"CLK_PMV_LOGIC_OUTS19_0",
|
||||
"CLK_PMV_IMUX34_0",
|
||||
"CLK_FEED_SW2A0",
|
||||
"CLK_FEED_CK_BUFG_CASC0",
|
||||
"CLK_FEED_WR1END0",
|
||||
"CLK_FEED_CK_BUFG_CASC29",
|
||||
"CLK_PMV_IMUX21_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC20",
|
||||
"CLK_PMV_IMUX41_0",
|
||||
"CLK_PMV_IMUX27_0",
|
||||
"CLK_MTBF2_CLK",
|
||||
"CLK_PMV_IMUX25_0",
|
||||
"CLK_FEED_NE4BEG1",
|
||||
"CLK_PMV_FAN6_0",
|
||||
"CLK_FEED_WW4B0",
|
||||
"CLK_PMV_LOGIC_OUTS1_0",
|
||||
"CLK_PMV_IMUX28_0",
|
||||
"CLK_FEED_NE2A1",
|
||||
"CLK_PMV_FAN4_0",
|
||||
"CLK_FEED_SE4C0",
|
||||
"CLK_FEED_R_CK_GCLK22",
|
||||
"CLK_FEED_R_CK_GCLK8",
|
||||
"CLK_PMV_LOGIC_OUTS20_0",
|
||||
"CLK_PMV_IMUX19_0",
|
||||
"CLK_FEED_WW2END3",
|
||||
"CLK_FEED_R_CK_BUFG_CASC25",
|
||||
"CLK_FEED_EE2A1",
|
||||
"CLK_FEED_EE4B2",
|
||||
"CLK_FEED_CK_GCLK0",
|
||||
"CLK_FEED_WW4B2",
|
||||
"CLK_PMV_IMUX46_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC26",
|
||||
"CLK_FEED_R_CK_BUFG_CASC22",
|
||||
"CLK_FEED_SW2A2",
|
||||
"CLK_FEED_CK_GCLK8",
|
||||
"CLK_FEED_LH11",
|
||||
"CLK_FEED_NW2A0",
|
||||
"CLK_FEED_CK_BUFG_CASC22",
|
||||
"CLK_FEED_CK_GCLK18",
|
||||
"CLK_FEED_CK_GCLK26",
|
||||
"CLK_FEED_CK_BUFG_CASC20",
|
||||
"CLK_PMV_IMUX35_0",
|
||||
"CLK_FEED_CK_GCLK3",
|
||||
"CLK_PMV_IMUX18_0",
|
||||
"CLK_FEED_SE4C1",
|
||||
"CLK_FEED_NW4A2",
|
||||
"CLK_FEED_WW2END0",
|
||||
"CLK_FEED_CK_BUFG_CASC6",
|
||||
"CLK_FEED_SE2A0",
|
||||
"CLK_PMV_IMUX12_0",
|
||||
"CLK_FEED_WW4A0",
|
||||
"CLK_FEED_EE4BEG2",
|
||||
"CLK_FEED_CK_GCLK10",
|
||||
"CLK_FEED_R_CK_BUFG_CASC30",
|
||||
"CLK_FEED_SW4END3",
|
||||
"CLK_FEED_EL1BEG0",
|
||||
"CLK_PMV_IMUX17_0",
|
||||
"CLK_FEED_EE4BEG0",
|
||||
"CLK_FEED_WR1END3",
|
||||
"CLK_PMV_LOGIC_OUTS16_0",
|
||||
"CLK_FEED_CK_GCLK5",
|
||||
"CLK_FEED_CK_BUFG_CASC30",
|
||||
"CLK_FEED_SE4BEG0",
|
||||
"CLK_PMV_LOGIC_OUTS21_0",
|
||||
"CLK_FEED_EE4BEG1",
|
||||
"CLK_FEED_SE4BEG3",
|
||||
"CLK_FEED_CK_GCLK17",
|
||||
"CLK_FEED_R_CK_BUFG_CASC6",
|
||||
"CLK_FEED_SW4A1",
|
||||
"CLK_FEED_R_CK_GCLK23",
|
||||
"CLK_MTBF2_Q4B",
|
||||
"CLK_FEED_EE2BEG3",
|
||||
"CLK_FEED_R_CK_BUFG_CASC16",
|
||||
"CLK_FEED_R_CK_GCLK21",
|
||||
"CLK_FEED_R_CK_GCLK10",
|
||||
"CLK_FEED_NE4C3",
|
||||
"CLK_FEED_R_CK_BUFG_CASC21",
|
||||
"CLK_PMV_LOGIC_OUTS4_0",
|
||||
"CLK_PMV_IMUX14_0",
|
||||
"CLK_FEED_NW4A0",
|
||||
"CLK_PMV_BYP5_0",
|
||||
"CLK_FEED_SE4BEG2",
|
||||
"CLK_FEED_R_CK_BUFG_CASC31",
|
||||
"CLK_FEED_CK_BUFG_CASC11",
|
||||
"CLK_FEED_R_CK_GCLK20",
|
||||
"CLK_FEED_SW4END0",
|
||||
"CLK_PMV_LOGIC_OUTS7_0",
|
||||
"CLK_PMV_IMUX32_0",
|
||||
"CLK_FEED_CK_BUFG_CASC26",
|
||||
"CLK_MTBF2_Q5B",
|
||||
"CLK_PMV_IMUX9_0",
|
||||
"CLK_MTBF2_Q6B",
|
||||
"CLK_FEED_LH5",
|
||||
"CLK_PMV_IMUX37_0",
|
||||
"CLK_PMV_IMUX7_0",
|
||||
"CLK_FEED_R_CK_GCLK31",
|
||||
"CLK_FEED_WW4B1",
|
||||
"CLK_FEED_CK_GCLK24",
|
||||
"CLK_FEED_WW4END1",
|
||||
"CLK_FEED_R_CK_GCLK17",
|
||||
"CLK_FEED_R_CK_GCLK7",
|
||||
"CLK_FEED_CK_BUFG_CASC28",
|
||||
"CLK_FEED_EE2A3",
|
||||
"CLK_FEED_CK_GCLK14",
|
||||
"CLK_FEED_CK_GCLK13",
|
||||
"CLK_FEED_CK_BUFG_CASC1",
|
||||
"CLK_FEED_R_CK_BUFG_CASC9",
|
||||
"CLK_FEED_LH8",
|
||||
"CLK_FEED_EE4C2",
|
||||
"CLK_FEED_WW4B3",
|
||||
"CLK_FEED_EE4A3",
|
||||
"CLK_MTBF2_EN",
|
||||
"CLK_FEED_NW2A2",
|
||||
"CLK_FEED_CK_BUFG_CASC10",
|
||||
"CLK_FEED_WL1END1",
|
||||
"CLK_PMV_BYP2_0",
|
||||
"CLK_FEED_SE4C3",
|
||||
"CLK_FEED_WL1END2",
|
||||
"CLK_PMV_LOGIC_OUTS13_0",
|
||||
"CLK_FEED_LH3",
|
||||
"CLK_MTBF2_DIN",
|
||||
"CLK_PMV_LOGIC_OUTS0_0",
|
||||
"CLK_PMV_IMUX39_0",
|
||||
"CLK_FEED_R_CK_GCLK13",
|
||||
"CLK_FEED_NW2A3",
|
||||
"CLK_FEED_LH4",
|
||||
"CLK_FEED_EE4B0",
|
||||
"CLK_PMV_IMUX29_0",
|
||||
"CLK_FEED_SE4C2",
|
||||
"CLK_FEED_SW2A3",
|
||||
"CLK_FEED_EE4BEG3",
|
||||
"CLK_FEED_CK_GCLK15",
|
||||
"CLK_FEED_R_CK_GCLK1",
|
||||
"CLK_FEED_R_CK_GCLK15",
|
||||
"CLK_PMV_IMUX38_0",
|
||||
"CLK_FEED_R_CK_GCLK12",
|
||||
"CLK_FEED_R_CK_GCLK28",
|
||||
"CLK_FEED_CK_BUFG_CASC17",
|
||||
"CLK_PMV_LOGIC_OUTS10_0",
|
||||
"CLK_PMV_CLK1_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC13",
|
||||
"CLK_PMV_IMUX2_0",
|
||||
"CLK_FEED_NW4END2",
|
||||
"CLK_FEED_WW4END2",
|
||||
"CLK_PMV_LOGIC_OUTS11_0",
|
||||
"CLK_PMV_IMUX3_0",
|
||||
"CLK_FEED_NE2A3",
|
||||
"CLK_FEED_NW2A3",
|
||||
"CLK_FEED_CK_BUFG_CASC10",
|
||||
"CLK_FEED_R_CK_BUFG_CASC9",
|
||||
"CLK_FEED_SW4A0",
|
||||
"CLK_FEED_SE4BEG1",
|
||||
"CLK_PMV_FAN7_0",
|
||||
"CLK_FEED_SE2A2",
|
||||
"CLK_FEED_R_CK_BUFG_CASC27",
|
||||
"CLK_FEED_NE2A0",
|
||||
"CLK_FEED_SW4A3",
|
||||
"CLK_MTBF2_EN",
|
||||
"CLK_FEED_NW2A0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC19",
|
||||
"CLK_PMV_BYP5_0",
|
||||
"CLK_FEED_NE4BEG3",
|
||||
"CLK_FEED_SE4BEG3",
|
||||
"CLK_PMV_IMUX5_0",
|
||||
"CLK_FEED_CK_BUFG_CASC29",
|
||||
"CLK_PMV_BYP6_0",
|
||||
"CLK_FEED_CK_GCLK26",
|
||||
"CLK_FEED_R_CK_GCLK5",
|
||||
"CLK_FEED_R_CK_BUFG_CASC12",
|
||||
"CLK_FEED_LH10",
|
||||
"CLK_FEED_SE4C3",
|
||||
"CLK_FEED_R_CK_BUFG_CASC14",
|
||||
"CLK_FEED_R_CK_GCLK14",
|
||||
"CLK_PMV_FAN1_0",
|
||||
"CLK_FEED_NW2A2",
|
||||
"CLK_FEED_NW4END2",
|
||||
"CLK_PMV_IMUX32_0",
|
||||
"CLK_MTBF2_DIN",
|
||||
"CLK_PMV_BYP3_0",
|
||||
"CLK_PMV_LOGIC_OUTS1_0",
|
||||
"CLK_FEED_R_CK_GCLK17",
|
||||
"CLK_FEED_R_CK_BUFG_CASC17",
|
||||
"CLK_FEED_R_CK_GCLK18",
|
||||
"CLK_FEED_R_CK_BUFG_CASC24",
|
||||
"CLK_FEED_CK_BUFG_CASC4",
|
||||
"CLK_PMV_LOGIC_OUTS13_0",
|
||||
"CLK_FEED_CK_BUFG_CASC18",
|
||||
"CLK_FEED_LH9",
|
||||
"CLK_FEED_NW4END1",
|
||||
"CLK_FEED_LH4",
|
||||
"CLK_PMV_IMUX37_0",
|
||||
"CLK_PMV_LOGIC_OUTS15_0",
|
||||
"CLK_FEED_NW4A2",
|
||||
"CLK_FEED_EE2BEG1",
|
||||
"CLK_PMV_IMUX2_0",
|
||||
"CLK_FEED_EE4BEG1",
|
||||
"CLK_FEED_CK_GCLK30",
|
||||
"CLK_PMV_IMUX8_0",
|
||||
"CLK_FEED_CK_GCLK22",
|
||||
"CLK_FEED_CK_GCLK16",
|
||||
"CLK_PMV_IMUX20_0",
|
||||
"CLK_FEED_R_CK_GCLK2",
|
||||
"CLK_PMV_FAN0_0",
|
||||
"CLK_FEED_LH1",
|
||||
"CLK_FEED_R_CK_GCLK23",
|
||||
"CLK_PMV_LOGIC_OUTS7_0",
|
||||
"CLK_PMV_IMUX31_0",
|
||||
"CLK_FEED_LH5",
|
||||
"CLK_FEED_EE2A0",
|
||||
"CLK_FEED_WW4B0",
|
||||
"CLK_PMV_BYP2_0",
|
||||
"CLK_FEED_SE4BEG2",
|
||||
"CLK_FEED_NW4END3",
|
||||
"CLK_FEED_NE4BEG2",
|
||||
"CLK_PMV_LOGIC_OUTS14_0",
|
||||
"CLK_PMV_CLK1_0",
|
||||
"CLK_FEED_NE4C3",
|
||||
"CLK_FEED_R_CK_GCLK25",
|
||||
"CLK_FEED_EE2BEG2",
|
||||
"CLK_PMV_IMUX43_0",
|
||||
"CLK_FEED_WL1END2",
|
||||
"CLK_FEED_CK_GCLK0",
|
||||
"CLK_PMV_CLK0_0",
|
||||
"CLK_FEED_R_CK_GCLK10",
|
||||
"CLK_PMV_LOGIC_OUTS0_0",
|
||||
"CLK_PMV_IMUX47_0",
|
||||
"CLK_FEED_CK_GCLK20",
|
||||
"CLK_FEED_ER1BEG3",
|
||||
"CLK_FEED_WW4A1",
|
||||
"CLK_FEED_CK_BUFG_CASC17",
|
||||
"CLK_FEED_CK_GCLK23",
|
||||
"CLK_FEED_LH2",
|
||||
"CLK_MTBF2_Q3B",
|
||||
"CLK_FEED_R_CK_GCLK3",
|
||||
"CLK_FEED_EE4B1",
|
||||
"CLK_FEED_R_CK_GCLK7",
|
||||
"CLK_FEED_LH8",
|
||||
"CLK_FEED_LH3",
|
||||
"CLK_FEED_NW2A1",
|
||||
"CLK_FEED_LH11",
|
||||
"CLK_FEED_R_CK_BUFG_CASC29",
|
||||
"CLK_FEED_CK_BUFG_CASC5",
|
||||
"CLK_PMV_IMUX35_0",
|
||||
"CLK_PMV_IMUX0_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC23",
|
||||
"CLK_FEED_CK_GCLK3",
|
||||
"CLK_FEED_WL1END3",
|
||||
"CLK_FEED_R_CK_BUFG_CASC15",
|
||||
"CLK_FEED_ER1BEG2",
|
||||
"CLK_FEED_CK_BUFG_CASC30",
|
||||
"CLK_PMV_LOGIC_OUTS2_0",
|
||||
"CLK_PMV_IMUX17_0",
|
||||
"CLK_FEED_EL1BEG3",
|
||||
"CLK_FEED_R_CK_GCLK16",
|
||||
"CLK_PMV_IMUX36_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC7",
|
||||
"CLK_MTBF2_Q6B",
|
||||
"CLK_FEED_EE4BEG2",
|
||||
"CLK_PMV_FAN5_0",
|
||||
"CLK_FEED_CK_GCLK19",
|
||||
"CLK_PMV_IMUX38_0",
|
||||
"CLK_PMV_IMUX10_0",
|
||||
"CLK_FEED_CK_GCLK11",
|
||||
"CLK_FEED_CK_BUFG_CASC21",
|
||||
"CLK_FEED_EE2BEG3",
|
||||
"CLK_PMV_LOGIC_OUTS10_0",
|
||||
"CLK_FEED_SW4END0",
|
||||
"CLK_PMV_LOGIC_OUTS19_0",
|
||||
"CLK_FEED_R_CK_GCLK1",
|
||||
"CLK_FEED_WL1END1",
|
||||
"CLK_FEED_R_CK_GCLK13",
|
||||
"CLK_FEED_EE4B2",
|
||||
"CLK_FEED_R_CK_BUFG_CASC4",
|
||||
"CLK_MTBF2_Q4B",
|
||||
"CLK_FEED_R_CK_GCLK28",
|
||||
"CLK_FEED_CK_GCLK4",
|
||||
"CLK_FEED_R_CK_BUFG_CASC8",
|
||||
"CLK_PMV_IMUX15_0",
|
||||
"CLK_PMV_IMUX19_0",
|
||||
"CLK_PMV_IMUX29_0",
|
||||
"CLK_FEED_CK_GCLK6",
|
||||
"CLK_FEED_EE4C3",
|
||||
"CLK_PMV_LOGIC_OUTS22_0",
|
||||
"CLK_FEED_NW4A0",
|
||||
"CLK_MTBF2_Q7B",
|
||||
"CLK_FEED_WW2END0",
|
||||
"CLK_FEED_SE2A0",
|
||||
"CLK_FEED_LH6",
|
||||
"CLK_FEED_MONITOR_P",
|
||||
"CLK_FEED_SE4C2",
|
||||
"CLK_PMV_LOGIC_OUTS6_0",
|
||||
"CLK_PMV_BYP0_0",
|
||||
"CLK_FEED_WW2END3",
|
||||
"CLK_FEED_R_CK_BUFG_CASC18",
|
||||
"CLK_FEED_WW4B2",
|
||||
"CLK_FEED_R_CK_GCLK27",
|
||||
"CLK_MTBF2_Q0B",
|
||||
"CLK_PMV_FAN4_0",
|
||||
"CLK_FEED_WR1END1",
|
||||
"CLK_FEED_R_CK_BUFG_CASC28",
|
||||
"CLK_FEED_WW4END0",
|
||||
"CLK_FEED_CK_BUFG_CASC12",
|
||||
"CLK_FEED_SW2A3",
|
||||
"CLK_FEED_WW4C0",
|
||||
"CLK_FEED_SW4END1",
|
||||
"CLK_FEED_LH12",
|
||||
"CLK_FEED_CK_BUFG_CASC7",
|
||||
"CLK_PMV_IMUX16_0",
|
||||
"CLK_FEED_R_CK_GCLK9",
|
||||
"CLK_FEED_CK_BUFG_CASC2",
|
||||
"CLK_PMV_IMUX4_0",
|
||||
"CLK_FEED_CK_BUFG_CASC9",
|
||||
"CLK_MTBF2_CLK",
|
||||
"CLK_FEED_NW4END0",
|
||||
"CLK_FEED_CK_BUFG_CASC28",
|
||||
"CLK_FEED_R_CK_BUFG_CASC5",
|
||||
"CLK_PMV_IMUX40_0",
|
||||
"CLK_PMV_LOGIC_OUTS16_0",
|
||||
"CLK_FEED_R_CK_GCLK30",
|
||||
"CLK_FEED_R_CK_GCLK21",
|
||||
"CLK_FEED_R_CK_BUFG_CASC10",
|
||||
"CLK_PMV_IMUX34_0",
|
||||
"CLK_FEED_EL1BEG1",
|
||||
"CLK_FEED_CK_BUFG_CASC20",
|
||||
"CLK_FEED_NE4C0",
|
||||
"CLK_FEED_WW4END1",
|
||||
"CLK_FEED_CK_BUFG_CASC25",
|
||||
"CLK_MTBF2_Q5B",
|
||||
"CLK_PMV_LOGIC_OUTS3_0",
|
||||
"CLK_FEED_ER1BEG1",
|
||||
"CLK_PMV_IMUX25_0",
|
||||
"CLK_PMV_LOGIC_OUTS12_0",
|
||||
"CLK_FEED_CK_BUFG_CASC19",
|
||||
"CLK_FEED_EE4A0",
|
||||
"CLK_FEED_SW2A0",
|
||||
"CLK_FEED_CK_BUFG_CASC22",
|
||||
"CLK_FEED_NW4A3",
|
||||
"CLK_PMV_BYP7_0",
|
||||
"CLK_PMV_FAN6_0",
|
||||
"CLK_FEED_CK_GCLK25",
|
||||
"CLK_PMV_LOGIC_OUTS5_0",
|
||||
"CLK_PMV_LOGIC_OUTS9_0",
|
||||
"CLK_FEED_CK_GCLK5",
|
||||
"CLK_FEED_WR1END0",
|
||||
"CLK_PMV_IMUX42_0",
|
||||
"CLK_FEED_SW4A2",
|
||||
"CLK_FEED_EE4C0",
|
||||
"CLK_PMV_LOGIC_OUTS21_0",
|
||||
"CLK_FEED_CK_BUFG_CASC11",
|
||||
"CLK_FEED_EL1BEG2",
|
||||
"CLK_FEED_WR1END3",
|
||||
"CLK_FEED_CK_BUFG_CASC3",
|
||||
"CLK_FEED_CK_GCLK15",
|
||||
"CLK_FEED_MONITOR_N",
|
||||
"CLK_PMV_IMUX3_0",
|
||||
"CLK_PMV_LOGIC_OUTS4_0",
|
||||
"CLK_PMV_BYP1_0",
|
||||
"CLK_FEED_NE4C2",
|
||||
"CLK_FEED_CK_BUFG_CASC1",
|
||||
"CLK_FEED_EE2A3",
|
||||
"CLK_FEED_WW2A3",
|
||||
"CLK_FEED_WW2END1",
|
||||
"CLK_FEED_R_CK_GCLK12",
|
||||
"CLK_FEED_CK_GCLK18",
|
||||
"CLK_MTBF2_Q2B",
|
||||
"CLK_FEED_WW2END2",
|
||||
"CLK_PMV_IMUX41_0",
|
||||
"CLK_FEED_SW4A1",
|
||||
"CLK_FEED_SE4C1",
|
||||
"CLK_PMV_IMUX26_0",
|
||||
"CLK_FEED_CK_BUFG_CASC14",
|
||||
"CLK_FEED_EE4B0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC6",
|
||||
"CLK_FEED_R_CK_BUFG_CASC31",
|
||||
"CLK_FEED_R_CK_GCLK0",
|
||||
"CLK_PMV_IMUX46_0",
|
||||
"CLK_FEED_CK_GCLK10",
|
||||
"CLK_FEED_CK_GCLK27",
|
||||
"CLK_FEED_WW4A2",
|
||||
"CLK_PMV_LOGIC_OUTS17_0",
|
||||
"CLK_FEED_R_CK_GCLK29",
|
||||
"CLK_FEED_R_CK_BUFG_CASC20",
|
||||
"CLK_FEED_R_CK_GCLK15",
|
||||
"CLK_FEED_R_CK_GCLK31",
|
||||
"CLK_FEED_CK_GCLK29",
|
||||
"CLK_PMV_LOGIC_OUTS11_0",
|
||||
"CLK_FEED_R_CK_GCLK11",
|
||||
"CLK_FEED_CK_BUFG_CASC27",
|
||||
"CLK_FEED_CK_BUFG_CASC16",
|
||||
"CLK_FEED_CK_BUFG_CASC15",
|
||||
"CLK_FEED_R_CK_BUFG_CASC1",
|
||||
"CLK_PMV_IMUX33_0",
|
||||
"CLK_FEED_CK_BUFG_CASC26",
|
||||
"CLK_FEED_R_CK_BUFG_CASC3",
|
||||
"CLK_PMV_IMUX42_0"
|
||||
"CLK_PMV_IMUX21_0",
|
||||
"CLK_FEED_CK_GCLK21",
|
||||
"CLK_FEED_NE2A2",
|
||||
"CLK_FEED_WW2A0",
|
||||
"CLK_PMV_IMUX11_0",
|
||||
"CLK_PMV_IMUX24_0",
|
||||
"CLK_PMV_LOGIC_OUTS20_0",
|
||||
"CLK_PMV_IMUX1_0",
|
||||
"CLK_PMV_FAN2_0",
|
||||
"CLK_FEED_EE2A2",
|
||||
"CLK_PMV_IMUX27_0",
|
||||
"CLK_FEED_LH7",
|
||||
"CLK_FEED_R_CK_BUFG_CASC21",
|
||||
"CLK_FEED_EE4A1",
|
||||
"CLK_FEED_CK_GCLK2",
|
||||
"CLK_FEED_WW4B1",
|
||||
"CLK_FEED_R_CK_BUFG_CASC0",
|
||||
"CLK_FEED_NW4A1",
|
||||
"CLK_PMV_LOGIC_OUTS23_0",
|
||||
"CLK_FEED_SW4END3",
|
||||
"CLK_FEED_R_CK_GCLK24",
|
||||
"CLK_FEED_EE4A2",
|
||||
"CLK_FEED_CK_GCLK28",
|
||||
"CLK_FEED_WW4END2",
|
||||
"CLK_FEED_EL1BEG0",
|
||||
"CLK_PMV_LOGIC_OUTS18_0",
|
||||
"CLK_FEED_CK_BUFG_CASC0",
|
||||
"CLK_FEED_CK_BUFG_CASC31",
|
||||
"CLK_FEED_SE4BEG0",
|
||||
"CLK_FEED_WW4C2",
|
||||
"CLK_FEED_WR1END2",
|
||||
"CLK_FEED_CK_BUFG_CASC6",
|
||||
"CLK_FEED_CK_GCLK24",
|
||||
"CLK_FEED_ER1BEG0",
|
||||
"CLK_PMV_IMUX12_0",
|
||||
"CLK_FEED_WW4C1",
|
||||
"CLK_FEED_CK_GCLK8",
|
||||
"CLK_FEED_SW4END2",
|
||||
"CLK_PMV_IMUX22_0",
|
||||
"CLK_PMV_BYP4_0",
|
||||
"CLK_FEED_R_CK_GCLK20",
|
||||
"CLK_FEED_SE2A3",
|
||||
"CLK_FEED_EE2A1",
|
||||
"CLK_FEED_R_CK_GCLK4",
|
||||
"CLK_FEED_EE4A3",
|
||||
"CLK_FEED_R_CK_BUFG_CASC13",
|
||||
"CLK_FEED_R_CK_GCLK19",
|
||||
"CLK_PMV_IMUX45_0",
|
||||
"CLK_FEED_CK_BUFG_CASC8",
|
||||
"CLK_FEED_CK_GCLK14",
|
||||
"CLK_FEED_WW2A1",
|
||||
"CLK_PMV_IMUX9_0",
|
||||
"CLK_PMV_IMUX7_0",
|
||||
"CLK_PMV_IMUX39_0",
|
||||
"CLK_FEED_CK_GCLK17",
|
||||
"CLK_PMV_CTRL0_0",
|
||||
"CLK_PMV_IMUX23_0",
|
||||
"CLK_PMV_IMUX18_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC22",
|
||||
"CLK_FEED_EE4B3",
|
||||
"CLK_PMV_IMUX14_0",
|
||||
"CLK_FEED_EE4C1",
|
||||
"CLK_FEED_SW2A2",
|
||||
"CLK_FEED_NE4C1",
|
||||
"CLK_FEED_R_CK_BUFG_CASC26",
|
||||
"CLK_FEED_SE2A1",
|
||||
"CLK_FEED_CK_GCLK7",
|
||||
"CLK_MTBF2_Q1B",
|
||||
"CLK_FEED_CK_GCLK1",
|
||||
"CLK_FEED_CK_GCLK9",
|
||||
"CLK_FEED_WW4C3",
|
||||
"CLK_FEED_R_CK_GCLK22",
|
||||
"CLK_FEED_CK_BUFG_CASC23",
|
||||
"CLK_FEED_EE4BEG0",
|
||||
"CLK_FEED_CK_BUFG_CASC24",
|
||||
"CLK_FEED_WW4A0",
|
||||
"CLK_PMV_IMUX44_0",
|
||||
"CLK_MTBF2_RESET",
|
||||
"CLK_FEED_WW2A2",
|
||||
"CLK_FEED_NE2A1",
|
||||
"CLK_FEED_CK_GCLK31",
|
||||
"CLK_PMV_CTRL1_0",
|
||||
"CLK_PMV_IMUX13_0",
|
||||
"CLK_FEED_NE4BEG1",
|
||||
"CLK_FEED_R_CK_GCLK8",
|
||||
"CLK_PMV_LOGIC_OUTS8_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC16",
|
||||
"CLK_FEED_EE4C2",
|
||||
"CLK_PMV_IMUX6_0",
|
||||
"CLK_FEED_EE4BEG3",
|
||||
"CLK_PMV_IMUX30_0",
|
||||
"CLK_FEED_CK_BUFG_CASC13",
|
||||
"CLK_FEED_WW4B3",
|
||||
"CLK_FEED_R_CK_GCLK26",
|
||||
"CLK_PMV_IMUX28_0",
|
||||
"CLK_FEED_NE4BEG0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC30",
|
||||
"CLK_FEED_SE4C0",
|
||||
"CLK_FEED_CK_GCLK13",
|
||||
"CLK_FEED_WW4A3",
|
||||
"CLK_FEED_EE2BEG0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC2",
|
||||
"CLK_FEED_R_CK_BUFG_CASC25",
|
||||
"CLK_FEED_R_CK_BUFG_CASC11",
|
||||
"CLK_FEED_SW2A1"
|
||||
],
|
||||
"tile_type": "CLK_MTBF2",
|
||||
"sites": []
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,377 +1,377 @@
|
|||
{
|
||||
"pips": {},
|
||||
"wires": [
|
||||
"CLK_PMV_IMUX40_0",
|
||||
"CLK_FEED_CK_GCLK31",
|
||||
"CLK_FEED_NE2A2",
|
||||
"CLK_PMV_IMUX43_0",
|
||||
"CLK_FEED_CK_BUFG_CASC9",
|
||||
"CLK_FEED_R_CK_BUFG_CASC23",
|
||||
"CLK_PMV_LOGIC_OUTS17_0",
|
||||
"CLK_FEED_NW4END3",
|
||||
"CLK_FEED_R_CK_GCLK0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC12",
|
||||
"CLK_FEED_EE4C3",
|
||||
"CLK_PMV_LOGIC_OUTS5_0",
|
||||
"CLK_PMV_BYP4_0",
|
||||
"CLK_FEED_CK_BUFG_CASC31",
|
||||
"CLK_FEED_R_CK_GCLK24",
|
||||
"CLK_PMV_LOGIC_OUTS18_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC29",
|
||||
"CLK_FEED_R_CK_BUFG_CASC8",
|
||||
"CLK_FEED_WW4C1",
|
||||
"CLK_FEED_SE2A3",
|
||||
"CLK_PMV_FAN7_0",
|
||||
"CLK_FEED_R_CK_GCLK19",
|
||||
"CLK_FEED_WW4A1",
|
||||
"CLK_FEED_R_CK_BUFG_CASC10",
|
||||
"CLK_PMV_FAN2_0",
|
||||
"CLK_PMV_BYP7_0",
|
||||
"CLK_FEED_EE4A2",
|
||||
"CLK_FEED_R_CK_BUFG_CASC7",
|
||||
"CLK_FEED_R_CK_BUFG_CASC2",
|
||||
"CLK_FEED_R_CK_GCLK9",
|
||||
"CLK_PMV_IMUX10_0",
|
||||
"CLK_FEED_CK_BUFG_CASC19",
|
||||
"CLK_PMV_IMUX5_0",
|
||||
"CLK_FEED_EE2BEG2",
|
||||
"CLK_FEED_EE2A2",
|
||||
"CLK_FEED_R_CK_BUFG_CASC5",
|
||||
"CLK_FEED_CK_BUFG_CASC4",
|
||||
"CLK_FEED_CK_GCLK19",
|
||||
"CLK_FEED_R_CK_BUFG_CASC17",
|
||||
"CLK_FEED_SW4A3",
|
||||
"CLK_PMV_IMUX23_0",
|
||||
"CLK_FEED_WW4C3",
|
||||
"CLK_FEED_LH10",
|
||||
"CLK_FEED_R_CK_GCLK29",
|
||||
"CLK_FEED_CK_GCLK11",
|
||||
"CLK_FEED_CK_GCLK7",
|
||||
"CLK_FEED_R_CK_BUFG_CASC27",
|
||||
"CLK_FEED_R_CK_BUFG_CASC11",
|
||||
"CLK_FEED_ER1BEG2",
|
||||
"CLK_FEED_EL1BEG3",
|
||||
"CLK_FEED_CK_GCLK1",
|
||||
"CLK_FEED_NE4C2",
|
||||
"CLK_FEED_CK_BUFG_CASC21",
|
||||
"CLK_FEED_EE4C1",
|
||||
"CLK_FEED_CK_BUFG_CASC12",
|
||||
"CLK_FEED_R_CK_GCLK2",
|
||||
"CLK_FEED_SE2A1",
|
||||
"CLK_FEED_CK_BUFG_CASC14",
|
||||
"CLK_FEED_ER1BEG3",
|
||||
"CLK_FEED_WW4C0",
|
||||
"CLK_FEED_CK_BUFG_CASC23",
|
||||
"CLK_FEED_CK_GCLK4",
|
||||
"CLK_FEED_ER1BEG1",
|
||||
"CLK_PMV_BYP6_0",
|
||||
"CLK_FEED_NW4A3",
|
||||
"CLK_FEED_R_CK_BUFG_CASC0",
|
||||
"CLK_PMV2_A0",
|
||||
"CLK_PMV_FAN0_0",
|
||||
"CLK_FEED_ER1BEG0",
|
||||
"CLK_PMV_IMUX31_0",
|
||||
"CLK_PMV_LOGIC_OUTS14_0",
|
||||
"CLK_FEED_CK_GCLK16",
|
||||
"CLK_FEED_CK_GCLK29",
|
||||
"CLK_FEED_R_CK_GCLK26",
|
||||
"CLK_PMV_LOGIC_OUTS3_0",
|
||||
"CLK_FEED_WW4C2",
|
||||
"CLK_FEED_R_CK_BUFG_CASC4",
|
||||
"CLK_FEED_R_CK_GCLK16",
|
||||
"CLK_FEED_CK_GCLK23",
|
||||
"CLK_FEED_EE4A0",
|
||||
"CLK_FEED_WR1END1",
|
||||
"CLK_FEED_NE4C0",
|
||||
"CLK_FEED_CK_BUFG_CASC16",
|
||||
"CLK_PMV_FAN1_0",
|
||||
"CLK_FEED_R_CK_GCLK5",
|
||||
"CLK_FEED_R_CK_BUFG_CASC19",
|
||||
"CLK_FEED_CK_GCLK6",
|
||||
"CLK_FEED_EE4B1",
|
||||
"CLK_FEED_CK_GCLK25",
|
||||
"CLK_FEED_EE4A1",
|
||||
"CLK_FEED_CK_GCLK9",
|
||||
"CLK_FEED_SW4END1",
|
||||
"CLK_FEED_SW4END2",
|
||||
"CLK_PMV_LOGIC_OUTS12_0",
|
||||
"CLK_FEED_CK_GCLK2",
|
||||
"CLK_FEED_WW2A3",
|
||||
"CLK_FEED_NE2A0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC14",
|
||||
"CLK_PMV_IMUX44_0",
|
||||
"CLK_FEED_CK_BUFG_CASC7",
|
||||
"CLK_FEED_CK_BUFG_CASC27",
|
||||
"CLK_PMV_IMUX8_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC1",
|
||||
"CLK_FEED_WW4A3",
|
||||
"CLK_PMV_IMUX1_0",
|
||||
"CLK_FEED_SW4A0",
|
||||
"CLK_PMV_LOGIC_OUTS2_0",
|
||||
"CLK_FEED_EE4C0",
|
||||
"CLK_PMV2_O",
|
||||
"CLK_FEED_CK_BUFG_CASC5",
|
||||
"CLK_FEED_CK_BUFG_CASC13",
|
||||
"CLK_FEED_CK_GCLK21",
|
||||
"CLK_PMV_FAN3_0",
|
||||
"CLK_FEED_CK_GCLK28",
|
||||
"CLK_PMV_IMUX15_0",
|
||||
"CLK_PMV_IMUX26_0",
|
||||
"CLK_PMV_CTRL1_0",
|
||||
"CLK_PMV_FAN5_0",
|
||||
"CLK_FEED_NE4BEG2",
|
||||
"CLK_FEED_WW2A2",
|
||||
"CLK_FEED_WR1END2",
|
||||
"CLK_PMV_CTRL0_0",
|
||||
"CLK_FEED_EL1BEG2",
|
||||
"CLK_PMV_IMUX30_0",
|
||||
"CLK_FEED_LH1",
|
||||
"CLK_FEED_CK_BUFG_CASC8",
|
||||
"CLK_FEED_R_CK_GCLK30",
|
||||
"CLK_PMV_LOGIC_OUTS9_0",
|
||||
"CLK_FEED_WW2A0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC15",
|
||||
"CLK_FEED_R_CK_GCLK3",
|
||||
"CLK_FEED_WW4A2",
|
||||
"CLK_PMV_IMUX13_0",
|
||||
"CLK_FEED_EL1BEG1",
|
||||
"CLK_FEED_WL1END0",
|
||||
"CLK_FEED_SE2A2",
|
||||
"CLK_PMV2_A2",
|
||||
"CLK_PMV_FAN3_0",
|
||||
"CLK_FEED_WW4END3",
|
||||
"CLK_FEED_R_CK_BUFG_CASC28",
|
||||
"CLK_FEED_NW4END0",
|
||||
"CLK_FEED_SW4A2",
|
||||
"CLK_PMV_IMUX22_0",
|
||||
"CLK_PMV_IMUX4_0",
|
||||
"CLK_PMV_BYP3_0",
|
||||
"CLK_FEED_NW4END1",
|
||||
"CLK_PMV_LOGIC_OUTS15_0",
|
||||
"CLK_FEED_WW2A1",
|
||||
"CLK_FEED_EE2A0",
|
||||
"CLK_FEED_EE2BEG0",
|
||||
"CLK_PMV_IMUX20_0",
|
||||
"CLK_PMV_BYP0_0",
|
||||
"CLK_PMV2_ODIV2",
|
||||
"CLK_FEED_NE4C1",
|
||||
"CLK_FEED_CK_GCLK20",
|
||||
"CLK_FEED_R_CK_GCLK11",
|
||||
"CLK_FEED_LH6",
|
||||
"CLK_FEED_NE4BEG0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC24",
|
||||
"CLK_FEED_NW2A1",
|
||||
"CLK_FEED_CK_GCLK12",
|
||||
"CLK_FEED_CK_BUFG_CASC2",
|
||||
"CLK_FEED_CK_GCLK22",
|
||||
"CLK_FEED_WL1END3",
|
||||
"CLK_FEED_R_CK_GCLK4",
|
||||
"CLK_PMV_IMUX33_0",
|
||||
"CLK_PMV_IMUX0_0",
|
||||
"CLK_FEED_LH9",
|
||||
"CLK_FEED_R_CK_GCLK6",
|
||||
"CLK_FEED_CK_GCLK30",
|
||||
"CLK_PMV_IMUX24_0",
|
||||
"CLK_FEED_NE4BEG3",
|
||||
"CLK_PMV_BYP1_0",
|
||||
"CLK_FEED_R_CK_GCLK27",
|
||||
"CLK_FEED_CK_BUFG_CASC3",
|
||||
"CLK_FEED_R_CK_GCLK18",
|
||||
"CLK_FEED_WW2END2",
|
||||
"CLK_FEED_EE2BEG1",
|
||||
"CLK_FEED_WW4END0",
|
||||
"CLK_FEED_CK_BUFG_CASC25",
|
||||
"CLK_PMV_IMUX16_0",
|
||||
"CLK_FEED_LH2",
|
||||
"CLK_PMV_LOGIC_OUTS6_0",
|
||||
"CLK_FEED_R_CK_GCLK25",
|
||||
"CLK_PMV_CLK0_0",
|
||||
"CLK_PMV_IMUX11_0",
|
||||
"CLK_FEED_EE4B3",
|
||||
"CLK_FEED_CK_BUFG_CASC24",
|
||||
"CLK_FEED_WW2END1",
|
||||
"CLK_PMV_LOGIC_OUTS23_0",
|
||||
"CLK_FEED_LH12",
|
||||
"CLK_FEED_LH7",
|
||||
"CLK_FEED_R_CK_GCLK14",
|
||||
"CLK_FEED_SW2A1",
|
||||
"CLK_PMV_IMUX6_0",
|
||||
"CLK_PMV_LOGIC_OUTS22_0",
|
||||
"CLK_FEED_NW4A1",
|
||||
"CLK_FEED_CK_GCLK27",
|
||||
"CLK_FEED_R_CK_BUFG_CASC18",
|
||||
"CLK_FEED_MONITOR_P",
|
||||
"CLK_FEED_SE4BEG1",
|
||||
"CLK_FEED_MONITOR_N",
|
||||
"CLK_PMV_IMUX47_0",
|
||||
"CLK_PMV_IMUX45_0",
|
||||
"CLK_FEED_CK_BUFG_CASC18",
|
||||
"CLK_PMV_IMUX36_0",
|
||||
"CLK_PMV_LOGIC_OUTS8_0",
|
||||
"CLK_FEED_CK_BUFG_CASC15",
|
||||
"CLK_PMV_LOGIC_OUTS19_0",
|
||||
"CLK_PMV_IMUX34_0",
|
||||
"CLK_FEED_SW2A0",
|
||||
"CLK_FEED_CK_BUFG_CASC0",
|
||||
"CLK_FEED_WR1END0",
|
||||
"CLK_FEED_CK_BUFG_CASC29",
|
||||
"CLK_PMV_IMUX21_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC20",
|
||||
"CLK_PMV_IMUX41_0",
|
||||
"CLK_PMV_IMUX27_0",
|
||||
"CLK_PMV_IMUX25_0",
|
||||
"CLK_FEED_NE4BEG1",
|
||||
"CLK_PMV_FAN6_0",
|
||||
"CLK_FEED_WW4B0",
|
||||
"CLK_PMV_LOGIC_OUTS1_0",
|
||||
"CLK_PMV_IMUX28_0",
|
||||
"CLK_FEED_NE2A1",
|
||||
"CLK_PMV_FAN4_0",
|
||||
"CLK_FEED_SE4C0",
|
||||
"CLK_FEED_R_CK_GCLK22",
|
||||
"CLK_FEED_R_CK_GCLK8",
|
||||
"CLK_PMV_LOGIC_OUTS20_0",
|
||||
"CLK_PMV_IMUX19_0",
|
||||
"CLK_FEED_WW2END3",
|
||||
"CLK_FEED_R_CK_BUFG_CASC25",
|
||||
"CLK_FEED_EE2A1",
|
||||
"CLK_FEED_EE4B2",
|
||||
"CLK_FEED_CK_GCLK0",
|
||||
"CLK_FEED_WW4B2",
|
||||
"CLK_PMV_IMUX46_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC26",
|
||||
"CLK_FEED_R_CK_BUFG_CASC22",
|
||||
"CLK_FEED_SW2A2",
|
||||
"CLK_FEED_CK_GCLK8",
|
||||
"CLK_FEED_LH11",
|
||||
"CLK_FEED_NW2A0",
|
||||
"CLK_FEED_CK_BUFG_CASC22",
|
||||
"CLK_FEED_CK_GCLK18",
|
||||
"CLK_FEED_CK_GCLK26",
|
||||
"CLK_FEED_CK_BUFG_CASC20",
|
||||
"CLK_PMV_IMUX35_0",
|
||||
"CLK_FEED_CK_GCLK3",
|
||||
"CLK_PMV_IMUX18_0",
|
||||
"CLK_FEED_SE4C1",
|
||||
"CLK_FEED_NW4A2",
|
||||
"CLK_FEED_WW2END0",
|
||||
"CLK_PMV2_A1",
|
||||
"CLK_FEED_CK_BUFG_CASC6",
|
||||
"CLK_FEED_SE2A0",
|
||||
"CLK_PMV_IMUX12_0",
|
||||
"CLK_FEED_WW4A0",
|
||||
"CLK_FEED_EE4BEG2",
|
||||
"CLK_FEED_CK_GCLK10",
|
||||
"CLK_FEED_R_CK_BUFG_CASC30",
|
||||
"CLK_FEED_SW4END3",
|
||||
"CLK_FEED_EL1BEG0",
|
||||
"CLK_PMV_IMUX17_0",
|
||||
"CLK_FEED_EE4BEG0",
|
||||
"CLK_FEED_WR1END3",
|
||||
"CLK_PMV_LOGIC_OUTS16_0",
|
||||
"CLK_PMV2_ODIV4",
|
||||
"CLK_FEED_CK_GCLK5",
|
||||
"CLK_FEED_CK_BUFG_CASC30",
|
||||
"CLK_FEED_SE4BEG0",
|
||||
"CLK_PMV_LOGIC_OUTS21_0",
|
||||
"CLK_FEED_EE4BEG1",
|
||||
"CLK_FEED_SE4BEG3",
|
||||
"CLK_FEED_CK_GCLK17",
|
||||
"CLK_FEED_R_CK_BUFG_CASC6",
|
||||
"CLK_FEED_SW4A1",
|
||||
"CLK_FEED_R_CK_GCLK23",
|
||||
"CLK_FEED_EE2BEG3",
|
||||
"CLK_FEED_R_CK_BUFG_CASC16",
|
||||
"CLK_FEED_R_CK_GCLK21",
|
||||
"CLK_FEED_R_CK_GCLK10",
|
||||
"CLK_FEED_NE4C3",
|
||||
"CLK_FEED_R_CK_BUFG_CASC21",
|
||||
"CLK_PMV_LOGIC_OUTS4_0",
|
||||
"CLK_PMV_IMUX14_0",
|
||||
"CLK_FEED_NW4A0",
|
||||
"CLK_PMV_BYP5_0",
|
||||
"CLK_FEED_SE4BEG2",
|
||||
"CLK_FEED_R_CK_BUFG_CASC31",
|
||||
"CLK_FEED_CK_BUFG_CASC11",
|
||||
"CLK_FEED_R_CK_GCLK20",
|
||||
"CLK_FEED_SW4END0",
|
||||
"CLK_PMV2_EN",
|
||||
"CLK_PMV_LOGIC_OUTS7_0",
|
||||
"CLK_PMV_IMUX32_0",
|
||||
"CLK_FEED_CK_BUFG_CASC26",
|
||||
"CLK_PMV_IMUX9_0",
|
||||
"CLK_FEED_LH5",
|
||||
"CLK_PMV_IMUX37_0",
|
||||
"CLK_PMV_IMUX7_0",
|
||||
"CLK_FEED_R_CK_GCLK31",
|
||||
"CLK_FEED_WW4B1",
|
||||
"CLK_FEED_CK_GCLK24",
|
||||
"CLK_FEED_WW4END1",
|
||||
"CLK_FEED_R_CK_GCLK17",
|
||||
"CLK_FEED_R_CK_GCLK7",
|
||||
"CLK_FEED_CK_BUFG_CASC28",
|
||||
"CLK_FEED_EE2A3",
|
||||
"CLK_FEED_CK_GCLK14",
|
||||
"CLK_FEED_CK_GCLK13",
|
||||
"CLK_FEED_CK_BUFG_CASC1",
|
||||
"CLK_FEED_R_CK_BUFG_CASC9",
|
||||
"CLK_FEED_LH8",
|
||||
"CLK_FEED_EE4C2",
|
||||
"CLK_FEED_WW4B3",
|
||||
"CLK_FEED_EE4A3",
|
||||
"CLK_FEED_NW2A2",
|
||||
"CLK_FEED_CK_BUFG_CASC10",
|
||||
"CLK_FEED_WL1END1",
|
||||
"CLK_PMV_BYP2_0",
|
||||
"CLK_FEED_SE4C3",
|
||||
"CLK_FEED_WL1END2",
|
||||
"CLK_PMV_LOGIC_OUTS13_0",
|
||||
"CLK_FEED_LH3",
|
||||
"CLK_PMV_LOGIC_OUTS0_0",
|
||||
"CLK_PMV_IMUX39_0",
|
||||
"CLK_FEED_R_CK_GCLK13",
|
||||
"CLK_FEED_NW2A3",
|
||||
"CLK_FEED_LH4",
|
||||
"CLK_FEED_EE4B0",
|
||||
"CLK_PMV_IMUX29_0",
|
||||
"CLK_FEED_SE4C2",
|
||||
"CLK_FEED_SW2A3",
|
||||
"CLK_FEED_EE4BEG3",
|
||||
"CLK_FEED_CK_GCLK15",
|
||||
"CLK_FEED_R_CK_GCLK1",
|
||||
"CLK_FEED_R_CK_GCLK15",
|
||||
"CLK_FEED_R_CK_GCLK12",
|
||||
"CLK_PMV_IMUX38_0",
|
||||
"CLK_FEED_R_CK_GCLK28",
|
||||
"CLK_FEED_CK_BUFG_CASC17",
|
||||
"CLK_PMV_LOGIC_OUTS10_0",
|
||||
"CLK_PMV_CLK1_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC13",
|
||||
"CLK_PMV_IMUX2_0",
|
||||
"CLK_FEED_NW4END2",
|
||||
"CLK_FEED_WW4END2",
|
||||
"CLK_PMV_LOGIC_OUTS11_0",
|
||||
"CLK_PMV_IMUX3_0",
|
||||
"CLK_FEED_NE2A3",
|
||||
"CLK_FEED_NW2A3",
|
||||
"CLK_FEED_CK_BUFG_CASC10",
|
||||
"CLK_FEED_R_CK_BUFG_CASC9",
|
||||
"CLK_FEED_SW4A0",
|
||||
"CLK_FEED_SE4BEG1",
|
||||
"CLK_PMV_FAN7_0",
|
||||
"CLK_FEED_SE2A2",
|
||||
"CLK_FEED_R_CK_BUFG_CASC27",
|
||||
"CLK_FEED_NE2A0",
|
||||
"CLK_FEED_SW4A3",
|
||||
"CLK_FEED_NW2A0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC19",
|
||||
"CLK_PMV_BYP5_0",
|
||||
"CLK_FEED_NE4BEG3",
|
||||
"CLK_FEED_SE4BEG3",
|
||||
"CLK_PMV_IMUX5_0",
|
||||
"CLK_FEED_CK_BUFG_CASC29",
|
||||
"CLK_PMV2_O",
|
||||
"CLK_PMV_BYP6_0",
|
||||
"CLK_FEED_CK_GCLK26",
|
||||
"CLK_FEED_R_CK_GCLK5",
|
||||
"CLK_FEED_R_CK_BUFG_CASC12",
|
||||
"CLK_FEED_LH10",
|
||||
"CLK_FEED_SE4C3",
|
||||
"CLK_FEED_R_CK_BUFG_CASC14",
|
||||
"CLK_FEED_R_CK_GCLK14",
|
||||
"CLK_PMV_FAN1_0",
|
||||
"CLK_FEED_NW2A2",
|
||||
"CLK_FEED_NW4END2",
|
||||
"CLK_PMV_IMUX32_0",
|
||||
"CLK_PMV_BYP3_0",
|
||||
"CLK_PMV_LOGIC_OUTS1_0",
|
||||
"CLK_FEED_R_CK_GCLK17",
|
||||
"CLK_FEED_R_CK_BUFG_CASC17",
|
||||
"CLK_FEED_R_CK_GCLK18",
|
||||
"CLK_FEED_R_CK_BUFG_CASC24",
|
||||
"CLK_FEED_CK_BUFG_CASC4",
|
||||
"CLK_PMV_LOGIC_OUTS13_0",
|
||||
"CLK_FEED_CK_BUFG_CASC18",
|
||||
"CLK_FEED_LH9",
|
||||
"CLK_FEED_NW4END1",
|
||||
"CLK_FEED_LH4",
|
||||
"CLK_PMV_IMUX37_0",
|
||||
"CLK_PMV_LOGIC_OUTS15_0",
|
||||
"CLK_FEED_NW4A2",
|
||||
"CLK_FEED_EE2BEG1",
|
||||
"CLK_PMV_IMUX2_0",
|
||||
"CLK_FEED_EE4BEG1",
|
||||
"CLK_FEED_CK_GCLK30",
|
||||
"CLK_PMV_IMUX8_0",
|
||||
"CLK_FEED_CK_GCLK22",
|
||||
"CLK_FEED_CK_GCLK16",
|
||||
"CLK_PMV_IMUX20_0",
|
||||
"CLK_FEED_R_CK_GCLK2",
|
||||
"CLK_PMV_FAN0_0",
|
||||
"CLK_FEED_LH1",
|
||||
"CLK_FEED_R_CK_GCLK23",
|
||||
"CLK_PMV_LOGIC_OUTS7_0",
|
||||
"CLK_PMV_IMUX31_0",
|
||||
"CLK_FEED_LH5",
|
||||
"CLK_FEED_EE2A0",
|
||||
"CLK_FEED_WW4B0",
|
||||
"CLK_PMV_BYP2_0",
|
||||
"CLK_FEED_SE4BEG2",
|
||||
"CLK_FEED_NW4END3",
|
||||
"CLK_FEED_NE4BEG2",
|
||||
"CLK_PMV_LOGIC_OUTS14_0",
|
||||
"CLK_PMV_CLK1_0",
|
||||
"CLK_FEED_NE4C3",
|
||||
"CLK_FEED_R_CK_GCLK25",
|
||||
"CLK_FEED_EE2BEG2",
|
||||
"CLK_PMV_IMUX43_0",
|
||||
"CLK_FEED_WL1END2",
|
||||
"CLK_FEED_CK_GCLK0",
|
||||
"CLK_PMV_CLK0_0",
|
||||
"CLK_FEED_R_CK_GCLK10",
|
||||
"CLK_PMV_LOGIC_OUTS0_0",
|
||||
"CLK_PMV_IMUX47_0",
|
||||
"CLK_FEED_CK_GCLK20",
|
||||
"CLK_FEED_ER1BEG3",
|
||||
"CLK_FEED_WW4A1",
|
||||
"CLK_FEED_CK_BUFG_CASC17",
|
||||
"CLK_FEED_CK_GCLK23",
|
||||
"CLK_FEED_LH2",
|
||||
"CLK_FEED_R_CK_GCLK3",
|
||||
"CLK_FEED_EE4B1",
|
||||
"CLK_FEED_R_CK_GCLK7",
|
||||
"CLK_FEED_LH8",
|
||||
"CLK_FEED_LH3",
|
||||
"CLK_FEED_NW2A1",
|
||||
"CLK_FEED_LH11",
|
||||
"CLK_FEED_R_CK_BUFG_CASC29",
|
||||
"CLK_FEED_CK_BUFG_CASC5",
|
||||
"CLK_PMV_IMUX35_0",
|
||||
"CLK_PMV_IMUX0_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC23",
|
||||
"CLK_FEED_CK_GCLK3",
|
||||
"CLK_FEED_WL1END3",
|
||||
"CLK_FEED_R_CK_BUFG_CASC15",
|
||||
"CLK_FEED_ER1BEG2",
|
||||
"CLK_FEED_CK_BUFG_CASC30",
|
||||
"CLK_PMV_LOGIC_OUTS2_0",
|
||||
"CLK_PMV_IMUX17_0",
|
||||
"CLK_FEED_EL1BEG3",
|
||||
"CLK_FEED_R_CK_GCLK16",
|
||||
"CLK_PMV_IMUX36_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC7",
|
||||
"CLK_FEED_EE4BEG2",
|
||||
"CLK_PMV_FAN5_0",
|
||||
"CLK_FEED_CK_GCLK19",
|
||||
"CLK_PMV_IMUX38_0",
|
||||
"CLK_PMV_IMUX10_0",
|
||||
"CLK_FEED_CK_GCLK11",
|
||||
"CLK_FEED_CK_BUFG_CASC21",
|
||||
"CLK_FEED_EE2BEG3",
|
||||
"CLK_FEED_SW4END0",
|
||||
"CLK_PMV_LOGIC_OUTS10_0",
|
||||
"CLK_PMV_LOGIC_OUTS19_0",
|
||||
"CLK_PMV2_A0",
|
||||
"CLK_FEED_R_CK_GCLK1",
|
||||
"CLK_FEED_WL1END1",
|
||||
"CLK_FEED_R_CK_GCLK13",
|
||||
"CLK_FEED_EE4B2",
|
||||
"CLK_FEED_R_CK_BUFG_CASC4",
|
||||
"CLK_FEED_R_CK_GCLK28",
|
||||
"CLK_FEED_CK_GCLK4",
|
||||
"CLK_FEED_R_CK_BUFG_CASC8",
|
||||
"CLK_PMV_IMUX15_0",
|
||||
"CLK_PMV_IMUX19_0",
|
||||
"CLK_PMV_IMUX29_0",
|
||||
"CLK_FEED_CK_GCLK6",
|
||||
"CLK_FEED_EE4C3",
|
||||
"CLK_PMV_LOGIC_OUTS22_0",
|
||||
"CLK_FEED_NW4A0",
|
||||
"CLK_FEED_WW2END0",
|
||||
"CLK_FEED_SE2A0",
|
||||
"CLK_FEED_LH6",
|
||||
"CLK_FEED_MONITOR_P",
|
||||
"CLK_FEED_SE4C2",
|
||||
"CLK_PMV_LOGIC_OUTS6_0",
|
||||
"CLK_PMV_BYP0_0",
|
||||
"CLK_PMV2_EN",
|
||||
"CLK_FEED_WW2END3",
|
||||
"CLK_FEED_R_CK_BUFG_CASC18",
|
||||
"CLK_FEED_WW4B2",
|
||||
"CLK_FEED_R_CK_GCLK27",
|
||||
"CLK_PMV_FAN4_0",
|
||||
"CLK_FEED_WR1END1",
|
||||
"CLK_FEED_R_CK_BUFG_CASC28",
|
||||
"CLK_FEED_WW4END0",
|
||||
"CLK_FEED_CK_BUFG_CASC12",
|
||||
"CLK_FEED_SW2A3",
|
||||
"CLK_FEED_WW4C0",
|
||||
"CLK_FEED_SW4END1",
|
||||
"CLK_FEED_LH12",
|
||||
"CLK_FEED_CK_BUFG_CASC7",
|
||||
"CLK_PMV_IMUX16_0",
|
||||
"CLK_FEED_R_CK_GCLK9",
|
||||
"CLK_FEED_CK_BUFG_CASC2",
|
||||
"CLK_PMV_IMUX4_0",
|
||||
"CLK_FEED_CK_BUFG_CASC9",
|
||||
"CLK_FEED_NW4END0",
|
||||
"CLK_FEED_CK_BUFG_CASC28",
|
||||
"CLK_FEED_R_CK_BUFG_CASC5",
|
||||
"CLK_PMV_IMUX40_0",
|
||||
"CLK_PMV_LOGIC_OUTS16_0",
|
||||
"CLK_FEED_R_CK_GCLK30",
|
||||
"CLK_FEED_R_CK_GCLK21",
|
||||
"CLK_FEED_R_CK_BUFG_CASC10",
|
||||
"CLK_PMV_IMUX34_0",
|
||||
"CLK_FEED_EL1BEG1",
|
||||
"CLK_FEED_CK_BUFG_CASC20",
|
||||
"CLK_FEED_NE4C0",
|
||||
"CLK_FEED_WW4END1",
|
||||
"CLK_FEED_CK_BUFG_CASC25",
|
||||
"CLK_PMV_LOGIC_OUTS3_0",
|
||||
"CLK_FEED_ER1BEG1",
|
||||
"CLK_PMV_IMUX25_0",
|
||||
"CLK_PMV_LOGIC_OUTS12_0",
|
||||
"CLK_FEED_CK_BUFG_CASC19",
|
||||
"CLK_FEED_EE4A0",
|
||||
"CLK_FEED_SW2A0",
|
||||
"CLK_FEED_CK_BUFG_CASC22",
|
||||
"CLK_FEED_NW4A3",
|
||||
"CLK_PMV_BYP7_0",
|
||||
"CLK_PMV_FAN6_0",
|
||||
"CLK_FEED_CK_GCLK25",
|
||||
"CLK_PMV_LOGIC_OUTS5_0",
|
||||
"CLK_PMV_LOGIC_OUTS9_0",
|
||||
"CLK_FEED_CK_GCLK5",
|
||||
"CLK_FEED_WR1END0",
|
||||
"CLK_PMV_IMUX42_0",
|
||||
"CLK_FEED_SW4A2",
|
||||
"CLK_FEED_EE4C0",
|
||||
"CLK_PMV_LOGIC_OUTS21_0",
|
||||
"CLK_FEED_CK_BUFG_CASC11",
|
||||
"CLK_FEED_EL1BEG2",
|
||||
"CLK_FEED_WR1END3",
|
||||
"CLK_FEED_CK_BUFG_CASC3",
|
||||
"CLK_FEED_CK_GCLK15",
|
||||
"CLK_FEED_MONITOR_N",
|
||||
"CLK_PMV_IMUX3_0",
|
||||
"CLK_PMV_LOGIC_OUTS4_0",
|
||||
"CLK_PMV_BYP1_0",
|
||||
"CLK_FEED_NE4C2",
|
||||
"CLK_FEED_CK_BUFG_CASC1",
|
||||
"CLK_FEED_EE2A3",
|
||||
"CLK_FEED_WW2A3",
|
||||
"CLK_FEED_WW2END1",
|
||||
"CLK_FEED_R_CK_GCLK12",
|
||||
"CLK_FEED_CK_GCLK18",
|
||||
"CLK_FEED_WW2END2",
|
||||
"CLK_PMV_IMUX41_0",
|
||||
"CLK_FEED_SW4A1",
|
||||
"CLK_FEED_SE4C1",
|
||||
"CLK_PMV_IMUX26_0",
|
||||
"CLK_FEED_CK_BUFG_CASC14",
|
||||
"CLK_FEED_EE4B0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC6",
|
||||
"CLK_FEED_R_CK_BUFG_CASC31",
|
||||
"CLK_FEED_R_CK_GCLK0",
|
||||
"CLK_PMV_IMUX46_0",
|
||||
"CLK_FEED_CK_GCLK10",
|
||||
"CLK_FEED_CK_GCLK27",
|
||||
"CLK_FEED_WW4A2",
|
||||
"CLK_PMV_LOGIC_OUTS17_0",
|
||||
"CLK_FEED_R_CK_GCLK29",
|
||||
"CLK_FEED_R_CK_BUFG_CASC20",
|
||||
"CLK_FEED_R_CK_GCLK15",
|
||||
"CLK_FEED_R_CK_GCLK31",
|
||||
"CLK_FEED_CK_GCLK29",
|
||||
"CLK_PMV_LOGIC_OUTS11_0",
|
||||
"CLK_FEED_R_CK_GCLK11",
|
||||
"CLK_FEED_CK_BUFG_CASC27",
|
||||
"CLK_FEED_CK_BUFG_CASC16",
|
||||
"CLK_FEED_CK_BUFG_CASC15",
|
||||
"CLK_FEED_R_CK_BUFG_CASC1",
|
||||
"CLK_PMV_IMUX33_0",
|
||||
"CLK_FEED_CK_BUFG_CASC26",
|
||||
"CLK_FEED_R_CK_BUFG_CASC3",
|
||||
"CLK_PMV_IMUX42_0"
|
||||
"CLK_PMV_IMUX21_0",
|
||||
"CLK_FEED_CK_GCLK21",
|
||||
"CLK_FEED_NE2A2",
|
||||
"CLK_FEED_WW2A0",
|
||||
"CLK_PMV_IMUX11_0",
|
||||
"CLK_PMV_IMUX24_0",
|
||||
"CLK_PMV_LOGIC_OUTS20_0",
|
||||
"CLK_PMV_IMUX1_0",
|
||||
"CLK_PMV_FAN2_0",
|
||||
"CLK_FEED_EE2A2",
|
||||
"CLK_PMV_IMUX27_0",
|
||||
"CLK_FEED_LH7",
|
||||
"CLK_FEED_R_CK_BUFG_CASC21",
|
||||
"CLK_FEED_EE4A1",
|
||||
"CLK_FEED_CK_GCLK2",
|
||||
"CLK_FEED_WW4B1",
|
||||
"CLK_FEED_R_CK_BUFG_CASC0",
|
||||
"CLK_FEED_NW4A1",
|
||||
"CLK_PMV_LOGIC_OUTS23_0",
|
||||
"CLK_FEED_SW4END3",
|
||||
"CLK_FEED_R_CK_GCLK24",
|
||||
"CLK_FEED_EE4A2",
|
||||
"CLK_FEED_CK_GCLK28",
|
||||
"CLK_FEED_WW4END2",
|
||||
"CLK_FEED_EL1BEG0",
|
||||
"CLK_PMV_LOGIC_OUTS18_0",
|
||||
"CLK_FEED_CK_BUFG_CASC0",
|
||||
"CLK_FEED_CK_BUFG_CASC31",
|
||||
"CLK_FEED_SE4BEG0",
|
||||
"CLK_FEED_WW4C2",
|
||||
"CLK_FEED_WR1END2",
|
||||
"CLK_FEED_CK_BUFG_CASC6",
|
||||
"CLK_FEED_CK_GCLK24",
|
||||
"CLK_FEED_ER1BEG0",
|
||||
"CLK_PMV_IMUX12_0",
|
||||
"CLK_FEED_WW4C1",
|
||||
"CLK_FEED_CK_GCLK8",
|
||||
"CLK_FEED_SW4END2",
|
||||
"CLK_PMV_IMUX22_0",
|
||||
"CLK_PMV_BYP4_0",
|
||||
"CLK_FEED_R_CK_GCLK20",
|
||||
"CLK_FEED_SE2A3",
|
||||
"CLK_FEED_EE2A1",
|
||||
"CLK_FEED_R_CK_GCLK4",
|
||||
"CLK_FEED_EE4A3",
|
||||
"CLK_FEED_R_CK_BUFG_CASC13",
|
||||
"CLK_FEED_R_CK_GCLK19",
|
||||
"CLK_PMV_IMUX45_0",
|
||||
"CLK_FEED_CK_BUFG_CASC8",
|
||||
"CLK_FEED_CK_GCLK14",
|
||||
"CLK_FEED_WW2A1",
|
||||
"CLK_PMV_IMUX9_0",
|
||||
"CLK_PMV_IMUX7_0",
|
||||
"CLK_PMV_IMUX39_0",
|
||||
"CLK_FEED_CK_GCLK17",
|
||||
"CLK_PMV_CTRL0_0",
|
||||
"CLK_PMV_IMUX23_0",
|
||||
"CLK_PMV_IMUX18_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC22",
|
||||
"CLK_PMV2_A1",
|
||||
"CLK_FEED_EE4B3",
|
||||
"CLK_PMV_IMUX14_0",
|
||||
"CLK_FEED_EE4C1",
|
||||
"CLK_FEED_SW2A2",
|
||||
"CLK_FEED_NE4C1",
|
||||
"CLK_FEED_R_CK_BUFG_CASC26",
|
||||
"CLK_PMV2_ODIV4",
|
||||
"CLK_FEED_SE2A1",
|
||||
"CLK_FEED_CK_GCLK7",
|
||||
"CLK_FEED_CK_GCLK1",
|
||||
"CLK_FEED_CK_GCLK9",
|
||||
"CLK_FEED_WW4C3",
|
||||
"CLK_FEED_R_CK_GCLK22",
|
||||
"CLK_FEED_CK_BUFG_CASC23",
|
||||
"CLK_FEED_EE4BEG0",
|
||||
"CLK_FEED_CK_BUFG_CASC24",
|
||||
"CLK_FEED_WW4A0",
|
||||
"CLK_PMV_IMUX44_0",
|
||||
"CLK_FEED_WW2A2",
|
||||
"CLK_FEED_NE2A1",
|
||||
"CLK_FEED_CK_GCLK31",
|
||||
"CLK_PMV_CTRL1_0",
|
||||
"CLK_PMV2_ODIV2",
|
||||
"CLK_PMV_IMUX13_0",
|
||||
"CLK_FEED_NE4BEG1",
|
||||
"CLK_FEED_R_CK_GCLK8",
|
||||
"CLK_PMV_LOGIC_OUTS8_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC16",
|
||||
"CLK_FEED_EE4C2",
|
||||
"CLK_PMV_IMUX6_0",
|
||||
"CLK_FEED_EE4BEG3",
|
||||
"CLK_PMV_IMUX30_0",
|
||||
"CLK_FEED_CK_BUFG_CASC13",
|
||||
"CLK_FEED_WW4B3",
|
||||
"CLK_FEED_R_CK_GCLK26",
|
||||
"CLK_PMV_IMUX28_0",
|
||||
"CLK_PMV2_A2",
|
||||
"CLK_FEED_NE4BEG0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC30",
|
||||
"CLK_FEED_SE4C0",
|
||||
"CLK_FEED_CK_GCLK13",
|
||||
"CLK_FEED_WW4A3",
|
||||
"CLK_FEED_EE2BEG0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC2",
|
||||
"CLK_FEED_R_CK_BUFG_CASC25",
|
||||
"CLK_FEED_R_CK_BUFG_CASC11",
|
||||
"CLK_FEED_SW2A1"
|
||||
],
|
||||
"tile_type": "CLK_PMV2",
|
||||
"sites": [
|
||||
{
|
||||
"x_coord": 0,
|
||||
"type": "PMV2",
|
||||
"y_coord": 0,
|
||||
"site_pins": {
|
||||
"A0": "CLK_PMV2_A0",
|
||||
"O": "CLK_PMV2_O",
|
||||
"A2": "CLK_PMV2_A2",
|
||||
"ODIV2": "CLK_PMV2_ODIV2",
|
||||
"ODIV4": "CLK_PMV2_ODIV4",
|
||||
"A1": "CLK_PMV2_A1",
|
||||
"EN": "CLK_PMV2_EN",
|
||||
"A1": "CLK_PMV2_A1"
|
||||
"ODIV2": "CLK_PMV2_ODIV2",
|
||||
"A0": "CLK_PMV2_A0",
|
||||
"ODIV4": "CLK_PMV2_ODIV4",
|
||||
"A2": "CLK_PMV2_A2"
|
||||
},
|
||||
"name": "X0Y0",
|
||||
"prefix": "PMV"
|
||||
"prefix": "PMV",
|
||||
"x_coord": 0
|
||||
}
|
||||
]
|
||||
}
|
||||
|
|
@ -1,359 +1,359 @@
|
|||
{
|
||||
"pips": {},
|
||||
"wires": [
|
||||
"CLK_PMV_IMUX40_0",
|
||||
"CLK_FEED_CK_GCLK31",
|
||||
"CLK_FEED_NE2A2",
|
||||
"CLK_PMV_IMUX43_0",
|
||||
"CLK_FEED_CK_BUFG_CASC9",
|
||||
"CLK_FEED_R_CK_BUFG_CASC23",
|
||||
"CLK_PMV_LOGIC_OUTS17_0",
|
||||
"CLK_FEED_NW4END3",
|
||||
"CLK_FEED_R_CK_GCLK0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC12",
|
||||
"CLK_FEED_EE4C3",
|
||||
"CLK_PMV_LOGIC_OUTS5_0",
|
||||
"CLK_PMV_BYP4_0",
|
||||
"CLK_FEED_CK_BUFG_CASC31",
|
||||
"CLK_FEED_R_CK_GCLK24",
|
||||
"CLK_PMV_LOGIC_OUTS18_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC29",
|
||||
"CLK_FEED_R_CK_BUFG_CASC8",
|
||||
"CLK_FEED_WW4C1",
|
||||
"CLK_FEED_SE2A3",
|
||||
"CLK_PMV_FAN7_0",
|
||||
"CLK_FEED_R_CK_GCLK19",
|
||||
"CLK_FEED_WW4A1",
|
||||
"CLK_FEED_R_CK_BUFG_CASC10",
|
||||
"CLK_PMV_FAN2_0",
|
||||
"CLK_PMV_BYP7_0",
|
||||
"CLK_FEED_EE4A2",
|
||||
"CLK_FEED_R_CK_BUFG_CASC7",
|
||||
"CLK_FEED_R_CK_BUFG_CASC2",
|
||||
"CLK_FEED_R_CK_GCLK9",
|
||||
"CLK_PMV_IMUX10_0",
|
||||
"CLK_FEED_CK_BUFG_CASC19",
|
||||
"CLK_PMV_IMUX5_0",
|
||||
"CLK_FEED_EE2BEG2",
|
||||
"CLK_FEED_EE2A2",
|
||||
"CLK_FEED_R_CK_BUFG_CASC5",
|
||||
"CLK_FEED_CK_BUFG_CASC4",
|
||||
"CLK_FEED_CK_GCLK19",
|
||||
"CLK_FEED_R_CK_BUFG_CASC17",
|
||||
"CLK_FEED_SW4A3",
|
||||
"CLK_PMV_IMUX23_0",
|
||||
"CLK_FEED_WW4C3",
|
||||
"CLK_FEED_LH10",
|
||||
"CLK_FEED_R_CK_GCLK29",
|
||||
"CLK_FEED_CK_GCLK11",
|
||||
"CLK_FEED_CK_GCLK7",
|
||||
"CLK_FEED_R_CK_BUFG_CASC27",
|
||||
"CLK_FEED_R_CK_BUFG_CASC11",
|
||||
"CLK_FEED_ER1BEG2",
|
||||
"CLK_FEED_EL1BEG3",
|
||||
"CLK_FEED_CK_GCLK1",
|
||||
"CLK_FEED_NE4C2",
|
||||
"CLK_FEED_CK_BUFG_CASC21",
|
||||
"CLK_FEED_EE4C1",
|
||||
"CLK_FEED_CK_BUFG_CASC12",
|
||||
"CLK_FEED_R_CK_GCLK2",
|
||||
"CLK_FEED_SE2A1",
|
||||
"CLK_FEED_CK_BUFG_CASC14",
|
||||
"CLK_FEED_ER1BEG3",
|
||||
"CLK_FEED_WW4C0",
|
||||
"CLK_FEED_CK_BUFG_CASC23",
|
||||
"CLK_FEED_CK_GCLK4",
|
||||
"CLK_FEED_ER1BEG1",
|
||||
"CLK_PMV_BYP6_0",
|
||||
"CLK_FEED_NW4A3",
|
||||
"CLK_FEED_R_CK_BUFG_CASC0",
|
||||
"CLK_PMV2_A0",
|
||||
"CLK_PMV_FAN0_0",
|
||||
"CLK_FEED_ER1BEG0",
|
||||
"CLK_PMV_IMUX31_0",
|
||||
"CLK_PMV_LOGIC_OUTS14_0",
|
||||
"CLK_FEED_CK_GCLK16",
|
||||
"CLK_FEED_CK_GCLK29",
|
||||
"CLK_FEED_R_CK_GCLK26",
|
||||
"CLK_PMV_LOGIC_OUTS3_0",
|
||||
"CLK_FEED_WW4C2",
|
||||
"CLK_FEED_R_CK_BUFG_CASC4",
|
||||
"CLK_FEED_R_CK_GCLK16",
|
||||
"CLK_FEED_CK_GCLK23",
|
||||
"CLK_FEED_EE4A0",
|
||||
"CLK_FEED_WR1END1",
|
||||
"CLK_FEED_NE4C0",
|
||||
"CLK_FEED_CK_BUFG_CASC16",
|
||||
"CLK_PMV_FAN1_0",
|
||||
"CLK_FEED_R_CK_GCLK5",
|
||||
"CLK_FEED_R_CK_BUFG_CASC19",
|
||||
"CLK_FEED_CK_GCLK6",
|
||||
"CLK_FEED_EE4B1",
|
||||
"CLK_FEED_CK_GCLK25",
|
||||
"CLK_FEED_EE4A1",
|
||||
"CLK_FEED_CK_GCLK9",
|
||||
"CLK_FEED_SW4END1",
|
||||
"CLK_FEED_SW4END2",
|
||||
"CLK_PMV_LOGIC_OUTS12_0",
|
||||
"CLK_FEED_CK_GCLK2",
|
||||
"CLK_FEED_WW2A3",
|
||||
"CLK_FEED_NE2A0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC14",
|
||||
"CLK_PMV_IMUX44_0",
|
||||
"CLK_FEED_CK_BUFG_CASC7",
|
||||
"CLK_FEED_CK_BUFG_CASC27",
|
||||
"CLK_PMV_IMUX8_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC1",
|
||||
"CLK_FEED_WW4A3",
|
||||
"CLK_PMV_IMUX1_0",
|
||||
"CLK_FEED_SW4A0",
|
||||
"CLK_PMV_LOGIC_OUTS2_0",
|
||||
"CLK_FEED_EE4C0",
|
||||
"CLK_PMV2_O",
|
||||
"CLK_FEED_CK_BUFG_CASC5",
|
||||
"CLK_FEED_CK_BUFG_CASC13",
|
||||
"CLK_FEED_CK_GCLK21",
|
||||
"CLK_PMV_FAN3_0",
|
||||
"CLK_FEED_CK_GCLK28",
|
||||
"CLK_PMV_IMUX15_0",
|
||||
"CLK_PMV_IMUX26_0",
|
||||
"CLK_PMV_CTRL1_0",
|
||||
"CLK_PMV_FAN5_0",
|
||||
"CLK_FEED_NE4BEG2",
|
||||
"CLK_FEED_WW2A2",
|
||||
"CLK_FEED_WR1END2",
|
||||
"CLK_PMV_CTRL0_0",
|
||||
"CLK_FEED_EL1BEG2",
|
||||
"CLK_PMV_IMUX30_0",
|
||||
"CLK_FEED_LH1",
|
||||
"CLK_FEED_CK_BUFG_CASC8",
|
||||
"CLK_FEED_R_CK_GCLK30",
|
||||
"CLK_PMV_LOGIC_OUTS9_0",
|
||||
"CLK_FEED_WW2A0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC15",
|
||||
"CLK_FEED_R_CK_GCLK3",
|
||||
"CLK_FEED_WW4A2",
|
||||
"CLK_PMV_IMUX13_0",
|
||||
"CLK_FEED_EL1BEG1",
|
||||
"CLK_FEED_WL1END0",
|
||||
"CLK_FEED_SE2A2",
|
||||
"CLK_PMV2_A2",
|
||||
"CLK_PMV_FAN3_0",
|
||||
"CLK_FEED_WW4END3",
|
||||
"CLK_FEED_R_CK_BUFG_CASC28",
|
||||
"CLK_FEED_NW4END0",
|
||||
"CLK_FEED_SW4A2",
|
||||
"CLK_PMV_IMUX22_0",
|
||||
"CLK_PMV_IMUX4_0",
|
||||
"CLK_PMV_BYP3_0",
|
||||
"CLK_FEED_NW4END1",
|
||||
"CLK_PMV_LOGIC_OUTS15_0",
|
||||
"CLK_FEED_WW2A1",
|
||||
"CLK_FEED_EE2A0",
|
||||
"CLK_FEED_EE2BEG0",
|
||||
"CLK_PMV_IMUX20_0",
|
||||
"CLK_PMV_BYP0_0",
|
||||
"CLK_PMV2_ODIV2",
|
||||
"CLK_FEED_NE4C1",
|
||||
"CLK_FEED_CK_GCLK20",
|
||||
"CLK_FEED_R_CK_GCLK11",
|
||||
"CLK_FEED_LH6",
|
||||
"CLK_FEED_NE4BEG0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC24",
|
||||
"CLK_FEED_NW2A1",
|
||||
"CLK_FEED_CK_GCLK12",
|
||||
"CLK_FEED_CK_BUFG_CASC2",
|
||||
"CLK_FEED_CK_GCLK22",
|
||||
"CLK_FEED_WL1END3",
|
||||
"CLK_FEED_R_CK_GCLK4",
|
||||
"CLK_PMV_IMUX33_0",
|
||||
"CLK_PMV_IMUX0_0",
|
||||
"CLK_FEED_LH9",
|
||||
"CLK_FEED_R_CK_GCLK6",
|
||||
"CLK_FEED_CK_GCLK30",
|
||||
"CLK_PMV_IMUX24_0",
|
||||
"CLK_FEED_NE4BEG3",
|
||||
"CLK_PMV_BYP1_0",
|
||||
"CLK_FEED_R_CK_GCLK27",
|
||||
"CLK_FEED_CK_BUFG_CASC3",
|
||||
"CLK_FEED_R_CK_GCLK18",
|
||||
"CLK_FEED_WW2END2",
|
||||
"CLK_FEED_EE2BEG1",
|
||||
"CLK_FEED_WW4END0",
|
||||
"CLK_FEED_CK_BUFG_CASC25",
|
||||
"CLK_PMV_IMUX16_0",
|
||||
"CLK_FEED_LH2",
|
||||
"CLK_PMV_LOGIC_OUTS6_0",
|
||||
"CLK_FEED_R_CK_GCLK25",
|
||||
"CLK_PMV_CLK0_0",
|
||||
"CLK_PMV_IMUX11_0",
|
||||
"CLK_FEED_EE4B3",
|
||||
"CLK_FEED_CK_BUFG_CASC24",
|
||||
"CLK_FEED_WW2END1",
|
||||
"CLK_PMV_LOGIC_OUTS23_0",
|
||||
"CLK_FEED_LH12",
|
||||
"CLK_FEED_LH7",
|
||||
"CLK_FEED_R_CK_GCLK14",
|
||||
"CLK_FEED_SW2A1",
|
||||
"CLK_PMV_IMUX6_0",
|
||||
"CLK_PMV_LOGIC_OUTS22_0",
|
||||
"CLK_FEED_NW4A1",
|
||||
"CLK_FEED_CK_GCLK27",
|
||||
"CLK_FEED_R_CK_BUFG_CASC18",
|
||||
"CLK_FEED_MONITOR_P",
|
||||
"CLK_FEED_SE4BEG1",
|
||||
"CLK_FEED_MONITOR_N",
|
||||
"CLK_PMV_IMUX47_0",
|
||||
"CLK_PMV_IMUX45_0",
|
||||
"CLK_FEED_CK_BUFG_CASC18",
|
||||
"CLK_PMV_IMUX36_0",
|
||||
"CLK_PMV_LOGIC_OUTS8_0",
|
||||
"CLK_FEED_CK_BUFG_CASC15",
|
||||
"CLK_PMV_LOGIC_OUTS19_0",
|
||||
"CLK_PMV_IMUX34_0",
|
||||
"CLK_FEED_SW2A0",
|
||||
"CLK_FEED_CK_BUFG_CASC0",
|
||||
"CLK_FEED_WR1END0",
|
||||
"CLK_FEED_CK_BUFG_CASC29",
|
||||
"CLK_PMV_IMUX21_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC20",
|
||||
"CLK_PMV_IMUX41_0",
|
||||
"CLK_PMV_IMUX27_0",
|
||||
"CLK_PMV_IMUX25_0",
|
||||
"CLK_FEED_NE4BEG1",
|
||||
"CLK_PMV_FAN6_0",
|
||||
"CLK_FEED_WW4B0",
|
||||
"CLK_PMV_LOGIC_OUTS1_0",
|
||||
"CLK_PMV_IMUX28_0",
|
||||
"CLK_FEED_NE2A1",
|
||||
"CLK_PMV_FAN4_0",
|
||||
"CLK_FEED_SE4C0",
|
||||
"CLK_FEED_R_CK_GCLK22",
|
||||
"CLK_FEED_R_CK_GCLK8",
|
||||
"CLK_PMV_LOGIC_OUTS20_0",
|
||||
"CLK_PMV_IMUX19_0",
|
||||
"CLK_FEED_WW2END3",
|
||||
"CLK_FEED_R_CK_BUFG_CASC25",
|
||||
"CLK_FEED_EE2A1",
|
||||
"CLK_FEED_EE4B2",
|
||||
"CLK_FEED_CK_GCLK0",
|
||||
"CLK_FEED_WW4B2",
|
||||
"CLK_PMV_IMUX46_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC26",
|
||||
"CLK_FEED_R_CK_BUFG_CASC22",
|
||||
"CLK_FEED_SW2A2",
|
||||
"CLK_FEED_CK_GCLK8",
|
||||
"CLK_FEED_LH11",
|
||||
"CLK_FEED_NW2A0",
|
||||
"CLK_FEED_CK_BUFG_CASC22",
|
||||
"CLK_FEED_CK_GCLK18",
|
||||
"CLK_FEED_CK_GCLK26",
|
||||
"CLK_FEED_CK_BUFG_CASC20",
|
||||
"CLK_PMV_IMUX35_0",
|
||||
"CLK_FEED_CK_GCLK3",
|
||||
"CLK_PMV_IMUX18_0",
|
||||
"CLK_FEED_SE4C1",
|
||||
"CLK_FEED_NW4A2",
|
||||
"CLK_FEED_WW2END0",
|
||||
"CLK_PMV2_A1",
|
||||
"CLK_FEED_CK_BUFG_CASC6",
|
||||
"CLK_FEED_SE2A0",
|
||||
"CLK_PMV_IMUX12_0",
|
||||
"CLK_FEED_WW4A0",
|
||||
"CLK_FEED_EE4BEG2",
|
||||
"CLK_FEED_CK_GCLK10",
|
||||
"CLK_FEED_R_CK_BUFG_CASC30",
|
||||
"CLK_FEED_SW4END3",
|
||||
"CLK_FEED_EL1BEG0",
|
||||
"CLK_PMV_IMUX17_0",
|
||||
"CLK_FEED_EE4BEG0",
|
||||
"CLK_FEED_WR1END3",
|
||||
"CLK_PMV_LOGIC_OUTS16_0",
|
||||
"CLK_PMV2_ODIV4",
|
||||
"CLK_FEED_CK_GCLK5",
|
||||
"CLK_FEED_CK_BUFG_CASC30",
|
||||
"CLK_FEED_SE4BEG0",
|
||||
"CLK_PMV_LOGIC_OUTS21_0",
|
||||
"CLK_FEED_EE4BEG1",
|
||||
"CLK_FEED_SE4BEG3",
|
||||
"CLK_FEED_CK_GCLK17",
|
||||
"CLK_FEED_R_CK_BUFG_CASC6",
|
||||
"CLK_FEED_SW4A1",
|
||||
"CLK_FEED_R_CK_GCLK23",
|
||||
"CLK_FEED_EE2BEG3",
|
||||
"CLK_FEED_R_CK_BUFG_CASC16",
|
||||
"CLK_FEED_R_CK_GCLK21",
|
||||
"CLK_FEED_R_CK_GCLK10",
|
||||
"CLK_FEED_NE4C3",
|
||||
"CLK_FEED_R_CK_BUFG_CASC21",
|
||||
"CLK_PMV_LOGIC_OUTS4_0",
|
||||
"CLK_PMV_IMUX14_0",
|
||||
"CLK_FEED_NW4A0",
|
||||
"CLK_PMV_BYP5_0",
|
||||
"CLK_FEED_SE4BEG2",
|
||||
"CLK_FEED_R_CK_BUFG_CASC31",
|
||||
"CLK_FEED_CK_BUFG_CASC11",
|
||||
"CLK_FEED_R_CK_GCLK20",
|
||||
"CLK_FEED_SW4END0",
|
||||
"CLK_PMV2_EN",
|
||||
"CLK_PMV_LOGIC_OUTS7_0",
|
||||
"CLK_PMV_IMUX32_0",
|
||||
"CLK_FEED_CK_BUFG_CASC26",
|
||||
"CLK_PMV_IMUX9_0",
|
||||
"CLK_FEED_LH5",
|
||||
"CLK_PMV_IMUX37_0",
|
||||
"CLK_PMV_IMUX7_0",
|
||||
"CLK_FEED_R_CK_GCLK31",
|
||||
"CLK_FEED_WW4B1",
|
||||
"CLK_FEED_CK_GCLK24",
|
||||
"CLK_FEED_WW4END1",
|
||||
"CLK_FEED_R_CK_GCLK17",
|
||||
"CLK_FEED_R_CK_GCLK7",
|
||||
"CLK_FEED_CK_BUFG_CASC28",
|
||||
"CLK_FEED_EE2A3",
|
||||
"CLK_FEED_CK_GCLK14",
|
||||
"CLK_FEED_CK_GCLK13",
|
||||
"CLK_FEED_CK_BUFG_CASC1",
|
||||
"CLK_FEED_R_CK_BUFG_CASC9",
|
||||
"CLK_FEED_LH8",
|
||||
"CLK_FEED_EE4C2",
|
||||
"CLK_FEED_WW4B3",
|
||||
"CLK_FEED_EE4A3",
|
||||
"CLK_FEED_NW2A2",
|
||||
"CLK_FEED_CK_BUFG_CASC10",
|
||||
"CLK_FEED_WL1END1",
|
||||
"CLK_PMV_BYP2_0",
|
||||
"CLK_FEED_SE4C3",
|
||||
"CLK_FEED_WL1END2",
|
||||
"CLK_PMV_LOGIC_OUTS13_0",
|
||||
"CLK_FEED_LH3",
|
||||
"CLK_PMV_LOGIC_OUTS0_0",
|
||||
"CLK_PMV_IMUX39_0",
|
||||
"CLK_FEED_R_CK_GCLK13",
|
||||
"CLK_FEED_NW2A3",
|
||||
"CLK_FEED_LH4",
|
||||
"CLK_FEED_EE4B0",
|
||||
"CLK_PMV_IMUX29_0",
|
||||
"CLK_FEED_SE4C2",
|
||||
"CLK_FEED_SW2A3",
|
||||
"CLK_FEED_EE4BEG3",
|
||||
"CLK_FEED_CK_GCLK15",
|
||||
"CLK_FEED_R_CK_GCLK1",
|
||||
"CLK_FEED_R_CK_GCLK15",
|
||||
"CLK_FEED_R_CK_GCLK12",
|
||||
"CLK_PMV_IMUX38_0",
|
||||
"CLK_FEED_R_CK_GCLK28",
|
||||
"CLK_FEED_CK_BUFG_CASC17",
|
||||
"CLK_PMV_LOGIC_OUTS10_0",
|
||||
"CLK_PMV_CLK1_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC13",
|
||||
"CLK_PMV_IMUX2_0",
|
||||
"CLK_FEED_NW4END2",
|
||||
"CLK_FEED_WW4END2",
|
||||
"CLK_PMV_LOGIC_OUTS11_0",
|
||||
"CLK_PMV_IMUX3_0",
|
||||
"CLK_FEED_NE2A3",
|
||||
"CLK_FEED_NW2A3",
|
||||
"CLK_FEED_CK_BUFG_CASC10",
|
||||
"CLK_FEED_R_CK_BUFG_CASC9",
|
||||
"CLK_FEED_SW4A0",
|
||||
"CLK_FEED_SE4BEG1",
|
||||
"CLK_PMV_FAN7_0",
|
||||
"CLK_FEED_SE2A2",
|
||||
"CLK_FEED_R_CK_BUFG_CASC27",
|
||||
"CLK_FEED_NE2A0",
|
||||
"CLK_FEED_SW4A3",
|
||||
"CLK_FEED_NW2A0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC19",
|
||||
"CLK_PMV_BYP5_0",
|
||||
"CLK_FEED_NE4BEG3",
|
||||
"CLK_FEED_SE4BEG3",
|
||||
"CLK_PMV_IMUX5_0",
|
||||
"CLK_FEED_CK_BUFG_CASC29",
|
||||
"CLK_PMV2_O",
|
||||
"CLK_PMV_BYP6_0",
|
||||
"CLK_FEED_CK_GCLK26",
|
||||
"CLK_FEED_R_CK_GCLK5",
|
||||
"CLK_FEED_R_CK_BUFG_CASC12",
|
||||
"CLK_FEED_LH10",
|
||||
"CLK_FEED_SE4C3",
|
||||
"CLK_FEED_R_CK_BUFG_CASC14",
|
||||
"CLK_FEED_R_CK_GCLK14",
|
||||
"CLK_PMV_FAN1_0",
|
||||
"CLK_FEED_NW2A2",
|
||||
"CLK_FEED_NW4END2",
|
||||
"CLK_PMV_IMUX32_0",
|
||||
"CLK_PMV_BYP3_0",
|
||||
"CLK_PMV_LOGIC_OUTS1_0",
|
||||
"CLK_FEED_R_CK_GCLK17",
|
||||
"CLK_FEED_R_CK_BUFG_CASC17",
|
||||
"CLK_FEED_R_CK_GCLK18",
|
||||
"CLK_FEED_R_CK_BUFG_CASC24",
|
||||
"CLK_FEED_CK_BUFG_CASC4",
|
||||
"CLK_PMV_LOGIC_OUTS13_0",
|
||||
"CLK_FEED_CK_BUFG_CASC18",
|
||||
"CLK_FEED_LH9",
|
||||
"CLK_FEED_NW4END1",
|
||||
"CLK_FEED_LH4",
|
||||
"CLK_PMV_IMUX37_0",
|
||||
"CLK_PMV_LOGIC_OUTS15_0",
|
||||
"CLK_FEED_NW4A2",
|
||||
"CLK_FEED_EE2BEG1",
|
||||
"CLK_PMV_IMUX2_0",
|
||||
"CLK_FEED_EE4BEG1",
|
||||
"CLK_FEED_CK_GCLK30",
|
||||
"CLK_PMV_IMUX8_0",
|
||||
"CLK_FEED_CK_GCLK22",
|
||||
"CLK_FEED_CK_GCLK16",
|
||||
"CLK_PMV_IMUX20_0",
|
||||
"CLK_FEED_R_CK_GCLK2",
|
||||
"CLK_PMV_FAN0_0",
|
||||
"CLK_FEED_LH1",
|
||||
"CLK_FEED_R_CK_GCLK23",
|
||||
"CLK_PMV_LOGIC_OUTS7_0",
|
||||
"CLK_PMV_IMUX31_0",
|
||||
"CLK_FEED_LH5",
|
||||
"CLK_FEED_EE2A0",
|
||||
"CLK_FEED_WW4B0",
|
||||
"CLK_PMV_BYP2_0",
|
||||
"CLK_FEED_SE4BEG2",
|
||||
"CLK_FEED_NW4END3",
|
||||
"CLK_FEED_NE4BEG2",
|
||||
"CLK_PMV_LOGIC_OUTS14_0",
|
||||
"CLK_PMV_CLK1_0",
|
||||
"CLK_FEED_NE4C3",
|
||||
"CLK_FEED_R_CK_GCLK25",
|
||||
"CLK_FEED_EE2BEG2",
|
||||
"CLK_PMV_IMUX43_0",
|
||||
"CLK_FEED_WL1END2",
|
||||
"CLK_FEED_CK_GCLK0",
|
||||
"CLK_PMV_CLK0_0",
|
||||
"CLK_FEED_R_CK_GCLK10",
|
||||
"CLK_PMV_LOGIC_OUTS0_0",
|
||||
"CLK_PMV_IMUX47_0",
|
||||
"CLK_FEED_CK_GCLK20",
|
||||
"CLK_FEED_ER1BEG3",
|
||||
"CLK_FEED_WW4A1",
|
||||
"CLK_FEED_CK_BUFG_CASC17",
|
||||
"CLK_FEED_CK_GCLK23",
|
||||
"CLK_FEED_LH2",
|
||||
"CLK_FEED_R_CK_GCLK3",
|
||||
"CLK_FEED_EE4B1",
|
||||
"CLK_FEED_R_CK_GCLK7",
|
||||
"CLK_FEED_LH8",
|
||||
"CLK_FEED_LH3",
|
||||
"CLK_FEED_NW2A1",
|
||||
"CLK_FEED_LH11",
|
||||
"CLK_FEED_R_CK_BUFG_CASC29",
|
||||
"CLK_FEED_CK_BUFG_CASC5",
|
||||
"CLK_PMV_IMUX35_0",
|
||||
"CLK_PMV_IMUX0_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC23",
|
||||
"CLK_FEED_CK_GCLK3",
|
||||
"CLK_FEED_WL1END3",
|
||||
"CLK_FEED_R_CK_BUFG_CASC15",
|
||||
"CLK_FEED_ER1BEG2",
|
||||
"CLK_FEED_CK_BUFG_CASC30",
|
||||
"CLK_PMV_LOGIC_OUTS2_0",
|
||||
"CLK_PMV_IMUX17_0",
|
||||
"CLK_FEED_EL1BEG3",
|
||||
"CLK_FEED_R_CK_GCLK16",
|
||||
"CLK_PMV_IMUX36_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC7",
|
||||
"CLK_FEED_EE4BEG2",
|
||||
"CLK_PMV_FAN5_0",
|
||||
"CLK_FEED_CK_GCLK19",
|
||||
"CLK_PMV_IMUX38_0",
|
||||
"CLK_PMV_IMUX10_0",
|
||||
"CLK_FEED_CK_GCLK11",
|
||||
"CLK_FEED_CK_BUFG_CASC21",
|
||||
"CLK_FEED_EE2BEG3",
|
||||
"CLK_FEED_SW4END0",
|
||||
"CLK_PMV_LOGIC_OUTS10_0",
|
||||
"CLK_PMV_LOGIC_OUTS19_0",
|
||||
"CLK_PMV2_A0",
|
||||
"CLK_FEED_R_CK_GCLK1",
|
||||
"CLK_FEED_WL1END1",
|
||||
"CLK_FEED_R_CK_GCLK13",
|
||||
"CLK_FEED_EE4B2",
|
||||
"CLK_FEED_R_CK_BUFG_CASC4",
|
||||
"CLK_FEED_R_CK_GCLK28",
|
||||
"CLK_FEED_CK_GCLK4",
|
||||
"CLK_FEED_R_CK_BUFG_CASC8",
|
||||
"CLK_PMV_IMUX15_0",
|
||||
"CLK_PMV_IMUX19_0",
|
||||
"CLK_PMV_IMUX29_0",
|
||||
"CLK_FEED_CK_GCLK6",
|
||||
"CLK_FEED_EE4C3",
|
||||
"CLK_PMV_LOGIC_OUTS22_0",
|
||||
"CLK_FEED_NW4A0",
|
||||
"CLK_FEED_WW2END0",
|
||||
"CLK_FEED_SE2A0",
|
||||
"CLK_FEED_LH6",
|
||||
"CLK_FEED_MONITOR_P",
|
||||
"CLK_FEED_SE4C2",
|
||||
"CLK_PMV_LOGIC_OUTS6_0",
|
||||
"CLK_PMV_BYP0_0",
|
||||
"CLK_PMV2_EN",
|
||||
"CLK_FEED_WW2END3",
|
||||
"CLK_FEED_R_CK_BUFG_CASC18",
|
||||
"CLK_FEED_WW4B2",
|
||||
"CLK_FEED_R_CK_GCLK27",
|
||||
"CLK_PMV_FAN4_0",
|
||||
"CLK_FEED_WR1END1",
|
||||
"CLK_FEED_R_CK_BUFG_CASC28",
|
||||
"CLK_FEED_WW4END0",
|
||||
"CLK_FEED_CK_BUFG_CASC12",
|
||||
"CLK_FEED_SW2A3",
|
||||
"CLK_FEED_WW4C0",
|
||||
"CLK_FEED_SW4END1",
|
||||
"CLK_FEED_LH12",
|
||||
"CLK_FEED_CK_BUFG_CASC7",
|
||||
"CLK_PMV_IMUX16_0",
|
||||
"CLK_FEED_R_CK_GCLK9",
|
||||
"CLK_FEED_CK_BUFG_CASC2",
|
||||
"CLK_PMV_IMUX4_0",
|
||||
"CLK_FEED_CK_BUFG_CASC9",
|
||||
"CLK_FEED_NW4END0",
|
||||
"CLK_FEED_CK_BUFG_CASC28",
|
||||
"CLK_FEED_R_CK_BUFG_CASC5",
|
||||
"CLK_PMV_IMUX40_0",
|
||||
"CLK_PMV_LOGIC_OUTS16_0",
|
||||
"CLK_FEED_R_CK_GCLK30",
|
||||
"CLK_FEED_R_CK_GCLK21",
|
||||
"CLK_FEED_R_CK_BUFG_CASC10",
|
||||
"CLK_PMV_IMUX34_0",
|
||||
"CLK_FEED_EL1BEG1",
|
||||
"CLK_FEED_CK_BUFG_CASC20",
|
||||
"CLK_FEED_NE4C0",
|
||||
"CLK_FEED_WW4END1",
|
||||
"CLK_FEED_CK_BUFG_CASC25",
|
||||
"CLK_PMV_LOGIC_OUTS3_0",
|
||||
"CLK_FEED_ER1BEG1",
|
||||
"CLK_PMV_IMUX25_0",
|
||||
"CLK_PMV_LOGIC_OUTS12_0",
|
||||
"CLK_FEED_CK_BUFG_CASC19",
|
||||
"CLK_FEED_EE4A0",
|
||||
"CLK_FEED_SW2A0",
|
||||
"CLK_FEED_CK_BUFG_CASC22",
|
||||
"CLK_FEED_NW4A3",
|
||||
"CLK_PMV_BYP7_0",
|
||||
"CLK_PMV_FAN6_0",
|
||||
"CLK_FEED_CK_GCLK25",
|
||||
"CLK_PMV_LOGIC_OUTS5_0",
|
||||
"CLK_PMV_LOGIC_OUTS9_0",
|
||||
"CLK_FEED_CK_GCLK5",
|
||||
"CLK_FEED_WR1END0",
|
||||
"CLK_PMV_IMUX42_0",
|
||||
"CLK_FEED_SW4A2",
|
||||
"CLK_FEED_EE4C0",
|
||||
"CLK_PMV_LOGIC_OUTS21_0",
|
||||
"CLK_FEED_CK_BUFG_CASC11",
|
||||
"CLK_FEED_EL1BEG2",
|
||||
"CLK_FEED_WR1END3",
|
||||
"CLK_FEED_CK_BUFG_CASC3",
|
||||
"CLK_FEED_CK_GCLK15",
|
||||
"CLK_FEED_MONITOR_N",
|
||||
"CLK_PMV_IMUX3_0",
|
||||
"CLK_PMV_LOGIC_OUTS4_0",
|
||||
"CLK_PMV_BYP1_0",
|
||||
"CLK_FEED_NE4C2",
|
||||
"CLK_FEED_CK_BUFG_CASC1",
|
||||
"CLK_FEED_EE2A3",
|
||||
"CLK_FEED_WW2A3",
|
||||
"CLK_FEED_WW2END1",
|
||||
"CLK_FEED_R_CK_GCLK12",
|
||||
"CLK_FEED_CK_GCLK18",
|
||||
"CLK_FEED_WW2END2",
|
||||
"CLK_PMV_IMUX41_0",
|
||||
"CLK_FEED_SW4A1",
|
||||
"CLK_FEED_SE4C1",
|
||||
"CLK_PMV_IMUX26_0",
|
||||
"CLK_FEED_CK_BUFG_CASC14",
|
||||
"CLK_FEED_EE4B0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC6",
|
||||
"CLK_FEED_R_CK_BUFG_CASC31",
|
||||
"CLK_FEED_R_CK_GCLK0",
|
||||
"CLK_PMV_IMUX46_0",
|
||||
"CLK_FEED_CK_GCLK10",
|
||||
"CLK_FEED_CK_GCLK27",
|
||||
"CLK_FEED_WW4A2",
|
||||
"CLK_PMV_LOGIC_OUTS17_0",
|
||||
"CLK_FEED_R_CK_GCLK29",
|
||||
"CLK_FEED_R_CK_BUFG_CASC20",
|
||||
"CLK_FEED_R_CK_GCLK15",
|
||||
"CLK_FEED_R_CK_GCLK31",
|
||||
"CLK_FEED_CK_GCLK29",
|
||||
"CLK_PMV_LOGIC_OUTS11_0",
|
||||
"CLK_FEED_R_CK_GCLK11",
|
||||
"CLK_FEED_CK_BUFG_CASC27",
|
||||
"CLK_FEED_CK_BUFG_CASC16",
|
||||
"CLK_FEED_CK_BUFG_CASC15",
|
||||
"CLK_FEED_R_CK_BUFG_CASC1",
|
||||
"CLK_PMV_IMUX33_0",
|
||||
"CLK_FEED_CK_BUFG_CASC26",
|
||||
"CLK_FEED_R_CK_BUFG_CASC3",
|
||||
"CLK_PMV_IMUX42_0"
|
||||
"CLK_PMV_IMUX21_0",
|
||||
"CLK_FEED_CK_GCLK21",
|
||||
"CLK_FEED_NE2A2",
|
||||
"CLK_FEED_WW2A0",
|
||||
"CLK_PMV_IMUX11_0",
|
||||
"CLK_PMV_IMUX24_0",
|
||||
"CLK_PMV_LOGIC_OUTS20_0",
|
||||
"CLK_PMV_IMUX1_0",
|
||||
"CLK_PMV_FAN2_0",
|
||||
"CLK_FEED_EE2A2",
|
||||
"CLK_PMV_IMUX27_0",
|
||||
"CLK_FEED_LH7",
|
||||
"CLK_FEED_R_CK_BUFG_CASC21",
|
||||
"CLK_FEED_EE4A1",
|
||||
"CLK_FEED_CK_GCLK2",
|
||||
"CLK_FEED_WW4B1",
|
||||
"CLK_FEED_R_CK_BUFG_CASC0",
|
||||
"CLK_FEED_NW4A1",
|
||||
"CLK_PMV_LOGIC_OUTS23_0",
|
||||
"CLK_FEED_SW4END3",
|
||||
"CLK_FEED_R_CK_GCLK24",
|
||||
"CLK_FEED_EE4A2",
|
||||
"CLK_FEED_CK_GCLK28",
|
||||
"CLK_FEED_WW4END2",
|
||||
"CLK_FEED_EL1BEG0",
|
||||
"CLK_PMV_LOGIC_OUTS18_0",
|
||||
"CLK_FEED_CK_BUFG_CASC0",
|
||||
"CLK_FEED_CK_BUFG_CASC31",
|
||||
"CLK_FEED_SE4BEG0",
|
||||
"CLK_FEED_WW4C2",
|
||||
"CLK_FEED_WR1END2",
|
||||
"CLK_FEED_CK_BUFG_CASC6",
|
||||
"CLK_FEED_CK_GCLK24",
|
||||
"CLK_FEED_ER1BEG0",
|
||||
"CLK_PMV_IMUX12_0",
|
||||
"CLK_FEED_WW4C1",
|
||||
"CLK_FEED_CK_GCLK8",
|
||||
"CLK_FEED_SW4END2",
|
||||
"CLK_PMV_IMUX22_0",
|
||||
"CLK_PMV_BYP4_0",
|
||||
"CLK_FEED_R_CK_GCLK20",
|
||||
"CLK_FEED_SE2A3",
|
||||
"CLK_FEED_EE2A1",
|
||||
"CLK_FEED_R_CK_GCLK4",
|
||||
"CLK_FEED_EE4A3",
|
||||
"CLK_FEED_R_CK_BUFG_CASC13",
|
||||
"CLK_FEED_R_CK_GCLK19",
|
||||
"CLK_PMV_IMUX45_0",
|
||||
"CLK_FEED_CK_BUFG_CASC8",
|
||||
"CLK_FEED_CK_GCLK14",
|
||||
"CLK_FEED_WW2A1",
|
||||
"CLK_PMV_IMUX9_0",
|
||||
"CLK_PMV_IMUX7_0",
|
||||
"CLK_PMV_IMUX39_0",
|
||||
"CLK_FEED_CK_GCLK17",
|
||||
"CLK_PMV_CTRL0_0",
|
||||
"CLK_PMV_IMUX23_0",
|
||||
"CLK_PMV_IMUX18_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC22",
|
||||
"CLK_PMV2_A1",
|
||||
"CLK_FEED_EE4B3",
|
||||
"CLK_PMV_IMUX14_0",
|
||||
"CLK_FEED_EE4C1",
|
||||
"CLK_FEED_SW2A2",
|
||||
"CLK_FEED_NE4C1",
|
||||
"CLK_FEED_R_CK_BUFG_CASC26",
|
||||
"CLK_PMV2_ODIV4",
|
||||
"CLK_FEED_SE2A1",
|
||||
"CLK_FEED_CK_GCLK7",
|
||||
"CLK_FEED_CK_GCLK1",
|
||||
"CLK_FEED_CK_GCLK9",
|
||||
"CLK_FEED_WW4C3",
|
||||
"CLK_FEED_R_CK_GCLK22",
|
||||
"CLK_FEED_CK_BUFG_CASC23",
|
||||
"CLK_FEED_EE4BEG0",
|
||||
"CLK_FEED_CK_BUFG_CASC24",
|
||||
"CLK_FEED_WW4A0",
|
||||
"CLK_PMV_IMUX44_0",
|
||||
"CLK_FEED_WW2A2",
|
||||
"CLK_FEED_NE2A1",
|
||||
"CLK_FEED_CK_GCLK31",
|
||||
"CLK_PMV_CTRL1_0",
|
||||
"CLK_PMV2_ODIV2",
|
||||
"CLK_PMV_IMUX13_0",
|
||||
"CLK_FEED_NE4BEG1",
|
||||
"CLK_FEED_R_CK_GCLK8",
|
||||
"CLK_PMV_LOGIC_OUTS8_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC16",
|
||||
"CLK_FEED_EE4C2",
|
||||
"CLK_PMV_IMUX6_0",
|
||||
"CLK_FEED_EE4BEG3",
|
||||
"CLK_PMV_IMUX30_0",
|
||||
"CLK_FEED_CK_BUFG_CASC13",
|
||||
"CLK_FEED_WW4B3",
|
||||
"CLK_FEED_R_CK_GCLK26",
|
||||
"CLK_PMV_IMUX28_0",
|
||||
"CLK_PMV2_A2",
|
||||
"CLK_FEED_NE4BEG0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC30",
|
||||
"CLK_FEED_SE4C0",
|
||||
"CLK_FEED_CK_GCLK13",
|
||||
"CLK_FEED_WW4A3",
|
||||
"CLK_FEED_EE2BEG0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC2",
|
||||
"CLK_FEED_R_CK_BUFG_CASC25",
|
||||
"CLK_FEED_R_CK_BUFG_CASC11",
|
||||
"CLK_FEED_SW2A1"
|
||||
],
|
||||
"tile_type": "CLK_PMV2_SVT",
|
||||
"sites": []
|
||||
|
|
|
|||
|
|
@ -1,358 +1,358 @@
|
|||
{
|
||||
"pips": {},
|
||||
"wires": [
|
||||
"CLK_PMV_IMUX40_0",
|
||||
"CLK_FEED_CK_GCLK31",
|
||||
"CLK_FEED_NE2A2",
|
||||
"CLK_PMV_IMUX43_0",
|
||||
"CLK_FEED_CK_BUFG_CASC9",
|
||||
"CLK_FEED_R_CK_BUFG_CASC23",
|
||||
"CLK_PMV_LOGIC_OUTS17_0",
|
||||
"CLK_FEED_NW4END3",
|
||||
"CLK_FEED_R_CK_GCLK0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC12",
|
||||
"CLK_FEED_EE4C3",
|
||||
"CLK_PMV_LOGIC_OUTS5_0",
|
||||
"CLK_PMV_BYP4_0",
|
||||
"CLK_FEED_CK_BUFG_CASC31",
|
||||
"CLK_FEED_R_CK_GCLK24",
|
||||
"CLK_PMVIOB_ODIV2",
|
||||
"CLK_PMV_LOGIC_OUTS18_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC29",
|
||||
"CLK_FEED_R_CK_BUFG_CASC8",
|
||||
"CLK_FEED_WW4C1",
|
||||
"CLK_FEED_SE2A3",
|
||||
"CLK_PMV_FAN7_0",
|
||||
"CLK_FEED_R_CK_GCLK19",
|
||||
"CLK_FEED_WW4A1",
|
||||
"CLK_FEED_R_CK_BUFG_CASC10",
|
||||
"CLK_PMV_FAN2_0",
|
||||
"CLK_PMV_BYP7_0",
|
||||
"CLK_FEED_EE4A2",
|
||||
"CLK_FEED_R_CK_BUFG_CASC7",
|
||||
"CLK_FEED_R_CK_BUFG_CASC2",
|
||||
"CLK_FEED_R_CK_GCLK9",
|
||||
"CLK_PMV_IMUX10_0",
|
||||
"CLK_FEED_CK_BUFG_CASC19",
|
||||
"CLK_PMV_IMUX5_0",
|
||||
"CLK_FEED_EE2BEG2",
|
||||
"CLK_FEED_EE2A2",
|
||||
"CLK_FEED_R_CK_BUFG_CASC5",
|
||||
"CLK_FEED_CK_BUFG_CASC4",
|
||||
"CLK_FEED_CK_GCLK19",
|
||||
"CLK_FEED_R_CK_BUFG_CASC17",
|
||||
"CLK_FEED_SW4A3",
|
||||
"CLK_PMV_IMUX23_0",
|
||||
"CLK_FEED_WW4C3",
|
||||
"CLK_FEED_LH10",
|
||||
"CLK_FEED_R_CK_GCLK29",
|
||||
"CLK_FEED_CK_GCLK11",
|
||||
"CLK_FEED_CK_GCLK7",
|
||||
"CLK_FEED_R_CK_BUFG_CASC27",
|
||||
"CLK_FEED_R_CK_BUFG_CASC11",
|
||||
"CLK_FEED_ER1BEG2",
|
||||
"CLK_FEED_EL1BEG3",
|
||||
"CLK_FEED_CK_GCLK1",
|
||||
"CLK_FEED_NE4C2",
|
||||
"CLK_FEED_CK_BUFG_CASC21",
|
||||
"CLK_FEED_EE4C1",
|
||||
"CLK_FEED_CK_BUFG_CASC12",
|
||||
"CLK_FEED_R_CK_GCLK2",
|
||||
"CLK_FEED_SE2A1",
|
||||
"CLK_FEED_CK_BUFG_CASC14",
|
||||
"CLK_FEED_ER1BEG3",
|
||||
"CLK_FEED_WW4C0",
|
||||
"CLK_FEED_CK_BUFG_CASC23",
|
||||
"CLK_FEED_CK_GCLK4",
|
||||
"CLK_FEED_ER1BEG1",
|
||||
"CLK_PMV_BYP6_0",
|
||||
"CLK_FEED_NW4A3",
|
||||
"CLK_FEED_R_CK_BUFG_CASC0",
|
||||
"CLK_PMV_FAN0_0",
|
||||
"CLK_FEED_ER1BEG0",
|
||||
"CLK_PMV_IMUX31_0",
|
||||
"CLK_PMV_LOGIC_OUTS14_0",
|
||||
"CLK_FEED_CK_GCLK16",
|
||||
"CLK_FEED_CK_GCLK29",
|
||||
"CLK_FEED_R_CK_GCLK26",
|
||||
"CLK_PMV_LOGIC_OUTS3_0",
|
||||
"CLK_FEED_WW4C2",
|
||||
"CLK_FEED_R_CK_BUFG_CASC4",
|
||||
"CLK_FEED_R_CK_GCLK16",
|
||||
"CLK_FEED_CK_GCLK23",
|
||||
"CLK_FEED_EE4A0",
|
||||
"CLK_FEED_WR1END1",
|
||||
"CLK_FEED_NE4C0",
|
||||
"CLK_FEED_CK_BUFG_CASC16",
|
||||
"CLK_PMV_FAN1_0",
|
||||
"CLK_FEED_R_CK_GCLK5",
|
||||
"CLK_FEED_R_CK_BUFG_CASC19",
|
||||
"CLK_FEED_CK_GCLK6",
|
||||
"CLK_FEED_EE4B1",
|
||||
"CLK_FEED_CK_GCLK25",
|
||||
"CLK_FEED_EE4A1",
|
||||
"CLK_FEED_CK_GCLK9",
|
||||
"CLK_FEED_SW4END1",
|
||||
"CLK_FEED_SW4END2",
|
||||
"CLK_PMV_LOGIC_OUTS12_0",
|
||||
"CLK_FEED_CK_GCLK2",
|
||||
"CLK_FEED_WW2A3",
|
||||
"CLK_FEED_NE2A0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC14",
|
||||
"CLK_PMV_IMUX44_0",
|
||||
"CLK_FEED_CK_BUFG_CASC7",
|
||||
"CLK_FEED_CK_BUFG_CASC27",
|
||||
"CLK_PMV_IMUX8_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC1",
|
||||
"CLK_FEED_WW4A3",
|
||||
"CLK_PMVIOB_O",
|
||||
"CLK_PMV_IMUX1_0",
|
||||
"CLK_FEED_SW4A0",
|
||||
"CLK_PMV_LOGIC_OUTS2_0",
|
||||
"CLK_FEED_EE4C0",
|
||||
"CLK_FEED_CK_BUFG_CASC5",
|
||||
"CLK_FEED_CK_BUFG_CASC13",
|
||||
"CLK_FEED_CK_GCLK21",
|
||||
"CLK_PMV_FAN3_0",
|
||||
"CLK_FEED_CK_GCLK28",
|
||||
"CLK_PMV_IMUX15_0",
|
||||
"CLK_PMV_IMUX26_0",
|
||||
"CLK_PMV_CTRL1_0",
|
||||
"CLK_PMV_FAN5_0",
|
||||
"CLK_FEED_NE4BEG2",
|
||||
"CLK_FEED_WW2A2",
|
||||
"CLK_FEED_WR1END2",
|
||||
"CLK_PMV_CTRL0_0",
|
||||
"CLK_FEED_EL1BEG2",
|
||||
"CLK_PMV_IMUX30_0",
|
||||
"CLK_FEED_LH1",
|
||||
"CLK_FEED_CK_BUFG_CASC8",
|
||||
"CLK_FEED_R_CK_GCLK30",
|
||||
"CLK_PMV_LOGIC_OUTS9_0",
|
||||
"CLK_FEED_WW2A0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC15",
|
||||
"CLK_FEED_R_CK_GCLK3",
|
||||
"CLK_FEED_WW4A2",
|
||||
"CLK_PMV_IMUX13_0",
|
||||
"CLK_FEED_EL1BEG1",
|
||||
"CLK_FEED_WL1END0",
|
||||
"CLK_FEED_SE2A2",
|
||||
"CLK_PMV_FAN3_0",
|
||||
"CLK_FEED_WW4END3",
|
||||
"CLK_FEED_R_CK_BUFG_CASC28",
|
||||
"CLK_FEED_NW4END0",
|
||||
"CLK_FEED_SW4A2",
|
||||
"CLK_PMV_IMUX22_0",
|
||||
"CLK_PMV_IMUX4_0",
|
||||
"CLK_PMV_BYP3_0",
|
||||
"CLK_FEED_NW4END1",
|
||||
"CLK_PMV_LOGIC_OUTS15_0",
|
||||
"CLK_FEED_WW2A1",
|
||||
"CLK_FEED_EE2A0",
|
||||
"CLK_FEED_EE2BEG0",
|
||||
"CLK_PMV_IMUX20_0",
|
||||
"CLK_PMV_BYP0_0",
|
||||
"CLK_FEED_NE4C1",
|
||||
"CLK_FEED_CK_GCLK20",
|
||||
"CLK_FEED_R_CK_GCLK11",
|
||||
"CLK_FEED_LH6",
|
||||
"CLK_FEED_NE4BEG0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC24",
|
||||
"CLK_FEED_NW2A1",
|
||||
"CLK_FEED_CK_GCLK12",
|
||||
"CLK_FEED_CK_BUFG_CASC2",
|
||||
"CLK_FEED_CK_GCLK22",
|
||||
"CLK_FEED_WL1END3",
|
||||
"CLK_FEED_R_CK_GCLK4",
|
||||
"CLK_PMV_IMUX33_0",
|
||||
"CLK_PMV_IMUX0_0",
|
||||
"CLK_FEED_LH9",
|
||||
"CLK_FEED_R_CK_GCLK6",
|
||||
"CLK_FEED_CK_GCLK30",
|
||||
"CLK_PMV_IMUX24_0",
|
||||
"CLK_FEED_NE4BEG3",
|
||||
"CLK_PMV_BYP1_0",
|
||||
"CLK_FEED_R_CK_GCLK27",
|
||||
"CLK_FEED_CK_BUFG_CASC3",
|
||||
"CLK_FEED_R_CK_GCLK18",
|
||||
"CLK_FEED_WW2END2",
|
||||
"CLK_FEED_EE2BEG1",
|
||||
"CLK_FEED_WW4END0",
|
||||
"CLK_FEED_CK_BUFG_CASC25",
|
||||
"CLK_PMV_IMUX16_0",
|
||||
"CLK_FEED_LH2",
|
||||
"CLK_PMV_LOGIC_OUTS6_0",
|
||||
"CLK_FEED_R_CK_GCLK25",
|
||||
"CLK_PMV_CLK0_0",
|
||||
"CLK_PMV_IMUX11_0",
|
||||
"CLK_FEED_EE4B3",
|
||||
"CLK_FEED_CK_BUFG_CASC24",
|
||||
"CLK_FEED_WW2END1",
|
||||
"CLK_PMV_LOGIC_OUTS23_0",
|
||||
"CLK_FEED_LH12",
|
||||
"CLK_FEED_LH7",
|
||||
"CLK_FEED_R_CK_GCLK14",
|
||||
"CLK_FEED_SW2A1",
|
||||
"CLK_PMV_IMUX6_0",
|
||||
"CLK_PMV_LOGIC_OUTS22_0",
|
||||
"CLK_FEED_NW4A1",
|
||||
"CLK_FEED_CK_GCLK27",
|
||||
"CLK_FEED_R_CK_BUFG_CASC18",
|
||||
"CLK_FEED_MONITOR_P",
|
||||
"CLK_FEED_SE4BEG1",
|
||||
"CLK_FEED_MONITOR_N",
|
||||
"CLK_PMV_IMUX47_0",
|
||||
"CLK_PMV_IMUX45_0",
|
||||
"CLK_FEED_CK_BUFG_CASC18",
|
||||
"CLK_PMV_IMUX36_0",
|
||||
"CLK_PMV_LOGIC_OUTS8_0",
|
||||
"CLK_FEED_CK_BUFG_CASC15",
|
||||
"CLK_PMV_LOGIC_OUTS19_0",
|
||||
"CLK_PMV_IMUX34_0",
|
||||
"CLK_FEED_SW2A0",
|
||||
"CLK_FEED_CK_BUFG_CASC0",
|
||||
"CLK_FEED_WR1END0",
|
||||
"CLK_FEED_CK_BUFG_CASC29",
|
||||
"CLK_PMV_IMUX21_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC20",
|
||||
"CLK_PMV_IMUX41_0",
|
||||
"CLK_PMV_IMUX27_0",
|
||||
"CLK_PMV_IMUX25_0",
|
||||
"CLK_FEED_NE4BEG1",
|
||||
"CLK_PMV_FAN6_0",
|
||||
"CLK_FEED_WW4B0",
|
||||
"CLK_PMV_LOGIC_OUTS1_0",
|
||||
"CLK_PMV_IMUX28_0",
|
||||
"CLK_FEED_NE2A1",
|
||||
"CLK_PMV_FAN4_0",
|
||||
"CLK_PMVIOB_ODIV4",
|
||||
"CLK_FEED_SE4C0",
|
||||
"CLK_FEED_R_CK_GCLK8",
|
||||
"CLK_FEED_R_CK_GCLK22",
|
||||
"CLK_PMV_LOGIC_OUTS20_0",
|
||||
"CLK_PMV_IMUX19_0",
|
||||
"CLK_FEED_WW2END3",
|
||||
"CLK_FEED_R_CK_BUFG_CASC25",
|
||||
"CLK_FEED_EE2A1",
|
||||
"CLK_FEED_EE4B2",
|
||||
"CLK_FEED_CK_GCLK0",
|
||||
"CLK_FEED_WW4B2",
|
||||
"CLK_PMV_IMUX46_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC26",
|
||||
"CLK_FEED_R_CK_BUFG_CASC22",
|
||||
"CLK_FEED_SW2A2",
|
||||
"CLK_FEED_CK_GCLK8",
|
||||
"CLK_FEED_LH11",
|
||||
"CLK_FEED_NW2A0",
|
||||
"CLK_FEED_CK_BUFG_CASC22",
|
||||
"CLK_FEED_CK_GCLK18",
|
||||
"CLK_FEED_CK_GCLK26",
|
||||
"CLK_FEED_CK_BUFG_CASC20",
|
||||
"CLK_PMV_IMUX35_0",
|
||||
"CLK_FEED_CK_GCLK3",
|
||||
"CLK_PMV_IMUX18_0",
|
||||
"CLK_FEED_SE4C1",
|
||||
"CLK_FEED_NW4A2",
|
||||
"CLK_FEED_WW2END0",
|
||||
"CLK_FEED_CK_BUFG_CASC6",
|
||||
"CLK_PMVIOB_EN",
|
||||
"CLK_FEED_SE2A0",
|
||||
"CLK_PMV_IMUX12_0",
|
||||
"CLK_FEED_WW4A0",
|
||||
"CLK_PMVIOB_A1",
|
||||
"CLK_FEED_EE4BEG2",
|
||||
"CLK_FEED_CK_GCLK10",
|
||||
"CLK_FEED_R_CK_BUFG_CASC30",
|
||||
"CLK_FEED_SW4END3",
|
||||
"CLK_FEED_EL1BEG0",
|
||||
"CLK_PMV_IMUX17_0",
|
||||
"CLK_FEED_EE4BEG0",
|
||||
"CLK_FEED_WR1END3",
|
||||
"CLK_PMV_LOGIC_OUTS16_0",
|
||||
"CLK_FEED_CK_GCLK5",
|
||||
"CLK_FEED_CK_BUFG_CASC30",
|
||||
"CLK_FEED_SE4BEG0",
|
||||
"CLK_PMV_LOGIC_OUTS21_0",
|
||||
"CLK_FEED_EE4BEG1",
|
||||
"CLK_FEED_SE4BEG3",
|
||||
"CLK_FEED_CK_GCLK17",
|
||||
"CLK_FEED_R_CK_BUFG_CASC6",
|
||||
"CLK_FEED_SW4A1",
|
||||
"CLK_FEED_R_CK_GCLK23",
|
||||
"CLK_FEED_EE2BEG3",
|
||||
"CLK_FEED_R_CK_BUFG_CASC16",
|
||||
"CLK_FEED_R_CK_GCLK21",
|
||||
"CLK_FEED_R_CK_GCLK10",
|
||||
"CLK_FEED_NE4C3",
|
||||
"CLK_FEED_R_CK_BUFG_CASC21",
|
||||
"CLK_PMV_LOGIC_OUTS4_0",
|
||||
"CLK_PMV_IMUX14_0",
|
||||
"CLK_FEED_NW4A0",
|
||||
"CLK_PMV_BYP5_0",
|
||||
"CLK_FEED_SE4BEG2",
|
||||
"CLK_FEED_R_CK_BUFG_CASC31",
|
||||
"CLK_FEED_CK_BUFG_CASC11",
|
||||
"CLK_FEED_R_CK_GCLK20",
|
||||
"CLK_FEED_SW4END0",
|
||||
"CLK_PMV_LOGIC_OUTS7_0",
|
||||
"CLK_PMV_IMUX32_0",
|
||||
"CLK_FEED_CK_BUFG_CASC26",
|
||||
"CLK_PMV_IMUX9_0",
|
||||
"CLK_FEED_LH5",
|
||||
"CLK_PMV_IMUX37_0",
|
||||
"CLK_PMV_IMUX7_0",
|
||||
"CLK_FEED_R_CK_GCLK31",
|
||||
"CLK_FEED_WW4B1",
|
||||
"CLK_FEED_CK_GCLK24",
|
||||
"CLK_FEED_WW4END1",
|
||||
"CLK_FEED_R_CK_GCLK17",
|
||||
"CLK_FEED_R_CK_GCLK7",
|
||||
"CLK_FEED_CK_BUFG_CASC28",
|
||||
"CLK_FEED_EE2A3",
|
||||
"CLK_FEED_CK_GCLK14",
|
||||
"CLK_FEED_CK_GCLK13",
|
||||
"CLK_FEED_CK_BUFG_CASC1",
|
||||
"CLK_FEED_R_CK_BUFG_CASC9",
|
||||
"CLK_FEED_LH8",
|
||||
"CLK_FEED_EE4C2",
|
||||
"CLK_FEED_WW4B3",
|
||||
"CLK_FEED_EE4A3",
|
||||
"CLK_FEED_NW2A2",
|
||||
"CLK_FEED_CK_BUFG_CASC10",
|
||||
"CLK_FEED_WL1END1",
|
||||
"CLK_PMV_BYP2_0",
|
||||
"CLK_FEED_SE4C3",
|
||||
"CLK_FEED_WL1END2",
|
||||
"CLK_PMVIOB_A0",
|
||||
"CLK_PMV_LOGIC_OUTS13_0",
|
||||
"CLK_FEED_LH3",
|
||||
"CLK_PMV_LOGIC_OUTS0_0",
|
||||
"CLK_PMV_IMUX39_0",
|
||||
"CLK_FEED_R_CK_GCLK13",
|
||||
"CLK_FEED_NW2A3",
|
||||
"CLK_FEED_LH4",
|
||||
"CLK_FEED_EE4B0",
|
||||
"CLK_PMV_IMUX29_0",
|
||||
"CLK_FEED_SE4C2",
|
||||
"CLK_FEED_SW2A3",
|
||||
"CLK_FEED_EE4BEG3",
|
||||
"CLK_FEED_CK_GCLK15",
|
||||
"CLK_FEED_R_CK_GCLK1",
|
||||
"CLK_FEED_R_CK_GCLK15",
|
||||
"CLK_FEED_R_CK_GCLK12",
|
||||
"CLK_PMV_IMUX38_0",
|
||||
"CLK_FEED_R_CK_GCLK28",
|
||||
"CLK_FEED_CK_BUFG_CASC17",
|
||||
"CLK_PMV_LOGIC_OUTS10_0",
|
||||
"CLK_PMV_CLK1_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC13",
|
||||
"CLK_PMV_IMUX2_0",
|
||||
"CLK_FEED_NW4END2",
|
||||
"CLK_FEED_WW4END2",
|
||||
"CLK_PMV_LOGIC_OUTS11_0",
|
||||
"CLK_PMV_IMUX3_0",
|
||||
"CLK_FEED_NE2A3",
|
||||
"CLK_FEED_NW2A3",
|
||||
"CLK_FEED_CK_BUFG_CASC10",
|
||||
"CLK_FEED_R_CK_BUFG_CASC9",
|
||||
"CLK_FEED_SW4A0",
|
||||
"CLK_FEED_SE4BEG1",
|
||||
"CLK_PMV_FAN7_0",
|
||||
"CLK_FEED_SE2A2",
|
||||
"CLK_FEED_R_CK_BUFG_CASC27",
|
||||
"CLK_FEED_NE2A0",
|
||||
"CLK_FEED_SW4A3",
|
||||
"CLK_FEED_NW2A0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC19",
|
||||
"CLK_PMV_BYP5_0",
|
||||
"CLK_FEED_NE4BEG3",
|
||||
"CLK_PMVIOB_A1",
|
||||
"CLK_FEED_SE4BEG3",
|
||||
"CLK_PMV_IMUX5_0",
|
||||
"CLK_FEED_CK_BUFG_CASC29",
|
||||
"CLK_PMV_BYP6_0",
|
||||
"CLK_FEED_CK_GCLK26",
|
||||
"CLK_FEED_R_CK_GCLK5",
|
||||
"CLK_FEED_R_CK_BUFG_CASC12",
|
||||
"CLK_FEED_LH10",
|
||||
"CLK_FEED_SE4C3",
|
||||
"CLK_FEED_R_CK_BUFG_CASC14",
|
||||
"CLK_FEED_R_CK_GCLK14",
|
||||
"CLK_PMV_FAN1_0",
|
||||
"CLK_FEED_NW2A2",
|
||||
"CLK_PMVIOB_A0",
|
||||
"CLK_FEED_NW4END2",
|
||||
"CLK_PMV_IMUX32_0",
|
||||
"CLK_PMV_BYP3_0",
|
||||
"CLK_PMV_LOGIC_OUTS1_0",
|
||||
"CLK_FEED_R_CK_GCLK17",
|
||||
"CLK_FEED_R_CK_BUFG_CASC17",
|
||||
"CLK_FEED_R_CK_GCLK18",
|
||||
"CLK_FEED_R_CK_BUFG_CASC24",
|
||||
"CLK_FEED_CK_BUFG_CASC4",
|
||||
"CLK_PMV_LOGIC_OUTS13_0",
|
||||
"CLK_FEED_CK_BUFG_CASC18",
|
||||
"CLK_FEED_LH9",
|
||||
"CLK_FEED_NW4END1",
|
||||
"CLK_FEED_LH4",
|
||||
"CLK_PMV_IMUX37_0",
|
||||
"CLK_PMV_LOGIC_OUTS15_0",
|
||||
"CLK_FEED_NW4A2",
|
||||
"CLK_FEED_EE2BEG1",
|
||||
"CLK_PMV_IMUX2_0",
|
||||
"CLK_FEED_EE4BEG1",
|
||||
"CLK_FEED_CK_GCLK30",
|
||||
"CLK_PMVIOB_ODIV2",
|
||||
"CLK_PMV_IMUX8_0",
|
||||
"CLK_FEED_CK_GCLK22",
|
||||
"CLK_FEED_CK_GCLK16",
|
||||
"CLK_PMV_IMUX20_0",
|
||||
"CLK_FEED_R_CK_GCLK2",
|
||||
"CLK_PMV_FAN0_0",
|
||||
"CLK_FEED_LH1",
|
||||
"CLK_FEED_R_CK_GCLK23",
|
||||
"CLK_PMV_LOGIC_OUTS7_0",
|
||||
"CLK_PMV_IMUX31_0",
|
||||
"CLK_FEED_LH5",
|
||||
"CLK_FEED_EE2A0",
|
||||
"CLK_FEED_WW4B0",
|
||||
"CLK_PMV_BYP2_0",
|
||||
"CLK_FEED_SE4BEG2",
|
||||
"CLK_FEED_NW4END3",
|
||||
"CLK_FEED_NE4BEG2",
|
||||
"CLK_PMVIOB_O",
|
||||
"CLK_PMV_LOGIC_OUTS14_0",
|
||||
"CLK_PMV_CLK1_0",
|
||||
"CLK_FEED_NE4C3",
|
||||
"CLK_FEED_R_CK_GCLK25",
|
||||
"CLK_FEED_EE2BEG2",
|
||||
"CLK_PMV_IMUX43_0",
|
||||
"CLK_FEED_WL1END2",
|
||||
"CLK_FEED_CK_GCLK0",
|
||||
"CLK_PMV_CLK0_0",
|
||||
"CLK_FEED_R_CK_GCLK10",
|
||||
"CLK_PMV_LOGIC_OUTS0_0",
|
||||
"CLK_PMV_IMUX47_0",
|
||||
"CLK_FEED_CK_GCLK20",
|
||||
"CLK_FEED_ER1BEG3",
|
||||
"CLK_FEED_WW4A1",
|
||||
"CLK_FEED_CK_BUFG_CASC17",
|
||||
"CLK_FEED_CK_GCLK23",
|
||||
"CLK_FEED_LH2",
|
||||
"CLK_FEED_R_CK_GCLK3",
|
||||
"CLK_FEED_EE4B1",
|
||||
"CLK_FEED_R_CK_GCLK7",
|
||||
"CLK_FEED_LH8",
|
||||
"CLK_FEED_LH3",
|
||||
"CLK_FEED_NW2A1",
|
||||
"CLK_FEED_LH11",
|
||||
"CLK_FEED_R_CK_BUFG_CASC29",
|
||||
"CLK_FEED_CK_BUFG_CASC5",
|
||||
"CLK_PMV_IMUX35_0",
|
||||
"CLK_PMV_IMUX0_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC23",
|
||||
"CLK_FEED_CK_GCLK3",
|
||||
"CLK_FEED_WL1END3",
|
||||
"CLK_FEED_R_CK_BUFG_CASC15",
|
||||
"CLK_FEED_ER1BEG2",
|
||||
"CLK_FEED_CK_BUFG_CASC30",
|
||||
"CLK_PMV_LOGIC_OUTS2_0",
|
||||
"CLK_PMV_IMUX17_0",
|
||||
"CLK_FEED_EL1BEG3",
|
||||
"CLK_FEED_R_CK_GCLK16",
|
||||
"CLK_PMV_IMUX36_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC7",
|
||||
"CLK_FEED_EE4BEG2",
|
||||
"CLK_PMV_FAN5_0",
|
||||
"CLK_FEED_CK_GCLK19",
|
||||
"CLK_PMV_IMUX38_0",
|
||||
"CLK_PMV_IMUX10_0",
|
||||
"CLK_FEED_CK_GCLK11",
|
||||
"CLK_FEED_CK_BUFG_CASC21",
|
||||
"CLK_FEED_EE2BEG3",
|
||||
"CLK_FEED_SW4END0",
|
||||
"CLK_PMV_LOGIC_OUTS10_0",
|
||||
"CLK_PMV_LOGIC_OUTS19_0",
|
||||
"CLK_FEED_R_CK_GCLK1",
|
||||
"CLK_FEED_WL1END1",
|
||||
"CLK_FEED_R_CK_GCLK13",
|
||||
"CLK_FEED_EE4B2",
|
||||
"CLK_FEED_R_CK_BUFG_CASC4",
|
||||
"CLK_FEED_R_CK_GCLK28",
|
||||
"CLK_FEED_CK_GCLK4",
|
||||
"CLK_FEED_R_CK_BUFG_CASC8",
|
||||
"CLK_PMV_IMUX15_0",
|
||||
"CLK_PMV_IMUX19_0",
|
||||
"CLK_PMV_IMUX29_0",
|
||||
"CLK_FEED_CK_GCLK6",
|
||||
"CLK_FEED_EE4C3",
|
||||
"CLK_PMV_LOGIC_OUTS22_0",
|
||||
"CLK_FEED_NW4A0",
|
||||
"CLK_FEED_WW2END0",
|
||||
"CLK_FEED_SE2A0",
|
||||
"CLK_FEED_LH6",
|
||||
"CLK_FEED_MONITOR_P",
|
||||
"CLK_FEED_SE4C2",
|
||||
"CLK_PMV_LOGIC_OUTS6_0",
|
||||
"CLK_PMV_BYP0_0",
|
||||
"CLK_FEED_WW2END3",
|
||||
"CLK_FEED_R_CK_BUFG_CASC18",
|
||||
"CLK_FEED_WW4B2",
|
||||
"CLK_FEED_R_CK_GCLK27",
|
||||
"CLK_PMV_FAN4_0",
|
||||
"CLK_FEED_WR1END1",
|
||||
"CLK_FEED_R_CK_BUFG_CASC28",
|
||||
"CLK_FEED_WW4END0",
|
||||
"CLK_FEED_CK_BUFG_CASC12",
|
||||
"CLK_FEED_SW2A3",
|
||||
"CLK_FEED_WW4C0",
|
||||
"CLK_FEED_SW4END1",
|
||||
"CLK_FEED_LH12",
|
||||
"CLK_FEED_CK_BUFG_CASC7",
|
||||
"CLK_PMV_IMUX16_0",
|
||||
"CLK_FEED_R_CK_GCLK9",
|
||||
"CLK_FEED_CK_BUFG_CASC2",
|
||||
"CLK_PMV_IMUX4_0",
|
||||
"CLK_FEED_CK_BUFG_CASC9",
|
||||
"CLK_FEED_NW4END0",
|
||||
"CLK_FEED_CK_BUFG_CASC28",
|
||||
"CLK_FEED_R_CK_BUFG_CASC5",
|
||||
"CLK_PMV_IMUX40_0",
|
||||
"CLK_PMV_LOGIC_OUTS16_0",
|
||||
"CLK_FEED_R_CK_GCLK30",
|
||||
"CLK_FEED_R_CK_GCLK21",
|
||||
"CLK_FEED_R_CK_BUFG_CASC10",
|
||||
"CLK_PMV_IMUX34_0",
|
||||
"CLK_FEED_EL1BEG1",
|
||||
"CLK_FEED_CK_BUFG_CASC20",
|
||||
"CLK_FEED_NE4C0",
|
||||
"CLK_FEED_WW4END1",
|
||||
"CLK_FEED_CK_BUFG_CASC25",
|
||||
"CLK_PMV_LOGIC_OUTS3_0",
|
||||
"CLK_FEED_ER1BEG1",
|
||||
"CLK_PMV_IMUX25_0",
|
||||
"CLK_PMV_LOGIC_OUTS12_0",
|
||||
"CLK_FEED_CK_BUFG_CASC19",
|
||||
"CLK_FEED_EE4A0",
|
||||
"CLK_FEED_SW2A0",
|
||||
"CLK_FEED_CK_BUFG_CASC22",
|
||||
"CLK_FEED_NW4A3",
|
||||
"CLK_PMV_BYP7_0",
|
||||
"CLK_PMV_FAN6_0",
|
||||
"CLK_FEED_CK_GCLK25",
|
||||
"CLK_PMV_LOGIC_OUTS5_0",
|
||||
"CLK_PMV_LOGIC_OUTS9_0",
|
||||
"CLK_FEED_CK_GCLK5",
|
||||
"CLK_FEED_WR1END0",
|
||||
"CLK_PMV_IMUX42_0",
|
||||
"CLK_FEED_SW4A2",
|
||||
"CLK_FEED_EE4C0",
|
||||
"CLK_PMV_LOGIC_OUTS21_0",
|
||||
"CLK_FEED_CK_BUFG_CASC11",
|
||||
"CLK_FEED_EL1BEG2",
|
||||
"CLK_FEED_WR1END3",
|
||||
"CLK_FEED_CK_BUFG_CASC3",
|
||||
"CLK_FEED_CK_GCLK15",
|
||||
"CLK_FEED_MONITOR_N",
|
||||
"CLK_PMV_IMUX3_0",
|
||||
"CLK_PMV_LOGIC_OUTS4_0",
|
||||
"CLK_PMV_BYP1_0",
|
||||
"CLK_FEED_NE4C2",
|
||||
"CLK_FEED_CK_BUFG_CASC1",
|
||||
"CLK_FEED_EE2A3",
|
||||
"CLK_PMVIOB_EN",
|
||||
"CLK_FEED_WW2A3",
|
||||
"CLK_FEED_WW2END1",
|
||||
"CLK_FEED_R_CK_GCLK12",
|
||||
"CLK_FEED_CK_GCLK18",
|
||||
"CLK_FEED_WW2END2",
|
||||
"CLK_PMV_IMUX41_0",
|
||||
"CLK_FEED_SW4A1",
|
||||
"CLK_FEED_SE4C1",
|
||||
"CLK_PMV_IMUX26_0",
|
||||
"CLK_FEED_CK_BUFG_CASC14",
|
||||
"CLK_FEED_EE4B0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC6",
|
||||
"CLK_FEED_R_CK_BUFG_CASC31",
|
||||
"CLK_FEED_R_CK_GCLK0",
|
||||
"CLK_PMV_IMUX46_0",
|
||||
"CLK_FEED_CK_GCLK10",
|
||||
"CLK_FEED_CK_GCLK27",
|
||||
"CLK_FEED_WW4A2",
|
||||
"CLK_PMV_LOGIC_OUTS17_0",
|
||||
"CLK_FEED_R_CK_GCLK29",
|
||||
"CLK_FEED_R_CK_BUFG_CASC20",
|
||||
"CLK_FEED_R_CK_GCLK15",
|
||||
"CLK_FEED_R_CK_GCLK31",
|
||||
"CLK_FEED_CK_GCLK29",
|
||||
"CLK_PMV_LOGIC_OUTS11_0",
|
||||
"CLK_FEED_R_CK_GCLK11",
|
||||
"CLK_FEED_CK_BUFG_CASC27",
|
||||
"CLK_FEED_CK_BUFG_CASC16",
|
||||
"CLK_FEED_CK_BUFG_CASC15",
|
||||
"CLK_FEED_R_CK_BUFG_CASC1",
|
||||
"CLK_PMV_IMUX33_0",
|
||||
"CLK_FEED_CK_BUFG_CASC26",
|
||||
"CLK_FEED_R_CK_BUFG_CASC3",
|
||||
"CLK_PMV_IMUX42_0"
|
||||
"CLK_PMV_IMUX21_0",
|
||||
"CLK_FEED_CK_GCLK21",
|
||||
"CLK_FEED_NE2A2",
|
||||
"CLK_FEED_WW2A0",
|
||||
"CLK_PMV_IMUX11_0",
|
||||
"CLK_PMV_IMUX24_0",
|
||||
"CLK_PMV_IMUX1_0",
|
||||
"CLK_PMV_LOGIC_OUTS20_0",
|
||||
"CLK_PMV_FAN2_0",
|
||||
"CLK_FEED_EE2A2",
|
||||
"CLK_PMV_IMUX27_0",
|
||||
"CLK_FEED_LH7",
|
||||
"CLK_FEED_R_CK_BUFG_CASC21",
|
||||
"CLK_FEED_EE4A1",
|
||||
"CLK_FEED_CK_GCLK2",
|
||||
"CLK_FEED_WW4B1",
|
||||
"CLK_FEED_R_CK_BUFG_CASC0",
|
||||
"CLK_FEED_NW4A1",
|
||||
"CLK_PMV_LOGIC_OUTS23_0",
|
||||
"CLK_FEED_SW4END3",
|
||||
"CLK_FEED_R_CK_GCLK24",
|
||||
"CLK_PMVIOB_ODIV4",
|
||||
"CLK_FEED_EE4A2",
|
||||
"CLK_FEED_CK_GCLK28",
|
||||
"CLK_FEED_WW4END2",
|
||||
"CLK_FEED_EL1BEG0",
|
||||
"CLK_PMV_LOGIC_OUTS18_0",
|
||||
"CLK_FEED_CK_BUFG_CASC0",
|
||||
"CLK_FEED_CK_BUFG_CASC31",
|
||||
"CLK_FEED_SE4BEG0",
|
||||
"CLK_FEED_WW4C2",
|
||||
"CLK_FEED_WR1END2",
|
||||
"CLK_FEED_CK_BUFG_CASC6",
|
||||
"CLK_FEED_CK_GCLK24",
|
||||
"CLK_FEED_ER1BEG0",
|
||||
"CLK_PMV_IMUX12_0",
|
||||
"CLK_FEED_WW4C1",
|
||||
"CLK_FEED_CK_GCLK8",
|
||||
"CLK_FEED_SW4END2",
|
||||
"CLK_PMV_IMUX22_0",
|
||||
"CLK_PMV_BYP4_0",
|
||||
"CLK_FEED_R_CK_GCLK20",
|
||||
"CLK_FEED_SE2A3",
|
||||
"CLK_FEED_EE2A1",
|
||||
"CLK_FEED_R_CK_GCLK4",
|
||||
"CLK_FEED_EE4A3",
|
||||
"CLK_FEED_R_CK_BUFG_CASC13",
|
||||
"CLK_FEED_R_CK_GCLK19",
|
||||
"CLK_PMV_IMUX45_0",
|
||||
"CLK_FEED_CK_BUFG_CASC8",
|
||||
"CLK_FEED_CK_GCLK14",
|
||||
"CLK_FEED_WW2A1",
|
||||
"CLK_PMV_IMUX9_0",
|
||||
"CLK_PMV_IMUX7_0",
|
||||
"CLK_PMV_IMUX39_0",
|
||||
"CLK_FEED_CK_GCLK17",
|
||||
"CLK_PMV_CTRL0_0",
|
||||
"CLK_PMV_IMUX23_0",
|
||||
"CLK_PMV_IMUX18_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC22",
|
||||
"CLK_FEED_EE4B3",
|
||||
"CLK_PMV_IMUX14_0",
|
||||
"CLK_FEED_EE4C1",
|
||||
"CLK_FEED_SW2A2",
|
||||
"CLK_FEED_NE4C1",
|
||||
"CLK_FEED_R_CK_BUFG_CASC26",
|
||||
"CLK_FEED_SE2A1",
|
||||
"CLK_FEED_CK_GCLK7",
|
||||
"CLK_FEED_CK_GCLK1",
|
||||
"CLK_FEED_CK_GCLK9",
|
||||
"CLK_FEED_WW4C3",
|
||||
"CLK_FEED_R_CK_GCLK22",
|
||||
"CLK_FEED_CK_BUFG_CASC23",
|
||||
"CLK_FEED_EE4BEG0",
|
||||
"CLK_FEED_CK_BUFG_CASC24",
|
||||
"CLK_FEED_WW4A0",
|
||||
"CLK_PMV_IMUX44_0",
|
||||
"CLK_FEED_WW2A2",
|
||||
"CLK_FEED_NE2A1",
|
||||
"CLK_FEED_CK_GCLK31",
|
||||
"CLK_PMV_CTRL1_0",
|
||||
"CLK_PMV_IMUX13_0",
|
||||
"CLK_FEED_NE4BEG1",
|
||||
"CLK_FEED_R_CK_GCLK8",
|
||||
"CLK_PMV_LOGIC_OUTS8_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC16",
|
||||
"CLK_FEED_EE4C2",
|
||||
"CLK_PMV_IMUX6_0",
|
||||
"CLK_FEED_EE4BEG3",
|
||||
"CLK_PMV_IMUX30_0",
|
||||
"CLK_FEED_CK_BUFG_CASC13",
|
||||
"CLK_FEED_WW4B3",
|
||||
"CLK_FEED_R_CK_GCLK26",
|
||||
"CLK_PMV_IMUX28_0",
|
||||
"CLK_FEED_NE4BEG0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC30",
|
||||
"CLK_FEED_SE4C0",
|
||||
"CLK_FEED_CK_GCLK13",
|
||||
"CLK_FEED_WW4A3",
|
||||
"CLK_FEED_EE2BEG0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC2",
|
||||
"CLK_FEED_R_CK_BUFG_CASC25",
|
||||
"CLK_FEED_R_CK_BUFG_CASC11",
|
||||
"CLK_FEED_SW2A1"
|
||||
],
|
||||
"tile_type": "CLK_PMVIOB",
|
||||
"sites": []
|
||||
|
|
|
|||
|
|
@ -1,70 +1,70 @@
|
|||
{
|
||||
"pips": {},
|
||||
"wires": [
|
||||
"CLK_TERM_GCLK2",
|
||||
"CLK_TERM_R_GCLK0",
|
||||
"CLK_TERM_GCLK3",
|
||||
"CLK_TERM_R_GCLK26",
|
||||
"CLK_TERM_R_GCLK28",
|
||||
"CLK_TERM_GCLK16",
|
||||
"CLK_TERM_GCLK6",
|
||||
"CLK_TERM_GCLK1",
|
||||
"CLK_TERM_R_GCLK25",
|
||||
"CLK_TERM_GCLK14",
|
||||
"CLK_TERM_R_GCLK30",
|
||||
"CLK_TERM_GCLK26",
|
||||
"CLK_TERM_GCLK24",
|
||||
"CLK_TERM_GCLK7",
|
||||
"CLK_TERM_R_GCLK13",
|
||||
"CLK_TERM_R_GCLK29",
|
||||
"CLK_TERM_R_GCLK10",
|
||||
"CLK_TERM_R_GCLK5",
|
||||
"CLK_TERM_GCLK21",
|
||||
"CLK_TERM_R_GCLK18",
|
||||
"CLK_TERM_R_GCLK14",
|
||||
"CLK_TERM_GCLK9",
|
||||
"CLK_TERM_GCLK15",
|
||||
"CLK_TERM_GCLK29",
|
||||
"CLK_TERM_R_GCLK12",
|
||||
"CLK_TERM_GCLK19",
|
||||
"CLK_TERM_R_GCLK21",
|
||||
"CLK_TERM_GCLK31",
|
||||
"CLK_TERM_GCLK10",
|
||||
"CLK_TERM_GCLK17",
|
||||
"CLK_TERM_R_GCLK22",
|
||||
"CLK_TERM_GCLK8",
|
||||
"CLK_TERM_R_GCLK9",
|
||||
"CLK_TERM_GCLK22",
|
||||
"CLK_TERM_R_GCLK31",
|
||||
"CLK_TERM_GCLK20",
|
||||
"CLK_TERM_R_GCLK17",
|
||||
"CLK_TERM_R_GCLK11",
|
||||
"CLK_TERM_GCLK0",
|
||||
"CLK_TERM_GCLK30",
|
||||
"CLK_TERM_GCLK4",
|
||||
"CLK_TERM_R_GCLK27",
|
||||
"CLK_TERM_R_GCLK4",
|
||||
"CLK_TERM_R_GCLK16",
|
||||
"CLK_TERM_R_GCLK20",
|
||||
"CLK_TERM_GCLK13",
|
||||
"CLK_TERM_GCLK18",
|
||||
"CLK_TERM_GCLK23",
|
||||
"CLK_TERM_R_GCLK2",
|
||||
"CLK_TERM_GCLK5",
|
||||
"CLK_TERM_R_GCLK19",
|
||||
"CLK_TERM_GCLK21",
|
||||
"CLK_TERM_R_GCLK3",
|
||||
"CLK_TERM_R_GCLK24",
|
||||
"CLK_TERM_GCLK27",
|
||||
"CLK_TERM_R_GCLK7",
|
||||
"CLK_TERM_R_GCLK9",
|
||||
"CLK_TERM_R_GCLK30",
|
||||
"CLK_TERM_GCLK25",
|
||||
"CLK_TERM_R_GCLK4",
|
||||
"CLK_TERM_GCLK16",
|
||||
"CLK_TERM_GCLK12",
|
||||
"CLK_TERM_R_GCLK15",
|
||||
"CLK_TERM_R_GCLK16",
|
||||
"CLK_TERM_R_GCLK23",
|
||||
"CLK_TERM_R_GCLK1",
|
||||
"CLK_TERM_R_GCLK6",
|
||||
"CLK_TERM_GCLK28",
|
||||
"CLK_TERM_R_GCLK8",
|
||||
"CLK_TERM_GCLK12",
|
||||
"CLK_TERM_GCLK25",
|
||||
"CLK_TERM_GCLK7",
|
||||
"CLK_TERM_R_GCLK19",
|
||||
"CLK_TERM_GCLK4",
|
||||
"CLK_TERM_GCLK22",
|
||||
"CLK_TERM_GCLK9",
|
||||
"CLK_TERM_GCLK8",
|
||||
"CLK_TERM_GCLK13",
|
||||
"CLK_TERM_GCLK29",
|
||||
"CLK_TERM_GCLK5",
|
||||
"CLK_TERM_GCLK20",
|
||||
"CLK_TERM_R_GCLK28",
|
||||
"CLK_TERM_R_GCLK0",
|
||||
"CLK_TERM_GCLK19",
|
||||
"CLK_TERM_GCLK1",
|
||||
"CLK_TERM_R_GCLK10",
|
||||
"CLK_TERM_GCLK31",
|
||||
"CLK_TERM_GCLK30",
|
||||
"CLK_TERM_GCLK6",
|
||||
"CLK_TERM_GCLK11",
|
||||
"CLK_TERM_R_GCLK15"
|
||||
"CLK_TERM_R_GCLK13",
|
||||
"CLK_TERM_R_GCLK22",
|
||||
"CLK_TERM_GCLK26",
|
||||
"CLK_TERM_GCLK23",
|
||||
"CLK_TERM_R_GCLK31",
|
||||
"CLK_TERM_R_GCLK14",
|
||||
"CLK_TERM_GCLK15",
|
||||
"CLK_TERM_GCLK28",
|
||||
"CLK_TERM_R_GCLK20",
|
||||
"CLK_TERM_GCLK14",
|
||||
"CLK_TERM_R_GCLK29",
|
||||
"CLK_TERM_R_GCLK2",
|
||||
"CLK_TERM_R_GCLK6",
|
||||
"CLK_TERM_R_GCLK27",
|
||||
"CLK_TERM_GCLK17",
|
||||
"CLK_TERM_R_GCLK7",
|
||||
"CLK_TERM_R_GCLK8",
|
||||
"CLK_TERM_GCLK24",
|
||||
"CLK_TERM_R_GCLK24",
|
||||
"CLK_TERM_R_GCLK5",
|
||||
"CLK_TERM_R_GCLK21",
|
||||
"CLK_TERM_GCLK2",
|
||||
"CLK_TERM_GCLK10",
|
||||
"CLK_TERM_GCLK18",
|
||||
"CLK_TERM_R_GCLK12",
|
||||
"CLK_TERM_R_GCLK18",
|
||||
"CLK_TERM_GCLK3",
|
||||
"CLK_TERM_R_GCLK26",
|
||||
"CLK_TERM_GCLK27",
|
||||
"CLK_TERM_R_GCLK25",
|
||||
"CLK_TERM_R_GCLK17",
|
||||
"CLK_TERM_GCLK0"
|
||||
],
|
||||
"tile_type": "CLK_TERM",
|
||||
"sites": []
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -1,229 +1,229 @@
|
|||
{
|
||||
"pips": {},
|
||||
"wires": [
|
||||
"CMT_PMV_BYP5",
|
||||
"CMT_PMV_CLK0",
|
||||
"CMT_PMV_IMUX41",
|
||||
"CMT_PMV_NW4END0",
|
||||
"CMT_PMV_LOGIC_OUTS21",
|
||||
"CMT_PMV_IMUX30",
|
||||
"CMT_PMV_ER1BEG1",
|
||||
"CMT_PMV_NW2A1",
|
||||
"CMT_PMV_IMUX39",
|
||||
"CMT_PMV_CTRL1",
|
||||
"CMT_PMV_SW4A1",
|
||||
"CMT_PMV_SE4BEG3",
|
||||
"CMT_PMV_IMUX3",
|
||||
"CMT_PMV_CTRL0",
|
||||
"CMT_PMV_WW4END1",
|
||||
"CMT_PMV_EE4B3",
|
||||
"CMT_PMV_LH10",
|
||||
"CMT_PMV_BYP6",
|
||||
"CMT_PMV_LOGIC_OUTS5",
|
||||
"CMT_PMV_LOGIC_OUTS0",
|
||||
"CMT_PMV_EE4BEG3",
|
||||
"CMT_PMV_WW2END2",
|
||||
"CMT_PMV_BYP1",
|
||||
"CMT_PMV_BYP2",
|
||||
"CMT_PMV_IMUX35",
|
||||
"CMT_PMV_IMUX8",
|
||||
"CMT_PMV_LH11",
|
||||
"CMT_PMV_NE4BEG2",
|
||||
"CMT_PMV_WW4A1",
|
||||
"CMT_PMV_NW2A3",
|
||||
"CMT_PMV_CLK1",
|
||||
"CMT_PMV_WW4B1",
|
||||
"CMT_PMV_IMUX6",
|
||||
"CMT_PMV_NW4END2",
|
||||
"CMT_PMV_EE2BEG0",
|
||||
"CMT_PMV_IMUX15",
|
||||
"CMT_PMV_WR1END0",
|
||||
"CMT_PMV_SE2A2",
|
||||
"CMT_PMV_LOGIC_OUTS10",
|
||||
"CMT_PMV_SE4C0",
|
||||
"CMT_PMV_IMUX11",
|
||||
"CMT_PMV_FAN3",
|
||||
"CMT_PMV_IMUX40",
|
||||
"CMT_PMV_SE4C1",
|
||||
"CMT_PMV_EL1BEG1",
|
||||
"CMT_PMV_LH7",
|
||||
"CMT_PMV_EE4C1",
|
||||
"CMT_PMV_LH3",
|
||||
"CMT_PMV_EE4B3",
|
||||
"CMT_PMV_WR1END3",
|
||||
"CMT_PMV_SE2A3",
|
||||
"CMT_PMV_LOGIC_OUTS2",
|
||||
"CMT_PMV_LOGIC_OUTS15",
|
||||
"CMT_PMV_LOGIC_OUTS13",
|
||||
"CMT_PMV_LOGIC_OUTS18",
|
||||
"CMT_PMV_IMUX24",
|
||||
"CMT_PMV_LH6",
|
||||
"CMT_PMV_IMUX33",
|
||||
"CMT_PMV_BYP7",
|
||||
"CMT_PMV_NW2A2",
|
||||
"CMT_PMV_NE4BEG0",
|
||||
"CMT_PMV_LH3",
|
||||
"CMT_PMV_WW4B1",
|
||||
"CMT_PMV_IMUX28",
|
||||
"CMT_PMV_LH7",
|
||||
"CMT_PMV_ER1BEG3",
|
||||
"L_TERM_INT_PHASER_TO_IO_ICLKDIV",
|
||||
"CMT_PMV_IMUX41",
|
||||
"CMT_PMV_EE4BEG2",
|
||||
"CMT_PMV_WW4A0",
|
||||
"CMT_PMV_IMUX31",
|
||||
"CMT_PMV_WL1END2",
|
||||
"CMT_PMV_LOGIC_OUTS6",
|
||||
"CMT_PMV_IMUX45",
|
||||
"CMT_PMV_LH12",
|
||||
"CMT_PMV_EE4A0",
|
||||
"CMT_PMV_BYP5",
|
||||
"CMT_PMV_IMUX25",
|
||||
"CMT_PMV_EE4BEG0",
|
||||
"CMT_PMV_MONITOR_P",
|
||||
"CMT_PMV_IMUX11",
|
||||
"CMT_PMV_EE2A3",
|
||||
"CMT_PMV_LOGIC_OUTS8",
|
||||
"CMT_PMV_LOGIC_OUTS7",
|
||||
"CMT_PMV_EE4BEG3",
|
||||
"CMT_PMV_EE2BEG1",
|
||||
"CMT_PMV_IMUX40",
|
||||
"CMT_PMV_NE2A1",
|
||||
"CMT_PMV_SW4END3",
|
||||
"CMT_PMV_LOGIC_OUTS22",
|
||||
"L_TERM_INT_PHASER_TO_IO_OCLK1X_90",
|
||||
"CMT_PMV_ER1BEG1",
|
||||
"CMT_PMV_EE2BEG3",
|
||||
"CMT_PMV_EE4A2",
|
||||
"CMT_PMV_EL1BEG3",
|
||||
"CMT_PMV_IMUX35",
|
||||
"CMT_PMV_SE4BEG1",
|
||||
"CMT_PMV_NW4END1",
|
||||
"CMT_PMV_IMUX42",
|
||||
"CMT_PMV_IMUX26",
|
||||
"CMT_PMV_WW2END3",
|
||||
"CMT_PMV_BYP2",
|
||||
"CMT_PMV_EL1BEG0",
|
||||
"CMT_PMV_EE2A2",
|
||||
"CMT_PMV_IMUX6",
|
||||
"CMT_PMV_NE2A2",
|
||||
"CMT_PMV_IMUX5",
|
||||
"CMT_PMV_EE4B1",
|
||||
"CMT_PMV_EL1BEG2",
|
||||
"CMT_PMV_IMUX18",
|
||||
"CMT_PMV_LOGIC_OUTS14",
|
||||
"CMT_PMV_FAN1",
|
||||
"CMT_PMV_IMUX2",
|
||||
"CMT_PMV_LOGIC_OUTS1",
|
||||
"CMT_PMV_WW2A0",
|
||||
"CMT_PMV_NE2A3",
|
||||
"CMT_PMV_LOGIC_OUTS13",
|
||||
"CMT_PMV_IMUX4",
|
||||
"CMT_PMV_NW4END0",
|
||||
"CMT_PMV_IMUX36",
|
||||
"CMT_PMV_FAN2",
|
||||
"CMT_PMV_IMUX22",
|
||||
"CMT_PMV_NE4C2",
|
||||
"CMT_PMV_WL1END0",
|
||||
"CMT_PMV_EE4C3",
|
||||
"CMT_PMV_EE2A1",
|
||||
"CMT_PMV_LOGIC_OUTS20",
|
||||
"L_TERM_INT_PHASER_TO_IO_OCLK",
|
||||
"CMT_PMV_SE2A1",
|
||||
"CMT_PMV_LOGIC_OUTS3",
|
||||
"CMT_PMV_LH6",
|
||||
"CMT_PMV_SW4END2",
|
||||
"CMT_PMV_WW4END0",
|
||||
"CMT_PMV_LOGIC_OUTS9",
|
||||
"CMT_PMV_WW2END0",
|
||||
"CMT_PMV_SE4C3",
|
||||
"CMT_PMV_IMUX12",
|
||||
"CMT_PMV_LOGIC_OUTS15",
|
||||
"CMT_PMV_FAN6",
|
||||
"CMT_PMV_FAN7",
|
||||
"CMT_PMV_LH10",
|
||||
"CMT_PMV_WW4A1",
|
||||
"CMT_PMV_LOGIC_OUTS23",
|
||||
"CMT_PMV_ER1BEG2",
|
||||
"CMT_PMV_WW4C3",
|
||||
"CMT_PMV_LOGIC_OUTS21",
|
||||
"CMT_PMV_WW2A1",
|
||||
"CMT_PMV_SW4A0",
|
||||
"L_TERM_INT_PHASER_TO_IO_OCLKDIV",
|
||||
"CMT_PMV_WL1END3",
|
||||
"CMT_PMV_LOGIC_OUTS16",
|
||||
"CMT_PMV_LH8",
|
||||
"CMT_PMV_IMUX29",
|
||||
"CMT_PMV_LOGIC_OUTS4",
|
||||
"CMT_PMV_SW4A2",
|
||||
"CMT_PMV_WW2A2",
|
||||
"CMT_PMV_SW2A3",
|
||||
"CMT_PMV_WW4A2",
|
||||
"CMT_PMV_WL1END1",
|
||||
"CMT_PMV_EE4A1",
|
||||
"CMT_PMV_IMUX43",
|
||||
"CMT_PMV_WW4A3",
|
||||
"CMT_PMV_SE4C1",
|
||||
"CMT_PMV_IMUX20",
|
||||
"L_TERM_INT_PHASER_TO_IO_ICLK",
|
||||
"CMT_PMV_NW4A2",
|
||||
"CMT_PMV_SW2A2",
|
||||
"CMT_PMV_LH2",
|
||||
"CMT_PMV_WW2END2",
|
||||
"CMT_PMV_LH5",
|
||||
"CMT_PMV_CTRL0",
|
||||
"CMT_PMV_NW2A0",
|
||||
"CMT_PMV_FAN4",
|
||||
"CMT_PMV_IMUX33",
|
||||
"CMT_PMV_NE4BEG3",
|
||||
"CMT_PMV_LOGIC_OUTS19",
|
||||
"CMT_PMV_IMUX13",
|
||||
"CMT_PMV_SW2A1",
|
||||
"CMT_PMV_IMUX44",
|
||||
"CMT_PMV_NE4C1",
|
||||
"CMT_PMV_IMUX46",
|
||||
"CMT_PMV_NE4C0",
|
||||
"CMT_PMV_WW4END1",
|
||||
"CMT_PMV_IMUX9",
|
||||
"CMT_PMV_SE2A2",
|
||||
"CMT_PMV_WW4C2",
|
||||
"CMT_PMV_BYP6",
|
||||
"CMT_PMV_EE4BEG1",
|
||||
"CMT_PMV_NE4BEG1",
|
||||
"CMT_PMV_IMUX27",
|
||||
"CMT_PMV_EE4A3",
|
||||
"CMT_PMV_FAN7",
|
||||
"CMT_PMV_SE4C3",
|
||||
"CMT_PMV_IMUX43",
|
||||
"CMT_PMV_SE4BEG0",
|
||||
"CMT_PMV_LH1",
|
||||
"CMT_PMV_EE2A0",
|
||||
"CMT_PMV_BYP0",
|
||||
"CMT_PMV_IMUX34",
|
||||
"CMT_PMV_SE2A3",
|
||||
"CMT_PMV_FAN4",
|
||||
"CMT_PMV_SE4BEG3",
|
||||
"CMT_PMV_IMUX0",
|
||||
"CMT_PMV_IMUX17",
|
||||
"CMT_PMV_IMUX36",
|
||||
"CMT_PMV_IMUX2",
|
||||
"CMT_PMV_IMUX22",
|
||||
"CMT_PMV_SW4END1",
|
||||
"CMT_PMV_WL1END0",
|
||||
"CMT_PMV_EL1BEG3",
|
||||
"CMT_PMV_ER1BEG0",
|
||||
"CMT_PMV_NW2A2",
|
||||
"CMT_PMV_SW4A0",
|
||||
"CMT_PMV_WW2A1",
|
||||
"CMT_PMV_IMUX1",
|
||||
"CMT_PMV_WL1END1",
|
||||
"CMT_PMV_LOGIC_OUTS7",
|
||||
"CMT_PMV_EE4B2",
|
||||
"CMT_PMV_BYP7",
|
||||
"CMT_PMV_FAN6",
|
||||
"CMT_PMV_SE2A0",
|
||||
"CMT_PMV_NE4C1",
|
||||
"CMT_PMV_IMUX26",
|
||||
"CMT_PMV_NW4A2",
|
||||
"CMT_PMV_SW4END3",
|
||||
"CMT_PMV_IMUX10",
|
||||
"CMT_PMV_IMUX32",
|
||||
"CMT_PMV_NE2A3",
|
||||
"CMT_PMV_LOGIC_OUTS3",
|
||||
"CMT_PMV_IMUX31",
|
||||
"CMT_PMV_NW4A0",
|
||||
"CMT_PMV_LOGIC_OUTS8",
|
||||
"CMT_PMV_IMUX19",
|
||||
"L_TERM_INT_PHASER_TO_IO_ICLK",
|
||||
"CMT_PMV_LOGIC_OUTS19",
|
||||
"CMT_PMV_WW4END3",
|
||||
"CMT_PMV_IMUX37",
|
||||
"CMT_PMV_LOGIC_OUTS4",
|
||||
"CMT_PMV_BYP4",
|
||||
"CMT_PMV_SW4A3",
|
||||
"CMT_PMV_NE2A0",
|
||||
"CMT_PMV_IMUX16",
|
||||
"CMT_PMV_SW2A3",
|
||||
"CMT_PMV_IMUX9",
|
||||
"CMT_PMV_WW4B2",
|
||||
"CMT_PMV_IMUX21",
|
||||
"CMT_PMV_EE4C2",
|
||||
"CMT_PMV_MONITOR_P",
|
||||
"CMT_PMV_WW4B0",
|
||||
"CMT_PMV_IMUX14",
|
||||
"CMT_PMV_NE4C3",
|
||||
"CMT_PMV_EE4BEG2",
|
||||
"CMT_PMV_NE4BEG0",
|
||||
"CMT_PMV_IMUX4",
|
||||
"CMT_PMV_EE2A1",
|
||||
"CMT_PMV_IMUX12",
|
||||
"CMT_PMV_WW2END0",
|
||||
"CMT_PMV_LOGIC_OUTS23",
|
||||
"CMT_PMV_EE4A1",
|
||||
"CMT_PMV_WR1END2",
|
||||
"CMT_PMV_EE2A2",
|
||||
"CMT_PMV_LOGIC_OUTS9",
|
||||
"CMT_PMV_LH9",
|
||||
"CMT_PMV_WW4C0",
|
||||
"CMT_PMV_NW4END3",
|
||||
"CMT_PMV_WW4A0",
|
||||
"CMT_PMV_EE2BEG2",
|
||||
"CMT_PMV_LH12",
|
||||
"CMT_PMV_WW4C2",
|
||||
"CMT_PMV_SW4END2",
|
||||
"CMT_PMV_LOGIC_OUTS14",
|
||||
"CMT_PMV_IMUX46",
|
||||
"CMT_PMV_WW2END1",
|
||||
"CMT_PMV_EE2BEG1",
|
||||
"CMT_PMV_LOGIC_OUTS1",
|
||||
"CMT_PMV_CTRL1",
|
||||
"CMT_PMV_WW4END2",
|
||||
"CMT_PMV_LH2",
|
||||
"L_TERM_INT_PHASER_TO_IO_OCLK1X_90",
|
||||
"CMT_PMV_SE4BEG2",
|
||||
"CMT_PMV_LOGIC_OUTS20",
|
||||
"CMT_PMV_SW2A2",
|
||||
"CMT_PMV_NW4END1",
|
||||
"CMT_PMV_NW4A3",
|
||||
"CMT_PMV_LOGIC_OUTS11",
|
||||
"CMT_PMV_FAN5",
|
||||
"CMT_PMV_WL1END3",
|
||||
"CMT_PMV_WW4C3",
|
||||
"CMT_PMV_EE4A2",
|
||||
"CMT_PMV_WW2A2",
|
||||
"CMT_PMV_LOGIC_OUTS22",
|
||||
"CMT_PMV_IMUX7",
|
||||
"CMT_PMV_LH4",
|
||||
"CMT_PMV_ER1BEG3",
|
||||
"CMT_PMV_SE2A1",
|
||||
"CMT_PMV_WW4B3",
|
||||
"CMT_PMV_EE4C3",
|
||||
"L_TERM_INT_PHASER_TO_IO_ICLKDIV",
|
||||
"CMT_PMV_WW2END3",
|
||||
"CMT_PMV_FAN0",
|
||||
"CMT_PMV_NW4A1",
|
||||
"CMT_PMV_IMUX38",
|
||||
"CMT_PMV_IMUX20",
|
||||
"CMT_PMV_BYP3",
|
||||
"CMT_PMV_NW2A0",
|
||||
"CMT_PMV_EE4BEG0",
|
||||
"L_TERM_INT_PHASER_TO_IO_OCLKDIV",
|
||||
"CMT_PMV_SW4A2",
|
||||
"CMT_PMV_IMUX42",
|
||||
"CMT_PMV_NE2A1",
|
||||
"L_TERM_INT_PHASER_TO_IO_OCLK",
|
||||
"CMT_PMV_IMUX28",
|
||||
"CMT_PMV_WW2A0",
|
||||
"CMT_PMV_NE2A2",
|
||||
"CMT_PMV_SW2A1",
|
||||
"CMT_PMV_WW4END0",
|
||||
"CMT_PMV_IMUX39",
|
||||
"CMT_PMV_LH5",
|
||||
"CMT_PMV_SE4C2",
|
||||
"CMT_PMV_SW2A0",
|
||||
"CMT_PMV_IMUX45",
|
||||
"CMT_PMV_ER1BEG2",
|
||||
"CMT_PMV_WR1END1",
|
||||
"CMT_PMV_FAN1",
|
||||
"CMT_PMV_EL1BEG0",
|
||||
"CMT_PMV_SE4BEG1",
|
||||
"CMT_PMV_IMUX23",
|
||||
"CMT_PMV_IMUX13",
|
||||
"CMT_PMV_IMUX47",
|
||||
"CMT_PMV_WW4A2",
|
||||
"CMT_PMV_EE4B0",
|
||||
"CMT_PMV_SW4END0",
|
||||
"CMT_PMV_LOGIC_OUTS12",
|
||||
"CMT_PMV_EE2BEG3",
|
||||
"CMT_PMV_LOGIC_OUTS16",
|
||||
"CMT_PMV_MONITOR_N",
|
||||
"CMT_PMV_NE4BEG3",
|
||||
"CMT_PMV_WR1END3",
|
||||
"CMT_PMV_EE2A3",
|
||||
"CMT_PMV_LOGIC_OUTS17",
|
||||
"CMT_PMV_EL1BEG2",
|
||||
"CMT_PMV_WW4END3",
|
||||
"CMT_PMV_ER1BEG0",
|
||||
"CMT_PMV_BYP3",
|
||||
"CMT_PMV_FAN3",
|
||||
"CMT_PMV_NW4END3",
|
||||
"CMT_PMV_IMUX38",
|
||||
"CMT_PMV_FAN0",
|
||||
"CMT_PMV_EE4C1",
|
||||
"CMT_PMV_SE4BEG0",
|
||||
"CMT_PMV_BYP4",
|
||||
"CMT_PMV_IMUX27",
|
||||
"CMT_PMV_WW2A3",
|
||||
"CMT_PMV_SW4A1",
|
||||
"CMT_PMV_EE4A0",
|
||||
"CMT_PMV_IMUX44",
|
||||
"CMT_PMV_WW4A3",
|
||||
"CMT_PMV_EE4C0",
|
||||
"CMT_PMV_NE4C0",
|
||||
"CMT_PMV_IMUX25",
|
||||
"CMT_PMV_NE4C2",
|
||||
"CMT_PMV_IMUX29",
|
||||
"CMT_PMV_WW4B3",
|
||||
"CMT_PMV_LOGIC_OUTS10",
|
||||
"CMT_PMV_EE4B2",
|
||||
"CMT_PMV_NW4END2",
|
||||
"CMT_PMV_MONITOR_N",
|
||||
"CMT_PMV_WW4C0",
|
||||
"CMT_PMV_LOGIC_OUTS11",
|
||||
"CMT_PMV_IMUX21",
|
||||
"CMT_PMV_IMUX1",
|
||||
"CMT_PMV_IMUX7",
|
||||
"CMT_PMV_NW4A0",
|
||||
"CMT_PMV_SW2A0",
|
||||
"CMT_PMV_BYP0",
|
||||
"CMT_PMV_CLK0",
|
||||
"CMT_PMV_NE2A0",
|
||||
"CMT_PMV_IMUX47",
|
||||
"CMT_PMV_EE4B1",
|
||||
"CMT_PMV_LOGIC_OUTS17",
|
||||
"CMT_PMV_WW4B0",
|
||||
"CMT_PMV_WR1END1",
|
||||
"CMT_PMV_LOGIC_OUTS12",
|
||||
"CMT_PMV_SE4BEG2",
|
||||
"CMT_PMV_IMUX14",
|
||||
"CMT_PMV_SE4C0",
|
||||
"CMT_PMV_WW4C1",
|
||||
"CMT_PMV_IMUX18",
|
||||
"CMT_PMV_FAN2"
|
||||
"CMT_PMV_EL1BEG1",
|
||||
"CMT_PMV_CLK1",
|
||||
"CMT_PMV_FAN5",
|
||||
"CMT_PMV_EE4C2",
|
||||
"CMT_PMV_IMUX17",
|
||||
"CMT_PMV_NW4A1",
|
||||
"CMT_PMV_LOGIC_OUTS5",
|
||||
"CMT_PMV_IMUX16",
|
||||
"CMT_PMV_IMUX10",
|
||||
"CMT_PMV_LOGIC_OUTS18",
|
||||
"CMT_PMV_IMUX30",
|
||||
"CMT_PMV_SW4A3",
|
||||
"CMT_PMV_SW4END1",
|
||||
"CMT_PMV_IMUX8",
|
||||
"CMT_PMV_WW4END2",
|
||||
"CMT_PMV_EE2A0",
|
||||
"CMT_PMV_EE2BEG0",
|
||||
"CMT_PMV_IMUX37",
|
||||
"CMT_PMV_IMUX32",
|
||||
"CMT_PMV_SE2A0",
|
||||
"CMT_PMV_IMUX19",
|
||||
"CMT_PMV_LH9",
|
||||
"CMT_PMV_NE4C3",
|
||||
"CMT_PMV_LH4",
|
||||
"CMT_PMV_NW4A3",
|
||||
"CMT_PMV_SE4C2",
|
||||
"CMT_PMV_IMUX0",
|
||||
"CMT_PMV_NE4BEG2",
|
||||
"CMT_PMV_LOGIC_OUTS0",
|
||||
"CMT_PMV_IMUX24",
|
||||
"CMT_PMV_WR1END0",
|
||||
"CMT_PMV_EE4C0",
|
||||
"CMT_PMV_IMUX34",
|
||||
"CMT_PMV_IMUX15",
|
||||
"CMT_PMV_EE2BEG2",
|
||||
"CMT_PMV_NW2A3",
|
||||
"CMT_PMV_IMUX23",
|
||||
"CMT_PMV_SW4END0",
|
||||
"CMT_PMV_WW4B2",
|
||||
"CMT_PMV_LOGIC_OUTS6",
|
||||
"CMT_PMV_NW2A1",
|
||||
"CMT_PMV_WW2END1",
|
||||
"CMT_PMV_LH1",
|
||||
"CMT_PMV_EE4A3",
|
||||
"CMT_PMV_LH11"
|
||||
],
|
||||
"tile_type": "CMT_PMV",
|
||||
"sites": []
|
||||
|
|
|
|||
|
|
@ -1,229 +1,229 @@
|
|||
{
|
||||
"pips": {},
|
||||
"wires": [
|
||||
"CMT_PMV_BYP5",
|
||||
"CMT_PMV_CLK0",
|
||||
"CMT_PMV_IMUX41",
|
||||
"CMT_PMV_NW4END0",
|
||||
"CMT_PMV_LOGIC_OUTS21",
|
||||
"CMT_PMV_IMUX30",
|
||||
"CMT_PMV_ER1BEG1",
|
||||
"CMT_PMV_NW2A1",
|
||||
"CMT_PMV_IMUX39",
|
||||
"CMT_PMV_CTRL1",
|
||||
"CMT_PMV_SW4A1",
|
||||
"CMT_PMV_SE4BEG3",
|
||||
"CMT_PMV_IMUX3",
|
||||
"CMT_PMV_CTRL0",
|
||||
"CMT_PMV_WW4END1",
|
||||
"CMT_PMV_EE4B3",
|
||||
"CMT_PMV_LH10",
|
||||
"CMT_PMV_BYP6",
|
||||
"CMT_PMV_LOGIC_OUTS5",
|
||||
"CMT_PMV_LOGIC_OUTS0",
|
||||
"CMT_PMV_EE4BEG3",
|
||||
"CMT_PMV_WW2END2",
|
||||
"CMT_PMV_BYP1",
|
||||
"CMT_PMV_BYP2",
|
||||
"CMT_PMV_IMUX35",
|
||||
"CMT_PMV_IMUX8",
|
||||
"CMT_PMV_LH11",
|
||||
"CMT_PMV_NE4BEG2",
|
||||
"CMT_PMV_WW4A1",
|
||||
"CMT_PMV_NW2A3",
|
||||
"CMT_PMV_CLK1",
|
||||
"CMT_PMV_WW4B1",
|
||||
"CMT_PMV_IMUX6",
|
||||
"CMT_PMV_NW4END2",
|
||||
"CMT_PMV_EE2BEG0",
|
||||
"CMT_PMV_IMUX15",
|
||||
"CMT_PMV_WR1END0",
|
||||
"CMT_PMV_SE2A2",
|
||||
"CMT_PMV_LOGIC_OUTS10",
|
||||
"CMT_PMV_SE4C0",
|
||||
"CMT_PMV_IMUX11",
|
||||
"CMT_PMV_FAN3",
|
||||
"CMT_PMV_IMUX40",
|
||||
"CMT_PMV_SE4C1",
|
||||
"CMT_PMV_EL1BEG1",
|
||||
"CMT_PMV_LH7",
|
||||
"CMT_PMV_EE4C1",
|
||||
"CMT_PMV_LH3",
|
||||
"CMT_PMV_EE4B3",
|
||||
"CMT_PMV_WR1END3",
|
||||
"CMT_PMV_SE2A3",
|
||||
"CMT_PMV_LOGIC_OUTS2",
|
||||
"CMT_PMV_LOGIC_OUTS15",
|
||||
"CMT_PMV_LOGIC_OUTS13",
|
||||
"CMT_PMV_LOGIC_OUTS18",
|
||||
"CMT_PMV_IMUX24",
|
||||
"CMT_PMV_LH6",
|
||||
"CMT_PMV_IMUX33",
|
||||
"CMT_PMV_BYP7",
|
||||
"CMT_PMV_NW2A2",
|
||||
"CMT_PMV_NE4BEG0",
|
||||
"CMT_PMV_LH3",
|
||||
"CMT_PMV_WW4B1",
|
||||
"CMT_PMV_IMUX28",
|
||||
"CMT_PMV_LH7",
|
||||
"CMT_PMV_ER1BEG3",
|
||||
"L_TERM_INT_PHASER_TO_IO_ICLKDIV",
|
||||
"CMT_PMV_IMUX41",
|
||||
"CMT_PMV_EE4BEG2",
|
||||
"CMT_PMV_WW4A0",
|
||||
"CMT_PMV_IMUX31",
|
||||
"CMT_PMV_WL1END2",
|
||||
"CMT_PMV_LOGIC_OUTS6",
|
||||
"CMT_PMV_IMUX45",
|
||||
"CMT_PMV_LH12",
|
||||
"CMT_PMV_EE4A0",
|
||||
"CMT_PMV_BYP5",
|
||||
"CMT_PMV_IMUX25",
|
||||
"CMT_PMV_EE4BEG0",
|
||||
"CMT_PMV_MONITOR_P",
|
||||
"CMT_PMV_IMUX11",
|
||||
"CMT_PMV_EE2A3",
|
||||
"CMT_PMV_LOGIC_OUTS8",
|
||||
"CMT_PMV_LOGIC_OUTS7",
|
||||
"CMT_PMV_EE4BEG3",
|
||||
"CMT_PMV_EE2BEG1",
|
||||
"CMT_PMV_IMUX40",
|
||||
"CMT_PMV_NE2A1",
|
||||
"CMT_PMV_SW4END3",
|
||||
"CMT_PMV_LOGIC_OUTS22",
|
||||
"L_TERM_INT_PHASER_TO_IO_OCLK1X_90",
|
||||
"CMT_PMV_ER1BEG1",
|
||||
"CMT_PMV_EE2BEG3",
|
||||
"CMT_PMV_EE4A2",
|
||||
"CMT_PMV_EL1BEG3",
|
||||
"CMT_PMV_IMUX35",
|
||||
"CMT_PMV_SE4BEG1",
|
||||
"CMT_PMV_NW4END1",
|
||||
"CMT_PMV_IMUX42",
|
||||
"CMT_PMV_IMUX26",
|
||||
"CMT_PMV_WW2END3",
|
||||
"CMT_PMV_BYP2",
|
||||
"CMT_PMV_EL1BEG0",
|
||||
"CMT_PMV_EE2A2",
|
||||
"CMT_PMV_IMUX6",
|
||||
"CMT_PMV_NE2A2",
|
||||
"CMT_PMV_IMUX5",
|
||||
"CMT_PMV_EE4B1",
|
||||
"CMT_PMV_EL1BEG2",
|
||||
"CMT_PMV_IMUX18",
|
||||
"CMT_PMV_LOGIC_OUTS14",
|
||||
"CMT_PMV_FAN1",
|
||||
"CMT_PMV_IMUX2",
|
||||
"CMT_PMV_LOGIC_OUTS1",
|
||||
"CMT_PMV_WW2A0",
|
||||
"CMT_PMV_NE2A3",
|
||||
"CMT_PMV_LOGIC_OUTS13",
|
||||
"CMT_PMV_IMUX4",
|
||||
"CMT_PMV_NW4END0",
|
||||
"CMT_PMV_IMUX36",
|
||||
"CMT_PMV_FAN2",
|
||||
"CMT_PMV_IMUX22",
|
||||
"CMT_PMV_NE4C2",
|
||||
"CMT_PMV_WL1END0",
|
||||
"CMT_PMV_EE4C3",
|
||||
"CMT_PMV_EE2A1",
|
||||
"CMT_PMV_LOGIC_OUTS20",
|
||||
"L_TERM_INT_PHASER_TO_IO_OCLK",
|
||||
"CMT_PMV_SE2A1",
|
||||
"CMT_PMV_LOGIC_OUTS3",
|
||||
"CMT_PMV_LH6",
|
||||
"CMT_PMV_SW4END2",
|
||||
"CMT_PMV_WW4END0",
|
||||
"CMT_PMV_LOGIC_OUTS9",
|
||||
"CMT_PMV_WW2END0",
|
||||
"CMT_PMV_SE4C3",
|
||||
"CMT_PMV_IMUX12",
|
||||
"CMT_PMV_LOGIC_OUTS15",
|
||||
"CMT_PMV_FAN6",
|
||||
"CMT_PMV_FAN7",
|
||||
"CMT_PMV_LH10",
|
||||
"CMT_PMV_WW4A1",
|
||||
"CMT_PMV_LOGIC_OUTS23",
|
||||
"CMT_PMV_ER1BEG2",
|
||||
"CMT_PMV_WW4C3",
|
||||
"CMT_PMV_LOGIC_OUTS21",
|
||||
"CMT_PMV_WW2A1",
|
||||
"CMT_PMV_SW4A0",
|
||||
"L_TERM_INT_PHASER_TO_IO_OCLKDIV",
|
||||
"CMT_PMV_WL1END3",
|
||||
"CMT_PMV_LOGIC_OUTS16",
|
||||
"CMT_PMV_LH8",
|
||||
"CMT_PMV_IMUX29",
|
||||
"CMT_PMV_LOGIC_OUTS4",
|
||||
"CMT_PMV_SW4A2",
|
||||
"CMT_PMV_WW2A2",
|
||||
"CMT_PMV_SW2A3",
|
||||
"CMT_PMV_WW4A2",
|
||||
"CMT_PMV_WL1END1",
|
||||
"CMT_PMV_EE4A1",
|
||||
"CMT_PMV_IMUX43",
|
||||
"CMT_PMV_WW4A3",
|
||||
"CMT_PMV_SE4C1",
|
||||
"CMT_PMV_IMUX20",
|
||||
"L_TERM_INT_PHASER_TO_IO_ICLK",
|
||||
"CMT_PMV_NW4A2",
|
||||
"CMT_PMV_SW2A2",
|
||||
"CMT_PMV_LH2",
|
||||
"CMT_PMV_WW2END2",
|
||||
"CMT_PMV_LH5",
|
||||
"CMT_PMV_CTRL0",
|
||||
"CMT_PMV_NW2A0",
|
||||
"CMT_PMV_FAN4",
|
||||
"CMT_PMV_IMUX33",
|
||||
"CMT_PMV_NE4BEG3",
|
||||
"CMT_PMV_LOGIC_OUTS19",
|
||||
"CMT_PMV_IMUX13",
|
||||
"CMT_PMV_SW2A1",
|
||||
"CMT_PMV_IMUX44",
|
||||
"CMT_PMV_NE4C1",
|
||||
"CMT_PMV_IMUX46",
|
||||
"CMT_PMV_NE4C0",
|
||||
"CMT_PMV_WW4END1",
|
||||
"CMT_PMV_IMUX9",
|
||||
"CMT_PMV_SE2A2",
|
||||
"CMT_PMV_WW4C2",
|
||||
"CMT_PMV_BYP6",
|
||||
"CMT_PMV_EE4BEG1",
|
||||
"CMT_PMV_NE4BEG1",
|
||||
"CMT_PMV_IMUX27",
|
||||
"CMT_PMV_EE4A3",
|
||||
"CMT_PMV_FAN7",
|
||||
"CMT_PMV_SE4C3",
|
||||
"CMT_PMV_IMUX43",
|
||||
"CMT_PMV_SE4BEG0",
|
||||
"CMT_PMV_LH1",
|
||||
"CMT_PMV_EE2A0",
|
||||
"CMT_PMV_BYP0",
|
||||
"CMT_PMV_IMUX34",
|
||||
"CMT_PMV_SE2A3",
|
||||
"CMT_PMV_FAN4",
|
||||
"CMT_PMV_SE4BEG3",
|
||||
"CMT_PMV_IMUX0",
|
||||
"CMT_PMV_IMUX17",
|
||||
"CMT_PMV_IMUX36",
|
||||
"CMT_PMV_IMUX2",
|
||||
"CMT_PMV_IMUX22",
|
||||
"CMT_PMV_SW4END1",
|
||||
"CMT_PMV_WL1END0",
|
||||
"CMT_PMV_EL1BEG3",
|
||||
"CMT_PMV_ER1BEG0",
|
||||
"CMT_PMV_NW2A2",
|
||||
"CMT_PMV_SW4A0",
|
||||
"CMT_PMV_WW2A1",
|
||||
"CMT_PMV_IMUX1",
|
||||
"CMT_PMV_WL1END1",
|
||||
"CMT_PMV_LOGIC_OUTS7",
|
||||
"CMT_PMV_EE4B2",
|
||||
"CMT_PMV_BYP7",
|
||||
"CMT_PMV_FAN6",
|
||||
"CMT_PMV_SE2A0",
|
||||
"CMT_PMV_NE4C1",
|
||||
"CMT_PMV_IMUX26",
|
||||
"CMT_PMV_NW4A2",
|
||||
"CMT_PMV_SW4END3",
|
||||
"CMT_PMV_IMUX10",
|
||||
"CMT_PMV_IMUX32",
|
||||
"CMT_PMV_NE2A3",
|
||||
"CMT_PMV_LOGIC_OUTS3",
|
||||
"CMT_PMV_IMUX31",
|
||||
"CMT_PMV_NW4A0",
|
||||
"CMT_PMV_LOGIC_OUTS8",
|
||||
"CMT_PMV_IMUX19",
|
||||
"L_TERM_INT_PHASER_TO_IO_ICLK",
|
||||
"CMT_PMV_LOGIC_OUTS19",
|
||||
"CMT_PMV_WW4END3",
|
||||
"CMT_PMV_IMUX37",
|
||||
"CMT_PMV_LOGIC_OUTS4",
|
||||
"CMT_PMV_BYP4",
|
||||
"CMT_PMV_SW4A3",
|
||||
"CMT_PMV_NE2A0",
|
||||
"CMT_PMV_IMUX16",
|
||||
"CMT_PMV_SW2A3",
|
||||
"CMT_PMV_IMUX9",
|
||||
"CMT_PMV_WW4B2",
|
||||
"CMT_PMV_IMUX21",
|
||||
"CMT_PMV_EE4C2",
|
||||
"CMT_PMV_MONITOR_P",
|
||||
"CMT_PMV_WW4B0",
|
||||
"CMT_PMV_IMUX14",
|
||||
"CMT_PMV_NE4C3",
|
||||
"CMT_PMV_EE4BEG2",
|
||||
"CMT_PMV_NE4BEG0",
|
||||
"CMT_PMV_IMUX4",
|
||||
"CMT_PMV_EE2A1",
|
||||
"CMT_PMV_IMUX12",
|
||||
"CMT_PMV_WW2END0",
|
||||
"CMT_PMV_LOGIC_OUTS23",
|
||||
"CMT_PMV_EE4A1",
|
||||
"CMT_PMV_WR1END2",
|
||||
"CMT_PMV_EE2A2",
|
||||
"CMT_PMV_LOGIC_OUTS9",
|
||||
"CMT_PMV_LH9",
|
||||
"CMT_PMV_WW4C0",
|
||||
"CMT_PMV_NW4END3",
|
||||
"CMT_PMV_WW4A0",
|
||||
"CMT_PMV_EE2BEG2",
|
||||
"CMT_PMV_LH12",
|
||||
"CMT_PMV_WW4C2",
|
||||
"CMT_PMV_SW4END2",
|
||||
"CMT_PMV_LOGIC_OUTS14",
|
||||
"CMT_PMV_IMUX46",
|
||||
"CMT_PMV_WW2END1",
|
||||
"CMT_PMV_EE2BEG1",
|
||||
"CMT_PMV_LOGIC_OUTS1",
|
||||
"CMT_PMV_CTRL1",
|
||||
"CMT_PMV_WW4END2",
|
||||
"CMT_PMV_LH2",
|
||||
"L_TERM_INT_PHASER_TO_IO_OCLK1X_90",
|
||||
"CMT_PMV_SE4BEG2",
|
||||
"CMT_PMV_LOGIC_OUTS20",
|
||||
"CMT_PMV_SW2A2",
|
||||
"CMT_PMV_NW4END1",
|
||||
"CMT_PMV_NW4A3",
|
||||
"CMT_PMV_LOGIC_OUTS11",
|
||||
"CMT_PMV_FAN5",
|
||||
"CMT_PMV_WL1END3",
|
||||
"CMT_PMV_WW4C3",
|
||||
"CMT_PMV_EE4A2",
|
||||
"CMT_PMV_WW2A2",
|
||||
"CMT_PMV_LOGIC_OUTS22",
|
||||
"CMT_PMV_IMUX7",
|
||||
"CMT_PMV_LH4",
|
||||
"CMT_PMV_ER1BEG3",
|
||||
"CMT_PMV_SE2A1",
|
||||
"CMT_PMV_WW4B3",
|
||||
"CMT_PMV_EE4C3",
|
||||
"L_TERM_INT_PHASER_TO_IO_ICLKDIV",
|
||||
"CMT_PMV_WW2END3",
|
||||
"CMT_PMV_FAN0",
|
||||
"CMT_PMV_NW4A1",
|
||||
"CMT_PMV_IMUX38",
|
||||
"CMT_PMV_IMUX20",
|
||||
"CMT_PMV_BYP3",
|
||||
"CMT_PMV_NW2A0",
|
||||
"CMT_PMV_EE4BEG0",
|
||||
"L_TERM_INT_PHASER_TO_IO_OCLKDIV",
|
||||
"CMT_PMV_SW4A2",
|
||||
"CMT_PMV_IMUX42",
|
||||
"CMT_PMV_NE2A1",
|
||||
"L_TERM_INT_PHASER_TO_IO_OCLK",
|
||||
"CMT_PMV_IMUX28",
|
||||
"CMT_PMV_WW2A0",
|
||||
"CMT_PMV_NE2A2",
|
||||
"CMT_PMV_SW2A1",
|
||||
"CMT_PMV_WW4END0",
|
||||
"CMT_PMV_IMUX39",
|
||||
"CMT_PMV_LH5",
|
||||
"CMT_PMV_SE4C2",
|
||||
"CMT_PMV_SW2A0",
|
||||
"CMT_PMV_IMUX45",
|
||||
"CMT_PMV_ER1BEG2",
|
||||
"CMT_PMV_WR1END1",
|
||||
"CMT_PMV_FAN1",
|
||||
"CMT_PMV_EL1BEG0",
|
||||
"CMT_PMV_SE4BEG1",
|
||||
"CMT_PMV_IMUX23",
|
||||
"CMT_PMV_IMUX13",
|
||||
"CMT_PMV_IMUX47",
|
||||
"CMT_PMV_WW4A2",
|
||||
"CMT_PMV_EE4B0",
|
||||
"CMT_PMV_SW4END0",
|
||||
"CMT_PMV_LOGIC_OUTS12",
|
||||
"CMT_PMV_EE2BEG3",
|
||||
"CMT_PMV_LOGIC_OUTS16",
|
||||
"CMT_PMV_MONITOR_N",
|
||||
"CMT_PMV_NE4BEG3",
|
||||
"CMT_PMV_WR1END3",
|
||||
"CMT_PMV_EE2A3",
|
||||
"CMT_PMV_LOGIC_OUTS17",
|
||||
"CMT_PMV_EL1BEG2",
|
||||
"CMT_PMV_WW4END3",
|
||||
"CMT_PMV_ER1BEG0",
|
||||
"CMT_PMV_BYP3",
|
||||
"CMT_PMV_FAN3",
|
||||
"CMT_PMV_NW4END3",
|
||||
"CMT_PMV_IMUX38",
|
||||
"CMT_PMV_FAN0",
|
||||
"CMT_PMV_EE4C1",
|
||||
"CMT_PMV_SE4BEG0",
|
||||
"CMT_PMV_BYP4",
|
||||
"CMT_PMV_IMUX27",
|
||||
"CMT_PMV_WW2A3",
|
||||
"CMT_PMV_SW4A1",
|
||||
"CMT_PMV_EE4A0",
|
||||
"CMT_PMV_IMUX44",
|
||||
"CMT_PMV_WW4A3",
|
||||
"CMT_PMV_EE4C0",
|
||||
"CMT_PMV_NE4C0",
|
||||
"CMT_PMV_IMUX25",
|
||||
"CMT_PMV_NE4C2",
|
||||
"CMT_PMV_IMUX29",
|
||||
"CMT_PMV_WW4B3",
|
||||
"CMT_PMV_LOGIC_OUTS10",
|
||||
"CMT_PMV_EE4B2",
|
||||
"CMT_PMV_NW4END2",
|
||||
"CMT_PMV_MONITOR_N",
|
||||
"CMT_PMV_WW4C0",
|
||||
"CMT_PMV_LOGIC_OUTS11",
|
||||
"CMT_PMV_IMUX21",
|
||||
"CMT_PMV_IMUX1",
|
||||
"CMT_PMV_IMUX7",
|
||||
"CMT_PMV_NW4A0",
|
||||
"CMT_PMV_SW2A0",
|
||||
"CMT_PMV_BYP0",
|
||||
"CMT_PMV_CLK0",
|
||||
"CMT_PMV_NE2A0",
|
||||
"CMT_PMV_IMUX47",
|
||||
"CMT_PMV_EE4B1",
|
||||
"CMT_PMV_LOGIC_OUTS17",
|
||||
"CMT_PMV_WW4B0",
|
||||
"CMT_PMV_WR1END1",
|
||||
"CMT_PMV_LOGIC_OUTS12",
|
||||
"CMT_PMV_SE4BEG2",
|
||||
"CMT_PMV_IMUX14",
|
||||
"CMT_PMV_SE4C0",
|
||||
"CMT_PMV_WW4C1",
|
||||
"CMT_PMV_IMUX18",
|
||||
"CMT_PMV_FAN2"
|
||||
"CMT_PMV_EL1BEG1",
|
||||
"CMT_PMV_CLK1",
|
||||
"CMT_PMV_FAN5",
|
||||
"CMT_PMV_EE4C2",
|
||||
"CMT_PMV_IMUX17",
|
||||
"CMT_PMV_NW4A1",
|
||||
"CMT_PMV_LOGIC_OUTS5",
|
||||
"CMT_PMV_IMUX16",
|
||||
"CMT_PMV_IMUX10",
|
||||
"CMT_PMV_LOGIC_OUTS18",
|
||||
"CMT_PMV_IMUX30",
|
||||
"CMT_PMV_SW4A3",
|
||||
"CMT_PMV_SW4END1",
|
||||
"CMT_PMV_IMUX8",
|
||||
"CMT_PMV_WW4END2",
|
||||
"CMT_PMV_EE2A0",
|
||||
"CMT_PMV_EE2BEG0",
|
||||
"CMT_PMV_IMUX37",
|
||||
"CMT_PMV_IMUX32",
|
||||
"CMT_PMV_SE2A0",
|
||||
"CMT_PMV_IMUX19",
|
||||
"CMT_PMV_LH9",
|
||||
"CMT_PMV_NE4C3",
|
||||
"CMT_PMV_LH4",
|
||||
"CMT_PMV_NW4A3",
|
||||
"CMT_PMV_SE4C2",
|
||||
"CMT_PMV_IMUX0",
|
||||
"CMT_PMV_NE4BEG2",
|
||||
"CMT_PMV_LOGIC_OUTS0",
|
||||
"CMT_PMV_IMUX24",
|
||||
"CMT_PMV_WR1END0",
|
||||
"CMT_PMV_EE4C0",
|
||||
"CMT_PMV_IMUX34",
|
||||
"CMT_PMV_IMUX15",
|
||||
"CMT_PMV_EE2BEG2",
|
||||
"CMT_PMV_NW2A3",
|
||||
"CMT_PMV_IMUX23",
|
||||
"CMT_PMV_SW4END0",
|
||||
"CMT_PMV_WW4B2",
|
||||
"CMT_PMV_LOGIC_OUTS6",
|
||||
"CMT_PMV_NW2A1",
|
||||
"CMT_PMV_WW2END1",
|
||||
"CMT_PMV_LH1",
|
||||
"CMT_PMV_EE4A3",
|
||||
"CMT_PMV_LH11"
|
||||
],
|
||||
"tile_type": "CMT_PMV_L",
|
||||
"sites": []
|
||||
|
|
|
|||
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Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue