Updating DB based on "Expanded ROI causes these asserts to fail.".
See [Info File](Info.md) for details. Signed-off-by: Tim 'mithro' Ansell <me@mith.ro>
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Info.md
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Info.md
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@ -37,36 +37,37 @@ These files are released under the very permissive [CC0 1.0 Universal](COPYING).
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# Details
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Last updated on Tue Oct 16 20:52:38 UTC 2018 (2018-10-16T20:52:38+00:00).
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Last updated on Mon Oct 22 16:06:34 UTC 2018 (2018-10-22T16:06:34+00:00).
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Created using [Project X-Ray](https://github.com/SymbiFlow/prjxray) version [v0.0-770-g6db8bd6](https://github.com/SymbiFlow/prjxray/commit/6db8bd65748e1a09e3c7a1433dd9e8693d977da0).
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Created using [Project X-Ray](https://github.com/SymbiFlow/prjxray) version [v0.0-774-gbba5c89](https://github.com/SymbiFlow/prjxray/commit/bba5c899ddb7917fe5d34675a05abfb9c4db8f51).
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Latest commit was;
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```
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commit 6db8bd65748e1a09e3c7a1433dd9e8693d977da0
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Merge: b117448 310101c
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Author: Tim Ansell <me@mith.ro>
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Date: Mon Oct 15 17:42:13 2018 -0700
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commit bba5c899ddb7917fe5d34675a05abfb9c4db8f51
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Author: Tim 'mithro' Ansell <me@mith.ro>
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Date: Wed Oct 17 23:09:04 2018 +0000
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Merge pull request #153 from SymbiFlow/mithro-patch-1
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Adding timing fuzzer needs to requirements.txt
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Expanded ROI causes these asserts to fail.
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```
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## Database for [artix7](artix7/)
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### Settings
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Created using following [settings.sh (sha256: 994008cff37affae1b334cba5908a1b8fe51ec69c47c553943f3d246763fb300)](https://github.com/SymbiFlow/prjxray/blob/6db8bd65748e1a09e3c7a1433dd9e8693d977da0/database/artix7/settings.sh)
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Created using following [settings.sh (sha256: a215bd6ad72742d242ed4d9e6712f393f57341577f9c5197e84c7d61635b9e18)](https://github.com/SymbiFlow/prjxray/blob/bba5c899ddb7917fe5d34675a05abfb9c4db8f51/database/artix7/settings.sh)
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```shell
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export XRAY_DATABASE="artix7"
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export XRAY_PART="xc7a50tfgg484-1"
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export XRAY_ROI="SLICE_X12Y100:SLICE_X27Y149"
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export XRAY_ROI_FRAMES="0x00020500:0x000208ff"
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export XRAY_ROI_GRID_X1="29"
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export XRAY_ROI_FRAMES="0x00000000:0xffffffff"
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# Leave some CLBs to the left to allow easy ROI entering
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export XRAY_ROI="SLICE_X8Y100:SLICE_X27Y149 RAMB18_X0Y20:RAMB18_X0Y59 RAMB36_X0Y10:RAMB36_X0Y29 DSP48_X0Y59:DSP48_X0Y20"
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export XRAY_ROI_GRID_X1="18"
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export XRAY_ROI_GRID_X2="47"
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export XRAY_ROI_GRID_Y1="0"
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export XRAY_ROI_GRID_Y2="52"
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export XRAY_PIN_00="E22"
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export XRAY_PIN_01="D22"
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export XRAY_PIN_02="E21"
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@ -84,13 +85,13 @@ Results have checksums;
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* [`8c6097166bf4b43969c49894dc464d1202f19683d7287a63ec709bc867d97105 ./artix7/element_counts.csv`](./artix7/element_counts.csv)
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* [`6864d8edcef442cb129f83b9c5cd27be85d1b4bded8007bbeadcfc70717f8c48 ./artix7/gridinfo/grid-xc7a50tfgg484-1-db.txt`](./artix7/gridinfo/grid-xc7a50tfgg484-1-db.txt)
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* [`76a9286b89fa91babd4ab8b59156b12a7024130d66f9f08da290797d00a115e6 ./artix7/mask_bram_l.db`](./artix7/mask_bram_l.db)
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* [`69f298082e6c8e537d8348b9d4c01f582d0d86fdeddf1e6606b90e800994bcdd ./artix7/mask_bram_l.db`](./artix7/mask_bram_l.db)
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* [`8fae8a634efb8929db28581b2acd436fd4c31a0bd241dd4643e5692e2da8e648 ./artix7/mask_bram_r.db`](./artix7/mask_bram_r.db)
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* [`5c274320294201935a3edccb43eca8e347ca1f0acded71ec388c794877d4b55b ./artix7/mask_clbll_l.db`](./artix7/mask_clbll_l.db)
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* [`5c274320294201935a3edccb43eca8e347ca1f0acded71ec388c794877d4b55b ./artix7/mask_clbll_r.db`](./artix7/mask_clbll_r.db)
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* [`5c274320294201935a3edccb43eca8e347ca1f0acded71ec388c794877d4b55b ./artix7/mask_clblm_l.db`](./artix7/mask_clblm_l.db)
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* [`5c274320294201935a3edccb43eca8e347ca1f0acded71ec388c794877d4b55b ./artix7/mask_clblm_r.db`](./artix7/mask_clblm_r.db)
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* [`76a9286b89fa91babd4ab8b59156b12a7024130d66f9f08da290797d00a115e6 ./artix7/mask_dsp_l.db`](./artix7/mask_dsp_l.db)
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* [`69f298082e6c8e537d8348b9d4c01f582d0d86fdeddf1e6606b90e800994bcdd ./artix7/mask_dsp_l.db`](./artix7/mask_dsp_l.db)
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* [`8fae8a634efb8929db28581b2acd436fd4c31a0bd241dd4643e5692e2da8e648 ./artix7/mask_dsp_r.db`](./artix7/mask_dsp_r.db)
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* [`76d1e0bd4b7ad492cf3fe8698b2b5f46f7dcc5fe446984e5dccae373c63edafd ./artix7/mask_hclk_l.db`](./artix7/mask_hclk_l.db)
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* [`76d1e0bd4b7ad492cf3fe8698b2b5f46f7dcc5fe446984e5dccae373c63edafd ./artix7/mask_hclk_r.db`](./artix7/mask_hclk_r.db)
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@ -98,8 +99,8 @@ Results have checksums;
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* [`3955d590e8ee64c843bb80f911a08781c1bac63e71b577436ae1f44195a88e22 ./artix7/ppips_clbll_r.db`](./artix7/ppips_clbll_r.db)
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* [`29f175153821dc13989eb580676ff0007e108d911275a74e7ebe45e819c14eaf ./artix7/ppips_clblm_l.db`](./artix7/ppips_clblm_l.db)
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* [`52b53ae735d40632403283ab720db2172794a22c5245b3da7693b264d69a122d ./artix7/ppips_clblm_r.db`](./artix7/ppips_clblm_r.db)
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* [`6d35b568a51f9b6761da2470a71738b2477ef72c16068a529ae8eb52b65bf17a ./artix7/ppips_hclk_l.db`](./artix7/ppips_hclk_l.db)
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* [`81e0696179a33bdf8d2279a53b406911a403d50224355e9ad29eccee01a70305 ./artix7/ppips_hclk_r.db`](./artix7/ppips_hclk_r.db)
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* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./artix7/ppips_hclk_l.db`](./artix7/ppips_hclk_l.db)
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* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./artix7/ppips_hclk_r.db`](./artix7/ppips_hclk_r.db)
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* [`be617c15d1ec311b6249791414bbd69380fe90b476353cbb2fc2a7cb06f5029d ./artix7/ppips_int_l.db`](./artix7/ppips_int_l.db)
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* [`a1423859c97a82dcfb114644f50b991db4ca7e0996e6d1ae4d2c97bfdfcb723d ./artix7/ppips_int_r.db`](./artix7/ppips_int_r.db)
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* [`8aba20247656e287de5d0033bfaf31f2514cff0d041bd438719116673dc5e815 ./artix7/segbits_clbll_l.db`](./artix7/segbits_clbll_l.db)
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@ -108,167 +109,167 @@ Results have checksums;
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* [`4bd2d802fb5b62ebe2941d658edc466bab26b87c12d3c6fcbdcd614e51eb2e3f ./artix7/segbits_clblm_r.db`](./artix7/segbits_clblm_r.db)
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* [`20f7bf469951b04a56e5e140b6327470750b08960643353384b35baf85eb9117 ./artix7/segbits_hclk_l.db`](./artix7/segbits_hclk_l.db)
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* [`5e22f758a04eab3185b2453c9994aa2fa48f50ca8a6b49bf82e8fc4351f23a5c ./artix7/segbits_hclk_r.db`](./artix7/segbits_hclk_r.db)
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* [`64e07cac8ac2dc7f2bfca584cda816a4b3e2feb629acb85bd8db843f7114563e ./artix7/segbits_int_l.db`](./artix7/segbits_int_l.db)
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* [`08dee581e565abbd09db559f9226139ba5a253f8aec4f3492152d8df8a87bbab ./artix7/segbits_int_l.db`](./artix7/segbits_int_l.db)
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* [`be5f0c64ee17ad010dfea5125200216b2c69a558477a80133d043ed466e565be ./artix7/segbits_int_r.db`](./artix7/segbits_int_r.db)
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* [`994008cff37affae1b334cba5908a1b8fe51ec69c47c553943f3d246763fb300 ./artix7/settings.sh`](./artix7/settings.sh)
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* [`68d7c7a9a5c97fbca8e7867536b43ac030e955710daea776d3858632be03b289 ./artix7/site_type_BSCAN.json`](./artix7/site_type_BSCAN.json)
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* [`48e835223effc9d381b53063018f109ca4f8f1d133770b369ee13627039018af ./artix7/site_type_BUFGCTRL.json`](./artix7/site_type_BUFGCTRL.json)
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* [`44ba2a2267847c6b818d7c4d77582060acaabaadeed73251fe20b91fe994c1b6 ./artix7/site_type_BUFHCE.json`](./artix7/site_type_BUFHCE.json)
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* [`3c3defc9905964a71ea5479cb567e25ee9fe570f3265111cbbd4e8fd0e4a8523 ./artix7/site_type_BUFIO.json`](./artix7/site_type_BUFIO.json)
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* [`8831721614d683525ca4731d7f8134a9b753a1c92fd6bdd7bcb7658eb943bfe4 ./artix7/site_type_BUFMRCE.json`](./artix7/site_type_BUFMRCE.json)
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* [`de735a235f7a446de50a3be308d5cd81f7da0e1232b58aa053d4b782ac246ca0 ./artix7/site_type_BUFR.json`](./artix7/site_type_BUFR.json)
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* [`209848c604c17479294dc8ebed63f461aae730eaff0540d424d523ef587f759a ./artix7/site_type_CAPTURE.json`](./artix7/site_type_CAPTURE.json)
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* [`987784fbf675e48be322751374983394cc9487133a6c94549a993fbc07e8a2d4 ./artix7/site_type_DCIRESET.json`](./artix7/site_type_DCIRESET.json)
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* [`62289a287b963c2b6b129fa8a5f31c49a500cfb8c3ab27f75ec57b9ffc552989 ./artix7/site_type_DNA_PORT.json`](./artix7/site_type_DNA_PORT.json)
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* [`2d0af6b7ef658b20cbf8fe32b9d095f145b7c50449eb5f9d947f67d5927fe3a0 ./artix7/site_type_DSP48E1.json`](./artix7/site_type_DSP48E1.json)
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* [`64cf02d69a36a13742dabcdbb6e806574535f9d32f601a788dbeb31c9464f010 ./artix7/site_type_EFUSE_USR.json`](./artix7/site_type_EFUSE_USR.json)
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* [`cbe6698e675c86092cf45398e2a01c7d50c102408594040c5bc8c17e9cc18880 ./artix7/site_type_FIFO18E1.json`](./artix7/site_type_FIFO18E1.json)
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* [`2d5277673e613068f64113f124e27c3fb9c5ebd5e0aee8d18509ea6be0ddf102 ./artix7/site_type_FRAME_ECC.json`](./artix7/site_type_FRAME_ECC.json)
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* [`7fb7b4e064d7797b57dd52e5562d6610a60901d69373c6e6430e18ab5ee5b5a4 ./artix7/site_type_GTPE2_CHANNEL.json`](./artix7/site_type_GTPE2_CHANNEL.json)
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* [`75bb5f8208c20f3411d51b6db6ca2fc7269527e820f0c75147f06980d6e9870b ./artix7/site_type_GTPE2_COMMON.json`](./artix7/site_type_GTPE2_COMMON.json)
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* [`802946f229a9cae335d14b7ec454a1b00c99ffa386a2757ff0e08cf173f4e586 ./artix7/site_type_IBUFDS_GTE2.json`](./artix7/site_type_IBUFDS_GTE2.json)
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* [`800265d879b19d71d149eca330d7af7782b20af5beedc7b56a9de7ab6a495484 ./artix7/site_type_ICAP.json`](./artix7/site_type_ICAP.json)
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* [`a2cb0e085e57ef5aae3fdf0ad581ccb1d70e637c7e6fd8eabaf6b8e7b8296fb5 ./artix7/site_type_IDELAYCTRL.json`](./artix7/site_type_IDELAYCTRL.json)
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* [`419dd4ac567c033750e5a3d1c719546b42a4aec43b7997ff754aa5d05a3f4957 ./artix7/site_type_IDELAYE2.json`](./artix7/site_type_IDELAYE2.json)
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* [`81374e99a343bd404d4398914f00c0ad70e4ce61260a0d4291acdff521a207ff ./artix7/site_type_ILOGICE3.json`](./artix7/site_type_ILOGICE3.json)
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* [`d0234256fb9d69ef8772ac862cb31f62c528551c85b8b89dcd9419e7e6e97dbf ./artix7/site_type_IN_FIFO.json`](./artix7/site_type_IN_FIFO.json)
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* [`e281b48b2ae05c81afd47274491bfb9dab16739b0410fc398901348feae0148f ./artix7/site_type_IOB33.json`](./artix7/site_type_IOB33.json)
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* [`efb16e39739c19f68d5d93d05f3cb8ec02b1e21507d09248bde860e56fb88bc0 ./artix7/site_type_IOB33M.json`](./artix7/site_type_IOB33M.json)
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* [`4675291cdfdb138134a81bb417c6669678da41d7c0d414cd76bdc9b127376daa ./artix7/site_type_IOB33S.json`](./artix7/site_type_IOB33S.json)
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* [`2b57b762c98a9d0dd4a0c9df64d3079c87d498affa8f44864e3865a56a9c4337 ./artix7/site_type_IPAD.json`](./artix7/site_type_IPAD.json)
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* [`c6f41a771b2c41cdf9d2c8f359b31c60a82ddc785cc37674dd3186b766f7e195 ./artix7/site_type_MMCME2_ADV.json`](./artix7/site_type_MMCME2_ADV.json)
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* [`a9b9d3b45879b1ba94d1e23951829abed8a3a74045c426f9608a6cd710037159 ./artix7/site_type_OLOGICE3.json`](./artix7/site_type_OLOGICE3.json)
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* [`52c3f259afb284b5fcd0b2f5c6cce1f10bbaba928c54314918deae733e1209c8 ./artix7/site_type_OPAD.json`](./artix7/site_type_OPAD.json)
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* [`785e40e885e6e0e30ad7c8c5b1bae91b2a66ee198de467cbe311207a1883a763 ./artix7/site_type_OUT_FIFO.json`](./artix7/site_type_OUT_FIFO.json)
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* [`bec68a01b085f668b3d670ba2eec33c6b013d91206074102dd0718a74f52a265 ./artix7/site_type_PCIE_2_1.json`](./artix7/site_type_PCIE_2_1.json)
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* [`a86aae218a0de991c702bb18989965a01a449022411c9bcc446a77b999a29f4f ./artix7/site_type_PHASER_IN_PHY.json`](./artix7/site_type_PHASER_IN_PHY.json)
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* [`1770469ab1f80899f97b2a73bcdab7dc1ac8264382fbb5a873a25c40f63f4025 ./artix7/site_type_PHASER_OUT_PHY.json`](./artix7/site_type_PHASER_OUT_PHY.json)
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* [`fb9790f8d144f07032d58f0661b6c57d04d59d01fe9dbcdf04785075d95f9775 ./artix7/site_type_PHASER_REF.json`](./artix7/site_type_PHASER_REF.json)
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* [`a255ece7302b4b9084000b2e59673f6226f9a20b65cd79f16b855959b9a5ef9a ./artix7/site_type_PHY_CONTROL.json`](./artix7/site_type_PHY_CONTROL.json)
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* [`0d6e8a27c97972610583753e8a55c30da363a077e66baab044102d9d68e4625c ./artix7/site_type_PLLE2_ADV.json`](./artix7/site_type_PLLE2_ADV.json)
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* [`55c262e8e810f40dc2a48c1610105a6188e6497b0edcd6a85e1b3f9746efcb69 ./artix7/site_type_PMV2.json`](./artix7/site_type_PMV2.json)
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* [`4a52dd7412da5863de0c97f8c9c18cdf9f7c18964a52cf210eac3a633ab7b020 ./artix7/site_type_RAMB18E1.json`](./artix7/site_type_RAMB18E1.json)
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* [`36d213c6a6b1834ad2069fce877c93f4de0be19a7d5d149881f92a5fe2d03660 ./artix7/site_type_RAMBFIFO36E1.json`](./artix7/site_type_RAMBFIFO36E1.json)
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* [`ac08ae36561e4da581fdad9d5b368585edfffe9ee0ac0f637583a5bb2dbc1b31 ./artix7/site_type_SLICEL.json`](./artix7/site_type_SLICEL.json)
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* [`60e7076d85bae6e3b91c13aebc5c5cdb8bbb3085f1e659111a96b3ff6aa30c0c ./artix7/site_type_SLICEM.json`](./artix7/site_type_SLICEM.json)
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* [`7b059e5a5f1ae6969e81e1467d65faae77094d08b37013fef3ee5f6eae138f4d ./artix7/site_type_STARTUP.json`](./artix7/site_type_STARTUP.json)
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* [`b0d154bdf6f088bd1dec95b51b7f7e3d2214816d03dd8515491e1468d8da7d50 ./artix7/site_type_TIEOFF.json`](./artix7/site_type_TIEOFF.json)
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* [`e8c9663846548b9d015c8bd9790ea2d546d1370a1be625d55cf67d2f2fdd85b0 ./artix7/site_type_USR_ACCESS.json`](./artix7/site_type_USR_ACCESS.json)
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* [`bed5b08143b80a48843489c99f454a5520622f4d07cfcec844cf5ae5a4d3a02a ./artix7/site_type_XADC.json`](./artix7/site_type_XADC.json)
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* [`05dc0f913271acdc3b847df1b865ca4eecb1aa4d62ed8c09a33c3fe4a94e5310 ./artix7/tileconn.json`](./artix7/tileconn.json)
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* [`cfcf625768dd4a389bc4f58144a96a5339836ee4d6c135f8d4b8a21e24cc8e1f ./artix7/tilegrid.json`](./artix7/tilegrid.json)
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* [`d9b746969fe43418700400f5eb28098ab1db1cd3c201646b4f98933e4ea4513c ./artix7/tile_type_BRAM_INT_INTERFACE_L.json`](./artix7/tile_type_BRAM_INT_INTERFACE_L.json)
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* [`1ace1125bc9f15f8d4c5b099c87c8879ebed5c782b019d3292ab309cf4c9f9f6 ./artix7/tile_type_BRAM_INT_INTERFACE_R.json`](./artix7/tile_type_BRAM_INT_INTERFACE_R.json)
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* [`fb0a193b9767c9aa6843b21642d7b22531ba99b1b20df73eb0e87d9d07323ff8 ./artix7/tile_type_BRAM_L.json`](./artix7/tile_type_BRAM_L.json)
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* [`2a1c2972e742277d748c70d9fb10de1e4e8db4a8cff78a1426373eede785045b ./artix7/tile_type_BRAM_R.json`](./artix7/tile_type_BRAM_R.json)
|
||||
* [`514495745877b0950efa5a6e85260e48311c7ec06639491b268596a1fcb1804e ./artix7/tile_type_BRKH_BRAM.json`](./artix7/tile_type_BRKH_BRAM.json)
|
||||
* [`8270a7c38061544fd554489395b2fcf5ca1d5b2657e86909115513e5df4632c1 ./artix7/tile_type_BRKH_B_TERM_INT.json`](./artix7/tile_type_BRKH_B_TERM_INT.json)
|
||||
* [`161d83d9c4f465ada1f97de86f033cef0307a77033a9bcd84b6dc5db72c3ce5e ./artix7/tile_type_BRKH_CLB.json`](./artix7/tile_type_BRKH_CLB.json)
|
||||
* [`e3495a6a48df14e4d2b46d37ba5b6d6e0b48e58f5079076c198cbf885e348687 ./artix7/tile_type_BRKH_CLK.json`](./artix7/tile_type_BRKH_CLK.json)
|
||||
* [`03b08aeaed997c64ed4b5eaf67c4ed7d2664b912d8b9ee3525dbcc60372fd33a ./artix7/tile_type_BRKH_CMT.json`](./artix7/tile_type_BRKH_CMT.json)
|
||||
* [`1d03a9c30038f68f985c3aa4c6b11eb67d351669a73741531843b67dfeb2d3bd ./artix7/tile_type_BRKH_DSP_L.json`](./artix7/tile_type_BRKH_DSP_L.json)
|
||||
* [`273c69bd73e8da97c8c5f6e46239f5b42519559db2ba6526db0cc5eb997f2810 ./artix7/tile_type_BRKH_DSP_R.json`](./artix7/tile_type_BRKH_DSP_R.json)
|
||||
* [`8728c790ff8a5b20b0b186128e7cac18a385416c3ce7e4fdfd016e63a9606e20 ./artix7/tile_type_BRKH_GTX.json`](./artix7/tile_type_BRKH_GTX.json)
|
||||
* [`8c2539052f41244e1efedacec1bceac3127c537829005721afe2e0fb68bbd954 ./artix7/tile_type_BRKH_INT.json`](./artix7/tile_type_BRKH_INT.json)
|
||||
* [`c53cb55ca3987567e1d92c8158921bf9040938d4fec0dcd46edd2fa66a8b0f96 ./artix7/tile_type_BRKH_TERM_INT.json`](./artix7/tile_type_BRKH_TERM_INT.json)
|
||||
* [`63e370ea04427f8f105645e6fb6ada35831db5c11d3193bebd8cf8a9b12466a9 ./artix7/tile_type_B_TERM_INT.json`](./artix7/tile_type_B_TERM_INT.json)
|
||||
* [`92dad8dfd99b93585fa663c9b8676a7396322efacf7eed4317ff17d34adc9e96 ./artix7/tile_type_CFG_CENTER_BOT.json`](./artix7/tile_type_CFG_CENTER_BOT.json)
|
||||
* [`ac1bb0479076e19e72f26ff0d30574062fa9e3c0975ea27d49492fb76cd2ccda ./artix7/tile_type_CFG_CENTER_MID.json`](./artix7/tile_type_CFG_CENTER_MID.json)
|
||||
* [`9017d2764450bd8abfb8130e8723a3c812d08594f33cfa30cd20cbbaa1d88ccc ./artix7/tile_type_CFG_CENTER_TOP.json`](./artix7/tile_type_CFG_CENTER_TOP.json)
|
||||
* [`0bad231056673da883e3e53f6f36b33f9a61193d35b1c019821d6f9216f9c38b ./artix7/tile_type_CLBLL_L.json`](./artix7/tile_type_CLBLL_L.json)
|
||||
* [`33b79b15bec3527cbc3bb5befa16c56b3e9871107eb9a0c7d1ab47f8fb5e7fca ./artix7/tile_type_CLBLL_R.json`](./artix7/tile_type_CLBLL_R.json)
|
||||
* [`6456207a5ded60d693c5a7fe2de6913dd857a0fea45dac839d5894c9eca07a3a ./artix7/tile_type_CLBLM_L.json`](./artix7/tile_type_CLBLM_L.json)
|
||||
* [`11f5ac4760aa31d1449f73c6ae75bf9967487af3841c5284be7a729b2e642cd5 ./artix7/tile_type_CLBLM_R.json`](./artix7/tile_type_CLBLM_R.json)
|
||||
* [`d2cc007c28f96e15a045cadae16e737c44d0cdb5b6feb6ac7a0e2d7d2a633113 ./artix7/tile_type_CLK_BUFG_BOT_R.json`](./artix7/tile_type_CLK_BUFG_BOT_R.json)
|
||||
* [`ca12c02dcb5161096b6615d740cda2286e203a8a6e58bac765553dba30fa03b5 ./artix7/tile_type_CLK_BUFG_REBUF.json`](./artix7/tile_type_CLK_BUFG_REBUF.json)
|
||||
* [`a4b3c90abc3b25401a35fc7311838c1256d2f7abf3434b8be4f077a9c211b5f5 ./artix7/tile_type_CLK_BUFG_TOP_R.json`](./artix7/tile_type_CLK_BUFG_TOP_R.json)
|
||||
* [`78402da14a8d33516e657f5cd8bc03167ea130381bf9fd49e529bc07f7d21bd1 ./artix7/tile_type_CLK_FEED.json`](./artix7/tile_type_CLK_FEED.json)
|
||||
* [`d70153bcd8b20080449614a1c3af5d5610b038f3b047c773ba089233235be199 ./artix7/tile_type_CLK_HROW_BOT_R.json`](./artix7/tile_type_CLK_HROW_BOT_R.json)
|
||||
* [`d26c22cea469b765bf86cba805da21f439914984d78c00ecea4637cfb04e53b4 ./artix7/tile_type_CLK_HROW_TOP_R.json`](./artix7/tile_type_CLK_HROW_TOP_R.json)
|
||||
* [`43731915b919e07a1e8cc06adcfbd20d04dcda35fedb1bd79ad9fc9d6babd35a ./artix7/tile_type_CLK_MTBF2.json`](./artix7/tile_type_CLK_MTBF2.json)
|
||||
* [`3cd7b7f864d5f3b01a9dd81240a0768d3b5a23e9f42f47d55fd38ffd42391ac2 ./artix7/tile_type_CLK_PMV2.json`](./artix7/tile_type_CLK_PMV2.json)
|
||||
* [`15dcfb0e7681e036c9f983c08cdafce8aa5ca4d851b398fcc57796d50956cd6f ./artix7/tile_type_CLK_PMV2_SVT.json`](./artix7/tile_type_CLK_PMV2_SVT.json)
|
||||
* [`13c071a98962402cfaf03ea8170a8bc95e777fa25e8907bcc9dd6e7392da620f ./artix7/tile_type_CLK_PMVIOB.json`](./artix7/tile_type_CLK_PMVIOB.json)
|
||||
* [`4882141fe5d8c8d99a1f8e54111e45fa1f72da72afb82b9338dc1f8d5339c47c ./artix7/tile_type_CLK_PMV.json`](./artix7/tile_type_CLK_PMV.json)
|
||||
* [`01831f7959fd450ebd4ff369effb58cd8dd6edb8c0a32910314e615bba7d0453 ./artix7/tile_type_CLK_TERM.json`](./artix7/tile_type_CLK_TERM.json)
|
||||
* [`6e14d1df41c7babcabc2a70642c979c233d29964dee547f97d6e6611eb3cf0fa ./artix7/tile_type_CMT_FIFO_L.json`](./artix7/tile_type_CMT_FIFO_L.json)
|
||||
* [`f11e6c8cb237981c22723594e11b91ba9a0520608c26b686984fa3a580006a53 ./artix7/tile_type_CMT_FIFO_R.json`](./artix7/tile_type_CMT_FIFO_R.json)
|
||||
* [`719e92c33454605348b48326a7216a05ed94972cbce07c009b9f91721354037d ./artix7/tile_type_CMT_PMV.json`](./artix7/tile_type_CMT_PMV.json)
|
||||
* [`71b43263ec93d4fb4b2a1908a3797960fdb889a956aa4c4b0417662a3c6134c6 ./artix7/tile_type_CMT_PMV_L.json`](./artix7/tile_type_CMT_PMV_L.json)
|
||||
* [`a43128995a064bdc7fb2912d85865045616e7566f17c04c7e0f2bfc069288021 ./artix7/tile_type_CMT_TOP_L_LOWER_B.json`](./artix7/tile_type_CMT_TOP_L_LOWER_B.json)
|
||||
* [`3d3cc99ab7581f1c79346167a4a674db38badee88093088984285cf4486ffabc ./artix7/tile_type_CMT_TOP_L_LOWER_T.json`](./artix7/tile_type_CMT_TOP_L_LOWER_T.json)
|
||||
* [`2353553a03e3a9add958c19eefd91666e7f65bb700e45cf55a51feeb1f1538a1 ./artix7/tile_type_CMT_TOP_L_UPPER_B.json`](./artix7/tile_type_CMT_TOP_L_UPPER_B.json)
|
||||
* [`546b36f818e4ce5bbbaeb004f0958bc71c196116df945a6a1cc15865b3ad36e0 ./artix7/tile_type_CMT_TOP_L_UPPER_T.json`](./artix7/tile_type_CMT_TOP_L_UPPER_T.json)
|
||||
* [`dcff89d800085c5ba4815965d96ee6e51ba0e0c2da67c5ab109a14ac8221f149 ./artix7/tile_type_CMT_TOP_R_LOWER_B.json`](./artix7/tile_type_CMT_TOP_R_LOWER_B.json)
|
||||
* [`df04301e96cb3a401a2410a59d5a8668b085eedc63136b2d83f13c1266ff0c7d ./artix7/tile_type_CMT_TOP_R_LOWER_T.json`](./artix7/tile_type_CMT_TOP_R_LOWER_T.json)
|
||||
* [`53aed496f57f63e85c4ca2e994efb90d5c411e1f7b2a2fdec7d591bbfd52911d ./artix7/tile_type_CMT_TOP_R_UPPER_B.json`](./artix7/tile_type_CMT_TOP_R_UPPER_B.json)
|
||||
* [`c5a8e11c13a7efff28f7ec890f79d5dbfa02879390b88ddf205ac0b80898219d ./artix7/tile_type_CMT_TOP_R_UPPER_T.json`](./artix7/tile_type_CMT_TOP_R_UPPER_T.json)
|
||||
* [`a27684136404d082ede94a76308e3e37ebc406014bab99be40f0db209582e778 ./artix7/tile_type_DSP_L.json`](./artix7/tile_type_DSP_L.json)
|
||||
* [`446e3735753ece77f4ff94587d02a71525bf1d800bdbdc9e5f8c6c7e2eb1ab7d ./artix7/tile_type_DSP_R.json`](./artix7/tile_type_DSP_R.json)
|
||||
* [`89c0f5064866f01eb7573184af6ad5b7a7cec268371140eb6d9a44022941ad90 ./artix7/tile_type_GTP_CHANNEL_0.json`](./artix7/tile_type_GTP_CHANNEL_0.json)
|
||||
* [`20df90e6bd299275e2a770fab0aa75d86c1044b075fc458431da325ac37f721a ./artix7/tile_type_GTP_CHANNEL_1.json`](./artix7/tile_type_GTP_CHANNEL_1.json)
|
||||
* [`9dba1b622368e6d7730e0cbb791821f059c7c5ae2836f745402be6a898e6be88 ./artix7/tile_type_GTP_CHANNEL_2.json`](./artix7/tile_type_GTP_CHANNEL_2.json)
|
||||
* [`64236bca14a2f24e555677d87688affea8db7690c9019b71a23094f26180d7ce ./artix7/tile_type_GTP_CHANNEL_3.json`](./artix7/tile_type_GTP_CHANNEL_3.json)
|
||||
* [`7b9e02947c682e6409bad34c945d54a457ac1e233f41801f58c3e1f8980408f8 ./artix7/tile_type_GTP_COMMON.json`](./artix7/tile_type_GTP_COMMON.json)
|
||||
* [`42c9dea1a7776d599a3427963e5018e257b780192f92021b304d843db8fdeaad ./artix7/tile_type_GTP_INT_INTERFACE.json`](./artix7/tile_type_GTP_INT_INTERFACE.json)
|
||||
* [`9ef4d2dd47b07c41632e3871079a0da594cb9dc2870a0477d2736284b38275c7 ./artix7/tile_type_HCLK_BRAM.json`](./artix7/tile_type_HCLK_BRAM.json)
|
||||
* [`39079ee2dbd2b38eba97db6755e40baf476f5f69ad48e240133d9b39aa2cfd13 ./artix7/tile_type_HCLK_CLB.json`](./artix7/tile_type_HCLK_CLB.json)
|
||||
* [`cbf55319ba7ac9fb21f588cc419894842458580754c82058651de357c5a9818c ./artix7/tile_type_HCLK_CMT.json`](./artix7/tile_type_HCLK_CMT.json)
|
||||
* [`41b294fe9401ecddda4459762f4bb7ebf5c03628be0aec279916b2a6caed0a96 ./artix7/tile_type_HCLK_CMT_L.json`](./artix7/tile_type_HCLK_CMT_L.json)
|
||||
* [`dfa72bfc5d8892ced732e5211c13febe1528448e170de2211ae820561f08abd4 ./artix7/tile_type_HCLK_DSP_L.json`](./artix7/tile_type_HCLK_DSP_L.json)
|
||||
* [`ad94ca9de878402479ae3b5c42aca142a765f25b5053d0a1875a6b22ff4760eb ./artix7/tile_type_HCLK_DSP_R.json`](./artix7/tile_type_HCLK_DSP_R.json)
|
||||
* [`117742d824958474ae4c985f716aeb8f6d0255ebb4e93b4b22ec4cbebd73493f ./artix7/tile_type_HCLK_FEEDTHRU_1.json`](./artix7/tile_type_HCLK_FEEDTHRU_1.json)
|
||||
* [`db44dcb5af12e6e66f2477f44ba121e0394b3808474d52e25bfb835d700b4fc4 ./artix7/tile_type_HCLK_FEEDTHRU_2.json`](./artix7/tile_type_HCLK_FEEDTHRU_2.json)
|
||||
* [`f91905f72be0323f3427bfbf8615ea4799d851347f41046f859d9004466e5ccf ./artix7/tile_type_HCLK_FIFO_L.json`](./artix7/tile_type_HCLK_FIFO_L.json)
|
||||
* [`fc6af43c34178d5b5e080673a26baa7ed44484ef800d93fbeb8b6026a06f8859 ./artix7/tile_type_HCLK_GTX.json`](./artix7/tile_type_HCLK_GTX.json)
|
||||
* [`c2ead7265df3fda9aa1056488daa80f7d8b31959866532d34ecc395821d3e44c ./artix7/tile_type_HCLK_INT_INTERFACE.json`](./artix7/tile_type_HCLK_INT_INTERFACE.json)
|
||||
* [`0866a9609e0acbedd63892aaeb3dbfa46a14375e7287770662efb00ee7fb9670 ./artix7/tile_type_HCLK_IOB.json`](./artix7/tile_type_HCLK_IOB.json)
|
||||
* [`b1bcaaf22ef15255f34dea49050bbe3db17e38af0ed31a759da08a3c35302916 ./artix7/tile_type_HCLK_IOI3.json`](./artix7/tile_type_HCLK_IOI3.json)
|
||||
* [`f866e73583ae7269c9a21a178d882c0046cdf1bd828ed5573d6f2d01b8bb54de ./artix7/tile_type_HCLK_L_BOT_UTURN.json`](./artix7/tile_type_HCLK_L_BOT_UTURN.json)
|
||||
* [`6c754fd475874fab6952207bdc7d44600d0a705cd8ce14261541a15c337884d5 ./artix7/tile_type_HCLK_L.json`](./artix7/tile_type_HCLK_L.json)
|
||||
* [`6d7efdb19ccf327eb331bb4269a3a6d4ddbf51bbf9729436937ffe4ee9495c16 ./artix7/tile_type_HCLK_R_BOT_UTURN.json`](./artix7/tile_type_HCLK_R_BOT_UTURN.json)
|
||||
* [`3dfafe228d2d787894d9eebbe5d8c4f4df3c7ea6ea8c9b7d63f15874608f22ec ./artix7/tile_type_HCLK_R.json`](./artix7/tile_type_HCLK_R.json)
|
||||
* [`b7fd505820f6fcc6fcc19efb779a4a4e40d15bb85de04389762669d3b18c404d ./artix7/tile_type_HCLK_TERM_GTX.json`](./artix7/tile_type_HCLK_TERM_GTX.json)
|
||||
* [`e81d41e509abafabada7a4b09082055c4dc3d05a0de6787954c6a0c78b006686 ./artix7/tile_type_HCLK_TERM.json`](./artix7/tile_type_HCLK_TERM.json)
|
||||
* [`1ef1561b19e23833d98cfa1540fcd41354471c27f6f3c11ddca4fec205dad1aa ./artix7/tile_type_HCLK_VBRK.json`](./artix7/tile_type_HCLK_VBRK.json)
|
||||
* [`07bf11c14b2b7f4987005095198fed32bb591c55509c03d2e63c61df6db07893 ./artix7/tile_type_HCLK_VFRAME.json`](./artix7/tile_type_HCLK_VFRAME.json)
|
||||
* [`05e1236960af05dfc5ebe18026e4c4011ecd04edfbbbcd284df2cf7b6875d0c7 ./artix7/tile_type_INT_FEEDTHRU_1.json`](./artix7/tile_type_INT_FEEDTHRU_1.json)
|
||||
* [`c073d8ae07caa06180adbda01745e0fa2733a641c3e703c30b867daeec20a61b ./artix7/tile_type_INT_FEEDTHRU_2.json`](./artix7/tile_type_INT_FEEDTHRU_2.json)
|
||||
* [`e7a7ffb95790ba317d7a47bff696496a53f19cbe1cb0261a513a5ac6606a568e ./artix7/tile_type_INT_INTERFACE_L.json`](./artix7/tile_type_INT_INTERFACE_L.json)
|
||||
* [`4405be19600b04935365f8123af240b8ab0ec25ff052a503d294c16339308079 ./artix7/tile_type_INT_INTERFACE_R.json`](./artix7/tile_type_INT_INTERFACE_R.json)
|
||||
* [`8275617e0acbbeb35b0df2a11cfb106768c8ea60bdd19082f2ea16a1753be545 ./artix7/tile_type_INT_L.json`](./artix7/tile_type_INT_L.json)
|
||||
* [`1edf113aef203d9849919256d7b5b1b2f9b6a60c1a10c3ed3f9866bdf6bcda4f ./artix7/tile_type_INT_R.json`](./artix7/tile_type_INT_R.json)
|
||||
* [`e26af6a231cd198936c88592d3e5514dee9ef8eb757255100999ef808b424209 ./artix7/tile_type_IO_INT_INTERFACE_L.json`](./artix7/tile_type_IO_INT_INTERFACE_L.json)
|
||||
* [`80554391d69ec33de704eaf1439aa58cf49cab8a0a8c5e22a267b0e6de034f6d ./artix7/tile_type_IO_INT_INTERFACE_R.json`](./artix7/tile_type_IO_INT_INTERFACE_R.json)
|
||||
* [`92973342c7b314c2bc5cf3b0ed75b3d65ad9b4c699e86f0700276c61c6b69fae ./artix7/tile_type_LIOB33.json`](./artix7/tile_type_LIOB33.json)
|
||||
* [`19f2b3096119583851c4643118b352e323a3c5157c36de8c03400ab37a853842 ./artix7/tile_type_LIOB33_SING.json`](./artix7/tile_type_LIOB33_SING.json)
|
||||
* [`1d380cfc83aec25c875a74a2b6f1bd5c7d79dc700443b8e832ebc4c5d8a6baec ./artix7/tile_type_LIOI3.json`](./artix7/tile_type_LIOI3.json)
|
||||
* [`251628591dab790ba58e6b86f359107febe334c39df7e430332774ae548f5775 ./artix7/tile_type_LIOI3_SING.json`](./artix7/tile_type_LIOI3_SING.json)
|
||||
* [`41dd66811905f1878598a3df566d899184f5df4bb9254af1165cf7e81a2457a4 ./artix7/tile_type_LIOI3_TBYTESRC.json`](./artix7/tile_type_LIOI3_TBYTESRC.json)
|
||||
* [`f4417af95b67d9476bb1bbe9d96ba53d40e71eba0856e8d28b6f7f623a3fa2df ./artix7/tile_type_LIOI3_TBYTETERM.json`](./artix7/tile_type_LIOI3_TBYTETERM.json)
|
||||
* [`d428444e07aefe192d6bf53fe9aabefc71bc3f2481ce43f71903a1a6c23fdd10 ./artix7/tile_type_L_TERM_INT.json`](./artix7/tile_type_L_TERM_INT.json)
|
||||
* [`8872b68595befac5a7d1c9716b05dc134c4b91c1f34b498e98449a6fa64c227a ./artix7/tile_type_MONITOR_BOT.json`](./artix7/tile_type_MONITOR_BOT.json)
|
||||
* [`f05a388977b0569ebcce158348088e6dae8b5b48da3653ffa728e7f9f44c260c ./artix7/tile_type_MONITOR_MID.json`](./artix7/tile_type_MONITOR_MID.json)
|
||||
* [`d7e25cd7418dc6f49cdb49dff10af9412b5ee5187c95af9bdb1893ccfec6e4a1 ./artix7/tile_type_MONITOR_TOP.json`](./artix7/tile_type_MONITOR_TOP.json)
|
||||
* [`a4374e14cdaa70c70f0466e9e4c811bcc68d85fd141b838e9b2bb8bea8fe6df4 ./artix7/tile_type_NULL.json`](./artix7/tile_type_NULL.json)
|
||||
* [`3321ac396d19e3c6ea5e483f2e03eff301ca62d0896cc1a0d6bc1e5be88501b3 ./artix7/tile_type_PCIE_BOT.json`](./artix7/tile_type_PCIE_BOT.json)
|
||||
* [`92e09a5ee4f9016c7a58a15801630f6bc0e9c9643df9fb208c24118eda070919 ./artix7/tile_type_PCIE_INT_INTERFACE_L.json`](./artix7/tile_type_PCIE_INT_INTERFACE_L.json)
|
||||
* [`b2e0fa4a38dc2955ec6781d3d4acd45344b27db6de2b50252e07b086fd34ac10 ./artix7/tile_type_PCIE_INT_INTERFACE_R.json`](./artix7/tile_type_PCIE_INT_INTERFACE_R.json)
|
||||
* [`4524e5852158ddb5ec7aa70967e68b14989b5276ad78e9ac7474390c43151cef ./artix7/tile_type_PCIE_NULL.json`](./artix7/tile_type_PCIE_NULL.json)
|
||||
* [`5eb5efd2c31db2dc8d12a44663b8e16025acae53221ee9df9763a4cf76370681 ./artix7/tile_type_PCIE_TOP.json`](./artix7/tile_type_PCIE_TOP.json)
|
||||
* [`5b6df3b2e20ce4ffb0661e894e975f907ae726444244fb970c9fab1aa926e3d5 ./artix7/tile_type_RIOB33.json`](./artix7/tile_type_RIOB33.json)
|
||||
* [`3a62b1dfe986f4e35608cb1330c585b479bceaf57a21775ad505eb8fb8a95cd5 ./artix7/tile_type_RIOB33_SING.json`](./artix7/tile_type_RIOB33_SING.json)
|
||||
* [`04d224fe2e76d45376d3037f18b5f0aa5632503ab3d255e2d7d0757442111eac ./artix7/tile_type_RIOI3.json`](./artix7/tile_type_RIOI3.json)
|
||||
* [`f9b3f0d450f975541ed3740ee4038d3ff6669c33b6d0ccc1e81493f3e74f41cc ./artix7/tile_type_RIOI3_SING.json`](./artix7/tile_type_RIOI3_SING.json)
|
||||
* [`2c56c5f629504e4ebdeb2170e6f09313ad58130aa82c3d28dfba2f0135d23577 ./artix7/tile_type_RIOI3_TBYTESRC.json`](./artix7/tile_type_RIOI3_TBYTESRC.json)
|
||||
* [`a468c471f7dbd6f00d5743153b72529fed1c2b70dbf86144796ebfab3f858e9d ./artix7/tile_type_RIOI3_TBYTETERM.json`](./artix7/tile_type_RIOI3_TBYTETERM.json)
|
||||
* [`db40d427ccf1aff3cc792ac065afba46812d333698eabd46b0fe0d4dc1cb7e2a ./artix7/tile_type_R_TERM_INT_GTX.json`](./artix7/tile_type_R_TERM_INT_GTX.json)
|
||||
* [`89f3d258950a4313b243eb78a11a68e0097c2dcbe6ea40fa3c1dcd87fbb0feab ./artix7/tile_type_R_TERM_INT.json`](./artix7/tile_type_R_TERM_INT.json)
|
||||
* [`b44973d83b020d2da4ad0f968bc5365d596c1962f7cfd7365060776261b08fbd ./artix7/tile_type_TERM_CMT.json`](./artix7/tile_type_TERM_CMT.json)
|
||||
* [`0b2928bf771913d137df312a58dd915192733d25e7ba020bcfa70f23f8704e5a ./artix7/tile_type_T_TERM_INT.json`](./artix7/tile_type_T_TERM_INT.json)
|
||||
* [`5f641bc2117a4a45d6db58dff650df2c876f9f2ce6b60ca89a8813b2b32f627a ./artix7/tile_type_VBRK_EXT.json`](./artix7/tile_type_VBRK_EXT.json)
|
||||
* [`301ae67062447199afc4626fffe2e935d96b58002b133c285ade08e179392642 ./artix7/tile_type_VBRK.json`](./artix7/tile_type_VBRK.json)
|
||||
* [`5e105635aa264b9a73d178102ee2950519964cbe6e3d18a48070edfbe5c26e98 ./artix7/tile_type_VFRAME.json`](./artix7/tile_type_VFRAME.json)
|
||||
* [`a215bd6ad72742d242ed4d9e6712f393f57341577f9c5197e84c7d61635b9e18 ./artix7/settings.sh`](./artix7/settings.sh)
|
||||
* [`6e06cb20258401bb5fdf87fb01fdcebf75f3f7211cadd89b485c21be8eb7f852 ./artix7/site_type_BSCAN.json`](./artix7/site_type_BSCAN.json)
|
||||
* [`d88f7d6166556e1a059fef6136a078252575e50feeb3e1bfc6e10c1d25aabf02 ./artix7/site_type_BUFGCTRL.json`](./artix7/site_type_BUFGCTRL.json)
|
||||
* [`dfc738eefd3f5f71ff6f39bb921708b81ae49e9a280a82c896c3a66bfefb8e58 ./artix7/site_type_BUFHCE.json`](./artix7/site_type_BUFHCE.json)
|
||||
* [`444ab7c3176130e6f08a1b00f43de4a7be085fae27f3cc47330f2c939f2d84dd ./artix7/site_type_BUFIO.json`](./artix7/site_type_BUFIO.json)
|
||||
* [`0e5088865d6cb5f795ee85ee96000d74acfebedcd07f7dd7a0f276033e4add2a ./artix7/site_type_BUFMRCE.json`](./artix7/site_type_BUFMRCE.json)
|
||||
* [`548366a566791e5d0d2bf6be4e8b4a96ec5893b4e108b9c92323f32710714bb8 ./artix7/site_type_BUFR.json`](./artix7/site_type_BUFR.json)
|
||||
* [`3a57071763e617312ef771029537a9ac29774b0aa757e77489fecb2f30971327 ./artix7/site_type_CAPTURE.json`](./artix7/site_type_CAPTURE.json)
|
||||
* [`5bb9dc6b888ef106dd6c56849ab2856b9b4e5988467672cf4966f3108c130a26 ./artix7/site_type_DCIRESET.json`](./artix7/site_type_DCIRESET.json)
|
||||
* [`fbe70221478cf4568f062ae6d039d349faba2c56cc76516b829887ae100b8915 ./artix7/site_type_DNA_PORT.json`](./artix7/site_type_DNA_PORT.json)
|
||||
* [`5c22c33d2185b4103ab60191e459d52b10ca43aa7cf069e8a8a15477ef5f95d8 ./artix7/site_type_DSP48E1.json`](./artix7/site_type_DSP48E1.json)
|
||||
* [`2a7e9bbe8bd61dbe085098ffadbe228a2a965b98198016baa8593615cba7408e ./artix7/site_type_EFUSE_USR.json`](./artix7/site_type_EFUSE_USR.json)
|
||||
* [`44da7fa75c6fb7b0f2f2be9e0b6e464631f143b2b6be3a867d3a004bac4b413e ./artix7/site_type_FIFO18E1.json`](./artix7/site_type_FIFO18E1.json)
|
||||
* [`1b9235a8849c1812886050948bb0cf1b287feea46ee303d8c9dd3b3ccc8957ba ./artix7/site_type_FRAME_ECC.json`](./artix7/site_type_FRAME_ECC.json)
|
||||
* [`a65074a1581355e1950ab39bf8ac5b13b7050d3f3b221b2f7ecf26cc1d984155 ./artix7/site_type_GTPE2_CHANNEL.json`](./artix7/site_type_GTPE2_CHANNEL.json)
|
||||
* [`f5b3a1e66bd974bcfeacdf7416837ff422fbf7dc3597518044e934d80718322b ./artix7/site_type_GTPE2_COMMON.json`](./artix7/site_type_GTPE2_COMMON.json)
|
||||
* [`d47a9d38e5c2e3111581214aebb2d870078fd2c091a163bf97e0a566e05688de ./artix7/site_type_IBUFDS_GTE2.json`](./artix7/site_type_IBUFDS_GTE2.json)
|
||||
* [`69d78ced4cf721f89e674f38a6c49eb1ff71afa1e589adae11581d3912721769 ./artix7/site_type_ICAP.json`](./artix7/site_type_ICAP.json)
|
||||
* [`a19bf15832620c26bcdaee163233ff1ce494de24bf345aae0614e2247601105e ./artix7/site_type_IDELAYCTRL.json`](./artix7/site_type_IDELAYCTRL.json)
|
||||
* [`969e58b5b790ef8cfb4ee2012baebef3a39e1641868a377e1a46d522acd6f7b4 ./artix7/site_type_IDELAYE2.json`](./artix7/site_type_IDELAYE2.json)
|
||||
* [`15badbd4e07896d3ea37b8b82bd82b74566302ee3ca7f1b66de6ef30c76ee3a0 ./artix7/site_type_ILOGICE3.json`](./artix7/site_type_ILOGICE3.json)
|
||||
* [`8005263511ad2099529bfadce9d0fd26b325ff08cc26c3e453bef26feec16f16 ./artix7/site_type_IN_FIFO.json`](./artix7/site_type_IN_FIFO.json)
|
||||
* [`98f08f89f011fe4a771b13bc62dba8e00e13186dcbe7b28ca6d2f3fe02c6ff58 ./artix7/site_type_IOB33.json`](./artix7/site_type_IOB33.json)
|
||||
* [`5942ca033249bcea32b252c912242bded0deb76d1175eba4e25396071c081995 ./artix7/site_type_IOB33M.json`](./artix7/site_type_IOB33M.json)
|
||||
* [`8d78bbf83cf8d8b3aa991d8f264d37636a8b9325791da95a914305606b946bb8 ./artix7/site_type_IOB33S.json`](./artix7/site_type_IOB33S.json)
|
||||
* [`2aebf9864f4098079d92ffa96240a18b2000b33dc04c956a4923828ed76f1a1a ./artix7/site_type_IPAD.json`](./artix7/site_type_IPAD.json)
|
||||
* [`05f7828421936f9e19de05d74716ef05bf77bb45c465014f458156b5d3335a05 ./artix7/site_type_MMCME2_ADV.json`](./artix7/site_type_MMCME2_ADV.json)
|
||||
* [`fe0943b7dc522a8df20a9ee3be5630ace77e041bd8669a1decb0664c82e61eca ./artix7/site_type_OLOGICE3.json`](./artix7/site_type_OLOGICE3.json)
|
||||
* [`d7bfe04a1abfb90fd1df4177c299229f981a036b63dd3f0be3677691b11ce66d ./artix7/site_type_OPAD.json`](./artix7/site_type_OPAD.json)
|
||||
* [`4cbd4bc0abc0c443003f96c17ddc8d3d2478546dd72f6e27473f12236841efc9 ./artix7/site_type_OUT_FIFO.json`](./artix7/site_type_OUT_FIFO.json)
|
||||
* [`0dd1a141a8bbb557e4ecd87b99901b4fd3cd1736e9e9aec7e00547a1f4b710cd ./artix7/site_type_PCIE_2_1.json`](./artix7/site_type_PCIE_2_1.json)
|
||||
* [`b234738303731a015f58fade2face8c4c885e8fb2e3de2250099e81e2d0f2821 ./artix7/site_type_PHASER_IN_PHY.json`](./artix7/site_type_PHASER_IN_PHY.json)
|
||||
* [`69c4ea774cfadfd7fa09bb35af1705a2733a3d07766e6e42c14667bff4c9fe35 ./artix7/site_type_PHASER_OUT_PHY.json`](./artix7/site_type_PHASER_OUT_PHY.json)
|
||||
* [`faba56326335ae03eccaf32a432a3a85051981057f38a348c3fee195e0b05c5c ./artix7/site_type_PHASER_REF.json`](./artix7/site_type_PHASER_REF.json)
|
||||
* [`d6cdfb4118627eac3cab985a95fa694e98389915352173e7564ad2571e510fe5 ./artix7/site_type_PHY_CONTROL.json`](./artix7/site_type_PHY_CONTROL.json)
|
||||
* [`52d56538d2113f810ec7a47f7439a9dbf9d7f6c4de40d981193af96634050845 ./artix7/site_type_PLLE2_ADV.json`](./artix7/site_type_PLLE2_ADV.json)
|
||||
* [`462191edfc3612812231c8fa64e788cfdcc23ea4de1f775e0ceed5b08fce4296 ./artix7/site_type_PMV2.json`](./artix7/site_type_PMV2.json)
|
||||
* [`e3073519cf2423ca2218ff0e60cc77a21c490ffa36032f5ec1b0760b02b8f2f2 ./artix7/site_type_RAMB18E1.json`](./artix7/site_type_RAMB18E1.json)
|
||||
* [`808ec16777af9a53a65f1669c56be3431247188b2381f7133ef6dc8ce797c466 ./artix7/site_type_RAMBFIFO36E1.json`](./artix7/site_type_RAMBFIFO36E1.json)
|
||||
* [`bb2fd61165fb0c50cd9ef622c1dc630044c3dd639754a613d8d9444505cb24d2 ./artix7/site_type_SLICEL.json`](./artix7/site_type_SLICEL.json)
|
||||
* [`0c5f1e1e92a453d193c5b49d1ec25d6da108bc3616965a8c437b6b16a30c4553 ./artix7/site_type_SLICEM.json`](./artix7/site_type_SLICEM.json)
|
||||
* [`1fe58f3068e4ba6b12dc75c1d187ba4ce829ae817f3924b1724f261ea569dcd3 ./artix7/site_type_STARTUP.json`](./artix7/site_type_STARTUP.json)
|
||||
* [`b246bc35a9bba6216fcc13a782361339a7b648e55cffb588a2393e0349003363 ./artix7/site_type_TIEOFF.json`](./artix7/site_type_TIEOFF.json)
|
||||
* [`6b1d14a3ab0749af2eb8fb6fbddd301f7e9643770521a18a7056ccea1852069d ./artix7/site_type_USR_ACCESS.json`](./artix7/site_type_USR_ACCESS.json)
|
||||
* [`b59ace663846a969f38d65d237840b8bfc1ff46d79722ddb3f9612d551036aa5 ./artix7/site_type_XADC.json`](./artix7/site_type_XADC.json)
|
||||
* [`907723c538bc8eb3739e894fdcfd82df3c3485f0b1345dc56cc7b0b8bf6c0edb ./artix7/tileconn.json`](./artix7/tileconn.json)
|
||||
* [`41df900062b5d42d53530bb7256f32c2d7bf9897b1a37567a80f35e9534e965b ./artix7/tilegrid.json`](./artix7/tilegrid.json)
|
||||
* [`6356dd92dc8ad3ec1f1d433a8fe7b353ea9ab5bfc336c0c5ec8f8d1edd7c576d ./artix7/tile_type_BRAM_INT_INTERFACE_L.json`](./artix7/tile_type_BRAM_INT_INTERFACE_L.json)
|
||||
* [`f4c47c50a489cd31281f0a70251bc01e94535a00f8ed57d460f8128e7b046b2c ./artix7/tile_type_BRAM_INT_INTERFACE_R.json`](./artix7/tile_type_BRAM_INT_INTERFACE_R.json)
|
||||
* [`3d330dae26477da58bfc146bacbbd4093cf6a32cb2c57ba4aebf1a792978a87e ./artix7/tile_type_BRAM_L.json`](./artix7/tile_type_BRAM_L.json)
|
||||
* [`37670b787af2fe94fc9117fc9c13eb1220e63d9b164b7671a70b134dfbc04eed ./artix7/tile_type_BRAM_R.json`](./artix7/tile_type_BRAM_R.json)
|
||||
* [`133963431bc4ce086281515049ab9686991e3b06833a20d44f9cc0a54beee1ab ./artix7/tile_type_BRKH_BRAM.json`](./artix7/tile_type_BRKH_BRAM.json)
|
||||
* [`5d236a4fde8e4d2fa3e8b3ab42c36fed30584538020fe944bcab14ec0cd867e0 ./artix7/tile_type_BRKH_B_TERM_INT.json`](./artix7/tile_type_BRKH_B_TERM_INT.json)
|
||||
* [`ccc47c69cac00b32b794d10912213cd29204b74418ddff980839073f6b2669a7 ./artix7/tile_type_BRKH_CLB.json`](./artix7/tile_type_BRKH_CLB.json)
|
||||
* [`c5e828e2a3991a145ed3cd270f18605d306aff50636f08a4ce26ac6951569cf3 ./artix7/tile_type_BRKH_CLK.json`](./artix7/tile_type_BRKH_CLK.json)
|
||||
* [`3cb8824582eac4d85e245349d82893cd8308ca0983fcb951f22ae94cc38b155e ./artix7/tile_type_BRKH_CMT.json`](./artix7/tile_type_BRKH_CMT.json)
|
||||
* [`43d7deb15885c9a4d1000bbcb0da828a2c7e88ca5d2f2ffd2be53e7506cee877 ./artix7/tile_type_BRKH_DSP_L.json`](./artix7/tile_type_BRKH_DSP_L.json)
|
||||
* [`26fe1a5dec260f5dc62c1eea8491fb22902e19cb274cc39c3814682bc986e892 ./artix7/tile_type_BRKH_DSP_R.json`](./artix7/tile_type_BRKH_DSP_R.json)
|
||||
* [`6dd978f8089f759ec788de1b2ef6aad9e5abdc3c4745fe6c04439fd9953c1b76 ./artix7/tile_type_BRKH_GTX.json`](./artix7/tile_type_BRKH_GTX.json)
|
||||
* [`0368e3a2ac3845ace5b9ff358659a647ec77d437bd1c18eb42c2379fa46d906b ./artix7/tile_type_BRKH_INT.json`](./artix7/tile_type_BRKH_INT.json)
|
||||
* [`8934e08a1178fb80ac93336ff8f3c10d34b933cf8bcf3788a303c2ec94df23b7 ./artix7/tile_type_BRKH_TERM_INT.json`](./artix7/tile_type_BRKH_TERM_INT.json)
|
||||
* [`b7ae936c572bb3c3933717690b2b96c620d6e01bb5f379fc4944bc31c0dba6cd ./artix7/tile_type_B_TERM_INT.json`](./artix7/tile_type_B_TERM_INT.json)
|
||||
* [`1af9a9a3b920d1370d1ef8454792975d8f67ae3333fbdddaff924171b2e54605 ./artix7/tile_type_CFG_CENTER_BOT.json`](./artix7/tile_type_CFG_CENTER_BOT.json)
|
||||
* [`07121c342f17ab519357852dfc766d6d1acadc4faae232dcf2f6880980e1161a ./artix7/tile_type_CFG_CENTER_MID.json`](./artix7/tile_type_CFG_CENTER_MID.json)
|
||||
* [`45ea67079399a2a8cfdf7d72d2923f4175e41b22ef1a8d133ea3fe767a54dd03 ./artix7/tile_type_CFG_CENTER_TOP.json`](./artix7/tile_type_CFG_CENTER_TOP.json)
|
||||
* [`580ec91c785cd5b03aced9a8847874ba55684392919d48db4b1978ee4967600b ./artix7/tile_type_CLBLL_L.json`](./artix7/tile_type_CLBLL_L.json)
|
||||
* [`c00ca5ec419fadaef8b9821a0942b5e814701857fe7ea8a4473b72c537d0250b ./artix7/tile_type_CLBLL_R.json`](./artix7/tile_type_CLBLL_R.json)
|
||||
* [`f3793273d2cc799eeb2e6edad90a8080f578d926999745c21444a5ddc25c73a1 ./artix7/tile_type_CLBLM_L.json`](./artix7/tile_type_CLBLM_L.json)
|
||||
* [`e56ab784988141c82a6f77a014e5d14b361ca00f4c475730dd7a045d9ca0eba6 ./artix7/tile_type_CLBLM_R.json`](./artix7/tile_type_CLBLM_R.json)
|
||||
* [`4246e4895570060ecb2b8e9b07ccb6812f760ab0cd77b8940a90046b20b5adea ./artix7/tile_type_CLK_BUFG_BOT_R.json`](./artix7/tile_type_CLK_BUFG_BOT_R.json)
|
||||
* [`cc4b2ba2649cfaabb7cb47ed6b65fcd0d1bd4b219e57d57635e7cb4cb8b0d0ca ./artix7/tile_type_CLK_BUFG_REBUF.json`](./artix7/tile_type_CLK_BUFG_REBUF.json)
|
||||
* [`97c1b94fa8cc6100f2d2ef3ff7ac82d8ccc2cf71dbcb47d8d0f8a743ace2a69c ./artix7/tile_type_CLK_BUFG_TOP_R.json`](./artix7/tile_type_CLK_BUFG_TOP_R.json)
|
||||
* [`8f6853d4a9b77e55806ab06116639227901b390306704adbca542b62e6914e42 ./artix7/tile_type_CLK_FEED.json`](./artix7/tile_type_CLK_FEED.json)
|
||||
* [`fc157995da3124034ef029a08f78e19633765ee018e9cbf62571fac205573508 ./artix7/tile_type_CLK_HROW_BOT_R.json`](./artix7/tile_type_CLK_HROW_BOT_R.json)
|
||||
* [`0de1f23baabaf73e41ea76ae873174f695763388d49e22e5c9796d25183a4bbf ./artix7/tile_type_CLK_HROW_TOP_R.json`](./artix7/tile_type_CLK_HROW_TOP_R.json)
|
||||
* [`833bdb0d9af9117e448781202bc61c3b00277c91d6e50490c8c8f9e02751ac76 ./artix7/tile_type_CLK_MTBF2.json`](./artix7/tile_type_CLK_MTBF2.json)
|
||||
* [`7182ef530e88cb9ad13b7c586b36c835a6e0b9f1a15e5a7164c2dd40204e2822 ./artix7/tile_type_CLK_PMV2.json`](./artix7/tile_type_CLK_PMV2.json)
|
||||
* [`839aadd33956b87fee5cfdac2e75829e5dbf3a74837de40e7b4ce9f305e635de ./artix7/tile_type_CLK_PMV2_SVT.json`](./artix7/tile_type_CLK_PMV2_SVT.json)
|
||||
* [`5a7c64a08d0e9399a04da58087c0e1ef2ea13bc879efcfc70c68d716781fbead ./artix7/tile_type_CLK_PMVIOB.json`](./artix7/tile_type_CLK_PMVIOB.json)
|
||||
* [`d3c479f6f586d43cfd26ddab08f5a51b15c882c0c72075dc9423392d232d17ae ./artix7/tile_type_CLK_PMV.json`](./artix7/tile_type_CLK_PMV.json)
|
||||
* [`67d0b147735439607eb0facca9b73df19173a3985bfd18d06826e9404a85f286 ./artix7/tile_type_CLK_TERM.json`](./artix7/tile_type_CLK_TERM.json)
|
||||
* [`36e91b08239972628f8d807fcc62469fe5d5c64e385ca6bfbcc8d8ceaae3a396 ./artix7/tile_type_CMT_FIFO_L.json`](./artix7/tile_type_CMT_FIFO_L.json)
|
||||
* [`816c98fa7b2fb9e4e797ba79d00b0ac77d85fa900f041aeb08676936a7ef9a08 ./artix7/tile_type_CMT_FIFO_R.json`](./artix7/tile_type_CMT_FIFO_R.json)
|
||||
* [`ae4f0edb9d3a2041fd00a3eebdd466bff555315486310cfb7f6c8d0954a0e812 ./artix7/tile_type_CMT_PMV.json`](./artix7/tile_type_CMT_PMV.json)
|
||||
* [`e015952fc06a5f7bd7daa9fcbb149881d96de31fcfd87bce8225216c2ba77370 ./artix7/tile_type_CMT_PMV_L.json`](./artix7/tile_type_CMT_PMV_L.json)
|
||||
* [`d488d4c336d73b1c3f876e94e32f5cec85c2c65036018df4d2af10f7b0c7da18 ./artix7/tile_type_CMT_TOP_L_LOWER_B.json`](./artix7/tile_type_CMT_TOP_L_LOWER_B.json)
|
||||
* [`f55ba22266c49bb2792ce81b90e2f221384065e1ec10a02a390695ea2ec6a83f ./artix7/tile_type_CMT_TOP_L_LOWER_T.json`](./artix7/tile_type_CMT_TOP_L_LOWER_T.json)
|
||||
* [`68be7fc8a5f5b5e7e4a2c93e919ae3bc00a692589b7b0d95997d80de60a04275 ./artix7/tile_type_CMT_TOP_L_UPPER_B.json`](./artix7/tile_type_CMT_TOP_L_UPPER_B.json)
|
||||
* [`175f10cc9e689c13a42a680bbe18d37bb5e07f7ef5fcfe1fc17ed45d9dd6f4a3 ./artix7/tile_type_CMT_TOP_L_UPPER_T.json`](./artix7/tile_type_CMT_TOP_L_UPPER_T.json)
|
||||
* [`7a13fe99e2c202da444123e300692bcb324fd9c10aac9b2d0dadd527a6c6731f ./artix7/tile_type_CMT_TOP_R_LOWER_B.json`](./artix7/tile_type_CMT_TOP_R_LOWER_B.json)
|
||||
* [`686116b0a5f38a5f0b46083608eda6c0d134198058b4837624037909264bf519 ./artix7/tile_type_CMT_TOP_R_LOWER_T.json`](./artix7/tile_type_CMT_TOP_R_LOWER_T.json)
|
||||
* [`f2343f190fe4e9ae1383115113e68b2b7e771b4a84869de9691b5cc522892222 ./artix7/tile_type_CMT_TOP_R_UPPER_B.json`](./artix7/tile_type_CMT_TOP_R_UPPER_B.json)
|
||||
* [`56758e082ded7986405779e89d0289f02b7f7bce4db9334defe5b1f43275faa3 ./artix7/tile_type_CMT_TOP_R_UPPER_T.json`](./artix7/tile_type_CMT_TOP_R_UPPER_T.json)
|
||||
* [`96f878723ba2388e9dad84fd814290fffad65ca5364750369788978606874378 ./artix7/tile_type_DSP_L.json`](./artix7/tile_type_DSP_L.json)
|
||||
* [`b06477da1adad00b2de65b615c6a55f4538169f93a409095c0c963f172969543 ./artix7/tile_type_DSP_R.json`](./artix7/tile_type_DSP_R.json)
|
||||
* [`c366ecc3619a2e578b0d2823cf6ed88b1e78d216196a06cbcc02793ee782cfca ./artix7/tile_type_GTP_CHANNEL_0.json`](./artix7/tile_type_GTP_CHANNEL_0.json)
|
||||
* [`7bf0277080473beebc905e4fe35d8f4342b5bd38cd95e31d0e291a4efc499d8d ./artix7/tile_type_GTP_CHANNEL_1.json`](./artix7/tile_type_GTP_CHANNEL_1.json)
|
||||
* [`d54dab3a77a24af47ae1e0e91f12c7e0d188fb20ffeb12cc6b0e9234d48fd3b3 ./artix7/tile_type_GTP_CHANNEL_2.json`](./artix7/tile_type_GTP_CHANNEL_2.json)
|
||||
* [`5e341fa5b0ff19d4ebb48279a36f6817b2cda45c15b6da0a29da79e9b8c8ca86 ./artix7/tile_type_GTP_CHANNEL_3.json`](./artix7/tile_type_GTP_CHANNEL_3.json)
|
||||
* [`1226a9185be15fbe197e024ca1f3df67a4ad21cf855b519a2a706928ec5dc0d1 ./artix7/tile_type_GTP_COMMON.json`](./artix7/tile_type_GTP_COMMON.json)
|
||||
* [`92ebe3a0813a866ca7eb4e39b2b959bc2bcd14b20ce76961e9e31674140ca80a ./artix7/tile_type_GTP_INT_INTERFACE.json`](./artix7/tile_type_GTP_INT_INTERFACE.json)
|
||||
* [`2103859c8eab4c32a335592cb3a009e036238d98642664b4cc21bab71f299b78 ./artix7/tile_type_HCLK_BRAM.json`](./artix7/tile_type_HCLK_BRAM.json)
|
||||
* [`147fa108c950b89ad0c5f86983239dcbc2f4c9ac7126499b2e2d4026d7686bfe ./artix7/tile_type_HCLK_CLB.json`](./artix7/tile_type_HCLK_CLB.json)
|
||||
* [`937444c2e4b8f3df717eadd832cf973474d7e97eecf4f21b7a70417ec75a4e81 ./artix7/tile_type_HCLK_CMT.json`](./artix7/tile_type_HCLK_CMT.json)
|
||||
* [`819ee4728cfed0daef54ce4594028e4dd718887ce5058b4b5e121cda6d6481e4 ./artix7/tile_type_HCLK_CMT_L.json`](./artix7/tile_type_HCLK_CMT_L.json)
|
||||
* [`916fc0a327bf43dc2a3f12ae6969bc7ebe80384a5a2f5a3eca55675eb5adc88a ./artix7/tile_type_HCLK_DSP_L.json`](./artix7/tile_type_HCLK_DSP_L.json)
|
||||
* [`d614d7b300cf0edffd5956b0e7559f25bdf04118ea04c286a80bef7fa486cc91 ./artix7/tile_type_HCLK_DSP_R.json`](./artix7/tile_type_HCLK_DSP_R.json)
|
||||
* [`0ce351c5aecb49f1f24d9eee219cabeb72febbb5c5d09fb371e0e255f2ad09c4 ./artix7/tile_type_HCLK_FEEDTHRU_1.json`](./artix7/tile_type_HCLK_FEEDTHRU_1.json)
|
||||
* [`5797792a339615dacccda4c1e5a52d5b7b34f391beffa19024d86aad3ce88cd5 ./artix7/tile_type_HCLK_FEEDTHRU_2.json`](./artix7/tile_type_HCLK_FEEDTHRU_2.json)
|
||||
* [`a772601f527ba7be10d32404995d0f5426bb8e78a8d6b3f081526a22560ae712 ./artix7/tile_type_HCLK_FIFO_L.json`](./artix7/tile_type_HCLK_FIFO_L.json)
|
||||
* [`9e421a5a9145b46b21e106827d6668575e993bd5f21c4afb46dcf3c8b170b09f ./artix7/tile_type_HCLK_GTX.json`](./artix7/tile_type_HCLK_GTX.json)
|
||||
* [`e83dd138edc732989b7a98769b8fb40d0035d02c036bf9326faf9e92ec2b3838 ./artix7/tile_type_HCLK_INT_INTERFACE.json`](./artix7/tile_type_HCLK_INT_INTERFACE.json)
|
||||
* [`0fae33b58ec0697b8fc8290484a88eabe768cfcc849924166a0e10d97fe775a4 ./artix7/tile_type_HCLK_IOB.json`](./artix7/tile_type_HCLK_IOB.json)
|
||||
* [`994e7f7b016d690357bff6c2603b53e10a68df8e8d3996edbb4b1bd7a0934107 ./artix7/tile_type_HCLK_IOI3.json`](./artix7/tile_type_HCLK_IOI3.json)
|
||||
* [`d743ebc6d7f0b21eac6d440bfc14b709012167d4534c0ce12323d332975721a0 ./artix7/tile_type_HCLK_L_BOT_UTURN.json`](./artix7/tile_type_HCLK_L_BOT_UTURN.json)
|
||||
* [`df7f40d36ccc7e747aadce47160719c15dfa5185f5833c0ba75a4ea402530864 ./artix7/tile_type_HCLK_L.json`](./artix7/tile_type_HCLK_L.json)
|
||||
* [`28492670f4e6ec07178c16bb3781dca7740a5a386daab4d22ae1f5c19a688a67 ./artix7/tile_type_HCLK_R_BOT_UTURN.json`](./artix7/tile_type_HCLK_R_BOT_UTURN.json)
|
||||
* [`a55fa19083d178a580e013f7434698cc379541de843e3203aa23a8b0c74824a3 ./artix7/tile_type_HCLK_R.json`](./artix7/tile_type_HCLK_R.json)
|
||||
* [`8166f2b9660d099930ef5295d8cf865952164e41c803dbad65d08268afd7abb3 ./artix7/tile_type_HCLK_TERM_GTX.json`](./artix7/tile_type_HCLK_TERM_GTX.json)
|
||||
* [`dab5572a041a5783fc7e71a735209dee881400f9ee79cc93c3624200d0454706 ./artix7/tile_type_HCLK_TERM.json`](./artix7/tile_type_HCLK_TERM.json)
|
||||
* [`fae6daec23c58a0bccb223052c4f9b36e37f4c3ace67b5e8189566d366006ba7 ./artix7/tile_type_HCLK_VBRK.json`](./artix7/tile_type_HCLK_VBRK.json)
|
||||
* [`c6099ae4a5e0154de6ef1d219b70c8612017dc3465d6958e6eccb3fdd0c12805 ./artix7/tile_type_HCLK_VFRAME.json`](./artix7/tile_type_HCLK_VFRAME.json)
|
||||
* [`b600208dd374c8059c89b757770eca2392262b638a49e67bba21e6323112da06 ./artix7/tile_type_INT_FEEDTHRU_1.json`](./artix7/tile_type_INT_FEEDTHRU_1.json)
|
||||
* [`aced5f852446d59b79f27aee4ec475908a81dac0353566de51ffb7ef68b5745d ./artix7/tile_type_INT_FEEDTHRU_2.json`](./artix7/tile_type_INT_FEEDTHRU_2.json)
|
||||
* [`7f992ab27ef35aded6066064690baa80299280d02dfa911f94a4e7b1a4a54b42 ./artix7/tile_type_INT_INTERFACE_L.json`](./artix7/tile_type_INT_INTERFACE_L.json)
|
||||
* [`1ead2b9f6c42fccaf6a8ee461cb3e6779547fe0802811377591f54b40ce2cbf3 ./artix7/tile_type_INT_INTERFACE_R.json`](./artix7/tile_type_INT_INTERFACE_R.json)
|
||||
* [`335a1441fbdae94463f27b548f1ad43bf0576013fa9fd1dd59f56f699c6cd959 ./artix7/tile_type_INT_L.json`](./artix7/tile_type_INT_L.json)
|
||||
* [`f48b15a421b553c5a5a7b07cd13d85c6ba9281c416d2ef3c3d82225b3aeb1e7e ./artix7/tile_type_INT_R.json`](./artix7/tile_type_INT_R.json)
|
||||
* [`bf4eadb5aaed8794d7a6d924913eacb4e1246b7deb831a76de357d2200ef4ba8 ./artix7/tile_type_IO_INT_INTERFACE_L.json`](./artix7/tile_type_IO_INT_INTERFACE_L.json)
|
||||
* [`73b411ab0c6a64f99e89419d8e4dbd43008642cdc2a5c808cee181b0a78362c5 ./artix7/tile_type_IO_INT_INTERFACE_R.json`](./artix7/tile_type_IO_INT_INTERFACE_R.json)
|
||||
* [`4cabd902bb0c365a5f73517614fb7f6cba68795618dbc2ac8faf89a576a68d14 ./artix7/tile_type_LIOB33.json`](./artix7/tile_type_LIOB33.json)
|
||||
* [`cb9f409f31747dab0dd2e223cd94c0f6cb8bcc42d9e86307d9514fbae9f531a9 ./artix7/tile_type_LIOB33_SING.json`](./artix7/tile_type_LIOB33_SING.json)
|
||||
* [`7b309379d9f838a16267f0ec169f81bacc10c56d34585bdda8c08a0a15ad5206 ./artix7/tile_type_LIOI3.json`](./artix7/tile_type_LIOI3.json)
|
||||
* [`4eff79aab044ef13040f7faa3f58ca142f5d14070c625ec23d0d6246d0c9959c ./artix7/tile_type_LIOI3_SING.json`](./artix7/tile_type_LIOI3_SING.json)
|
||||
* [`151c56730a8a9ab5ec9b647d12e99be6797427e4ee83b0298bb64c7dd180cf6b ./artix7/tile_type_LIOI3_TBYTESRC.json`](./artix7/tile_type_LIOI3_TBYTESRC.json)
|
||||
* [`dbf7d9e7a0037c00cd0293e6179a888061ec3f4de471a739f160b06b35f2d183 ./artix7/tile_type_LIOI3_TBYTETERM.json`](./artix7/tile_type_LIOI3_TBYTETERM.json)
|
||||
* [`c4fcf212d0da1576a4b7592baac2991770b8efa970698f7ee86fa64e7df5850f ./artix7/tile_type_L_TERM_INT.json`](./artix7/tile_type_L_TERM_INT.json)
|
||||
* [`9f1fb838d0ef958ed8ae1f645821efd17490ae905f8bb9c6f4a31e56bf5a260a ./artix7/tile_type_MONITOR_BOT.json`](./artix7/tile_type_MONITOR_BOT.json)
|
||||
* [`8d9ebbe2124c95c29e434669a9f235bb3172342f9954a389c493d5b90de9d2a8 ./artix7/tile_type_MONITOR_MID.json`](./artix7/tile_type_MONITOR_MID.json)
|
||||
* [`e5c8f860810967712fc9bca81b6507b4b745a4097c7a167197cb7e2c32221b79 ./artix7/tile_type_MONITOR_TOP.json`](./artix7/tile_type_MONITOR_TOP.json)
|
||||
* [`6b16e9202757be322b72cdcd73f45a1e61252444ef4ee6557272fc8361d87557 ./artix7/tile_type_NULL.json`](./artix7/tile_type_NULL.json)
|
||||
* [`3c1d65f24e5a14adf1fad58418d9d80a0fc501767c7c57ae6b03c761d9e6ec49 ./artix7/tile_type_PCIE_BOT.json`](./artix7/tile_type_PCIE_BOT.json)
|
||||
* [`e88f6157dd103e57fb6a09ad61e08e3390491f3e2e680ed158851761b416b297 ./artix7/tile_type_PCIE_INT_INTERFACE_L.json`](./artix7/tile_type_PCIE_INT_INTERFACE_L.json)
|
||||
* [`1ba5597c9b4759001c507d6cde338b8ce6ffeba1cd303b3332a34a909eae6ada ./artix7/tile_type_PCIE_INT_INTERFACE_R.json`](./artix7/tile_type_PCIE_INT_INTERFACE_R.json)
|
||||
* [`e39fb1e8b8c9d0d9da3307a260fee2bf05ad0f6dfa9456b90a031893b7131e2e ./artix7/tile_type_PCIE_NULL.json`](./artix7/tile_type_PCIE_NULL.json)
|
||||
* [`6916ac8353f91f6ef993cde1accb0f4c23e4f0530864a211b09e2dc002ec8f07 ./artix7/tile_type_PCIE_TOP.json`](./artix7/tile_type_PCIE_TOP.json)
|
||||
* [`08e94d8c944671afa5fb5f3ba934b94d455213ecb8f0561f74b01a4579307ca9 ./artix7/tile_type_RIOB33.json`](./artix7/tile_type_RIOB33.json)
|
||||
* [`630e9e7920452cbb1bb3be49ca3cc4d2df84c55376891319d718bb73a1a44560 ./artix7/tile_type_RIOB33_SING.json`](./artix7/tile_type_RIOB33_SING.json)
|
||||
* [`dee0eac7b1fd18fdafe9b6707f17e3aaaafdf3d114e975751842824043413f79 ./artix7/tile_type_RIOI3.json`](./artix7/tile_type_RIOI3.json)
|
||||
* [`e9a298be79752276ff2bc65aacf0a772e46eab6ef97993181dbd1468ee4bfffa ./artix7/tile_type_RIOI3_SING.json`](./artix7/tile_type_RIOI3_SING.json)
|
||||
* [`811820d57f2b09a2da967f27721e2fae0067ce1ed48e00e84082aa909f279177 ./artix7/tile_type_RIOI3_TBYTESRC.json`](./artix7/tile_type_RIOI3_TBYTESRC.json)
|
||||
* [`071c62417007e1c5769a1e094da3e3920051e222066248a3a496af471f11a4e3 ./artix7/tile_type_RIOI3_TBYTETERM.json`](./artix7/tile_type_RIOI3_TBYTETERM.json)
|
||||
* [`1b0a39d14effc60a06ad9b395c2a5991fd961a12c029b62864d8d3cff89ba9a6 ./artix7/tile_type_R_TERM_INT_GTX.json`](./artix7/tile_type_R_TERM_INT_GTX.json)
|
||||
* [`f2ad48f977bf23568f1e46b19c71bf92307199ef674a948804e35b3f5ebd586a ./artix7/tile_type_R_TERM_INT.json`](./artix7/tile_type_R_TERM_INT.json)
|
||||
* [`84fae385439211f2c3020e7fda6bcafdf8173d5a7d40493c3bb2e8145eb13474 ./artix7/tile_type_TERM_CMT.json`](./artix7/tile_type_TERM_CMT.json)
|
||||
* [`45b4dd6d5936e5d8e554417006bef838a5dcc93fca9e1a1928a5fc57ffc4498c ./artix7/tile_type_T_TERM_INT.json`](./artix7/tile_type_T_TERM_INT.json)
|
||||
* [`27efff498583b8a2d6a488a28036f907e0849e8ed7b28c9bb19df5376016815a ./artix7/tile_type_VBRK_EXT.json`](./artix7/tile_type_VBRK_EXT.json)
|
||||
* [`fd0b5a76321e846df69abd82062db6ee6c0ebace89c9c3d0bb09722ef2de999e ./artix7/tile_type_VBRK.json`](./artix7/tile_type_VBRK.json)
|
||||
* [`3b1f73177e0f162741cd791b01da13b9d5baf1d16bac36bdcbec1ea3047f388f ./artix7/tile_type_VFRAME.json`](./artix7/tile_type_VFRAME.json)
|
||||
* [`ef0724733da87455426a0f833642d96e9d206d047f4eb97072c3093f80c40d7d ./artix7/xc7a35tcpg236-1.yaml`](./artix7/xc7a35tcpg236-1.yaml)
|
||||
* [`41c360b1e2f7e08b9051f1160a34954ce4c05a445a07f226f1f4059caf1fa1d3 ./artix7/xc7a50tfgg484-1.yaml`](./artix7/xc7a50tfgg484-1.yaml)
|
||||
|
||||
|
|
@ -276,7 +277,7 @@ Results have checksums;
|
|||
|
||||
### Settings
|
||||
|
||||
Created using following [settings.sh (sha256: 2daf6a69dd6d20df7b1273ff43c5c340abe36f8229d297646865edcfd91eff18)](https://github.com/SymbiFlow/prjxray/blob/6db8bd65748e1a09e3c7a1433dd9e8693d977da0/database/kintex7/settings.sh)
|
||||
Created using following [settings.sh (sha256: 2daf6a69dd6d20df7b1273ff43c5c340abe36f8229d297646865edcfd91eff18)](https://github.com/SymbiFlow/prjxray/blob/bba5c899ddb7917fe5d34675a05abfb9c4db8f51/database/kintex7/settings.sh)
|
||||
```shell
|
||||
export XRAY_DATABASE="kintex7"
|
||||
export XRAY_PART="xc7k70tfbg676-2"
|
||||
|
|
|
|||
|
|
@ -6,6 +6,7 @@ bit 00_06
|
|||
bit 00_07
|
||||
bit 00_09
|
||||
bit 00_10
|
||||
bit 00_100
|
||||
bit 00_101
|
||||
bit 00_102
|
||||
bit 00_103
|
||||
|
|
@ -57,6 +58,7 @@ bit 00_158
|
|||
bit 00_161
|
||||
bit 00_162
|
||||
bit 00_163
|
||||
bit 00_164
|
||||
bit 00_165
|
||||
bit 00_166
|
||||
bit 00_167
|
||||
|
|
@ -109,6 +111,7 @@ bit 00_222
|
|||
bit 00_225
|
||||
bit 00_226
|
||||
bit 00_227
|
||||
bit 00_228
|
||||
bit 00_229
|
||||
bit 00_23
|
||||
bit 00_230
|
||||
|
|
@ -161,6 +164,7 @@ bit 00_289
|
|||
bit 00_29
|
||||
bit 00_290
|
||||
bit 00_291
|
||||
bit 00_292
|
||||
bit 00_293
|
||||
bit 00_294
|
||||
bit 00_295
|
||||
|
|
@ -186,6 +190,7 @@ bit 00_319
|
|||
bit 00_33
|
||||
bit 00_34
|
||||
bit 00_35
|
||||
bit 00_36
|
||||
bit 00_37
|
||||
bit 00_38
|
||||
bit 00_39
|
||||
|
|
|
|||
|
|
@ -6,6 +6,7 @@ bit 00_06
|
|||
bit 00_07
|
||||
bit 00_09
|
||||
bit 00_10
|
||||
bit 00_100
|
||||
bit 00_101
|
||||
bit 00_102
|
||||
bit 00_103
|
||||
|
|
@ -57,6 +58,7 @@ bit 00_158
|
|||
bit 00_161
|
||||
bit 00_162
|
||||
bit 00_163
|
||||
bit 00_164
|
||||
bit 00_165
|
||||
bit 00_166
|
||||
bit 00_167
|
||||
|
|
@ -109,6 +111,7 @@ bit 00_222
|
|||
bit 00_225
|
||||
bit 00_226
|
||||
bit 00_227
|
||||
bit 00_228
|
||||
bit 00_229
|
||||
bit 00_23
|
||||
bit 00_230
|
||||
|
|
@ -161,6 +164,7 @@ bit 00_289
|
|||
bit 00_29
|
||||
bit 00_290
|
||||
bit 00_291
|
||||
bit 00_292
|
||||
bit 00_293
|
||||
bit 00_294
|
||||
bit 00_295
|
||||
|
|
@ -186,6 +190,7 @@ bit 00_319
|
|||
bit 00_33
|
||||
bit 00_34
|
||||
bit 00_35
|
||||
bit 00_36
|
||||
bit 00_37
|
||||
bit 00_38
|
||||
bit 00_39
|
||||
|
|
|
|||
|
|
@ -1,8 +0,0 @@
|
|||
HCLK.HCLK_CK_INOUT_L0.HCLK_CK_BUFHCLK8 always
|
||||
HCLK.HCLK_CK_INOUT_L1.HCLK_CK_BUFHCLK9 always
|
||||
HCLK.HCLK_CK_INOUT_L2.HCLK_CK_BUFHCLK10 always
|
||||
HCLK.HCLK_CK_INOUT_L3.HCLK_CK_BUFHCLK11 always
|
||||
HCLK.HCLK_CK_INOUT_L4.HCLK_CK_BUFRCLK0 always
|
||||
HCLK.HCLK_CK_INOUT_L5.HCLK_CK_BUFRCLK1 always
|
||||
HCLK.HCLK_CK_INOUT_L6.HCLK_CK_BUFRCLK2 always
|
||||
HCLK.HCLK_CK_INOUT_L7.HCLK_CK_BUFRCLK3 always
|
||||
|
|
@ -1,8 +0,0 @@
|
|||
HCLK.HCLK_CK_INOUT_R0.HCLK_CK_BUFHCLK0 always
|
||||
HCLK.HCLK_CK_INOUT_R1.HCLK_CK_BUFHCLK1 always
|
||||
HCLK.HCLK_CK_INOUT_R2.HCLK_CK_BUFHCLK2 always
|
||||
HCLK.HCLK_CK_INOUT_R3.HCLK_CK_BUFHCLK3 always
|
||||
HCLK.HCLK_CK_INOUT_R4.HCLK_CK_BUFHCLK4 always
|
||||
HCLK.HCLK_CK_INOUT_R5.HCLK_CK_BUFHCLK5 always
|
||||
HCLK.HCLK_CK_INOUT_R6.HCLK_CK_BUFHCLK6 always
|
||||
HCLK.HCLK_CK_INOUT_R7.HCLK_CK_BUFHCLK7 always
|
||||
|
|
@ -727,6 +727,7 @@ INT_L.FAN_ALT6.EL1END1 !22_24 16_24 23_24 24_24 25_24
|
|||
INT_L.FAN_ALT6.ER1END1 !23_24 17_24 22_24 24_24 25_24
|
||||
INT_L.FAN_ALT6.FAN_BOUNCE1 !22_24 20_24 23_24 24_24 25_24
|
||||
INT_L.FAN_ALT6.FAN_BOUNCE7 !23_24 20_24 22_24 24_24 25_24
|
||||
INT_L.FAN_ALT6.GFAN0 !22_24 !23_24 !24_24 00_36 21_24 25_24
|
||||
INT_L.FAN_ALT6.GFAN0 !22_24 !23_24 !24_24 21_24 25_24
|
||||
INT_L.FAN_ALT6.LOGIC_OUTS_L1 !23_24 21_24 22_24 24_24 25_24
|
||||
INT_L.FAN_ALT6.LOGIC_OUTS_L13 !22_24 21_24 23_24 24_24 25_24
|
||||
|
|
|
|||
|
|
@ -1,11 +1,15 @@
|
|||
export XRAY_DATABASE="artix7"
|
||||
export XRAY_PART="xc7a50tfgg484-1"
|
||||
export XRAY_ROI="SLICE_X12Y100:SLICE_X27Y149"
|
||||
export XRAY_ROI_FRAMES="0x00020500:0x000208ff"
|
||||
export XRAY_ROI_GRID_X1="29"
|
||||
export XRAY_ROI_FRAMES="0x00000000:0xffffffff"
|
||||
|
||||
# Leave some CLBs to the left to allow easy ROI entering
|
||||
export XRAY_ROI="SLICE_X8Y100:SLICE_X27Y149 RAMB18_X0Y20:RAMB18_X0Y59 RAMB36_X0Y10:RAMB36_X0Y29 DSP48_X0Y59:DSP48_X0Y20"
|
||||
export XRAY_ROI_GRID_X1="18"
|
||||
export XRAY_ROI_GRID_X2="47"
|
||||
export XRAY_ROI_GRID_Y1="0"
|
||||
export XRAY_ROI_GRID_Y2="52"
|
||||
|
||||
export XRAY_PIN_00="E22"
|
||||
export XRAY_PIN_01="D22"
|
||||
export XRAY_PIN_02="E21"
|
||||
|
|
|
|||
|
|
@ -1,39 +1,39 @@
|
|||
{
|
||||
"type": "BSCAN",
|
||||
"site_pins": {
|
||||
"UPDATE": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"RESET": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SEL": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SHIFT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CAPTURE": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"RUNTEST": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DRCK": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TDI": {
|
||||
"TCK": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"RESET": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SHIFT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TMS": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TCK": {
|
||||
"RUNTEST": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SEL": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TDO": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TDI": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CAPTURE": {
|
||||
"direction": "OUT"
|
||||
}
|
||||
},
|
||||
"site_pips": {},
|
||||
"type": "BSCAN"
|
||||
"site_pips": {}
|
||||
}
|
||||
|
|
@ -1,82 +1,82 @@
|
|||
{
|
||||
"type": "BUFGCTRL",
|
||||
"site_pins": {
|
||||
"IGNORE1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CE0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"S0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"I1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"IGNORE0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"I0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CE1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"S1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CE0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"I0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"S0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"I1": {
|
||||
"direction": "IN"
|
||||
}
|
||||
},
|
||||
"site_pips": {
|
||||
"S0INV:S0_B": {
|
||||
"from_pin": "S0_B",
|
||||
"S1INV:S1_B": {
|
||||
"from_pin": "S1_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"CE0INV:CE0_B": {
|
||||
"from_pin": "CE0_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"S1INV:S1": {
|
||||
"from_pin": "S1",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"S0INV:S0": {
|
||||
"from_pin": "S0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"S1INV:S1_B": {
|
||||
"from_pin": "S1_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"CE0INV:CE0": {
|
||||
"from_pin": "CE0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"CE1INV:CE1_B": {
|
||||
"from_pin": "CE1_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"IGNORE1INV:IGNORE1": {
|
||||
"from_pin": "IGNORE1",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"IGNORE1INV:IGNORE1_B": {
|
||||
"from_pin": "IGNORE1_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"IGNORE0INV:IGNORE0": {
|
||||
"from_pin": "IGNORE0",
|
||||
"S0INV:S0_B": {
|
||||
"from_pin": "S0_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"CE1INV:CE1": {
|
||||
"from_pin": "CE1",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"S1INV:S1": {
|
||||
"from_pin": "S1",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"IGNORE0INV:IGNORE0": {
|
||||
"from_pin": "IGNORE0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"IGNORE1INV:IGNORE1_B": {
|
||||
"from_pin": "IGNORE1_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"S0INV:S0": {
|
||||
"from_pin": "S0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"IGNORE0INV:IGNORE0_B": {
|
||||
"from_pin": "IGNORE0_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"IGNORE1INV:IGNORE1": {
|
||||
"from_pin": "IGNORE1",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"CE1INV:CE1_B": {
|
||||
"from_pin": "CE1_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"CE0INV:CE0": {
|
||||
"from_pin": "CE0",
|
||||
"to_pin": "OUT"
|
||||
}
|
||||
},
|
||||
"type": "BUFGCTRL"
|
||||
}
|
||||
}
|
||||
|
|
@ -1,13 +1,14 @@
|
|||
{
|
||||
"type": "BUFHCE",
|
||||
"site_pins": {
|
||||
"O": {
|
||||
"direction": "OUT"
|
||||
"CE": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"I": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CE": {
|
||||
"direction": "IN"
|
||||
"O": {
|
||||
"direction": "OUT"
|
||||
}
|
||||
},
|
||||
"site_pips": {
|
||||
|
|
@ -19,6 +20,5 @@
|
|||
"from_pin": "CE_B",
|
||||
"to_pin": "OUT"
|
||||
}
|
||||
},
|
||||
"type": "BUFHCE"
|
||||
}
|
||||
}
|
||||
|
|
@ -1,12 +1,12 @@
|
|||
{
|
||||
"type": "BUFIO",
|
||||
"site_pins": {
|
||||
"O": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"I": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O": {
|
||||
"direction": "OUT"
|
||||
}
|
||||
},
|
||||
"site_pips": {},
|
||||
"type": "BUFIO"
|
||||
"site_pips": {}
|
||||
}
|
||||
|
|
@ -1,13 +1,14 @@
|
|||
{
|
||||
"type": "BUFMRCE",
|
||||
"site_pins": {
|
||||
"O": {
|
||||
"direction": "OUT"
|
||||
"CE": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"I": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CE": {
|
||||
"direction": "IN"
|
||||
"O": {
|
||||
"direction": "OUT"
|
||||
}
|
||||
},
|
||||
"site_pips": {
|
||||
|
|
@ -19,6 +20,5 @@
|
|||
"from_pin": "CE_B",
|
||||
"to_pin": "OUT"
|
||||
}
|
||||
},
|
||||
"type": "BUFMRCE"
|
||||
}
|
||||
}
|
||||
|
|
@ -1,18 +1,18 @@
|
|||
{
|
||||
"type": "BUFR",
|
||||
"site_pins": {
|
||||
"I": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CLR": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CE": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"I": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O": {
|
||||
"direction": "OUT"
|
||||
}
|
||||
},
|
||||
"site_pips": {},
|
||||
"type": "BUFR"
|
||||
"site_pips": {}
|
||||
}
|
||||
|
|
@ -1,4 +1,5 @@
|
|||
{
|
||||
"type": "CAPTURE",
|
||||
"site_pins": {
|
||||
"CLK": {
|
||||
"direction": "IN"
|
||||
|
|
@ -7,6 +8,5 @@
|
|||
"direction": "IN"
|
||||
}
|
||||
},
|
||||
"site_pips": {},
|
||||
"type": "CAPTURE"
|
||||
"site_pips": {}
|
||||
}
|
||||
|
|
@ -1,4 +1,5 @@
|
|||
{
|
||||
"type": "DCIRESET",
|
||||
"site_pins": {
|
||||
"LOCKED": {
|
||||
"direction": "OUT"
|
||||
|
|
@ -7,6 +8,5 @@
|
|||
"direction": "IN"
|
||||
}
|
||||
},
|
||||
"site_pips": {},
|
||||
"type": "DCIRESET"
|
||||
"site_pips": {}
|
||||
}
|
||||
|
|
@ -1,12 +1,13 @@
|
|||
{
|
||||
"type": "DNA_PORT",
|
||||
"site_pins": {
|
||||
"READ": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CLK": {
|
||||
"DIN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIN": {
|
||||
"CLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SHIFT": {
|
||||
|
|
@ -16,6 +17,5 @@
|
|||
"direction": "OUT"
|
||||
}
|
||||
},
|
||||
"site_pips": {},
|
||||
"type": "DNA_PORT"
|
||||
"site_pips": {}
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,102 +1,102 @@
|
|||
{
|
||||
"type": "EFUSE_USR",
|
||||
"site_pins": {
|
||||
"EFUSEUSR14": {
|
||||
"EFUSEUSR13": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR17": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR11": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR25": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR10": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR23": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR21": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR26": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR30": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR22": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR9": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR18": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR7": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR8": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR27": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR28": {
|
||||
"EFUSEUSR4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR31": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR5": {
|
||||
"EFUSEUSR29": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR20": {
|
||||
"EFUSEUSR30": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR26": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR22": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR11": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR8": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR27": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR15": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR12": {
|
||||
"EFUSEUSR25": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR16": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR29": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR13": {
|
||||
"EFUSEUSR7": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR24": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR18": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR5": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR16": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR12": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR21": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR10": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR14": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR28": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR20": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR23": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR19": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR9": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR6": {
|
||||
"direction": "OUT"
|
||||
}
|
||||
},
|
||||
"site_pips": {},
|
||||
"type": "EFUSE_USR"
|
||||
"site_pips": {}
|
||||
}
|
||||
|
|
@ -1,519 +1,524 @@
|
|||
{
|
||||
"type": "FIFO18E1",
|
||||
"site_pins": {
|
||||
"WRCOUNT10": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"ADDRBWRADDR6": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DO20": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"ADDRBWRADDR10": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIADI11": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DO29": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO21": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"ADDRARDADDR10": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DO22": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"WEBWE5": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIADI7": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"RDCOUNT3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO27": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DIADI3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DO14": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"ADDRARDADDR1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DO19": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DIBDI8": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DO6": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"ALMOSTEMPTY": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"WRCOUNT2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DIBDI5": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ADDRBWRADDR0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"RDERR": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO24": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DIBDI7": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"WRCOUNT7": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"RDCOUNT6": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DIBDI11": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DO12": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DIADI0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DO2": {
|
||||
"WRCOUNT5": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO10": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO23": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"WRCOUNT3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"ADDRARDADDR12": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ADDRBWRADDR2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ADDRBWRADDR3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ALMOSTFULL": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO15": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DOP3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"RDCOUNT10": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DIPBDIP1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"RDCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ADDRARDADDR9": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIADI5": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIBDI0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIBDI14": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"WEA3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIADI14": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"WEA0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIADI1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIADI10": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"RDCOUNT11": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"ADDRBWRADDR8": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"WRCOUNT4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"WRCOUNT0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DIPBDIP0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DOP1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DIADI8": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DO30": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"ADDRARDADDR7": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DO4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"RDCOUNT7": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"ADDRARDADDR4": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ADDRBWRADDR11": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"RSTREGB": {
|
||||
"WEBWE7": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ADDRBWRADDR9": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIBDI4": {
|
||||
"DIBDI3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DO11": {
|
||||
"DIBDI11": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"WEBWE0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIADI14": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ADDRBWRADDR10": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DOP1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"RDCOUNT2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"WEBWE6": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"REGCE": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"REGCLKB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"RDCOUNT5": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"ADDRARDADDR5": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"WEA1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"WRCOUNT1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DIBDI6": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ADDRBWRADDR5": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"RDCOUNT4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"WEBWE3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"RDRCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DO7": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO25": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"RSTRAMB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIADI15": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ADDRBTIEHIGH0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIADI6": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"RDCOUNT0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO18": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"RSTREG": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"RDCOUNT8": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"WRCOUNT11": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"WRCOUNT6": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"REGCEB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DO8": {
|
||||
"DOP3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"ADDRARDADDR11": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ADDRARDADDR8": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"WRERR": {
|
||||
"DO6": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"WEBWE0": {
|
||||
"DIBDI7": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DO13": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DIBDI2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIBDI13": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"WRCOUNT5": {
|
||||
"WRCOUNT1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"WRCOUNT9": {
|
||||
"RDCOUNT0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"RDCOUNT1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO17": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"ADDRARDADDR0": {
|
||||
"RDRCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"WEBWE2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ADDRATIEHIGH0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIBDI15": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ADDRARDADDR6": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DO16": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DIBDI3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DO28": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DIBDI9": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ADDRBWRADDR7": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DO5": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"RST": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DOP0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"WEA2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DO31": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"ADDRBWRADDR12": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ADDRBWRADDR4": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"WEBWE7": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ADDRARDADDR2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"WEBWE1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIBDI1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIADI2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIPADIP1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIBDI10": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ADDRBWRADDR1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIADI13": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DO0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"WRCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"WRCOUNT8": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DIADI4": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ADDRARDADDR3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ADDRARDADDR13": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ADDRBWRADDR13": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"RDEN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"RDCOUNT9": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO9": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DOP2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DIPADIP0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ADDRATIEHIGH1": {
|
||||
"ADDRBWRADDR11": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"FULL": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"WEBWE4": {
|
||||
"DIBDI14": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"WREN": {
|
||||
"ADDRBWRADDR5": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"EMPTY": {
|
||||
"DOP0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"ADDRBWRADDR3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIADI1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"WRCOUNT9": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DIADI12": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"RDCOUNT6": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO7": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO31": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"WEBWE5": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ADDRBWRADDR4": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DO17": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO19": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"WEA0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ADDRBWRADDR8": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIADI11": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ADDRARDADDR1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIPBDIP0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIADI5": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ADDRBWRADDR6": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ADDRBWRADDR12": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"WEA2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DO14": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO26": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"ADDRBTIEHIGH1": {
|
||||
"WEBWE3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ADDRBWRADDR7": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"WEA1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DO30": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO28": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"WRCOUNT7": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DIADI2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ADDRARDADDR3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DO18": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"ADDRBWRADDR1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"WRCOUNT0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"ALMOSTEMPTY": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"RSTRAMB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIBDI5": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIADI6": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"WRCOUNT10": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO9": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"ADDRARDADDR5": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIADI9": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DO4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DIADI3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ALMOSTFULL": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DIPADIP0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIBDI4": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIADI0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIBDI0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"WRCOUNT2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"WRERR": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DIADI13": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ADDRBTIEHIGH1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DO21": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO11": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DIBDI10": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"RDERR": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"ADDRARDADDR6": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DO2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO25": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO10": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"RDCOUNT1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"RDEN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DOP2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"ADDRARDADDR11": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIBDI1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"RDCOUNT9": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO27": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DIADI4": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"WRCOUNT4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"ADDRATIEHIGH0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"WRCOUNT11": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EMPTY": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"RDCOUNT3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DIADI8": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"RDCOUNT10": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DIBDI6": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DO5": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"ADDRBWRADDR2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"RSTREGB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIBDI15": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ADDRARDADDR4": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DO29": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"WRCOUNT3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"WRCOUNT8": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DIBDI8": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"WREN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ADDRBTIEHIGH0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"RDCOUNT4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO15": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"RST": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"RDCOUNT5": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"WEBWE1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DO16": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO8": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"ADDRARDADDR12": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"RDCOUNT11": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO22": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO24": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"ADDRARDADDR0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DO20": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"ADDRARDADDR7": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ADDRARDADDR9": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIPADIP1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DO3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"ADDRBWRADDR13": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIBDI12": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIPBDIP1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DO1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"WEBWE4": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"REGCLKB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"RSTREG": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ADDRARDADDR10": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"REGCE": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIBDI13": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ADDRATIEHIGH1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"WRCOUNT6": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DIBDI9": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"RDCOUNT8": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"WEBWE6": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIBDI2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"RDCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIADI10": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"WRCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ADDRARDADDR13": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DO23": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"WEBWE2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"RDCOUNT7": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"WEA3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ADDRARDADDR8": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ADDRARDADDR2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"RDCOUNT2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DIADI7": {
|
||||
"direction": "IN"
|
||||
}
|
||||
},
|
||||
"site_pips": {
|
||||
"RDRCLKINV:RDRCLK": {
|
||||
"from_pin": "RDRCLK",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"RDENINV:RDEN_B": {
|
||||
"from_pin": "RDEN_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"RSTINV:RST_B": {
|
||||
"from_pin": "RST_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"RDCLKINV:RDCLK": {
|
||||
"from_pin": "RDCLK",
|
||||
"RDCLKINV:RDCLK_B": {
|
||||
"from_pin": "RDCLK_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"WRENINV:WREN_B": {
|
||||
"from_pin": "WREN_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"RDRCLKINV:RDRCLK_B": {
|
||||
"from_pin": "RDRCLK_B",
|
||||
"WRCLKINV:WRCLK": {
|
||||
"from_pin": "WRCLK",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"RDCLKINV:RDCLK": {
|
||||
"from_pin": "RDCLK",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"RDENINV:RDEN": {
|
||||
"from_pin": "RDEN",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"WRCLKINV:WRCLK": {
|
||||
"from_pin": "WRCLK",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"RSTREGINV:RSTREG": {
|
||||
"from_pin": "RSTREG",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"RDCLKINV:RDCLK_B": {
|
||||
"from_pin": "RDCLK_B",
|
||||
"RSTREGINV:RSTREG_B": {
|
||||
"from_pin": "RSTREG_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"RSTINV:RST_B": {
|
||||
"from_pin": "RST_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"RDRCLKINV:RDRCLK": {
|
||||
"from_pin": "RDRCLK",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"RDRCLKINV:RDRCLK_B": {
|
||||
"from_pin": "RDRCLK_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"WRENINV:WREN": {
|
||||
|
|
@ -524,14 +529,9 @@
|
|||
"from_pin": "WRCLK_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"RSTREGINV:RSTREG_B": {
|
||||
"from_pin": "RSTREG_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"RSTINV:RST": {
|
||||
"from_pin": "RST",
|
||||
"to_pin": "OUT"
|
||||
}
|
||||
},
|
||||
"type": "FIFO18E1"
|
||||
}
|
||||
}
|
||||
|
|
@ -1,171 +1,171 @@
|
|||
{
|
||||
"type": "FRAME_ECC",
|
||||
"site_pins": {
|
||||
"FAR24": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNWORD5": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR5": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNWORD3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR8": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNDROME12": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNWORD6": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CRCERROR": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR7": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR20": {
|
||||
"FAR10": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR12": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNDROME7": {
|
||||
"SYNWORD1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR13": {
|
||||
"SYNWORD5": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR24": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR7": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR22": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNDROMEVALID": {
|
||||
"SYNDROME7": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR19": {
|
||||
"FAR17": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR6": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNDROME3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNDROME0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNDROME2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR16": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNBIT1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNDROME8": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNBIT4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNBIT2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNDROME6": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR9": {
|
||||
"FAR0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR23": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"ECCERROR": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNWORD2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR15": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR25": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR14": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNDROME1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR21": {
|
||||
"SYNBIT4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNDROME5": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR10": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNDROME4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNDROME10": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNBIT0": {
|
||||
"FAR8": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"ECCERRORSINGLE": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR3": {
|
||||
"FAR21": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNBIT3": {
|
||||
"SYNDROME3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNDROME11": {
|
||||
"SYNDROME4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNWORD4": {
|
||||
"SYNDROME8": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNWORD0": {
|
||||
"SYNDROME2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNWORD2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNDROME1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNDROME9": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNWORD1": {
|
||||
"SYNBIT2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR18": {
|
||||
"FAR15": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNWORD4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR13": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR14": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNDROME11": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNDROME0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNBIT0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNDROME6": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNWORD6": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNWORD3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"ECCERROR": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR11": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNWORD0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR17": {
|
||||
"FAR5": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNBIT3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR9": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR19": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR16": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNDROMEVALID": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR20": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNDROME12": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CRCERROR": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNDROME10": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR18": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNBIT1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR25": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR6": {
|
||||
"direction": "OUT"
|
||||
}
|
||||
},
|
||||
"site_pips": {},
|
||||
"type": "FRAME_ECC"
|
||||
"site_pips": {}
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -1,33 +1,33 @@
|
|||
{
|
||||
"type": "IBUFDS_GTE2",
|
||||
"site_pins": {
|
||||
"O": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CLKTESTSIG": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"IB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CEB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ODIV2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CEB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"I": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CLKTESTSIG": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O": {
|
||||
"direction": "OUT"
|
||||
}
|
||||
},
|
||||
"site_pips": {
|
||||
"CLKTESTSIGINV:CLKTESTSIG": {
|
||||
"from_pin": "CLKTESTSIG",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"CLKTESTSIGINV:CLKTESTSIG_B": {
|
||||
"from_pin": "CLKTESTSIG_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"CLKTESTSIGINV:CLKTESTSIG": {
|
||||
"from_pin": "CLKTESTSIG",
|
||||
"to_pin": "OUT"
|
||||
}
|
||||
},
|
||||
"type": "IBUFDS_GTE2"
|
||||
}
|
||||
}
|
||||
|
|
@ -1,207 +1,207 @@
|
|||
{
|
||||
"type": "ICAP",
|
||||
"site_pins": {
|
||||
"O8": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"O2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"O24": {
|
||||
"O11": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"I22": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O16": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"I20": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O25": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"O26": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"O5": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"O3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"I15": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"I17": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O31": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"I10": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O18": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"O12": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"I19": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"I12": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"I28": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"I14": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O30": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"RDWRB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"I29": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"I0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"I18": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"I21": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O14": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"O11": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"O17": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"I8": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"I31": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"I1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"I11": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"I3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O23": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"O27": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"I30": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"I26": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CSIB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"I23": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O9": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"O13": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"I5": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O6": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"O28": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"O22": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"O10": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"O21": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"O20": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"I24": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O7": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"I9": {
|
||||
"I21": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"I13": {
|
||||
"I20": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O28": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"O25": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"I17": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"I3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O12": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"I1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CSIB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"I12": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O8": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"I19": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O24": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"I31": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"I11": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O9": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"I28": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O13": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O20": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"I4": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"O10": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"I10": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"I7": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"I27": {
|
||||
"I16": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"I9": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O27": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"I13": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O17": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"I25": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"I29": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"I8": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O29": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"O4": {
|
||||
"O26": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"I2": {
|
||||
"I23": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O21": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"RDWRB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"I18": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O5": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"I5": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"I27": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"I0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O7": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"O15": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"I30": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"I16": {
|
||||
"I15": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"I4": {
|
||||
"direction": "IN"
|
||||
"O14": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"O15": {
|
||||
"O30": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"I6": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"I26": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O16": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"O22": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"I2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O31": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"O3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"O6": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"O19": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"I14": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O18": {
|
||||
"direction": "OUT"
|
||||
}
|
||||
},
|
||||
"site_pips": {},
|
||||
"type": "ICAP"
|
||||
"site_pips": {}
|
||||
}
|
||||
|
|
@ -1,15 +1,13 @@
|
|||
{
|
||||
"type": "IDELAYCTRL",
|
||||
"site_pins": {
|
||||
"OUTN65": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"OUTN1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DNPULSEOUT": {
|
||||
"OUTN65": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"UPPULSEOUT": {
|
||||
"RDY": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"RST": {
|
||||
|
|
@ -18,10 +16,12 @@
|
|||
"REFCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"RDY": {
|
||||
"UPPULSEOUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DNPULSEOUT": {
|
||||
"direction": "OUT"
|
||||
}
|
||||
},
|
||||
"site_pips": {},
|
||||
"type": "IDELAYCTRL"
|
||||
"site_pips": {}
|
||||
}
|
||||
|
|
@ -1,100 +1,100 @@
|
|||
{
|
||||
"type": "IDELAYE2",
|
||||
"site_pins": {
|
||||
"CNTVALUEOUT4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"INC": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"REGRST": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CNTVALUEIN3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"IDATAIN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CNTVALUEIN0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CNTVALUEOUT1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"IFDLY1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"IFDLY2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"LD": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DATAOUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CNTVALUEIN2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"C": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CNTVALUEOUT3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CNTVALUEOUT2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"IFDLY0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CNTVALUEIN1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"LDPIPEEN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CNTVALUEOUT0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATAIN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CINVCTRL": {
|
||||
"IDATAIN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CNTVALUEIN3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CNTVALUEIN0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"INC": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CNTVALUEOUT4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CNTVALUEOUT2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"C": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CE": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CNTVALUEOUT0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CNTVALUEIN1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CNTVALUEIN4": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CNTVALUEOUT3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CINVCTRL": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"LDPIPEEN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CNTVALUEOUT1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"IFDLY2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"IFDLY1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"LD": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CNTVALUEIN2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"REGRST": {
|
||||
"direction": "IN"
|
||||
}
|
||||
},
|
||||
"site_pips": {
|
||||
"CINV:C_B": {
|
||||
"from_pin": "C_B",
|
||||
"IDATAININV:IDATAIN_B": {
|
||||
"from_pin": "IDATAIN_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"DATAININV:DATAIN": {
|
||||
"from_pin": "DATAIN",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"CINV:C": {
|
||||
"from_pin": "C",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"IDATAININV:IDATAIN_B": {
|
||||
"from_pin": "IDATAIN_B",
|
||||
"CINV:C_B": {
|
||||
"from_pin": "C_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"IDATAININV:IDATAIN": {
|
||||
"from_pin": "IDATAIN",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"CINV:C": {
|
||||
"from_pin": "C",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"DATAININV:DATAIN_B": {
|
||||
"from_pin": "DATAIN_B",
|
||||
"to_pin": "OUT"
|
||||
}
|
||||
},
|
||||
"type": "IDELAYE2"
|
||||
}
|
||||
}
|
||||
|
|
@ -1,27 +1,10 @@
|
|||
{
|
||||
"type": "ILOGICE3",
|
||||
"site_pins": {
|
||||
"SHIFTOUT2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SHIFTIN1": {
|
||||
"TFB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q6": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q7": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"OCLKB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SR": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DDLY": {
|
||||
"DYNCLKDIVSEL": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CE2": {
|
||||
|
|
@ -30,105 +13,171 @@
|
|||
"OFB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CE1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CLKB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"BITSLIP": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q8": {
|
||||
"direction": "OUT"
|
||||
"SHIFTIN1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"OCLK": {
|
||||
"CE1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TFB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DYNCLKDIVPSEL": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O": {
|
||||
"Q6": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DYNCLKDIVSEL": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CLKDIV": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"REV": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SHIFTOUT1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CLKDIVP": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DYNCLKSEL": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q5": {
|
||||
"direction": "OUT"
|
||||
"OCLKB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SHIFTIN2": {
|
||||
"CLKB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"OCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SR": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SHIFTOUT1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q8": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"O": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q5": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SHIFTOUT2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DDLY": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q7": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CLKDIVP": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SHIFTIN2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DYNCLKDIVPSEL": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"REV": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CLKDIV": {
|
||||
"direction": "IN"
|
||||
}
|
||||
},
|
||||
"site_pips": {
|
||||
"IFFDELMUXE3:2": {
|
||||
"IDELMUXE3:2": {
|
||||
"from_pin": "2",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"SRUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"CE1USED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"IDELMUXE3:1": {
|
||||
"from_pin": "1",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"ZHOLD_FABRIC_INV:D": {
|
||||
"from_pin": "D",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"D2OBYP_SEL:T": {
|
||||
"from_pin": "T",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"CLKBINV:CLKB": {
|
||||
"from_pin": "CLKB",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"IMUX:1": {
|
||||
"from_pin": "1",
|
||||
"D2OFFBYP_SEL:T": {
|
||||
"from_pin": "T",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"REVUSED:0": {
|
||||
"from_pin": "0",
|
||||
"CLKBINV:CLKB_B": {
|
||||
"from_pin": "CLKB_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"CLKINV:CLK_B": {
|
||||
"from_pin": "CLK_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"ZHOLD_IFF_INV:D_B": {
|
||||
"from_pin": "D_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"DINV:D": {
|
||||
"from_pin": "D",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"DINV:D_B": {
|
||||
"from_pin": "D_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"D2OBYP_SEL:GND": {
|
||||
"from_pin": "GND",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"REVUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"IFFDELMUXE3:1": {
|
||||
"from_pin": "1",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"IMUX:1": {
|
||||
"from_pin": "1",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"D2OFFBYP_SEL:GND": {
|
||||
"from_pin": "GND",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"IFFMUX:1": {
|
||||
"from_pin": "1",
|
||||
"ZHOLD_FABRIC_INV:D_B": {
|
||||
"from_pin": "D_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"ZHOLD_IFF_INV:D_B": {
|
||||
"from_pin": "D_B",
|
||||
"IFFDELMUXE3:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"IFFMUX:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"CLKINV:CLK": {
|
||||
|
|
@ -139,70 +188,21 @@
|
|||
"from_pin": "D",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"CLKINV:CLK_B": {
|
||||
"from_pin": "CLK_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"IDELMUXE3:2": {
|
||||
"from_pin": "2",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"ZHOLD_FABRIC_INV:D_B": {
|
||||
"from_pin": "D_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"SRUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"IDELMUXE3:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"DINV:D": {
|
||||
"from_pin": "D",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"ZHOLD_FABRIC_INV:D": {
|
||||
"from_pin": "D",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"IFFMUX:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"CLKBINV:CLKB_B": {
|
||||
"from_pin": "CLKB_B",
|
||||
"IFFMUX:1": {
|
||||
"from_pin": "1",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"IMUX:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"CE1USED:0": {
|
||||
"IFFDELMUXE3:2": {
|
||||
"from_pin": "2",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"IDELMUXE3:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"IFFDELMUXE3:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"IFFDELMUXE3:1": {
|
||||
"from_pin": "1",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"DINV:D_B": {
|
||||
"from_pin": "D_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"D2OBYP_SEL:T": {
|
||||
"from_pin": "T",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"D2OFFBYP_SEL:T": {
|
||||
"from_pin": "T",
|
||||
"to_pin": "OUT"
|
||||
}
|
||||
},
|
||||
"type": "ILOGICE3"
|
||||
}
|
||||
}
|
||||
|
|
@ -1,453 +1,453 @@
|
|||
{
|
||||
"type": "IN_FIFO",
|
||||
"site_pins": {
|
||||
"TESTMODEB": {
|
||||
"D81": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q71": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q46": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q93": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q97": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D52": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D51": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D57": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ALMOSTFULL": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q15": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D43": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q56": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D32": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q87": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q73": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q23": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q30": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D53": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q51": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q57": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q01": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q77": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D30": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q35": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q82": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q26": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q75": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q24": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q04": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q40": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D65": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q43": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q14": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q96": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D10": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q81": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTREADDISB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q06": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTWRITEDISB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"RDCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q63": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q60": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D42": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q64": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q07": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D56": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D90": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q47": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q91": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q55": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SCANIN2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q17": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q11": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q61": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D64": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q33": {
|
||||
"Q30": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D91": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q92": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D66": {
|
||||
"D51": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q21": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D11": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q74": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q83": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q95": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D54": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"RDEN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SCANOUT2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q67": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q90": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q62": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D60": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D93": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D13": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q45": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q12": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D03": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q36": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q27": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q41": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D23": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q34": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q13": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q54": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SCANENB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q52": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q32": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SCANIN0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SCANIN3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D72": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D20": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D73": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D82": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D21": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SCANOUT0": {
|
||||
"Q43": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q31": {
|
||||
"Q04": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q22": {
|
||||
"Q36": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D01": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"EMPTY": {
|
||||
"Q71": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D92": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D61": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q84": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q05": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SCANOUT3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D40": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ALMOSTEMPTY": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q85": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D80": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q42": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D41": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D00": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q53": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q50": {
|
||||
"Q75": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q94": {
|
||||
"Q47": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D02": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q37": {
|
||||
"SCANOUT0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SCANIN1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q25": {
|
||||
"Q42": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D67": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D33": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q66": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D70": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D55": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D12": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q80": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q20": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SCANOUT1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"WREN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q03": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q16": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D83": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q86": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"WRCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D22": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q10": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D50": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D71": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q02": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q70": {
|
||||
"Q17": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D63": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D81": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q44": {
|
||||
"Q84": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q76": {
|
||||
"Q97": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D31": {
|
||||
"D53": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"FULL": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q00": {
|
||||
"Q83": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q26": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q94": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D63": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D30": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q23": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q91": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q22": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q96": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q44": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"RDCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q76": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D32": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q14": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D67": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D82": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D31": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q56": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q62": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SCANIN1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SCANENB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q64": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTWRITEDISB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q93": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q81": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"RDEN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D93": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q33": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q60": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q45": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D62": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q31": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q11": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D02": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D42": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q65": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D66": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D11": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ALMOSTFULL": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D73": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q73": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q12": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q13": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q41": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q35": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D01": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D22": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q32": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q16": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q85": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q03": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q63": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTMODEB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q10": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D70": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q57": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q77": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q74": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q25": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D43": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"RESET": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SCANOUT1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SCANOUT3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q66": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D61": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"WRCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D71": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q07": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q86": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EMPTY": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q55": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D52": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q20": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D92": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q80": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q54": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q27": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q61": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q34": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q72": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q65": {
|
||||
"Q70": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"WREN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D54": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q15": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SCANIN2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D80": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ALMOSTEMPTY": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q00": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D13": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q90": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q67": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SCANIN3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D12": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D56": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q24": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D65": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q21": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D10": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SCANOUT2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q06": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q51": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q40": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D83": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q87": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D00": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D33": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q52": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D57": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D23": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D21": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q82": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D90": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D20": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D64": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q50": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D50": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D40": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q05": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q37": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SCANIN0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D41": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D60": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q01": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D55": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q46": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q95": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q92": {
|
||||
"direction": "OUT"
|
||||
}
|
||||
},
|
||||
"site_pips": {},
|
||||
"type": "IN_FIFO"
|
||||
"site_pips": {}
|
||||
}
|
||||
|
|
@ -1,12 +1,46 @@
|
|||
{
|
||||
"type": "IOB33",
|
||||
"site_pins": {
|
||||
"PADOUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"INTERMDISABLE": {
|
||||
"O": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"KEEPER_INT_EN": {
|
||||
"O_IN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"T_OUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"O_OUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"I": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DIFFI_IN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PU_INT_EN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"T_IN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIFFO_IN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PD_INT_EN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"IBUFDISABLE": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"T": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"INTERMDISABLE": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIFF_TERM_INT_EN": {
|
||||
|
|
@ -15,57 +49,16 @@
|
|||
"DIFFO_OUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"I": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"T_IN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O_IN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O_OUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DIFFO_IN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PD_INT_EN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"T_OUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DIFFI_IN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"IBUFDISABLE": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PU_INT_EN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"T": {
|
||||
"KEEPER_INT_EN": {
|
||||
"direction": "IN"
|
||||
}
|
||||
},
|
||||
"site_pips": {
|
||||
"INTERMDISABLE_SEL:I": {
|
||||
"from_pin": "I",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"IUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"TUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"PADOUTUSED:0": {
|
||||
"DIFFI_INUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
|
|
@ -73,22 +66,29 @@
|
|||
"from_pin": "I",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"TUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"INTERMDISABLE_SEL:I": {
|
||||
"from_pin": "I",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"IBUFDISABLE_SEL:GND": {
|
||||
"from_pin": "GND",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"DIFFI_INUSED:0": {
|
||||
"INTERMDISABLE_SEL:GND": {
|
||||
"from_pin": "GND",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"PADOUTUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"OUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"INTERMDISABLE_SEL:GND": {
|
||||
"from_pin": "GND",
|
||||
"to_pin": "OUT"
|
||||
}
|
||||
},
|
||||
"type": "IOB33"
|
||||
}
|
||||
}
|
||||
|
|
@ -1,8 +1,42 @@
|
|||
{
|
||||
"type": "IOB33M",
|
||||
"site_pins": {
|
||||
"PADOUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"O_IN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"T_OUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"I": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"O_OUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DIFFI_IN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIFFO_OUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"T_IN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIFFO_IN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PD_INT_EN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"IBUFDISABLE": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"T": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"INTERMDISABLE": {
|
||||
"direction": "IN"
|
||||
},
|
||||
|
|
@ -12,56 +46,19 @@
|
|||
"DIFF_TERM_INT_EN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIFFO_OUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"I": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"T_IN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O_IN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O_OUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DIFFO_IN": {
|
||||
"PU_INT_EN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PD_INT_EN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"T_OUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DIFFI_IN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"IBUFDISABLE": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PU_INT_EN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"T": {
|
||||
"direction": "IN"
|
||||
}
|
||||
},
|
||||
"site_pips": {
|
||||
"DIFFO_OUTUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"IUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"PADOUTUSED:0": {
|
||||
"DIFFI_INUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
|
|
@ -69,27 +66,15 @@
|
|||
"from_pin": "I",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"INTERMDISABLE_SEL:GND": {
|
||||
"from_pin": "GND",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"IBUFDISABLE_SEL:GND": {
|
||||
"from_pin": "GND",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"TUSED:0": {
|
||||
"PADOUTUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"INTERMDISABLE_SEL:I": {
|
||||
"from_pin": "I",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"O_OUTUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"DIFFI_INUSED:0": {
|
||||
"TUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
|
|
@ -100,7 +85,22 @@
|
|||
"T_OUTUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"IBUFDISABLE_SEL:GND": {
|
||||
"from_pin": "GND",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"INTERMDISABLE_SEL:GND": {
|
||||
"from_pin": "GND",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"DIFFO_OUTUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"INTERMDISABLE_SEL:I": {
|
||||
"from_pin": "I",
|
||||
"to_pin": "OUT"
|
||||
}
|
||||
},
|
||||
"type": "IOB33M"
|
||||
}
|
||||
}
|
||||
|
|
@ -1,8 +1,42 @@
|
|||
{
|
||||
"type": "IOB33S",
|
||||
"site_pins": {
|
||||
"PADOUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"O_IN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"T_OUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"I": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"O_OUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DIFFI_IN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIFFO_OUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"T_IN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIFFO_IN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PD_INT_EN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"IBUFDISABLE": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"T": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"INTERMDISABLE": {
|
||||
"direction": "IN"
|
||||
},
|
||||
|
|
@ -12,87 +46,14 @@
|
|||
"DIFF_TERM_INT_EN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIFFO_OUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"I": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"T_IN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O_IN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O_OUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DIFFO_IN": {
|
||||
"PU_INT_EN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PD_INT_EN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"T_OUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DIFFI_IN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"IBUFDISABLE": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PU_INT_EN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"T": {
|
||||
"direction": "IN"
|
||||
}
|
||||
},
|
||||
"site_pips": {
|
||||
"OUTMUX:1": {
|
||||
"from_pin": "1",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"TINMUX:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"TINMUX:1": {
|
||||
"from_pin": "1",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"PADOUTUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"IBUFDISABLE_SEL:I": {
|
||||
"from_pin": "I",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"INTERMDISABLE_SEL:GND": {
|
||||
"from_pin": "GND",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"INTERMDISABLE_SEL:I": {
|
||||
"from_pin": "I",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"IBUFDISABLE_SEL:GND": {
|
||||
"from_pin": "GND",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"OUTMUX:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"OINMUX:1": {
|
||||
"from_pin": "1",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"IUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
|
|
@ -101,14 +62,53 @@
|
|||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"OINMUX:0": {
|
||||
"IBUFDISABLE_SEL:I": {
|
||||
"from_pin": "I",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"TINMUX:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"DIFFO_INUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"TINMUX:1": {
|
||||
"from_pin": "1",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"OUTMUX:1": {
|
||||
"from_pin": "1",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"OINMUX:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"OINMUX:1": {
|
||||
"from_pin": "1",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"IBUFDISABLE_SEL:GND": {
|
||||
"from_pin": "GND",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"INTERMDISABLE_SEL:GND": {
|
||||
"from_pin": "GND",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"PADOUTUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"INTERMDISABLE_SEL:I": {
|
||||
"from_pin": "I",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"OUTMUX:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
}
|
||||
},
|
||||
"type": "IOB33S"
|
||||
}
|
||||
}
|
||||
|
|
@ -1,9 +1,9 @@
|
|||
{
|
||||
"type": "IPAD",
|
||||
"site_pins": {
|
||||
"O": {
|
||||
"direction": "OUT"
|
||||
}
|
||||
},
|
||||
"site_pips": {},
|
||||
"type": "IPAD"
|
||||
"site_pips": {}
|
||||
}
|
||||
|
|
@ -1,529 +1,510 @@
|
|||
{
|
||||
"type": "MMCME2_ADV",
|
||||
"site_pins": {
|
||||
"TESTIN4": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN23": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DO6": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN14": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT38": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DO3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CLKOUT1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DI15": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN24": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN7": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DI6": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT55": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO10": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN28": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DI7": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT12": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CLKFBOUTB": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DADDR4": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT37": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT6": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DADDR2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT54": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CLKOUT3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN8": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT62": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT28": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CLKFBOUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN27": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT27": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT14": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DI9": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DI11": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DADDR0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DI12": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT57": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DI13": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN29": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DI14": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DO15": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DI4": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT48": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DI1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DADDR6": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN15": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT22": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN22": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CLKINSTOPPED": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT21": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TMUXOUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT43": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN9": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DO1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT25": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT17": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN26": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN20": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT32": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DRDY": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN17": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT5": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT13": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CLKOUT5": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CLKOUT3B": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT15": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PWRDWN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DO4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DADDR3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PSEN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT49": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT44": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN12": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DO11": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN16": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DEN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DI10": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DO14": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DWE": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT19": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT60": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT23": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT39": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CLKOUT0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT20": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT18": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PSDONE": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO12": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DI2": {
|
||||
"DADDR0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DO7": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN6": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN30": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN31": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT46": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CLKOUT2B": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN19": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT16": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT45": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CLKOUT1B": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CLKOUT4": {
|
||||
"CLKOUT0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CLKOUT6": {
|
||||
"TESTOUT15": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN11": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT51": {
|
||||
"TESTOUT13": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT33": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT36": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN21": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DADDR5": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DO8": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CLKINSEL": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN13": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PSINCDEC": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CLKIN1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DO13": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN5": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT34": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT50": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN10": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CLKOUT0B": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT7": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT11": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT9": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT10": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT59": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT56": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT63": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO5": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DI5": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"RST": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT31": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO9": {
|
||||
"TESTOUT49": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CLKIN2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN1": {
|
||||
"CLKOUT1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT10": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TMUXOUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT14": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT27": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT50": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT12": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO11": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT62": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DI6": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT58": {
|
||||
"PSDONE": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN5": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CLKOUT0B": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN31": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO6": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN18": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT61": {
|
||||
"TESTOUT52": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT29": {
|
||||
"TESTOUT17": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT30": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DI3": {
|
||||
"TESTIN2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"LOCKED": {
|
||||
"TESTOUT37": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT24": {
|
||||
"TESTOUT38": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CLKFBSTOPPED": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT8": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DI0": {
|
||||
"TESTIN6": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PSCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DO7": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN22": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DI13": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DADDR6": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DWE": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CLKOUT4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT40": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DI5": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN29": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PSINCDEC": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DI10": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT48": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DO14": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT23": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CLKOUT5": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CLKOUT3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CLKIN1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CLKFBOUTB": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT41": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DI11": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DO13": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DI9": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN17": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DADDR2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN12": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DI14": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT8": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT35": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DI8": {
|
||||
"TESTIN8": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT53": {
|
||||
"DO9": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DADDR1": {
|
||||
"direction": "IN"
|
||||
"TESTOUT57": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CLKOUT2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT16": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CLKOUT2B": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DI12": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CLKOUT6": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT34": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT18": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT43": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT56": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PSEN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT55": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CLKFBSTOPPED": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DI2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DO2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN23": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT22": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CLKFBIN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT26": {
|
||||
"TESTIN7": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT19": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN3": {
|
||||
"TESTIN15": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT46": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DI15": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DADDR4": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DO10": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT28": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT20": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT45": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CLKINSEL": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DADDR1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DI4": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT47": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT29": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT42": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT47": {
|
||||
"TESTOUT31": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN28": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DO5": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN25": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT41": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT52": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PSCLK": {
|
||||
"PWRDWN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT58": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT39": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DI1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT21": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT30": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN26": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DI7": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CLKINSTOPPED": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO15": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"RST": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN24": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN16": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DI0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT33": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO8": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DEN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT9": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN27": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN14": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"LOCKED": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT11": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DI8": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DADDR3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN9": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT6": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT63": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN11": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT7": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT54": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN30": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN21": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CLKOUT3B": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT32": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT36": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN13": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT24": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT51": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN10": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DADDR5": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN19": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT59": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN20": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT53": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CLKFBOUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT60": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DI3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT25": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DRDY": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT44": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT61": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN4": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT26": {
|
||||
"direction": "OUT"
|
||||
}
|
||||
},
|
||||
"site_pips": {
|
||||
"CLKINSELINV:CLKINSEL": {
|
||||
"from_pin": "CLKINSEL",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"PSINCDECINV:PSINCDEC_B": {
|
||||
"from_pin": "PSINCDEC_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"RSTINV:RST_B": {
|
||||
"from_pin": "RST_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"PWRDWNINV:PWRDWN_B": {
|
||||
"from_pin": "PWRDWN_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"PWRDWNINV:PWRDWN": {
|
||||
"from_pin": "PWRDWN",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"PSENINV:PSEN_B": {
|
||||
"from_pin": "PSEN_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"CLKINSELINV:CLKINSEL_B": {
|
||||
"from_pin": "CLKINSEL_B",
|
||||
"to_pin": "OUT"
|
||||
|
|
@ -532,14 +513,33 @@
|
|||
"from_pin": "PSEN",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"PSINCDECINV:PSINCDEC_B": {
|
||||
"from_pin": "PSINCDEC_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"PSINCDECINV:PSINCDEC": {
|
||||
"from_pin": "PSINCDEC",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"CLKINSELINV:CLKINSEL": {
|
||||
"from_pin": "CLKINSEL",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"PSENINV:PSEN_B": {
|
||||
"from_pin": "PSEN_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"RSTINV:RST": {
|
||||
"from_pin": "RST",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"PWRDWNINV:PWRDWN": {
|
||||
"from_pin": "PWRDWN",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"RSTINV:RST_B": {
|
||||
"from_pin": "RST_B",
|
||||
"to_pin": "OUT"
|
||||
}
|
||||
},
|
||||
"type": "MMCME2_ADV"
|
||||
}
|
||||
}
|
||||
|
|
@ -1,198 +1,107 @@
|
|||
{
|
||||
"type": "OLOGICE3",
|
||||
"site_pins": {
|
||||
"OCE": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CLKDIVF": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TQ": {
|
||||
"TFB": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"T1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D7": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"OFB": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CLKDIVB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SHIFTIN1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D6": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"T3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CLKDIVFB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"T2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TBYTEOUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CLKDIV": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SR": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D5": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"OFB": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CLKDIVFB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CLKB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"T4": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TFB": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D4": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"T1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D6": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"OQ": {
|
||||
"TQ": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CLKDIVB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"REV": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SHIFTOUT2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TBYTEIN": {
|
||||
"SR": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SHIFTOUT1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"IOCLKGLITCH": {
|
||||
"OQ": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D5": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SHIFTOUT2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D8": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"T3": {
|
||||
"D4": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TCE": {
|
||||
"CLKB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"IOCLKGLITCH": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"REV": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TBYTEIN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SHIFTIN2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D7": {
|
||||
"D2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"OCE": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CLKDIVF": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TCE": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"T4": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CLKDIV": {
|
||||
"direction": "IN"
|
||||
}
|
||||
},
|
||||
"site_pips": {
|
||||
"T2INV:T2_B": {
|
||||
"from_pin": "T2_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"T1USED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"TQUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"D2INV:D2": {
|
||||
"from_pin": "D2",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"T1INV:T1_B": {
|
||||
"from_pin": "T1_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"OMUX:OUTFF": {
|
||||
"from_pin": "OUTFF",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"OMUX:D1": {
|
||||
"from_pin": "D1",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"D1INV:D1_B": {
|
||||
"from_pin": "D1_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"OCEUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"T2INV:T2": {
|
||||
"from_pin": "T2",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"CLKINV:CLK": {
|
||||
"from_pin": "CLK",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"OREVUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"TMUX:TFF": {
|
||||
"from_pin": "TFF",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"CLKINV:CLK_B": {
|
||||
"from_pin": "CLK_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"D2INV:D2_B": {
|
||||
"from_pin": "D2_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"TSRUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"TREVUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"TCEUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"OQUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"TFBUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"O1USED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"T1INV:T1": {
|
||||
"from_pin": "T1",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"D1INV:D1": {
|
||||
"from_pin": "D1",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"TMUX:T1": {
|
||||
"from_pin": "T1",
|
||||
"to_pin": "OUT"
|
||||
|
|
@ -201,10 +110,101 @@
|
|||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"T1INV:T1": {
|
||||
"from_pin": "T1",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"TMUX:TFF": {
|
||||
"from_pin": "TFF",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"T2INV:T2_B": {
|
||||
"from_pin": "T2_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"OCEUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"D1INV:D1": {
|
||||
"from_pin": "D1",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"CLKINV:CLK_B": {
|
||||
"from_pin": "CLK_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"T1INV:T1_B": {
|
||||
"from_pin": "T1_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"T2INV:T2": {
|
||||
"from_pin": "T2",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"OFBUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"O1USED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"TFBUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"OREVUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"D2INV:D2_B": {
|
||||
"from_pin": "D2_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"TCEUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"OMUX:D1": {
|
||||
"from_pin": "D1",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"D2INV:D2": {
|
||||
"from_pin": "D2",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"T1USED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"D1INV:D1_B": {
|
||||
"from_pin": "D1_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"TREVUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"CLKINV:CLK": {
|
||||
"from_pin": "CLK",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"TQUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"TSRUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"OQUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"OMUX:OUTFF": {
|
||||
"from_pin": "OUTFF",
|
||||
"to_pin": "OUT"
|
||||
}
|
||||
},
|
||||
"type": "OLOGICE3"
|
||||
}
|
||||
}
|
||||
|
|
@ -1,9 +1,9 @@
|
|||
{
|
||||
"type": "OPAD",
|
||||
"site_pins": {
|
||||
"I": {
|
||||
"direction": "IN"
|
||||
}
|
||||
},
|
||||
"site_pips": {},
|
||||
"type": "OPAD"
|
||||
"site_pips": {}
|
||||
}
|
||||
|
|
@ -1,453 +1,453 @@
|
|||
{
|
||||
"type": "OUT_FIFO",
|
||||
"site_pins": {
|
||||
"D47": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D24": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D15": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D97": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D35": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D51": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D96": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q93": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D17": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q56": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D86": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D05": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D32": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q73": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q23": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q30": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D07": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D53": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D37": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D83": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q01": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTMODEB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D30": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D52": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q82": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D25": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q33": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D65": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q43": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D46": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D66": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D54": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D10": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q81": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D36": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q65": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SCANOUT1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D06": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"RDCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q63": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q60": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q80": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D42": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q64": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SCANOUT3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D56": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D90": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q91": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q55": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SCANIN2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q02": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D74": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q61": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D64": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D43": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D91": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q92": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D45": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q21": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D11": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D84": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q83": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q72": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTWRITEDISB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q70": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SCANOUT2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D87": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q67": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q90": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q62": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D60": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D93": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D13": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q12": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D03": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"WRCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D34": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q41": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D23": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q13": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q54": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D44": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SCANENB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q52": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q40": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D27": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SCANIN0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SCANIN3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D72": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D20": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D73": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D82": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D21": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SCANOUT0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q31": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q22": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D01": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"EMPTY": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D14": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D61": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D04": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D16": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D40": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ALMOSTEMPTY": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D85": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D77": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ALMOSTFULL": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D80": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D94": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q42": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D41": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D76": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D00": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q53": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q50": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SCANIN1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D63": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D02": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D92": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D67": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D33": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q66": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D70": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D55": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D12": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q51": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q20": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"WREN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q03": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q71": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D57": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q57": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D22": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q32": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D50": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D71": {
|
||||
"D81": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTREADDISB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"RDEN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D81": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D31": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"FULL": {
|
||||
"Q30": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q00": {
|
||||
"D91": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D51": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q63": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D62": {
|
||||
"D03": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"RESET": {
|
||||
"D72": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D95": {
|
||||
"Q43": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D87": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D75": {
|
||||
"Q71": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q53": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D97": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SCANOUT0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q42": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q02": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D16": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D26": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q10": {
|
||||
"D74": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D53": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D46": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q03": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q83": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D96": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D63": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D30": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q23": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q91": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q22": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D47": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D45": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D32": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D36": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D67": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D82": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D31": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q56": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q62": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SCANIN1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SCANENB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D83": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D37": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTWRITEDISB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q40": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D35": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q81": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q57": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D93": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q33": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q60": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D62": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q31": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q11": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D42": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q65": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D04": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D76": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D11": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D27": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ALMOSTFULL": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D73": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q73": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D66": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q13": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q41": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D75": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D01": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D22": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"RDCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q64": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D34": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTMODEB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q10": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D70": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"RDEN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D24": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D43": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"RESET": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SCANOUT1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SCANOUT3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q66": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SCANIN3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D61": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SCANIN0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D71": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"FULL": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q12": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EMPTY": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D05": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D52": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q20": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D15": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D92": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q80": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q61": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D95": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D25": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q72": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q70": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"WREN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D54": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D07": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SCANIN2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D94": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D80": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ALMOSTEMPTY": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q00": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D13": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q90": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q67": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D84": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D12": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D56": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q54": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q21": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D65": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D44": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D10": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D06": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q32": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q51": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q52": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D02": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D00": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D33": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D57": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D23": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D21": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D85": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q82": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D77": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SCANOUT2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D20": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D64": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q50": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D86": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D50": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D90": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D14": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D40": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D17": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q93": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"WRCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D41": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D60": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q01": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D55": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q55": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q92": {
|
||||
"direction": "OUT"
|
||||
}
|
||||
},
|
||||
"site_pips": {},
|
||||
"type": "OUT_FIFO"
|
||||
"site_pips": {}
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,291 +1,291 @@
|
|||
{
|
||||
"type": "PHASER_IN_PHY",
|
||||
"site_pins": {
|
||||
"TESTIN4": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COUNTERREADVAL2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN9": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"EDGEADV": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COUNTERLOADVAL4": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"BURSTPENDINGPHY": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COUNTERLOADVAL5": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SYNCIN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"FINEENABLE": {
|
||||
"COUNTERLOADEN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DQSFOUND": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"STG1REGL1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"STG1REGL8": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"STG1INCDEC": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ENCALIBPHY0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"STG1REGL5": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ENSTG1ADJUSTB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COUNTERREADVAL3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FINEOVERFLOW": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"COUNTERLOADVAL0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ICLK": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"STG1REGL6": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHASEREFCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ENCALIBPHY1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DQSOUTOFRANGE": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"STG1REGL2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"MEMREFCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SCANOUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PHASELOCKED": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"STG1REGR3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DIVIDERST": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"ENSTG1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"STG1REGL4": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"STG1REGR6": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"COUNTERLOADEN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN12": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"RANKSEL1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"STG1REGR0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"STG1REGR2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"STG1REGR8": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"COUNTERREADVAL4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"COUNTERLOADVAL3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COUNTERREADEN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SCANCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN6": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"STG1OVERFLOW": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"COUNTERREADVAL0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"STG1REGR1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"RSTDQSFIND": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"RANKSELPHY1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN11": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ICLKDIV": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"BURSTPENDING": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN8": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN13": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SYSCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ENCALIB0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ENCALIB1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"STG1REGR7": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN5": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"STG1REGL0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"COUNTERLOADVAL2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"RANKSEL0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"STG1REGL7": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"RCLK": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"COUNTERLOADVAL1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"RST": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COUNTERREADVAL5": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"COUNTERREADVAL1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"STG1LOAD": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"FINEINC": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN7": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"STG1REGL3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SCANMODEB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"STG1READ": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN10": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SELCALORSTG1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"STG1REGR5": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"WRENABLE": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"ISERDESRST": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SCANENB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SCANIN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"FREQREFCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"RANKSELPHY0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ENCALIBPHY1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN9": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SCANCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"STG1REGL0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"STG1REGL1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN5": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COUNTERLOADVAL1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COUNTERLOADVAL0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COUNTERREADVAL1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"COUNTERLOADVAL3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"STG1REGR4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"COUNTERREADVAL2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN6": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ENSTG1ADJUSTB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"STG1LOAD": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"FREQREFCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHASELOCKED": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FINEINC": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COUNTERLOADVAL4": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"STG1REGR6": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SCANENB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ICLK": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"STG1READ": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"STG1REGL6": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"STG1REGR1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"COUNTERREADEN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIVIDERST": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"COUNTERREADVAL3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN12": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"EDGEADV": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"STG1REGL8": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN8": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"STG1REGR7": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"ISERDESRST": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"COUNTERREADVAL4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"STG1OVERFLOW": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"RSTDQSFIND": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"RANKSEL1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"MEMREFCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COUNTERREADVAL0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"STG1REGL4": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"STG1REGR2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PHASEREFCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SYNCIN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DQSOUTOFRANGE": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FINEOVERFLOW": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN7": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"RCLK": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"STG1REGR5": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FINEENABLE": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"STG1REGL5": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SCANOUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"ENSTG1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SELCALORSTG1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"WRENABLE": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYSCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ENCALIB1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SCANIN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"BURSTPENDINGPHY": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"RST": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"STG1REGL7": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"RANKSEL0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COUNTERLOADVAL2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"STG1REGL3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"RANKSELPHY1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ENCALIBPHY0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"BURSTPENDING": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN11": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COUNTERREADVAL5": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"STG1REGR0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN13": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ENCALIB0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"STG1INCDEC": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN10": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"STG1REGR8": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"STG1REGL2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ICLKDIV": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"STG1REGR3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"COUNTERLOADVAL5": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN4": {
|
||||
"direction": "IN"
|
||||
}
|
||||
},
|
||||
"site_pips": {
|
||||
"RSTINV:RST_B": {
|
||||
"from_pin": "RST_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"RSTINV:RST": {
|
||||
"from_pin": "RST",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"RSTINV:RST_B": {
|
||||
"from_pin": "RST_B",
|
||||
"to_pin": "OUT"
|
||||
}
|
||||
},
|
||||
"type": "PHASER_IN_PHY"
|
||||
}
|
||||
}
|
||||
|
|
@ -1,246 +1,246 @@
|
|||
{
|
||||
"type": "PHASER_OUT_PHY",
|
||||
"site_pins": {
|
||||
"TESTIN4": {
|
||||
"COUNTERLOADEN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN12": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DTSBUS1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ENCALIBPHY1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FINEOVERFLOW": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN7": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SCANCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN15": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SCANMODEB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COARSEOVERFLOW": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"COUNTERREADVAL6": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN5": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SYNCIN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"BURSTPENDINGPHY": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN6": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"FINEENABLE": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COUNTERLOADVAL1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SELFINEOCLKDELAY": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SCANOUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"COUNTERLOADVAL0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COUNTERREADVAL1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CTSBUS1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"COUNTERLOADVAL3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DTSBUS0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYSCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"OCLK": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"OCLKDIV": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"ENCALIB1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SELFINEOCLKDELAY": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN6": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DTSBUS0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COUNTERREADVAL2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN9": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SCANOUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"COUNTERREADVAL0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"COUNTERLOADVAL4": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"BURSTPENDINGPHY": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COUNTERLOADVAL5": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SYNCIN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN11": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"FINEENABLE": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COARSEOVERFLOW": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN8": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"OCLK": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"BURSTPENDING": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"ENCALIBPHY0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN13": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SYSCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ENCALIB0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ENCALIBPHY1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"OCLKDELAYED": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"COUNTERREADVAL3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN5": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"FINEOVERFLOW": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"COUNTERLOADVAL2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COARSEENABLE": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COUNTERLOADVAL0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COUNTERLOADVAL6": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"RDENABLE": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"COUNTERLOADVAL8": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHASEREFCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN15": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COUNTERREADVAL6": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"COUNTERLOADVAL1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"RST": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"OSERDESRST": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CTSBUS1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"COUNTERREADVAL5": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"MEMREFCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COUNTERLOADVAL3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COUNTERREADVAL7": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FINEINC": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"EDGEADV": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CTSBUS0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN7": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SCANMODEB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIVIDERST": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN10": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COUNTERREADVAL1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DQSBUS0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DTSBUS1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"COARSEINC": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COUNTERREADVAL4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"COUNTERLOADVAL7": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COUNTERLOADEN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DQSBUS1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN12": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SCANENB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SCANIN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN14": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"FREQREFCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COUNTERREADVAL8": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"RST": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"FINEINC": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COUNTERLOADVAL5": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DQSBUS0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"OSERDESRST": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"COUNTERLOADVAL2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COUNTERREADVAL7": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DQSBUS1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN14": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SCANENB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"BURSTPENDING": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COARSEINC": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COARSEENABLE": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COUNTERLOADVAL6": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CTSBUS0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN11": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COUNTERREADEN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SCANCLK": {
|
||||
"COUNTERREADVAL5": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DIVIDERST": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COUNTERREADVAL2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"COUNTERREADVAL3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"OCLKDELAYED": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"ENCALIBPHY0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN13": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ENCALIB0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN10": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"EDGEADV": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN9": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN8": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"RDENABLE": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"COUNTERREADVAL4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"COUNTERLOADVAL7": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"COUNTERLOADVAL4": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"MEMREFCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COUNTERREADVAL0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN4": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHASEREFCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT3": {
|
||||
"direction": "OUT"
|
||||
}
|
||||
},
|
||||
"site_pips": {
|
||||
"RSTINV:RST_B": {
|
||||
"from_pin": "RST_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"RSTINV:RST": {
|
||||
"from_pin": "RST",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"RSTINV:RST_B": {
|
||||
"from_pin": "RST_B",
|
||||
"to_pin": "OUT"
|
||||
}
|
||||
},
|
||||
"type": "PHASER_OUT_PHY"
|
||||
}
|
||||
}
|
||||
|
|
@ -1,24 +1,19 @@
|
|||
{
|
||||
"type": "PHASER_REF",
|
||||
"site_pins": {
|
||||
"TESTIN4": {
|
||||
"CLKIN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN6": {
|
||||
"TESTIN3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CLKOUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"RST": {
|
||||
"direction": "IN"
|
||||
"TESTOUT1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TMUXOUT": {
|
||||
"TESTOUT4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN1": {
|
||||
|
|
@ -27,63 +22,68 @@
|
|||
"TESTIN7": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN3": {
|
||||
"LOCKED": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT5": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT6": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"LOCKED": {
|
||||
"direction": "OUT"
|
||||
"PWRDWN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PWRDWN": {
|
||||
"TESTIN6": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CLKIN": {
|
||||
"direction": "IN"
|
||||
"TESTOUT7": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT3": {
|
||||
"TESTOUT0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CLKOUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TMUXOUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT6": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN5": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT0": {
|
||||
"direction": "OUT"
|
||||
"RST": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT4": {
|
||||
"direction": "OUT"
|
||||
"TESTIN4": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT7": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT1": {
|
||||
"TESTOUT3": {
|
||||
"direction": "OUT"
|
||||
}
|
||||
},
|
||||
"site_pips": {
|
||||
"RSTINV:RST_B": {
|
||||
"from_pin": "RST_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"PWRDWNINV:PWRDWN_B": {
|
||||
"from_pin": "PWRDWN_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"RSTINV:RST": {
|
||||
"from_pin": "RST",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"PWRDWNINV:PWRDWN": {
|
||||
"from_pin": "PWRDWN",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"RSTINV:RST": {
|
||||
"from_pin": "RST",
|
||||
"RSTINV:RST_B": {
|
||||
"from_pin": "RST_B",
|
||||
"to_pin": "OUT"
|
||||
}
|
||||
},
|
||||
"type": "PHASER_REF"
|
||||
}
|
||||
}
|
||||
|
|
@ -1,318 +1,318 @@
|
|||
{
|
||||
"type": "PHY_CONTROL",
|
||||
"site_pins": {
|
||||
"INRANKA0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUTPUT4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"INRANKD0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUTPUT15": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PHYCTLWD20": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD8": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUTPUT10": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUTPUT9": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PHYCTLWD9": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD6": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTINPUT14": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"OUTBURSTPENDING2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"INBURSTPENDING2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTINPUT1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTINPUT5": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"INBURSTPENDING1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUTPUT13": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"INRANKB1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"AUXOUTPUT2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PHYCTLWD27": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD23": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD17": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD22": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD15": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTINPUT3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUTPUT11": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PHYCTLWD18": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD30": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTINPUT15": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"MEMREFCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD4": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"REFDLLLOCK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD12": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PLLLOCK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWRENABLE": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTINPUT7": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"OUTBURSTPENDING0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"INRANKB0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUTPUT14": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUTPUT7": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PHYCTLWD1": {
|
||||
"PHYCTLWD8": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTINPUT0": {
|
||||
"TESTOUTPUT8": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PHYCTLWD6": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD14": {
|
||||
"PHYCTLWD24": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"OUTBURSTPENDING1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTINPUT12": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"AUXOUTPUT1": {
|
||||
"TESTOUTPUT3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PHYCTLWD25": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SYNCIN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTSELECT0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLALMOSTFULL": {
|
||||
"PHYCTLEMPTY": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PHYCTLWD3": {
|
||||
"PHYCTLWD13": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCLK": {
|
||||
"PHYCTLMSTREMPTY": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PCENABLECALIB0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PHYCTLWD11": {
|
||||
"PHYCTLWD30": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTINPUT10": {
|
||||
"PHYCTLWRENABLE": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLREADY": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"INRANKD1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUTPUT6": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PHYCTLWD2": {
|
||||
"TESTINPUT4": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PCENABLECALIB1": {
|
||||
"direction": "OUT"
|
||||
"PHYCTLWD20": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SCANENABLEN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTINPUT13": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUTPUT2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"INRANKC0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"READCALIBENABLE": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD10": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD7": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"INRANKC0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"AUXOUTPUT0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUTPUT8": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTSELECT1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD13": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD29": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTINPUT9": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTINPUT6": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"WRITECALIBENABLE": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUTPUT0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"INRANKA1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUTPUT1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"INBURSTPENDING0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTINPUT13": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTINPUT2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"OUTBURSTPENDING3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PHYCTLWD26": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLMSTREMPTY": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTINPUT8": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD28": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTSELECT2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SCANENABLEN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD5": {
|
||||
"PHYCTLWD31": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUTPUT5": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PHYCTLWD3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLFULL": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"AUXOUTPUT3": {
|
||||
"AUXOUTPUT2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PHYCTLWD24": {
|
||||
"TESTINPUT6": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"INBURSTPENDING3": {
|
||||
"TESTOUTPUT14": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTINPUT4": {
|
||||
"PCENABLECALIB0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUTPUT0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUTPUT13": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PHYCTLWD7": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD16": {
|
||||
"INRANKB1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PHYCTLWD9": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD31": {
|
||||
"TESTOUTPUT15": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PHYCTLWD15": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTINPUT11": {
|
||||
"PHYCTLWD18": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"RESET": {
|
||||
"PHYCTLWD1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"INRANKC1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PHYCTLWD19": {
|
||||
"TESTINPUT10": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUTPUT3": {
|
||||
"INRANKA1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTINPUT8": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTINPUT11": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTINPUT5": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD29": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"MEMREFCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD23": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTINPUT0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTINPUT15": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SYNCIN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTINPUT1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUTPUT10": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"INRANKA0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PHYCTLWD21": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLEMPTY": {
|
||||
"PHYCTLWD14": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD11": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLREADY": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"RESET": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTINPUT14": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"INBURSTPENDING0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PHYCTLALMOSTFULL": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PHYCTLWD2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD25": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD22": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"INBURSTPENDING1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PCENABLECALIB1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"INRANKD0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTSELECT0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD26": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"AUXOUTPUT3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"INBURSTPENDING2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PHYCTLWD12": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"INBURSTPENDING3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUTPUT9": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"AUXOUTPUT1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUTPUT12": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUTPUT11": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTSELECT2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUTPUT6": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"OUTBURSTPENDING0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PHYCTLWD27": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"WRITECALIBENABLE": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD16": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTINPUT12": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUTPUT1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PHYCTLWD19": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTINPUT7": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"REFDLLLOCK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"OUTBURSTPENDING2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"OUTBURSTPENDING3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"INRANKB0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTINPUT3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTSELECT1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTINPUT9": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTINPUT2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD28": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUTPUT7": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"INRANKD1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUTPUT4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PHYCTLWD17": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD5": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"AUXOUTPUT0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PLLLOCK": {
|
||||
"direction": "IN"
|
||||
}
|
||||
},
|
||||
"site_pips": {},
|
||||
"type": "PHY_CONTROL"
|
||||
"site_pips": {}
|
||||
}
|
||||
|
|
@ -1,27 +1,199 @@
|
|||
{
|
||||
"type": "PLLE2_ADV",
|
||||
"site_pins": {
|
||||
"TESTIN4": {
|
||||
"TESTOUT5": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO12": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DADDR0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CLKFBOUT": {
|
||||
"TESTOUT15": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO6": {
|
||||
"TESTOUT13": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT48": {
|
||||
"TESTOUT49": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN23": {
|
||||
"CLKIN2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CLKOUT1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT10": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TMUXOUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT14": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT27": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT62": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DI6": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN5": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN31": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN18": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT52": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT17": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT37": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT38": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO1": {
|
||||
"TESTIN6": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DO7": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO3": {
|
||||
"TESTIN22": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DI13": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DADDR6": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DWE": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CLKOUT4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT40": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DI5": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN29": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DI4": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT55": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DI10": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT48": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DO14": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CLKOUT5": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CLKOUT3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CLKIN1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN13": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT41": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO13": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DI9": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"LOCKED": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DADDR2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN12": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN17": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DI14": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT50": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT35": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN8": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DO9": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT57": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CLKOUT2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT16": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT7": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DI12": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN9": {
|
||||
|
|
@ -30,379 +202,238 @@
|
|||
"DI15": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN24": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN7": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DI6": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT55": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN28": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DI7": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT12": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DADDR4": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT37": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT6": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO8": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT47": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT54": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CLKOUT3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT62": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN14": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT28": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO10": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT23": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT27": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN21": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DI9": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DI11": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN27": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DADDR0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DI12": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DADDR6": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DI13": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN29": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DI14": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DO15": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DI4": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT63": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DI1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN15": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT22": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN22": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT21": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TMUXOUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT43": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT25": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT17": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN26": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN20": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT32": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DRDY": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN17": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT5": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT13": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CLKOUT5": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT15": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PWRDWN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DO4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DADDR3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT49": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT44": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN12": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT51": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN16": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DEN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DI10": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DO14": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DWE": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DADDR2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CLKOUT0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT19": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT30": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CLKOUT2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT39": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT45": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT20": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT18": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CLKOUT1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO12": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DI2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DO7": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN6": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN30": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT46": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN19": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT16": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN31": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CLKOUT4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT33": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN11": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DO11": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT36": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DI5": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DADDR5": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN8": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CLKINSEL": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN13": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CLKIN1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DO13": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN5": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT14": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT34": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT50": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN10": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT7": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT11": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT9": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT10": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT59": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT56": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT2": {
|
||||
"CLKOUT0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT23": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DI2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DO2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN23": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT22": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CLKFBIN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN7": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT19": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN15": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT46": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO11": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DADDR4": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DO10": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT28": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT20": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT45": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CLKINSEL": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DADDR1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT34": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT47": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DI11": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT42": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN28": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DO5": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"RST": {
|
||||
"TESTIN25": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT31": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO9": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CLKIN2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN1": {
|
||||
"PWRDWN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT58": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN18": {
|
||||
"TESTIN14": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT61": {
|
||||
"TESTOUT39": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DI1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT21": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT30": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN26": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DI7": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DO6": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO15": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"RST": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN24": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN16": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DI0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT33": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO8": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DEN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT9": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT31": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN27": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT18": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DI8": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT11": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DADDR3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT29": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT1": {
|
||||
"TESTOUT6": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO0": {
|
||||
"TESTOUT63": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN11": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT12": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT54": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN30": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN21": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT32": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT36": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT8": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT24": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT51": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN10": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DADDR5": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN19": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT59": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN20": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT53": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CLKFBOUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT60": {
|
||||
|
|
@ -411,67 +442,29 @@
|
|||
"DI3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"LOCKED": {
|
||||
"TESTOUT25": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT24": {
|
||||
"DRDY": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT8": {
|
||||
"TESTOUT44": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DI0": {
|
||||
"DO3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT61": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN4": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT40": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT35": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DI8": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT53": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DADDR1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CLKFBIN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT57": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT26": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT42": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN25": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT41": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT52": {
|
||||
"direction": "OUT"
|
||||
}
|
||||
},
|
||||
"site_pips": {
|
||||
"CLKINSELINV:CLKINSEL": {
|
||||
"from_pin": "CLKINSEL",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"RSTINV:RST_B": {
|
||||
"from_pin": "RST_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"PWRDWNINV:PWRDWN_B": {
|
||||
"from_pin": "PWRDWN_B",
|
||||
"to_pin": "OUT"
|
||||
|
|
@ -480,14 +473,21 @@
|
|||
"from_pin": "CLKINSEL_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"PWRDWNINV:PWRDWN": {
|
||||
"from_pin": "PWRDWN",
|
||||
"CLKINSELINV:CLKINSEL": {
|
||||
"from_pin": "CLKINSEL",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"RSTINV:RST": {
|
||||
"from_pin": "RST",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"PWRDWNINV:PWRDWN": {
|
||||
"from_pin": "PWRDWN",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"RSTINV:RST_B": {
|
||||
"from_pin": "RST_B",
|
||||
"to_pin": "OUT"
|
||||
}
|
||||
},
|
||||
"type": "PLLE2_ADV"
|
||||
}
|
||||
}
|
||||
|
|
@ -1,27 +1,27 @@
|
|||
{
|
||||
"type": "PMV2",
|
||||
"site_pins": {
|
||||
"O": {
|
||||
"ODIV2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"ODIV4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"A2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ODIV4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ODIV2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"A0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"A1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O": {
|
||||
"direction": "OUT"
|
||||
}
|
||||
},
|
||||
"site_pips": {},
|
||||
"type": "PMV2"
|
||||
"site_pips": {}
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -1,45 +1,45 @@
|
|||
{
|
||||
"type": "STARTUP",
|
||||
"site_pins": {
|
||||
"GSR": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CFGCLK": {
|
||||
"CFGMCLK": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PACK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"USRCCLKTS": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"USRCCLKO": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"USRDONEO": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CFGMCLK": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"USRDONETS": {
|
||||
"GSR": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"KEYCLEARB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PREQ": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PACK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"EOS": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PREQ": {
|
||||
"USRDONETS": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"USRCCLKO": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CFGCLK": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"USRDONEO": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"USRCCLKTS": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"GTS": {
|
||||
"direction": "IN"
|
||||
}
|
||||
},
|
||||
"site_pips": {},
|
||||
"type": "STARTUP"
|
||||
"site_pips": {}
|
||||
}
|
||||
|
|
@ -1,4 +1,5 @@
|
|||
{
|
||||
"type": "TIEOFF",
|
||||
"site_pins": {
|
||||
"HARD1": {
|
||||
"direction": "OUT"
|
||||
|
|
@ -7,6 +8,5 @@
|
|||
"direction": "OUT"
|
||||
}
|
||||
},
|
||||
"site_pips": {},
|
||||
"type": "TIEOFF"
|
||||
"site_pips": {}
|
||||
}
|
||||
|
|
@ -1,99 +1,19 @@
|
|||
{
|
||||
"type": "USR_ACCESS",
|
||||
"site_pins": {
|
||||
"DATA14": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA26": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA17": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CFGCLK": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA9": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA29": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA27": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA19": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA25": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA8": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA7": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATAVALID": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA24": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA30": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA22": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA23": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA13": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA16": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA15": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA28": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA10": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA6": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA11": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA18": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA12": {
|
||||
"DATA6": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA5": {
|
||||
"DATAVALID": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA20": {
|
||||
"DATA23": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA21": {
|
||||
|
|
@ -101,8 +21,88 @@
|
|||
},
|
||||
"DATA31": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA28": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA17": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA30": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CFGCLK": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA29": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA22": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA25": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA27": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA9": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA26": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA10": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA16": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA11": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA12": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA20": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA13": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA15": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA5": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA14": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA24": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA8": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA19": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA7": {
|
||||
"direction": "OUT"
|
||||
}
|
||||
},
|
||||
"site_pips": {},
|
||||
"type": "USR_ACCESS"
|
||||
"site_pips": {}
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,476 +1,476 @@
|
|||
{
|
||||
"tile_type": "BRAM_INT_INTERFACE_L",
|
||||
"pips": {
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B16->>INT_INTERFACE_LOGIC_OUTS_L16": {
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L16",
|
||||
"is_pseudo": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B16",
|
||||
"is_directional": "1",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B23->>INT_INTERFACE_LOGIC_OUTS_L23": {
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L23",
|
||||
"is_pseudo": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B23",
|
||||
"is_directional": "1",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B9->>INT_INTERFACE_LOGIC_OUTS_L9": {
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L9",
|
||||
"is_pseudo": "0",
|
||||
"is_directional": "1",
|
||||
"can_invert": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B9",
|
||||
"is_directional": "1",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B5->>INT_INTERFACE_LOGIC_OUTS_L5": {
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L5",
|
||||
"is_pseudo": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B5",
|
||||
"is_directional": "1",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B2->>INT_INTERFACE_LOGIC_OUTS_L2": {
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L2",
|
||||
"is_pseudo": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B2",
|
||||
"is_directional": "1",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B19->>INT_INTERFACE_LOGIC_OUTS_L19": {
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L19",
|
||||
"is_pseudo": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B19",
|
||||
"is_directional": "1",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B20->>INT_INTERFACE_LOGIC_OUTS_L20": {
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L20",
|
||||
"is_pseudo": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B20",
|
||||
"is_directional": "1",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B22->>INT_INTERFACE_LOGIC_OUTS_L22": {
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L22",
|
||||
"is_pseudo": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B22",
|
||||
"is_directional": "1",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B6->>INT_INTERFACE_LOGIC_OUTS_L6": {
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L6",
|
||||
"is_pseudo": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B6",
|
||||
"is_directional": "1",
|
||||
"can_invert": "0"
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L9",
|
||||
"is_pseudo": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B4->>INT_INTERFACE_LOGIC_OUTS_L4": {
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L4",
|
||||
"is_pseudo": "0",
|
||||
"is_directional": "1",
|
||||
"can_invert": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B4",
|
||||
"is_directional": "1",
|
||||
"can_invert": "0"
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L4",
|
||||
"is_pseudo": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B15->>INT_INTERFACE_LOGIC_OUTS_L15": {
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L15",
|
||||
"is_pseudo": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B15",
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B2->>INT_INTERFACE_LOGIC_OUTS_L2": {
|
||||
"is_directional": "1",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B7->>INT_INTERFACE_LOGIC_OUTS_L7": {
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L7",
|
||||
"is_pseudo": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B7",
|
||||
"is_directional": "1",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B18->>INT_INTERFACE_LOGIC_OUTS_L18": {
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L18",
|
||||
"is_pseudo": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B18",
|
||||
"is_directional": "1",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B1->>INT_INTERFACE_LOGIC_OUTS_L1": {
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L1",
|
||||
"is_pseudo": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B1",
|
||||
"is_directional": "1",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B0->>INT_INTERFACE_LOGIC_OUTS_L0": {
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L0",
|
||||
"is_pseudo": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B0",
|
||||
"is_directional": "1",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B11->>INT_INTERFACE_LOGIC_OUTS_L11": {
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L11",
|
||||
"is_pseudo": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B11",
|
||||
"is_directional": "1",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B17->>INT_INTERFACE_LOGIC_OUTS_L17": {
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L17",
|
||||
"is_pseudo": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B17",
|
||||
"is_directional": "1",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B3->>INT_INTERFACE_LOGIC_OUTS_L3": {
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L3",
|
||||
"is_pseudo": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B3",
|
||||
"is_directional": "1",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B12->>INT_INTERFACE_LOGIC_OUTS_L12": {
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L12",
|
||||
"is_pseudo": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B12",
|
||||
"is_directional": "1",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B13->>INT_INTERFACE_LOGIC_OUTS_L13": {
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L13",
|
||||
"is_pseudo": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B13",
|
||||
"is_directional": "1",
|
||||
"can_invert": "0"
|
||||
"can_invert": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B2",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L2",
|
||||
"is_pseudo": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B14->>INT_INTERFACE_LOGIC_OUTS_L14": {
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L14",
|
||||
"is_pseudo": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B14",
|
||||
"is_directional": "1",
|
||||
"can_invert": "0"
|
||||
"can_invert": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B14",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L14",
|
||||
"is_pseudo": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B13->>INT_INTERFACE_LOGIC_OUTS_L13": {
|
||||
"is_directional": "1",
|
||||
"can_invert": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B13",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L13",
|
||||
"is_pseudo": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B6->>INT_INTERFACE_LOGIC_OUTS_L6": {
|
||||
"is_directional": "1",
|
||||
"can_invert": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B6",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L6",
|
||||
"is_pseudo": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B19->>INT_INTERFACE_LOGIC_OUTS_L19": {
|
||||
"is_directional": "1",
|
||||
"can_invert": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B19",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L19",
|
||||
"is_pseudo": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B17->>INT_INTERFACE_LOGIC_OUTS_L17": {
|
||||
"is_directional": "1",
|
||||
"can_invert": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B17",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L17",
|
||||
"is_pseudo": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B0->>INT_INTERFACE_LOGIC_OUTS_L0": {
|
||||
"is_directional": "1",
|
||||
"can_invert": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L0",
|
||||
"is_pseudo": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B8->>INT_INTERFACE_LOGIC_OUTS_L8": {
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L8",
|
||||
"is_pseudo": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B8",
|
||||
"is_directional": "1",
|
||||
"can_invert": "0"
|
||||
"can_invert": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B8",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L8",
|
||||
"is_pseudo": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B10->>INT_INTERFACE_LOGIC_OUTS_L10": {
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L10",
|
||||
"is_pseudo": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B10",
|
||||
"is_directional": "1",
|
||||
"can_invert": "0"
|
||||
"can_invert": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B10",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L10",
|
||||
"is_pseudo": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B15->>INT_INTERFACE_LOGIC_OUTS_L15": {
|
||||
"is_directional": "1",
|
||||
"can_invert": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B15",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L15",
|
||||
"is_pseudo": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B1->>INT_INTERFACE_LOGIC_OUTS_L1": {
|
||||
"is_directional": "1",
|
||||
"can_invert": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B1",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L1",
|
||||
"is_pseudo": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B20->>INT_INTERFACE_LOGIC_OUTS_L20": {
|
||||
"is_directional": "1",
|
||||
"can_invert": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B20",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L20",
|
||||
"is_pseudo": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B11->>INT_INTERFACE_LOGIC_OUTS_L11": {
|
||||
"is_directional": "1",
|
||||
"can_invert": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B11",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L11",
|
||||
"is_pseudo": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B5->>INT_INTERFACE_LOGIC_OUTS_L5": {
|
||||
"is_directional": "1",
|
||||
"can_invert": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B5",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L5",
|
||||
"is_pseudo": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B12->>INT_INTERFACE_LOGIC_OUTS_L12": {
|
||||
"is_directional": "1",
|
||||
"can_invert": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B12",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L12",
|
||||
"is_pseudo": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B21->>INT_INTERFACE_LOGIC_OUTS_L21": {
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L21",
|
||||
"is_pseudo": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B21",
|
||||
"is_directional": "1",
|
||||
"can_invert": "0"
|
||||
"can_invert": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B21",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L21",
|
||||
"is_pseudo": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B16->>INT_INTERFACE_LOGIC_OUTS_L16": {
|
||||
"is_directional": "1",
|
||||
"can_invert": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B16",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L16",
|
||||
"is_pseudo": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B7->>INT_INTERFACE_LOGIC_OUTS_L7": {
|
||||
"is_directional": "1",
|
||||
"can_invert": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B7",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L7",
|
||||
"is_pseudo": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B18->>INT_INTERFACE_LOGIC_OUTS_L18": {
|
||||
"is_directional": "1",
|
||||
"can_invert": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B18",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L18",
|
||||
"is_pseudo": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B23->>INT_INTERFACE_LOGIC_OUTS_L23": {
|
||||
"is_directional": "1",
|
||||
"can_invert": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B23",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L23",
|
||||
"is_pseudo": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B22->>INT_INTERFACE_LOGIC_OUTS_L22": {
|
||||
"is_directional": "1",
|
||||
"can_invert": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B22",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L22",
|
||||
"is_pseudo": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B3->>INT_INTERFACE_LOGIC_OUTS_L3": {
|
||||
"is_directional": "1",
|
||||
"can_invert": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B3",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L3",
|
||||
"is_pseudo": "0"
|
||||
}
|
||||
},
|
||||
"wires": [
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX31",
|
||||
"INT_INTERFACE_WW4B3",
|
||||
"INT_INTERFACE_BYP0",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX17",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX44",
|
||||
"INT_INTERFACE_WR1END1",
|
||||
"INT_INTERFACE_LH4",
|
||||
"INT_INTERFACE_WW4END1",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L16",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L19",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX2",
|
||||
"INT_INTERFACE_BRAM_IMUX46",
|
||||
"INT_INTERFACE_BRAM_IMUX27",
|
||||
"INT_INTERFACE_WR1END3",
|
||||
"INT_INTERFACE_NW2A0",
|
||||
"INT_INTERFACE_EL1BEG2",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX37",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX33",
|
||||
"INT_INTERFACE_BRAM_IMUX0",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX42",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX8",
|
||||
"INT_INTERFACE_WW4A1",
|
||||
"INT_INTERFACE_ER1BEG0",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX29",
|
||||
"INT_INTERFACE_SW4A0",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B14",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX41",
|
||||
"INT_INTERFACE_NW4A2",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L14",
|
||||
"INT_INTERFACE_CTRL0",
|
||||
"INT_INTERFACE_FAN6",
|
||||
"INT_INTERFACE_WW4C3",
|
||||
"INT_INTERFACE_ER1BEG2",
|
||||
"INT_INTERFACE_FAN3",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX39",
|
||||
"INT_INTERFACE_BRAM_IMUX28",
|
||||
"INT_INTERFACE_BRAM_IMUX35",
|
||||
"INT_INTERFACE_BRAM_IMUX13",
|
||||
"INT_INTERFACE_NW4A1",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L4",
|
||||
"INT_INTERFACE_BRAM_IMUX30",
|
||||
"INT_INTERFACE_BLOCK_OUTS_L_B0",
|
||||
"INT_INTERFACE_LH7",
|
||||
"INT_INTERFACE_WW2A3",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX30",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L9",
|
||||
"INT_INTERFACE_NW4A0",
|
||||
"INT_INTERFACE_BRAM_IMUX33",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B22",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L12",
|
||||
"INT_INTERFACE_FAN5",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX28",
|
||||
"INT_INTERFACE_WW2END1",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B10",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX45",
|
||||
"INT_INTERFACE_LH10",
|
||||
"INT_INTERFACE_LH3",
|
||||
"INT_INTERFACE_BRAM_IMUX5",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX15",
|
||||
"INT_INTERFACE_PHASER_TO_IO_OCLK",
|
||||
"INT_INTERFACE_SE2A2",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B8",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX16",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX43",
|
||||
"INT_INTERFACE_EE4BEG0",
|
||||
"INT_INTERFACE_NE4BEG3",
|
||||
"INT_INTERFACE_BRAM_IMUX45",
|
||||
"INT_INTERFACE_EE4BEG2",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX47",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX1",
|
||||
"INT_INTERFACE_BRAM_IMUX11",
|
||||
"INT_INTERFACE_BYP6",
|
||||
"INT_INTERFACE_WW4END0",
|
||||
"INT_INTERFACE_EE2A1",
|
||||
"INT_INTERFACE_SW4END0",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX32",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX10",
|
||||
"INT_INTERFACE_BRAM_IMUX20",
|
||||
"INT_INTERFACE_BRAM_IMUX22",
|
||||
"INT_INTERFACE_SW2A0",
|
||||
"INT_INTERFACE_NW2A2",
|
||||
"INT_INTERFACE_SW4A2",
|
||||
"INT_INTERFACE_BYP1",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B1",
|
||||
"INT_INTERFACE_EE2A2",
|
||||
"INT_INTERFACE_WW4C2",
|
||||
"INT_INTERFACE_NE4C1",
|
||||
"INT_INTERFACE_BRAM_IMUX29",
|
||||
"INT_INTERFACE_NW2A3",
|
||||
"INT_INTERFACE_WL1END3",
|
||||
"INT_INTERFACE_SW2A2",
|
||||
"INT_INTERFACE_EE2BEG1",
|
||||
"INT_INTERFACE_BRAM_IMUX3",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L11",
|
||||
"INT_INTERFACE_BRAM_IMUX26",
|
||||
"INT_INTERFACE_BRAM_IMUX42",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX0",
|
||||
"INT_INTERFACE_PHASER_TO_IO_ICLK",
|
||||
"INT_INTERFACE_NE2A2",
|
||||
"INT_INTERFACE_NW4A3",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B17",
|
||||
"INT_INTERFACE_NE4BEG1",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B18",
|
||||
"INT_INTERFACE_EE4C3",
|
||||
"INT_INTERFACE_EE4A1",
|
||||
"INT_INTERFACE_CTRL1",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L15",
|
||||
"INT_INTERFACE_EE4C1",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B20",
|
||||
"INT_INTERFACE_BRAM_IMUX24",
|
||||
"INT_INTERFACE_BRAM_IMUX41",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX3",
|
||||
"INT_INTERFACE_CLK0",
|
||||
"INT_INTERFACE_BRAM_IMUX8",
|
||||
"INT_INTERFACE_BRAM_IMUX37",
|
||||
"INT_INTERFACE_SW2A1",
|
||||
"INT_INTERFACE_BRAM_IMUX9",
|
||||
"INT_INTERFACE_SW4END2",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L3",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX38",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX35",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B3",
|
||||
"INT_INTERFACE_NE4C3",
|
||||
"INT_INTERFACE_BRAM_IMUX18",
|
||||
"INT_INTERFACE_NE2A0",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L2",
|
||||
"INT_INTERFACE_NE4C0",
|
||||
"INT_INTERFACE_EE2A0",
|
||||
"INT_INTERFACE_FAN2",
|
||||
"INT_INTERFACE_EE4A2",
|
||||
"INT_INTERFACE_LH12",
|
||||
"INT_INTERFACE_SW2A3",
|
||||
"INT_INTERFACE_BYP3",
|
||||
"INT_INTERFACE_LH6",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B23",
|
||||
"INT_INTERFACE_WW2A2",
|
||||
"INT_INTERFACE_WW2END0",
|
||||
"INT_INTERFACE_BLOCK_OUTS_L_B1",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX9",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B7",
|
||||
"INT_INTERFACE_WW4B1",
|
||||
"INT_INTERFACE_EE4C2",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L21",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX36",
|
||||
"INT_INTERFACE_BRAM_IMUX17",
|
||||
"INT_INTERFACE_WW2END2",
|
||||
"INT_INTERFACE_SE4C1",
|
||||
"INT_INTERFACE_NW4END2",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L13",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX12",
|
||||
"INT_INTERFACE_WW4C1",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX23",
|
||||
"INT_INTERFACE_WW4C0",
|
||||
"INT_INTERFACE_WW4B2",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B6",
|
||||
"INT_INTERFACE_EE2BEG2",
|
||||
"INT_INTERFACE_WR1END0",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B4",
|
||||
"INT_INTERFACE_BYP4",
|
||||
"INT_INTERFACE_WW2A1",
|
||||
"INT_INTERFACE_SE4BEG2",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B9",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B16",
|
||||
"INT_INTERFACE_PHASER_TO_IO_OCLKDIV",
|
||||
"INT_INTERFACE_WW4A2",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX4",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX7",
|
||||
"INT_INTERFACE_BYP2",
|
||||
"INT_INTERFACE_WW2A0",
|
||||
"INT_INTERFACE_SW4A3",
|
||||
"INT_INTERFACE_NE2A1",
|
||||
"INT_INTERFACE_WL1END2",
|
||||
"INT_INTERFACE_LH8",
|
||||
"INT_INTERFACE_WL1END1",
|
||||
"INT_INTERFACE_WW4END2",
|
||||
"INT_INTERFACE_LH2",
|
||||
"INT_INTERFACE_BRAM_IMUX34",
|
||||
"INT_INTERFACE_BRAM_IMUX40",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX40",
|
||||
"INT_INTERFACE_FAN1",
|
||||
"INT_INTERFACE_EE4BEG1",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L5",
|
||||
"INT_INTERFACE_BRAM_IMUX31",
|
||||
"INT_INTERFACE_PHASER_TO_IO_OCLK1X_90",
|
||||
"INT_INTERFACE_SE2A3",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B13",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L22",
|
||||
"INT_INTERFACE_BRAM_IMUX6",
|
||||
"INT_INTERFACE_SE4BEG1",
|
||||
"INT_INTERFACE_SW4END3",
|
||||
"INT_INTERFACE_SW4END1",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX24",
|
||||
"INT_INTERFACE_MONITOR_P",
|
||||
"INT_INTERFACE_WL1END0",
|
||||
"INT_INTERFACE_WW2END3",
|
||||
"INT_INTERFACE_NE4C2",
|
||||
"INT_INTERFACE_BRAM_IMUX15",
|
||||
"INT_INTERFACE_BRAM_IMUX16",
|
||||
"INT_INTERFACE_NW2A1",
|
||||
"INT_INTERFACE_NW4END3",
|
||||
"INT_INTERFACE_BRAM_IMUX25",
|
||||
"INT_INTERFACE_NW4END0",
|
||||
"INT_INTERFACE_BRAM_IMUX7",
|
||||
"INT_INTERFACE_EE4B3",
|
||||
"INT_INTERFACE_SE4C0",
|
||||
"INT_INTERFACE_SE4C3",
|
||||
"INT_INTERFACE_BLOCK_OUTS_L_B3",
|
||||
"INT_INTERFACE_ER1BEG3",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX27",
|
||||
"INT_INTERFACE_BRAM_IMUX23",
|
||||
"INT_INTERFACE_EE4BEG3",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX34",
|
||||
"INT_INTERFACE_EE2A3",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L7",
|
||||
"INT_INTERFACE_BRAM_IMUX14",
|
||||
"INT_INTERFACE_BLOCK_OUTS_L_B2",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B5",
|
||||
"INT_INTERFACE_LH5",
|
||||
"INT_INTERFACE_FAN7",
|
||||
"INT_INTERFACE_EE4C0",
|
||||
"INT_INTERFACE_BRAM_IMUX47",
|
||||
"INT_INTERFACE_BYP7",
|
||||
"INT_INTERFACE_NE4BEG2",
|
||||
"INT_INTERFACE_NE4BEG0",
|
||||
"INT_INTERFACE_BRAM_IMUX1",
|
||||
"INT_INTERFACE_WR1END2",
|
||||
"INT_INTERFACE_BRAM_IMUX19",
|
||||
"L_INT_INTER_DQS_IOTOPHASER",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX19",
|
||||
"INT_INTERFACE_CLK1",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L8",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L17",
|
||||
"INT_INTERFACE_SE4C2",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B2",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX13",
|
||||
"INT_INTERFACE_EE2BEG3",
|
||||
"INT_INTERFACE_EE4B1",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX21",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX25",
|
||||
"INT_INTERFACE_BRAM_IMUX10",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B21",
|
||||
"INT_INTERFACE_EE4B0",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX26",
|
||||
"INT_INTERFACE_EL1BEG3",
|
||||
"INT_INTERFACE_FAN4",
|
||||
"INT_INTERFACE_BRAM_IMUX43",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L1",
|
||||
"INT_INTERFACE_EE4C2",
|
||||
"INT_INTERFACE_EE4BEG3",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L0",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX21",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX14",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B19",
|
||||
"INT_INTERFACE_WW4END3",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX20",
|
||||
"INT_INTERFACE_BRAM_IMUX4",
|
||||
"INT_INTERFACE_ER1BEG1",
|
||||
"INT_INTERFACE_BYP5",
|
||||
"INT_INTERFACE_EE4A0",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B11",
|
||||
"INT_INTERFACE_WW4A0",
|
||||
"INT_INTERFACE_BRAM_IMUX44",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B15",
|
||||
"INT_INTERFACE_WW4B0",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L10",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX11",
|
||||
"INT_INTERFACE_BRAM_IMUX39",
|
||||
"INT_INTERFACE_SE2A1",
|
||||
"INT_INTERFACE_PHASER_TO_IO_ICLKDIV",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX6",
|
||||
"INT_INTERFACE_SE4BEG0",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L23",
|
||||
"INT_INTERFACE_EE4A3",
|
||||
"INT_INTERFACE_NE2A3",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L20",
|
||||
"INT_INTERFACE_BRAM_IMUX38",
|
||||
"INT_INTERFACE_BRAM_IMUX12",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX5",
|
||||
"INT_INTERFACE_BRAM_IMUX2",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX22",
|
||||
"INT_INTERFACE_LH1",
|
||||
"INT_INTERFACE_LH9",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX42",
|
||||
"INT_INTERFACE_BRAM_IMUX17",
|
||||
"INT_INTERFACE_BYP6",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX27",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX13",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX31",
|
||||
"INT_INTERFACE_BRAM_IMUX24",
|
||||
"INT_INTERFACE_FAN0",
|
||||
"INT_INTERFACE_EE4B2",
|
||||
"INT_INTERFACE_LH11",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L18",
|
||||
"INT_INTERFACE_MONITOR_N",
|
||||
"INT_INTERFACE_EL1BEG0",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B12",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B0",
|
||||
"INT_INTERFACE_SW4A1",
|
||||
"INT_INTERFACE_EE2BEG0",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX18",
|
||||
"INT_INTERFACE_SE2A0",
|
||||
"INT_INTERFACE_EL1BEG1",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L6",
|
||||
"INT_INTERFACE_SE4BEG3",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L14",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX37",
|
||||
"INT_INTERFACE_NW2A3",
|
||||
"INT_INTERFACE_EE4C1",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX12",
|
||||
"INT_INTERFACE_FAN5",
|
||||
"INT_INTERFACE_EE4BEG0",
|
||||
"INT_INTERFACE_BRAM_IMUX23",
|
||||
"INT_INTERFACE_CTRL1",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX5",
|
||||
"INT_INTERFACE_BYP0",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B16",
|
||||
"L_INT_INTER_DQS_IOTOPHASER",
|
||||
"INT_INTERFACE_SW4END3",
|
||||
"INT_INTERFACE_EE4A0",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX6",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX10",
|
||||
"INT_INTERFACE_BYP2",
|
||||
"INT_INTERFACE_EE4BEG2",
|
||||
"INT_INTERFACE_WW2END1",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B7",
|
||||
"INT_INTERFACE_WW2A3",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX32",
|
||||
"INT_INTERFACE_LH5",
|
||||
"INT_INTERFACE_NE4C2",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L12",
|
||||
"INT_INTERFACE_BRAM_IMUX3",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L13",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B22",
|
||||
"INT_INTERFACE_BRAM_IMUX25",
|
||||
"INT_INTERFACE_LH3",
|
||||
"INT_INTERFACE_BLOCK_OUTS_L_B2",
|
||||
"INT_INTERFACE_NE2A2",
|
||||
"INT_INTERFACE_WW4A3",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX46",
|
||||
"INT_INTERFACE_BRAM_IMUX40",
|
||||
"INT_INTERFACE_SE4BEG2",
|
||||
"INT_INTERFACE_WW4END0",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B14",
|
||||
"INT_INTERFACE_BRAM_IMUX19",
|
||||
"INT_INTERFACE_BRAM_IMUX39",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B1",
|
||||
"INT_INTERFACE_FAN3",
|
||||
"INT_INTERFACE_BRAM_IMUX13",
|
||||
"INT_INTERFACE_BRAM_IMUX46",
|
||||
"INT_INTERFACE_WW4END2",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX20",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B5",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX39",
|
||||
"INT_INTERFACE_NW4A2",
|
||||
"INT_INTERFACE_EL1BEG1",
|
||||
"INT_INTERFACE_SW4END0",
|
||||
"INT_INTERFACE_BYP5",
|
||||
"INT_INTERFACE_BRAM_IMUX35",
|
||||
"INT_INTERFACE_BRAM_IMUX37",
|
||||
"INT_INTERFACE_WW4END3",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX33",
|
||||
"INT_INTERFACE_NE4C0",
|
||||
"INT_INTERFACE_WW4B3",
|
||||
"INT_INTERFACE_NW4END3",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L17",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX26",
|
||||
"INT_INTERFACE_WW2A1",
|
||||
"INT_INTERFACE_WL1END2",
|
||||
"INT_INTERFACE_NW4A0",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX30",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B4",
|
||||
"INT_INTERFACE_LH4",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX22",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B23",
|
||||
"INT_INTERFACE_LH11",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B20",
|
||||
"INT_INTERFACE_BRAM_IMUX15",
|
||||
"INT_INTERFACE_EE2A3",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX2",
|
||||
"INT_INTERFACE_NE4C3",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B21",
|
||||
"INT_INTERFACE_BRAM_IMUX28",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L20",
|
||||
"INT_INTERFACE_EE2BEG2",
|
||||
"INT_INTERFACE_WR1END3",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX38",
|
||||
"INT_INTERFACE_NW4END1",
|
||||
"INT_INTERFACE_BRAM_IMUX30",
|
||||
"INT_INTERFACE_PHASER_TO_IO_ICLKDIV",
|
||||
"INT_INTERFACE_PHASER_TO_IO_OCLK",
|
||||
"INT_INTERFACE_SW2A3",
|
||||
"INT_INTERFACE_NW2A1",
|
||||
"INT_INTERFACE_BRAM_IMUX5",
|
||||
"INT_INTERFACE_EE4BEG1",
|
||||
"INT_INTERFACE_WW4C0",
|
||||
"INT_INTERFACE_SW2A0",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L1",
|
||||
"INT_INTERFACE_WW2A0",
|
||||
"INT_INTERFACE_NW2A0",
|
||||
"INT_INTERFACE_WL1END3",
|
||||
"INT_INTERFACE_NW4END2",
|
||||
"INT_INTERFACE_EL1BEG2",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B18",
|
||||
"INT_INTERFACE_BRAM_IMUX11",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX16",
|
||||
"INT_INTERFACE_BLOCK_OUTS_L_B1",
|
||||
"INT_INTERFACE_BRAM_IMUX34",
|
||||
"INT_INTERFACE_BRAM_IMUX18",
|
||||
"INT_INTERFACE_BRAM_IMUX10",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX44",
|
||||
"INT_INTERFACE_FAN2",
|
||||
"INT_INTERFACE_BRAM_IMUX29",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L3",
|
||||
"INT_INTERFACE_BRAM_IMUX1",
|
||||
"INT_INTERFACE_WW4A0",
|
||||
"INT_INTERFACE_EE2BEG1",
|
||||
"INT_INTERFACE_SW4A2",
|
||||
"INT_INTERFACE_PHASER_TO_IO_OCLK1X_90",
|
||||
"INT_INTERFACE_BRAM_IMUX41",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B6",
|
||||
"INT_INTERFACE_EE4A2",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX47",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L15",
|
||||
"INT_INTERFACE_SW4END1",
|
||||
"INT_INTERFACE_SE2A3",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B10",
|
||||
"INT_INTERFACE_EE4B2",
|
||||
"INT_INTERFACE_SE4C2",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B11",
|
||||
"INT_INTERFACE_LH9",
|
||||
"INT_INTERFACE_SW2A1",
|
||||
"INT_INTERFACE_BRAM_IMUX44",
|
||||
"INT_INTERFACE_ER1BEG0",
|
||||
"INT_INTERFACE_NE4BEG0",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX28",
|
||||
"INT_INTERFACE_WL1END1",
|
||||
"INT_INTERFACE_BRAM_IMUX20",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX19",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX17",
|
||||
"INT_INTERFACE_NW4A1",
|
||||
"INT_INTERFACE_LH2",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B12",
|
||||
"INT_INTERFACE_NE4BEG3",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L11",
|
||||
"INT_INTERFACE_BRAM_IMUX27",
|
||||
"INT_INTERFACE_BYP7",
|
||||
"INT_INTERFACE_NW4END0",
|
||||
"INT_INTERFACE_EE4C3",
|
||||
"INT_INTERFACE_BRAM_IMUX6",
|
||||
"INT_INTERFACE_EE2A0",
|
||||
"INT_INTERFACE_BRAM_IMUX26",
|
||||
"INT_INTERFACE_BYP1",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L10",
|
||||
"INT_INTERFACE_CLK0",
|
||||
"INT_INTERFACE_WR1END0",
|
||||
"INT_INTERFACE_WW2END3",
|
||||
"INT_INTERFACE_SE4BEG1",
|
||||
"INT_INTERFACE_FAN1",
|
||||
"INT_INTERFACE_MONITOR_P",
|
||||
"INT_INTERFACE_LH1",
|
||||
"INT_INTERFACE_LH6",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B0",
|
||||
"INT_INTERFACE_FAN4",
|
||||
"INT_INTERFACE_BRAM_IMUX12",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L9",
|
||||
"INT_INTERFACE_EE2BEG3",
|
||||
"INT_INTERFACE_WR1END2",
|
||||
"INT_INTERFACE_MONITOR_N",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX41",
|
||||
"INT_INTERFACE_BRAM_IMUX9",
|
||||
"INT_INTERFACE_EE2A2",
|
||||
"INT_INTERFACE_SE2A2",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L2",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L4",
|
||||
"INT_INTERFACE_NE4C1",
|
||||
"INT_INTERFACE_ER1BEG2",
|
||||
"INT_INTERFACE_SE4BEG3",
|
||||
"INT_INTERFACE_EE4A1",
|
||||
"INT_INTERFACE_NE2A3",
|
||||
"INT_INTERFACE_WW4B1",
|
||||
"INT_INTERFACE_SE2A0",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B9",
|
||||
"INT_INTERFACE_BRAM_IMUX8",
|
||||
"INT_INTERFACE_EE4B3",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L7",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B19",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L21",
|
||||
"INT_INTERFACE_LH8",
|
||||
"INT_INTERFACE_BRAM_IMUX22",
|
||||
"INT_INTERFACE_BRAM_IMUX16",
|
||||
"INT_INTERFACE_EE4B1",
|
||||
"INT_INTERFACE_BYP4",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX11",
|
||||
"INT_INTERFACE_WW4END1",
|
||||
"INT_INTERFACE_SE4BEG0",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX35",
|
||||
"INT_INTERFACE_LH7",
|
||||
"INT_INTERFACE_BRAM_IMUX36",
|
||||
"INT_INTERFACE_BRAM_IMUX47",
|
||||
"INT_INTERFACE_LH10",
|
||||
"INT_INTERFACE_PHASER_TO_IO_ICLK",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L8",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX23",
|
||||
"INT_INTERFACE_PHASER_TO_IO_OCLKDIV",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX18",
|
||||
"INT_INTERFACE_ER1BEG1",
|
||||
"INT_INTERFACE_NE4BEG1",
|
||||
"INT_INTERFACE_BLOCK_OUTS_L_B3",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX0",
|
||||
"INT_INTERFACE_SW4A0",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX9",
|
||||
"INT_INTERFACE_SW4A3",
|
||||
"INT_INTERFACE_WW4B2",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX40",
|
||||
"INT_INTERFACE_FAN7",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX45",
|
||||
"INT_INTERFACE_WW2END0",
|
||||
"INT_INTERFACE_BRAM_IMUX43",
|
||||
"INT_INTERFACE_WW4A2",
|
||||
"INT_INTERFACE_EE4B0",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX25",
|
||||
"INT_INTERFACE_NE2A1",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L5",
|
||||
"INT_INTERFACE_EE4C0",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L23",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX8",
|
||||
"INT_INTERFACE_SE4C0",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B13",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX4",
|
||||
"INT_INTERFACE_BRAM_IMUX45",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX7",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L16",
|
||||
"INT_INTERFACE_BLOCK_OUTS_L_B0",
|
||||
"INT_INTERFACE_SW2A2",
|
||||
"INT_INTERFACE_BRAM_IMUX31",
|
||||
"INT_INTERFACE_WW4C3",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B15",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L19",
|
||||
"INT_INTERFACE_NE2A0",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B3",
|
||||
"INT_INTERFACE_EE2BEG0",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B8",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B17",
|
||||
"INT_INTERFACE_BRAM_IMUX14",
|
||||
"INT_INTERFACE_WW4B0",
|
||||
"INT_INTERFACE_NW2A2",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX43",
|
||||
"INT_INTERFACE_WW2END2",
|
||||
"INT_INTERFACE_SE2A1",
|
||||
"INT_INTERFACE_BRAM_IMUX32",
|
||||
"INT_INTERFACE_EL1BEG0",
|
||||
"INT_INTERFACE_BRAM_IMUX7",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L18",
|
||||
"INT_INTERFACE_BRAM_IMUX33",
|
||||
"INT_INTERFACE_BRAM_IMUX42",
|
||||
"INT_INTERFACE_WW4C2",
|
||||
"INT_INTERFACE_WW4C1",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX46",
|
||||
"INT_INTERFACE_BRAM_IMUX21",
|
||||
"INT_INTERFACE_BRAM_IMUX32"
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX24",
|
||||
"INT_INTERFACE_NE4BEG2",
|
||||
"INT_INTERFACE_BRAM_IMUX38",
|
||||
"INT_INTERFACE_EE4A3",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX1",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX34",
|
||||
"INT_INTERFACE_CTRL0",
|
||||
"INT_INTERFACE_BRAM_IMUX0",
|
||||
"INT_INTERFACE_SE4C1",
|
||||
"INT_INTERFACE_WL1END0",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L6",
|
||||
"INT_INTERFACE_WW4A1",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B2",
|
||||
"INT_INTERFACE_BYP3",
|
||||
"INT_INTERFACE_EL1BEG3",
|
||||
"INT_INTERFACE_FAN6",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX15",
|
||||
"INT_INTERFACE_LH12",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX36",
|
||||
"INT_INTERFACE_WR1END1",
|
||||
"INT_INTERFACE_BRAM_IMUX2",
|
||||
"INT_INTERFACE_ER1BEG3",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX3",
|
||||
"INT_INTERFACE_SW4A1",
|
||||
"INT_INTERFACE_EE2A1",
|
||||
"INT_INTERFACE_WW2A2",
|
||||
"INT_INTERFACE_SE4C3",
|
||||
"INT_INTERFACE_NW4A3",
|
||||
"INT_INTERFACE_SW4END2",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L22",
|
||||
"INT_INTERFACE_BRAM_IMUX4",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX29"
|
||||
],
|
||||
"tile_type": "BRAM_INT_INTERFACE_L",
|
||||
"sites": []
|
||||
}
|
||||
|
|
@ -1,476 +1,476 @@
|
|||
{
|
||||
"tile_type": "BRAM_INT_INTERFACE_R",
|
||||
"pips": {
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B7->>INT_INTERFACE_LOGIC_OUTS7": {
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS7",
|
||||
"is_pseudo": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B7",
|
||||
"is_directional": "1",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B9->>INT_INTERFACE_LOGIC_OUTS9": {
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS9",
|
||||
"is_pseudo": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B9",
|
||||
"is_directional": "1",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B21->>INT_INTERFACE_LOGIC_OUTS21": {
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS21",
|
||||
"is_pseudo": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B21",
|
||||
"is_directional": "1",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B17->>INT_INTERFACE_LOGIC_OUTS17": {
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS17",
|
||||
"is_pseudo": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B17",
|
||||
"is_directional": "1",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B5->>INT_INTERFACE_LOGIC_OUTS5": {
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS5",
|
||||
"is_pseudo": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B5",
|
||||
"is_directional": "1",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B22->>INT_INTERFACE_LOGIC_OUTS22": {
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS22",
|
||||
"is_pseudo": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B22",
|
||||
"is_directional": "1",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B16->>INT_INTERFACE_LOGIC_OUTS16": {
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS16",
|
||||
"is_pseudo": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B16",
|
||||
"is_directional": "1",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B2->>INT_INTERFACE_LOGIC_OUTS2": {
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS2",
|
||||
"is_pseudo": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B2",
|
||||
"is_directional": "1",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B11->>INT_INTERFACE_LOGIC_OUTS11": {
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS11",
|
||||
"is_pseudo": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B11",
|
||||
"is_directional": "1",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B19->>INT_INTERFACE_LOGIC_OUTS19": {
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS19",
|
||||
"is_pseudo": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B19",
|
||||
"is_directional": "1",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B23->>INT_INTERFACE_LOGIC_OUTS23": {
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS23",
|
||||
"is_pseudo": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B23",
|
||||
"is_directional": "1",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B20->>INT_INTERFACE_LOGIC_OUTS20": {
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS20",
|
||||
"is_pseudo": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B20",
|
||||
"is_directional": "1",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B4->>INT_INTERFACE_LOGIC_OUTS4": {
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS4",
|
||||
"is_pseudo": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B4",
|
||||
"is_directional": "1",
|
||||
"can_invert": "0"
|
||||
"can_invert": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B4",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS4",
|
||||
"is_pseudo": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B1->>INT_INTERFACE_LOGIC_OUTS1": {
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS1",
|
||||
"is_pseudo": "0",
|
||||
"is_directional": "1",
|
||||
"can_invert": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B1",
|
||||
"is_directional": "1",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B15->>INT_INTERFACE_LOGIC_OUTS15": {
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS15",
|
||||
"is_pseudo": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B15",
|
||||
"is_directional": "1",
|
||||
"can_invert": "0"
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS1",
|
||||
"is_pseudo": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B0->>INT_INTERFACE_LOGIC_OUTS0": {
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS0",
|
||||
"is_pseudo": "0",
|
||||
"is_directional": "1",
|
||||
"can_invert": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B0",
|
||||
"is_directional": "1",
|
||||
"can_invert": "0"
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS0",
|
||||
"is_pseudo": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B13->>INT_INTERFACE_LOGIC_OUTS13": {
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS13",
|
||||
"is_pseudo": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B13",
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B20->>INT_INTERFACE_LOGIC_OUTS20": {
|
||||
"is_directional": "1",
|
||||
"can_invert": "0"
|
||||
"can_invert": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B20",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS20",
|
||||
"is_pseudo": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B22->>INT_INTERFACE_LOGIC_OUTS22": {
|
||||
"is_directional": "1",
|
||||
"can_invert": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B22",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS22",
|
||||
"is_pseudo": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B23->>INT_INTERFACE_LOGIC_OUTS23": {
|
||||
"is_directional": "1",
|
||||
"can_invert": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B23",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS23",
|
||||
"is_pseudo": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B11->>INT_INTERFACE_LOGIC_OUTS11": {
|
||||
"is_directional": "1",
|
||||
"can_invert": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B11",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS11",
|
||||
"is_pseudo": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B18->>INT_INTERFACE_LOGIC_OUTS18": {
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS18",
|
||||
"is_pseudo": "0",
|
||||
"is_directional": "1",
|
||||
"can_invert": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B18",
|
||||
"is_directional": "1",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B14->>INT_INTERFACE_LOGIC_OUTS14": {
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS14",
|
||||
"is_pseudo": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B14",
|
||||
"is_directional": "1",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B8->>INT_INTERFACE_LOGIC_OUTS8": {
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS8",
|
||||
"is_pseudo": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B8",
|
||||
"is_directional": "1",
|
||||
"can_invert": "0"
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS18",
|
||||
"is_pseudo": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B3->>INT_INTERFACE_LOGIC_OUTS3": {
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS3",
|
||||
"is_pseudo": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B3",
|
||||
"is_directional": "1",
|
||||
"can_invert": "0"
|
||||
"can_invert": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B3",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS3",
|
||||
"is_pseudo": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B17->>INT_INTERFACE_LOGIC_OUTS17": {
|
||||
"is_directional": "1",
|
||||
"can_invert": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B17",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS17",
|
||||
"is_pseudo": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B15->>INT_INTERFACE_LOGIC_OUTS15": {
|
||||
"is_directional": "1",
|
||||
"can_invert": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B15",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS15",
|
||||
"is_pseudo": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B12->>INT_INTERFACE_LOGIC_OUTS12": {
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS12",
|
||||
"is_pseudo": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B12",
|
||||
"is_directional": "1",
|
||||
"can_invert": "0"
|
||||
"can_invert": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B12",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS12",
|
||||
"is_pseudo": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B13->>INT_INTERFACE_LOGIC_OUTS13": {
|
||||
"is_directional": "1",
|
||||
"can_invert": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B13",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS13",
|
||||
"is_pseudo": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B9->>INT_INTERFACE_LOGIC_OUTS9": {
|
||||
"is_directional": "1",
|
||||
"can_invert": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B9",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS9",
|
||||
"is_pseudo": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B21->>INT_INTERFACE_LOGIC_OUTS21": {
|
||||
"is_directional": "1",
|
||||
"can_invert": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B21",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS21",
|
||||
"is_pseudo": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B7->>INT_INTERFACE_LOGIC_OUTS7": {
|
||||
"is_directional": "1",
|
||||
"can_invert": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B7",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS7",
|
||||
"is_pseudo": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B5->>INT_INTERFACE_LOGIC_OUTS5": {
|
||||
"is_directional": "1",
|
||||
"can_invert": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B5",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS5",
|
||||
"is_pseudo": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B10->>INT_INTERFACE_LOGIC_OUTS10": {
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS10",
|
||||
"is_pseudo": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B10",
|
||||
"is_directional": "1",
|
||||
"can_invert": "0"
|
||||
"can_invert": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B10",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS10",
|
||||
"is_pseudo": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B14->>INT_INTERFACE_LOGIC_OUTS14": {
|
||||
"is_directional": "1",
|
||||
"can_invert": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B14",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS14",
|
||||
"is_pseudo": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B16->>INT_INTERFACE_LOGIC_OUTS16": {
|
||||
"is_directional": "1",
|
||||
"can_invert": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B16",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS16",
|
||||
"is_pseudo": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B19->>INT_INTERFACE_LOGIC_OUTS19": {
|
||||
"is_directional": "1",
|
||||
"can_invert": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B19",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS19",
|
||||
"is_pseudo": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B2->>INT_INTERFACE_LOGIC_OUTS2": {
|
||||
"is_directional": "1",
|
||||
"can_invert": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B2",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS2",
|
||||
"is_pseudo": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B6->>INT_INTERFACE_LOGIC_OUTS6": {
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS6",
|
||||
"is_pseudo": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B6",
|
||||
"is_directional": "1",
|
||||
"can_invert": "0"
|
||||
"can_invert": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B6",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS6",
|
||||
"is_pseudo": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B8->>INT_INTERFACE_LOGIC_OUTS8": {
|
||||
"is_directional": "1",
|
||||
"can_invert": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B8",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS8",
|
||||
"is_pseudo": "0"
|
||||
}
|
||||
},
|
||||
"wires": [
|
||||
"INT_INTERFACE_WW4B3",
|
||||
"INT_INTERFACE_BYP0",
|
||||
"INT_INTERFACE_LH4",
|
||||
"INT_INTERFACE_WR1END1",
|
||||
"INT_INTERFACE_WW4END1",
|
||||
"INT_INTERFACE_LOGIC_OUTS0",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B15",
|
||||
"INT_INTERFACE_LOGIC_OUTS4",
|
||||
"INT_INTERFACE_LOGIC_OUTS1",
|
||||
"INT_INTERFACE_BRAM_IMUX46",
|
||||
"INT_INTERFACE_BRAM_IMUX27",
|
||||
"INT_INTERFACE_WR1END3",
|
||||
"INT_INTERFACE_NW2A0",
|
||||
"INT_INTERFACE_EL1BEG2",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX32",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX24",
|
||||
"INT_INTERFACE_BRAM_IMUX0",
|
||||
"INT_INTERFACE_WW4A1",
|
||||
"INT_INTERFACE_ER1BEG0",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX9",
|
||||
"INT_INTERFACE_SW4A0",
|
||||
"INT_INTERFACE_CLK1",
|
||||
"INT_INTERFACE_EE4C2",
|
||||
"INT_INTERFACE_EE4BEG3",
|
||||
"INT_INTERFACE_BRAM_IMUX17",
|
||||
"INT_INTERFACE_BYP6",
|
||||
"INT_INTERFACE_BRAM_IMUX24",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX18",
|
||||
"INT_INTERFACE_NW4A2",
|
||||
"INT_INTERFACE_FAN0",
|
||||
"INT_INTERFACE_LOGIC_OUTS8",
|
||||
"INT_INTERFACE_NW2A3",
|
||||
"INT_INTERFACE_LOGIC_OUTS13",
|
||||
"INT_INTERFACE_CTRL0",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX13",
|
||||
"INT_INTERFACE_WW4C3",
|
||||
"INT_INTERFACE_FAN6",
|
||||
"INT_INTERFACE_ER1BEG2",
|
||||
"INT_INTERFACE_FAN3",
|
||||
"INT_INTERFACE_LOGIC_OUTS18",
|
||||
"INT_INTERFACE_BRAM_IMUX28",
|
||||
"INT_INTERFACE_BRAM_IMUX35",
|
||||
"INT_INTERFACE_BRAM_IMUX13",
|
||||
"INT_INTERFACE_NW4A1",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B4",
|
||||
"INT_INTERFACE_BRAM_IMUX21",
|
||||
"INT_INTERFACE_BRAM_IMUX30",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX20",
|
||||
"INT_INTERFACE_LH7",
|
||||
"INT_INTERFACE_WW2A3",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX29",
|
||||
"INT_INTERFACE_NW4A0",
|
||||
"INT_INTERFACE_BRAM_IMUX33",
|
||||
"INT_INTERFACE_EE4C1",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX28",
|
||||
"INT_INTERFACE_FAN5",
|
||||
"INT_INTERFACE_WW2END1",
|
||||
"INT_INTERFACE_LOGIC_OUTS10",
|
||||
"INT_INTERFACE_LH10",
|
||||
"INT_INTERFACE_LH3",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX14",
|
||||
"INT_INTERFACE_BRAM_IMUX5",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B23",
|
||||
"INT_INTERFACE_PHASER_TO_IO_OCLK",
|
||||
"INT_INTERFACE_SE2A2",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B9",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX12",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B1",
|
||||
"INT_INTERFACE_EE4BEG0",
|
||||
"INT_INTERFACE_BRAM_IMUX32",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B0",
|
||||
"INT_INTERFACE_NE4BEG3",
|
||||
"INT_INTERFACE_BRAM_IMUX45",
|
||||
"INT_INTERFACE_BRAM_IMUX23",
|
||||
"INT_INTERFACE_CTRL1",
|
||||
"INT_INTERFACE_BYP0",
|
||||
"INT_INTERFACE_LOGIC_OUTS14",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX19",
|
||||
"INT_INTERFACE_SW4END3",
|
||||
"L_INT_INTER_DQS_IOTOPHASER",
|
||||
"INT_INTERFACE_EE4A0",
|
||||
"INT_INTERFACE_BYP2",
|
||||
"INT_INTERFACE_EE4BEG2",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B13",
|
||||
"INT_INTERFACE_LOGIC_OUTS2",
|
||||
"INT_INTERFACE_WW2END1",
|
||||
"INT_INTERFACE_WW2A3",
|
||||
"INT_INTERFACE_LH5",
|
||||
"INT_INTERFACE_NE4C2",
|
||||
"INT_INTERFACE_BRAM_IMUX3",
|
||||
"INT_INTERFACE_BLOCK_OUTS_B2",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX14",
|
||||
"INT_INTERFACE_BRAM_IMUX25",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX46",
|
||||
"INT_INTERFACE_LH3",
|
||||
"INT_INTERFACE_LOGIC_OUTS6",
|
||||
"INT_INTERFACE_NE2A2",
|
||||
"INT_INTERFACE_WW4A3",
|
||||
"INT_INTERFACE_BRAM_IMUX40",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX8",
|
||||
"INT_INTERFACE_SE4BEG2",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B6",
|
||||
"INT_INTERFACE_WW4END0",
|
||||
"INT_INTERFACE_BRAM_IMUX19",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B23",
|
||||
"INT_INTERFACE_BRAM_IMUX39",
|
||||
"INT_INTERFACE_LOGIC_OUTS22",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX47",
|
||||
"INT_INTERFACE_FAN3",
|
||||
"INT_INTERFACE_BRAM_IMUX13",
|
||||
"INT_INTERFACE_BRAM_IMUX46",
|
||||
"INT_INTERFACE_BLOCK_OUTS_B1",
|
||||
"INT_INTERFACE_WW4END2",
|
||||
"INT_INTERFACE_LOGIC_OUTS11",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX4",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX8",
|
||||
"INT_INTERFACE_BRAM_IMUX11",
|
||||
"INT_INTERFACE_BYP6",
|
||||
"INT_INTERFACE_WW4END0",
|
||||
"INT_INTERFACE_EE2A1",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX45",
|
||||
"INT_INTERFACE_SW4END0",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX39",
|
||||
"INT_INTERFACE_BLOCK_OUTS_B0",
|
||||
"INT_INTERFACE_BRAM_IMUX20",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B3",
|
||||
"INT_INTERFACE_BRAM_IMUX22",
|
||||
"INT_INTERFACE_SW2A0",
|
||||
"INT_INTERFACE_NW2A2",
|
||||
"INT_INTERFACE_SW4A2",
|
||||
"INT_INTERFACE_BYP1",
|
||||
"INT_INTERFACE_LOGIC_OUTS15",
|
||||
"INT_INTERFACE_EE2A2",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX43",
|
||||
"INT_INTERFACE_BRAM_IMUX29",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX41",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX11",
|
||||
"INT_INTERFACE_WW4C2",
|
||||
"INT_INTERFACE_NE4C1",
|
||||
"INT_INTERFACE_WL1END3",
|
||||
"INT_INTERFACE_SW2A2",
|
||||
"INT_INTERFACE_NW2A3",
|
||||
"INT_INTERFACE_LOGIC_OUTS5",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX31",
|
||||
"INT_INTERFACE_EE2BEG1",
|
||||
"INT_INTERFACE_LOGIC_OUTS12",
|
||||
"INT_INTERFACE_BRAM_IMUX3",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B18",
|
||||
"INT_INTERFACE_BRAM_IMUX26",
|
||||
"INT_INTERFACE_BRAM_IMUX42",
|
||||
"INT_INTERFACE_LOGIC_OUTS3",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX19",
|
||||
"INT_INTERFACE_PHASER_TO_IO_ICLK",
|
||||
"INT_INTERFACE_NE2A2",
|
||||
"INT_INTERFACE_NW4A3",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX34",
|
||||
"INT_INTERFACE_LOGIC_OUTS9",
|
||||
"INT_INTERFACE_NE4BEG1",
|
||||
"INT_INTERFACE_EE4C3",
|
||||
"INT_INTERFACE_EE4A1",
|
||||
"INT_INTERFACE_LOGIC_OUTS20",
|
||||
"INT_INTERFACE_CTRL1",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX16",
|
||||
"INT_INTERFACE_EE4C1",
|
||||
"INT_INTERFACE_BRAM_IMUX24",
|
||||
"INT_INTERFACE_BRAM_IMUX41",
|
||||
"INT_INTERFACE_CLK0",
|
||||
"INT_INTERFACE_BRAM_IMUX8",
|
||||
"INT_INTERFACE_BRAM_IMUX37",
|
||||
"INT_INTERFACE_SW2A1",
|
||||
"INT_INTERFACE_BRAM_IMUX9",
|
||||
"INT_INTERFACE_SW4END2",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B12",
|
||||
"INT_INTERFACE_LOGIC_OUTS17",
|
||||
"INT_INTERFACE_NE4C3",
|
||||
"INT_INTERFACE_BRAM_IMUX18",
|
||||
"INT_INTERFACE_NE2A0",
|
||||
"INT_INTERFACE_NE4C0",
|
||||
"INT_INTERFACE_LOGIC_OUTS6",
|
||||
"INT_INTERFACE_EE2A0",
|
||||
"INT_INTERFACE_LOGIC_OUTS8",
|
||||
"INT_INTERFACE_FAN2",
|
||||
"INT_INTERFACE_EE4A2",
|
||||
"INT_INTERFACE_LH12",
|
||||
"INT_INTERFACE_SW2A3",
|
||||
"INT_INTERFACE_BYP3",
|
||||
"INT_INTERFACE_LH6",
|
||||
"INT_INTERFACE_WW2A2",
|
||||
"INT_INTERFACE_WW2END0",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX22",
|
||||
"INT_INTERFACE_WW4B1",
|
||||
"INT_INTERFACE_EE4C2",
|
||||
"INT_INTERFACE_BRAM_IMUX17",
|
||||
"INT_INTERFACE_LOGIC_OUTS16",
|
||||
"INT_INTERFACE_WW2END2",
|
||||
"INT_INTERFACE_SE4C1",
|
||||
"INT_INTERFACE_NW4END2",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX26",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B8",
|
||||
"INT_INTERFACE_WW4C1",
|
||||
"INT_INTERFACE_WW4C0",
|
||||
"INT_INTERFACE_WW4B2",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B2",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX23",
|
||||
"INT_INTERFACE_EE2BEG2",
|
||||
"INT_INTERFACE_WR1END0",
|
||||
"INT_INTERFACE_LOGIC_OUTS22",
|
||||
"INT_INTERFACE_BYP4",
|
||||
"INT_INTERFACE_WW2A1",
|
||||
"INT_INTERFACE_SE4BEG2",
|
||||
"INT_INTERFACE_PHASER_TO_IO_OCLKDIV",
|
||||
"INT_INTERFACE_WW4A2",
|
||||
"INT_INTERFACE_BYP2",
|
||||
"INT_INTERFACE_LOGIC_OUTS14",
|
||||
"INT_INTERFACE_BLOCK_OUTS_B2",
|
||||
"INT_INTERFACE_WW2A0",
|
||||
"INT_INTERFACE_SW4A3",
|
||||
"INT_INTERFACE_NE2A1",
|
||||
"INT_INTERFACE_WL1END2",
|
||||
"INT_INTERFACE_LH8",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B20",
|
||||
"INT_INTERFACE_WL1END1",
|
||||
"INT_INTERFACE_WW4END2",
|
||||
"INT_INTERFACE_LH2",
|
||||
"INT_INTERFACE_BRAM_IMUX34",
|
||||
"INT_INTERFACE_BRAM_IMUX40",
|
||||
"INT_INTERFACE_FAN1",
|
||||
"INT_INTERFACE_EE4BEG1",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B16",
|
||||
"INT_INTERFACE_BRAM_IMUX31",
|
||||
"INT_INTERFACE_PHASER_TO_IO_OCLK1X_90",
|
||||
"INT_INTERFACE_SE2A3",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B10",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B19",
|
||||
"INT_INTERFACE_BRAM_IMUX6",
|
||||
"INT_INTERFACE_SE4BEG1",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B17",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX7",
|
||||
"INT_INTERFACE_SW4END3",
|
||||
"INT_INTERFACE_SW4END1",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX30",
|
||||
"INT_INTERFACE_MONITOR_P",
|
||||
"INT_INTERFACE_WL1END0",
|
||||
"INT_INTERFACE_WW2END3",
|
||||
"INT_INTERFACE_NE4C2",
|
||||
"INT_INTERFACE_BRAM_IMUX15",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX35",
|
||||
"INT_INTERFACE_BRAM_IMUX16",
|
||||
"INT_INTERFACE_NW2A1",
|
||||
"INT_INTERFACE_NW4END3",
|
||||
"INT_INTERFACE_BRAM_IMUX25",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX2",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B22",
|
||||
"INT_INTERFACE_NW4END0",
|
||||
"INT_INTERFACE_BRAM_IMUX7",
|
||||
"INT_INTERFACE_EE4B3",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX28",
|
||||
"INT_INTERFACE_SE4C0",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX33",
|
||||
"INT_INTERFACE_SE4C3",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX40",
|
||||
"INT_INTERFACE_ER1BEG3",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX5",
|
||||
"INT_INTERFACE_EE4BEG3",
|
||||
"INT_INTERFACE_BRAM_IMUX23",
|
||||
"INT_INTERFACE_EE2A3",
|
||||
"INT_INTERFACE_BRAM_IMUX14",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B5",
|
||||
"INT_INTERFACE_LH5",
|
||||
"INT_INTERFACE_FAN7",
|
||||
"INT_INTERFACE_EE4C0",
|
||||
"INT_INTERFACE_BRAM_IMUX47",
|
||||
"INT_INTERFACE_BYP7",
|
||||
"INT_INTERFACE_NE4BEG2",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX38",
|
||||
"INT_INTERFACE_NE4BEG0",
|
||||
"INT_INTERFACE_BRAM_IMUX1",
|
||||
"INT_INTERFACE_WR1END2",
|
||||
"INT_INTERFACE_BRAM_IMUX19",
|
||||
"L_INT_INTER_DQS_IOTOPHASER",
|
||||
"INT_INTERFACE_CLK1",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX10",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX1",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B6",
|
||||
"INT_INTERFACE_SE4C2",
|
||||
"INT_INTERFACE_EE2BEG3",
|
||||
"INT_INTERFACE_EE4B1",
|
||||
"INT_INTERFACE_BRAM_IMUX10",
|
||||
"INT_INTERFACE_EE4B0",
|
||||
"INT_INTERFACE_LOGIC_OUTS21",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX37",
|
||||
"INT_INTERFACE_EL1BEG3",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B11",
|
||||
"INT_INTERFACE_FAN4",
|
||||
"INT_INTERFACE_BRAM_IMUX43",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX46",
|
||||
"INT_INTERFACE_WW4END3",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B14",
|
||||
"INT_INTERFACE_BLOCK_OUTS_B1",
|
||||
"INT_INTERFACE_BRAM_IMUX4",
|
||||
"INT_INTERFACE_ER1BEG1",
|
||||
"INT_INTERFACE_BYP5",
|
||||
"INT_INTERFACE_EE4A0",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX36",
|
||||
"INT_INTERFACE_WW4A0",
|
||||
"INT_INTERFACE_BRAM_IMUX44",
|
||||
"INT_INTERFACE_WW4B0",
|
||||
"INT_INTERFACE_BRAM_IMUX39",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX0",
|
||||
"INT_INTERFACE_SE2A1",
|
||||
"INT_INTERFACE_PHASER_TO_IO_ICLKDIV",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX25",
|
||||
"INT_INTERFACE_SE4BEG0",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX47",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX15",
|
||||
"INT_INTERFACE_EE4A3",
|
||||
"INT_INTERFACE_NE2A3",
|
||||
"INT_INTERFACE_BRAM_IMUX38",
|
||||
"INT_INTERFACE_BRAM_IMUX12",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX3",
|
||||
"INT_INTERFACE_BLOCK_OUTS_B3",
|
||||
"INT_INTERFACE_BRAM_IMUX2",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B21",
|
||||
"INT_INTERFACE_LH1",
|
||||
"INT_INTERFACE_LH9",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX21",
|
||||
"INT_INTERFACE_FAN0",
|
||||
"INT_INTERFACE_EE4B2",
|
||||
"INT_INTERFACE_LH11",
|
||||
"INT_INTERFACE_MONITOR_N",
|
||||
"INT_INTERFACE_EL1BEG0",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX6",
|
||||
"INT_INTERFACE_LOGIC_OUTS23",
|
||||
"INT_INTERFACE_LOGIC_OUTS2",
|
||||
"INT_INTERFACE_SW4A1",
|
||||
"INT_INTERFACE_LOGIC_OUTS7",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX42",
|
||||
"INT_INTERFACE_EE2BEG0",
|
||||
"INT_INTERFACE_LOGIC_OUTS19",
|
||||
"INT_INTERFACE_SE2A0",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B1",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX24",
|
||||
"INT_INTERFACE_NW4A2",
|
||||
"INT_INTERFACE_EL1BEG1",
|
||||
"INT_INTERFACE_SE4BEG3",
|
||||
"INT_INTERFACE_WW4A3",
|
||||
"INT_INTERFACE_SW4END0",
|
||||
"INT_INTERFACE_BYP5",
|
||||
"INT_INTERFACE_BRAM_IMUX35",
|
||||
"INT_INTERFACE_BRAM_IMUX37",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B16",
|
||||
"INT_INTERFACE_WW4END3",
|
||||
"INT_INTERFACE_NE4C0",
|
||||
"INT_INTERFACE_WW4B3",
|
||||
"INT_INTERFACE_NW4END3",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B19",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX30",
|
||||
"INT_INTERFACE_LOGIC_OUTS1",
|
||||
"INT_INTERFACE_WW2A1",
|
||||
"INT_INTERFACE_WL1END2",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B21",
|
||||
"INT_INTERFACE_NW4A0",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B17",
|
||||
"INT_INTERFACE_LH4",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX31",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX3",
|
||||
"INT_INTERFACE_LH11",
|
||||
"INT_INTERFACE_BRAM_IMUX15",
|
||||
"INT_INTERFACE_EE2A3",
|
||||
"INT_INTERFACE_NE4C3",
|
||||
"INT_INTERFACE_BRAM_IMUX28",
|
||||
"INT_INTERFACE_EE2BEG2",
|
||||
"INT_INTERFACE_WR1END3",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B14",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B10",
|
||||
"INT_INTERFACE_NW4END1",
|
||||
"INT_INTERFACE_BRAM_IMUX36",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B7",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX44",
|
||||
"INT_INTERFACE_LOGIC_OUTS20",
|
||||
"INT_INTERFACE_BRAM_IMUX30",
|
||||
"INT_INTERFACE_PHASER_TO_IO_ICLKDIV",
|
||||
"INT_INTERFACE_PHASER_TO_IO_OCLK",
|
||||
"INT_INTERFACE_LOGIC_OUTS12",
|
||||
"INT_INTERFACE_SW2A3",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX27",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX17"
|
||||
"INT_INTERFACE_NW2A1",
|
||||
"INT_INTERFACE_BRAM_IMUX5",
|
||||
"INT_INTERFACE_WW4C0",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX0",
|
||||
"INT_INTERFACE_SW2A0",
|
||||
"INT_INTERFACE_EE4BEG1",
|
||||
"INT_INTERFACE_WW2A0",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX26",
|
||||
"INT_INTERFACE_NW2A0",
|
||||
"INT_INTERFACE_WL1END3",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B15",
|
||||
"INT_INTERFACE_NW4END2",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX42",
|
||||
"INT_INTERFACE_EL1BEG2",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX23",
|
||||
"INT_INTERFACE_BRAM_IMUX11",
|
||||
"INT_INTERFACE_BRAM_IMUX34",
|
||||
"INT_INTERFACE_BRAM_IMUX18",
|
||||
"INT_INTERFACE_BRAM_IMUX10",
|
||||
"INT_INTERFACE_FAN2",
|
||||
"INT_INTERFACE_LOGIC_OUTS3",
|
||||
"INT_INTERFACE_BRAM_IMUX29",
|
||||
"INT_INTERFACE_BRAM_IMUX1",
|
||||
"INT_INTERFACE_WW4A0",
|
||||
"INT_INTERFACE_EE2BEG1",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX16",
|
||||
"INT_INTERFACE_SW4A2",
|
||||
"INT_INTERFACE_PHASER_TO_IO_OCLK1X_90",
|
||||
"INT_INTERFACE_BRAM_IMUX41",
|
||||
"INT_INTERFACE_EE4A2",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B0",
|
||||
"INT_INTERFACE_SW4END1",
|
||||
"INT_INTERFACE_SE2A3",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B2",
|
||||
"INT_INTERFACE_EE4B2",
|
||||
"INT_INTERFACE_LOGIC_OUTS23",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B13",
|
||||
"INT_INTERFACE_SE4C2",
|
||||
"INT_INTERFACE_LH9",
|
||||
"INT_INTERFACE_SW2A1",
|
||||
"INT_INTERFACE_BRAM_IMUX44",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX40",
|
||||
"INT_INTERFACE_ER1BEG0",
|
||||
"INT_INTERFACE_NE4BEG0",
|
||||
"INT_INTERFACE_WL1END1",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B5",
|
||||
"INT_INTERFACE_BRAM_IMUX20",
|
||||
"INT_INTERFACE_NW4A1",
|
||||
"INT_INTERFACE_LH2",
|
||||
"INT_INTERFACE_NE4BEG3",
|
||||
"INT_INTERFACE_BRAM_IMUX27",
|
||||
"INT_INTERFACE_BYP7",
|
||||
"INT_INTERFACE_NW4END0",
|
||||
"INT_INTERFACE_EE4C3",
|
||||
"INT_INTERFACE_EE2A0",
|
||||
"INT_INTERFACE_BRAM_IMUX6",
|
||||
"INT_INTERFACE_BRAM_IMUX26",
|
||||
"INT_INTERFACE_BYP1",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX43",
|
||||
"INT_INTERFACE_CLK0",
|
||||
"INT_INTERFACE_LOGIC_OUTS7",
|
||||
"INT_INTERFACE_WR1END0",
|
||||
"INT_INTERFACE_WW2END3",
|
||||
"INT_INTERFACE_SE4BEG1",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B4",
|
||||
"INT_INTERFACE_FAN1",
|
||||
"INT_INTERFACE_BLOCK_OUTS_B0",
|
||||
"INT_INTERFACE_MONITOR_P",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B8",
|
||||
"INT_INTERFACE_LH1",
|
||||
"INT_INTERFACE_LH6",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B18",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX9",
|
||||
"INT_INTERFACE_FAN4",
|
||||
"INT_INTERFACE_BRAM_IMUX12",
|
||||
"INT_INTERFACE_EE2BEG3",
|
||||
"INT_INTERFACE_WR1END2",
|
||||
"INT_INTERFACE_MONITOR_N",
|
||||
"INT_INTERFACE_LOGIC_OUTS15",
|
||||
"INT_INTERFACE_BRAM_IMUX9",
|
||||
"INT_INTERFACE_LOGIC_OUTS21",
|
||||
"INT_INTERFACE_EE2A2",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX15",
|
||||
"INT_INTERFACE_SE2A2",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX13",
|
||||
"INT_INTERFACE_NE4C1",
|
||||
"INT_INTERFACE_ER1BEG2",
|
||||
"INT_INTERFACE_LOGIC_OUTS19",
|
||||
"INT_INTERFACE_SE4BEG3",
|
||||
"INT_INTERFACE_EE4A1",
|
||||
"INT_INTERFACE_NE2A3",
|
||||
"INT_INTERFACE_WW4B1",
|
||||
"INT_INTERFACE_SE2A0",
|
||||
"INT_INTERFACE_BRAM_IMUX8",
|
||||
"INT_INTERFACE_EE4B3",
|
||||
"INT_INTERFACE_BLOCK_OUTS_B3",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B7",
|
||||
"INT_INTERFACE_LH8",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX2",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX1",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX44",
|
||||
"INT_INTERFACE_BRAM_IMUX22",
|
||||
"INT_INTERFACE_BRAM_IMUX16",
|
||||
"INT_INTERFACE_EE4B1",
|
||||
"INT_INTERFACE_BYP4",
|
||||
"INT_INTERFACE_WW4END1",
|
||||
"INT_INTERFACE_SE4BEG0",
|
||||
"INT_INTERFACE_LH7",
|
||||
"INT_INTERFACE_BRAM_IMUX36",
|
||||
"INT_INTERFACE_BRAM_IMUX47",
|
||||
"INT_INTERFACE_LH10",
|
||||
"INT_INTERFACE_LOGIC_OUTS10",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX45",
|
||||
"INT_INTERFACE_PHASER_TO_IO_ICLK",
|
||||
"INT_INTERFACE_PHASER_TO_IO_OCLKDIV",
|
||||
"INT_INTERFACE_LOGIC_OUTS0",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX6",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX29",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX34",
|
||||
"INT_INTERFACE_ER1BEG1",
|
||||
"INT_INTERFACE_NE4BEG1",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX37",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX22",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX21",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B20",
|
||||
"INT_INTERFACE_SW4A0",
|
||||
"INT_INTERFACE_SW4A3",
|
||||
"INT_INTERFACE_LOGIC_OUTS18",
|
||||
"INT_INTERFACE_WW4B2",
|
||||
"INT_INTERFACE_FAN7",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX41",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX33",
|
||||
"INT_INTERFACE_WW2END0",
|
||||
"INT_INTERFACE_BRAM_IMUX43",
|
||||
"INT_INTERFACE_WW4A2",
|
||||
"INT_INTERFACE_EE4B0",
|
||||
"INT_INTERFACE_NE2A1",
|
||||
"INT_INTERFACE_EE4C0",
|
||||
"INT_INTERFACE_SE4C0",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX39",
|
||||
"INT_INTERFACE_BRAM_IMUX45",
|
||||
"INT_INTERFACE_SW2A2",
|
||||
"INT_INTERFACE_BRAM_IMUX31",
|
||||
"INT_INTERFACE_LOGIC_OUTS5",
|
||||
"INT_INTERFACE_WW4C3",
|
||||
"INT_INTERFACE_NE2A0",
|
||||
"INT_INTERFACE_EE2BEG0",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX32",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX12",
|
||||
"INT_INTERFACE_BRAM_IMUX14",
|
||||
"INT_INTERFACE_WW4B0",
|
||||
"INT_INTERFACE_NW2A2",
|
||||
"INT_INTERFACE_WW2END2",
|
||||
"INT_INTERFACE_SE2A1",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX5",
|
||||
"INT_INTERFACE_BRAM_IMUX32",
|
||||
"INT_INTERFACE_EL1BEG0",
|
||||
"INT_INTERFACE_BRAM_IMUX7",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX36",
|
||||
"INT_INTERFACE_LOGIC_OUTS16",
|
||||
"INT_INTERFACE_BRAM_IMUX33",
|
||||
"INT_INTERFACE_LOGIC_OUTS4",
|
||||
"INT_INTERFACE_BRAM_IMUX42",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B12",
|
||||
"INT_INTERFACE_WW4C2",
|
||||
"INT_INTERFACE_WW4C1",
|
||||
"INT_INTERFACE_BRAM_IMUX21",
|
||||
"INT_INTERFACE_NE4BEG2",
|
||||
"INT_INTERFACE_BRAM_IMUX38",
|
||||
"INT_INTERFACE_EE4A3",
|
||||
"INT_INTERFACE_CTRL0",
|
||||
"INT_INTERFACE_BRAM_IMUX0",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX20",
|
||||
"INT_INTERFACE_SE4C1",
|
||||
"INT_INTERFACE_WL1END0",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX11",
|
||||
"INT_INTERFACE_WW4A1",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B3",
|
||||
"INT_INTERFACE_BYP3",
|
||||
"INT_INTERFACE_EL1BEG3",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX35",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX17",
|
||||
"INT_INTERFACE_FAN6",
|
||||
"INT_INTERFACE_LH12",
|
||||
"INT_INTERFACE_WR1END1",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX38",
|
||||
"INT_INTERFACE_BRAM_IMUX2",
|
||||
"INT_INTERFACE_ER1BEG3",
|
||||
"INT_INTERFACE_SW4A1",
|
||||
"INT_INTERFACE_EE2A1",
|
||||
"INT_INTERFACE_LOGIC_OUTS9",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX25",
|
||||
"INT_INTERFACE_WW2A2",
|
||||
"INT_INTERFACE_SE4C3",
|
||||
"INT_INTERFACE_NW4A3",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX7",
|
||||
"INT_INTERFACE_LOGIC_OUTS17",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B11",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B22",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX10",
|
||||
"INT_INTERFACE_SW4END2",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B9",
|
||||
"INT_INTERFACE_BRAM_IMUX4"
|
||||
],
|
||||
"tile_type": "BRAM_INT_INTERFACE_R",
|
||||
"sites": []
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -1,71 +1,71 @@
|
|||
{
|
||||
"tile_type": "BRKH_BRAM",
|
||||
"pips": {},
|
||||
"wires": [
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU14",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU12",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU1",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU12",
|
||||
"BRKH_BRAM_CASCADEA_L",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU9",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU5",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU1",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU6",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU10",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU11",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU12",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU14",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU13",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU0",
|
||||
"BRKH_BRAM_CASCADEA_R",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU3",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU14",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU4",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU3",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU10",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU7",
|
||||
"BRKH_BRAM_CASCADEB_L",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU8",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU7",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU6",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU8",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU10",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU8",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU3",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU0",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU7",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU11",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU6",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU9",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU14",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU5",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU6",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU0",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU2",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU13",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU2",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU10",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU1",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU9",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU2",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU5",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU1",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU13",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU11",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU4",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU2",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU3",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU8",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU5",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU14",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU2",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU12",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU13",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU4",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU9",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU11",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU9",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU4",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU6",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU9",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU14",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU13",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU8",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU2",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU12",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU1",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU0",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU8",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU10",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU7",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU2",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU8",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU3",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU9",
|
||||
"BRKH_BRAM_CASCADEB_L",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU6",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU8",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU13",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU0",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU10",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU0",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU1",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU6",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU1",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU1",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU0",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU4",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU12",
|
||||
"BRKH_BRAM_CASCADEA_L",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU13",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU14",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU3",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU11",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU7",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU3",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU10",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU5",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU10",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU5",
|
||||
"BRKH_BRAM_CASCADEB_R",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU14",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU5",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU7",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU4"
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU4",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU9",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU6",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU11",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU11",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU4",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU3",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU12",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU7",
|
||||
"BRKH_BRAM_CASCADEA_R",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU5",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU13"
|
||||
],
|
||||
"tile_type": "BRKH_BRAM",
|
||||
"sites": []
|
||||
}
|
||||
|
|
@ -1,125 +1,125 @@
|
|||
{
|
||||
"tile_type": "BRKH_B_TERM_INT",
|
||||
"pips": {},
|
||||
"wires": [
|
||||
"B_TERM_UTURN_INT_SS6C3",
|
||||
"B_TERM_UTURN_INT_SE6C0",
|
||||
"B_TERM_UTURN_INT_FAN_BOUNCE6",
|
||||
"B_TERM_UTURN_INT_FAN_BOUNCE0",
|
||||
"B_TERM_UTURN_INT_SW6D3",
|
||||
"B_TERM_UTURN_INT_LV5",
|
||||
"B_TERM_UTURN_INT_LVB1",
|
||||
"B_TERM_UTURN_INT_SS6B2",
|
||||
"B_TERM_UTURN_INT_FAN_BOUNCE4",
|
||||
"B_TERM_UTURN_INT_SS2BEG2",
|
||||
"B_TERM_UTURN_INT_SW6D1",
|
||||
"B_TERM_UTURN_INT_LV4",
|
||||
"B_TERM_UTURN_INT_LVB0",
|
||||
"B_TERM_UTURN_INT_ER1END_N3_3",
|
||||
"B_TERM_UTURN_INT_SW6D0",
|
||||
"B_TERM_UTURN_INT_SS6B1",
|
||||
"B_TERM_UTURN_INT_SS2A1",
|
||||
"B_TERM_UTURN_INT_SW2BEG3",
|
||||
"B_TERM_UTURN_INT_SW6C2",
|
||||
"B_TERM_UTURN_INT_SE6A2",
|
||||
"B_TERM_UTURN_INT_SW2BEG0",
|
||||
"B_TERM_UTURN_INT_SW6B1",
|
||||
"B_TERM_UTURN_INT_LV_L8",
|
||||
"B_TERM_UTURN_INT_SR1BEG2",
|
||||
"B_TERM_UTURN_INT_SS6BEG0",
|
||||
"B_TERM_UTURN_INT_LV9",
|
||||
"B_TERM_UTURN_INT_LV_L4",
|
||||
"B_TERM_UTURN_INT_SW6B3",
|
||||
"B_TERM_UTURN_INT_SL1BEG2",
|
||||
"B_TERM_UTURN_INT_SW2BEG1",
|
||||
"B_TERM_UTURN_INT_SS2BEG1",
|
||||
"B_TERM_UTURN_INT_SL1BEG3",
|
||||
"B_TERM_UTURN_INT_SE6A3",
|
||||
"B_TERM_UTURN_INT_ER1BEG0",
|
||||
"B_TERM_UTURN_INT_SS6D1",
|
||||
"B_TERM_UTURN_INT_SS6BEG1",
|
||||
"B_TERM_UTURN_INT_SW6A3",
|
||||
"B_TERM_UTURN_INT_LV8",
|
||||
"B_TERM_UTURN_INT_SW6D2",
|
||||
"B_TERM_UTURN_INT_SW6B0",
|
||||
"B_TERM_UTURN_INT_SE6D3",
|
||||
"B_TERM_UTURN_INT_SW6C3",
|
||||
"B_TERM_UTURN_INT_LVB_L5",
|
||||
"B_TERM_UTURN_INT_SW2BEG2",
|
||||
"B_TERM_UTURN_INT_SR1BEG1",
|
||||
"B_TERM_UTURN_INT_SE6B1",
|
||||
"B_TERM_UTURN_INT_LVB4",
|
||||
"B_TERM_UTURN_INT_SS6A0",
|
||||
"B_TERM_UTURN_INT_SS2A2",
|
||||
"B_TERM_UTURN_INT_SS2BEG0",
|
||||
"B_TERM_UTURN_INT_SW6C1",
|
||||
"B_TERM_UTURN_INT_SE6B3",
|
||||
"B_TERM_UTURN_INT_LV3",
|
||||
"B_TERM_UTURN_INT_SL1BEG0",
|
||||
"B_TERM_UTURN_INT_SW6C0",
|
||||
"B_TERM_UTURN_INT_SS6E2",
|
||||
"B_TERM_UTURN_INT_LV_L5",
|
||||
"B_TERM_UTURN_INT_LV_L18",
|
||||
"B_TERM_UTURN_INT_SS6A2",
|
||||
"B_TERM_UTURN_INT_SE6C1",
|
||||
"B_TERM_UTURN_INT_SS6E1",
|
||||
"B_TERM_UTURN_INT_SE6A1",
|
||||
"B_TERM_UTURN_INT_SW6A0",
|
||||
"B_TERM_UTURN_INT_LV_L7",
|
||||
"B_TERM_UTURN_INT_SS6E3",
|
||||
"B_TERM_UTURN_INT_LVB2",
|
||||
"B_TERM_UTURN_INT_SS6D2",
|
||||
"B_TERM_UTURN_INT_LV_L3",
|
||||
"B_TERM_UTURN_INT_SS2A0",
|
||||
"B_TERM_UTURN_INT_LVB_L2",
|
||||
"B_TERM_UTURN_INT_SE6D1",
|
||||
"B_TERM_UTURN_INT_SS6E0",
|
||||
"B_TERM_UTURN_INT_LV7",
|
||||
"B_TERM_UTURN_INT_SE6B0",
|
||||
"B_TERM_UTURN_INT_SS6B3",
|
||||
"B_TERM_UTURN_INT_SE2BEG3",
|
||||
"B_TERM_UTURN_INT_SW6END_N0_3",
|
||||
"B_TERM_UTURN_INT_SS6C1",
|
||||
"B_TERM_UTURN_INT_SW6A2",
|
||||
"B_TERM_UTURN_INT_LVB_L0",
|
||||
"B_TERM_UTURN_INT_SS6BEG3",
|
||||
"B_TERM_UTURN_INT_LV_L2",
|
||||
"B_TERM_UTURN_INT_WR1BEG0",
|
||||
"B_TERM_UTURN_INT_SS6E2",
|
||||
"B_TERM_UTURN_INT_SR1BEG3",
|
||||
"B_TERM_UTURN_INT_SE6A1",
|
||||
"B_TERM_UTURN_INT_SW2BEG1",
|
||||
"B_TERM_UTURN_INT_LVB5",
|
||||
"B_TERM_UTURN_INT_SS2BEG3",
|
||||
"B_TERM_UTURN_INT_LVB_L3",
|
||||
"B_TERM_UTURN_INT_SW6B2",
|
||||
"B_TERM_UTURN_INT_SW2BEG3",
|
||||
"B_TERM_UTURN_INT_SS6BEG3",
|
||||
"B_TERM_UTURN_INT_SW6C3",
|
||||
"B_TERM_UTURN_INT_SW2BEG2",
|
||||
"B_TERM_UTURN_INT_LVB_L0",
|
||||
"B_TERM_UTURN_INT_SS6A0",
|
||||
"B_TERM_UTURN_INT_SE2BEG2",
|
||||
"B_TERM_UTURN_INT_SS6A1",
|
||||
"B_TERM_UTURN_INT_SS6B2",
|
||||
"B_TERM_UTURN_INT_LV_L5",
|
||||
"B_TERM_UTURN_INT_LVB_L3",
|
||||
"B_TERM_UTURN_INT_LVB_L2",
|
||||
"B_TERM_UTURN_INT_ER1END_N3_3",
|
||||
"B_TERM_UTURN_INT_SS2BEG1",
|
||||
"B_TERM_UTURN_INT_SW6A0",
|
||||
"B_TERM_UTURN_INT_LVB2",
|
||||
"B_TERM_UTURN_INT_LV5",
|
||||
"B_TERM_UTURN_INT_SE6C2",
|
||||
"B_TERM_UTURN_INT_SW2BEG0",
|
||||
"B_TERM_UTURN_INT_LVB4",
|
||||
"B_TERM_UTURN_INT_SW6A3",
|
||||
"B_TERM_UTURN_INT_LVB3",
|
||||
"B_TERM_UTURN_INT_LV_L6",
|
||||
"B_TERM_UTURN_INT_SS6D3",
|
||||
"B_TERM_UTURN_INT_SE2BEG1",
|
||||
"B_TERM_UTURN_INT_FAN_BOUNCE0",
|
||||
"B_TERM_UTURN_INT_LV_L3",
|
||||
"B_TERM_UTURN_INT_SE6D2",
|
||||
"B_TERM_UTURN_INT_SS6B0",
|
||||
"B_TERM_UTURN_INT_FAN_BOUNCE6",
|
||||
"B_TERM_UTURN_INT_LV_L2",
|
||||
"B_TERM_UTURN_INT_SS6E0",
|
||||
"B_TERM_UTURN_INT_SE6C0",
|
||||
"B_TERM_UTURN_INT_ER1BEG0",
|
||||
"B_TERM_UTURN_INT_WR1BEG0",
|
||||
"B_TERM_UTURN_INT_SS6A2",
|
||||
"B_TERM_UTURN_INT_LV_L8",
|
||||
"B_TERM_UTURN_INT_SE6B3",
|
||||
"B_TERM_UTURN_INT_LV18",
|
||||
"B_TERM_UTURN_INT_SW6B1",
|
||||
"B_TERM_UTURN_INT_LV_L9",
|
||||
"B_TERM_UTURN_INT_LVB_L1",
|
||||
"B_TERM_UTURN_INT_SE2BEG2",
|
||||
"B_TERM_UTURN_INT_SE6B2",
|
||||
"B_TERM_UTURN_INT_SS6BEG2",
|
||||
"B_TERM_UTURN_INT_SE2BEG1",
|
||||
"B_TERM_UTURN_INT_FAN_BOUNCE2",
|
||||
"B_TERM_UTURN_INT_SE6C2",
|
||||
"B_TERM_UTURN_INT_SS2A3",
|
||||
"B_TERM_UTURN_INT_LVB_L4",
|
||||
"B_TERM_UTURN_INT_LV2",
|
||||
"B_TERM_UTURN_INT_SS6B0",
|
||||
"B_TERM_UTURN_INT_LV18",
|
||||
"B_TERM_UTURN_INT_LV6",
|
||||
"B_TERM_UTURN_INT_SS6C0",
|
||||
"B_TERM_UTURN_INT_SE6A0",
|
||||
"B_TERM_UTURN_INT_SS6C2",
|
||||
"B_TERM_UTURN_INT_SW6A1",
|
||||
"B_TERM_UTURN_INT_SE6D0",
|
||||
"B_TERM_UTURN_INT_SE2BEG0",
|
||||
"B_TERM_UTURN_INT_SS6D0",
|
||||
"B_TERM_UTURN_INT_SR1BEG3",
|
||||
"B_TERM_UTURN_INT_SW6B2",
|
||||
"B_TERM_UTURN_INT_SE6C3",
|
||||
"B_TERM_UTURN_INT_LVB_L5",
|
||||
"B_TERM_UTURN_INT_SS2BEG0",
|
||||
"B_TERM_UTURN_INT_SL1BEG1",
|
||||
"B_TERM_UTURN_INT_WR1END0",
|
||||
"B_TERM_UTURN_INT_SE6C1",
|
||||
"B_TERM_UTURN_INT_SW6D1",
|
||||
"B_TERM_UTURN_INT_FAN_BOUNCE2",
|
||||
"B_TERM_UTURN_INT_SR1BEG2",
|
||||
"B_TERM_UTURN_INT_SW6A1",
|
||||
"B_TERM_UTURN_INT_SS6D1",
|
||||
"B_TERM_UTURN_INT_LVB0",
|
||||
"B_TERM_UTURN_INT_SS6D2",
|
||||
"B_TERM_UTURN_INT_SW6C0",
|
||||
"B_TERM_UTURN_INT_SS6D0",
|
||||
"B_TERM_UTURN_INT_SS6A3",
|
||||
"B_TERM_UTURN_INT_SE6D2"
|
||||
"B_TERM_UTURN_INT_SL1BEG3",
|
||||
"B_TERM_UTURN_INT_LV2",
|
||||
"B_TERM_UTURN_INT_SE6D3",
|
||||
"B_TERM_UTURN_INT_SW6C1",
|
||||
"B_TERM_UTURN_INT_SS2A1",
|
||||
"B_TERM_UTURN_INT_LVB_L4",
|
||||
"B_TERM_UTURN_INT_SS2A2",
|
||||
"B_TERM_UTURN_INT_SW6B0",
|
||||
"B_TERM_UTURN_INT_LV6",
|
||||
"B_TERM_UTURN_INT_SE6B1",
|
||||
"B_TERM_UTURN_INT_SW6D2",
|
||||
"B_TERM_UTURN_INT_SE6D1",
|
||||
"B_TERM_UTURN_INT_FAN_BOUNCE4",
|
||||
"B_TERM_UTURN_INT_SW6D3",
|
||||
"B_TERM_UTURN_INT_SW6END_N0_3",
|
||||
"B_TERM_UTURN_INT_WR1END0",
|
||||
"B_TERM_UTURN_INT_SW6A2",
|
||||
"B_TERM_UTURN_INT_LV7",
|
||||
"B_TERM_UTURN_INT_SE6B2",
|
||||
"B_TERM_UTURN_INT_SE6A0",
|
||||
"B_TERM_UTURN_INT_SE6A2",
|
||||
"B_TERM_UTURN_INT_SS6B1",
|
||||
"B_TERM_UTURN_INT_SS2BEG3",
|
||||
"B_TERM_UTURN_INT_SS6C1",
|
||||
"B_TERM_UTURN_INT_SS6C0",
|
||||
"B_TERM_UTURN_INT_LVB1",
|
||||
"B_TERM_UTURN_INT_LV_L4",
|
||||
"B_TERM_UTURN_INT_LV3",
|
||||
"B_TERM_UTURN_INT_SS2A0",
|
||||
"B_TERM_UTURN_INT_LV4",
|
||||
"B_TERM_UTURN_INT_SE6C3",
|
||||
"B_TERM_UTURN_INT_SS2BEG2",
|
||||
"B_TERM_UTURN_INT_SS6BEG1",
|
||||
"B_TERM_UTURN_INT_LV_L18",
|
||||
"B_TERM_UTURN_INT_LV_L6",
|
||||
"B_TERM_UTURN_INT_SW6D0",
|
||||
"B_TERM_UTURN_INT_SS6B3",
|
||||
"B_TERM_UTURN_INT_SS6C3",
|
||||
"B_TERM_UTURN_INT_SW6C2",
|
||||
"B_TERM_UTURN_INT_SE6A3",
|
||||
"B_TERM_UTURN_INT_LV_L7",
|
||||
"B_TERM_UTURN_INT_SS2A3",
|
||||
"B_TERM_UTURN_INT_SS6C2",
|
||||
"B_TERM_UTURN_INT_LV8",
|
||||
"B_TERM_UTURN_INT_SS6BEG2",
|
||||
"B_TERM_UTURN_INT_SL1BEG0",
|
||||
"B_TERM_UTURN_INT_SS6E3",
|
||||
"B_TERM_UTURN_INT_SS6BEG0",
|
||||
"B_TERM_UTURN_INT_SS6E1",
|
||||
"B_TERM_UTURN_INT_SR1BEG1",
|
||||
"B_TERM_UTURN_INT_SW6B3",
|
||||
"B_TERM_UTURN_INT_SE6D0",
|
||||
"B_TERM_UTURN_INT_SE6B0",
|
||||
"B_TERM_UTURN_INT_LV9",
|
||||
"B_TERM_UTURN_INT_SS6D3",
|
||||
"B_TERM_UTURN_INT_SL1BEG2"
|
||||
],
|
||||
"tile_type": "BRKH_B_TERM_INT",
|
||||
"sites": []
|
||||
}
|
||||
|
|
@ -1,11 +1,11 @@
|
|||
{
|
||||
"tile_type": "BRKH_CLB",
|
||||
"pips": {},
|
||||
"wires": [
|
||||
"BRKH_CLB_COUT1_L",
|
||||
"BRKH_CLB_COUT0_L",
|
||||
"BRKH_CLB_COUT1_R",
|
||||
"BRKH_CLB_COUT0_R"
|
||||
"BRKH_CLB_COUT0_L",
|
||||
"BRKH_CLB_COUT0_R",
|
||||
"BRKH_CLB_COUT1_L"
|
||||
],
|
||||
"tile_type": "BRKH_CLB",
|
||||
"sites": []
|
||||
}
|
||||
|
|
@ -1,135 +1,135 @@
|
|||
{
|
||||
"tile_type": "BRKH_CLK",
|
||||
"pips": {},
|
||||
"wires": [
|
||||
"BRKH_CLK_R_CK_BUFG_CASC13",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC12",
|
||||
"BRKH_CLK_R_CK_GCLK2",
|
||||
"BRKH_CLK_CK_GCLK20",
|
||||
"BRKH_CLK_CK_GCLK30",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC15",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC30",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC2",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC4",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC8",
|
||||
"BRKH_CLK_R_CK_GCLK3",
|
||||
"BRKH_CLK_CK_GCLK24",
|
||||
"BRKH_CLK_CK_GCLK9",
|
||||
"BRKH_CLK_CK_GCLK25",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC25",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC26",
|
||||
"BRKH_CLK_CK_GCLK5",
|
||||
"BRKH_CLK_CK_GCLK0",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC9",
|
||||
"BRKH_CLK_CK_BUFG_CASC11",
|
||||
"BRKH_CLK_CK_BUFG_CASC4",
|
||||
"BRKH_CLK_CK_GCLK12",
|
||||
"BRKH_CLK_CK_GCLK17",
|
||||
"BRKH_CLK_CK_GCLK14",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC28",
|
||||
"BRKH_CLK_CK_GCLK31",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC10",
|
||||
"BRKH_CLK_CK_BUFG_CASC0",
|
||||
"BRKH_CLK_CK_GCLK2",
|
||||
"BRKH_CLK_CK_BUFG_CASC14",
|
||||
"BRKH_CLK_CK_GCLK18",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC24",
|
||||
"BRKH_CLK_CK_BUFG_CASC18",
|
||||
"BRKH_CLK_CK_GCLK28",
|
||||
"BRKH_CLK_CK_BUFG_CASC15",
|
||||
"BRKH_CLK_CK_GCLK4",
|
||||
"BRKH_CLK_CK_BUFG_CASC21",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC29",
|
||||
"BRKH_CLK_R_CK_GCLK1",
|
||||
"BRKH_CLK_R_CK_GCLK21",
|
||||
"BRKH_CLK_CK_BUFG_CASC28",
|
||||
"BRKH_CLK_CK_GCLK3",
|
||||
"BRKH_CLK_R_CK_GCLK17",
|
||||
"BRKH_CLK_R_CK_GCLK27",
|
||||
"BRKH_CLK_R_CK_GCLK25",
|
||||
"BRKH_CLK_R_CK_GCLK7",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC11",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC27",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC20",
|
||||
"BRKH_CLK_CK_BUFG_CASC12",
|
||||
"BRKH_CLK_CK_BUFG_CASC2",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC3",
|
||||
"BRKH_CLK_CK_BUFG_CASC29",
|
||||
"BRKH_CLK_CK_GCLK27",
|
||||
"BRKH_CLK_CK_GCLK21",
|
||||
"BRKH_CLK_CK_GCLK15",
|
||||
"BRKH_CLK_CK_BUFG_CASC26",
|
||||
"BRKH_CLK_R_CK_GCLK28",
|
||||
"BRKH_CLK_CK_GCLK16",
|
||||
"BRKH_CLK_CK_GCLK22",
|
||||
"BRKH_CLK_CK_BUFG_CASC25",
|
||||
"BRKH_CLK_CK_GCLK10",
|
||||
"BRKH_CLK_CK_BUFG_CASC3",
|
||||
"BRKH_CLK_R_CK_GCLK14",
|
||||
"BRKH_CLK_R_CK_GCLK19",
|
||||
"BRKH_CLK_CK_GCLK19",
|
||||
"BRKH_CLK_CK_GCLK23",
|
||||
"BRKH_CLK_R_CK_GCLK24",
|
||||
"BRKH_CLK_CK_GCLK13",
|
||||
"BRKH_CLK_R_CK_GCLK31",
|
||||
"BRKH_CLK_R_CK_GCLK8",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC21",
|
||||
"BRKH_CLK_CK_GCLK7",
|
||||
"BRKH_CLK_R_CK_GCLK0",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC6",
|
||||
"BRKH_CLK_CK_BUFG_CASC23",
|
||||
"BRKH_CLK_CK_GCLK26",
|
||||
"BRKH_CLK_CK_BUFG_CASC30",
|
||||
"BRKH_CLK_R_CK_GCLK18",
|
||||
"BRKH_CLK_R_CK_GCLK29",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC7",
|
||||
"BRKH_CLK_CK_BUFG_CASC22",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC16",
|
||||
"BRKH_CLK_CK_BUFG_CASC1",
|
||||
"BRKH_CLK_R_CK_GCLK12",
|
||||
"BRKH_CLK_R_CK_GCLK11",
|
||||
"BRKH_CLK_CK_GCLK8",
|
||||
"BRKH_CLK_CK_BUFG_CASC16",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC18",
|
||||
"BRKH_CLK_CK_BUFG_CASC7",
|
||||
"BRKH_CLK_CK_BUFG_CASC31",
|
||||
"BRKH_CLK_R_CK_GCLK4",
|
||||
"BRKH_CLK_CK_GCLK11",
|
||||
"BRKH_CLK_R_CK_GCLK26",
|
||||
"BRKH_CLK_CK_BUFG_CASC17",
|
||||
"BRKH_CLK_CK_BUFG_CASC9",
|
||||
"BRKH_CLK_CK_GCLK6",
|
||||
"BRKH_CLK_CK_BUFG_CASC24",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC5",
|
||||
"BRKH_CLK_CK_BUFG_CASC19",
|
||||
"BRKH_CLK_R_CK_GCLK23",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC22",
|
||||
"BRKH_CLK_CK_GCLK1",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC17",
|
||||
"BRKH_CLK_R_CK_GCLK22",
|
||||
"BRKH_CLK_R_CK_GCLK9",
|
||||
"BRKH_CLK_CK_BUFG_CASC13",
|
||||
"BRKH_CLK_CK_BUFG_CASC10",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC0",
|
||||
"BRKH_CLK_R_CK_GCLK20",
|
||||
"BRKH_CLK_R_CK_GCLK5",
|
||||
"BRKH_CLK_CK_BUFG_CASC20",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC23",
|
||||
"BRKH_CLK_R_CK_GCLK6",
|
||||
"BRKH_CLK_R_CK_GCLK15",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC1",
|
||||
"BRKH_CLK_CK_BUFG_CASC8",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC31",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC14",
|
||||
"BRKH_CLK_CK_BUFG_CASC27",
|
||||
"BRKH_CLK_R_CK_GCLK30",
|
||||
"BRKH_CLK_CK_GCLK29",
|
||||
"BRKH_CLK_R_CK_GCLK10",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC24",
|
||||
"BRKH_CLK_CK_GCLK28",
|
||||
"BRKH_CLK_R_CK_GCLK2",
|
||||
"BRKH_CLK_CK_GCLK30",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC19",
|
||||
"BRKH_CLK_CK_GCLK15",
|
||||
"BRKH_CLK_R_CK_GCLK23",
|
||||
"BRKH_CLK_CK_BUFG_CASC22",
|
||||
"BRKH_CLK_CK_BUFG_CASC5",
|
||||
"BRKH_CLK_CK_BUFG_CASC6",
|
||||
"BRKH_CLK_R_CK_GCLK13",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC2",
|
||||
"BRKH_CLK_CK_GCLK11",
|
||||
"BRKH_CLK_R_CK_GCLK9",
|
||||
"BRKH_CLK_CK_BUFG_CASC20",
|
||||
"BRKH_CLK_R_CK_GCLK18",
|
||||
"BRKH_CLK_R_CK_GCLK21",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC3",
|
||||
"BRKH_CLK_CK_BUFG_CASC7",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC1",
|
||||
"BRKH_CLK_CK_BUFG_CASC16",
|
||||
"BRKH_CLK_CK_BUFG_CASC15",
|
||||
"BRKH_CLK_CK_GCLK14",
|
||||
"BRKH_CLK_CK_GCLK5",
|
||||
"BRKH_CLK_R_CK_GCLK16",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC19"
|
||||
"BRKH_CLK_R_CK_GCLK14",
|
||||
"BRKH_CLK_CK_BUFG_CASC13",
|
||||
"BRKH_CLK_R_CK_GCLK22",
|
||||
"BRKH_CLK_R_CK_GCLK0",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC21",
|
||||
"BRKH_CLK_R_CK_GCLK26",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC0",
|
||||
"BRKH_CLK_CK_GCLK8",
|
||||
"BRKH_CLK_CK_BUFG_CASC8",
|
||||
"BRKH_CLK_CK_GCLK24",
|
||||
"BRKH_CLK_CK_BUFG_CASC30",
|
||||
"BRKH_CLK_CK_BUFG_CASC0",
|
||||
"BRKH_CLK_CK_BUFG_CASC24",
|
||||
"BRKH_CLK_CK_BUFG_CASC25",
|
||||
"BRKH_CLK_CK_BUFG_CASC10",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC29",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC14",
|
||||
"BRKH_CLK_CK_GCLK29",
|
||||
"BRKH_CLK_CK_BUFG_CASC18",
|
||||
"BRKH_CLK_CK_GCLK4",
|
||||
"BRKH_CLK_CK_BUFG_CASC4",
|
||||
"BRKH_CLK_CK_GCLK23",
|
||||
"BRKH_CLK_CK_GCLK20",
|
||||
"BRKH_CLK_R_CK_GCLK24",
|
||||
"BRKH_CLK_CK_GCLK1",
|
||||
"BRKH_CLK_R_CK_GCLK25",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC25",
|
||||
"BRKH_CLK_CK_GCLK18",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC7",
|
||||
"BRKH_CLK_R_CK_GCLK3",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC17",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC22",
|
||||
"BRKH_CLK_CK_BUFG_CASC31",
|
||||
"BRKH_CLK_CK_GCLK7",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC4",
|
||||
"BRKH_CLK_CK_GCLK25",
|
||||
"BRKH_CLK_CK_GCLK10",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC20",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC23",
|
||||
"BRKH_CLK_CK_BUFG_CASC23",
|
||||
"BRKH_CLK_CK_GCLK31",
|
||||
"BRKH_CLK_R_CK_GCLK15",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC13",
|
||||
"BRKH_CLK_CK_BUFG_CASC14",
|
||||
"BRKH_CLK_CK_BUFG_CASC27",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC26",
|
||||
"BRKH_CLK_R_CK_GCLK5",
|
||||
"BRKH_CLK_CK_GCLK16",
|
||||
"BRKH_CLK_CK_BUFG_CASC21",
|
||||
"BRKH_CLK_R_CK_GCLK28",
|
||||
"BRKH_CLK_R_CK_GCLK19",
|
||||
"BRKH_CLK_CK_BUFG_CASC11",
|
||||
"BRKH_CLK_R_CK_GCLK31",
|
||||
"BRKH_CLK_R_CK_GCLK12",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC12",
|
||||
"BRKH_CLK_CK_BUFG_CASC2",
|
||||
"BRKH_CLK_R_CK_GCLK4",
|
||||
"BRKH_CLK_R_CK_GCLK30",
|
||||
"BRKH_CLK_CK_GCLK6",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC11",
|
||||
"BRKH_CLK_CK_BUFG_CASC19",
|
||||
"BRKH_CLK_R_CK_GCLK17",
|
||||
"BRKH_CLK_R_CK_GCLK10",
|
||||
"BRKH_CLK_CK_GCLK0",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC27",
|
||||
"BRKH_CLK_CK_BUFG_CASC17",
|
||||
"BRKH_CLK_CK_GCLK17",
|
||||
"BRKH_CLK_CK_GCLK27",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC9",
|
||||
"BRKH_CLK_CK_GCLK2",
|
||||
"BRKH_CLK_CK_BUFG_CASC3",
|
||||
"BRKH_CLK_R_CK_GCLK7",
|
||||
"BRKH_CLK_CK_GCLK19",
|
||||
"BRKH_CLK_CK_BUFG_CASC1",
|
||||
"BRKH_CLK_R_CK_GCLK1",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC5",
|
||||
"BRKH_CLK_CK_GCLK21",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC31",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC30",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC28",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC8",
|
||||
"BRKH_CLK_R_CK_GCLK29",
|
||||
"BRKH_CLK_CK_GCLK13",
|
||||
"BRKH_CLK_CK_GCLK12",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC16",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC18",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC15",
|
||||
"BRKH_CLK_R_CK_GCLK20",
|
||||
"BRKH_CLK_CK_BUFG_CASC9",
|
||||
"BRKH_CLK_CK_BUFG_CASC26",
|
||||
"BRKH_CLK_R_CK_GCLK8",
|
||||
"BRKH_CLK_CK_GCLK26",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC10",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC6",
|
||||
"BRKH_CLK_CK_BUFG_CASC29",
|
||||
"BRKH_CLK_R_CK_GCLK13",
|
||||
"BRKH_CLK_R_CK_GCLK27",
|
||||
"BRKH_CLK_CK_BUFG_CASC6",
|
||||
"BRKH_CLK_CK_BUFG_CASC12",
|
||||
"BRKH_CLK_CK_GCLK9",
|
||||
"BRKH_CLK_CK_GCLK3",
|
||||
"BRKH_CLK_R_CK_GCLK11",
|
||||
"BRKH_CLK_CK_BUFG_CASC28"
|
||||
],
|
||||
"tile_type": "BRKH_CLK",
|
||||
"sites": []
|
||||
}
|
||||
|
|
@ -1,16 +1,16 @@
|
|||
{
|
||||
"tile_type": "BRKH_CMT",
|
||||
"pips": {},
|
||||
"wires": [
|
||||
"BRKH_CMT_FREQ_REF_NS3",
|
||||
"BRKH_CMT_PHASEREF1",
|
||||
"BRKH_CMT_FREQ_REF_NS2",
|
||||
"BRKH_CMT_FREQ_REF_NS0",
|
||||
"BRKH_CMT_PHASEREF_BELOW1",
|
||||
"BRKH_CMT_PHYCTRL_SYNC_BB",
|
||||
"BRKH_CMT_PHASEREF0",
|
||||
"BRKH_CMT_FREQ_REF_NS2",
|
||||
"BRKH_CMT_PHASEREF_BELOW0",
|
||||
"BRKH_CMT_FREQ_REF_NS1",
|
||||
"BRKH_CMT_PHASEREF_BELOW0"
|
||||
"BRKH_CMT_FREQ_REF_NS3",
|
||||
"BRKH_CMT_FREQ_REF_NS0",
|
||||
"BRKH_CMT_PHYCTRL_SYNC_BB",
|
||||
"BRKH_CMT_PHASEREF1",
|
||||
"BRKH_CMT_PHASEREF0"
|
||||
],
|
||||
"tile_type": "BRKH_CMT",
|
||||
"sites": []
|
||||
}
|
||||
|
|
@ -1,105 +1,105 @@
|
|||
{
|
||||
"tile_type": "BRKH_DSP_L",
|
||||
"pips": {},
|
||||
"wires": [
|
||||
"BRKH_DSP_ACIN2",
|
||||
"BRKH_DSP_PCIN35",
|
||||
"BRKH_DSP_PCIN20",
|
||||
"BRKH_DSP_BCIN15",
|
||||
"BRKH_DSP_ACIN11",
|
||||
"BRKH_DSP_ACIN9",
|
||||
"BRKH_DSP_ACIN14",
|
||||
"BRKH_DSP_PCIN45",
|
||||
"BRKH_DSP_PCIN12",
|
||||
"BRKH_DSP_BCIN16",
|
||||
"BRKH_DSP_PCIN30",
|
||||
"BRKH_DSP_PCIN31",
|
||||
"BRKH_DSP_PCIN29",
|
||||
"BRKH_DSP_ACIN5",
|
||||
"BRKH_DSP_PCIN21",
|
||||
"BRKH_DSP_ACIN3",
|
||||
"BRKH_DSP_PCIN8",
|
||||
"BRKH_DSP_PCIN3",
|
||||
"BRKH_DSP_PCIN46",
|
||||
"BRKH_DSP_BCIN4",
|
||||
"BRKH_DSP_BCIN13",
|
||||
"BRKH_DSP_PCIN18",
|
||||
"BRKH_DSP_ACIN24",
|
||||
"BRKH_DSP_PCIN6",
|
||||
"BRKH_DSP_PCIN4",
|
||||
"BRKH_DSP_BCIN0",
|
||||
"BRKH_DSP_PCIN44",
|
||||
"BRKH_DSP_BCIN17",
|
||||
"BRKH_DSP_ACIN15",
|
||||
"BRKH_DSP_PCIN34",
|
||||
"BRKH_DSP_ACIN17",
|
||||
"BRKH_DSP_BCIN14",
|
||||
"BRKH_DSP_PCIN27",
|
||||
"BRKH_DSP_BCIN8",
|
||||
"BRKH_DSP_PCIN2",
|
||||
"BRKH_DSP_CARRYCASCIN",
|
||||
"BRKH_DSP_PCIN40",
|
||||
"BRKH_DSP_PCIN41",
|
||||
"BRKH_DSP_PCIN16",
|
||||
"BRKH_DSP_ACIN12",
|
||||
"BRKH_DSP_PCIN39",
|
||||
"BRKH_DSP_ACIN23",
|
||||
"BRKH_DSP_BCIN3",
|
||||
"BRKH_DSP_PCIN37",
|
||||
"BRKH_DSP_PCIN32",
|
||||
"BRKH_DSP_ACIN6",
|
||||
"BRKH_DSP_PCIN14",
|
||||
"BRKH_DSP_ACIN25",
|
||||
"BRKH_DSP_BCIN1",
|
||||
"BRKH_DSP_PCIN23",
|
||||
"BRKH_DSP_PCIN33",
|
||||
"BRKH_DSP_ACIN16",
|
||||
"BRKH_DSP_PCIN7",
|
||||
"BRKH_DSP_ACIN26",
|
||||
"BRKH_DSP_BCIN10",
|
||||
"BRKH_DSP_ACIN4",
|
||||
"BRKH_DSP_ACIN21",
|
||||
"BRKH_DSP_PCIN38",
|
||||
"BRKH_DSP_PCIN22",
|
||||
"BRKH_DSP_PCIN1",
|
||||
"BRKH_DSP_BCIN11",
|
||||
"BRKH_DSP_BCIN5",
|
||||
"BRKH_DSP_ACIN10",
|
||||
"BRKH_DSP_PCIN43",
|
||||
"BRKH_DSP_PCIN15",
|
||||
"BRKH_DSP_PCIN36",
|
||||
"BRKH_DSP_PCIN26",
|
||||
"BRKH_DSP_ACIN29",
|
||||
"BRKH_DSP_PCIN24",
|
||||
"BRKH_DSP_ACIN19",
|
||||
"BRKH_DSP_BCIN7",
|
||||
"BRKH_DSP_PCIN25",
|
||||
"BRKH_DSP_ACIN8",
|
||||
"BRKH_DSP_PCIN42",
|
||||
"BRKH_DSP_PCIN5",
|
||||
"BRKH_DSP_BCIN2",
|
||||
"BRKH_DSP_BCIN9",
|
||||
"BRKH_DSP_PCIN13",
|
||||
"BRKH_DSP_ACIN7",
|
||||
"BRKH_DSP_PCIN20",
|
||||
"BRKH_DSP_BCIN4",
|
||||
"BRKH_DSP_PCIN29",
|
||||
"BRKH_DSP_PCIN35",
|
||||
"BRKH_DSP_PCIN36",
|
||||
"BRKH_DSP_PCIN37",
|
||||
"BRKH_DSP_PCIN44",
|
||||
"BRKH_DSP_BCIN14",
|
||||
"BRKH_DSP_BCIN13",
|
||||
"BRKH_DSP_PCIN4",
|
||||
"BRKH_DSP_PCIN39",
|
||||
"BRKH_DSP_PCIN19",
|
||||
"BRKH_DSP_PCIN11",
|
||||
"BRKH_DSP_ACIN0",
|
||||
"BRKH_DSP_BCIN12",
|
||||
"BRKH_DSP_PCIN46",
|
||||
"BRKH_DSP_BCIN3",
|
||||
"BRKH_DSP_ACIN26",
|
||||
"BRKH_DSP_BCIN7",
|
||||
"BRKH_DSP_PCIN0",
|
||||
"BRKH_DSP_PCIN47",
|
||||
"BRKH_DSP_PCIN17",
|
||||
"BRKH_DSP_PCIN9",
|
||||
"BRKH_DSP_ACIN20",
|
||||
"BRKH_DSP_ACIN27",
|
||||
"BRKH_DSP_ACIN13",
|
||||
"BRKH_DSP_ACIN22",
|
||||
"BRKH_DSP_ACIN28",
|
||||
"BRKH_DSP_PCIN10",
|
||||
"BRKH_DSP_MULTSIGNIN",
|
||||
"BRKH_DSP_PCIN43",
|
||||
"BRKH_DSP_ACIN24",
|
||||
"BRKH_DSP_ACIN1",
|
||||
"BRKH_DSP_BCIN6",
|
||||
"BRKH_DSP_PCIN12",
|
||||
"BRKH_DSP_PCIN31",
|
||||
"BRKH_DSP_ACIN8",
|
||||
"BRKH_DSP_BCIN0",
|
||||
"BRKH_DSP_PCIN38",
|
||||
"BRKH_DSP_PCIN40",
|
||||
"BRKH_DSP_PCIN28",
|
||||
"BRKH_DSP_ACIN5",
|
||||
"BRKH_DSP_ACIN2",
|
||||
"BRKH_DSP_ACIN20",
|
||||
"BRKH_DSP_MULTSIGNIN",
|
||||
"BRKH_DSP_PCIN1",
|
||||
"BRKH_DSP_ACIN22",
|
||||
"BRKH_DSP_ACIN14",
|
||||
"BRKH_DSP_ACIN15",
|
||||
"BRKH_DSP_BCIN1",
|
||||
"BRKH_DSP_ACIN25",
|
||||
"BRKH_DSP_PCIN24",
|
||||
"BRKH_DSP_PCIN22",
|
||||
"BRKH_DSP_ACIN10",
|
||||
"BRKH_DSP_ACIN23",
|
||||
"BRKH_DSP_PCIN42",
|
||||
"BRKH_DSP_PCIN15",
|
||||
"BRKH_DSP_ACIN9",
|
||||
"BRKH_DSP_ACIN18",
|
||||
"BRKH_DSP_PCIN28"
|
||||
"BRKH_DSP_PCIN9",
|
||||
"BRKH_DSP_BCIN16",
|
||||
"BRKH_DSP_ACIN28",
|
||||
"BRKH_DSP_ACIN27",
|
||||
"BRKH_DSP_PCIN47",
|
||||
"BRKH_DSP_PCIN45",
|
||||
"BRKH_DSP_BCIN6",
|
||||
"BRKH_DSP_PCIN34",
|
||||
"BRKH_DSP_BCIN8",
|
||||
"BRKH_DSP_PCIN18",
|
||||
"BRKH_DSP_PCIN16",
|
||||
"BRKH_DSP_PCIN3",
|
||||
"BRKH_DSP_PCIN26",
|
||||
"BRKH_DSP_PCIN7",
|
||||
"BRKH_DSP_PCIN41",
|
||||
"BRKH_DSP_PCIN21",
|
||||
"BRKH_DSP_PCIN5",
|
||||
"BRKH_DSP_PCIN14",
|
||||
"BRKH_DSP_PCIN13",
|
||||
"BRKH_DSP_ACIN12",
|
||||
"BRKH_DSP_ACIN16",
|
||||
"BRKH_DSP_BCIN17",
|
||||
"BRKH_DSP_ACIN21",
|
||||
"BRKH_DSP_ACIN4",
|
||||
"BRKH_DSP_ACIN3",
|
||||
"BRKH_DSP_BCIN9",
|
||||
"BRKH_DSP_BCIN12",
|
||||
"BRKH_DSP_ACIN17",
|
||||
"BRKH_DSP_ACIN0",
|
||||
"BRKH_DSP_ACIN7",
|
||||
"BRKH_DSP_PCIN30",
|
||||
"BRKH_DSP_ACIN11",
|
||||
"BRKH_DSP_BCIN11",
|
||||
"BRKH_DSP_PCIN6",
|
||||
"BRKH_DSP_PCIN32",
|
||||
"BRKH_DSP_PCIN17",
|
||||
"BRKH_DSP_PCIN23",
|
||||
"BRKH_DSP_PCIN8",
|
||||
"BRKH_DSP_PCIN10",
|
||||
"BRKH_DSP_PCIN25",
|
||||
"BRKH_DSP_ACIN13",
|
||||
"BRKH_DSP_PCIN2",
|
||||
"BRKH_DSP_BCIN5",
|
||||
"BRKH_DSP_ACIN19",
|
||||
"BRKH_DSP_ACIN29",
|
||||
"BRKH_DSP_PCIN11",
|
||||
"BRKH_DSP_ACIN6",
|
||||
"BRKH_DSP_PCIN33",
|
||||
"BRKH_DSP_BCIN15",
|
||||
"BRKH_DSP_CARRYCASCIN",
|
||||
"BRKH_DSP_PCIN27",
|
||||
"BRKH_DSP_BCIN10"
|
||||
],
|
||||
"tile_type": "BRKH_DSP_L",
|
||||
"sites": []
|
||||
}
|
||||
|
|
@ -1,105 +1,105 @@
|
|||
{
|
||||
"tile_type": "BRKH_DSP_R",
|
||||
"pips": {},
|
||||
"wires": [
|
||||
"BRKH_DSP_ACIN2",
|
||||
"BRKH_DSP_PCIN35",
|
||||
"BRKH_DSP_PCIN20",
|
||||
"BRKH_DSP_BCIN15",
|
||||
"BRKH_DSP_ACIN11",
|
||||
"BRKH_DSP_ACIN9",
|
||||
"BRKH_DSP_ACIN14",
|
||||
"BRKH_DSP_PCIN45",
|
||||
"BRKH_DSP_PCIN12",
|
||||
"BRKH_DSP_BCIN16",
|
||||
"BRKH_DSP_PCIN30",
|
||||
"BRKH_DSP_PCIN31",
|
||||
"BRKH_DSP_PCIN29",
|
||||
"BRKH_DSP_ACIN5",
|
||||
"BRKH_DSP_PCIN21",
|
||||
"BRKH_DSP_ACIN3",
|
||||
"BRKH_DSP_PCIN8",
|
||||
"BRKH_DSP_PCIN3",
|
||||
"BRKH_DSP_PCIN46",
|
||||
"BRKH_DSP_BCIN4",
|
||||
"BRKH_DSP_BCIN13",
|
||||
"BRKH_DSP_PCIN18",
|
||||
"BRKH_DSP_ACIN24",
|
||||
"BRKH_DSP_PCIN6",
|
||||
"BRKH_DSP_PCIN4",
|
||||
"BRKH_DSP_BCIN0",
|
||||
"BRKH_DSP_PCIN44",
|
||||
"BRKH_DSP_BCIN17",
|
||||
"BRKH_DSP_ACIN15",
|
||||
"BRKH_DSP_PCIN34",
|
||||
"BRKH_DSP_ACIN17",
|
||||
"BRKH_DSP_BCIN14",
|
||||
"BRKH_DSP_PCIN27",
|
||||
"BRKH_DSP_BCIN8",
|
||||
"BRKH_DSP_PCIN2",
|
||||
"BRKH_DSP_CARRYCASCIN",
|
||||
"BRKH_DSP_PCIN40",
|
||||
"BRKH_DSP_PCIN41",
|
||||
"BRKH_DSP_PCIN16",
|
||||
"BRKH_DSP_ACIN12",
|
||||
"BRKH_DSP_PCIN39",
|
||||
"BRKH_DSP_ACIN23",
|
||||
"BRKH_DSP_BCIN3",
|
||||
"BRKH_DSP_PCIN37",
|
||||
"BRKH_DSP_PCIN32",
|
||||
"BRKH_DSP_ACIN6",
|
||||
"BRKH_DSP_PCIN14",
|
||||
"BRKH_DSP_ACIN25",
|
||||
"BRKH_DSP_BCIN1",
|
||||
"BRKH_DSP_PCIN23",
|
||||
"BRKH_DSP_PCIN33",
|
||||
"BRKH_DSP_ACIN16",
|
||||
"BRKH_DSP_PCIN7",
|
||||
"BRKH_DSP_ACIN26",
|
||||
"BRKH_DSP_BCIN10",
|
||||
"BRKH_DSP_ACIN4",
|
||||
"BRKH_DSP_ACIN21",
|
||||
"BRKH_DSP_PCIN38",
|
||||
"BRKH_DSP_PCIN22",
|
||||
"BRKH_DSP_PCIN1",
|
||||
"BRKH_DSP_BCIN11",
|
||||
"BRKH_DSP_BCIN5",
|
||||
"BRKH_DSP_ACIN10",
|
||||
"BRKH_DSP_PCIN43",
|
||||
"BRKH_DSP_PCIN15",
|
||||
"BRKH_DSP_PCIN36",
|
||||
"BRKH_DSP_PCIN26",
|
||||
"BRKH_DSP_ACIN29",
|
||||
"BRKH_DSP_PCIN24",
|
||||
"BRKH_DSP_ACIN19",
|
||||
"BRKH_DSP_BCIN7",
|
||||
"BRKH_DSP_PCIN25",
|
||||
"BRKH_DSP_ACIN8",
|
||||
"BRKH_DSP_PCIN42",
|
||||
"BRKH_DSP_PCIN5",
|
||||
"BRKH_DSP_BCIN2",
|
||||
"BRKH_DSP_BCIN9",
|
||||
"BRKH_DSP_PCIN13",
|
||||
"BRKH_DSP_ACIN7",
|
||||
"BRKH_DSP_PCIN20",
|
||||
"BRKH_DSP_BCIN4",
|
||||
"BRKH_DSP_PCIN29",
|
||||
"BRKH_DSP_PCIN35",
|
||||
"BRKH_DSP_PCIN36",
|
||||
"BRKH_DSP_PCIN37",
|
||||
"BRKH_DSP_PCIN44",
|
||||
"BRKH_DSP_BCIN14",
|
||||
"BRKH_DSP_BCIN13",
|
||||
"BRKH_DSP_PCIN4",
|
||||
"BRKH_DSP_PCIN39",
|
||||
"BRKH_DSP_PCIN19",
|
||||
"BRKH_DSP_PCIN11",
|
||||
"BRKH_DSP_ACIN0",
|
||||
"BRKH_DSP_BCIN12",
|
||||
"BRKH_DSP_PCIN46",
|
||||
"BRKH_DSP_BCIN3",
|
||||
"BRKH_DSP_ACIN26",
|
||||
"BRKH_DSP_BCIN7",
|
||||
"BRKH_DSP_PCIN0",
|
||||
"BRKH_DSP_PCIN47",
|
||||
"BRKH_DSP_PCIN17",
|
||||
"BRKH_DSP_PCIN9",
|
||||
"BRKH_DSP_ACIN20",
|
||||
"BRKH_DSP_ACIN27",
|
||||
"BRKH_DSP_ACIN13",
|
||||
"BRKH_DSP_ACIN22",
|
||||
"BRKH_DSP_ACIN28",
|
||||
"BRKH_DSP_PCIN10",
|
||||
"BRKH_DSP_MULTSIGNIN",
|
||||
"BRKH_DSP_PCIN43",
|
||||
"BRKH_DSP_ACIN24",
|
||||
"BRKH_DSP_ACIN1",
|
||||
"BRKH_DSP_BCIN6",
|
||||
"BRKH_DSP_PCIN12",
|
||||
"BRKH_DSP_PCIN31",
|
||||
"BRKH_DSP_ACIN8",
|
||||
"BRKH_DSP_BCIN0",
|
||||
"BRKH_DSP_PCIN38",
|
||||
"BRKH_DSP_PCIN40",
|
||||
"BRKH_DSP_PCIN28",
|
||||
"BRKH_DSP_ACIN5",
|
||||
"BRKH_DSP_ACIN2",
|
||||
"BRKH_DSP_ACIN20",
|
||||
"BRKH_DSP_MULTSIGNIN",
|
||||
"BRKH_DSP_PCIN1",
|
||||
"BRKH_DSP_ACIN22",
|
||||
"BRKH_DSP_ACIN14",
|
||||
"BRKH_DSP_ACIN15",
|
||||
"BRKH_DSP_BCIN1",
|
||||
"BRKH_DSP_ACIN25",
|
||||
"BRKH_DSP_PCIN24",
|
||||
"BRKH_DSP_PCIN22",
|
||||
"BRKH_DSP_ACIN10",
|
||||
"BRKH_DSP_ACIN23",
|
||||
"BRKH_DSP_PCIN42",
|
||||
"BRKH_DSP_PCIN15",
|
||||
"BRKH_DSP_ACIN9",
|
||||
"BRKH_DSP_ACIN18",
|
||||
"BRKH_DSP_PCIN28"
|
||||
"BRKH_DSP_PCIN9",
|
||||
"BRKH_DSP_BCIN16",
|
||||
"BRKH_DSP_ACIN28",
|
||||
"BRKH_DSP_ACIN27",
|
||||
"BRKH_DSP_PCIN47",
|
||||
"BRKH_DSP_PCIN45",
|
||||
"BRKH_DSP_BCIN6",
|
||||
"BRKH_DSP_PCIN34",
|
||||
"BRKH_DSP_BCIN8",
|
||||
"BRKH_DSP_PCIN18",
|
||||
"BRKH_DSP_PCIN16",
|
||||
"BRKH_DSP_PCIN3",
|
||||
"BRKH_DSP_PCIN26",
|
||||
"BRKH_DSP_PCIN7",
|
||||
"BRKH_DSP_PCIN41",
|
||||
"BRKH_DSP_PCIN21",
|
||||
"BRKH_DSP_PCIN5",
|
||||
"BRKH_DSP_PCIN14",
|
||||
"BRKH_DSP_PCIN13",
|
||||
"BRKH_DSP_ACIN12",
|
||||
"BRKH_DSP_ACIN16",
|
||||
"BRKH_DSP_BCIN17",
|
||||
"BRKH_DSP_ACIN21",
|
||||
"BRKH_DSP_ACIN4",
|
||||
"BRKH_DSP_ACIN3",
|
||||
"BRKH_DSP_BCIN9",
|
||||
"BRKH_DSP_BCIN12",
|
||||
"BRKH_DSP_ACIN17",
|
||||
"BRKH_DSP_ACIN0",
|
||||
"BRKH_DSP_ACIN7",
|
||||
"BRKH_DSP_PCIN30",
|
||||
"BRKH_DSP_ACIN11",
|
||||
"BRKH_DSP_BCIN11",
|
||||
"BRKH_DSP_PCIN6",
|
||||
"BRKH_DSP_PCIN32",
|
||||
"BRKH_DSP_PCIN17",
|
||||
"BRKH_DSP_PCIN23",
|
||||
"BRKH_DSP_PCIN8",
|
||||
"BRKH_DSP_PCIN10",
|
||||
"BRKH_DSP_PCIN25",
|
||||
"BRKH_DSP_ACIN13",
|
||||
"BRKH_DSP_PCIN2",
|
||||
"BRKH_DSP_BCIN5",
|
||||
"BRKH_DSP_ACIN19",
|
||||
"BRKH_DSP_ACIN29",
|
||||
"BRKH_DSP_PCIN11",
|
||||
"BRKH_DSP_ACIN6",
|
||||
"BRKH_DSP_PCIN33",
|
||||
"BRKH_DSP_BCIN15",
|
||||
"BRKH_DSP_CARRYCASCIN",
|
||||
"BRKH_DSP_PCIN27",
|
||||
"BRKH_DSP_BCIN10"
|
||||
],
|
||||
"tile_type": "BRKH_DSP_R",
|
||||
"sites": []
|
||||
}
|
||||
|
|
@ -1,104 +1,104 @@
|
|||
{
|
||||
"tile_type": "BRKH_GTX",
|
||||
"pips": {
|
||||
"BRKH_GTX.BRKH_GTX_SOUTHREFCLK1_UPPER->BRKH_GTX_SOUTHREFCLK1_LOWER": {
|
||||
"dst_wire": "BRKH_GTX_SOUTHREFCLK1_LOWER",
|
||||
"can_invert": "0",
|
||||
"src_wire": "BRKH_GTX_SOUTHREFCLK1_UPPER",
|
||||
"BRKH_GTX.BRKH_GTX_REFCLK1_UPPER->BRKH_GTX_SOUTHREFCLK0_LOWER": {
|
||||
"is_directional": "1",
|
||||
"can_invert": "0",
|
||||
"src_wire": "BRKH_GTX_REFCLK1_UPPER",
|
||||
"dst_wire": "BRKH_GTX_SOUTHREFCLK0_LOWER",
|
||||
"is_pseudo": "0"
|
||||
},
|
||||
"BRKH_GTX.BRKH_GTX_REFCLK1_LOWER->BRKH_GTX_NORTHREFCLK1_UPPER": {
|
||||
"dst_wire": "BRKH_GTX_NORTHREFCLK1_UPPER",
|
||||
"is_directional": "1",
|
||||
"can_invert": "0",
|
||||
"src_wire": "BRKH_GTX_REFCLK1_LOWER",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0"
|
||||
},
|
||||
"BRKH_GTX.BRKH_GTX_NORTHREFCLK0_LOWER->BRKH_GTX_NORTHREFCLK0_UPPER": {
|
||||
"dst_wire": "BRKH_GTX_NORTHREFCLK0_UPPER",
|
||||
"can_invert": "0",
|
||||
"src_wire": "BRKH_GTX_NORTHREFCLK0_LOWER",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0"
|
||||
},
|
||||
"BRKH_GTX.BRKH_GTX_REFCLK1_LOWER->BRKH_GTX_NORTHREFCLK0_UPPER": {
|
||||
"dst_wire": "BRKH_GTX_NORTHREFCLK0_UPPER",
|
||||
"can_invert": "0",
|
||||
"src_wire": "BRKH_GTX_REFCLK1_LOWER",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0"
|
||||
},
|
||||
"BRKH_GTX.BRKH_GTX_REFCLK0_UPPER->BRKH_GTX_SOUTHREFCLK0_LOWER": {
|
||||
"dst_wire": "BRKH_GTX_SOUTHREFCLK0_LOWER",
|
||||
"can_invert": "0",
|
||||
"src_wire": "BRKH_GTX_REFCLK0_UPPER",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0"
|
||||
},
|
||||
"BRKH_GTX.BRKH_GTX_NORTHREFCLK1_LOWER->BRKH_GTX_NORTHREFCLK1_UPPER": {
|
||||
"dst_wire": "BRKH_GTX_NORTHREFCLK1_UPPER",
|
||||
"can_invert": "0",
|
||||
"src_wire": "BRKH_GTX_NORTHREFCLK1_LOWER",
|
||||
"is_pseudo": "0"
|
||||
},
|
||||
"BRKH_GTX.BRKH_GTX_SOUTHREFCLK1_UPPER->BRKH_GTX_SOUTHREFCLK1_LOWER": {
|
||||
"is_directional": "1",
|
||||
"can_invert": "0",
|
||||
"src_wire": "BRKH_GTX_SOUTHREFCLK1_UPPER",
|
||||
"dst_wire": "BRKH_GTX_SOUTHREFCLK1_LOWER",
|
||||
"is_pseudo": "0"
|
||||
},
|
||||
"BRKH_GTX.BRKH_GTX_REFCLK0_LOWER->BRKH_GTX_NORTHREFCLK0_UPPER": {
|
||||
"dst_wire": "BRKH_GTX_NORTHREFCLK0_UPPER",
|
||||
"is_directional": "1",
|
||||
"can_invert": "0",
|
||||
"src_wire": "BRKH_GTX_REFCLK0_LOWER",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0"
|
||||
},
|
||||
"BRKH_GTX.BRKH_GTX_SOUTHREFCLK0_UPPER->BRKH_GTX_SOUTHREFCLK0_LOWER": {
|
||||
"dst_wire": "BRKH_GTX_SOUTHREFCLK0_LOWER",
|
||||
"can_invert": "0",
|
||||
"src_wire": "BRKH_GTX_SOUTHREFCLK0_UPPER",
|
||||
"is_directional": "1",
|
||||
"dst_wire": "BRKH_GTX_NORTHREFCLK0_UPPER",
|
||||
"is_pseudo": "0"
|
||||
},
|
||||
"BRKH_GTX.BRKH_GTX_REFCLK1_UPPER->BRKH_GTX_SOUTHREFCLK1_LOWER": {
|
||||
"dst_wire": "BRKH_GTX_SOUTHREFCLK1_LOWER",
|
||||
"is_directional": "1",
|
||||
"can_invert": "0",
|
||||
"src_wire": "BRKH_GTX_REFCLK1_UPPER",
|
||||
"is_directional": "1",
|
||||
"dst_wire": "BRKH_GTX_SOUTHREFCLK1_LOWER",
|
||||
"is_pseudo": "0"
|
||||
},
|
||||
"BRKH_GTX.BRKH_GTX_REFCLK0_UPPER->BRKH_GTX_SOUTHREFCLK1_LOWER": {
|
||||
"dst_wire": "BRKH_GTX_SOUTHREFCLK1_LOWER",
|
||||
"is_directional": "1",
|
||||
"can_invert": "0",
|
||||
"src_wire": "BRKH_GTX_REFCLK0_UPPER",
|
||||
"is_directional": "1",
|
||||
"dst_wire": "BRKH_GTX_SOUTHREFCLK1_LOWER",
|
||||
"is_pseudo": "0"
|
||||
},
|
||||
"BRKH_GTX.BRKH_GTX_REFCLK0_LOWER->BRKH_GTX_NORTHREFCLK1_UPPER": {
|
||||
"dst_wire": "BRKH_GTX_NORTHREFCLK1_UPPER",
|
||||
"is_directional": "1",
|
||||
"can_invert": "0",
|
||||
"src_wire": "BRKH_GTX_REFCLK0_LOWER",
|
||||
"is_directional": "1",
|
||||
"dst_wire": "BRKH_GTX_NORTHREFCLK1_UPPER",
|
||||
"is_pseudo": "0"
|
||||
},
|
||||
"BRKH_GTX.BRKH_GTX_REFCLK1_UPPER->BRKH_GTX_SOUTHREFCLK0_LOWER": {
|
||||
"dst_wire": "BRKH_GTX_SOUTHREFCLK0_LOWER",
|
||||
"can_invert": "0",
|
||||
"src_wire": "BRKH_GTX_REFCLK1_UPPER",
|
||||
"BRKH_GTX.BRKH_GTX_SOUTHREFCLK0_UPPER->BRKH_GTX_SOUTHREFCLK0_LOWER": {
|
||||
"is_directional": "1",
|
||||
"can_invert": "0",
|
||||
"src_wire": "BRKH_GTX_SOUTHREFCLK0_UPPER",
|
||||
"dst_wire": "BRKH_GTX_SOUTHREFCLK0_LOWER",
|
||||
"is_pseudo": "0"
|
||||
},
|
||||
"BRKH_GTX.BRKH_GTX_REFCLK0_UPPER->BRKH_GTX_SOUTHREFCLK0_LOWER": {
|
||||
"is_directional": "1",
|
||||
"can_invert": "0",
|
||||
"src_wire": "BRKH_GTX_REFCLK0_UPPER",
|
||||
"dst_wire": "BRKH_GTX_SOUTHREFCLK0_LOWER",
|
||||
"is_pseudo": "0"
|
||||
},
|
||||
"BRKH_GTX.BRKH_GTX_NORTHREFCLK1_LOWER->BRKH_GTX_NORTHREFCLK1_UPPER": {
|
||||
"is_directional": "1",
|
||||
"can_invert": "0",
|
||||
"src_wire": "BRKH_GTX_NORTHREFCLK1_LOWER",
|
||||
"dst_wire": "BRKH_GTX_NORTHREFCLK1_UPPER",
|
||||
"is_pseudo": "0"
|
||||
},
|
||||
"BRKH_GTX.BRKH_GTX_REFCLK1_LOWER->BRKH_GTX_NORTHREFCLK0_UPPER": {
|
||||
"is_directional": "1",
|
||||
"can_invert": "0",
|
||||
"src_wire": "BRKH_GTX_REFCLK1_LOWER",
|
||||
"dst_wire": "BRKH_GTX_NORTHREFCLK0_UPPER",
|
||||
"is_pseudo": "0"
|
||||
},
|
||||
"BRKH_GTX.BRKH_GTX_NORTHREFCLK0_LOWER->BRKH_GTX_NORTHREFCLK0_UPPER": {
|
||||
"is_directional": "1",
|
||||
"can_invert": "0",
|
||||
"src_wire": "BRKH_GTX_NORTHREFCLK0_LOWER",
|
||||
"dst_wire": "BRKH_GTX_NORTHREFCLK0_UPPER",
|
||||
"is_pseudo": "0"
|
||||
}
|
||||
},
|
||||
"wires": [
|
||||
"BRKH_GTX_REFCLK0_LOWER",
|
||||
"BRKH_GTX_NORTHREFCLK1_LOWER",
|
||||
"BRKH_GTX_REFCLK0_UPPER",
|
||||
"BRKH_GTX_NORTHREFCLK1_UPPER",
|
||||
"BRKH_GTX_SOUTHREFCLK0_UPPER",
|
||||
"BRKH_GTX_SOUTHREFCLK0_LOWER",
|
||||
"BRKH_GTX_REFCLK1_LOWER",
|
||||
"BRKH_GTX_NORTHREFCLK0_UPPER",
|
||||
"BRKH_GTX_REFCLK1_UPPER",
|
||||
"BRKH_GTX_NORTHREFCLK0_LOWER",
|
||||
"BRKH_GTX_SOUTHREFCLK1_LOWER",
|
||||
"BRKH_GTX_SOUTHREFCLK0_UPPER",
|
||||
"BRKH_GTX_REFCLK0_UPPER",
|
||||
"BRKH_GTX_SOUTHREFCLK1_UPPER"
|
||||
"BRKH_GTX_SOUTHREFCLK1_UPPER",
|
||||
"BRKH_GTX_NORTHREFCLK1_LOWER",
|
||||
"BRKH_GTX_REFCLK1_UPPER",
|
||||
"BRKH_GTX_REFCLK0_LOWER"
|
||||
],
|
||||
"tile_type": "BRKH_GTX",
|
||||
"sites": []
|
||||
}
|
||||
|
|
@ -1,367 +1,367 @@
|
|||
{
|
||||
"tile_type": "BRKH_INT",
|
||||
"pips": {
|
||||
"BRKH_INT.BRKH_INT_NR1BEG2->>BRKH_INT_NR1BEG2_SLOW": {
|
||||
"dst_wire": "BRKH_INT_NR1BEG2_SLOW",
|
||||
"is_pseudo": "0",
|
||||
"src_wire": "BRKH_INT_NR1BEG2",
|
||||
"BRKH_INT.BRKH_INT_NL1BEG1->>BRKH_INT_NL1BEG1_SLOW": {
|
||||
"is_directional": "1",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRKH_INT.BRKH_INT_NR1BEG3->>BRKH_INT_NR1BEG3_SLOW": {
|
||||
"dst_wire": "BRKH_INT_NR1BEG3_SLOW",
|
||||
"is_pseudo": "0",
|
||||
"src_wire": "BRKH_INT_NR1BEG3",
|
||||
"is_directional": "1",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRKH_INT.BRKH_INT_SR1END1_SLOW->>BRKH_INT_SR1END1": {
|
||||
"dst_wire": "BRKH_INT_SR1END1",
|
||||
"is_pseudo": "0",
|
||||
"src_wire": "BRKH_INT_SR1END1_SLOW",
|
||||
"is_directional": "1",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRKH_INT.BRKH_INT_SL1END2_SLOW->>BRKH_INT_SL1END2": {
|
||||
"dst_wire": "BRKH_INT_SL1END2",
|
||||
"is_pseudo": "0",
|
||||
"src_wire": "BRKH_INT_SL1END2_SLOW",
|
||||
"is_directional": "1",
|
||||
"can_invert": "0"
|
||||
"can_invert": "0",
|
||||
"src_wire": "BRKH_INT_NL1BEG1",
|
||||
"dst_wire": "BRKH_INT_NL1BEG1_SLOW",
|
||||
"is_pseudo": "0"
|
||||
},
|
||||
"BRKH_INT.BRKH_INT_SL1END3_SLOW->>BRKH_INT_SL1END3": {
|
||||
"dst_wire": "BRKH_INT_SL1END3",
|
||||
"is_pseudo": "0",
|
||||
"is_directional": "1",
|
||||
"can_invert": "0",
|
||||
"src_wire": "BRKH_INT_SL1END3_SLOW",
|
||||
"is_directional": "1",
|
||||
"can_invert": "0"
|
||||
"dst_wire": "BRKH_INT_SL1END3",
|
||||
"is_pseudo": "0"
|
||||
},
|
||||
"BRKH_INT.BRKH_INT_NL1BEG2->>BRKH_INT_NL1BEG2_SLOW": {
|
||||
"dst_wire": "BRKH_INT_NL1BEG2_SLOW",
|
||||
"is_pseudo": "0",
|
||||
"src_wire": "BRKH_INT_NL1BEG2",
|
||||
"BRKH_INT.BRKH_INT_SR1END1_SLOW->>BRKH_INT_SR1END1": {
|
||||
"is_directional": "1",
|
||||
"can_invert": "0"
|
||||
"can_invert": "0",
|
||||
"src_wire": "BRKH_INT_SR1END1_SLOW",
|
||||
"dst_wire": "BRKH_INT_SR1END1",
|
||||
"is_pseudo": "0"
|
||||
},
|
||||
"BRKH_INT.BRKH_INT_NR1BEG0->>BRKH_INT_NR1BEG0_SLOW": {
|
||||
"dst_wire": "BRKH_INT_NR1BEG0_SLOW",
|
||||
"is_pseudo": "0",
|
||||
"src_wire": "BRKH_INT_NR1BEG0",
|
||||
"BRKH_INT.BRKH_INT_NR1BEG2->>BRKH_INT_NR1BEG2_SLOW": {
|
||||
"is_directional": "1",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRKH_INT.BRKH_INT_SL1END1_SLOW->>BRKH_INT_SL1END1": {
|
||||
"dst_wire": "BRKH_INT_SL1END1",
|
||||
"is_pseudo": "0",
|
||||
"src_wire": "BRKH_INT_SL1END1_SLOW",
|
||||
"is_directional": "1",
|
||||
"can_invert": "0"
|
||||
"can_invert": "0",
|
||||
"src_wire": "BRKH_INT_NR1BEG2",
|
||||
"dst_wire": "BRKH_INT_NR1BEG2_SLOW",
|
||||
"is_pseudo": "0"
|
||||
},
|
||||
"BRKH_INT.BRKH_INT_SL1END0_SLOW->>BRKH_INT_SL1END0": {
|
||||
"dst_wire": "BRKH_INT_SL1END0",
|
||||
"is_pseudo": "0",
|
||||
"src_wire": "BRKH_INT_SL1END0_SLOW",
|
||||
"is_directional": "1",
|
||||
"can_invert": "0"
|
||||
"can_invert": "0",
|
||||
"src_wire": "BRKH_INT_SL1END0_SLOW",
|
||||
"dst_wire": "BRKH_INT_SL1END0",
|
||||
"is_pseudo": "0"
|
||||
},
|
||||
"BRKH_INT.BRKH_INT_SL1END1_SLOW->>BRKH_INT_SL1END1": {
|
||||
"is_directional": "1",
|
||||
"can_invert": "0",
|
||||
"src_wire": "BRKH_INT_SL1END1_SLOW",
|
||||
"dst_wire": "BRKH_INT_SL1END1",
|
||||
"is_pseudo": "0"
|
||||
},
|
||||
"BRKH_INT.BRKH_INT_NR1BEG1->>BRKH_INT_NR1BEG1_SLOW": {
|
||||
"dst_wire": "BRKH_INT_NR1BEG1_SLOW",
|
||||
"is_pseudo": "0",
|
||||
"is_directional": "1",
|
||||
"can_invert": "0",
|
||||
"src_wire": "BRKH_INT_NR1BEG1",
|
||||
"is_directional": "1",
|
||||
"can_invert": "0"
|
||||
"dst_wire": "BRKH_INT_NR1BEG1_SLOW",
|
||||
"is_pseudo": "0"
|
||||
},
|
||||
"BRKH_INT.BRKH_INT_NL1BEG1->>BRKH_INT_NL1BEG1_SLOW": {
|
||||
"dst_wire": "BRKH_INT_NL1BEG1_SLOW",
|
||||
"is_pseudo": "0",
|
||||
"src_wire": "BRKH_INT_NL1BEG1",
|
||||
"BRKH_INT.BRKH_INT_NR1BEG0->>BRKH_INT_NR1BEG0_SLOW": {
|
||||
"is_directional": "1",
|
||||
"can_invert": "0"
|
||||
"can_invert": "0",
|
||||
"src_wire": "BRKH_INT_NR1BEG0",
|
||||
"dst_wire": "BRKH_INT_NR1BEG0_SLOW",
|
||||
"is_pseudo": "0"
|
||||
},
|
||||
"BRKH_INT.BRKH_INT_SR1END2_SLOW->>BRKH_INT_SR1END2": {
|
||||
"dst_wire": "BRKH_INT_SR1END2",
|
||||
"is_pseudo": "0",
|
||||
"is_directional": "1",
|
||||
"can_invert": "0",
|
||||
"src_wire": "BRKH_INT_SR1END2_SLOW",
|
||||
"is_directional": "1",
|
||||
"can_invert": "0"
|
||||
"dst_wire": "BRKH_INT_SR1END2",
|
||||
"is_pseudo": "0"
|
||||
},
|
||||
"BRKH_INT.BRKH_INT_NL1BEG0->>BRKH_INT_NL1BEG0_SLOW": {
|
||||
"dst_wire": "BRKH_INT_NL1BEG0_SLOW",
|
||||
"is_pseudo": "0",
|
||||
"src_wire": "BRKH_INT_NL1BEG0",
|
||||
"BRKH_INT.BRKH_INT_NR1BEG3->>BRKH_INT_NR1BEG3_SLOW": {
|
||||
"is_directional": "1",
|
||||
"can_invert": "0"
|
||||
"can_invert": "0",
|
||||
"src_wire": "BRKH_INT_NR1BEG3",
|
||||
"dst_wire": "BRKH_INT_NR1BEG3_SLOW",
|
||||
"is_pseudo": "0"
|
||||
},
|
||||
"BRKH_INT.BRKH_INT_SR1END3_SLOW->>BRKH_INT_SR1END3": {
|
||||
"dst_wire": "BRKH_INT_SR1END3",
|
||||
"is_pseudo": "0",
|
||||
"src_wire": "BRKH_INT_SR1END3_SLOW",
|
||||
"is_directional": "1",
|
||||
"can_invert": "0"
|
||||
"can_invert": "0",
|
||||
"src_wire": "BRKH_INT_SR1END3_SLOW",
|
||||
"dst_wire": "BRKH_INT_SR1END3",
|
||||
"is_pseudo": "0"
|
||||
},
|
||||
"BRKH_INT.BRKH_INT_SL1END2_SLOW->>BRKH_INT_SL1END2": {
|
||||
"is_directional": "1",
|
||||
"can_invert": "0",
|
||||
"src_wire": "BRKH_INT_SL1END2_SLOW",
|
||||
"dst_wire": "BRKH_INT_SL1END2",
|
||||
"is_pseudo": "0"
|
||||
},
|
||||
"BRKH_INT.BRKH_INT_NL1BEG2->>BRKH_INT_NL1BEG2_SLOW": {
|
||||
"is_directional": "1",
|
||||
"can_invert": "0",
|
||||
"src_wire": "BRKH_INT_NL1BEG2",
|
||||
"dst_wire": "BRKH_INT_NL1BEG2_SLOW",
|
||||
"is_pseudo": "0"
|
||||
},
|
||||
"BRKH_INT.BRKH_INT_NL1BEG0->>BRKH_INT_NL1BEG0_SLOW": {
|
||||
"is_directional": "1",
|
||||
"can_invert": "0",
|
||||
"src_wire": "BRKH_INT_NL1BEG0",
|
||||
"dst_wire": "BRKH_INT_NL1BEG0_SLOW",
|
||||
"is_pseudo": "0"
|
||||
}
|
||||
},
|
||||
"wires": [
|
||||
"BRKH_INT_SW2A0",
|
||||
"BRKH_INT_SS6END0",
|
||||
"BRKH_INT_SS6D1",
|
||||
"BRKH_INT_SS6END_N0_3",
|
||||
"BRKH_INT_NN2A2",
|
||||
"BRKH_INT_LV8",
|
||||
"BRKH_INT_SL1END2_SLOW",
|
||||
"BRKH_INT_SE2A1",
|
||||
"BRKH_INT_FAN_BOUNCE_S3_4",
|
||||
"BRKH_INT_NN6BEG3",
|
||||
"BRKH_INT_SW6D3",
|
||||
"BRKH_INT_NN6D2",
|
||||
"BRKH_INT_NE6C3",
|
||||
"BRKH_INT_SE6B3",
|
||||
"BRKH_INT_SL1END1",
|
||||
"BRKH_INT_NW6A0",
|
||||
"BRKH_INT_NW6C0",
|
||||
"BRKH_INT_SW6C1",
|
||||
"BRKH_INT_NR1BEG3_SLOW",
|
||||
"BRKH_INT_SS2END1",
|
||||
"BRKH_INT_SR1END1_SLOW",
|
||||
"BRKH_INT_LVB_L4",
|
||||
"BRKH_INT_SW6END3",
|
||||
"BRKH_INT_L_LV5",
|
||||
"BRKH_INT_LVB_L3",
|
||||
"BRKH_INT_SR1END2_SLOW",
|
||||
"BRKH_INT_L_LV12",
|
||||
"BRKH_INT_SE6D1",
|
||||
"BRKH_INT_SE6C1",
|
||||
"BRKH_INT_SE6C0",
|
||||
"BRKH_INT_NW6B0",
|
||||
"BRKH_INT_NE6A1",
|
||||
"BRKH_INT_SL1END0",
|
||||
"BRKH_INT_SW6C2",
|
||||
"BRKH_INT_NE6D0",
|
||||
"BRKH_INT_EL1BEG3",
|
||||
"BRKH_INT_NW6D0",
|
||||
"BRKH_INT_SE6E2",
|
||||
"BRKH_INT_SL1END3",
|
||||
"BRKH_INT_WR1BEG_S0",
|
||||
"BRKH_INT_SW2END3",
|
||||
"BRKH_INT_SS6A1",
|
||||
"BRKH_INT_LVB_L2",
|
||||
"BRKH_INT_LVB_L9",
|
||||
"BRKH_INT_LV9",
|
||||
"BRKH_INT_FAN_BOUNCE_S3_0",
|
||||
"BRKH_INT_L_LV8",
|
||||
"BRKH_INT_SS2END2",
|
||||
"BRKH_INT_SS6E1",
|
||||
"BRKH_INT_NW6B1",
|
||||
"BRKH_INT_NN6E3",
|
||||
"BRKH_INT_NN6A0",
|
||||
"BRKH_INT_SE6C2",
|
||||
"BRKH_INT_SW6D2",
|
||||
"BRKH_INT_LV12",
|
||||
"BRKH_INT_L_LV0",
|
||||
"BRKH_INT_NE6B0",
|
||||
"BRKH_INT_BYP_BOUNCE2",
|
||||
"BRKH_INT_SW6B2",
|
||||
"BRKH_INT_SE6B2",
|
||||
"BRKH_INT_LVB11",
|
||||
"BRKH_INT_NL1END_S3_0",
|
||||
"BRKH_INT_NR1BEG3",
|
||||
"BRKH_INT_NE2BEG2",
|
||||
"BRKH_INT_LVB6",
|
||||
"BRKH_INT_NE6B3",
|
||||
"BRKH_INT_NN6D3",
|
||||
"BRKH_INT_L_LV3",
|
||||
"BRKH_INT_NR1BEG1",
|
||||
"BRKH_INT_NN6BEG1",
|
||||
"BRKH_INT_SW6B3",
|
||||
"BRKH_INT_SS6A3",
|
||||
"BRKH_INT_LVB7",
|
||||
"BRKH_INT_L_LV6",
|
||||
"BRKH_INT_SE6E3",
|
||||
"BRKH_INT_SL1END1_SLOW",
|
||||
"BRKH_INT_NW6D1",
|
||||
"BRKH_INT_NN2A0",
|
||||
"BRKH_INT_NN2A1",
|
||||
"BRKH_INT_SS6D3",
|
||||
"BRKH_INT_SS6B3",
|
||||
"BRKH_INT_NE6C0",
|
||||
"BRKH_INT_SR1END1",
|
||||
"BRKH_INT_SW2A1",
|
||||
"BRKH_INT_NE2END_S3_0",
|
||||
"BRKH_INT_NL1BEG0",
|
||||
"BRKH_INT_NN6BEG0",
|
||||
"BRKH_INT_NN6A3",
|
||||
"BRKH_INT_L_LV2",
|
||||
"BRKH_INT_NE6D3",
|
||||
"BRKH_INT_NE6B1",
|
||||
"BRKH_INT_NN2BEG3",
|
||||
"BRKH_INT_LVB_L6",
|
||||
"BRKH_INT_L_LV10",
|
||||
"BRKH_INT_NE2BEG3",
|
||||
"BRKH_INT_ER1BEG_S0",
|
||||
"BRKH_INT_NN6C1",
|
||||
"BRKH_INT_NE6A2",
|
||||
"BRKH_INT_LV2",
|
||||
"BRKH_INT_FAN_BOUNCE_S3_6",
|
||||
"BRKH_INT_SW6D1",
|
||||
"BRKH_INT_NN6C3",
|
||||
"BRKH_INT_EL1END_S3_0",
|
||||
"BRKH_INT_LVB_L1",
|
||||
"BRKH_INT_NN6C2",
|
||||
"BRKH_INT_NN6B2",
|
||||
"BRKH_INT_SE2A2",
|
||||
"BRKH_INT_SS2A0",
|
||||
"BRKH_INT_SL1END0_SLOW",
|
||||
"BRKH_INT_LVB5",
|
||||
"BRKH_INT_BYP_BOUNCE3",
|
||||
"BRKH_INT_NW6A2",
|
||||
"BRKH_INT_NE6A0",
|
||||
"BRKH_INT_SS6END3",
|
||||
"BRKH_INT_NE2BEG0",
|
||||
"BRKH_INT_LV16",
|
||||
"BRKH_INT_SS6C2",
|
||||
"BRKH_INT_SS6C3",
|
||||
"BRKH_INT_LVB_L12",
|
||||
"BRKH_INT_NW6END_S0_0",
|
||||
"BRKH_INT_LV11",
|
||||
"BRKH_INT_SS6A2",
|
||||
"BRKH_INT_NR1BEG2_SLOW",
|
||||
"BRKH_INT_LV6",
|
||||
"BRKH_INT_SW6E1",
|
||||
"BRKH_INT_SW6B0",
|
||||
"BRKH_INT_SW6B1",
|
||||
"BRKH_INT_LVB1",
|
||||
"BRKH_INT_WL1BEG3",
|
||||
"BRKH_INT_LVB12",
|
||||
"BRKH_INT_L_LV16",
|
||||
"BRKH_INT_NL1BEG2",
|
||||
"BRKH_INT_SS2END_N0_3",
|
||||
"BRKH_INT_BYP_BOUNCE6",
|
||||
"BRKH_INT_NE6D2",
|
||||
"BRKH_INT_NE6C1",
|
||||
"BRKH_INT_SL1END2",
|
||||
"BRKH_INT_SS6B0",
|
||||
"BRKH_INT_LV0",
|
||||
"BRKH_INT_NW6B3",
|
||||
"BRKH_INT_NN6B0",
|
||||
"BRKH_INT_LV15",
|
||||
"BRKH_INT_NN6E2",
|
||||
"BRKH_INT_SS2A2",
|
||||
"BRKH_INT_BYP_BOUNCE7",
|
||||
"BRKH_INT_SS2END3",
|
||||
"BRKH_INT_NN2BEG2",
|
||||
"BRKH_INT_LVB_L11",
|
||||
"BRKH_INT_NR1BEG0",
|
||||
"BRKH_INT_L_LV11",
|
||||
"BRKH_INT_NE6D1",
|
||||
"BRKH_INT_L_LV15",
|
||||
"BRKH_INT_SS6E0",
|
||||
"BRKH_INT_SS6E2",
|
||||
"BRKH_INT_SE6D0",
|
||||
"BRKH_INT_NW2BEG2",
|
||||
"BRKH_INT_SS6D2",
|
||||
"BRKH_INT_LV10",
|
||||
"BRKH_INT_NN2BEG0",
|
||||
"BRKH_INT_WW4END_S0_0",
|
||||
"BRKH_INT_NN6C0",
|
||||
"BRKH_INT_SE6B1",
|
||||
"BRKH_INT_NR1BEG1_SLOW",
|
||||
"BRKH_INT_FAN_BOUNCE_S3_2",
|
||||
"BRKH_INT_NW6B2",
|
||||
"BRKH_INT_L_LV7",
|
||||
"BRKH_INT_LVB_L7",
|
||||
"BRKH_INT_LVB4",
|
||||
"BRKH_INT_NW6A1",
|
||||
"BRKH_INT_SS6B2",
|
||||
"BRKH_INT_WW2END3",
|
||||
"BRKH_INT_WR1END_S1_0",
|
||||
"BRKH_INT_NW2BEG1",
|
||||
"BRKH_INT_LV5",
|
||||
"BRKH_INT_LV13",
|
||||
"BRKH_INT_NN6END_S1_0",
|
||||
"BRKH_INT_SE6E1",
|
||||
"BRKH_INT_NN6E0",
|
||||
"BRKH_INT_LVB2",
|
||||
"BRKH_INT_NE6B2",
|
||||
"BRKH_INT_SE2A0",
|
||||
"BRKH_INT_NN6BEG2",
|
||||
"BRKH_INT_SE6D3",
|
||||
"BRKH_INT_NW6A3",
|
||||
"BRKH_INT_SS6END1",
|
||||
"BRKH_INT_L_LV13",
|
||||
"BRKH_INT_NL1BEG0_SLOW",
|
||||
"BRKH_INT_SS6C0",
|
||||
"BRKH_INT_SS6C1",
|
||||
"BRKH_INT_NN6B3",
|
||||
"BRKH_INT_SW6C3",
|
||||
"BRKH_INT_NN2A3",
|
||||
"BRKH_INT_SE6C3",
|
||||
"BRKH_INT_LVB_L5",
|
||||
"BRKH_INT_LV7",
|
||||
"BRKH_INT_SE6D2",
|
||||
"BRKH_INT_NR1BEG0_SLOW",
|
||||
"BRKH_INT_WL1END3",
|
||||
"BRKH_INT_NE6C2",
|
||||
"BRKH_INT_NW6C1",
|
||||
"BRKH_INT_SS6E3",
|
||||
"BRKH_INT_LVB8",
|
||||
"BRKH_INT_LVB10",
|
||||
"BRKH_INT_SR1END_N3_3",
|
||||
"BRKH_INT_LV14",
|
||||
"BRKH_INT_NW2BEG3",
|
||||
"BRKH_INT_L_LV4",
|
||||
"BRKH_INT_L_LV1",
|
||||
"BRKH_INT_LV1",
|
||||
"BRKH_INT_LV3",
|
||||
"BRKH_INT_SS6D0",
|
||||
"BRKH_INT_SE6B0",
|
||||
"BRKH_INT_NN6B1",
|
||||
"BRKH_INT_SR1END2",
|
||||
"BRKH_INT_SW2A3",
|
||||
"BRKH_INT_LV4",
|
||||
"BRKH_INT_SW2A2",
|
||||
"BRKH_INT_NN6E1",
|
||||
"BRKH_INT_NW2END_S0_0",
|
||||
"BRKH_INT_SL1END3_SLOW",
|
||||
"BRKH_INT_NR1BEG2",
|
||||
"BRKH_INT_SW6E2",
|
||||
"BRKH_INT_SE6E0",
|
||||
"BRKH_INT_NN6A1",
|
||||
"BRKH_INT_NL1BEG1",
|
||||
"BRKH_INT_NW6D3",
|
||||
"BRKH_INT_L_LV17",
|
||||
"BRKH_INT_SS6A0",
|
||||
"BRKH_INT_LVB9",
|
||||
"BRKH_INT_LV17",
|
||||
"BRKH_INT_NL1BEG2_SLOW",
|
||||
"BRKH_INT_SE2A3",
|
||||
"BRKH_INT_L_LV9",
|
||||
"BRKH_INT_NN6A2",
|
||||
"BRKH_INT_SW6E3",
|
||||
"BRKH_INT_ER1END3",
|
||||
"BRKH_INT_SW6E0",
|
||||
"BRKH_INT_NN2BEG1",
|
||||
"BRKH_INT_LVB3",
|
||||
"BRKH_INT_NW2BEG0",
|
||||
"BRKH_INT_SS2END0",
|
||||
"BRKH_INT_NW6C3",
|
||||
"BRKH_INT_NN2END_S2_0",
|
||||
"BRKH_INT_SW6D0",
|
||||
"BRKH_INT_NN6D0",
|
||||
"BRKH_INT_L_LV14",
|
||||
"BRKH_INT_LVB_L10",
|
||||
"BRKH_INT_SR1END3",
|
||||
"BRKH_INT_SS6END1",
|
||||
"BRKH_INT_SE6B2",
|
||||
"BRKH_INT_LV9",
|
||||
"BRKH_INT_WW4END_S0_0",
|
||||
"BRKH_INT_LVB4",
|
||||
"BRKH_INT_NW6D3",
|
||||
"BRKH_INT_NN6D2",
|
||||
"BRKH_INT_NL1BEG2",
|
||||
"BRKH_INT_NR1BEG3_SLOW",
|
||||
"BRKH_INT_NL1BEG1",
|
||||
"BRKH_INT_L_LV16",
|
||||
"BRKH_INT_SS6D3",
|
||||
"BRKH_INT_NE6C1",
|
||||
"BRKH_INT_LV13",
|
||||
"BRKH_INT_LV11",
|
||||
"BRKH_INT_SS6E3",
|
||||
"BRKH_INT_NR1BEG3",
|
||||
"BRKH_INT_NW6D0",
|
||||
"BRKH_INT_SE6B3",
|
||||
"BRKH_INT_L_LV17",
|
||||
"BRKH_INT_FAN_BOUNCE_S3_6",
|
||||
"BRKH_INT_NE6C0",
|
||||
"BRKH_INT_SS6C3",
|
||||
"BRKH_INT_SS2END1",
|
||||
"BRKH_INT_WR1BEG_S0",
|
||||
"BRKH_INT_NL1BEG0_SLOW",
|
||||
"BRKH_INT_BYP_BOUNCE6",
|
||||
"BRKH_INT_SS6E2",
|
||||
"BRKH_INT_SW6E2",
|
||||
"BRKH_INT_LVB_L1",
|
||||
"BRKH_INT_SE6B1",
|
||||
"BRKH_INT_SS6A2",
|
||||
"BRKH_INT_L_LV11",
|
||||
"BRKH_INT_LV12",
|
||||
"BRKH_INT_WL1BEG3",
|
||||
"BRKH_INT_FAN_BOUNCE_S3_0",
|
||||
"BRKH_INT_LV2",
|
||||
"BRKH_INT_WR1END_S1_0",
|
||||
"BRKH_INT_NR1BEG0",
|
||||
"BRKH_INT_LV4",
|
||||
"BRKH_INT_SS6C1",
|
||||
"BRKH_INT_NW2END_S0_0",
|
||||
"BRKH_INT_NN2BEG2",
|
||||
"BRKH_INT_NN6C3",
|
||||
"BRKH_INT_SS6A3",
|
||||
"BRKH_INT_LVB_L9",
|
||||
"BRKH_INT_L_LV8",
|
||||
"BRKH_INT_NW6C0",
|
||||
"BRKH_INT_SW6END3",
|
||||
"BRKH_INT_SS6END0",
|
||||
"BRKH_INT_NE6D2",
|
||||
"BRKH_INT_NL1BEG1_SLOW",
|
||||
"BRKH_INT_SS2A1",
|
||||
"BRKH_INT_LVB_L8",
|
||||
"BRKH_INT_NN6D1",
|
||||
"BRKH_INT_SS6END2",
|
||||
"BRKH_INT_SS6B1",
|
||||
"BRKH_INT_NW6C2",
|
||||
"BRKH_INT_NW6D2",
|
||||
"BRKH_INT_NN6A2",
|
||||
"BRKH_INT_NR1BEG1",
|
||||
"BRKH_INT_SW6D0",
|
||||
"BRKH_INT_SS2END_N0_3",
|
||||
"BRKH_INT_SS2END2",
|
||||
"BRKH_INT_LVB_L10",
|
||||
"BRKH_INT_SW2A2",
|
||||
"BRKH_INT_L_LV15",
|
||||
"BRKH_INT_SL1END2_SLOW",
|
||||
"BRKH_INT_SR1END3_SLOW",
|
||||
"BRKH_INT_NN6B3",
|
||||
"BRKH_INT_SW6E1",
|
||||
"BRKH_INT_SE6C3",
|
||||
"BRKH_INT_NN6A0",
|
||||
"BRKH_INT_NN6B1",
|
||||
"BRKH_INT_NN6E0",
|
||||
"BRKH_INT_NN6D3",
|
||||
"BRKH_INT_SE2A2",
|
||||
"BRKH_INT_NN6C1",
|
||||
"BRKH_INT_SS2END0",
|
||||
"BRKH_INT_NN6E3",
|
||||
"BRKH_INT_SL1END3",
|
||||
"BRKH_INT_NW6B2",
|
||||
"BRKH_INT_NL1END_S3_0",
|
||||
"BRKH_INT_L_LV7",
|
||||
"BRKH_INT_SL1END0",
|
||||
"BRKH_INT_LVB_L7",
|
||||
"BRKH_INT_SS6B3",
|
||||
"BRKH_INT_NE6B1",
|
||||
"BRKH_INT_NN2A1",
|
||||
"BRKH_INT_SS6E0",
|
||||
"BRKH_INT_SE6E2",
|
||||
"BRKH_INT_ER1BEG_S0",
|
||||
"BRKH_INT_SS6END2",
|
||||
"BRKH_INT_SS2A1",
|
||||
"BRKH_INT_LV10",
|
||||
"BRKH_INT_NN6BEG1",
|
||||
"BRKH_INT_NR1BEG1_SLOW",
|
||||
"BRKH_INT_SS2END3",
|
||||
"BRKH_INT_SR1END2",
|
||||
"BRKH_INT_LVB5",
|
||||
"BRKH_INT_NN6BEG2",
|
||||
"BRKH_INT_NE6A2",
|
||||
"BRKH_INT_EL1BEG3",
|
||||
"BRKH_INT_NN6B2",
|
||||
"BRKH_INT_NE6A0",
|
||||
"BRKH_INT_SR1END2_SLOW",
|
||||
"BRKH_INT_LVB_L4",
|
||||
"BRKH_INT_L_LV3",
|
||||
"BRKH_INT_NE6A1",
|
||||
"BRKH_INT_NW6C1",
|
||||
"BRKH_INT_SS6A1",
|
||||
"BRKH_INT_LV17",
|
||||
"BRKH_INT_SR1END_N3_3",
|
||||
"BRKH_INT_NW6C3",
|
||||
"BRKH_INT_NW2BEG0",
|
||||
"BRKH_INT_NW6A2",
|
||||
"BRKH_INT_NL1BEG0",
|
||||
"BRKH_INT_SS6END3",
|
||||
"BRKH_INT_SS6A0",
|
||||
"BRKH_INT_SE6D1",
|
||||
"BRKH_INT_SL1END1",
|
||||
"BRKH_INT_LV0",
|
||||
"BRKH_INT_SL1END3_SLOW",
|
||||
"BRKH_INT_LVB6",
|
||||
"BRKH_INT_NW2BEG1",
|
||||
"BRKH_INT_SE6D0",
|
||||
"BRKH_INT_NN6A1",
|
||||
"BRKH_INT_SE6C0",
|
||||
"BRKH_INT_SR1END1",
|
||||
"BRKH_INT_NN6B0",
|
||||
"BRKH_INT_FAN_BOUNCE_S3_2",
|
||||
"BRKH_INT_NW6B1",
|
||||
"BRKH_INT_NE6C2",
|
||||
"BRKH_INT_WL1END3",
|
||||
"BRKH_INT_EL1END_S3_0",
|
||||
"BRKH_INT_L_LV6",
|
||||
"BRKH_INT_NN2A3",
|
||||
"BRKH_INT_LV1",
|
||||
"BRKH_INT_LV8",
|
||||
"BRKH_INT_NE6B3",
|
||||
"BRKH_INT_SR1END1_SLOW",
|
||||
"BRKH_INT_NE6D3",
|
||||
"BRKH_INT_SS6END_N0_3",
|
||||
"BRKH_INT_NN6D0",
|
||||
"BRKH_INT_LVB_L2",
|
||||
"BRKH_INT_SW6D1",
|
||||
"BRKH_INT_SS2A3",
|
||||
"BRKH_INT_NE6A3",
|
||||
"BRKH_INT_SS2A2",
|
||||
"BRKH_INT_NR1BEG0_SLOW",
|
||||
"BRKH_INT_SL1END1_SLOW",
|
||||
"BRKH_INT_NE6D1",
|
||||
"BRKH_INT_SE2A0",
|
||||
"BRKH_INT_SE2A1",
|
||||
"BRKH_INT_L_LV9",
|
||||
"BRKH_INT_SS6B2",
|
||||
"BRKH_INT_LVB_L5",
|
||||
"BRKH_INT_L_LV10",
|
||||
"BRKH_INT_NE6D0",
|
||||
"BRKH_INT_LVB9",
|
||||
"BRKH_INT_SS6E1",
|
||||
"BRKH_INT_LVB2",
|
||||
"BRKH_INT_LVB8",
|
||||
"BRKH_INT_LVB11",
|
||||
"BRKH_INT_NN2A2",
|
||||
"BRKH_INT_SL1END0_SLOW",
|
||||
"BRKH_INT_NN6BEG0",
|
||||
"BRKH_INT_SW6C2",
|
||||
"BRKH_INT_NN6BEG3",
|
||||
"BRKH_INT_L_LV2",
|
||||
"BRKH_INT_FAN_BOUNCE_S3_4",
|
||||
"BRKH_INT_SW2A3",
|
||||
"BRKH_INT_NE6B0",
|
||||
"BRKH_INT_LVB1",
|
||||
"BRKH_INT_NW6C2",
|
||||
"BRKH_INT_BYP_BOUNCE2",
|
||||
"BRKH_INT_SL1END2",
|
||||
"BRKH_INT_LV7",
|
||||
"BRKH_INT_NN2A0",
|
||||
"BRKH_INT_NW6END_S0_0",
|
||||
"BRKH_INT_SW6C3",
|
||||
"BRKH_INT_SW6B0",
|
||||
"BRKH_INT_NE2BEG3",
|
||||
"BRKH_INT_SW6C0",
|
||||
"BRKH_INT_NE2BEG1"
|
||||
"BRKH_INT_SS6B1",
|
||||
"BRKH_INT_L_LV12",
|
||||
"BRKH_INT_NW2BEG3",
|
||||
"BRKH_INT_LVB10",
|
||||
"BRKH_INT_LV6",
|
||||
"BRKH_INT_SE6C1",
|
||||
"BRKH_INT_LVB12",
|
||||
"BRKH_INT_NW6A1",
|
||||
"BRKH_INT_SS6B0",
|
||||
"BRKH_INT_LV14",
|
||||
"BRKH_INT_NN6C2",
|
||||
"BRKH_INT_SS6D0",
|
||||
"BRKH_INT_LVB3",
|
||||
"BRKH_INT_NN2END_S2_0",
|
||||
"BRKH_INT_NR1BEG2_SLOW",
|
||||
"BRKH_INT_NN2BEG0",
|
||||
"BRKH_INT_NW6A3",
|
||||
"BRKH_INT_NN6END_S1_0",
|
||||
"BRKH_INT_SE2A3",
|
||||
"BRKH_INT_L_LV14",
|
||||
"BRKH_INT_NE6A3",
|
||||
"BRKH_INT_NE2BEG2",
|
||||
"BRKH_INT_NN6C0",
|
||||
"BRKH_INT_SS6C0",
|
||||
"BRKH_INT_NW6D2",
|
||||
"BRKH_INT_SE6D2",
|
||||
"BRKH_INT_NN6E2",
|
||||
"BRKH_INT_NW6B3",
|
||||
"BRKH_INT_SW6B2",
|
||||
"BRKH_INT_LVB_L8",
|
||||
"BRKH_INT_SE6C2",
|
||||
"BRKH_INT_L_LV5",
|
||||
"BRKH_INT_NN6D1",
|
||||
"BRKH_INT_LVB_L11",
|
||||
"BRKH_INT_SW6B3",
|
||||
"BRKH_INT_SW6B1",
|
||||
"BRKH_INT_NN2BEG3",
|
||||
"BRKH_INT_BYP_BOUNCE7",
|
||||
"BRKH_INT_NW6D1",
|
||||
"BRKH_INT_SW6D3",
|
||||
"BRKH_INT_SW6C1",
|
||||
"BRKH_INT_SW6E0",
|
||||
"BRKH_INT_SS6D2",
|
||||
"BRKH_INT_SW2A1",
|
||||
"BRKH_INT_L_LV13",
|
||||
"BRKH_INT_SE6E3",
|
||||
"BRKH_INT_LVB7",
|
||||
"BRKH_INT_SW2A0",
|
||||
"BRKH_INT_SE6E1",
|
||||
"BRKH_INT_BYP_BOUNCE3",
|
||||
"BRKH_INT_NE2BEG0",
|
||||
"BRKH_INT_ER1END3",
|
||||
"BRKH_INT_SR1END3",
|
||||
"BRKH_INT_LV5",
|
||||
"BRKH_INT_L_LV4",
|
||||
"BRKH_INT_NE6C3",
|
||||
"BRKH_INT_NN6E1",
|
||||
"BRKH_INT_SW6D2",
|
||||
"BRKH_INT_SE6E0",
|
||||
"BRKH_INT_NN2BEG1",
|
||||
"BRKH_INT_LVB_L3",
|
||||
"BRKH_INT_LV15",
|
||||
"BRKH_INT_NE2END_S3_0",
|
||||
"BRKH_INT_SW2END3",
|
||||
"BRKH_INT_WW2END3",
|
||||
"BRKH_INT_LV16",
|
||||
"BRKH_INT_SS2A0",
|
||||
"BRKH_INT_NR1BEG2",
|
||||
"BRKH_INT_SW6E3",
|
||||
"BRKH_INT_NW6A0",
|
||||
"BRKH_INT_SS6D1",
|
||||
"BRKH_INT_LVB_L12",
|
||||
"BRKH_INT_NE2BEG1",
|
||||
"BRKH_INT_SS6C2",
|
||||
"BRKH_INT_L_LV1",
|
||||
"BRKH_INT_SE6B0",
|
||||
"BRKH_INT_NW2BEG2",
|
||||
"BRKH_INT_LVB_L6",
|
||||
"BRKH_INT_NE6B2",
|
||||
"BRKH_INT_L_LV0",
|
||||
"BRKH_INT_NN6A3",
|
||||
"BRKH_INT_LV3",
|
||||
"BRKH_INT_SE6D3",
|
||||
"BRKH_INT_NW6B0"
|
||||
],
|
||||
"tile_type": "BRKH_INT",
|
||||
"sites": []
|
||||
}
|
||||
|
|
@ -1,124 +1,124 @@
|
|||
{
|
||||
"tile_type": "BRKH_TERM_INT",
|
||||
"pips": {},
|
||||
"wires": [
|
||||
"T_TERM_UTURN_INT_LVB_L0",
|
||||
"T_TERM_UTURN_INT_SS6E2",
|
||||
"T_TERM_UTURN_INT_SS6A2",
|
||||
"T_TERM_UTURN_INT_SR1END2_SLOW",
|
||||
"T_TERM_UTURN_INT_SS6C2",
|
||||
"T_TERM_UTURN_INT_SE2A3",
|
||||
"T_TERM_UTURN_INT_SW6E3",
|
||||
"T_TERM_UTURN_INT_FAN_BOUNCE_S3_4",
|
||||
"T_TERM_UTURN_INT_SS6B0",
|
||||
"T_TERM_UTURN_INT_FAN_BOUNCE_S3_2",
|
||||
"T_TERM_UTURN_INT_LV_L16",
|
||||
"T_TERM_UTURN_INT_SS6C0",
|
||||
"T_TERM_UTURN_INT_SS6D3",
|
||||
"T_TERM_UTURN_INT_SW6B2",
|
||||
"T_TERM_UTURN_INT_LV_L7",
|
||||
"T_TERM_INT_UTURN_LV_R9",
|
||||
"T_TERM_UTURN_INT_SW2A3",
|
||||
"T_TERM_UTURN_INT_SS6END1",
|
||||
"T_TERM_UTURN_INT_SS6B1",
|
||||
"T_TERM_UTURN_INT_SS6C1",
|
||||
"T_TERM_UTURN_INT_SS6B3",
|
||||
"T_TERM_UTURN_INT_SE6E0",
|
||||
"T_TERM_UTURN_INT_SW2A0",
|
||||
"T_TERM_UTURN_INT_SW6E0",
|
||||
"T_TERM_INT_UTURN_LV_R16",
|
||||
"T_TERM_UTURN_INT_SE2A2",
|
||||
"T_TERM_UTURN_INT_SE6D2",
|
||||
"T_TERM_UTURN_INT_LVB4",
|
||||
"T_TERM_UTURN_INT_SS6END0",
|
||||
"T_TERM_INT_UTURN_LV_R3",
|
||||
"T_TERM_UTURN_INT_LVB_L3",
|
||||
"T_TERM_UTURN_INT_SR1END3_SLOW",
|
||||
"T_TERM_UTURN_INT_SW2A1",
|
||||
"T_TERM_INT_UTURN_LV_R6",
|
||||
"T_TERM_UTURN_INT_SE6B3",
|
||||
"T_TERM_UTURN_INT_LV_L5",
|
||||
"T_TERM_UTURN_INT_SS6END2",
|
||||
"T_TERM_UTURN_INT_LVB5",
|
||||
"T_TERM_UTURN_INT_SS6C3",
|
||||
"T_TERM_UTURN_INT_FAN_BOUNCE_S3_0",
|
||||
"T_TERM_UTURN_INT_LVB_L2",
|
||||
"T_TERM_INT_UTURN_LV_R17",
|
||||
"T_TERM_UTURN_INT_SE6C2",
|
||||
"T_TERM_UTURN_INT_FAN_BOUNCE_S3_6",
|
||||
"T_TERM_UTURN_INT_SS6D0",
|
||||
"T_TERM_UTURN_INT_LV_L3",
|
||||
"T_TERM_UTURN_INT_SS2A0",
|
||||
"T_TERM_UTURN_INT_SW2A2",
|
||||
"T_TERM_UTURN_INT_LV_L17",
|
||||
"T_TERM_UTURN_INT_SR1END1_SLOW",
|
||||
"T_TERM_UTURN_INT_LV_L4",
|
||||
"T_TERM_UTURN_INT_WR1BEG_S0",
|
||||
"T_TERM_UTURN_INT_SW6D2",
|
||||
"T_TERM_UTURN_INT_LVB0",
|
||||
"T_TERM_UTURN_INT_SW6C0",
|
||||
"T_TERM_UTURN_INT_SW6E1",
|
||||
"T_TERM_UTURN_INT_SW6D0",
|
||||
"T_TERM_UTURN_INT_SS6A0",
|
||||
"T_TERM_UTURN_INT_SW6C3",
|
||||
"T_TERM_UTURN_INT_SL1END0_SLOW",
|
||||
"T_TERM_UTURN_INT_SS6D1",
|
||||
"T_TERM_UTURN_INT_SE2A0",
|
||||
"T_TERM_UTURN_INT_SS2A2",
|
||||
"T_TERM_UTURN_INT_SW6D1",
|
||||
"T_TERM_UTURN_INT_SS6A1",
|
||||
"T_TERM_UTURN_INT_SS6E3",
|
||||
"T_TERM_UTURN_INT_LV_L9",
|
||||
"T_TERM_UTURN_INT_SS6A3",
|
||||
"T_TERM_UTURN_INT_SW6C1",
|
||||
"T_TERM_UTURN_INT_SR1END2_SLOW",
|
||||
"T_TERM_UTURN_INT_SL1END3_SLOW",
|
||||
"T_TERM_UTURN_INT_SS2END3",
|
||||
"T_TERM_UTURN_INT_LV_L2",
|
||||
"T_TERM_UTURN_INT_SS2END0",
|
||||
"T_TERM_UTURN_INT_ER1BEG_S0",
|
||||
"T_TERM_UTURN_INT_LV_L6",
|
||||
"T_TERM_UTURN_INT_LVB1",
|
||||
"T_TERM_UTURN_INT_SE6B1",
|
||||
"T_TERM_UTURN_INT_FAN_BOUNCE_S3_6",
|
||||
"T_TERM_INT_UTURN_LV_R16",
|
||||
"T_TERM_UTURN_INT_SE2A2",
|
||||
"T_TERM_UTURN_INT_SW6B0",
|
||||
"T_TERM_UTURN_INT_LVB_L4",
|
||||
"T_TERM_UTURN_INT_SL1END2_SLOW",
|
||||
"T_TERM_UTURN_INT_SE6E2",
|
||||
"T_TERM_UTURN_INT_WR1END_S1_0",
|
||||
"T_TERM_UTURN_INT_LVB2",
|
||||
"T_TERM_UTURN_INT_SL1END1_SLOW",
|
||||
"T_TERM_UTURN_INT_SS6E0",
|
||||
"T_TERM_UTURN_INT_SW6B1",
|
||||
"T_TERM_UTURN_INT_ER1END3",
|
||||
"T_TERM_INT_UTURN_LV_R4",
|
||||
"T_TERM_INT_UTURN_LV_R5",
|
||||
"T_TERM_UTURN_INT_SS6E1",
|
||||
"T_TERM_UTURN_INT_SW6B3",
|
||||
"T_TERM_UTURN_INT_SE6E1",
|
||||
"T_TERM_UTURN_INT_SW6B0",
|
||||
"T_TERM_UTURN_INT_SS6END3",
|
||||
"T_TERM_UTURN_INT_LVB_L1",
|
||||
"T_TERM_UTURN_INT_LVB_L5",
|
||||
"T_TERM_UTURN_INT_SS6B2",
|
||||
"T_TERM_UTURN_INT_SS6D2",
|
||||
"T_TERM_INT_UTURN_LV_R2",
|
||||
"T_TERM_UTURN_INT_SE6B2",
|
||||
"T_TERM_UTURN_INT_SE6B0",
|
||||
"T_TERM_UTURN_INT_SW6D3",
|
||||
"T_TERM_UTURN_INT_SE6D1",
|
||||
"T_TERM_UTURN_INT_SS2A1",
|
||||
"T_TERM_UTURN_INT_SE6D0",
|
||||
"T_TERM_UTURN_INT_SE6D3",
|
||||
"T_TERM_UTURN_INT_SS2END2",
|
||||
"T_TERM_UTURN_INT_SE6C3",
|
||||
"T_TERM_UTURN_INT_SE6C0",
|
||||
"T_TERM_UTURN_INT_SS2A3",
|
||||
"T_TERM_INT_UTURN_LV_R7",
|
||||
"T_TERM_UTURN_INT_LVB3",
|
||||
"T_TERM_UTURN_INT_SE6E3",
|
||||
"T_TERM_UTURN_INT_SW6E2",
|
||||
"T_TERM_UTURN_INT_SW2A2",
|
||||
"T_TERM_UTURN_INT_SS6E3",
|
||||
"T_TERM_UTURN_INT_LVB0",
|
||||
"T_TERM_UTURN_INT_SE2A1",
|
||||
"T_TERM_UTURN_INT_SS2END1",
|
||||
"T_TERM_UTURN_INT_SS6D1",
|
||||
"T_TERM_UTURN_INT_SS6A1",
|
||||
"T_TERM_UTURN_INT_SW6D2",
|
||||
"T_TERM_UTURN_INT_SR1END3_SLOW",
|
||||
"T_TERM_UTURN_INT_SE6C0",
|
||||
"T_TERM_UTURN_INT_SE6E0",
|
||||
"T_TERM_UTURN_INT_ER1END3",
|
||||
"T_TERM_UTURN_INT_SL1END1_SLOW",
|
||||
"T_TERM_UTURN_INT_SW6C2",
|
||||
"T_TERM_UTURN_INT_SE6C1"
|
||||
"T_TERM_UTURN_INT_SS6D0",
|
||||
"T_TERM_UTURN_INT_FAN_BOUNCE_S3_4",
|
||||
"T_TERM_UTURN_INT_LVB_L1",
|
||||
"T_TERM_UTURN_INT_SS2A1",
|
||||
"T_TERM_UTURN_INT_SE6B2",
|
||||
"T_TERM_UTURN_INT_LV_L5",
|
||||
"T_TERM_UTURN_INT_LVB2",
|
||||
"T_TERM_INT_UTURN_LV_R6",
|
||||
"T_TERM_UTURN_INT_SS6END3",
|
||||
"T_TERM_UTURN_INT_SS6END0",
|
||||
"T_TERM_UTURN_INT_SS6B1",
|
||||
"T_TERM_UTURN_INT_SE2A0",
|
||||
"T_TERM_UTURN_INT_SS2END3",
|
||||
"T_TERM_UTURN_INT_LV_L7",
|
||||
"T_TERM_UTURN_INT_SW6C3",
|
||||
"T_TERM_INT_UTURN_LV_R7",
|
||||
"T_TERM_UTURN_INT_LVB_L3",
|
||||
"T_TERM_UTURN_INT_LVB_L2",
|
||||
"T_TERM_UTURN_INT_LVB4",
|
||||
"T_TERM_UTURN_INT_LV_L9",
|
||||
"T_TERM_UTURN_INT_SE6B0",
|
||||
"T_TERM_UTURN_INT_SS6E2",
|
||||
"T_TERM_UTURN_INT_SW6B1",
|
||||
"T_TERM_UTURN_INT_SS6E1",
|
||||
"T_TERM_UTURN_INT_SS2END1",
|
||||
"T_TERM_UTURN_INT_LV_L17",
|
||||
"T_TERM_UTURN_INT_SS2A3",
|
||||
"T_TERM_UTURN_INT_SW6E2",
|
||||
"T_TERM_UTURN_INT_LVB3",
|
||||
"T_TERM_UTURN_INT_SE2A3",
|
||||
"T_TERM_UTURN_INT_LV_L16",
|
||||
"T_TERM_UTURN_INT_LV_L2",
|
||||
"T_TERM_UTURN_INT_SW6E1",
|
||||
"T_TERM_UTURN_INT_SS6E0",
|
||||
"T_TERM_UTURN_INT_SW6D3",
|
||||
"T_TERM_UTURN_INT_SS2END2",
|
||||
"T_TERM_UTURN_INT_SS6C0",
|
||||
"T_TERM_UTURN_INT_SS6END2",
|
||||
"T_TERM_UTURN_INT_SE6C3",
|
||||
"T_TERM_UTURN_INT_LV_L4",
|
||||
"T_TERM_UTURN_INT_SW6C0",
|
||||
"T_TERM_INT_UTURN_LV_R9",
|
||||
"T_TERM_INT_UTURN_LV_R5",
|
||||
"T_TERM_UTURN_INT_SS6A0",
|
||||
"T_TERM_UTURN_INT_SS2A0",
|
||||
"T_TERM_UTURN_INT_SS6B2",
|
||||
"T_TERM_INT_UTURN_LV_R17",
|
||||
"T_TERM_UTURN_INT_SL1END0_SLOW",
|
||||
"T_TERM_UTURN_INT_ER1BEG_S0",
|
||||
"T_TERM_UTURN_INT_SE6E3",
|
||||
"T_TERM_UTURN_INT_SS6C3",
|
||||
"T_TERM_UTURN_INT_WR1BEG_S0",
|
||||
"T_TERM_UTURN_INT_SE6D1",
|
||||
"T_TERM_UTURN_INT_SE6B1",
|
||||
"T_TERM_INT_UTURN_LV_R2",
|
||||
"T_TERM_UTURN_INT_SE6D3",
|
||||
"T_TERM_UTURN_INT_FAN_BOUNCE_S3_2",
|
||||
"T_TERM_UTURN_INT_SW2A1",
|
||||
"T_TERM_UTURN_INT_LVB1",
|
||||
"T_TERM_UTURN_INT_FAN_BOUNCE_S3_0",
|
||||
"T_TERM_UTURN_INT_SW6E0",
|
||||
"T_TERM_UTURN_INT_SW6C1",
|
||||
"T_TERM_UTURN_INT_SS6B0",
|
||||
"T_TERM_UTURN_INT_SS6A3",
|
||||
"T_TERM_UTURN_INT_SS2END0",
|
||||
"T_TERM_UTURN_INT_SS6C2",
|
||||
"T_TERM_UTURN_INT_SE6E1",
|
||||
"T_TERM_UTURN_INT_SE6C2",
|
||||
"T_TERM_UTURN_INT_SE6D2",
|
||||
"T_TERM_UTURN_INT_SS6A2",
|
||||
"T_TERM_UTURN_INT_SE6E2",
|
||||
"T_TERM_UTURN_INT_SW2A3",
|
||||
"T_TERM_UTURN_INT_LVB_L0",
|
||||
"T_TERM_UTURN_INT_SE6B3",
|
||||
"T_TERM_UTURN_INT_SS6END1",
|
||||
"T_TERM_UTURN_INT_SS6D2",
|
||||
"T_TERM_INT_UTURN_LV_R3",
|
||||
"T_TERM_UTURN_INT_WR1END_S1_0",
|
||||
"T_TERM_UTURN_INT_SS6B3",
|
||||
"T_TERM_UTURN_INT_LV_L6",
|
||||
"T_TERM_UTURN_INT_LV_L3",
|
||||
"T_TERM_INT_UTURN_LV_R4",
|
||||
"T_TERM_UTURN_INT_SW6E3",
|
||||
"T_TERM_UTURN_INT_SW6B2",
|
||||
"T_TERM_UTURN_INT_SW6B3",
|
||||
"T_TERM_UTURN_INT_SW6D0",
|
||||
"T_TERM_UTURN_INT_SE6C1",
|
||||
"T_TERM_UTURN_INT_SW2A0",
|
||||
"T_TERM_UTURN_INT_LVB_L5",
|
||||
"T_TERM_UTURN_INT_SS6D3",
|
||||
"T_TERM_UTURN_INT_SS6C1",
|
||||
"T_TERM_UTURN_INT_SE6D0",
|
||||
"T_TERM_UTURN_INT_LVB5"
|
||||
],
|
||||
"tile_type": "BRKH_TERM_INT",
|
||||
"sites": []
|
||||
}
|
||||
|
|
@ -1,125 +1,125 @@
|
|||
{
|
||||
"tile_type": "B_TERM_INT",
|
||||
"pips": {},
|
||||
"wires": [
|
||||
"B_TERM_UTURN_INT_SS6C3",
|
||||
"B_TERM_UTURN_INT_SE6C0",
|
||||
"B_TERM_UTURN_INT_FAN_BOUNCE6",
|
||||
"B_TERM_UTURN_INT_FAN_BOUNCE0",
|
||||
"B_TERM_UTURN_INT_SW6D3",
|
||||
"B_TERM_UTURN_INT_LV5",
|
||||
"B_TERM_UTURN_INT_LVB1",
|
||||
"B_TERM_UTURN_INT_SS6B2",
|
||||
"B_TERM_UTURN_INT_FAN_BOUNCE4",
|
||||
"B_TERM_UTURN_INT_SS2BEG2",
|
||||
"B_TERM_UTURN_INT_SW6D1",
|
||||
"B_TERM_UTURN_INT_LV4",
|
||||
"B_TERM_UTURN_INT_LVB0",
|
||||
"B_TERM_UTURN_INT_ER1END_N3_3",
|
||||
"B_TERM_UTURN_INT_SW6D0",
|
||||
"B_TERM_UTURN_INT_SS6B1",
|
||||
"B_TERM_UTURN_INT_SS2A1",
|
||||
"B_TERM_UTURN_INT_SW2BEG3",
|
||||
"B_TERM_UTURN_INT_SW6C2",
|
||||
"B_TERM_UTURN_INT_SE6A2",
|
||||
"B_TERM_UTURN_INT_SW2BEG0",
|
||||
"B_TERM_UTURN_INT_SW6B1",
|
||||
"B_TERM_UTURN_INT_LV_L8",
|
||||
"B_TERM_UTURN_INT_SR1BEG2",
|
||||
"B_TERM_UTURN_INT_SS6BEG0",
|
||||
"B_TERM_UTURN_INT_LV9",
|
||||
"B_TERM_UTURN_INT_LV_L4",
|
||||
"B_TERM_UTURN_INT_SW6B3",
|
||||
"B_TERM_UTURN_INT_SL1BEG2",
|
||||
"B_TERM_UTURN_INT_SW2BEG1",
|
||||
"B_TERM_UTURN_INT_SS2BEG1",
|
||||
"B_TERM_UTURN_INT_SL1BEG3",
|
||||
"B_TERM_UTURN_INT_SE6A3",
|
||||
"B_TERM_UTURN_INT_ER1BEG0",
|
||||
"B_TERM_UTURN_INT_SS6D1",
|
||||
"B_TERM_UTURN_INT_SS6BEG1",
|
||||
"B_TERM_UTURN_INT_SW6A3",
|
||||
"B_TERM_UTURN_INT_LV8",
|
||||
"B_TERM_UTURN_INT_SW6D2",
|
||||
"B_TERM_UTURN_INT_SW6B0",
|
||||
"B_TERM_UTURN_INT_SE6D3",
|
||||
"B_TERM_UTURN_INT_SW6C3",
|
||||
"B_TERM_UTURN_INT_LVB_L5",
|
||||
"B_TERM_UTURN_INT_SW2BEG2",
|
||||
"B_TERM_UTURN_INT_SR1BEG1",
|
||||
"B_TERM_UTURN_INT_SE6B1",
|
||||
"B_TERM_UTURN_INT_LVB4",
|
||||
"B_TERM_UTURN_INT_SS6A0",
|
||||
"B_TERM_UTURN_INT_SS2A2",
|
||||
"B_TERM_UTURN_INT_SS2BEG0",
|
||||
"B_TERM_UTURN_INT_SW6C1",
|
||||
"B_TERM_UTURN_INT_SE6B3",
|
||||
"B_TERM_UTURN_INT_LV3",
|
||||
"B_TERM_UTURN_INT_SL1BEG0",
|
||||
"B_TERM_UTURN_INT_SW6C0",
|
||||
"B_TERM_UTURN_INT_SS6E2",
|
||||
"B_TERM_UTURN_INT_LV_L5",
|
||||
"B_TERM_UTURN_INT_LV_L18",
|
||||
"B_TERM_UTURN_INT_SS6A2",
|
||||
"B_TERM_UTURN_INT_SE6C1",
|
||||
"B_TERM_UTURN_INT_SS6E1",
|
||||
"B_TERM_UTURN_INT_SE6A1",
|
||||
"B_TERM_UTURN_INT_SW6A0",
|
||||
"B_TERM_UTURN_INT_LV_L7",
|
||||
"B_TERM_UTURN_INT_SS6E3",
|
||||
"B_TERM_UTURN_INT_LVB2",
|
||||
"B_TERM_UTURN_INT_SS6D2",
|
||||
"B_TERM_UTURN_INT_LV_L3",
|
||||
"B_TERM_UTURN_INT_SS2A0",
|
||||
"B_TERM_UTURN_INT_LVB_L2",
|
||||
"B_TERM_UTURN_INT_SE6D1",
|
||||
"B_TERM_UTURN_INT_SS6E0",
|
||||
"B_TERM_UTURN_INT_LV7",
|
||||
"B_TERM_UTURN_INT_SE6B0",
|
||||
"B_TERM_UTURN_INT_SS6B3",
|
||||
"B_TERM_UTURN_INT_SE2BEG3",
|
||||
"B_TERM_UTURN_INT_SW6END_N0_3",
|
||||
"B_TERM_UTURN_INT_SS6C1",
|
||||
"B_TERM_UTURN_INT_SW6A2",
|
||||
"B_TERM_UTURN_INT_LVB_L0",
|
||||
"B_TERM_UTURN_INT_SS6BEG3",
|
||||
"B_TERM_UTURN_INT_LV_L2",
|
||||
"B_TERM_UTURN_INT_WR1BEG0",
|
||||
"B_TERM_UTURN_INT_SS6E2",
|
||||
"B_TERM_UTURN_INT_SR1BEG3",
|
||||
"B_TERM_UTURN_INT_SE6A1",
|
||||
"B_TERM_UTURN_INT_SW2BEG1",
|
||||
"B_TERM_UTURN_INT_LVB5",
|
||||
"B_TERM_UTURN_INT_SS2BEG3",
|
||||
"B_TERM_UTURN_INT_LVB_L3",
|
||||
"B_TERM_UTURN_INT_SW6B2",
|
||||
"B_TERM_UTURN_INT_SW2BEG3",
|
||||
"B_TERM_UTURN_INT_SS6BEG3",
|
||||
"B_TERM_UTURN_INT_SW6C3",
|
||||
"B_TERM_UTURN_INT_SW2BEG2",
|
||||
"B_TERM_UTURN_INT_LVB_L0",
|
||||
"B_TERM_UTURN_INT_SS6A0",
|
||||
"B_TERM_UTURN_INT_SE2BEG2",
|
||||
"B_TERM_UTURN_INT_SS6A1",
|
||||
"B_TERM_UTURN_INT_SS6B2",
|
||||
"B_TERM_UTURN_INT_LV_L5",
|
||||
"B_TERM_UTURN_INT_LVB_L3",
|
||||
"B_TERM_UTURN_INT_LVB_L2",
|
||||
"B_TERM_UTURN_INT_ER1END_N3_3",
|
||||
"B_TERM_UTURN_INT_SS2BEG1",
|
||||
"B_TERM_UTURN_INT_SW6A0",
|
||||
"B_TERM_UTURN_INT_LVB2",
|
||||
"B_TERM_UTURN_INT_LV5",
|
||||
"B_TERM_UTURN_INT_SE6C2",
|
||||
"B_TERM_UTURN_INT_SW2BEG0",
|
||||
"B_TERM_UTURN_INT_LVB4",
|
||||
"B_TERM_UTURN_INT_SW6A3",
|
||||
"B_TERM_UTURN_INT_LVB3",
|
||||
"B_TERM_UTURN_INT_LV_L6",
|
||||
"B_TERM_UTURN_INT_SS6D3",
|
||||
"B_TERM_UTURN_INT_SE2BEG1",
|
||||
"B_TERM_UTURN_INT_FAN_BOUNCE0",
|
||||
"B_TERM_UTURN_INT_LV_L3",
|
||||
"B_TERM_UTURN_INT_SE6D2",
|
||||
"B_TERM_UTURN_INT_SS6B0",
|
||||
"B_TERM_UTURN_INT_FAN_BOUNCE6",
|
||||
"B_TERM_UTURN_INT_LV_L2",
|
||||
"B_TERM_UTURN_INT_SS6E0",
|
||||
"B_TERM_UTURN_INT_SE6C0",
|
||||
"B_TERM_UTURN_INT_ER1BEG0",
|
||||
"B_TERM_UTURN_INT_WR1BEG0",
|
||||
"B_TERM_UTURN_INT_SS6A2",
|
||||
"B_TERM_UTURN_INT_LV_L8",
|
||||
"B_TERM_UTURN_INT_SE6B3",
|
||||
"B_TERM_UTURN_INT_LV18",
|
||||
"B_TERM_UTURN_INT_SW6B1",
|
||||
"B_TERM_UTURN_INT_LV_L9",
|
||||
"B_TERM_UTURN_INT_LVB_L1",
|
||||
"B_TERM_UTURN_INT_SE2BEG2",
|
||||
"B_TERM_UTURN_INT_SE6B2",
|
||||
"B_TERM_UTURN_INT_SS6BEG2",
|
||||
"B_TERM_UTURN_INT_SE2BEG1",
|
||||
"B_TERM_UTURN_INT_FAN_BOUNCE2",
|
||||
"B_TERM_UTURN_INT_SE6C2",
|
||||
"B_TERM_UTURN_INT_SS2A3",
|
||||
"B_TERM_UTURN_INT_LVB_L4",
|
||||
"B_TERM_UTURN_INT_LV2",
|
||||
"B_TERM_UTURN_INT_SS6B0",
|
||||
"B_TERM_UTURN_INT_LV18",
|
||||
"B_TERM_UTURN_INT_LV6",
|
||||
"B_TERM_UTURN_INT_SS6C0",
|
||||
"B_TERM_UTURN_INT_SE6A0",
|
||||
"B_TERM_UTURN_INT_SS6C2",
|
||||
"B_TERM_UTURN_INT_SW6A1",
|
||||
"B_TERM_UTURN_INT_SE6D0",
|
||||
"B_TERM_UTURN_INT_SE2BEG0",
|
||||
"B_TERM_UTURN_INT_SS6D0",
|
||||
"B_TERM_UTURN_INT_SR1BEG3",
|
||||
"B_TERM_UTURN_INT_SW6B2",
|
||||
"B_TERM_UTURN_INT_SE6C3",
|
||||
"B_TERM_UTURN_INT_LVB_L5",
|
||||
"B_TERM_UTURN_INT_SS2BEG0",
|
||||
"B_TERM_UTURN_INT_SL1BEG1",
|
||||
"B_TERM_UTURN_INT_WR1END0",
|
||||
"B_TERM_UTURN_INT_SE6C1",
|
||||
"B_TERM_UTURN_INT_SW6D1",
|
||||
"B_TERM_UTURN_INT_FAN_BOUNCE2",
|
||||
"B_TERM_UTURN_INT_SR1BEG2",
|
||||
"B_TERM_UTURN_INT_SW6A1",
|
||||
"B_TERM_UTURN_INT_SS6D1",
|
||||
"B_TERM_UTURN_INT_LVB0",
|
||||
"B_TERM_UTURN_INT_SS6D2",
|
||||
"B_TERM_UTURN_INT_SW6C0",
|
||||
"B_TERM_UTURN_INT_SS6D0",
|
||||
"B_TERM_UTURN_INT_SS6A3",
|
||||
"B_TERM_UTURN_INT_SE6D2"
|
||||
"B_TERM_UTURN_INT_SL1BEG3",
|
||||
"B_TERM_UTURN_INT_LV2",
|
||||
"B_TERM_UTURN_INT_SE6D3",
|
||||
"B_TERM_UTURN_INT_SW6C1",
|
||||
"B_TERM_UTURN_INT_SS2A1",
|
||||
"B_TERM_UTURN_INT_LVB_L4",
|
||||
"B_TERM_UTURN_INT_SS2A2",
|
||||
"B_TERM_UTURN_INT_SW6B0",
|
||||
"B_TERM_UTURN_INT_LV6",
|
||||
"B_TERM_UTURN_INT_SE6B1",
|
||||
"B_TERM_UTURN_INT_SW6D2",
|
||||
"B_TERM_UTURN_INT_SE6D1",
|
||||
"B_TERM_UTURN_INT_FAN_BOUNCE4",
|
||||
"B_TERM_UTURN_INT_SW6D3",
|
||||
"B_TERM_UTURN_INT_SW6END_N0_3",
|
||||
"B_TERM_UTURN_INT_WR1END0",
|
||||
"B_TERM_UTURN_INT_SW6A2",
|
||||
"B_TERM_UTURN_INT_LV7",
|
||||
"B_TERM_UTURN_INT_SE6B2",
|
||||
"B_TERM_UTURN_INT_SE6A0",
|
||||
"B_TERM_UTURN_INT_SE6A2",
|
||||
"B_TERM_UTURN_INT_SS6B1",
|
||||
"B_TERM_UTURN_INT_SS2BEG3",
|
||||
"B_TERM_UTURN_INT_SS6C1",
|
||||
"B_TERM_UTURN_INT_SS6C0",
|
||||
"B_TERM_UTURN_INT_LVB1",
|
||||
"B_TERM_UTURN_INT_LV_L4",
|
||||
"B_TERM_UTURN_INT_LV3",
|
||||
"B_TERM_UTURN_INT_SS2A0",
|
||||
"B_TERM_UTURN_INT_LV4",
|
||||
"B_TERM_UTURN_INT_SE6C3",
|
||||
"B_TERM_UTURN_INT_SS2BEG2",
|
||||
"B_TERM_UTURN_INT_SS6BEG1",
|
||||
"B_TERM_UTURN_INT_LV_L18",
|
||||
"B_TERM_UTURN_INT_LV_L6",
|
||||
"B_TERM_UTURN_INT_SW6D0",
|
||||
"B_TERM_UTURN_INT_SS6B3",
|
||||
"B_TERM_UTURN_INT_SS6C3",
|
||||
"B_TERM_UTURN_INT_SW6C2",
|
||||
"B_TERM_UTURN_INT_SE6A3",
|
||||
"B_TERM_UTURN_INT_LV_L7",
|
||||
"B_TERM_UTURN_INT_SS2A3",
|
||||
"B_TERM_UTURN_INT_SS6C2",
|
||||
"B_TERM_UTURN_INT_LV8",
|
||||
"B_TERM_UTURN_INT_SS6BEG2",
|
||||
"B_TERM_UTURN_INT_SL1BEG0",
|
||||
"B_TERM_UTURN_INT_SS6E3",
|
||||
"B_TERM_UTURN_INT_SS6BEG0",
|
||||
"B_TERM_UTURN_INT_SS6E1",
|
||||
"B_TERM_UTURN_INT_SR1BEG1",
|
||||
"B_TERM_UTURN_INT_SW6B3",
|
||||
"B_TERM_UTURN_INT_SE6D0",
|
||||
"B_TERM_UTURN_INT_SE6B0",
|
||||
"B_TERM_UTURN_INT_LV9",
|
||||
"B_TERM_UTURN_INT_SS6D3",
|
||||
"B_TERM_UTURN_INT_SL1BEG2"
|
||||
],
|
||||
"tile_type": "B_TERM_INT",
|
||||
"sites": []
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -1,261 +1,261 @@
|
|||
{
|
||||
"tile_type": "CLK_FEED",
|
||||
"pips": {},
|
||||
"wires": [
|
||||
"CLK_FEED_LH4",
|
||||
"CLK_FEED_NE4C2",
|
||||
"CLK_FEED_EL1BEG2",
|
||||
"CLK_FEED_LH3",
|
||||
"CLK_FEED_WW4END3",
|
||||
"CLK_FEED_CK_BUFG_CASC29",
|
||||
"CLK_FEED_WW4B0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC22",
|
||||
"CLK_FEED_R_CK_BUFG_CASC4",
|
||||
"CLK_FEED_R_CK_BUFG_CASC30",
|
||||
"CLK_FEED_EE2A0",
|
||||
"CLK_FEED_CK_BUFG_CASC5",
|
||||
"CLK_FEED_R_CK_GCLK1",
|
||||
"CLK_FEED_NE4BEG0",
|
||||
"CLK_FEED_CK_BUFG_CASC30",
|
||||
"CLK_FEED_WW4B2",
|
||||
"CLK_FEED_EE2A2",
|
||||
"CLK_FEED_CK_GCLK28",
|
||||
"CLK_FEED_R_CK_GCLK13",
|
||||
"CLK_FEED_CK_GCLK26",
|
||||
"CLK_FEED_SW4END1",
|
||||
"CLK_FEED_SE2A0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC27",
|
||||
"CLK_FEED_CK_GCLK13",
|
||||
"CLK_FEED_CK_GCLK19",
|
||||
"CLK_FEED_LH6",
|
||||
"CLK_FEED_R_CK_BUFG_CASC29",
|
||||
"CLK_FEED_NW4END1",
|
||||
"CLK_FEED_R_CK_BUFG_CASC2",
|
||||
"CLK_FEED_R_CK_BUFG_CASC15",
|
||||
"CLK_FEED_NW4A1",
|
||||
"CLK_FEED_CK_GCLK22",
|
||||
"CLK_FEED_EE2A3",
|
||||
"CLK_FEED_NE2A0",
|
||||
"CLK_FEED_EE4C2",
|
||||
"CLK_FEED_EE4A0",
|
||||
"CLK_FEED_EE4BEG3",
|
||||
"CLK_FEED_CK_GCLK6",
|
||||
"CLK_FEED_NW2A0",
|
||||
"CLK_FEED_R_CK_GCLK25",
|
||||
"CLK_FEED_R_CK_BUFG_CASC28",
|
||||
"CLK_FEED_R_CK_GCLK2",
|
||||
"CLK_FEED_NE4BEG1",
|
||||
"CLK_FEED_CK_BUFG_CASC7",
|
||||
"CLK_FEED_R_CK_GCLK5",
|
||||
"CLK_FEED_WW4END2",
|
||||
"CLK_FEED_CK_GCLK8",
|
||||
"CLK_FEED_EE4B1",
|
||||
"CLK_FEED_R_CK_GCLK21",
|
||||
"CLK_FEED_SE2A2",
|
||||
"CLK_FEED_WW4C2",
|
||||
"CLK_FEED_NE4BEG2",
|
||||
"CLK_FEED_SE4C2",
|
||||
"CLK_FEED_WW4A2",
|
||||
"CLK_FEED_CK_GCLK20",
|
||||
"CLK_FEED_NW2A2",
|
||||
"CLK_FEED_CK_BUFG_CASC15",
|
||||
"CLK_FEED_LH10",
|
||||
"CLK_FEED_EL1BEG0",
|
||||
"CLK_FEED_CK_BUFG_CASC9",
|
||||
"CLK_FEED_CK_BUFG_CASC17",
|
||||
"CLK_FEED_R_CK_BUFG_CASC3",
|
||||
"CLK_FEED_CK_BUFG_CASC3",
|
||||
"CLK_FEED_WW4B3",
|
||||
"CLK_FEED_CK_BUFG_CASC14",
|
||||
"CLK_FEED_R_CK_GCLK23",
|
||||
"CLK_FEED_SE4C0",
|
||||
"CLK_FEED_WW2A2",
|
||||
"CLK_FEED_CK_GCLK17",
|
||||
"CLK_FEED_NE4C0",
|
||||
"CLK_FEED_NW4END2",
|
||||
"CLK_FEED_CK_GCLK29",
|
||||
"CLK_FEED_WL1END0",
|
||||
"CLK_FEED_WW2END2",
|
||||
"CLK_FEED_CK_BUFG_CASC26",
|
||||
"CLK_FEED_R_CK_BUFG_CASC26",
|
||||
"CLK_FEED_CK_BUFG_CASC0",
|
||||
"CLK_FEED_WW4B1",
|
||||
"CLK_FEED_CK_GCLK0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC19",
|
||||
"CLK_FEED_WL1END2",
|
||||
"CLK_FEED_CK_BUFG_CASC23",
|
||||
"CLK_FEED_R_CK_GCLK6",
|
||||
"CLK_FEED_ER1BEG2",
|
||||
"CLK_FEED_R_CK_GCLK31",
|
||||
"CLK_FEED_SE4BEG3",
|
||||
"CLK_FEED_LH7",
|
||||
"CLK_FEED_NW2A3",
|
||||
"CLK_FEED_NW4A0",
|
||||
"CLK_FEED_WW2A0",
|
||||
"CLK_FEED_EE4B2",
|
||||
"CLK_FEED_SW2A3",
|
||||
"CLK_FEED_R_CK_GCLK3",
|
||||
"CLK_FEED_CK_BUFG_CASC21",
|
||||
"CLK_FEED_EE2A1",
|
||||
"CLK_FEED_EE4C1",
|
||||
"CLK_FEED_SW4END3",
|
||||
"CLK_FEED_WR1END3",
|
||||
"CLK_FEED_EE4C3",
|
||||
"CLK_FEED_R_CK_GCLK8",
|
||||
"CLK_FEED_CK_BUFG_CASC1",
|
||||
"CLK_FEED_R_CK_GCLK10",
|
||||
"CLK_FEED_SW4A2",
|
||||
"CLK_FEED_R_CK_GCLK4",
|
||||
"CLK_FEED_R_CK_GCLK7",
|
||||
"CLK_FEED_WW4A0",
|
||||
"CLK_FEED_CK_BUFG_CASC28",
|
||||
"CLK_FEED_CK_GCLK31",
|
||||
"CLK_FEED_R_CK_BUFG_CASC11",
|
||||
"CLK_FEED_WW2A3",
|
||||
"CLK_FEED_CK_BUFG_CASC2",
|
||||
"CLK_FEED_EE2BEG2",
|
||||
"CLK_FEED_CK_BUFG_CASC24",
|
||||
"CLK_FEED_EE2BEG0",
|
||||
"CLK_FEED_LH1",
|
||||
"CLK_FEED_CK_BUFG_CASC22",
|
||||
"CLK_FEED_SE4C1",
|
||||
"CLK_FEED_R_CK_BUFG_CASC25",
|
||||
"CLK_FEED_NE4C3",
|
||||
"CLK_FEED_SE2A1",
|
||||
"CLK_FEED_NE2A1",
|
||||
"CLK_FEED_R_CK_BUFG_CASC18",
|
||||
"CLK_FEED_WW2END3",
|
||||
"CLK_FEED_MONITOR_N",
|
||||
"CLK_FEED_R_CK_BUFG_CASC17",
|
||||
"CLK_FEED_ER1BEG1",
|
||||
"CLK_FEED_EE4BEG1",
|
||||
"CLK_FEED_WR1END1",
|
||||
"CLK_FEED_R_CK_GCLK26",
|
||||
"CLK_FEED_R_CK_GCLK16",
|
||||
"CLK_FEED_R_CK_BUFG_CASC9",
|
||||
"CLK_FEED_EE4BEG2",
|
||||
"CLK_FEED_R_CK_BUFG_CASC7",
|
||||
"CLK_FEED_WW4C3",
|
||||
"CLK_FEED_R_CK_GCLK29",
|
||||
"CLK_FEED_CK_BUFG_CASC6",
|
||||
"CLK_FEED_LH2",
|
||||
"CLK_FEED_SW4END2",
|
||||
"CLK_FEED_WW4END0",
|
||||
"CLK_FEED_CK_GCLK12",
|
||||
"CLK_FEED_CK_BUFG_CASC31",
|
||||
"CLK_FEED_R_CK_GCLK9",
|
||||
"CLK_FEED_CK_BUFG_CASC11",
|
||||
"CLK_FEED_LH9",
|
||||
"CLK_FEED_NW2A1",
|
||||
"CLK_FEED_WW2END0",
|
||||
"CLK_FEED_CK_GCLK9",
|
||||
"CLK_FEED_R_CK_GCLK22",
|
||||
"CLK_FEED_R_CK_BUFG_CASC10",
|
||||
"CLK_FEED_EE4BEG0",
|
||||
"CLK_FEED_NW4END0",
|
||||
"CLK_FEED_CK_BUFG_CASC19",
|
||||
"CLK_FEED_CK_GCLK7",
|
||||
"CLK_FEED_EE2BEG1",
|
||||
"CLK_FEED_SE4BEG0",
|
||||
"CLK_FEED_R_CK_GCLK27",
|
||||
"CLK_FEED_CK_GCLK30",
|
||||
"CLK_FEED_R_CK_BUFG_CASC12",
|
||||
"CLK_FEED_CK_BUFG_CASC4",
|
||||
"CLK_FEED_CK_BUFG_CASC20",
|
||||
"CLK_FEED_R_CK_GCLK20",
|
||||
"CLK_FEED_SE2A3",
|
||||
"CLK_FEED_SW2A2",
|
||||
"CLK_FEED_NE4C1",
|
||||
"CLK_FEED_SE4BEG1",
|
||||
"CLK_FEED_ER1BEG0",
|
||||
"CLK_FEED_EE4A1",
|
||||
"CLK_FEED_WW4C0",
|
||||
"CLK_FEED_R_CK_GCLK11",
|
||||
"CLK_FEED_NE2A3",
|
||||
"CLK_FEED_SW4A3",
|
||||
"CLK_FEED_NW4A2",
|
||||
"CLK_FEED_R_CK_BUFG_CASC1",
|
||||
"CLK_FEED_CK_GCLK18",
|
||||
"CLK_FEED_CK_GCLK23",
|
||||
"CLK_FEED_R_CK_BUFG_CASC20",
|
||||
"CLK_FEED_NE4BEG3",
|
||||
"CLK_FEED_CK_GCLK16",
|
||||
"CLK_FEED_SW4A1",
|
||||
"CLK_FEED_R_CK_BUFG_CASC23",
|
||||
"CLK_FEED_CK_GCLK21",
|
||||
"CLK_FEED_LH8",
|
||||
"CLK_FEED_MONITOR_P",
|
||||
"CLK_FEED_WL1END3",
|
||||
"CLK_FEED_R_CK_GCLK18",
|
||||
"CLK_FEED_WW4END1",
|
||||
"CLK_FEED_LH5",
|
||||
"CLK_FEED_SW4END0",
|
||||
"CLK_FEED_WW4A1",
|
||||
"CLK_FEED_R_CK_GCLK15",
|
||||
"CLK_FEED_CK_BUFG_CASC18",
|
||||
"CLK_FEED_R_CK_BUFG_CASC6",
|
||||
"CLK_FEED_ER1BEG3",
|
||||
"CLK_FEED_SE4BEG2",
|
||||
"CLK_FEED_CK_GCLK1",
|
||||
"CLK_FEED_NW4A3",
|
||||
"CLK_FEED_WR1END2",
|
||||
"CLK_FEED_CK_GCLK24",
|
||||
"CLK_FEED_EE4A3",
|
||||
"CLK_FEED_R_CK_BUFG_CASC0",
|
||||
"CLK_FEED_R_CK_GCLK12",
|
||||
"CLK_FEED_CK_GCLK14",
|
||||
"CLK_FEED_CK_GCLK4",
|
||||
"CLK_FEED_EE4C0",
|
||||
"CLK_FEED_EE4B3",
|
||||
"CLK_FEED_R_CK_GCLK24",
|
||||
"CLK_FEED_EE4A2",
|
||||
"CLK_FEED_R_CK_GCLK30",
|
||||
"CLK_FEED_R_CK_BUFG_CASC24",
|
||||
"CLK_FEED_CK_BUFG_CASC13",
|
||||
"CLK_FEED_R_CK_BUFG_CASC5",
|
||||
"CLK_FEED_NW4END3",
|
||||
"CLK_FEED_R_CK_BUFG_CASC21",
|
||||
"CLK_FEED_WW4C1",
|
||||
"CLK_FEED_R_CK_BUFG_CASC8",
|
||||
"CLK_FEED_SE4C3",
|
||||
"CLK_FEED_CK_BUFG_CASC10",
|
||||
"CLK_FEED_SW4A0",
|
||||
"CLK_FEED_CK_BUFG_CASC27",
|
||||
"CLK_FEED_R_CK_BUFG_CASC13",
|
||||
"CLK_FEED_NE2A2",
|
||||
"CLK_FEED_SW2A1",
|
||||
"CLK_FEED_CK_GCLK15",
|
||||
"CLK_FEED_SW2A0",
|
||||
"CLK_FEED_CK_GCLK11",
|
||||
"CLK_FEED_CK_BUFG_CASC25",
|
||||
"CLK_FEED_CK_GCLK2",
|
||||
"CLK_FEED_CK_GCLK25",
|
||||
"CLK_FEED_CK_BUFG_CASC9",
|
||||
"CLK_FEED_R_CK_BUFG_CASC23",
|
||||
"CLK_FEED_R_CK_GCLK0",
|
||||
"CLK_FEED_CK_GCLK3",
|
||||
"CLK_FEED_WL1END1",
|
||||
"CLK_FEED_R_CK_GCLK14",
|
||||
"CLK_FEED_CK_GCLK10",
|
||||
"CLK_FEED_WW2END1",
|
||||
"CLK_FEED_WW4A3",
|
||||
"CLK_FEED_R_CK_BUFG_CASC31",
|
||||
"CLK_FEED_CK_GCLK5",
|
||||
"CLK_FEED_CK_GCLK27",
|
||||
"CLK_FEED_R_CK_GCLK28",
|
||||
"CLK_FEED_CK_BUFG_CASC16",
|
||||
"CLK_FEED_EL1BEG1",
|
||||
"CLK_FEED_NW4END3",
|
||||
"CLK_FEED_R_CK_BUFG_CASC12",
|
||||
"CLK_FEED_EE4C3",
|
||||
"CLK_FEED_CK_BUFG_CASC31",
|
||||
"CLK_FEED_R_CK_GCLK24",
|
||||
"CLK_FEED_R_CK_BUFG_CASC29",
|
||||
"CLK_FEED_R_CK_BUFG_CASC8",
|
||||
"CLK_FEED_WW4C1",
|
||||
"CLK_FEED_SE2A3",
|
||||
"CLK_FEED_R_CK_GCLK19",
|
||||
"CLK_FEED_CK_BUFG_CASC8",
|
||||
"CLK_FEED_LH12",
|
||||
"CLK_FEED_R_CK_GCLK17",
|
||||
"CLK_FEED_WR1END0",
|
||||
"CLK_FEED_LH11",
|
||||
"CLK_FEED_WW2A1",
|
||||
"CLK_FEED_R_CK_BUFG_CASC10",
|
||||
"CLK_FEED_WW4A1",
|
||||
"CLK_FEED_EE4A2",
|
||||
"CLK_FEED_R_CK_BUFG_CASC7",
|
||||
"CLK_FEED_R_CK_BUFG_CASC2",
|
||||
"CLK_FEED_R_CK_GCLK9",
|
||||
"CLK_FEED_CK_BUFG_CASC19",
|
||||
"CLK_FEED_EE2BEG2",
|
||||
"CLK_FEED_EE2A2",
|
||||
"CLK_FEED_R_CK_BUFG_CASC5",
|
||||
"CLK_FEED_CK_BUFG_CASC4",
|
||||
"CLK_FEED_CK_GCLK19",
|
||||
"CLK_FEED_R_CK_BUFG_CASC17",
|
||||
"CLK_FEED_SW4A3",
|
||||
"CLK_FEED_WW4C3",
|
||||
"CLK_FEED_LH10",
|
||||
"CLK_FEED_R_CK_GCLK29",
|
||||
"CLK_FEED_CK_GCLK11",
|
||||
"CLK_FEED_CK_GCLK7",
|
||||
"CLK_FEED_R_CK_BUFG_CASC27",
|
||||
"CLK_FEED_R_CK_BUFG_CASC11",
|
||||
"CLK_FEED_ER1BEG2",
|
||||
"CLK_FEED_EL1BEG3",
|
||||
"CLK_FEED_EE4B0",
|
||||
"CLK_FEED_EE2BEG3",
|
||||
"CLK_FEED_CK_GCLK1",
|
||||
"CLK_FEED_NE4C2",
|
||||
"CLK_FEED_CK_BUFG_CASC21",
|
||||
"CLK_FEED_EE4C1",
|
||||
"CLK_FEED_CK_BUFG_CASC12",
|
||||
"CLK_FEED_R_CK_GCLK2",
|
||||
"CLK_FEED_SE2A1",
|
||||
"CLK_FEED_CK_BUFG_CASC14",
|
||||
"CLK_FEED_ER1BEG3",
|
||||
"CLK_FEED_WW4C0",
|
||||
"CLK_FEED_CK_GCLK4",
|
||||
"CLK_FEED_CK_BUFG_CASC23",
|
||||
"CLK_FEED_ER1BEG1",
|
||||
"CLK_FEED_NW4A3",
|
||||
"CLK_FEED_R_CK_BUFG_CASC0",
|
||||
"CLK_FEED_ER1BEG0",
|
||||
"CLK_FEED_CK_GCLK16",
|
||||
"CLK_FEED_CK_GCLK29",
|
||||
"CLK_FEED_R_CK_GCLK26",
|
||||
"CLK_FEED_R_CK_BUFG_CASC4",
|
||||
"CLK_FEED_WW4C2",
|
||||
"CLK_FEED_R_CK_GCLK16",
|
||||
"CLK_FEED_CK_GCLK23",
|
||||
"CLK_FEED_EE4A0",
|
||||
"CLK_FEED_WR1END1",
|
||||
"CLK_FEED_NE4C0",
|
||||
"CLK_FEED_CK_BUFG_CASC16",
|
||||
"CLK_FEED_R_CK_GCLK5",
|
||||
"CLK_FEED_R_CK_BUFG_CASC19",
|
||||
"CLK_FEED_CK_GCLK6",
|
||||
"CLK_FEED_EE4B1",
|
||||
"CLK_FEED_CK_GCLK9",
|
||||
"CLK_FEED_CK_GCLK25",
|
||||
"CLK_FEED_EE4A1",
|
||||
"CLK_FEED_SW4END1",
|
||||
"CLK_FEED_SW4END2",
|
||||
"CLK_FEED_CK_GCLK2",
|
||||
"CLK_FEED_WW2A3",
|
||||
"CLK_FEED_NE2A0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC14",
|
||||
"CLK_FEED_CK_BUFG_CASC7",
|
||||
"CLK_FEED_CK_BUFG_CASC27",
|
||||
"CLK_FEED_R_CK_BUFG_CASC1",
|
||||
"CLK_FEED_WW4A3",
|
||||
"CLK_FEED_SW4A0",
|
||||
"CLK_FEED_EE4C0",
|
||||
"CLK_FEED_CK_BUFG_CASC5",
|
||||
"CLK_FEED_CK_BUFG_CASC13",
|
||||
"CLK_FEED_CK_GCLK21",
|
||||
"CLK_FEED_CK_GCLK28",
|
||||
"CLK_FEED_WW2A2",
|
||||
"CLK_FEED_NE4BEG2",
|
||||
"CLK_FEED_WR1END2",
|
||||
"CLK_FEED_EL1BEG2",
|
||||
"CLK_FEED_CK_BUFG_CASC8",
|
||||
"CLK_FEED_LH1",
|
||||
"CLK_FEED_R_CK_GCLK30",
|
||||
"CLK_FEED_WW2A0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC15",
|
||||
"CLK_FEED_R_CK_GCLK3",
|
||||
"CLK_FEED_WW4A2",
|
||||
"CLK_FEED_EL1BEG1",
|
||||
"CLK_FEED_WL1END0",
|
||||
"CLK_FEED_SE2A2",
|
||||
"CLK_FEED_WW4END3",
|
||||
"CLK_FEED_R_CK_BUFG_CASC28",
|
||||
"CLK_FEED_NW4END0",
|
||||
"CLK_FEED_SW4A2",
|
||||
"CLK_FEED_NW4END1",
|
||||
"CLK_FEED_WW2A1",
|
||||
"CLK_FEED_EE2A0",
|
||||
"CLK_FEED_EE2BEG0",
|
||||
"CLK_FEED_NE4C1",
|
||||
"CLK_FEED_CK_GCLK20",
|
||||
"CLK_FEED_R_CK_GCLK11",
|
||||
"CLK_FEED_LH6",
|
||||
"CLK_FEED_NE4BEG0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC24",
|
||||
"CLK_FEED_NW2A1",
|
||||
"CLK_FEED_CK_GCLK12",
|
||||
"CLK_FEED_CK_BUFG_CASC2",
|
||||
"CLK_FEED_WL1END3",
|
||||
"CLK_FEED_CK_GCLK22",
|
||||
"CLK_FEED_R_CK_GCLK4",
|
||||
"CLK_FEED_LH9",
|
||||
"CLK_FEED_R_CK_GCLK6",
|
||||
"CLK_FEED_CK_GCLK30",
|
||||
"CLK_FEED_NE4BEG3",
|
||||
"CLK_FEED_R_CK_GCLK27",
|
||||
"CLK_FEED_R_CK_GCLK18",
|
||||
"CLK_FEED_CK_BUFG_CASC3",
|
||||
"CLK_FEED_WW2END2",
|
||||
"CLK_FEED_EE2BEG1",
|
||||
"CLK_FEED_WW4END0",
|
||||
"CLK_FEED_CK_BUFG_CASC25",
|
||||
"CLK_FEED_LH2",
|
||||
"CLK_FEED_R_CK_GCLK25",
|
||||
"CLK_FEED_EE4B3",
|
||||
"CLK_FEED_CK_BUFG_CASC24",
|
||||
"CLK_FEED_WW2END1",
|
||||
"CLK_FEED_LH12",
|
||||
"CLK_FEED_LH7",
|
||||
"CLK_FEED_R_CK_GCLK14",
|
||||
"CLK_FEED_SW2A1",
|
||||
"CLK_FEED_NW4A1",
|
||||
"CLK_FEED_R_CK_BUFG_CASC18",
|
||||
"CLK_FEED_CK_GCLK27",
|
||||
"CLK_FEED_MONITOR_P",
|
||||
"CLK_FEED_SE4BEG1",
|
||||
"CLK_FEED_MONITOR_N",
|
||||
"CLK_FEED_CK_BUFG_CASC18",
|
||||
"CLK_FEED_CK_BUFG_CASC15",
|
||||
"CLK_FEED_SW2A0",
|
||||
"CLK_FEED_CK_BUFG_CASC0",
|
||||
"CLK_FEED_WR1END0",
|
||||
"CLK_FEED_CK_BUFG_CASC29",
|
||||
"CLK_FEED_R_CK_BUFG_CASC20",
|
||||
"CLK_FEED_NE4BEG1",
|
||||
"CLK_FEED_WW4B0",
|
||||
"CLK_FEED_NE2A1",
|
||||
"CLK_FEED_SE4C0",
|
||||
"CLK_FEED_R_CK_GCLK22",
|
||||
"CLK_FEED_R_CK_GCLK8",
|
||||
"CLK_FEED_WW2END3",
|
||||
"CLK_FEED_R_CK_BUFG_CASC25",
|
||||
"CLK_FEED_EE2A1",
|
||||
"CLK_FEED_EE4B2",
|
||||
"CLK_FEED_CK_GCLK0",
|
||||
"CLK_FEED_WW4B2",
|
||||
"CLK_FEED_R_CK_BUFG_CASC26",
|
||||
"CLK_FEED_R_CK_BUFG_CASC22",
|
||||
"CLK_FEED_SW2A2",
|
||||
"CLK_FEED_CK_GCLK8",
|
||||
"CLK_FEED_LH11",
|
||||
"CLK_FEED_NW2A0",
|
||||
"CLK_FEED_CK_BUFG_CASC22",
|
||||
"CLK_FEED_CK_GCLK18",
|
||||
"CLK_FEED_CK_GCLK26",
|
||||
"CLK_FEED_CK_BUFG_CASC20",
|
||||
"CLK_FEED_CK_GCLK3",
|
||||
"CLK_FEED_SE4C1",
|
||||
"CLK_FEED_NW4A2",
|
||||
"CLK_FEED_WW2END0",
|
||||
"CLK_FEED_CK_BUFG_CASC6",
|
||||
"CLK_FEED_SE2A0",
|
||||
"CLK_FEED_WW4A0",
|
||||
"CLK_FEED_EE4BEG2",
|
||||
"CLK_FEED_CK_GCLK10",
|
||||
"CLK_FEED_R_CK_BUFG_CASC30",
|
||||
"CLK_FEED_SW4END3",
|
||||
"CLK_FEED_EL1BEG0",
|
||||
"CLK_FEED_EE4BEG0",
|
||||
"CLK_FEED_WR1END3",
|
||||
"CLK_FEED_CK_GCLK5",
|
||||
"CLK_FEED_CK_BUFG_CASC30",
|
||||
"CLK_FEED_SE4BEG0",
|
||||
"CLK_FEED_SE4BEG3",
|
||||
"CLK_FEED_EE4BEG1",
|
||||
"CLK_FEED_R_CK_BUFG_CASC6",
|
||||
"CLK_FEED_CK_GCLK17",
|
||||
"CLK_FEED_SW4A1",
|
||||
"CLK_FEED_R_CK_GCLK23",
|
||||
"CLK_FEED_EE2BEG3",
|
||||
"CLK_FEED_R_CK_BUFG_CASC16",
|
||||
"CLK_FEED_CK_BUFG_CASC12"
|
||||
"CLK_FEED_R_CK_GCLK21",
|
||||
"CLK_FEED_R_CK_GCLK10",
|
||||
"CLK_FEED_NE4C3",
|
||||
"CLK_FEED_R_CK_BUFG_CASC21",
|
||||
"CLK_FEED_NW4A0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC31",
|
||||
"CLK_FEED_SE4BEG2",
|
||||
"CLK_FEED_CK_BUFG_CASC11",
|
||||
"CLK_FEED_R_CK_GCLK20",
|
||||
"CLK_FEED_SW4END0",
|
||||
"CLK_FEED_CK_BUFG_CASC26",
|
||||
"CLK_FEED_LH5",
|
||||
"CLK_FEED_R_CK_GCLK31",
|
||||
"CLK_FEED_WW4B1",
|
||||
"CLK_FEED_R_CK_GCLK17",
|
||||
"CLK_FEED_R_CK_GCLK7",
|
||||
"CLK_FEED_WW4END1",
|
||||
"CLK_FEED_CK_GCLK24",
|
||||
"CLK_FEED_CK_BUFG_CASC28",
|
||||
"CLK_FEED_EE2A3",
|
||||
"CLK_FEED_CK_GCLK14",
|
||||
"CLK_FEED_CK_GCLK13",
|
||||
"CLK_FEED_CK_BUFG_CASC1",
|
||||
"CLK_FEED_R_CK_BUFG_CASC9",
|
||||
"CLK_FEED_LH8",
|
||||
"CLK_FEED_EE4C2",
|
||||
"CLK_FEED_WW4B3",
|
||||
"CLK_FEED_EE4A3",
|
||||
"CLK_FEED_NW2A2",
|
||||
"CLK_FEED_CK_BUFG_CASC10",
|
||||
"CLK_FEED_WL1END1",
|
||||
"CLK_FEED_SE4C3",
|
||||
"CLK_FEED_WL1END2",
|
||||
"CLK_FEED_LH3",
|
||||
"CLK_FEED_R_CK_GCLK13",
|
||||
"CLK_FEED_NW2A3",
|
||||
"CLK_FEED_LH4",
|
||||
"CLK_FEED_EE4B0",
|
||||
"CLK_FEED_SE4C2",
|
||||
"CLK_FEED_SW2A3",
|
||||
"CLK_FEED_EE4BEG3",
|
||||
"CLK_FEED_CK_GCLK15",
|
||||
"CLK_FEED_R_CK_GCLK1",
|
||||
"CLK_FEED_R_CK_GCLK15",
|
||||
"CLK_FEED_R_CK_GCLK12",
|
||||
"CLK_FEED_R_CK_GCLK28",
|
||||
"CLK_FEED_CK_BUFG_CASC17",
|
||||
"CLK_FEED_R_CK_BUFG_CASC13",
|
||||
"CLK_FEED_NW4END2",
|
||||
"CLK_FEED_WW4END2",
|
||||
"CLK_FEED_R_CK_BUFG_CASC3",
|
||||
"CLK_FEED_NE2A3"
|
||||
],
|
||||
"tile_type": "CLK_FEED",
|
||||
"sites": []
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -1,365 +1,365 @@
|
|||
{
|
||||
"tile_type": "CLK_MTBF2",
|
||||
"pips": {},
|
||||
"wires": [
|
||||
"CLK_FEED_LH4",
|
||||
"CLK_FEED_NE4C2",
|
||||
"CLK_PMV_CLK0_0",
|
||||
"CLK_FEED_EL1BEG2",
|
||||
"CLK_FEED_LH3",
|
||||
"CLK_FEED_WW4END3",
|
||||
"CLK_FEED_CK_BUFG_CASC29",
|
||||
"CLK_PMV_FAN0_0",
|
||||
"CLK_PMV_LOGIC_OUTS17_0",
|
||||
"CLK_FEED_WW4B0",
|
||||
"CLK_PMV_BYP5_0",
|
||||
"CLK_PMV_LOGIC_OUTS21_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC22",
|
||||
"CLK_PMV_LOGIC_OUTS4_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC4",
|
||||
"CLK_FEED_R_CK_BUFG_CASC30",
|
||||
"CLK_FEED_EE2A0",
|
||||
"CLK_PMV_IMUX34_0",
|
||||
"CLK_MTBF2_Q2B",
|
||||
"CLK_FEED_CK_BUFG_CASC5",
|
||||
"CLK_PMV_IMUX3_0",
|
||||
"CLK_FEED_R_CK_GCLK1",
|
||||
"CLK_PMV_BYP4_0",
|
||||
"CLK_FEED_NE4BEG0",
|
||||
"CLK_FEED_CK_BUFG_CASC30",
|
||||
"CLK_PMV_LOGIC_OUTS15_0",
|
||||
"CLK_FEED_WW4B2",
|
||||
"CLK_FEED_EE2A2",
|
||||
"CLK_FEED_CK_GCLK28",
|
||||
"CLK_FEED_R_CK_GCLK13",
|
||||
"CLK_FEED_CK_GCLK26",
|
||||
"CLK_FEED_SW4END1",
|
||||
"CLK_FEED_SE2A0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC27",
|
||||
"CLK_PMV_IMUX41_0",
|
||||
"CLK_FEED_CK_GCLK13",
|
||||
"CLK_FEED_CK_GCLK19",
|
||||
"CLK_FEED_LH6",
|
||||
"CLK_FEED_R_CK_BUFG_CASC29",
|
||||
"CLK_FEED_NW4END1",
|
||||
"CLK_FEED_R_CK_BUFG_CASC2",
|
||||
"CLK_FEED_R_CK_BUFG_CASC15",
|
||||
"CLK_PMV_IMUX25_0",
|
||||
"CLK_FEED_NW4A1",
|
||||
"CLK_FEED_CK_GCLK22",
|
||||
"CLK_FEED_EE2A3",
|
||||
"CLK_FEED_NE2A0",
|
||||
"CLK_FEED_EE4C2",
|
||||
"CLK_PMV_IMUX15_0",
|
||||
"CLK_FEED_EE4A0",
|
||||
"CLK_FEED_EE4BEG3",
|
||||
"CLK_FEED_CK_GCLK6",
|
||||
"CLK_FEED_NW2A0",
|
||||
"CLK_FEED_R_CK_GCLK25",
|
||||
"CLK_FEED_R_CK_BUFG_CASC28",
|
||||
"CLK_PMV_LOGIC_OUTS3_0",
|
||||
"CLK_FEED_R_CK_GCLK2",
|
||||
"CLK_MTBF2_Q3B",
|
||||
"CLK_PMV_FAN7_0",
|
||||
"CLK_PMV_IMUX2_0",
|
||||
"CLK_FEED_NE4BEG1",
|
||||
"CLK_FEED_CK_BUFG_CASC7",
|
||||
"CLK_PMV_IMUX13_0",
|
||||
"CLK_PMV_IMUX16_0",
|
||||
"CLK_FEED_R_CK_GCLK5",
|
||||
"CLK_MTBF2_Q4B",
|
||||
"CLK_FEED_WW4END2",
|
||||
"CLK_PMV_CTRL0_0",
|
||||
"CLK_PMV_IMUX31_0",
|
||||
"CLK_FEED_CK_GCLK8",
|
||||
"CLK_FEED_EE4B1",
|
||||
"CLK_FEED_SE2A2",
|
||||
"CLK_FEED_R_CK_GCLK21",
|
||||
"CLK_FEED_WW4C2",
|
||||
"CLK_FEED_NE4BEG2",
|
||||
"CLK_FEED_SE4C2",
|
||||
"CLK_FEED_WW4A2",
|
||||
"CLK_FEED_CK_GCLK20",
|
||||
"CLK_FEED_NW2A2",
|
||||
"CLK_PMV_IMUX33_0",
|
||||
"CLK_PMV_CLK1_0",
|
||||
"CLK_PMV_IMUX9_0",
|
||||
"CLK_PMV_LOGIC_OUTS10_0",
|
||||
"CLK_FEED_CK_BUFG_CASC15",
|
||||
"CLK_FEED_LH10",
|
||||
"CLK_FEED_EL1BEG0",
|
||||
"CLK_PMV_IMUX40_0",
|
||||
"CLK_FEED_CK_GCLK31",
|
||||
"CLK_FEED_NE2A2",
|
||||
"CLK_PMV_IMUX43_0",
|
||||
"CLK_FEED_CK_BUFG_CASC9",
|
||||
"CLK_PMV_LOGIC_OUTS9_0",
|
||||
"CLK_PMV_LOGIC_OUTS20_0",
|
||||
"CLK_FEED_CK_BUFG_CASC17",
|
||||
"CLK_FEED_CK_BUFG_CASC3",
|
||||
"CLK_FEED_WW4B3",
|
||||
"CLK_FEED_R_CK_BUFG_CASC3",
|
||||
"CLK_FEED_CK_BUFG_CASC14",
|
||||
"CLK_PMV_IMUX18_0",
|
||||
"CLK_PMV_IMUX37_0",
|
||||
"CLK_FEED_R_CK_GCLK23",
|
||||
"CLK_PMV_LOGIC_OUTS8_0",
|
||||
"CLK_FEED_SE4C0",
|
||||
"CLK_FEED_WW2A2",
|
||||
"CLK_PMV_IMUX1_0",
|
||||
"CLK_FEED_CK_GCLK17",
|
||||
"CLK_FEED_NE4C0",
|
||||
"CLK_FEED_NW4END2",
|
||||
"CLK_FEED_CK_GCLK29",
|
||||
"CLK_MTBF2_Q0B",
|
||||
"CLK_FEED_WL1END0",
|
||||
"CLK_PMV_IMUX36_0",
|
||||
"CLK_FEED_WW2END2",
|
||||
"CLK_FEED_CK_BUFG_CASC26",
|
||||
"CLK_FEED_R_CK_BUFG_CASC26",
|
||||
"CLK_PMV_LOGIC_OUTS11_0",
|
||||
"CLK_FEED_CK_BUFG_CASC0",
|
||||
"CLK_FEED_WW4B1",
|
||||
"CLK_FEED_CK_GCLK0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC19",
|
||||
"CLK_FEED_WL1END2",
|
||||
"CLK_FEED_CK_BUFG_CASC23",
|
||||
"CLK_FEED_R_CK_GCLK6",
|
||||
"CLK_FEED_R_CK_BUFG_CASC23",
|
||||
"CLK_PMV_LOGIC_OUTS17_0",
|
||||
"CLK_FEED_R_CK_GCLK0",
|
||||
"CLK_FEED_NW4END3",
|
||||
"CLK_FEED_R_CK_BUFG_CASC12",
|
||||
"CLK_FEED_EE4C3",
|
||||
"CLK_PMV_LOGIC_OUTS5_0",
|
||||
"CLK_PMV_BYP4_0",
|
||||
"CLK_FEED_CK_BUFG_CASC31",
|
||||
"CLK_FEED_R_CK_GCLK24",
|
||||
"CLK_PMV_LOGIC_OUTS18_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC29",
|
||||
"CLK_FEED_R_CK_BUFG_CASC8",
|
||||
"CLK_FEED_WW4C1",
|
||||
"CLK_FEED_SE2A3",
|
||||
"CLK_PMV_FAN7_0",
|
||||
"CLK_FEED_R_CK_GCLK19",
|
||||
"CLK_FEED_WW4A1",
|
||||
"CLK_FEED_R_CK_BUFG_CASC10",
|
||||
"CLK_PMV_FAN2_0",
|
||||
"CLK_PMV_BYP7_0",
|
||||
"CLK_FEED_EE4A2",
|
||||
"CLK_FEED_R_CK_BUFG_CASC7",
|
||||
"CLK_FEED_R_CK_BUFG_CASC2",
|
||||
"CLK_FEED_R_CK_GCLK9",
|
||||
"CLK_PMV_IMUX10_0",
|
||||
"CLK_FEED_CK_BUFG_CASC19",
|
||||
"CLK_PMV_IMUX5_0",
|
||||
"CLK_FEED_EE2BEG2",
|
||||
"CLK_FEED_EE2A2",
|
||||
"CLK_FEED_R_CK_BUFG_CASC5",
|
||||
"CLK_FEED_CK_BUFG_CASC4",
|
||||
"CLK_FEED_CK_GCLK19",
|
||||
"CLK_FEED_R_CK_BUFG_CASC17",
|
||||
"CLK_FEED_SW4A3",
|
||||
"CLK_PMV_IMUX23_0",
|
||||
"CLK_FEED_WW4C3",
|
||||
"CLK_FEED_LH10",
|
||||
"CLK_FEED_R_CK_GCLK29",
|
||||
"CLK_FEED_CK_GCLK11",
|
||||
"CLK_FEED_CK_GCLK7",
|
||||
"CLK_FEED_R_CK_BUFG_CASC27",
|
||||
"CLK_FEED_R_CK_BUFG_CASC11",
|
||||
"CLK_FEED_ER1BEG2",
|
||||
"CLK_FEED_R_CK_GCLK31",
|
||||
"CLK_PMV_LOGIC_OUTS13_0",
|
||||
"CLK_FEED_SE4BEG3",
|
||||
"CLK_PMV_IMUX20_0",
|
||||
"CLK_FEED_LH7",
|
||||
"CLK_FEED_NW4A0",
|
||||
"CLK_FEED_NW2A3",
|
||||
"CLK_FEED_EL1BEG3",
|
||||
"CLK_FEED_CK_GCLK1",
|
||||
"CLK_FEED_NE4C2",
|
||||
"CLK_FEED_CK_BUFG_CASC21",
|
||||
"CLK_FEED_EE4C1",
|
||||
"CLK_FEED_CK_BUFG_CASC12",
|
||||
"CLK_FEED_R_CK_GCLK2",
|
||||
"CLK_FEED_SE2A1",
|
||||
"CLK_FEED_CK_BUFG_CASC14",
|
||||
"CLK_FEED_ER1BEG3",
|
||||
"CLK_FEED_WW4C0",
|
||||
"CLK_FEED_CK_BUFG_CASC23",
|
||||
"CLK_FEED_CK_GCLK4",
|
||||
"CLK_FEED_ER1BEG1",
|
||||
"CLK_PMV_BYP6_0",
|
||||
"CLK_FEED_NW4A3",
|
||||
"CLK_FEED_R_CK_BUFG_CASC0",
|
||||
"CLK_PMV_FAN0_0",
|
||||
"CLK_FEED_ER1BEG0",
|
||||
"CLK_MTBF2_Q3B",
|
||||
"CLK_PMV_IMUX31_0",
|
||||
"CLK_PMV_LOGIC_OUTS14_0",
|
||||
"CLK_FEED_CK_GCLK16",
|
||||
"CLK_FEED_CK_GCLK29",
|
||||
"CLK_FEED_R_CK_GCLK26",
|
||||
"CLK_PMV_LOGIC_OUTS3_0",
|
||||
"CLK_FEED_WW4C2",
|
||||
"CLK_FEED_R_CK_BUFG_CASC4",
|
||||
"CLK_FEED_R_CK_GCLK16",
|
||||
"CLK_FEED_CK_GCLK23",
|
||||
"CLK_FEED_EE4A0",
|
||||
"CLK_FEED_WR1END1",
|
||||
"CLK_FEED_NE4C0",
|
||||
"CLK_FEED_CK_BUFG_CASC16",
|
||||
"CLK_PMV_FAN1_0",
|
||||
"CLK_FEED_R_CK_GCLK5",
|
||||
"CLK_FEED_R_CK_BUFG_CASC19",
|
||||
"CLK_FEED_CK_GCLK6",
|
||||
"CLK_FEED_EE4B1",
|
||||
"CLK_FEED_CK_GCLK25",
|
||||
"CLK_FEED_EE4A1",
|
||||
"CLK_FEED_CK_GCLK9",
|
||||
"CLK_FEED_SW4END1",
|
||||
"CLK_FEED_SW4END2",
|
||||
"CLK_PMV_LOGIC_OUTS12_0",
|
||||
"CLK_FEED_CK_GCLK2",
|
||||
"CLK_FEED_WW2A3",
|
||||
"CLK_FEED_NE2A0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC14",
|
||||
"CLK_PMV_IMUX44_0",
|
||||
"CLK_FEED_CK_BUFG_CASC7",
|
||||
"CLK_FEED_CK_BUFG_CASC27",
|
||||
"CLK_PMV_IMUX8_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC1",
|
||||
"CLK_FEED_WW4A3",
|
||||
"CLK_PMV_IMUX1_0",
|
||||
"CLK_MTBF2_RESET",
|
||||
"CLK_FEED_SW4A0",
|
||||
"CLK_PMV_LOGIC_OUTS2_0",
|
||||
"CLK_MTBF2_Q2B",
|
||||
"CLK_FEED_EE4C0",
|
||||
"CLK_FEED_CK_BUFG_CASC5",
|
||||
"CLK_FEED_CK_BUFG_CASC13",
|
||||
"CLK_FEED_CK_GCLK21",
|
||||
"CLK_PMV_FAN3_0",
|
||||
"CLK_FEED_CK_GCLK28",
|
||||
"CLK_PMV_IMUX15_0",
|
||||
"CLK_PMV_IMUX26_0",
|
||||
"CLK_PMV_CTRL1_0",
|
||||
"CLK_PMV_FAN5_0",
|
||||
"CLK_FEED_NE4BEG2",
|
||||
"CLK_FEED_WW2A2",
|
||||
"CLK_FEED_WR1END2",
|
||||
"CLK_PMV_CTRL0_0",
|
||||
"CLK_MTBF2_Q7B",
|
||||
"CLK_FEED_EL1BEG2",
|
||||
"CLK_PMV_IMUX30_0",
|
||||
"CLK_FEED_LH1",
|
||||
"CLK_FEED_CK_BUFG_CASC8",
|
||||
"CLK_FEED_R_CK_GCLK30",
|
||||
"CLK_PMV_LOGIC_OUTS9_0",
|
||||
"CLK_FEED_WW2A0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC15",
|
||||
"CLK_FEED_R_CK_GCLK3",
|
||||
"CLK_FEED_WW4A2",
|
||||
"CLK_PMV_IMUX13_0",
|
||||
"CLK_FEED_EL1BEG1",
|
||||
"CLK_FEED_WL1END0",
|
||||
"CLK_FEED_SE2A2",
|
||||
"CLK_FEED_WW4END3",
|
||||
"CLK_FEED_R_CK_BUFG_CASC28",
|
||||
"CLK_FEED_NW4END0",
|
||||
"CLK_FEED_SW4A2",
|
||||
"CLK_PMV_IMUX22_0",
|
||||
"CLK_PMV_IMUX4_0",
|
||||
"CLK_FEED_WW2A0",
|
||||
"CLK_FEED_EE4B2",
|
||||
"CLK_FEED_SW2A3",
|
||||
"CLK_PMV_IMUX45_0",
|
||||
"CLK_FEED_EE2A1",
|
||||
"CLK_FEED_CK_BUFG_CASC21",
|
||||
"CLK_FEED_R_CK_GCLK3",
|
||||
"CLK_FEED_EE4C1",
|
||||
"CLK_FEED_SW4END3",
|
||||
"CLK_FEED_WR1END3",
|
||||
"CLK_FEED_EE4C3",
|
||||
"CLK_FEED_R_CK_GCLK8",
|
||||
"CLK_FEED_CK_BUFG_CASC1",
|
||||
"CLK_FEED_R_CK_GCLK10",
|
||||
"CLK_FEED_SW4A2",
|
||||
"CLK_PMV_FAN1_0",
|
||||
"CLK_FEED_R_CK_GCLK7",
|
||||
"CLK_PMV_BYP3_0",
|
||||
"CLK_FEED_NW4END1",
|
||||
"CLK_PMV_LOGIC_OUTS15_0",
|
||||
"CLK_FEED_WW2A1",
|
||||
"CLK_FEED_EE2A0",
|
||||
"CLK_FEED_EE2BEG0",
|
||||
"CLK_PMV_IMUX20_0",
|
||||
"CLK_PMV_BYP0_0",
|
||||
"CLK_FEED_NE4C1",
|
||||
"CLK_FEED_CK_GCLK20",
|
||||
"CLK_FEED_R_CK_GCLK11",
|
||||
"CLK_FEED_LH6",
|
||||
"CLK_FEED_NE4BEG0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC24",
|
||||
"CLK_FEED_NW2A1",
|
||||
"CLK_FEED_CK_GCLK12",
|
||||
"CLK_FEED_CK_BUFG_CASC2",
|
||||
"CLK_FEED_CK_GCLK22",
|
||||
"CLK_FEED_WL1END3",
|
||||
"CLK_FEED_R_CK_GCLK4",
|
||||
"CLK_FEED_WW4A0",
|
||||
"CLK_FEED_CK_BUFG_CASC28",
|
||||
"CLK_FEED_CK_GCLK31",
|
||||
"CLK_FEED_R_CK_BUFG_CASC11",
|
||||
"CLK_PMV_IMUX7_0",
|
||||
"CLK_PMV_BYP7_0",
|
||||
"CLK_PMV_IMUX33_0",
|
||||
"CLK_PMV_IMUX0_0",
|
||||
"CLK_FEED_LH9",
|
||||
"CLK_FEED_R_CK_GCLK6",
|
||||
"CLK_FEED_CK_GCLK30",
|
||||
"CLK_PMV_IMUX24_0",
|
||||
"CLK_MTBF2_Q1B",
|
||||
"CLK_FEED_NE4BEG3",
|
||||
"CLK_PMV_BYP1_0",
|
||||
"CLK_PMV_LOGIC_OUTS7_0",
|
||||
"CLK_FEED_WW2A3",
|
||||
"CLK_PMV_FAN2_0",
|
||||
"CLK_PMV_LOGIC_OUTS2_0",
|
||||
"CLK_FEED_R_CK_GCLK27",
|
||||
"CLK_FEED_CK_BUFG_CASC3",
|
||||
"CLK_FEED_R_CK_GCLK18",
|
||||
"CLK_FEED_WW2END2",
|
||||
"CLK_FEED_EE2BEG1",
|
||||
"CLK_FEED_WW4END0",
|
||||
"CLK_FEED_CK_BUFG_CASC25",
|
||||
"CLK_MTBF2_Q0B",
|
||||
"CLK_PMV_IMUX16_0",
|
||||
"CLK_FEED_LH2",
|
||||
"CLK_PMV_LOGIC_OUTS6_0",
|
||||
"CLK_FEED_R_CK_GCLK25",
|
||||
"CLK_PMV_CLK0_0",
|
||||
"CLK_PMV_IMUX11_0",
|
||||
"CLK_FEED_EE4B3",
|
||||
"CLK_FEED_CK_BUFG_CASC24",
|
||||
"CLK_FEED_WW2END1",
|
||||
"CLK_PMV_LOGIC_OUTS23_0",
|
||||
"CLK_FEED_LH12",
|
||||
"CLK_FEED_LH7",
|
||||
"CLK_FEED_R_CK_GCLK14",
|
||||
"CLK_FEED_SW2A1",
|
||||
"CLK_PMV_IMUX6_0",
|
||||
"CLK_PMV_LOGIC_OUTS22_0",
|
||||
"CLK_PMV_IMUX23_0",
|
||||
"CLK_FEED_EE2BEG0",
|
||||
"CLK_FEED_CK_BUFG_CASC2",
|
||||
"CLK_FEED_CK_BUFG_CASC24",
|
||||
"CLK_FEED_EE2BEG2",
|
||||
"CLK_FEED_LH1",
|
||||
"CLK_FEED_CK_BUFG_CASC22",
|
||||
"CLK_PMV_IMUX11_0",
|
||||
"CLK_FEED_SE4C1",
|
||||
"CLK_PMV_LOGIC_OUTS23_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC25",
|
||||
"CLK_FEED_NE4C3",
|
||||
"CLK_PMV_FAN3_0",
|
||||
"CLK_FEED_SE2A1",
|
||||
"CLK_FEED_NE2A1",
|
||||
"CLK_FEED_R_CK_BUFG_CASC18",
|
||||
"CLK_PMV_LOGIC_OUTS19_0",
|
||||
"CLK_FEED_WW2END3",
|
||||
"CLK_FEED_MONITOR_N",
|
||||
"CLK_FEED_R_CK_BUFG_CASC17",
|
||||
"CLK_FEED_ER1BEG1",
|
||||
"CLK_FEED_EE4BEG1",
|
||||
"CLK_PMV_IMUX35_0",
|
||||
"CLK_FEED_WR1END1",
|
||||
"CLK_FEED_R_CK_GCLK26",
|
||||
"CLK_PMV_IMUX19_0",
|
||||
"CLK_PMV_LOGIC_OUTS0_0",
|
||||
"CLK_FEED_R_CK_GCLK16",
|
||||
"CLK_PMV_FAN5_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC9",
|
||||
"CLK_FEED_EE4BEG2",
|
||||
"CLK_PMV_LOGIC_OUTS12_0",
|
||||
"CLK_PMV_BYP3_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC7",
|
||||
"CLK_FEED_WW4C3",
|
||||
"CLK_FEED_R_CK_GCLK29",
|
||||
"CLK_FEED_CK_BUFG_CASC6",
|
||||
"CLK_PMV_IMUX43_0",
|
||||
"CLK_FEED_LH2",
|
||||
"CLK_FEED_SW4END2",
|
||||
"CLK_FEED_WW4END0",
|
||||
"CLK_FEED_CK_GCLK12",
|
||||
"CLK_FEED_CK_BUFG_CASC31",
|
||||
"CLK_FEED_R_CK_GCLK9",
|
||||
"CLK_FEED_CK_BUFG_CASC11",
|
||||
"CLK_FEED_NW2A1",
|
||||
"CLK_FEED_LH9",
|
||||
"CLK_FEED_WW2END0",
|
||||
"CLK_FEED_CK_GCLK9",
|
||||
"CLK_FEED_R_CK_GCLK22",
|
||||
"CLK_PMV_IMUX24_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC10",
|
||||
"CLK_FEED_EE4BEG0",
|
||||
"CLK_PMV_IMUX10_0",
|
||||
"CLK_FEED_NW4END0",
|
||||
"CLK_FEED_CK_GCLK7",
|
||||
"CLK_FEED_CK_BUFG_CASC19",
|
||||
"CLK_FEED_EE2BEG1",
|
||||
"CLK_FEED_SE4BEG0",
|
||||
"CLK_FEED_R_CK_GCLK27",
|
||||
"CLK_FEED_CK_GCLK30",
|
||||
"CLK_FEED_R_CK_BUFG_CASC12",
|
||||
"CLK_FEED_CK_BUFG_CASC4",
|
||||
"CLK_MTBF2_Q6B",
|
||||
"CLK_FEED_CK_BUFG_CASC20",
|
||||
"CLK_PMV_IMUX28_0",
|
||||
"CLK_MTBF2_Q7B",
|
||||
"CLK_PMV_BYP6_0",
|
||||
"CLK_PMV_LOGIC_OUTS5_0",
|
||||
"CLK_FEED_R_CK_GCLK20",
|
||||
"CLK_FEED_SE2A3",
|
||||
"CLK_PMV_IMUX40_0",
|
||||
"CLK_FEED_SW2A2",
|
||||
"CLK_FEED_NE4C1",
|
||||
"CLK_FEED_SE4BEG1",
|
||||
"CLK_FEED_ER1BEG0",
|
||||
"CLK_PMV_LOGIC_OUTS16_0",
|
||||
"CLK_PMV_IMUX42_0",
|
||||
"CLK_FEED_EE4A1",
|
||||
"CLK_FEED_WW4C0",
|
||||
"CLK_FEED_R_CK_GCLK11",
|
||||
"CLK_FEED_NE2A3",
|
||||
"CLK_FEED_SW4A3",
|
||||
"CLK_PMV_LOGIC_OUTS6_0",
|
||||
"CLK_PMV_IMUX27_0",
|
||||
"CLK_FEED_NW4A2",
|
||||
"CLK_PMV_IMUX38_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC1",
|
||||
"CLK_PMV_LOGIC_OUTS14_0",
|
||||
"CLK_PMV_IMUX30_0",
|
||||
"CLK_FEED_CK_GCLK23",
|
||||
"CLK_FEED_CK_GCLK18",
|
||||
"CLK_FEED_R_CK_BUFG_CASC20",
|
||||
"CLK_FEED_NE4BEG3",
|
||||
"CLK_FEED_CK_GCLK16",
|
||||
"CLK_FEED_SW4A1",
|
||||
"CLK_FEED_R_CK_BUFG_CASC23",
|
||||
"CLK_FEED_CK_GCLK21",
|
||||
"CLK_FEED_MONITOR_P",
|
||||
"CLK_FEED_LH8",
|
||||
"CLK_FEED_WL1END3",
|
||||
"CLK_FEED_R_CK_GCLK18",
|
||||
"CLK_FEED_WW4END1",
|
||||
"CLK_FEED_LH5",
|
||||
"CLK_FEED_SW4END0",
|
||||
"CLK_FEED_WW4A1",
|
||||
"CLK_FEED_R_CK_GCLK15",
|
||||
"CLK_FEED_CK_BUFG_CASC18",
|
||||
"CLK_FEED_R_CK_BUFG_CASC6",
|
||||
"CLK_FEED_ER1BEG3",
|
||||
"CLK_FEED_SE4BEG2",
|
||||
"CLK_FEED_CK_GCLK1",
|
||||
"CLK_FEED_WR1END2",
|
||||
"CLK_FEED_NW4A3",
|
||||
"CLK_FEED_CK_GCLK24",
|
||||
"CLK_FEED_EE4A3",
|
||||
"CLK_FEED_R_CK_BUFG_CASC0",
|
||||
"CLK_PMV_LOGIC_OUTS18_0",
|
||||
"CLK_FEED_R_CK_GCLK12",
|
||||
"CLK_PMV_CTRL1_0",
|
||||
"CLK_FEED_CK_GCLK14",
|
||||
"CLK_PMV_FAN4_0",
|
||||
"CLK_FEED_CK_GCLK4",
|
||||
"CLK_FEED_EE4C0",
|
||||
"CLK_FEED_EE4B3",
|
||||
"CLK_FEED_R_CK_GCLK24",
|
||||
"CLK_FEED_EE4A2",
|
||||
"CLK_PMV_IMUX44_0",
|
||||
"CLK_PMV_IMUX21_0",
|
||||
"CLK_FEED_R_CK_GCLK30",
|
||||
"CLK_FEED_R_CK_BUFG_CASC24",
|
||||
"CLK_FEED_CK_BUFG_CASC13",
|
||||
"CLK_FEED_R_CK_BUFG_CASC5",
|
||||
"CLK_FEED_NW4END3",
|
||||
"CLK_PMV_BYP0_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC21",
|
||||
"CLK_PMV_IMUX47_0",
|
||||
"CLK_FEED_WW4C1",
|
||||
"CLK_PMV_IMUX32_0",
|
||||
"CLK_PMV_LOGIC_OUTS1_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC8",
|
||||
"CLK_MTBF2_Q1B",
|
||||
"CLK_FEED_SE4C3",
|
||||
"CLK_PMV_IMUX26_0",
|
||||
"CLK_FEED_CK_BUFG_CASC10",
|
||||
"CLK_FEED_SW4A0",
|
||||
"CLK_FEED_CK_BUFG_CASC27",
|
||||
"CLK_FEED_R_CK_BUFG_CASC13",
|
||||
"CLK_PMV_IMUX17_0",
|
||||
"CLK_FEED_NE2A2",
|
||||
"CLK_FEED_SW2A1",
|
||||
"CLK_FEED_CK_GCLK15",
|
||||
"CLK_FEED_SW2A0",
|
||||
"CLK_FEED_CK_GCLK11",
|
||||
"CLK_PMV_IMUX46_0",
|
||||
"CLK_FEED_CK_BUFG_CASC25",
|
||||
"CLK_PMV_IMUX12_0",
|
||||
"CLK_FEED_CK_GCLK2",
|
||||
"CLK_FEED_CK_GCLK25",
|
||||
"CLK_PMV_IMUX14_0",
|
||||
"CLK_FEED_R_CK_GCLK0",
|
||||
"CLK_FEED_CK_GCLK3",
|
||||
"CLK_FEED_WL1END1",
|
||||
"CLK_FEED_R_CK_GCLK14",
|
||||
"CLK_PMV_IMUX0_0",
|
||||
"CLK_FEED_CK_GCLK10",
|
||||
"CLK_MTBF2_Q5B",
|
||||
"CLK_FEED_WW2END1",
|
||||
"CLK_FEED_WW4A3",
|
||||
"CLK_FEED_R_CK_BUFG_CASC31",
|
||||
"CLK_FEED_CK_GCLK5",
|
||||
"CLK_FEED_NW4A1",
|
||||
"CLK_FEED_CK_GCLK27",
|
||||
"CLK_FEED_CK_BUFG_CASC16",
|
||||
"CLK_FEED_R_CK_GCLK28",
|
||||
"CLK_FEED_EL1BEG1",
|
||||
"CLK_MTBF2_RESET",
|
||||
"CLK_MTBF2_CLK",
|
||||
"CLK_FEED_R_CK_GCLK19",
|
||||
"CLK_FEED_CK_BUFG_CASC8",
|
||||
"CLK_PMV_IMUX5_0",
|
||||
"CLK_FEED_LH12",
|
||||
"CLK_FEED_R_CK_GCLK17",
|
||||
"CLK_FEED_R_CK_BUFG_CASC18",
|
||||
"CLK_FEED_MONITOR_P",
|
||||
"CLK_FEED_SE4BEG1",
|
||||
"CLK_FEED_MONITOR_N",
|
||||
"CLK_PMV_IMUX47_0",
|
||||
"CLK_PMV_IMUX45_0",
|
||||
"CLK_FEED_CK_BUFG_CASC18",
|
||||
"CLK_PMV_IMUX36_0",
|
||||
"CLK_PMV_LOGIC_OUTS8_0",
|
||||
"CLK_FEED_CK_BUFG_CASC15",
|
||||
"CLK_PMV_LOGIC_OUTS19_0",
|
||||
"CLK_PMV_IMUX34_0",
|
||||
"CLK_FEED_SW2A0",
|
||||
"CLK_FEED_CK_BUFG_CASC0",
|
||||
"CLK_FEED_WR1END0",
|
||||
"CLK_FEED_LH11",
|
||||
"CLK_MTBF2_DIN",
|
||||
"CLK_PMV_BYP2_0",
|
||||
"CLK_FEED_WW2A1",
|
||||
"CLK_PMV_IMUX8_0",
|
||||
"CLK_FEED_EL1BEG3",
|
||||
"CLK_PMV_IMUX39_0",
|
||||
"CLK_FEED_CK_BUFG_CASC29",
|
||||
"CLK_PMV_IMUX21_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC20",
|
||||
"CLK_PMV_IMUX41_0",
|
||||
"CLK_PMV_IMUX27_0",
|
||||
"CLK_MTBF2_CLK",
|
||||
"CLK_PMV_IMUX25_0",
|
||||
"CLK_FEED_NE4BEG1",
|
||||
"CLK_PMV_FAN6_0",
|
||||
"CLK_FEED_WW4B0",
|
||||
"CLK_PMV_LOGIC_OUTS1_0",
|
||||
"CLK_PMV_IMUX28_0",
|
||||
"CLK_FEED_NE2A1",
|
||||
"CLK_PMV_FAN4_0",
|
||||
"CLK_FEED_SE4C0",
|
||||
"CLK_FEED_R_CK_GCLK22",
|
||||
"CLK_FEED_R_CK_GCLK8",
|
||||
"CLK_PMV_LOGIC_OUTS20_0",
|
||||
"CLK_PMV_IMUX19_0",
|
||||
"CLK_FEED_WW2END3",
|
||||
"CLK_FEED_R_CK_BUFG_CASC25",
|
||||
"CLK_FEED_EE2A1",
|
||||
"CLK_FEED_EE4B2",
|
||||
"CLK_FEED_CK_GCLK0",
|
||||
"CLK_FEED_WW4B2",
|
||||
"CLK_PMV_IMUX46_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC26",
|
||||
"CLK_FEED_R_CK_BUFG_CASC22",
|
||||
"CLK_FEED_SW2A2",
|
||||
"CLK_FEED_CK_GCLK8",
|
||||
"CLK_FEED_LH11",
|
||||
"CLK_FEED_NW2A0",
|
||||
"CLK_FEED_CK_BUFG_CASC22",
|
||||
"CLK_FEED_CK_GCLK18",
|
||||
"CLK_FEED_CK_GCLK26",
|
||||
"CLK_FEED_CK_BUFG_CASC20",
|
||||
"CLK_PMV_IMUX35_0",
|
||||
"CLK_FEED_CK_GCLK3",
|
||||
"CLK_PMV_IMUX18_0",
|
||||
"CLK_FEED_SE4C1",
|
||||
"CLK_FEED_NW4A2",
|
||||
"CLK_FEED_WW2END0",
|
||||
"CLK_FEED_CK_BUFG_CASC6",
|
||||
"CLK_FEED_SE2A0",
|
||||
"CLK_PMV_IMUX12_0",
|
||||
"CLK_FEED_WW4A0",
|
||||
"CLK_FEED_EE4BEG2",
|
||||
"CLK_FEED_CK_GCLK10",
|
||||
"CLK_FEED_R_CK_BUFG_CASC30",
|
||||
"CLK_FEED_SW4END3",
|
||||
"CLK_FEED_EL1BEG0",
|
||||
"CLK_PMV_IMUX17_0",
|
||||
"CLK_FEED_EE4BEG0",
|
||||
"CLK_FEED_WR1END3",
|
||||
"CLK_PMV_LOGIC_OUTS16_0",
|
||||
"CLK_FEED_CK_GCLK5",
|
||||
"CLK_FEED_CK_BUFG_CASC30",
|
||||
"CLK_FEED_SE4BEG0",
|
||||
"CLK_PMV_LOGIC_OUTS21_0",
|
||||
"CLK_FEED_EE4BEG1",
|
||||
"CLK_FEED_SE4BEG3",
|
||||
"CLK_FEED_CK_GCLK17",
|
||||
"CLK_FEED_R_CK_BUFG_CASC6",
|
||||
"CLK_FEED_SW4A1",
|
||||
"CLK_FEED_R_CK_GCLK23",
|
||||
"CLK_MTBF2_Q4B",
|
||||
"CLK_FEED_EE2BEG3",
|
||||
"CLK_FEED_R_CK_BUFG_CASC16",
|
||||
"CLK_FEED_R_CK_GCLK21",
|
||||
"CLK_FEED_R_CK_GCLK10",
|
||||
"CLK_FEED_NE4C3",
|
||||
"CLK_FEED_R_CK_BUFG_CASC21",
|
||||
"CLK_PMV_LOGIC_OUTS4_0",
|
||||
"CLK_PMV_IMUX14_0",
|
||||
"CLK_FEED_NW4A0",
|
||||
"CLK_PMV_BYP5_0",
|
||||
"CLK_FEED_SE4BEG2",
|
||||
"CLK_FEED_R_CK_BUFG_CASC31",
|
||||
"CLK_FEED_CK_BUFG_CASC11",
|
||||
"CLK_FEED_R_CK_GCLK20",
|
||||
"CLK_FEED_SW4END0",
|
||||
"CLK_PMV_LOGIC_OUTS7_0",
|
||||
"CLK_PMV_IMUX32_0",
|
||||
"CLK_FEED_CK_BUFG_CASC26",
|
||||
"CLK_MTBF2_Q5B",
|
||||
"CLK_PMV_IMUX9_0",
|
||||
"CLK_MTBF2_Q6B",
|
||||
"CLK_FEED_LH5",
|
||||
"CLK_PMV_IMUX37_0",
|
||||
"CLK_PMV_IMUX7_0",
|
||||
"CLK_FEED_R_CK_GCLK31",
|
||||
"CLK_FEED_WW4B1",
|
||||
"CLK_FEED_CK_GCLK24",
|
||||
"CLK_FEED_WW4END1",
|
||||
"CLK_FEED_R_CK_GCLK17",
|
||||
"CLK_FEED_R_CK_GCLK7",
|
||||
"CLK_FEED_CK_BUFG_CASC28",
|
||||
"CLK_FEED_EE2A3",
|
||||
"CLK_FEED_CK_GCLK14",
|
||||
"CLK_FEED_CK_GCLK13",
|
||||
"CLK_FEED_CK_BUFG_CASC1",
|
||||
"CLK_FEED_R_CK_BUFG_CASC9",
|
||||
"CLK_FEED_LH8",
|
||||
"CLK_FEED_EE4C2",
|
||||
"CLK_FEED_WW4B3",
|
||||
"CLK_FEED_EE4A3",
|
||||
"CLK_MTBF2_EN",
|
||||
"CLK_FEED_NW2A2",
|
||||
"CLK_FEED_CK_BUFG_CASC10",
|
||||
"CLK_FEED_WL1END1",
|
||||
"CLK_PMV_BYP2_0",
|
||||
"CLK_FEED_SE4C3",
|
||||
"CLK_FEED_WL1END2",
|
||||
"CLK_PMV_LOGIC_OUTS13_0",
|
||||
"CLK_FEED_LH3",
|
||||
"CLK_MTBF2_DIN",
|
||||
"CLK_PMV_LOGIC_OUTS0_0",
|
||||
"CLK_PMV_IMUX39_0",
|
||||
"CLK_FEED_R_CK_GCLK13",
|
||||
"CLK_FEED_NW2A3",
|
||||
"CLK_FEED_LH4",
|
||||
"CLK_FEED_EE4B0",
|
||||
"CLK_PMV_IMUX29_0",
|
||||
"CLK_FEED_EE2BEG3",
|
||||
"CLK_FEED_R_CK_BUFG_CASC14",
|
||||
"CLK_FEED_R_CK_BUFG_CASC16",
|
||||
"CLK_FEED_CK_BUFG_CASC12"
|
||||
"CLK_FEED_SE4C2",
|
||||
"CLK_FEED_SW2A3",
|
||||
"CLK_FEED_EE4BEG3",
|
||||
"CLK_FEED_CK_GCLK15",
|
||||
"CLK_FEED_R_CK_GCLK1",
|
||||
"CLK_FEED_R_CK_GCLK15",
|
||||
"CLK_PMV_IMUX38_0",
|
||||
"CLK_FEED_R_CK_GCLK12",
|
||||
"CLK_FEED_R_CK_GCLK28",
|
||||
"CLK_FEED_CK_BUFG_CASC17",
|
||||
"CLK_PMV_LOGIC_OUTS10_0",
|
||||
"CLK_PMV_CLK1_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC13",
|
||||
"CLK_PMV_IMUX2_0",
|
||||
"CLK_FEED_NW4END2",
|
||||
"CLK_FEED_WW4END2",
|
||||
"CLK_PMV_LOGIC_OUTS11_0",
|
||||
"CLK_PMV_IMUX3_0",
|
||||
"CLK_FEED_NE2A3",
|
||||
"CLK_FEED_R_CK_BUFG_CASC3",
|
||||
"CLK_PMV_IMUX42_0"
|
||||
],
|
||||
"tile_type": "CLK_MTBF2",
|
||||
"sites": []
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,377 +1,377 @@
|
|||
{
|
||||
"tile_type": "CLK_PMV2",
|
||||
"pips": {},
|
||||
"wires": [
|
||||
"CLK_FEED_LH4",
|
||||
"CLK_FEED_NE4C2",
|
||||
"CLK_PMV_CLK0_0",
|
||||
"CLK_FEED_EL1BEG2",
|
||||
"CLK_FEED_LH3",
|
||||
"CLK_FEED_WW4END3",
|
||||
"CLK_FEED_CK_BUFG_CASC29",
|
||||
"CLK_PMV_FAN0_0",
|
||||
"CLK_PMV_LOGIC_OUTS17_0",
|
||||
"CLK_FEED_WW4B0",
|
||||
"CLK_PMV_BYP5_0",
|
||||
"CLK_PMV_LOGIC_OUTS21_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC22",
|
||||
"CLK_PMV_LOGIC_OUTS4_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC4",
|
||||
"CLK_FEED_R_CK_BUFG_CASC30",
|
||||
"CLK_FEED_EE2A0",
|
||||
"CLK_PMV_IMUX34_0",
|
||||
"CLK_FEED_CK_BUFG_CASC5",
|
||||
"CLK_PMV_IMUX3_0",
|
||||
"CLK_FEED_R_CK_GCLK1",
|
||||
"CLK_PMV_BYP4_0",
|
||||
"CLK_FEED_NE4BEG0",
|
||||
"CLK_FEED_CK_BUFG_CASC30",
|
||||
"CLK_PMV_LOGIC_OUTS15_0",
|
||||
"CLK_FEED_WW4B2",
|
||||
"CLK_FEED_EE2A2",
|
||||
"CLK_FEED_CK_GCLK28",
|
||||
"CLK_FEED_R_CK_GCLK13",
|
||||
"CLK_FEED_CK_GCLK26",
|
||||
"CLK_FEED_SW4END1",
|
||||
"CLK_FEED_SE2A0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC27",
|
||||
"CLK_PMV_IMUX41_0",
|
||||
"CLK_FEED_CK_GCLK13",
|
||||
"CLK_FEED_CK_GCLK19",
|
||||
"CLK_FEED_LH6",
|
||||
"CLK_FEED_R_CK_BUFG_CASC29",
|
||||
"CLK_FEED_NW4END1",
|
||||
"CLK_FEED_R_CK_BUFG_CASC2",
|
||||
"CLK_FEED_R_CK_BUFG_CASC15",
|
||||
"CLK_PMV_IMUX25_0",
|
||||
"CLK_FEED_NW4A1",
|
||||
"CLK_FEED_CK_GCLK22",
|
||||
"CLK_FEED_EE2A3",
|
||||
"CLK_FEED_NE2A0",
|
||||
"CLK_PMV2_ODIV4",
|
||||
"CLK_FEED_EE4C2",
|
||||
"CLK_PMV_IMUX15_0",
|
||||
"CLK_FEED_EE4A0",
|
||||
"CLK_FEED_EE4BEG3",
|
||||
"CLK_FEED_CK_GCLK6",
|
||||
"CLK_FEED_NW2A0",
|
||||
"CLK_FEED_R_CK_GCLK25",
|
||||
"CLK_FEED_R_CK_BUFG_CASC28",
|
||||
"CLK_PMV2_EN",
|
||||
"CLK_PMV_LOGIC_OUTS3_0",
|
||||
"CLK_FEED_R_CK_GCLK2",
|
||||
"CLK_PMV_FAN7_0",
|
||||
"CLK_PMV_IMUX2_0",
|
||||
"CLK_FEED_NE4BEG1",
|
||||
"CLK_FEED_CK_BUFG_CASC7",
|
||||
"CLK_PMV_IMUX13_0",
|
||||
"CLK_PMV_IMUX16_0",
|
||||
"CLK_FEED_R_CK_GCLK5",
|
||||
"CLK_FEED_WW4END2",
|
||||
"CLK_PMV_CTRL0_0",
|
||||
"CLK_PMV_IMUX31_0",
|
||||
"CLK_FEED_CK_GCLK8",
|
||||
"CLK_FEED_EE4B1",
|
||||
"CLK_FEED_SE2A2",
|
||||
"CLK_FEED_R_CK_GCLK21",
|
||||
"CLK_FEED_WW4C2",
|
||||
"CLK_FEED_NE4BEG2",
|
||||
"CLK_FEED_SE4C2",
|
||||
"CLK_FEED_WW4A2",
|
||||
"CLK_FEED_CK_GCLK20",
|
||||
"CLK_FEED_NW2A2",
|
||||
"CLK_PMV_IMUX33_0",
|
||||
"CLK_PMV_CLK1_0",
|
||||
"CLK_PMV_IMUX9_0",
|
||||
"CLK_PMV_LOGIC_OUTS10_0",
|
||||
"CLK_FEED_CK_BUFG_CASC15",
|
||||
"CLK_FEED_LH10",
|
||||
"CLK_FEED_EL1BEG0",
|
||||
"CLK_PMV_IMUX40_0",
|
||||
"CLK_FEED_CK_GCLK31",
|
||||
"CLK_FEED_NE2A2",
|
||||
"CLK_PMV_IMUX43_0",
|
||||
"CLK_FEED_CK_BUFG_CASC9",
|
||||
"CLK_PMV_LOGIC_OUTS9_0",
|
||||
"CLK_PMV_LOGIC_OUTS20_0",
|
||||
"CLK_FEED_CK_BUFG_CASC17",
|
||||
"CLK_FEED_CK_BUFG_CASC3",
|
||||
"CLK_FEED_WW4B3",
|
||||
"CLK_FEED_R_CK_BUFG_CASC3",
|
||||
"CLK_FEED_CK_BUFG_CASC14",
|
||||
"CLK_PMV_IMUX18_0",
|
||||
"CLK_PMV_IMUX37_0",
|
||||
"CLK_FEED_R_CK_GCLK23",
|
||||
"CLK_PMV_LOGIC_OUTS8_0",
|
||||
"CLK_FEED_SE4C0",
|
||||
"CLK_FEED_WW2A2",
|
||||
"CLK_PMV_IMUX1_0",
|
||||
"CLK_FEED_CK_GCLK17",
|
||||
"CLK_FEED_NE4C0",
|
||||
"CLK_FEED_NW4END2",
|
||||
"CLK_FEED_CK_GCLK29",
|
||||
"CLK_FEED_WL1END0",
|
||||
"CLK_PMV_IMUX36_0",
|
||||
"CLK_FEED_WW2END2",
|
||||
"CLK_FEED_CK_BUFG_CASC26",
|
||||
"CLK_FEED_R_CK_BUFG_CASC26",
|
||||
"CLK_PMV_LOGIC_OUTS11_0",
|
||||
"CLK_FEED_CK_BUFG_CASC0",
|
||||
"CLK_FEED_WW4B1",
|
||||
"CLK_FEED_CK_GCLK0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC19",
|
||||
"CLK_FEED_WL1END2",
|
||||
"CLK_FEED_CK_BUFG_CASC23",
|
||||
"CLK_FEED_R_CK_GCLK6",
|
||||
"CLK_FEED_R_CK_BUFG_CASC23",
|
||||
"CLK_PMV_LOGIC_OUTS17_0",
|
||||
"CLK_FEED_NW4END3",
|
||||
"CLK_FEED_R_CK_GCLK0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC12",
|
||||
"CLK_FEED_EE4C3",
|
||||
"CLK_PMV_LOGIC_OUTS5_0",
|
||||
"CLK_PMV_BYP4_0",
|
||||
"CLK_FEED_CK_BUFG_CASC31",
|
||||
"CLK_FEED_R_CK_GCLK24",
|
||||
"CLK_PMV_LOGIC_OUTS18_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC29",
|
||||
"CLK_FEED_R_CK_BUFG_CASC8",
|
||||
"CLK_FEED_WW4C1",
|
||||
"CLK_FEED_SE2A3",
|
||||
"CLK_PMV_FAN7_0",
|
||||
"CLK_FEED_R_CK_GCLK19",
|
||||
"CLK_FEED_WW4A1",
|
||||
"CLK_FEED_R_CK_BUFG_CASC10",
|
||||
"CLK_PMV_FAN2_0",
|
||||
"CLK_PMV_BYP7_0",
|
||||
"CLK_FEED_EE4A2",
|
||||
"CLK_FEED_R_CK_BUFG_CASC7",
|
||||
"CLK_FEED_R_CK_BUFG_CASC2",
|
||||
"CLK_FEED_R_CK_GCLK9",
|
||||
"CLK_PMV_IMUX10_0",
|
||||
"CLK_FEED_CK_BUFG_CASC19",
|
||||
"CLK_PMV_IMUX5_0",
|
||||
"CLK_FEED_EE2BEG2",
|
||||
"CLK_FEED_EE2A2",
|
||||
"CLK_FEED_R_CK_BUFG_CASC5",
|
||||
"CLK_FEED_CK_BUFG_CASC4",
|
||||
"CLK_FEED_CK_GCLK19",
|
||||
"CLK_FEED_R_CK_BUFG_CASC17",
|
||||
"CLK_FEED_SW4A3",
|
||||
"CLK_PMV_IMUX23_0",
|
||||
"CLK_FEED_WW4C3",
|
||||
"CLK_FEED_LH10",
|
||||
"CLK_FEED_R_CK_GCLK29",
|
||||
"CLK_FEED_CK_GCLK11",
|
||||
"CLK_FEED_CK_GCLK7",
|
||||
"CLK_FEED_R_CK_BUFG_CASC27",
|
||||
"CLK_FEED_R_CK_BUFG_CASC11",
|
||||
"CLK_FEED_ER1BEG2",
|
||||
"CLK_FEED_R_CK_GCLK31",
|
||||
"CLK_PMV_LOGIC_OUTS13_0",
|
||||
"CLK_FEED_SE4BEG3",
|
||||
"CLK_PMV_IMUX20_0",
|
||||
"CLK_FEED_LH7",
|
||||
"CLK_FEED_NW2A3",
|
||||
"CLK_FEED_NW4A0",
|
||||
"CLK_FEED_EL1BEG3",
|
||||
"CLK_FEED_CK_GCLK1",
|
||||
"CLK_FEED_NE4C2",
|
||||
"CLK_FEED_CK_BUFG_CASC21",
|
||||
"CLK_FEED_EE4C1",
|
||||
"CLK_FEED_CK_BUFG_CASC12",
|
||||
"CLK_FEED_R_CK_GCLK2",
|
||||
"CLK_FEED_SE2A1",
|
||||
"CLK_FEED_CK_BUFG_CASC14",
|
||||
"CLK_FEED_ER1BEG3",
|
||||
"CLK_FEED_WW4C0",
|
||||
"CLK_FEED_CK_BUFG_CASC23",
|
||||
"CLK_FEED_CK_GCLK4",
|
||||
"CLK_FEED_ER1BEG1",
|
||||
"CLK_PMV_BYP6_0",
|
||||
"CLK_FEED_NW4A3",
|
||||
"CLK_FEED_R_CK_BUFG_CASC0",
|
||||
"CLK_PMV2_A0",
|
||||
"CLK_PMV_FAN0_0",
|
||||
"CLK_FEED_ER1BEG0",
|
||||
"CLK_PMV_IMUX31_0",
|
||||
"CLK_PMV_LOGIC_OUTS14_0",
|
||||
"CLK_FEED_CK_GCLK16",
|
||||
"CLK_FEED_CK_GCLK29",
|
||||
"CLK_FEED_R_CK_GCLK26",
|
||||
"CLK_PMV_LOGIC_OUTS3_0",
|
||||
"CLK_FEED_WW4C2",
|
||||
"CLK_FEED_R_CK_BUFG_CASC4",
|
||||
"CLK_FEED_R_CK_GCLK16",
|
||||
"CLK_FEED_CK_GCLK23",
|
||||
"CLK_FEED_EE4A0",
|
||||
"CLK_FEED_WR1END1",
|
||||
"CLK_FEED_NE4C0",
|
||||
"CLK_FEED_CK_BUFG_CASC16",
|
||||
"CLK_PMV_FAN1_0",
|
||||
"CLK_FEED_R_CK_GCLK5",
|
||||
"CLK_FEED_R_CK_BUFG_CASC19",
|
||||
"CLK_FEED_CK_GCLK6",
|
||||
"CLK_FEED_EE4B1",
|
||||
"CLK_FEED_CK_GCLK25",
|
||||
"CLK_FEED_EE4A1",
|
||||
"CLK_FEED_CK_GCLK9",
|
||||
"CLK_FEED_SW4END1",
|
||||
"CLK_FEED_SW4END2",
|
||||
"CLK_PMV_LOGIC_OUTS12_0",
|
||||
"CLK_FEED_CK_GCLK2",
|
||||
"CLK_FEED_WW2A3",
|
||||
"CLK_FEED_NE2A0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC14",
|
||||
"CLK_PMV_IMUX44_0",
|
||||
"CLK_FEED_CK_BUFG_CASC7",
|
||||
"CLK_FEED_CK_BUFG_CASC27",
|
||||
"CLK_PMV_IMUX8_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC1",
|
||||
"CLK_FEED_WW4A3",
|
||||
"CLK_PMV_IMUX1_0",
|
||||
"CLK_FEED_SW4A0",
|
||||
"CLK_PMV_LOGIC_OUTS2_0",
|
||||
"CLK_FEED_EE4C0",
|
||||
"CLK_PMV2_O",
|
||||
"CLK_FEED_CK_BUFG_CASC5",
|
||||
"CLK_FEED_CK_BUFG_CASC13",
|
||||
"CLK_FEED_CK_GCLK21",
|
||||
"CLK_PMV_FAN3_0",
|
||||
"CLK_FEED_CK_GCLK28",
|
||||
"CLK_PMV_IMUX15_0",
|
||||
"CLK_PMV_IMUX26_0",
|
||||
"CLK_PMV_CTRL1_0",
|
||||
"CLK_PMV_FAN5_0",
|
||||
"CLK_FEED_NE4BEG2",
|
||||
"CLK_FEED_WW2A2",
|
||||
"CLK_FEED_WR1END2",
|
||||
"CLK_PMV_CTRL0_0",
|
||||
"CLK_FEED_EL1BEG2",
|
||||
"CLK_PMV_IMUX30_0",
|
||||
"CLK_FEED_LH1",
|
||||
"CLK_FEED_CK_BUFG_CASC8",
|
||||
"CLK_FEED_R_CK_GCLK30",
|
||||
"CLK_PMV_LOGIC_OUTS9_0",
|
||||
"CLK_FEED_WW2A0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC15",
|
||||
"CLK_FEED_R_CK_GCLK3",
|
||||
"CLK_FEED_WW4A2",
|
||||
"CLK_PMV_IMUX13_0",
|
||||
"CLK_FEED_EL1BEG1",
|
||||
"CLK_FEED_WL1END0",
|
||||
"CLK_FEED_SE2A2",
|
||||
"CLK_PMV2_A2",
|
||||
"CLK_FEED_WW4END3",
|
||||
"CLK_FEED_R_CK_BUFG_CASC28",
|
||||
"CLK_FEED_NW4END0",
|
||||
"CLK_FEED_SW4A2",
|
||||
"CLK_PMV_IMUX22_0",
|
||||
"CLK_PMV_IMUX4_0",
|
||||
"CLK_FEED_WW2A0",
|
||||
"CLK_FEED_EE4B2",
|
||||
"CLK_PMV2_A0",
|
||||
"CLK_FEED_SW2A3",
|
||||
"CLK_PMV_IMUX45_0",
|
||||
"CLK_FEED_EE2A1",
|
||||
"CLK_FEED_CK_BUFG_CASC21",
|
||||
"CLK_FEED_R_CK_GCLK3",
|
||||
"CLK_FEED_EE4C1",
|
||||
"CLK_FEED_SW4END3",
|
||||
"CLK_FEED_WR1END3",
|
||||
"CLK_FEED_EE4C3",
|
||||
"CLK_FEED_R_CK_GCLK8",
|
||||
"CLK_FEED_CK_BUFG_CASC1",
|
||||
"CLK_FEED_R_CK_GCLK10",
|
||||
"CLK_FEED_SW4A2",
|
||||
"CLK_PMV_FAN1_0",
|
||||
"CLK_FEED_R_CK_GCLK7",
|
||||
"CLK_PMV_BYP3_0",
|
||||
"CLK_FEED_NW4END1",
|
||||
"CLK_PMV_LOGIC_OUTS15_0",
|
||||
"CLK_FEED_WW2A1",
|
||||
"CLK_FEED_EE2A0",
|
||||
"CLK_FEED_EE2BEG0",
|
||||
"CLK_PMV_IMUX20_0",
|
||||
"CLK_PMV_BYP0_0",
|
||||
"CLK_PMV2_ODIV2",
|
||||
"CLK_FEED_NE4C1",
|
||||
"CLK_FEED_CK_GCLK20",
|
||||
"CLK_FEED_R_CK_GCLK11",
|
||||
"CLK_FEED_LH6",
|
||||
"CLK_FEED_NE4BEG0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC24",
|
||||
"CLK_FEED_NW2A1",
|
||||
"CLK_FEED_CK_GCLK12",
|
||||
"CLK_FEED_CK_BUFG_CASC2",
|
||||
"CLK_FEED_CK_GCLK22",
|
||||
"CLK_FEED_WL1END3",
|
||||
"CLK_FEED_R_CK_GCLK4",
|
||||
"CLK_FEED_WW4A0",
|
||||
"CLK_FEED_CK_BUFG_CASC28",
|
||||
"CLK_FEED_CK_GCLK31",
|
||||
"CLK_FEED_R_CK_BUFG_CASC11",
|
||||
"CLK_PMV_IMUX7_0",
|
||||
"CLK_PMV_BYP7_0",
|
||||
"CLK_PMV_IMUX33_0",
|
||||
"CLK_PMV_IMUX0_0",
|
||||
"CLK_FEED_LH9",
|
||||
"CLK_FEED_R_CK_GCLK6",
|
||||
"CLK_FEED_CK_GCLK30",
|
||||
"CLK_PMV_IMUX24_0",
|
||||
"CLK_FEED_NE4BEG3",
|
||||
"CLK_PMV_BYP1_0",
|
||||
"CLK_PMV_LOGIC_OUTS7_0",
|
||||
"CLK_FEED_WW2A3",
|
||||
"CLK_PMV_FAN2_0",
|
||||
"CLK_PMV_LOGIC_OUTS2_0",
|
||||
"CLK_FEED_R_CK_GCLK27",
|
||||
"CLK_FEED_CK_BUFG_CASC3",
|
||||
"CLK_FEED_R_CK_GCLK18",
|
||||
"CLK_FEED_WW2END2",
|
||||
"CLK_FEED_EE2BEG1",
|
||||
"CLK_FEED_WW4END0",
|
||||
"CLK_FEED_CK_BUFG_CASC25",
|
||||
"CLK_PMV_IMUX16_0",
|
||||
"CLK_FEED_LH2",
|
||||
"CLK_PMV_LOGIC_OUTS6_0",
|
||||
"CLK_FEED_R_CK_GCLK25",
|
||||
"CLK_PMV_CLK0_0",
|
||||
"CLK_PMV_IMUX11_0",
|
||||
"CLK_FEED_EE4B3",
|
||||
"CLK_FEED_CK_BUFG_CASC24",
|
||||
"CLK_FEED_WW2END1",
|
||||
"CLK_PMV_LOGIC_OUTS23_0",
|
||||
"CLK_FEED_LH12",
|
||||
"CLK_FEED_LH7",
|
||||
"CLK_FEED_R_CK_GCLK14",
|
||||
"CLK_FEED_SW2A1",
|
||||
"CLK_PMV_IMUX6_0",
|
||||
"CLK_PMV_LOGIC_OUTS22_0",
|
||||
"CLK_PMV_IMUX23_0",
|
||||
"CLK_FEED_EE2BEG0",
|
||||
"CLK_FEED_CK_BUFG_CASC2",
|
||||
"CLK_FEED_CK_BUFG_CASC24",
|
||||
"CLK_FEED_EE2BEG2",
|
||||
"CLK_FEED_LH1",
|
||||
"CLK_FEED_CK_BUFG_CASC22",
|
||||
"CLK_PMV_IMUX11_0",
|
||||
"CLK_FEED_SE4C1",
|
||||
"CLK_PMV_LOGIC_OUTS23_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC25",
|
||||
"CLK_FEED_NE4C3",
|
||||
"CLK_PMV_FAN3_0",
|
||||
"CLK_FEED_SE2A1",
|
||||
"CLK_FEED_NE2A1",
|
||||
"CLK_FEED_R_CK_BUFG_CASC18",
|
||||
"CLK_PMV_LOGIC_OUTS19_0",
|
||||
"CLK_FEED_WW2END3",
|
||||
"CLK_FEED_MONITOR_N",
|
||||
"CLK_FEED_R_CK_BUFG_CASC17",
|
||||
"CLK_FEED_ER1BEG1",
|
||||
"CLK_FEED_EE4BEG1",
|
||||
"CLK_PMV_IMUX35_0",
|
||||
"CLK_FEED_WR1END1",
|
||||
"CLK_FEED_R_CK_GCLK26",
|
||||
"CLK_PMV_IMUX19_0",
|
||||
"CLK_PMV_LOGIC_OUTS0_0",
|
||||
"CLK_FEED_R_CK_GCLK16",
|
||||
"CLK_PMV_FAN5_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC9",
|
||||
"CLK_FEED_EE4BEG2",
|
||||
"CLK_PMV_LOGIC_OUTS12_0",
|
||||
"CLK_PMV_BYP3_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC7",
|
||||
"CLK_FEED_WW4C3",
|
||||
"CLK_FEED_R_CK_GCLK29",
|
||||
"CLK_FEED_CK_BUFG_CASC6",
|
||||
"CLK_PMV_IMUX43_0",
|
||||
"CLK_FEED_LH2",
|
||||
"CLK_FEED_SW4END2",
|
||||
"CLK_FEED_WW4END0",
|
||||
"CLK_PMV2_A1",
|
||||
"CLK_PMV2_ODIV2",
|
||||
"CLK_FEED_CK_GCLK12",
|
||||
"CLK_PMV2_O",
|
||||
"CLK_FEED_CK_BUFG_CASC31",
|
||||
"CLK_FEED_R_CK_GCLK9",
|
||||
"CLK_FEED_NW2A1",
|
||||
"CLK_FEED_CK_BUFG_CASC11",
|
||||
"CLK_FEED_LH9",
|
||||
"CLK_FEED_WW2END0",
|
||||
"CLK_FEED_CK_GCLK9",
|
||||
"CLK_FEED_R_CK_GCLK22",
|
||||
"CLK_PMV_IMUX24_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC10",
|
||||
"CLK_FEED_EE4BEG0",
|
||||
"CLK_PMV_IMUX10_0",
|
||||
"CLK_FEED_NW4END0",
|
||||
"CLK_FEED_CK_GCLK7",
|
||||
"CLK_FEED_CK_BUFG_CASC19",
|
||||
"CLK_FEED_EE2BEG1",
|
||||
"CLK_FEED_SE4BEG0",
|
||||
"CLK_FEED_R_CK_GCLK27",
|
||||
"CLK_FEED_CK_GCLK30",
|
||||
"CLK_FEED_R_CK_BUFG_CASC12",
|
||||
"CLK_FEED_CK_BUFG_CASC4",
|
||||
"CLK_FEED_CK_BUFG_CASC20",
|
||||
"CLK_PMV_IMUX28_0",
|
||||
"CLK_PMV_BYP6_0",
|
||||
"CLK_PMV_LOGIC_OUTS5_0",
|
||||
"CLK_FEED_R_CK_GCLK20",
|
||||
"CLK_FEED_SE2A3",
|
||||
"CLK_PMV_IMUX40_0",
|
||||
"CLK_FEED_SW2A2",
|
||||
"CLK_FEED_NE4C1",
|
||||
"CLK_FEED_SE4BEG1",
|
||||
"CLK_FEED_ER1BEG0",
|
||||
"CLK_PMV_LOGIC_OUTS16_0",
|
||||
"CLK_PMV_IMUX42_0",
|
||||
"CLK_FEED_EE4A1",
|
||||
"CLK_FEED_WW4C0",
|
||||
"CLK_FEED_R_CK_GCLK11",
|
||||
"CLK_FEED_NE2A3",
|
||||
"CLK_FEED_SW4A3",
|
||||
"CLK_PMV_LOGIC_OUTS6_0",
|
||||
"CLK_PMV_IMUX27_0",
|
||||
"CLK_FEED_NW4A2",
|
||||
"CLK_PMV_IMUX38_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC1",
|
||||
"CLK_PMV_IMUX30_0",
|
||||
"CLK_PMV_LOGIC_OUTS14_0",
|
||||
"CLK_FEED_CK_GCLK23",
|
||||
"CLK_FEED_CK_GCLK18",
|
||||
"CLK_FEED_R_CK_BUFG_CASC20",
|
||||
"CLK_FEED_NE4BEG3",
|
||||
"CLK_FEED_CK_GCLK16",
|
||||
"CLK_FEED_SW4A1",
|
||||
"CLK_FEED_R_CK_BUFG_CASC23",
|
||||
"CLK_FEED_CK_GCLK21",
|
||||
"CLK_FEED_MONITOR_P",
|
||||
"CLK_FEED_LH8",
|
||||
"CLK_FEED_WL1END3",
|
||||
"CLK_FEED_R_CK_GCLK18",
|
||||
"CLK_FEED_WW4END1",
|
||||
"CLK_FEED_LH5",
|
||||
"CLK_FEED_SW4END0",
|
||||
"CLK_FEED_WW4A1",
|
||||
"CLK_FEED_R_CK_GCLK15",
|
||||
"CLK_FEED_CK_BUFG_CASC18",
|
||||
"CLK_FEED_R_CK_BUFG_CASC6",
|
||||
"CLK_FEED_ER1BEG3",
|
||||
"CLK_FEED_SE4BEG2",
|
||||
"CLK_FEED_CK_GCLK1",
|
||||
"CLK_FEED_WR1END2",
|
||||
"CLK_FEED_NW4A3",
|
||||
"CLK_FEED_CK_GCLK24",
|
||||
"CLK_FEED_EE4A3",
|
||||
"CLK_FEED_R_CK_BUFG_CASC0",
|
||||
"CLK_PMV_LOGIC_OUTS18_0",
|
||||
"CLK_FEED_R_CK_GCLK12",
|
||||
"CLK_PMV_CTRL1_0",
|
||||
"CLK_FEED_CK_GCLK14",
|
||||
"CLK_PMV_FAN4_0",
|
||||
"CLK_FEED_CK_GCLK4",
|
||||
"CLK_FEED_EE4C0",
|
||||
"CLK_FEED_EE4B3",
|
||||
"CLK_FEED_R_CK_GCLK24",
|
||||
"CLK_FEED_EE4A2",
|
||||
"CLK_PMV_IMUX44_0",
|
||||
"CLK_PMV_IMUX21_0",
|
||||
"CLK_FEED_R_CK_GCLK30",
|
||||
"CLK_FEED_R_CK_BUFG_CASC24",
|
||||
"CLK_FEED_CK_BUFG_CASC13",
|
||||
"CLK_FEED_R_CK_BUFG_CASC5",
|
||||
"CLK_FEED_NW4END3",
|
||||
"CLK_PMV_BYP0_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC21",
|
||||
"CLK_PMV_IMUX47_0",
|
||||
"CLK_FEED_WW4C1",
|
||||
"CLK_PMV_IMUX32_0",
|
||||
"CLK_PMV_LOGIC_OUTS1_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC8",
|
||||
"CLK_FEED_SE4C3",
|
||||
"CLK_PMV_IMUX26_0",
|
||||
"CLK_FEED_CK_BUFG_CASC10",
|
||||
"CLK_FEED_SW4A0",
|
||||
"CLK_FEED_CK_BUFG_CASC27",
|
||||
"CLK_FEED_R_CK_BUFG_CASC13",
|
||||
"CLK_PMV_IMUX17_0",
|
||||
"CLK_FEED_NE2A2",
|
||||
"CLK_FEED_SW2A1",
|
||||
"CLK_FEED_CK_GCLK15",
|
||||
"CLK_FEED_SW2A0",
|
||||
"CLK_FEED_CK_GCLK11",
|
||||
"CLK_PMV_IMUX46_0",
|
||||
"CLK_FEED_CK_BUFG_CASC25",
|
||||
"CLK_PMV_IMUX12_0",
|
||||
"CLK_FEED_CK_GCLK2",
|
||||
"CLK_FEED_CK_GCLK25",
|
||||
"CLK_PMV_IMUX14_0",
|
||||
"CLK_FEED_R_CK_GCLK0",
|
||||
"CLK_FEED_CK_GCLK3",
|
||||
"CLK_PMV2_A2",
|
||||
"CLK_FEED_WL1END1",
|
||||
"CLK_FEED_R_CK_GCLK14",
|
||||
"CLK_PMV_IMUX0_0",
|
||||
"CLK_FEED_CK_GCLK10",
|
||||
"CLK_FEED_WW2END1",
|
||||
"CLK_FEED_WW4A3",
|
||||
"CLK_FEED_R_CK_BUFG_CASC31",
|
||||
"CLK_FEED_CK_GCLK5",
|
||||
"CLK_FEED_NW4A1",
|
||||
"CLK_FEED_CK_GCLK27",
|
||||
"CLK_FEED_CK_BUFG_CASC16",
|
||||
"CLK_FEED_R_CK_GCLK28",
|
||||
"CLK_FEED_EL1BEG1",
|
||||
"CLK_FEED_R_CK_GCLK19",
|
||||
"CLK_FEED_CK_BUFG_CASC8",
|
||||
"CLK_PMV_IMUX5_0",
|
||||
"CLK_FEED_LH12",
|
||||
"CLK_FEED_R_CK_GCLK17",
|
||||
"CLK_FEED_R_CK_BUFG_CASC18",
|
||||
"CLK_FEED_MONITOR_P",
|
||||
"CLK_FEED_SE4BEG1",
|
||||
"CLK_FEED_MONITOR_N",
|
||||
"CLK_PMV_IMUX47_0",
|
||||
"CLK_PMV_IMUX45_0",
|
||||
"CLK_FEED_CK_BUFG_CASC18",
|
||||
"CLK_PMV_IMUX36_0",
|
||||
"CLK_PMV_LOGIC_OUTS8_0",
|
||||
"CLK_FEED_CK_BUFG_CASC15",
|
||||
"CLK_PMV_LOGIC_OUTS19_0",
|
||||
"CLK_PMV_IMUX34_0",
|
||||
"CLK_FEED_SW2A0",
|
||||
"CLK_FEED_CK_BUFG_CASC0",
|
||||
"CLK_FEED_WR1END0",
|
||||
"CLK_FEED_LH11",
|
||||
"CLK_PMV_BYP2_0",
|
||||
"CLK_FEED_WW2A1",
|
||||
"CLK_PMV_IMUX8_0",
|
||||
"CLK_FEED_EL1BEG3",
|
||||
"CLK_PMV_IMUX39_0",
|
||||
"CLK_FEED_CK_BUFG_CASC29",
|
||||
"CLK_PMV_IMUX21_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC20",
|
||||
"CLK_PMV_IMUX41_0",
|
||||
"CLK_PMV_IMUX27_0",
|
||||
"CLK_PMV_IMUX25_0",
|
||||
"CLK_FEED_NE4BEG1",
|
||||
"CLK_PMV_FAN6_0",
|
||||
"CLK_FEED_WW4B0",
|
||||
"CLK_PMV_LOGIC_OUTS1_0",
|
||||
"CLK_PMV_IMUX28_0",
|
||||
"CLK_FEED_NE2A1",
|
||||
"CLK_PMV_FAN4_0",
|
||||
"CLK_FEED_SE4C0",
|
||||
"CLK_FEED_R_CK_GCLK22",
|
||||
"CLK_FEED_R_CK_GCLK8",
|
||||
"CLK_PMV_LOGIC_OUTS20_0",
|
||||
"CLK_PMV_IMUX19_0",
|
||||
"CLK_FEED_WW2END3",
|
||||
"CLK_FEED_R_CK_BUFG_CASC25",
|
||||
"CLK_FEED_EE2A1",
|
||||
"CLK_FEED_EE4B2",
|
||||
"CLK_FEED_CK_GCLK0",
|
||||
"CLK_FEED_WW4B2",
|
||||
"CLK_PMV_IMUX46_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC26",
|
||||
"CLK_FEED_R_CK_BUFG_CASC22",
|
||||
"CLK_FEED_SW2A2",
|
||||
"CLK_FEED_CK_GCLK8",
|
||||
"CLK_FEED_LH11",
|
||||
"CLK_FEED_NW2A0",
|
||||
"CLK_FEED_CK_BUFG_CASC22",
|
||||
"CLK_FEED_CK_GCLK18",
|
||||
"CLK_FEED_CK_GCLK26",
|
||||
"CLK_FEED_CK_BUFG_CASC20",
|
||||
"CLK_PMV_IMUX35_0",
|
||||
"CLK_FEED_CK_GCLK3",
|
||||
"CLK_PMV_IMUX18_0",
|
||||
"CLK_FEED_SE4C1",
|
||||
"CLK_FEED_NW4A2",
|
||||
"CLK_FEED_WW2END0",
|
||||
"CLK_PMV2_A1",
|
||||
"CLK_FEED_CK_BUFG_CASC6",
|
||||
"CLK_FEED_SE2A0",
|
||||
"CLK_PMV_IMUX12_0",
|
||||
"CLK_FEED_WW4A0",
|
||||
"CLK_FEED_EE4BEG2",
|
||||
"CLK_FEED_CK_GCLK10",
|
||||
"CLK_FEED_R_CK_BUFG_CASC30",
|
||||
"CLK_FEED_SW4END3",
|
||||
"CLK_FEED_EL1BEG0",
|
||||
"CLK_PMV_IMUX17_0",
|
||||
"CLK_FEED_EE4BEG0",
|
||||
"CLK_FEED_WR1END3",
|
||||
"CLK_PMV_LOGIC_OUTS16_0",
|
||||
"CLK_PMV2_ODIV4",
|
||||
"CLK_FEED_CK_GCLK5",
|
||||
"CLK_FEED_CK_BUFG_CASC30",
|
||||
"CLK_FEED_SE4BEG0",
|
||||
"CLK_PMV_LOGIC_OUTS21_0",
|
||||
"CLK_FEED_EE4BEG1",
|
||||
"CLK_FEED_SE4BEG3",
|
||||
"CLK_FEED_CK_GCLK17",
|
||||
"CLK_FEED_R_CK_BUFG_CASC6",
|
||||
"CLK_FEED_SW4A1",
|
||||
"CLK_FEED_R_CK_GCLK23",
|
||||
"CLK_FEED_EE2BEG3",
|
||||
"CLK_FEED_R_CK_BUFG_CASC16",
|
||||
"CLK_FEED_R_CK_GCLK21",
|
||||
"CLK_FEED_R_CK_GCLK10",
|
||||
"CLK_FEED_NE4C3",
|
||||
"CLK_FEED_R_CK_BUFG_CASC21",
|
||||
"CLK_PMV_LOGIC_OUTS4_0",
|
||||
"CLK_PMV_IMUX14_0",
|
||||
"CLK_FEED_NW4A0",
|
||||
"CLK_PMV_BYP5_0",
|
||||
"CLK_FEED_SE4BEG2",
|
||||
"CLK_FEED_R_CK_BUFG_CASC31",
|
||||
"CLK_FEED_CK_BUFG_CASC11",
|
||||
"CLK_FEED_R_CK_GCLK20",
|
||||
"CLK_FEED_SW4END0",
|
||||
"CLK_PMV2_EN",
|
||||
"CLK_PMV_LOGIC_OUTS7_0",
|
||||
"CLK_PMV_IMUX32_0",
|
||||
"CLK_FEED_CK_BUFG_CASC26",
|
||||
"CLK_PMV_IMUX9_0",
|
||||
"CLK_FEED_LH5",
|
||||
"CLK_PMV_IMUX37_0",
|
||||
"CLK_PMV_IMUX7_0",
|
||||
"CLK_FEED_R_CK_GCLK31",
|
||||
"CLK_FEED_WW4B1",
|
||||
"CLK_FEED_CK_GCLK24",
|
||||
"CLK_FEED_WW4END1",
|
||||
"CLK_FEED_R_CK_GCLK17",
|
||||
"CLK_FEED_R_CK_GCLK7",
|
||||
"CLK_FEED_CK_BUFG_CASC28",
|
||||
"CLK_FEED_EE2A3",
|
||||
"CLK_FEED_CK_GCLK14",
|
||||
"CLK_FEED_CK_GCLK13",
|
||||
"CLK_FEED_CK_BUFG_CASC1",
|
||||
"CLK_FEED_R_CK_BUFG_CASC9",
|
||||
"CLK_FEED_LH8",
|
||||
"CLK_FEED_EE4C2",
|
||||
"CLK_FEED_WW4B3",
|
||||
"CLK_FEED_EE4A3",
|
||||
"CLK_FEED_NW2A2",
|
||||
"CLK_FEED_CK_BUFG_CASC10",
|
||||
"CLK_FEED_WL1END1",
|
||||
"CLK_PMV_BYP2_0",
|
||||
"CLK_FEED_SE4C3",
|
||||
"CLK_FEED_WL1END2",
|
||||
"CLK_PMV_LOGIC_OUTS13_0",
|
||||
"CLK_FEED_LH3",
|
||||
"CLK_PMV_LOGIC_OUTS0_0",
|
||||
"CLK_PMV_IMUX39_0",
|
||||
"CLK_FEED_R_CK_GCLK13",
|
||||
"CLK_FEED_NW2A3",
|
||||
"CLK_FEED_LH4",
|
||||
"CLK_FEED_EE4B0",
|
||||
"CLK_PMV_IMUX29_0",
|
||||
"CLK_FEED_EE2BEG3",
|
||||
"CLK_FEED_R_CK_BUFG_CASC14",
|
||||
"CLK_FEED_R_CK_BUFG_CASC16",
|
||||
"CLK_FEED_CK_BUFG_CASC12"
|
||||
"CLK_FEED_SE4C2",
|
||||
"CLK_FEED_SW2A3",
|
||||
"CLK_FEED_EE4BEG3",
|
||||
"CLK_FEED_CK_GCLK15",
|
||||
"CLK_FEED_R_CK_GCLK1",
|
||||
"CLK_FEED_R_CK_GCLK15",
|
||||
"CLK_FEED_R_CK_GCLK12",
|
||||
"CLK_PMV_IMUX38_0",
|
||||
"CLK_FEED_R_CK_GCLK28",
|
||||
"CLK_FEED_CK_BUFG_CASC17",
|
||||
"CLK_PMV_LOGIC_OUTS10_0",
|
||||
"CLK_PMV_CLK1_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC13",
|
||||
"CLK_PMV_IMUX2_0",
|
||||
"CLK_FEED_NW4END2",
|
||||
"CLK_FEED_WW4END2",
|
||||
"CLK_PMV_LOGIC_OUTS11_0",
|
||||
"CLK_PMV_IMUX3_0",
|
||||
"CLK_FEED_NE2A3",
|
||||
"CLK_FEED_R_CK_BUFG_CASC3",
|
||||
"CLK_PMV_IMUX42_0"
|
||||
],
|
||||
"tile_type": "CLK_PMV2",
|
||||
"sites": [
|
||||
{
|
||||
"x_coord": 0,
|
||||
"type": "PMV2",
|
||||
"y_coord": 0,
|
||||
"name": "X0Y0",
|
||||
"prefix": "PMV",
|
||||
"x_coord": 0,
|
||||
"site_pins": {
|
||||
"A0": "CLK_PMV2_A0",
|
||||
"O": "CLK_PMV2_O",
|
||||
"A2": "CLK_PMV2_A2",
|
||||
"ODIV2": "CLK_PMV2_ODIV2",
|
||||
"ODIV4": "CLK_PMV2_ODIV4",
|
||||
"EN": "CLK_PMV2_EN",
|
||||
"ODIV2": "CLK_PMV2_ODIV2",
|
||||
"A1": "CLK_PMV2_A1"
|
||||
}
|
||||
},
|
||||
"name": "X0Y0",
|
||||
"prefix": "PMV"
|
||||
}
|
||||
]
|
||||
}
|
||||
|
|
@ -1,360 +1,360 @@
|
|||
{
|
||||
"tile_type": "CLK_PMV2_SVT",
|
||||
"pips": {},
|
||||
"wires": [
|
||||
"CLK_FEED_LH4",
|
||||
"CLK_FEED_NE4C2",
|
||||
"CLK_PMV_CLK0_0",
|
||||
"CLK_FEED_EL1BEG2",
|
||||
"CLK_FEED_LH3",
|
||||
"CLK_FEED_WW4END3",
|
||||
"CLK_FEED_CK_BUFG_CASC29",
|
||||
"CLK_PMV_FAN0_0",
|
||||
"CLK_PMV_LOGIC_OUTS17_0",
|
||||
"CLK_FEED_WW4B0",
|
||||
"CLK_PMV_BYP5_0",
|
||||
"CLK_PMV_LOGIC_OUTS21_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC22",
|
||||
"CLK_PMV_LOGIC_OUTS4_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC4",
|
||||
"CLK_FEED_R_CK_BUFG_CASC30",
|
||||
"CLK_FEED_EE2A0",
|
||||
"CLK_PMV_IMUX34_0",
|
||||
"CLK_FEED_CK_BUFG_CASC5",
|
||||
"CLK_PMV_IMUX3_0",
|
||||
"CLK_FEED_R_CK_GCLK1",
|
||||
"CLK_PMV_BYP4_0",
|
||||
"CLK_FEED_NE4BEG0",
|
||||
"CLK_FEED_CK_BUFG_CASC30",
|
||||
"CLK_PMV_LOGIC_OUTS15_0",
|
||||
"CLK_FEED_WW4B2",
|
||||
"CLK_FEED_EE2A2",
|
||||
"CLK_FEED_CK_GCLK28",
|
||||
"CLK_FEED_R_CK_GCLK13",
|
||||
"CLK_FEED_CK_GCLK26",
|
||||
"CLK_FEED_SW4END1",
|
||||
"CLK_FEED_SE2A0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC27",
|
||||
"CLK_PMV_IMUX41_0",
|
||||
"CLK_FEED_CK_GCLK13",
|
||||
"CLK_FEED_CK_GCLK19",
|
||||
"CLK_FEED_LH6",
|
||||
"CLK_FEED_R_CK_BUFG_CASC29",
|
||||
"CLK_FEED_NW4END1",
|
||||
"CLK_FEED_R_CK_BUFG_CASC2",
|
||||
"CLK_FEED_R_CK_BUFG_CASC15",
|
||||
"CLK_PMV_IMUX25_0",
|
||||
"CLK_FEED_NW4A1",
|
||||
"CLK_FEED_CK_GCLK22",
|
||||
"CLK_FEED_EE2A3",
|
||||
"CLK_FEED_NE2A0",
|
||||
"CLK_PMV2_ODIV4",
|
||||
"CLK_FEED_EE4C2",
|
||||
"CLK_PMV_IMUX15_0",
|
||||
"CLK_FEED_EE4A0",
|
||||
"CLK_FEED_EE4BEG3",
|
||||
"CLK_FEED_CK_GCLK6",
|
||||
"CLK_FEED_NW2A0",
|
||||
"CLK_FEED_R_CK_GCLK25",
|
||||
"CLK_FEED_R_CK_BUFG_CASC28",
|
||||
"CLK_PMV2_EN",
|
||||
"CLK_PMV_LOGIC_OUTS3_0",
|
||||
"CLK_FEED_R_CK_GCLK2",
|
||||
"CLK_PMV_FAN7_0",
|
||||
"CLK_PMV_IMUX2_0",
|
||||
"CLK_FEED_NE4BEG1",
|
||||
"CLK_FEED_CK_BUFG_CASC7",
|
||||
"CLK_PMV_IMUX13_0",
|
||||
"CLK_PMV_IMUX16_0",
|
||||
"CLK_FEED_R_CK_GCLK5",
|
||||
"CLK_FEED_WW4END2",
|
||||
"CLK_PMV_CTRL0_0",
|
||||
"CLK_PMV_IMUX31_0",
|
||||
"CLK_FEED_CK_GCLK8",
|
||||
"CLK_FEED_EE4B1",
|
||||
"CLK_FEED_SE2A2",
|
||||
"CLK_FEED_R_CK_GCLK21",
|
||||
"CLK_FEED_WW4C2",
|
||||
"CLK_FEED_NE4BEG2",
|
||||
"CLK_FEED_SE4C2",
|
||||
"CLK_FEED_WW4A2",
|
||||
"CLK_FEED_CK_GCLK20",
|
||||
"CLK_FEED_NW2A2",
|
||||
"CLK_PMV_IMUX33_0",
|
||||
"CLK_PMV_CLK1_0",
|
||||
"CLK_PMV_IMUX9_0",
|
||||
"CLK_PMV_LOGIC_OUTS10_0",
|
||||
"CLK_FEED_CK_BUFG_CASC15",
|
||||
"CLK_FEED_LH10",
|
||||
"CLK_FEED_EL1BEG0",
|
||||
"CLK_PMV_IMUX40_0",
|
||||
"CLK_FEED_CK_GCLK31",
|
||||
"CLK_FEED_NE2A2",
|
||||
"CLK_PMV_IMUX43_0",
|
||||
"CLK_FEED_CK_BUFG_CASC9",
|
||||
"CLK_PMV_LOGIC_OUTS9_0",
|
||||
"CLK_PMV_LOGIC_OUTS20_0",
|
||||
"CLK_FEED_CK_BUFG_CASC17",
|
||||
"CLK_FEED_CK_BUFG_CASC3",
|
||||
"CLK_FEED_WW4B3",
|
||||
"CLK_FEED_R_CK_BUFG_CASC3",
|
||||
"CLK_FEED_CK_BUFG_CASC14",
|
||||
"CLK_PMV_IMUX18_0",
|
||||
"CLK_PMV_IMUX37_0",
|
||||
"CLK_FEED_R_CK_GCLK23",
|
||||
"CLK_PMV_LOGIC_OUTS8_0",
|
||||
"CLK_FEED_SE4C0",
|
||||
"CLK_FEED_WW2A2",
|
||||
"CLK_PMV_IMUX1_0",
|
||||
"CLK_FEED_CK_GCLK17",
|
||||
"CLK_FEED_NE4C0",
|
||||
"CLK_FEED_NW4END2",
|
||||
"CLK_FEED_CK_GCLK29",
|
||||
"CLK_FEED_WL1END0",
|
||||
"CLK_PMV_IMUX36_0",
|
||||
"CLK_FEED_WW2END2",
|
||||
"CLK_FEED_CK_BUFG_CASC26",
|
||||
"CLK_FEED_R_CK_BUFG_CASC26",
|
||||
"CLK_PMV_LOGIC_OUTS11_0",
|
||||
"CLK_FEED_CK_BUFG_CASC0",
|
||||
"CLK_FEED_WW4B1",
|
||||
"CLK_FEED_CK_GCLK0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC19",
|
||||
"CLK_FEED_WL1END2",
|
||||
"CLK_FEED_CK_BUFG_CASC23",
|
||||
"CLK_FEED_R_CK_GCLK6",
|
||||
"CLK_FEED_R_CK_BUFG_CASC23",
|
||||
"CLK_PMV_LOGIC_OUTS17_0",
|
||||
"CLK_FEED_NW4END3",
|
||||
"CLK_FEED_R_CK_GCLK0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC12",
|
||||
"CLK_FEED_EE4C3",
|
||||
"CLK_PMV_LOGIC_OUTS5_0",
|
||||
"CLK_PMV_BYP4_0",
|
||||
"CLK_FEED_CK_BUFG_CASC31",
|
||||
"CLK_FEED_R_CK_GCLK24",
|
||||
"CLK_PMV_LOGIC_OUTS18_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC29",
|
||||
"CLK_FEED_R_CK_BUFG_CASC8",
|
||||
"CLK_FEED_WW4C1",
|
||||
"CLK_FEED_SE2A3",
|
||||
"CLK_PMV_FAN7_0",
|
||||
"CLK_FEED_R_CK_GCLK19",
|
||||
"CLK_FEED_WW4A1",
|
||||
"CLK_FEED_R_CK_BUFG_CASC10",
|
||||
"CLK_PMV_FAN2_0",
|
||||
"CLK_PMV_BYP7_0",
|
||||
"CLK_FEED_EE4A2",
|
||||
"CLK_FEED_R_CK_BUFG_CASC7",
|
||||
"CLK_FEED_R_CK_BUFG_CASC2",
|
||||
"CLK_FEED_R_CK_GCLK9",
|
||||
"CLK_PMV_IMUX10_0",
|
||||
"CLK_FEED_CK_BUFG_CASC19",
|
||||
"CLK_PMV_IMUX5_0",
|
||||
"CLK_FEED_EE2BEG2",
|
||||
"CLK_FEED_EE2A2",
|
||||
"CLK_FEED_R_CK_BUFG_CASC5",
|
||||
"CLK_FEED_CK_BUFG_CASC4",
|
||||
"CLK_FEED_CK_GCLK19",
|
||||
"CLK_FEED_R_CK_BUFG_CASC17",
|
||||
"CLK_FEED_SW4A3",
|
||||
"CLK_PMV_IMUX23_0",
|
||||
"CLK_FEED_WW4C3",
|
||||
"CLK_FEED_LH10",
|
||||
"CLK_FEED_R_CK_GCLK29",
|
||||
"CLK_FEED_CK_GCLK11",
|
||||
"CLK_FEED_CK_GCLK7",
|
||||
"CLK_FEED_R_CK_BUFG_CASC27",
|
||||
"CLK_FEED_R_CK_BUFG_CASC11",
|
||||
"CLK_FEED_ER1BEG2",
|
||||
"CLK_FEED_R_CK_GCLK31",
|
||||
"CLK_PMV_LOGIC_OUTS13_0",
|
||||
"CLK_FEED_SE4BEG3",
|
||||
"CLK_PMV_IMUX20_0",
|
||||
"CLK_FEED_LH7",
|
||||
"CLK_FEED_NW2A3",
|
||||
"CLK_FEED_NW4A0",
|
||||
"CLK_FEED_EL1BEG3",
|
||||
"CLK_FEED_CK_GCLK1",
|
||||
"CLK_FEED_NE4C2",
|
||||
"CLK_FEED_CK_BUFG_CASC21",
|
||||
"CLK_FEED_EE4C1",
|
||||
"CLK_FEED_CK_BUFG_CASC12",
|
||||
"CLK_FEED_R_CK_GCLK2",
|
||||
"CLK_FEED_SE2A1",
|
||||
"CLK_FEED_CK_BUFG_CASC14",
|
||||
"CLK_FEED_ER1BEG3",
|
||||
"CLK_FEED_WW4C0",
|
||||
"CLK_FEED_CK_BUFG_CASC23",
|
||||
"CLK_FEED_CK_GCLK4",
|
||||
"CLK_FEED_ER1BEG1",
|
||||
"CLK_PMV_BYP6_0",
|
||||
"CLK_FEED_NW4A3",
|
||||
"CLK_FEED_R_CK_BUFG_CASC0",
|
||||
"CLK_PMV2_A0",
|
||||
"CLK_PMV_FAN0_0",
|
||||
"CLK_FEED_ER1BEG0",
|
||||
"CLK_PMV_IMUX31_0",
|
||||
"CLK_PMV_LOGIC_OUTS14_0",
|
||||
"CLK_FEED_CK_GCLK16",
|
||||
"CLK_FEED_CK_GCLK29",
|
||||
"CLK_FEED_R_CK_GCLK26",
|
||||
"CLK_PMV_LOGIC_OUTS3_0",
|
||||
"CLK_FEED_WW4C2",
|
||||
"CLK_FEED_R_CK_BUFG_CASC4",
|
||||
"CLK_FEED_R_CK_GCLK16",
|
||||
"CLK_FEED_CK_GCLK23",
|
||||
"CLK_FEED_EE4A0",
|
||||
"CLK_FEED_WR1END1",
|
||||
"CLK_FEED_NE4C0",
|
||||
"CLK_FEED_CK_BUFG_CASC16",
|
||||
"CLK_PMV_FAN1_0",
|
||||
"CLK_FEED_R_CK_GCLK5",
|
||||
"CLK_FEED_R_CK_BUFG_CASC19",
|
||||
"CLK_FEED_CK_GCLK6",
|
||||
"CLK_FEED_EE4B1",
|
||||
"CLK_FEED_CK_GCLK25",
|
||||
"CLK_FEED_EE4A1",
|
||||
"CLK_FEED_CK_GCLK9",
|
||||
"CLK_FEED_SW4END1",
|
||||
"CLK_FEED_SW4END2",
|
||||
"CLK_PMV_LOGIC_OUTS12_0",
|
||||
"CLK_FEED_CK_GCLK2",
|
||||
"CLK_FEED_WW2A3",
|
||||
"CLK_FEED_NE2A0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC14",
|
||||
"CLK_PMV_IMUX44_0",
|
||||
"CLK_FEED_CK_BUFG_CASC7",
|
||||
"CLK_FEED_CK_BUFG_CASC27",
|
||||
"CLK_PMV_IMUX8_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC1",
|
||||
"CLK_FEED_WW4A3",
|
||||
"CLK_PMV_IMUX1_0",
|
||||
"CLK_FEED_SW4A0",
|
||||
"CLK_PMV_LOGIC_OUTS2_0",
|
||||
"CLK_FEED_EE4C0",
|
||||
"CLK_PMV2_O",
|
||||
"CLK_FEED_CK_BUFG_CASC5",
|
||||
"CLK_FEED_CK_BUFG_CASC13",
|
||||
"CLK_FEED_CK_GCLK21",
|
||||
"CLK_PMV_FAN3_0",
|
||||
"CLK_FEED_CK_GCLK28",
|
||||
"CLK_PMV_IMUX15_0",
|
||||
"CLK_PMV_IMUX26_0",
|
||||
"CLK_PMV_CTRL1_0",
|
||||
"CLK_PMV_FAN5_0",
|
||||
"CLK_FEED_NE4BEG2",
|
||||
"CLK_FEED_WW2A2",
|
||||
"CLK_FEED_WR1END2",
|
||||
"CLK_PMV_CTRL0_0",
|
||||
"CLK_FEED_EL1BEG2",
|
||||
"CLK_PMV_IMUX30_0",
|
||||
"CLK_FEED_LH1",
|
||||
"CLK_FEED_CK_BUFG_CASC8",
|
||||
"CLK_FEED_R_CK_GCLK30",
|
||||
"CLK_PMV_LOGIC_OUTS9_0",
|
||||
"CLK_FEED_WW2A0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC15",
|
||||
"CLK_FEED_R_CK_GCLK3",
|
||||
"CLK_FEED_WW4A2",
|
||||
"CLK_PMV_IMUX13_0",
|
||||
"CLK_FEED_EL1BEG1",
|
||||
"CLK_FEED_WL1END0",
|
||||
"CLK_FEED_SE2A2",
|
||||
"CLK_PMV2_A2",
|
||||
"CLK_FEED_WW4END3",
|
||||
"CLK_FEED_R_CK_BUFG_CASC28",
|
||||
"CLK_FEED_NW4END0",
|
||||
"CLK_FEED_SW4A2",
|
||||
"CLK_PMV_IMUX22_0",
|
||||
"CLK_PMV_IMUX4_0",
|
||||
"CLK_FEED_WW2A0",
|
||||
"CLK_FEED_EE4B2",
|
||||
"CLK_PMV2_A0",
|
||||
"CLK_FEED_SW2A3",
|
||||
"CLK_PMV_IMUX45_0",
|
||||
"CLK_FEED_EE2A1",
|
||||
"CLK_FEED_CK_BUFG_CASC21",
|
||||
"CLK_FEED_R_CK_GCLK3",
|
||||
"CLK_FEED_EE4C1",
|
||||
"CLK_FEED_SW4END3",
|
||||
"CLK_FEED_WR1END3",
|
||||
"CLK_FEED_EE4C3",
|
||||
"CLK_FEED_R_CK_GCLK8",
|
||||
"CLK_FEED_CK_BUFG_CASC1",
|
||||
"CLK_FEED_R_CK_GCLK10",
|
||||
"CLK_FEED_SW4A2",
|
||||
"CLK_PMV_FAN1_0",
|
||||
"CLK_FEED_R_CK_GCLK7",
|
||||
"CLK_PMV_BYP3_0",
|
||||
"CLK_FEED_NW4END1",
|
||||
"CLK_PMV_LOGIC_OUTS15_0",
|
||||
"CLK_FEED_WW2A1",
|
||||
"CLK_FEED_EE2A0",
|
||||
"CLK_FEED_EE2BEG0",
|
||||
"CLK_PMV_IMUX20_0",
|
||||
"CLK_PMV_BYP0_0",
|
||||
"CLK_PMV2_ODIV2",
|
||||
"CLK_FEED_NE4C1",
|
||||
"CLK_FEED_CK_GCLK20",
|
||||
"CLK_FEED_R_CK_GCLK11",
|
||||
"CLK_FEED_LH6",
|
||||
"CLK_FEED_NE4BEG0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC24",
|
||||
"CLK_FEED_NW2A1",
|
||||
"CLK_FEED_CK_GCLK12",
|
||||
"CLK_FEED_CK_BUFG_CASC2",
|
||||
"CLK_FEED_CK_GCLK22",
|
||||
"CLK_FEED_WL1END3",
|
||||
"CLK_FEED_R_CK_GCLK4",
|
||||
"CLK_FEED_WW4A0",
|
||||
"CLK_FEED_CK_BUFG_CASC28",
|
||||
"CLK_FEED_CK_GCLK31",
|
||||
"CLK_FEED_R_CK_BUFG_CASC11",
|
||||
"CLK_PMV_IMUX7_0",
|
||||
"CLK_PMV_BYP7_0",
|
||||
"CLK_PMV_IMUX33_0",
|
||||
"CLK_PMV_IMUX0_0",
|
||||
"CLK_FEED_LH9",
|
||||
"CLK_FEED_R_CK_GCLK6",
|
||||
"CLK_FEED_CK_GCLK30",
|
||||
"CLK_PMV_IMUX24_0",
|
||||
"CLK_FEED_NE4BEG3",
|
||||
"CLK_PMV_BYP1_0",
|
||||
"CLK_PMV_LOGIC_OUTS7_0",
|
||||
"CLK_FEED_WW2A3",
|
||||
"CLK_PMV_FAN2_0",
|
||||
"CLK_PMV_LOGIC_OUTS2_0",
|
||||
"CLK_FEED_R_CK_GCLK27",
|
||||
"CLK_FEED_CK_BUFG_CASC3",
|
||||
"CLK_FEED_R_CK_GCLK18",
|
||||
"CLK_FEED_WW2END2",
|
||||
"CLK_FEED_EE2BEG1",
|
||||
"CLK_FEED_WW4END0",
|
||||
"CLK_FEED_CK_BUFG_CASC25",
|
||||
"CLK_PMV_IMUX16_0",
|
||||
"CLK_FEED_LH2",
|
||||
"CLK_PMV_LOGIC_OUTS6_0",
|
||||
"CLK_FEED_R_CK_GCLK25",
|
||||
"CLK_PMV_CLK0_0",
|
||||
"CLK_PMV_IMUX11_0",
|
||||
"CLK_FEED_EE4B3",
|
||||
"CLK_FEED_CK_BUFG_CASC24",
|
||||
"CLK_FEED_WW2END1",
|
||||
"CLK_PMV_LOGIC_OUTS23_0",
|
||||
"CLK_FEED_LH12",
|
||||
"CLK_FEED_LH7",
|
||||
"CLK_FEED_R_CK_GCLK14",
|
||||
"CLK_FEED_SW2A1",
|
||||
"CLK_PMV_IMUX6_0",
|
||||
"CLK_PMV_LOGIC_OUTS22_0",
|
||||
"CLK_PMV_IMUX23_0",
|
||||
"CLK_FEED_EE2BEG0",
|
||||
"CLK_FEED_CK_BUFG_CASC2",
|
||||
"CLK_FEED_CK_BUFG_CASC24",
|
||||
"CLK_FEED_EE2BEG2",
|
||||
"CLK_FEED_LH1",
|
||||
"CLK_FEED_CK_BUFG_CASC22",
|
||||
"CLK_PMV_IMUX11_0",
|
||||
"CLK_FEED_SE4C1",
|
||||
"CLK_PMV_LOGIC_OUTS23_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC25",
|
||||
"CLK_FEED_NE4C3",
|
||||
"CLK_PMV_FAN3_0",
|
||||
"CLK_FEED_SE2A1",
|
||||
"CLK_FEED_NE2A1",
|
||||
"CLK_FEED_R_CK_BUFG_CASC18",
|
||||
"CLK_PMV_LOGIC_OUTS19_0",
|
||||
"CLK_FEED_WW2END3",
|
||||
"CLK_FEED_MONITOR_N",
|
||||
"CLK_FEED_R_CK_BUFG_CASC17",
|
||||
"CLK_FEED_ER1BEG1",
|
||||
"CLK_FEED_EE4BEG1",
|
||||
"CLK_PMV_IMUX35_0",
|
||||
"CLK_FEED_WR1END1",
|
||||
"CLK_FEED_R_CK_GCLK26",
|
||||
"CLK_PMV_IMUX19_0",
|
||||
"CLK_PMV_LOGIC_OUTS0_0",
|
||||
"CLK_FEED_R_CK_GCLK16",
|
||||
"CLK_PMV_FAN5_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC9",
|
||||
"CLK_FEED_EE4BEG2",
|
||||
"CLK_PMV_LOGIC_OUTS12_0",
|
||||
"CLK_PMV_BYP3_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC7",
|
||||
"CLK_FEED_WW4C3",
|
||||
"CLK_FEED_R_CK_GCLK29",
|
||||
"CLK_FEED_CK_BUFG_CASC6",
|
||||
"CLK_PMV_IMUX43_0",
|
||||
"CLK_FEED_LH2",
|
||||
"CLK_FEED_SW4END2",
|
||||
"CLK_FEED_WW4END0",
|
||||
"CLK_PMV2_A1",
|
||||
"CLK_PMV2_ODIV2",
|
||||
"CLK_FEED_CK_GCLK12",
|
||||
"CLK_PMV2_O",
|
||||
"CLK_FEED_CK_BUFG_CASC31",
|
||||
"CLK_FEED_R_CK_GCLK9",
|
||||
"CLK_FEED_NW2A1",
|
||||
"CLK_FEED_CK_BUFG_CASC11",
|
||||
"CLK_FEED_LH9",
|
||||
"CLK_FEED_WW2END0",
|
||||
"CLK_FEED_CK_GCLK9",
|
||||
"CLK_FEED_R_CK_GCLK22",
|
||||
"CLK_PMV_IMUX24_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC10",
|
||||
"CLK_FEED_EE4BEG0",
|
||||
"CLK_PMV_IMUX10_0",
|
||||
"CLK_FEED_NW4END0",
|
||||
"CLK_FEED_CK_GCLK7",
|
||||
"CLK_FEED_CK_BUFG_CASC19",
|
||||
"CLK_FEED_EE2BEG1",
|
||||
"CLK_FEED_SE4BEG0",
|
||||
"CLK_FEED_R_CK_GCLK27",
|
||||
"CLK_FEED_CK_GCLK30",
|
||||
"CLK_FEED_R_CK_BUFG_CASC12",
|
||||
"CLK_FEED_CK_BUFG_CASC4",
|
||||
"CLK_FEED_CK_BUFG_CASC20",
|
||||
"CLK_PMV_IMUX28_0",
|
||||
"CLK_PMV_BYP6_0",
|
||||
"CLK_PMV_LOGIC_OUTS5_0",
|
||||
"CLK_FEED_R_CK_GCLK20",
|
||||
"CLK_FEED_SE2A3",
|
||||
"CLK_PMV_IMUX40_0",
|
||||
"CLK_FEED_SW2A2",
|
||||
"CLK_FEED_NE4C1",
|
||||
"CLK_FEED_SE4BEG1",
|
||||
"CLK_FEED_ER1BEG0",
|
||||
"CLK_PMV_LOGIC_OUTS16_0",
|
||||
"CLK_PMV_IMUX42_0",
|
||||
"CLK_FEED_EE4A1",
|
||||
"CLK_FEED_WW4C0",
|
||||
"CLK_FEED_R_CK_GCLK11",
|
||||
"CLK_FEED_NE2A3",
|
||||
"CLK_FEED_SW4A3",
|
||||
"CLK_PMV_LOGIC_OUTS6_0",
|
||||
"CLK_PMV_IMUX27_0",
|
||||
"CLK_FEED_NW4A2",
|
||||
"CLK_PMV_IMUX38_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC1",
|
||||
"CLK_PMV_IMUX30_0",
|
||||
"CLK_PMV_LOGIC_OUTS14_0",
|
||||
"CLK_FEED_CK_GCLK23",
|
||||
"CLK_FEED_CK_GCLK18",
|
||||
"CLK_FEED_R_CK_BUFG_CASC20",
|
||||
"CLK_FEED_NE4BEG3",
|
||||
"CLK_FEED_CK_GCLK16",
|
||||
"CLK_FEED_SW4A1",
|
||||
"CLK_FEED_R_CK_BUFG_CASC23",
|
||||
"CLK_FEED_CK_GCLK21",
|
||||
"CLK_FEED_MONITOR_P",
|
||||
"CLK_FEED_LH8",
|
||||
"CLK_FEED_WL1END3",
|
||||
"CLK_FEED_R_CK_GCLK18",
|
||||
"CLK_FEED_WW4END1",
|
||||
"CLK_FEED_LH5",
|
||||
"CLK_FEED_SW4END0",
|
||||
"CLK_FEED_WW4A1",
|
||||
"CLK_FEED_R_CK_GCLK15",
|
||||
"CLK_FEED_CK_BUFG_CASC18",
|
||||
"CLK_FEED_R_CK_BUFG_CASC6",
|
||||
"CLK_FEED_ER1BEG3",
|
||||
"CLK_FEED_SE4BEG2",
|
||||
"CLK_FEED_CK_GCLK1",
|
||||
"CLK_FEED_WR1END2",
|
||||
"CLK_FEED_NW4A3",
|
||||
"CLK_FEED_CK_GCLK24",
|
||||
"CLK_FEED_EE4A3",
|
||||
"CLK_FEED_R_CK_BUFG_CASC0",
|
||||
"CLK_PMV_LOGIC_OUTS18_0",
|
||||
"CLK_FEED_R_CK_GCLK12",
|
||||
"CLK_PMV_CTRL1_0",
|
||||
"CLK_FEED_CK_GCLK14",
|
||||
"CLK_PMV_FAN4_0",
|
||||
"CLK_FEED_CK_GCLK4",
|
||||
"CLK_FEED_EE4C0",
|
||||
"CLK_FEED_EE4B3",
|
||||
"CLK_FEED_R_CK_GCLK24",
|
||||
"CLK_FEED_EE4A2",
|
||||
"CLK_PMV_IMUX44_0",
|
||||
"CLK_PMV_IMUX21_0",
|
||||
"CLK_FEED_R_CK_GCLK30",
|
||||
"CLK_FEED_R_CK_BUFG_CASC24",
|
||||
"CLK_FEED_CK_BUFG_CASC13",
|
||||
"CLK_FEED_R_CK_BUFG_CASC5",
|
||||
"CLK_FEED_NW4END3",
|
||||
"CLK_PMV_BYP0_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC21",
|
||||
"CLK_PMV_IMUX47_0",
|
||||
"CLK_FEED_WW4C1",
|
||||
"CLK_PMV_IMUX32_0",
|
||||
"CLK_PMV_LOGIC_OUTS1_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC8",
|
||||
"CLK_FEED_SE4C3",
|
||||
"CLK_PMV_IMUX26_0",
|
||||
"CLK_FEED_CK_BUFG_CASC10",
|
||||
"CLK_FEED_SW4A0",
|
||||
"CLK_FEED_CK_BUFG_CASC27",
|
||||
"CLK_FEED_R_CK_BUFG_CASC13",
|
||||
"CLK_PMV_IMUX17_0",
|
||||
"CLK_FEED_NE2A2",
|
||||
"CLK_FEED_SW2A1",
|
||||
"CLK_FEED_CK_GCLK15",
|
||||
"CLK_FEED_SW2A0",
|
||||
"CLK_FEED_CK_GCLK11",
|
||||
"CLK_PMV_IMUX46_0",
|
||||
"CLK_FEED_CK_BUFG_CASC25",
|
||||
"CLK_PMV_IMUX12_0",
|
||||
"CLK_FEED_CK_GCLK2",
|
||||
"CLK_FEED_CK_GCLK25",
|
||||
"CLK_PMV_IMUX14_0",
|
||||
"CLK_FEED_R_CK_GCLK0",
|
||||
"CLK_FEED_CK_GCLK3",
|
||||
"CLK_PMV2_A2",
|
||||
"CLK_FEED_WL1END1",
|
||||
"CLK_FEED_R_CK_GCLK14",
|
||||
"CLK_PMV_IMUX0_0",
|
||||
"CLK_FEED_CK_GCLK10",
|
||||
"CLK_FEED_WW2END1",
|
||||
"CLK_FEED_WW4A3",
|
||||
"CLK_FEED_R_CK_BUFG_CASC31",
|
||||
"CLK_FEED_CK_GCLK5",
|
||||
"CLK_FEED_NW4A1",
|
||||
"CLK_FEED_CK_GCLK27",
|
||||
"CLK_FEED_CK_BUFG_CASC16",
|
||||
"CLK_FEED_R_CK_GCLK28",
|
||||
"CLK_FEED_EL1BEG1",
|
||||
"CLK_FEED_R_CK_GCLK19",
|
||||
"CLK_FEED_CK_BUFG_CASC8",
|
||||
"CLK_PMV_IMUX5_0",
|
||||
"CLK_FEED_LH12",
|
||||
"CLK_FEED_R_CK_GCLK17",
|
||||
"CLK_FEED_R_CK_BUFG_CASC18",
|
||||
"CLK_FEED_MONITOR_P",
|
||||
"CLK_FEED_SE4BEG1",
|
||||
"CLK_FEED_MONITOR_N",
|
||||
"CLK_PMV_IMUX47_0",
|
||||
"CLK_PMV_IMUX45_0",
|
||||
"CLK_FEED_CK_BUFG_CASC18",
|
||||
"CLK_PMV_IMUX36_0",
|
||||
"CLK_PMV_LOGIC_OUTS8_0",
|
||||
"CLK_FEED_CK_BUFG_CASC15",
|
||||
"CLK_PMV_LOGIC_OUTS19_0",
|
||||
"CLK_PMV_IMUX34_0",
|
||||
"CLK_FEED_SW2A0",
|
||||
"CLK_FEED_CK_BUFG_CASC0",
|
||||
"CLK_FEED_WR1END0",
|
||||
"CLK_FEED_LH11",
|
||||
"CLK_PMV_BYP2_0",
|
||||
"CLK_FEED_WW2A1",
|
||||
"CLK_PMV_IMUX8_0",
|
||||
"CLK_FEED_EL1BEG3",
|
||||
"CLK_PMV_IMUX39_0",
|
||||
"CLK_FEED_CK_BUFG_CASC29",
|
||||
"CLK_PMV_IMUX21_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC20",
|
||||
"CLK_PMV_IMUX41_0",
|
||||
"CLK_PMV_IMUX27_0",
|
||||
"CLK_PMV_IMUX25_0",
|
||||
"CLK_FEED_NE4BEG1",
|
||||
"CLK_PMV_FAN6_0",
|
||||
"CLK_FEED_WW4B0",
|
||||
"CLK_PMV_LOGIC_OUTS1_0",
|
||||
"CLK_PMV_IMUX28_0",
|
||||
"CLK_FEED_NE2A1",
|
||||
"CLK_PMV_FAN4_0",
|
||||
"CLK_FEED_SE4C0",
|
||||
"CLK_FEED_R_CK_GCLK22",
|
||||
"CLK_FEED_R_CK_GCLK8",
|
||||
"CLK_PMV_LOGIC_OUTS20_0",
|
||||
"CLK_PMV_IMUX19_0",
|
||||
"CLK_FEED_WW2END3",
|
||||
"CLK_FEED_R_CK_BUFG_CASC25",
|
||||
"CLK_FEED_EE2A1",
|
||||
"CLK_FEED_EE4B2",
|
||||
"CLK_FEED_CK_GCLK0",
|
||||
"CLK_FEED_WW4B2",
|
||||
"CLK_PMV_IMUX46_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC26",
|
||||
"CLK_FEED_R_CK_BUFG_CASC22",
|
||||
"CLK_FEED_SW2A2",
|
||||
"CLK_FEED_CK_GCLK8",
|
||||
"CLK_FEED_LH11",
|
||||
"CLK_FEED_NW2A0",
|
||||
"CLK_FEED_CK_BUFG_CASC22",
|
||||
"CLK_FEED_CK_GCLK18",
|
||||
"CLK_FEED_CK_GCLK26",
|
||||
"CLK_FEED_CK_BUFG_CASC20",
|
||||
"CLK_PMV_IMUX35_0",
|
||||
"CLK_FEED_CK_GCLK3",
|
||||
"CLK_PMV_IMUX18_0",
|
||||
"CLK_FEED_SE4C1",
|
||||
"CLK_FEED_NW4A2",
|
||||
"CLK_FEED_WW2END0",
|
||||
"CLK_PMV2_A1",
|
||||
"CLK_FEED_CK_BUFG_CASC6",
|
||||
"CLK_FEED_SE2A0",
|
||||
"CLK_PMV_IMUX12_0",
|
||||
"CLK_FEED_WW4A0",
|
||||
"CLK_FEED_EE4BEG2",
|
||||
"CLK_FEED_CK_GCLK10",
|
||||
"CLK_FEED_R_CK_BUFG_CASC30",
|
||||
"CLK_FEED_SW4END3",
|
||||
"CLK_FEED_EL1BEG0",
|
||||
"CLK_PMV_IMUX17_0",
|
||||
"CLK_FEED_EE4BEG0",
|
||||
"CLK_FEED_WR1END3",
|
||||
"CLK_PMV_LOGIC_OUTS16_0",
|
||||
"CLK_PMV2_ODIV4",
|
||||
"CLK_FEED_CK_GCLK5",
|
||||
"CLK_FEED_CK_BUFG_CASC30",
|
||||
"CLK_FEED_SE4BEG0",
|
||||
"CLK_PMV_LOGIC_OUTS21_0",
|
||||
"CLK_FEED_EE4BEG1",
|
||||
"CLK_FEED_SE4BEG3",
|
||||
"CLK_FEED_CK_GCLK17",
|
||||
"CLK_FEED_R_CK_BUFG_CASC6",
|
||||
"CLK_FEED_SW4A1",
|
||||
"CLK_FEED_R_CK_GCLK23",
|
||||
"CLK_FEED_EE2BEG3",
|
||||
"CLK_FEED_R_CK_BUFG_CASC16",
|
||||
"CLK_FEED_R_CK_GCLK21",
|
||||
"CLK_FEED_R_CK_GCLK10",
|
||||
"CLK_FEED_NE4C3",
|
||||
"CLK_FEED_R_CK_BUFG_CASC21",
|
||||
"CLK_PMV_LOGIC_OUTS4_0",
|
||||
"CLK_PMV_IMUX14_0",
|
||||
"CLK_FEED_NW4A0",
|
||||
"CLK_PMV_BYP5_0",
|
||||
"CLK_FEED_SE4BEG2",
|
||||
"CLK_FEED_R_CK_BUFG_CASC31",
|
||||
"CLK_FEED_CK_BUFG_CASC11",
|
||||
"CLK_FEED_R_CK_GCLK20",
|
||||
"CLK_FEED_SW4END0",
|
||||
"CLK_PMV2_EN",
|
||||
"CLK_PMV_LOGIC_OUTS7_0",
|
||||
"CLK_PMV_IMUX32_0",
|
||||
"CLK_FEED_CK_BUFG_CASC26",
|
||||
"CLK_PMV_IMUX9_0",
|
||||
"CLK_FEED_LH5",
|
||||
"CLK_PMV_IMUX37_0",
|
||||
"CLK_PMV_IMUX7_0",
|
||||
"CLK_FEED_R_CK_GCLK31",
|
||||
"CLK_FEED_WW4B1",
|
||||
"CLK_FEED_CK_GCLK24",
|
||||
"CLK_FEED_WW4END1",
|
||||
"CLK_FEED_R_CK_GCLK17",
|
||||
"CLK_FEED_R_CK_GCLK7",
|
||||
"CLK_FEED_CK_BUFG_CASC28",
|
||||
"CLK_FEED_EE2A3",
|
||||
"CLK_FEED_CK_GCLK14",
|
||||
"CLK_FEED_CK_GCLK13",
|
||||
"CLK_FEED_CK_BUFG_CASC1",
|
||||
"CLK_FEED_R_CK_BUFG_CASC9",
|
||||
"CLK_FEED_LH8",
|
||||
"CLK_FEED_EE4C2",
|
||||
"CLK_FEED_WW4B3",
|
||||
"CLK_FEED_EE4A3",
|
||||
"CLK_FEED_NW2A2",
|
||||
"CLK_FEED_CK_BUFG_CASC10",
|
||||
"CLK_FEED_WL1END1",
|
||||
"CLK_PMV_BYP2_0",
|
||||
"CLK_FEED_SE4C3",
|
||||
"CLK_FEED_WL1END2",
|
||||
"CLK_PMV_LOGIC_OUTS13_0",
|
||||
"CLK_FEED_LH3",
|
||||
"CLK_PMV_LOGIC_OUTS0_0",
|
||||
"CLK_PMV_IMUX39_0",
|
||||
"CLK_FEED_R_CK_GCLK13",
|
||||
"CLK_FEED_NW2A3",
|
||||
"CLK_FEED_LH4",
|
||||
"CLK_FEED_EE4B0",
|
||||
"CLK_PMV_IMUX29_0",
|
||||
"CLK_FEED_EE2BEG3",
|
||||
"CLK_FEED_R_CK_BUFG_CASC14",
|
||||
"CLK_FEED_R_CK_BUFG_CASC16",
|
||||
"CLK_FEED_CK_BUFG_CASC12"
|
||||
"CLK_FEED_SE4C2",
|
||||
"CLK_FEED_SW2A3",
|
||||
"CLK_FEED_EE4BEG3",
|
||||
"CLK_FEED_CK_GCLK15",
|
||||
"CLK_FEED_R_CK_GCLK1",
|
||||
"CLK_FEED_R_CK_GCLK15",
|
||||
"CLK_FEED_R_CK_GCLK12",
|
||||
"CLK_PMV_IMUX38_0",
|
||||
"CLK_FEED_R_CK_GCLK28",
|
||||
"CLK_FEED_CK_BUFG_CASC17",
|
||||
"CLK_PMV_LOGIC_OUTS10_0",
|
||||
"CLK_PMV_CLK1_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC13",
|
||||
"CLK_PMV_IMUX2_0",
|
||||
"CLK_FEED_NW4END2",
|
||||
"CLK_FEED_WW4END2",
|
||||
"CLK_PMV_LOGIC_OUTS11_0",
|
||||
"CLK_PMV_IMUX3_0",
|
||||
"CLK_FEED_NE2A3",
|
||||
"CLK_FEED_R_CK_BUFG_CASC3",
|
||||
"CLK_PMV_IMUX42_0"
|
||||
],
|
||||
"tile_type": "CLK_PMV2_SVT",
|
||||
"sites": []
|
||||
}
|
||||
|
|
@ -1,359 +1,359 @@
|
|||
{
|
||||
"tile_type": "CLK_PMVIOB",
|
||||
"pips": {},
|
||||
"wires": [
|
||||
"CLK_FEED_LH4",
|
||||
"CLK_FEED_NE4C2",
|
||||
"CLK_PMV_CLK0_0",
|
||||
"CLK_FEED_EL1BEG2",
|
||||
"CLK_FEED_LH3",
|
||||
"CLK_FEED_WW4END3",
|
||||
"CLK_FEED_CK_BUFG_CASC29",
|
||||
"CLK_PMV_FAN0_0",
|
||||
"CLK_PMV_LOGIC_OUTS17_0",
|
||||
"CLK_FEED_WW4B0",
|
||||
"CLK_PMV_BYP5_0",
|
||||
"CLK_PMV_LOGIC_OUTS21_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC22",
|
||||
"CLK_PMV_LOGIC_OUTS4_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC4",
|
||||
"CLK_FEED_R_CK_BUFG_CASC30",
|
||||
"CLK_FEED_EE2A0",
|
||||
"CLK_PMV_IMUX34_0",
|
||||
"CLK_FEED_CK_BUFG_CASC5",
|
||||
"CLK_PMV_IMUX3_0",
|
||||
"CLK_FEED_R_CK_GCLK1",
|
||||
"CLK_PMV_BYP4_0",
|
||||
"CLK_FEED_NE4BEG0",
|
||||
"CLK_FEED_CK_BUFG_CASC30",
|
||||
"CLK_PMVIOB_ODIV2",
|
||||
"CLK_PMV_LOGIC_OUTS15_0",
|
||||
"CLK_FEED_WW4B2",
|
||||
"CLK_FEED_EE2A2",
|
||||
"CLK_FEED_CK_GCLK28",
|
||||
"CLK_FEED_R_CK_GCLK13",
|
||||
"CLK_FEED_CK_GCLK26",
|
||||
"CLK_FEED_SW4END1",
|
||||
"CLK_FEED_SE2A0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC27",
|
||||
"CLK_PMV_IMUX41_0",
|
||||
"CLK_FEED_CK_GCLK13",
|
||||
"CLK_FEED_CK_GCLK19",
|
||||
"CLK_FEED_LH6",
|
||||
"CLK_PMVIOB_ODIV4",
|
||||
"CLK_FEED_R_CK_BUFG_CASC29",
|
||||
"CLK_FEED_NW4END1",
|
||||
"CLK_PMVIOB_A0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC2",
|
||||
"CLK_FEED_R_CK_BUFG_CASC15",
|
||||
"CLK_PMV_IMUX25_0",
|
||||
"CLK_FEED_NW4A1",
|
||||
"CLK_FEED_CK_GCLK22",
|
||||
"CLK_FEED_EE2A3",
|
||||
"CLK_FEED_NE2A0",
|
||||
"CLK_FEED_EE4C2",
|
||||
"CLK_PMV_IMUX15_0",
|
||||
"CLK_FEED_EE4A0",
|
||||
"CLK_FEED_EE4BEG3",
|
||||
"CLK_FEED_CK_GCLK6",
|
||||
"CLK_FEED_NW2A0",
|
||||
"CLK_FEED_R_CK_GCLK25",
|
||||
"CLK_FEED_R_CK_BUFG_CASC28",
|
||||
"CLK_PMV_LOGIC_OUTS3_0",
|
||||
"CLK_FEED_R_CK_GCLK2",
|
||||
"CLK_PMV_FAN7_0",
|
||||
"CLK_PMV_IMUX2_0",
|
||||
"CLK_FEED_NE4BEG1",
|
||||
"CLK_FEED_CK_BUFG_CASC7",
|
||||
"CLK_PMV_IMUX13_0",
|
||||
"CLK_PMV_IMUX16_0",
|
||||
"CLK_FEED_R_CK_GCLK5",
|
||||
"CLK_FEED_WW4END2",
|
||||
"CLK_PMV_CTRL0_0",
|
||||
"CLK_PMV_IMUX31_0",
|
||||
"CLK_FEED_CK_GCLK8",
|
||||
"CLK_FEED_EE4B1",
|
||||
"CLK_FEED_SE2A2",
|
||||
"CLK_FEED_R_CK_GCLK21",
|
||||
"CLK_FEED_WW4C2",
|
||||
"CLK_FEED_NE4BEG2",
|
||||
"CLK_FEED_SE4C2",
|
||||
"CLK_FEED_WW4A2",
|
||||
"CLK_FEED_CK_GCLK20",
|
||||
"CLK_FEED_NW2A2",
|
||||
"CLK_PMV_IMUX33_0",
|
||||
"CLK_PMV_CLK1_0",
|
||||
"CLK_PMV_IMUX9_0",
|
||||
"CLK_PMV_LOGIC_OUTS10_0",
|
||||
"CLK_FEED_CK_BUFG_CASC15",
|
||||
"CLK_FEED_LH10",
|
||||
"CLK_FEED_EL1BEG0",
|
||||
"CLK_FEED_CK_BUFG_CASC9",
|
||||
"CLK_PMV_LOGIC_OUTS9_0",
|
||||
"CLK_PMV_LOGIC_OUTS20_0",
|
||||
"CLK_FEED_CK_BUFG_CASC17",
|
||||
"CLK_FEED_CK_BUFG_CASC3",
|
||||
"CLK_FEED_WW4B3",
|
||||
"CLK_FEED_R_CK_BUFG_CASC3",
|
||||
"CLK_FEED_CK_BUFG_CASC14",
|
||||
"CLK_PMV_IMUX18_0",
|
||||
"CLK_PMV_IMUX37_0",
|
||||
"CLK_FEED_R_CK_GCLK23",
|
||||
"CLK_PMV_LOGIC_OUTS8_0",
|
||||
"CLK_FEED_SE4C0",
|
||||
"CLK_PMV_IMUX1_0",
|
||||
"CLK_FEED_WW2A2",
|
||||
"CLK_FEED_CK_GCLK17",
|
||||
"CLK_FEED_NE4C0",
|
||||
"CLK_FEED_NW4END2",
|
||||
"CLK_FEED_CK_GCLK29",
|
||||
"CLK_FEED_WL1END0",
|
||||
"CLK_PMV_IMUX36_0",
|
||||
"CLK_FEED_WW2END2",
|
||||
"CLK_FEED_CK_BUFG_CASC26",
|
||||
"CLK_FEED_R_CK_BUFG_CASC26",
|
||||
"CLK_PMV_LOGIC_OUTS11_0",
|
||||
"CLK_FEED_CK_BUFG_CASC0",
|
||||
"CLK_FEED_WW4B1",
|
||||
"CLK_FEED_CK_GCLK0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC19",
|
||||
"CLK_FEED_WL1END2",
|
||||
"CLK_FEED_CK_BUFG_CASC23",
|
||||
"CLK_FEED_R_CK_GCLK6",
|
||||
"CLK_FEED_ER1BEG2",
|
||||
"CLK_FEED_R_CK_GCLK31",
|
||||
"CLK_PMV_LOGIC_OUTS13_0",
|
||||
"CLK_FEED_SE4BEG3",
|
||||
"CLK_PMV_IMUX20_0",
|
||||
"CLK_FEED_LH7",
|
||||
"CLK_FEED_NW2A3",
|
||||
"CLK_FEED_NW4A0",
|
||||
"CLK_PMV_IMUX22_0",
|
||||
"CLK_FEED_WW2A0",
|
||||
"CLK_PMV_IMUX4_0",
|
||||
"CLK_FEED_EE4B2",
|
||||
"CLK_FEED_SW2A3",
|
||||
"CLK_PMV_IMUX45_0",
|
||||
"CLK_FEED_EE2A1",
|
||||
"CLK_FEED_CK_BUFG_CASC21",
|
||||
"CLK_FEED_R_CK_GCLK3",
|
||||
"CLK_FEED_EE4C1",
|
||||
"CLK_FEED_SW4END3",
|
||||
"CLK_FEED_WR1END3",
|
||||
"CLK_FEED_EE4C3",
|
||||
"CLK_FEED_R_CK_GCLK8",
|
||||
"CLK_FEED_CK_BUFG_CASC1",
|
||||
"CLK_FEED_R_CK_GCLK10",
|
||||
"CLK_FEED_SW4A2",
|
||||
"CLK_PMV_FAN1_0",
|
||||
"CLK_FEED_R_CK_GCLK7",
|
||||
"CLK_FEED_R_CK_GCLK4",
|
||||
"CLK_FEED_WW4A0",
|
||||
"CLK_FEED_CK_BUFG_CASC28",
|
||||
"CLK_PMV_IMUX40_0",
|
||||
"CLK_FEED_CK_GCLK31",
|
||||
"CLK_FEED_R_CK_BUFG_CASC11",
|
||||
"CLK_PMV_IMUX7_0",
|
||||
"CLK_PMV_BYP7_0",
|
||||
"CLK_PMV_BYP1_0",
|
||||
"CLK_PMV_LOGIC_OUTS7_0",
|
||||
"CLK_FEED_WW2A3",
|
||||
"CLK_FEED_NE2A2",
|
||||
"CLK_PMV_IMUX43_0",
|
||||
"CLK_FEED_CK_BUFG_CASC9",
|
||||
"CLK_FEED_R_CK_BUFG_CASC23",
|
||||
"CLK_PMV_LOGIC_OUTS17_0",
|
||||
"CLK_FEED_NW4END3",
|
||||
"CLK_FEED_R_CK_GCLK0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC12",
|
||||
"CLK_FEED_EE4C3",
|
||||
"CLK_PMV_LOGIC_OUTS5_0",
|
||||
"CLK_PMV_BYP4_0",
|
||||
"CLK_FEED_CK_BUFG_CASC31",
|
||||
"CLK_FEED_R_CK_GCLK24",
|
||||
"CLK_PMVIOB_ODIV2",
|
||||
"CLK_PMV_LOGIC_OUTS18_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC29",
|
||||
"CLK_FEED_R_CK_BUFG_CASC8",
|
||||
"CLK_FEED_WW4C1",
|
||||
"CLK_FEED_SE2A3",
|
||||
"CLK_PMV_FAN7_0",
|
||||
"CLK_FEED_R_CK_GCLK19",
|
||||
"CLK_FEED_WW4A1",
|
||||
"CLK_FEED_R_CK_BUFG_CASC10",
|
||||
"CLK_PMV_FAN2_0",
|
||||
"CLK_PMV_BYP7_0",
|
||||
"CLK_FEED_EE4A2",
|
||||
"CLK_FEED_R_CK_BUFG_CASC7",
|
||||
"CLK_FEED_R_CK_BUFG_CASC2",
|
||||
"CLK_FEED_R_CK_GCLK9",
|
||||
"CLK_PMV_IMUX10_0",
|
||||
"CLK_FEED_CK_BUFG_CASC19",
|
||||
"CLK_PMV_IMUX5_0",
|
||||
"CLK_FEED_EE2BEG2",
|
||||
"CLK_FEED_EE2A2",
|
||||
"CLK_FEED_R_CK_BUFG_CASC5",
|
||||
"CLK_FEED_CK_BUFG_CASC4",
|
||||
"CLK_FEED_CK_GCLK19",
|
||||
"CLK_FEED_R_CK_BUFG_CASC17",
|
||||
"CLK_FEED_SW4A3",
|
||||
"CLK_PMV_IMUX23_0",
|
||||
"CLK_FEED_WW4C3",
|
||||
"CLK_FEED_LH10",
|
||||
"CLK_FEED_R_CK_GCLK29",
|
||||
"CLK_FEED_CK_GCLK11",
|
||||
"CLK_FEED_CK_GCLK7",
|
||||
"CLK_FEED_R_CK_BUFG_CASC27",
|
||||
"CLK_FEED_R_CK_BUFG_CASC11",
|
||||
"CLK_FEED_ER1BEG2",
|
||||
"CLK_FEED_EL1BEG3",
|
||||
"CLK_FEED_CK_GCLK1",
|
||||
"CLK_FEED_NE4C2",
|
||||
"CLK_FEED_CK_BUFG_CASC21",
|
||||
"CLK_FEED_EE4C1",
|
||||
"CLK_FEED_CK_BUFG_CASC12",
|
||||
"CLK_FEED_R_CK_GCLK2",
|
||||
"CLK_FEED_SE2A1",
|
||||
"CLK_FEED_CK_BUFG_CASC14",
|
||||
"CLK_FEED_ER1BEG3",
|
||||
"CLK_FEED_WW4C0",
|
||||
"CLK_FEED_CK_BUFG_CASC23",
|
||||
"CLK_FEED_CK_GCLK4",
|
||||
"CLK_FEED_ER1BEG1",
|
||||
"CLK_PMV_BYP6_0",
|
||||
"CLK_FEED_NW4A3",
|
||||
"CLK_FEED_R_CK_BUFG_CASC0",
|
||||
"CLK_PMV_FAN0_0",
|
||||
"CLK_FEED_ER1BEG0",
|
||||
"CLK_PMV_IMUX31_0",
|
||||
"CLK_PMV_LOGIC_OUTS14_0",
|
||||
"CLK_FEED_CK_GCLK16",
|
||||
"CLK_FEED_CK_GCLK29",
|
||||
"CLK_FEED_R_CK_GCLK26",
|
||||
"CLK_PMV_LOGIC_OUTS3_0",
|
||||
"CLK_FEED_WW4C2",
|
||||
"CLK_FEED_R_CK_BUFG_CASC4",
|
||||
"CLK_FEED_R_CK_GCLK16",
|
||||
"CLK_FEED_CK_GCLK23",
|
||||
"CLK_FEED_EE4A0",
|
||||
"CLK_FEED_WR1END1",
|
||||
"CLK_FEED_NE4C0",
|
||||
"CLK_FEED_CK_BUFG_CASC16",
|
||||
"CLK_PMV_FAN1_0",
|
||||
"CLK_FEED_R_CK_GCLK5",
|
||||
"CLK_FEED_R_CK_BUFG_CASC19",
|
||||
"CLK_FEED_CK_GCLK6",
|
||||
"CLK_FEED_EE4B1",
|
||||
"CLK_FEED_CK_GCLK25",
|
||||
"CLK_FEED_EE4A1",
|
||||
"CLK_FEED_CK_GCLK9",
|
||||
"CLK_FEED_SW4END1",
|
||||
"CLK_FEED_SW4END2",
|
||||
"CLK_PMV_LOGIC_OUTS12_0",
|
||||
"CLK_FEED_CK_GCLK2",
|
||||
"CLK_FEED_WW2A3",
|
||||
"CLK_FEED_NE2A0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC14",
|
||||
"CLK_PMV_IMUX44_0",
|
||||
"CLK_FEED_CK_BUFG_CASC7",
|
||||
"CLK_FEED_CK_BUFG_CASC27",
|
||||
"CLK_PMV_IMUX8_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC1",
|
||||
"CLK_FEED_WW4A3",
|
||||
"CLK_PMVIOB_O",
|
||||
"CLK_PMV_IMUX1_0",
|
||||
"CLK_FEED_SW4A0",
|
||||
"CLK_PMV_LOGIC_OUTS2_0",
|
||||
"CLK_FEED_EE4C0",
|
||||
"CLK_FEED_CK_BUFG_CASC5",
|
||||
"CLK_FEED_CK_BUFG_CASC13",
|
||||
"CLK_FEED_CK_GCLK21",
|
||||
"CLK_PMV_FAN3_0",
|
||||
"CLK_FEED_CK_GCLK28",
|
||||
"CLK_PMV_IMUX15_0",
|
||||
"CLK_PMV_IMUX26_0",
|
||||
"CLK_PMV_CTRL1_0",
|
||||
"CLK_PMV_FAN5_0",
|
||||
"CLK_FEED_NE4BEG2",
|
||||
"CLK_FEED_WW2A2",
|
||||
"CLK_FEED_WR1END2",
|
||||
"CLK_PMV_CTRL0_0",
|
||||
"CLK_FEED_EL1BEG2",
|
||||
"CLK_PMV_IMUX30_0",
|
||||
"CLK_FEED_LH1",
|
||||
"CLK_FEED_CK_BUFG_CASC8",
|
||||
"CLK_FEED_R_CK_GCLK30",
|
||||
"CLK_PMV_LOGIC_OUTS9_0",
|
||||
"CLK_FEED_WW2A0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC15",
|
||||
"CLK_FEED_R_CK_GCLK3",
|
||||
"CLK_FEED_WW4A2",
|
||||
"CLK_PMV_IMUX13_0",
|
||||
"CLK_FEED_EL1BEG1",
|
||||
"CLK_FEED_WL1END0",
|
||||
"CLK_FEED_SE2A2",
|
||||
"CLK_FEED_WW4END3",
|
||||
"CLK_FEED_R_CK_BUFG_CASC28",
|
||||
"CLK_FEED_NW4END0",
|
||||
"CLK_FEED_SW4A2",
|
||||
"CLK_PMV_IMUX22_0",
|
||||
"CLK_PMV_IMUX4_0",
|
||||
"CLK_PMV_BYP3_0",
|
||||
"CLK_FEED_NW4END1",
|
||||
"CLK_PMV_LOGIC_OUTS15_0",
|
||||
"CLK_FEED_WW2A1",
|
||||
"CLK_FEED_EE2A0",
|
||||
"CLK_FEED_EE2BEG0",
|
||||
"CLK_PMV_IMUX20_0",
|
||||
"CLK_PMV_BYP0_0",
|
||||
"CLK_FEED_NE4C1",
|
||||
"CLK_FEED_CK_GCLK20",
|
||||
"CLK_FEED_R_CK_GCLK11",
|
||||
"CLK_FEED_LH6",
|
||||
"CLK_FEED_NE4BEG0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC24",
|
||||
"CLK_FEED_NW2A1",
|
||||
"CLK_FEED_CK_GCLK12",
|
||||
"CLK_FEED_CK_BUFG_CASC2",
|
||||
"CLK_FEED_CK_GCLK22",
|
||||
"CLK_FEED_WL1END3",
|
||||
"CLK_FEED_R_CK_GCLK4",
|
||||
"CLK_PMV_IMUX33_0",
|
||||
"CLK_PMV_IMUX0_0",
|
||||
"CLK_FEED_LH9",
|
||||
"CLK_FEED_R_CK_GCLK6",
|
||||
"CLK_FEED_CK_GCLK30",
|
||||
"CLK_PMV_IMUX24_0",
|
||||
"CLK_FEED_NE4BEG3",
|
||||
"CLK_PMV_BYP1_0",
|
||||
"CLK_FEED_R_CK_GCLK27",
|
||||
"CLK_FEED_CK_BUFG_CASC3",
|
||||
"CLK_FEED_R_CK_GCLK18",
|
||||
"CLK_FEED_WW2END2",
|
||||
"CLK_FEED_EE2BEG1",
|
||||
"CLK_FEED_WW4END0",
|
||||
"CLK_FEED_CK_BUFG_CASC25",
|
||||
"CLK_PMV_IMUX16_0",
|
||||
"CLK_FEED_LH2",
|
||||
"CLK_PMV_LOGIC_OUTS6_0",
|
||||
"CLK_FEED_R_CK_GCLK25",
|
||||
"CLK_PMV_CLK0_0",
|
||||
"CLK_PMV_IMUX11_0",
|
||||
"CLK_FEED_EE4B3",
|
||||
"CLK_FEED_CK_BUFG_CASC24",
|
||||
"CLK_FEED_WW2END1",
|
||||
"CLK_PMV_LOGIC_OUTS23_0",
|
||||
"CLK_FEED_LH12",
|
||||
"CLK_FEED_LH7",
|
||||
"CLK_FEED_R_CK_GCLK14",
|
||||
"CLK_FEED_SW2A1",
|
||||
"CLK_PMV_IMUX6_0",
|
||||
"CLK_PMV_LOGIC_OUTS22_0",
|
||||
"CLK_PMV_IMUX23_0",
|
||||
"CLK_FEED_EE2BEG0",
|
||||
"CLK_FEED_CK_BUFG_CASC2",
|
||||
"CLK_FEED_CK_BUFG_CASC24",
|
||||
"CLK_FEED_EE2BEG2",
|
||||
"CLK_FEED_LH1",
|
||||
"CLK_FEED_CK_BUFG_CASC22",
|
||||
"CLK_PMV_IMUX11_0",
|
||||
"CLK_FEED_SE4C1",
|
||||
"CLK_PMV_LOGIC_OUTS23_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC25",
|
||||
"CLK_FEED_NE4C3",
|
||||
"CLK_PMV_FAN3_0",
|
||||
"CLK_FEED_SE2A1",
|
||||
"CLK_FEED_NE2A1",
|
||||
"CLK_FEED_R_CK_BUFG_CASC18",
|
||||
"CLK_PMV_LOGIC_OUTS19_0",
|
||||
"CLK_FEED_WW2END3",
|
||||
"CLK_FEED_MONITOR_N",
|
||||
"CLK_FEED_R_CK_BUFG_CASC17",
|
||||
"CLK_FEED_ER1BEG1",
|
||||
"CLK_FEED_EE4BEG1",
|
||||
"CLK_PMV_IMUX35_0",
|
||||
"CLK_FEED_WR1END1",
|
||||
"CLK_FEED_R_CK_GCLK26",
|
||||
"CLK_PMV_IMUX19_0",
|
||||
"CLK_PMV_LOGIC_OUTS0_0",
|
||||
"CLK_FEED_R_CK_GCLK16",
|
||||
"CLK_PMV_FAN5_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC9",
|
||||
"CLK_FEED_EE4BEG2",
|
||||
"CLK_PMV_LOGIC_OUTS12_0",
|
||||
"CLK_PMV_BYP3_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC7",
|
||||
"CLK_FEED_WW4C3",
|
||||
"CLK_FEED_R_CK_GCLK29",
|
||||
"CLK_FEED_CK_BUFG_CASC6",
|
||||
"CLK_PMV_IMUX43_0",
|
||||
"CLK_FEED_LH2",
|
||||
"CLK_FEED_SW4END2",
|
||||
"CLK_FEED_WW4END0",
|
||||
"CLK_FEED_CK_GCLK12",
|
||||
"CLK_FEED_CK_BUFG_CASC31",
|
||||
"CLK_FEED_R_CK_GCLK9",
|
||||
"CLK_FEED_CK_BUFG_CASC11",
|
||||
"CLK_FEED_NW2A1",
|
||||
"CLK_FEED_LH9",
|
||||
"CLK_FEED_WW2END0",
|
||||
"CLK_FEED_CK_GCLK9",
|
||||
"CLK_FEED_R_CK_GCLK22",
|
||||
"CLK_PMV_IMUX24_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC10",
|
||||
"CLK_FEED_EE4BEG0",
|
||||
"CLK_PMV_IMUX10_0",
|
||||
"CLK_FEED_NW4END0",
|
||||
"CLK_FEED_CK_GCLK7",
|
||||
"CLK_FEED_CK_BUFG_CASC19",
|
||||
"CLK_FEED_EE2BEG1",
|
||||
"CLK_FEED_SE4BEG0",
|
||||
"CLK_FEED_R_CK_GCLK27",
|
||||
"CLK_FEED_CK_GCLK30",
|
||||
"CLK_FEED_R_CK_BUFG_CASC12",
|
||||
"CLK_FEED_CK_BUFG_CASC4",
|
||||
"CLK_FEED_CK_BUFG_CASC20",
|
||||
"CLK_PMV_IMUX28_0",
|
||||
"CLK_PMV_BYP6_0",
|
||||
"CLK_PMV_LOGIC_OUTS5_0",
|
||||
"CLK_FEED_R_CK_GCLK20",
|
||||
"CLK_FEED_SE2A3",
|
||||
"CLK_PMV_IMUX40_0",
|
||||
"CLK_FEED_SW2A2",
|
||||
"CLK_FEED_NE4C1",
|
||||
"CLK_FEED_SE4BEG1",
|
||||
"CLK_FEED_ER1BEG0",
|
||||
"CLK_PMV_LOGIC_OUTS16_0",
|
||||
"CLK_PMV_IMUX42_0",
|
||||
"CLK_FEED_EE4A1",
|
||||
"CLK_FEED_WW4C0",
|
||||
"CLK_PMVIOB_A1",
|
||||
"CLK_FEED_R_CK_GCLK11",
|
||||
"CLK_FEED_NE2A3",
|
||||
"CLK_FEED_SW4A3",
|
||||
"CLK_PMV_LOGIC_OUTS6_0",
|
||||
"CLK_PMV_IMUX27_0",
|
||||
"CLK_FEED_NW4A2",
|
||||
"CLK_PMV_IMUX38_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC1",
|
||||
"CLK_PMVIOB_O",
|
||||
"CLK_PMV_LOGIC_OUTS14_0",
|
||||
"CLK_PMV_IMUX30_0",
|
||||
"CLK_FEED_CK_GCLK23",
|
||||
"CLK_FEED_CK_GCLK18",
|
||||
"CLK_FEED_R_CK_BUFG_CASC20",
|
||||
"CLK_FEED_NE4BEG3",
|
||||
"CLK_FEED_CK_GCLK16",
|
||||
"CLK_FEED_SW4A1",
|
||||
"CLK_FEED_R_CK_BUFG_CASC23",
|
||||
"CLK_FEED_CK_GCLK21",
|
||||
"CLK_FEED_MONITOR_P",
|
||||
"CLK_FEED_LH8",
|
||||
"CLK_FEED_WL1END3",
|
||||
"CLK_FEED_R_CK_GCLK18",
|
||||
"CLK_FEED_WW4END1",
|
||||
"CLK_FEED_LH5",
|
||||
"CLK_FEED_SW4END0",
|
||||
"CLK_FEED_WW4A1",
|
||||
"CLK_FEED_R_CK_GCLK15",
|
||||
"CLK_FEED_CK_BUFG_CASC18",
|
||||
"CLK_FEED_R_CK_BUFG_CASC6",
|
||||
"CLK_FEED_ER1BEG3",
|
||||
"CLK_FEED_SE4BEG2",
|
||||
"CLK_FEED_CK_GCLK1",
|
||||
"CLK_FEED_WR1END2",
|
||||
"CLK_FEED_NW4A3",
|
||||
"CLK_FEED_CK_GCLK24",
|
||||
"CLK_FEED_EE4A3",
|
||||
"CLK_FEED_R_CK_BUFG_CASC0",
|
||||
"CLK_PMV_LOGIC_OUTS18_0",
|
||||
"CLK_FEED_R_CK_GCLK12",
|
||||
"CLK_PMV_CTRL1_0",
|
||||
"CLK_FEED_CK_GCLK14",
|
||||
"CLK_PMV_FAN4_0",
|
||||
"CLK_FEED_CK_GCLK4",
|
||||
"CLK_FEED_EE4C0",
|
||||
"CLK_FEED_EE4B3",
|
||||
"CLK_FEED_R_CK_GCLK24",
|
||||
"CLK_FEED_EE4A2",
|
||||
"CLK_PMV_IMUX44_0",
|
||||
"CLK_PMV_IMUX21_0",
|
||||
"CLK_FEED_R_CK_GCLK30",
|
||||
"CLK_FEED_R_CK_BUFG_CASC24",
|
||||
"CLK_FEED_CK_BUFG_CASC13",
|
||||
"CLK_FEED_R_CK_BUFG_CASC5",
|
||||
"CLK_FEED_NW4END3",
|
||||
"CLK_PMV_BYP0_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC21",
|
||||
"CLK_PMV_IMUX47_0",
|
||||
"CLK_FEED_WW4C1",
|
||||
"CLK_PMV_IMUX32_0",
|
||||
"CLK_PMV_LOGIC_OUTS1_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC8",
|
||||
"CLK_FEED_SE4C3",
|
||||
"CLK_PMV_IMUX26_0",
|
||||
"CLK_FEED_CK_BUFG_CASC10",
|
||||
"CLK_FEED_SW4A0",
|
||||
"CLK_FEED_CK_BUFG_CASC27",
|
||||
"CLK_FEED_R_CK_BUFG_CASC13",
|
||||
"CLK_PMV_IMUX17_0",
|
||||
"CLK_FEED_NE2A2",
|
||||
"CLK_FEED_SW2A1",
|
||||
"CLK_FEED_CK_GCLK15",
|
||||
"CLK_FEED_SW2A0",
|
||||
"CLK_FEED_CK_GCLK11",
|
||||
"CLK_PMV_IMUX46_0",
|
||||
"CLK_FEED_CK_BUFG_CASC25",
|
||||
"CLK_PMV_IMUX12_0",
|
||||
"CLK_FEED_CK_GCLK2",
|
||||
"CLK_FEED_CK_GCLK25",
|
||||
"CLK_PMV_IMUX14_0",
|
||||
"CLK_FEED_R_CK_GCLK0",
|
||||
"CLK_FEED_CK_GCLK3",
|
||||
"CLK_FEED_WL1END1",
|
||||
"CLK_FEED_R_CK_GCLK14",
|
||||
"CLK_PMV_IMUX0_0",
|
||||
"CLK_FEED_CK_GCLK10",
|
||||
"CLK_FEED_WW2END1",
|
||||
"CLK_FEED_WW4A3",
|
||||
"CLK_FEED_R_CK_BUFG_CASC31",
|
||||
"CLK_FEED_CK_GCLK5",
|
||||
"CLK_FEED_NW4A1",
|
||||
"CLK_FEED_CK_GCLK27",
|
||||
"CLK_FEED_CK_BUFG_CASC16",
|
||||
"CLK_FEED_R_CK_GCLK28",
|
||||
"CLK_FEED_EL1BEG1",
|
||||
"CLK_PMVIOB_EN",
|
||||
"CLK_FEED_R_CK_GCLK19",
|
||||
"CLK_FEED_CK_BUFG_CASC8",
|
||||
"CLK_PMV_IMUX5_0",
|
||||
"CLK_FEED_LH12",
|
||||
"CLK_FEED_R_CK_GCLK17",
|
||||
"CLK_FEED_R_CK_BUFG_CASC18",
|
||||
"CLK_FEED_MONITOR_P",
|
||||
"CLK_FEED_SE4BEG1",
|
||||
"CLK_FEED_MONITOR_N",
|
||||
"CLK_PMV_IMUX47_0",
|
||||
"CLK_PMV_IMUX45_0",
|
||||
"CLK_FEED_CK_BUFG_CASC18",
|
||||
"CLK_PMV_IMUX36_0",
|
||||
"CLK_PMV_LOGIC_OUTS8_0",
|
||||
"CLK_FEED_CK_BUFG_CASC15",
|
||||
"CLK_PMV_LOGIC_OUTS19_0",
|
||||
"CLK_PMV_IMUX34_0",
|
||||
"CLK_FEED_SW2A0",
|
||||
"CLK_FEED_CK_BUFG_CASC0",
|
||||
"CLK_FEED_WR1END0",
|
||||
"CLK_FEED_LH11",
|
||||
"CLK_PMV_BYP2_0",
|
||||
"CLK_FEED_WW2A1",
|
||||
"CLK_PMV_IMUX8_0",
|
||||
"CLK_FEED_EL1BEG3",
|
||||
"CLK_PMV_IMUX39_0",
|
||||
"CLK_FEED_CK_BUFG_CASC29",
|
||||
"CLK_PMV_IMUX21_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC20",
|
||||
"CLK_PMV_IMUX41_0",
|
||||
"CLK_PMV_IMUX27_0",
|
||||
"CLK_PMV_IMUX25_0",
|
||||
"CLK_FEED_NE4BEG1",
|
||||
"CLK_PMV_FAN6_0",
|
||||
"CLK_FEED_WW4B0",
|
||||
"CLK_PMV_LOGIC_OUTS1_0",
|
||||
"CLK_PMV_IMUX28_0",
|
||||
"CLK_FEED_NE2A1",
|
||||
"CLK_PMV_FAN4_0",
|
||||
"CLK_PMVIOB_ODIV4",
|
||||
"CLK_FEED_SE4C0",
|
||||
"CLK_FEED_R_CK_GCLK8",
|
||||
"CLK_FEED_R_CK_GCLK22",
|
||||
"CLK_PMV_LOGIC_OUTS20_0",
|
||||
"CLK_PMV_IMUX19_0",
|
||||
"CLK_FEED_WW2END3",
|
||||
"CLK_FEED_R_CK_BUFG_CASC25",
|
||||
"CLK_FEED_EE2A1",
|
||||
"CLK_FEED_EE4B2",
|
||||
"CLK_FEED_CK_GCLK0",
|
||||
"CLK_FEED_WW4B2",
|
||||
"CLK_PMV_IMUX46_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC26",
|
||||
"CLK_FEED_R_CK_BUFG_CASC22",
|
||||
"CLK_FEED_SW2A2",
|
||||
"CLK_FEED_CK_GCLK8",
|
||||
"CLK_FEED_LH11",
|
||||
"CLK_FEED_NW2A0",
|
||||
"CLK_FEED_CK_BUFG_CASC22",
|
||||
"CLK_FEED_CK_GCLK18",
|
||||
"CLK_FEED_CK_GCLK26",
|
||||
"CLK_FEED_CK_BUFG_CASC20",
|
||||
"CLK_PMV_IMUX35_0",
|
||||
"CLK_FEED_CK_GCLK3",
|
||||
"CLK_PMV_IMUX18_0",
|
||||
"CLK_FEED_SE4C1",
|
||||
"CLK_FEED_NW4A2",
|
||||
"CLK_FEED_WW2END0",
|
||||
"CLK_FEED_CK_BUFG_CASC6",
|
||||
"CLK_PMVIOB_EN",
|
||||
"CLK_FEED_SE2A0",
|
||||
"CLK_PMV_IMUX12_0",
|
||||
"CLK_FEED_WW4A0",
|
||||
"CLK_PMVIOB_A1",
|
||||
"CLK_FEED_EE4BEG2",
|
||||
"CLK_FEED_CK_GCLK10",
|
||||
"CLK_FEED_R_CK_BUFG_CASC30",
|
||||
"CLK_FEED_SW4END3",
|
||||
"CLK_FEED_EL1BEG0",
|
||||
"CLK_PMV_IMUX17_0",
|
||||
"CLK_FEED_EE4BEG0",
|
||||
"CLK_FEED_WR1END3",
|
||||
"CLK_PMV_LOGIC_OUTS16_0",
|
||||
"CLK_FEED_CK_GCLK5",
|
||||
"CLK_FEED_CK_BUFG_CASC30",
|
||||
"CLK_FEED_SE4BEG0",
|
||||
"CLK_PMV_LOGIC_OUTS21_0",
|
||||
"CLK_FEED_EE4BEG1",
|
||||
"CLK_FEED_SE4BEG3",
|
||||
"CLK_FEED_CK_GCLK17",
|
||||
"CLK_FEED_R_CK_BUFG_CASC6",
|
||||
"CLK_FEED_SW4A1",
|
||||
"CLK_FEED_R_CK_GCLK23",
|
||||
"CLK_FEED_EE2BEG3",
|
||||
"CLK_FEED_R_CK_BUFG_CASC16",
|
||||
"CLK_FEED_R_CK_GCLK21",
|
||||
"CLK_FEED_R_CK_GCLK10",
|
||||
"CLK_FEED_NE4C3",
|
||||
"CLK_FEED_R_CK_BUFG_CASC21",
|
||||
"CLK_PMV_LOGIC_OUTS4_0",
|
||||
"CLK_PMV_IMUX14_0",
|
||||
"CLK_FEED_NW4A0",
|
||||
"CLK_PMV_BYP5_0",
|
||||
"CLK_FEED_SE4BEG2",
|
||||
"CLK_FEED_R_CK_BUFG_CASC31",
|
||||
"CLK_FEED_CK_BUFG_CASC11",
|
||||
"CLK_FEED_R_CK_GCLK20",
|
||||
"CLK_FEED_SW4END0",
|
||||
"CLK_PMV_LOGIC_OUTS7_0",
|
||||
"CLK_PMV_IMUX32_0",
|
||||
"CLK_FEED_CK_BUFG_CASC26",
|
||||
"CLK_PMV_IMUX9_0",
|
||||
"CLK_FEED_LH5",
|
||||
"CLK_PMV_IMUX37_0",
|
||||
"CLK_PMV_IMUX7_0",
|
||||
"CLK_FEED_R_CK_GCLK31",
|
||||
"CLK_FEED_WW4B1",
|
||||
"CLK_FEED_CK_GCLK24",
|
||||
"CLK_FEED_WW4END1",
|
||||
"CLK_FEED_R_CK_GCLK17",
|
||||
"CLK_FEED_R_CK_GCLK7",
|
||||
"CLK_FEED_CK_BUFG_CASC28",
|
||||
"CLK_FEED_EE2A3",
|
||||
"CLK_FEED_CK_GCLK14",
|
||||
"CLK_FEED_CK_GCLK13",
|
||||
"CLK_FEED_CK_BUFG_CASC1",
|
||||
"CLK_FEED_R_CK_BUFG_CASC9",
|
||||
"CLK_FEED_LH8",
|
||||
"CLK_FEED_EE4C2",
|
||||
"CLK_FEED_WW4B3",
|
||||
"CLK_FEED_EE4A3",
|
||||
"CLK_FEED_NW2A2",
|
||||
"CLK_FEED_CK_BUFG_CASC10",
|
||||
"CLK_FEED_WL1END1",
|
||||
"CLK_PMV_BYP2_0",
|
||||
"CLK_FEED_SE4C3",
|
||||
"CLK_FEED_WL1END2",
|
||||
"CLK_PMVIOB_A0",
|
||||
"CLK_PMV_LOGIC_OUTS13_0",
|
||||
"CLK_FEED_LH3",
|
||||
"CLK_PMV_LOGIC_OUTS0_0",
|
||||
"CLK_PMV_IMUX39_0",
|
||||
"CLK_FEED_R_CK_GCLK13",
|
||||
"CLK_FEED_NW2A3",
|
||||
"CLK_FEED_LH4",
|
||||
"CLK_FEED_EE4B0",
|
||||
"CLK_PMV_IMUX29_0",
|
||||
"CLK_FEED_EE2BEG3",
|
||||
"CLK_FEED_R_CK_BUFG_CASC14",
|
||||
"CLK_FEED_R_CK_BUFG_CASC16",
|
||||
"CLK_FEED_CK_BUFG_CASC12"
|
||||
"CLK_FEED_SE4C2",
|
||||
"CLK_FEED_SW2A3",
|
||||
"CLK_FEED_EE4BEG3",
|
||||
"CLK_FEED_CK_GCLK15",
|
||||
"CLK_FEED_R_CK_GCLK1",
|
||||
"CLK_FEED_R_CK_GCLK15",
|
||||
"CLK_FEED_R_CK_GCLK12",
|
||||
"CLK_PMV_IMUX38_0",
|
||||
"CLK_FEED_R_CK_GCLK28",
|
||||
"CLK_FEED_CK_BUFG_CASC17",
|
||||
"CLK_PMV_LOGIC_OUTS10_0",
|
||||
"CLK_PMV_CLK1_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC13",
|
||||
"CLK_PMV_IMUX2_0",
|
||||
"CLK_FEED_NW4END2",
|
||||
"CLK_FEED_WW4END2",
|
||||
"CLK_PMV_LOGIC_OUTS11_0",
|
||||
"CLK_PMV_IMUX3_0",
|
||||
"CLK_FEED_NE2A3",
|
||||
"CLK_FEED_R_CK_BUFG_CASC3",
|
||||
"CLK_PMV_IMUX42_0"
|
||||
],
|
||||
"tile_type": "CLK_PMVIOB",
|
||||
"sites": []
|
||||
}
|
||||
|
|
@ -1,71 +1,71 @@
|
|||
{
|
||||
"tile_type": "CLK_TERM",
|
||||
"pips": {},
|
||||
"wires": [
|
||||
"CLK_TERM_R_GCLK6",
|
||||
"CLK_TERM_R_GCLK28",
|
||||
"CLK_TERM_GCLK15",
|
||||
"CLK_TERM_R_GCLK12",
|
||||
"CLK_TERM_R_GCLK23",
|
||||
"CLK_TERM_R_GCLK20",
|
||||
"CLK_TERM_GCLK1",
|
||||
"CLK_TERM_R_GCLK14",
|
||||
"CLK_TERM_GCLK28",
|
||||
"CLK_TERM_R_GCLK3",
|
||||
"CLK_TERM_R_GCLK30",
|
||||
"CLK_TERM_GCLK13",
|
||||
"CLK_TERM_GCLK21",
|
||||
"CLK_TERM_GCLK14",
|
||||
"CLK_TERM_GCLK0",
|
||||
"CLK_TERM_GCLK26",
|
||||
"CLK_TERM_R_GCLK4",
|
||||
"CLK_TERM_R_GCLK5",
|
||||
"CLK_TERM_R_GCLK18",
|
||||
"CLK_TERM_R_GCLK31",
|
||||
"CLK_TERM_GCLK10",
|
||||
"CLK_TERM_R_GCLK8",
|
||||
"CLK_TERM_R_GCLK22",
|
||||
"CLK_TERM_GCLK22",
|
||||
"CLK_TERM_GCLK24",
|
||||
"CLK_TERM_R_GCLK1",
|
||||
"CLK_TERM_GCLK17",
|
||||
"CLK_TERM_GCLK9",
|
||||
"CLK_TERM_GCLK2",
|
||||
"CLK_TERM_R_GCLK0",
|
||||
"CLK_TERM_GCLK3",
|
||||
"CLK_TERM_R_GCLK26",
|
||||
"CLK_TERM_GCLK25",
|
||||
"CLK_TERM_R_GCLK19",
|
||||
"CLK_TERM_GCLK19",
|
||||
"CLK_TERM_GCLK30",
|
||||
"CLK_TERM_R_GCLK15",
|
||||
"CLK_TERM_GCLK29",
|
||||
"CLK_TERM_GCLK5",
|
||||
"CLK_TERM_R_GCLK17",
|
||||
"CLK_TERM_GCLK7",
|
||||
"CLK_TERM_R_GCLK21",
|
||||
"CLK_TERM_GCLK18",
|
||||
"CLK_TERM_R_GCLK24",
|
||||
"CLK_TERM_R_GCLK7",
|
||||
"CLK_TERM_GCLK8",
|
||||
"CLK_TERM_GCLK12",
|
||||
"CLK_TERM_R_GCLK13",
|
||||
"CLK_TERM_GCLK2",
|
||||
"CLK_TERM_R_GCLK2",
|
||||
"CLK_TERM_R_GCLK0",
|
||||
"CLK_TERM_R_GCLK9",
|
||||
"CLK_TERM_R_GCLK16",
|
||||
"CLK_TERM_R_GCLK27",
|
||||
"CLK_TERM_R_GCLK11",
|
||||
"CLK_TERM_GCLK6",
|
||||
"CLK_TERM_R_GCLK10",
|
||||
"CLK_TERM_GCLK20",
|
||||
"CLK_TERM_GCLK23",
|
||||
"CLK_TERM_R_GCLK28",
|
||||
"CLK_TERM_GCLK16",
|
||||
"CLK_TERM_GCLK6",
|
||||
"CLK_TERM_GCLK1",
|
||||
"CLK_TERM_R_GCLK25",
|
||||
"CLK_TERM_GCLK11",
|
||||
"CLK_TERM_GCLK27",
|
||||
"CLK_TERM_GCLK31",
|
||||
"CLK_TERM_GCLK14",
|
||||
"CLK_TERM_R_GCLK30",
|
||||
"CLK_TERM_GCLK26",
|
||||
"CLK_TERM_GCLK24",
|
||||
"CLK_TERM_GCLK7",
|
||||
"CLK_TERM_R_GCLK13",
|
||||
"CLK_TERM_R_GCLK29",
|
||||
"CLK_TERM_GCLK4"
|
||||
"CLK_TERM_R_GCLK10",
|
||||
"CLK_TERM_R_GCLK5",
|
||||
"CLK_TERM_GCLK21",
|
||||
"CLK_TERM_R_GCLK18",
|
||||
"CLK_TERM_R_GCLK14",
|
||||
"CLK_TERM_GCLK9",
|
||||
"CLK_TERM_GCLK15",
|
||||
"CLK_TERM_GCLK29",
|
||||
"CLK_TERM_R_GCLK12",
|
||||
"CLK_TERM_GCLK19",
|
||||
"CLK_TERM_R_GCLK21",
|
||||
"CLK_TERM_GCLK31",
|
||||
"CLK_TERM_GCLK10",
|
||||
"CLK_TERM_GCLK17",
|
||||
"CLK_TERM_R_GCLK22",
|
||||
"CLK_TERM_GCLK8",
|
||||
"CLK_TERM_R_GCLK9",
|
||||
"CLK_TERM_GCLK22",
|
||||
"CLK_TERM_R_GCLK31",
|
||||
"CLK_TERM_GCLK20",
|
||||
"CLK_TERM_R_GCLK17",
|
||||
"CLK_TERM_R_GCLK11",
|
||||
"CLK_TERM_GCLK0",
|
||||
"CLK_TERM_GCLK30",
|
||||
"CLK_TERM_GCLK4",
|
||||
"CLK_TERM_R_GCLK27",
|
||||
"CLK_TERM_R_GCLK4",
|
||||
"CLK_TERM_R_GCLK16",
|
||||
"CLK_TERM_R_GCLK20",
|
||||
"CLK_TERM_GCLK13",
|
||||
"CLK_TERM_GCLK18",
|
||||
"CLK_TERM_GCLK23",
|
||||
"CLK_TERM_R_GCLK2",
|
||||
"CLK_TERM_GCLK5",
|
||||
"CLK_TERM_R_GCLK19",
|
||||
"CLK_TERM_R_GCLK3",
|
||||
"CLK_TERM_R_GCLK24",
|
||||
"CLK_TERM_GCLK27",
|
||||
"CLK_TERM_R_GCLK7",
|
||||
"CLK_TERM_R_GCLK23",
|
||||
"CLK_TERM_R_GCLK1",
|
||||
"CLK_TERM_R_GCLK6",
|
||||
"CLK_TERM_GCLK28",
|
||||
"CLK_TERM_R_GCLK8",
|
||||
"CLK_TERM_GCLK12",
|
||||
"CLK_TERM_GCLK25",
|
||||
"CLK_TERM_GCLK11",
|
||||
"CLK_TERM_R_GCLK15"
|
||||
],
|
||||
"tile_type": "CLK_TERM",
|
||||
"sites": []
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -1,230 +1,230 @@
|
|||
{
|
||||
"tile_type": "CMT_PMV",
|
||||
"pips": {},
|
||||
"wires": [
|
||||
"CMT_PMV_IMUX37",
|
||||
"CMT_PMV_IMUX42",
|
||||
"CMT_PMV_WW4END1",
|
||||
"CMT_PMV_WW4A1",
|
||||
"CMT_PMV_FAN1",
|
||||
"CMT_PMV_IMUX38",
|
||||
"CMT_PMV_LOGIC_OUTS3",
|
||||
"CMT_PMV_SW4A1",
|
||||
"CMT_PMV_SE4C2",
|
||||
"CMT_PMV_FAN6",
|
||||
"CMT_PMV_WL1END2",
|
||||
"CMT_PMV_EE4C3",
|
||||
"CMT_PMV_SW2A0",
|
||||
"CMT_PMV_LOGIC_OUTS4",
|
||||
"CMT_PMV_MONITOR_N",
|
||||
"CMT_PMV_NW4END1",
|
||||
"CMT_PMV_NW2A0",
|
||||
"CMT_PMV_EE4C1",
|
||||
"CMT_PMV_LOGIC_OUTS11",
|
||||
"CMT_PMV_EE2A1",
|
||||
"CMT_PMV_IMUX46",
|
||||
"CMT_PMV_LOGIC_OUTS7",
|
||||
"CMT_PMV_WL1END0",
|
||||
"CMT_PMV_IMUX6",
|
||||
"CMT_PMV_NW4A3",
|
||||
"CMT_PMV_WW4B3",
|
||||
"CMT_PMV_SW2A2",
|
||||
"CMT_PMV_IMUX47",
|
||||
"CMT_PMV_SE2A2",
|
||||
"CMT_PMV_NE4C2",
|
||||
"CMT_PMV_NE4C1",
|
||||
"CMT_PMV_EE4B3",
|
||||
"CMT_PMV_WW2A1",
|
||||
"CMT_PMV_NE4BEG0",
|
||||
"CMT_PMV_SW2A3",
|
||||
"CMT_PMV_EE2BEG3",
|
||||
"CMT_PMV_IMUX15",
|
||||
"CMT_PMV_FAN4",
|
||||
"CMT_PMV_WW4C1",
|
||||
"CMT_PMV_EE2BEG0",
|
||||
"CMT_PMV_EE4C2",
|
||||
"CMT_PMV_LOGIC_OUTS8",
|
||||
"CMT_PMV_LOGIC_OUTS2",
|
||||
"CMT_PMV_NW4A0",
|
||||
"CMT_PMV_WW4B0",
|
||||
"CMT_PMV_WW4B2",
|
||||
"CMT_PMV_BYP4",
|
||||
"CMT_PMV_IMUX20",
|
||||
"CMT_PMV_IMUX7",
|
||||
"CMT_PMV_WW4C2",
|
||||
"CMT_PMV_NW4A1",
|
||||
"CMT_PMV_LOGIC_OUTS16",
|
||||
"CMT_PMV_WW4END2",
|
||||
"CMT_PMV_IMUX25",
|
||||
"CMT_PMV_SW4END3",
|
||||
"CMT_PMV_LOGIC_OUTS23",
|
||||
"CMT_PMV_WW4END0",
|
||||
"CMT_PMV_IMUX39",
|
||||
"CMT_PMV_IMUX9",
|
||||
"CMT_PMV_SE2A0",
|
||||
"CMT_PMV_LOGIC_OUTS22",
|
||||
"CMT_PMV_BYP6",
|
||||
"CMT_PMV_LH9",
|
||||
"CMT_PMV_LOGIC_OUTS10",
|
||||
"CMT_PMV_IMUX31",
|
||||
"CMT_PMV_EE4B1",
|
||||
"CMT_PMV_LOGIC_OUTS1",
|
||||
"CMT_PMV_SW4A2",
|
||||
"CMT_PMV_WL1END1",
|
||||
"CMT_PMV_IMUX28",
|
||||
"CMT_PMV_IMUX27",
|
||||
"CMT_PMV_LOGIC_OUTS5",
|
||||
"CMT_PMV_SE2A3",
|
||||
"CMT_PMV_WR1END0",
|
||||
"CMT_PMV_SW4END1",
|
||||
"CMT_PMV_SW4END2",
|
||||
"CMT_PMV_IMUX23",
|
||||
"CMT_PMV_NW4END0",
|
||||
"CMT_PMV_EE4A3",
|
||||
"CMT_PMV_EE4A1",
|
||||
"CMT_PMV_NW2A3",
|
||||
"CMT_PMV_IMUX30",
|
||||
"CMT_PMV_SE4BEG3",
|
||||
"CMT_PMV_CTRL0",
|
||||
"CMT_PMV_IMUX3",
|
||||
"CMT_PMV_NW2A2",
|
||||
"CMT_PMV_ER1BEG2",
|
||||
"CMT_PMV_IMUX26",
|
||||
"CMT_PMV_NE4BEG3",
|
||||
"CMT_PMV_EE4A0",
|
||||
"CMT_PMV_LH6",
|
||||
"CMT_PMV_NE2A0",
|
||||
"CMT_PMV_WW2END3",
|
||||
"CMT_PMV_FAN7",
|
||||
"CMT_PMV_LOGIC_OUTS13",
|
||||
"CMT_PMV_IMUX10",
|
||||
"CMT_PMV_SE4C1",
|
||||
"CMT_PMV_NE4C3",
|
||||
"CMT_PMV_LH1",
|
||||
"CMT_PMV_EE4A2",
|
||||
"CMT_PMV_FAN3",
|
||||
"CMT_PMV_WW2END2",
|
||||
"CMT_PMV_LOGIC_OUTS15",
|
||||
"CMT_PMV_SW4END0",
|
||||
"CMT_PMV_IMUX29",
|
||||
"CMT_PMV_NE2A2",
|
||||
"CMT_PMV_BYP5",
|
||||
"CMT_PMV_MONITOR_P",
|
||||
"CMT_PMV_SE2A1",
|
||||
"CMT_PMV_EE4B2",
|
||||
"CMT_PMV_LH8",
|
||||
"CMT_PMV_NW4END3",
|
||||
"CMT_PMV_NE2A1",
|
||||
"CMT_PMV_SE4BEG2",
|
||||
"CMT_PMV_IMUX8",
|
||||
"CMT_PMV_IMUX24",
|
||||
"CMT_PMV_IMUX18",
|
||||
"CMT_PMV_WW2END1",
|
||||
"CMT_PMV_WW2END0",
|
||||
"CMT_PMV_SE4C0",
|
||||
"L_TERM_INT_PHASER_TO_IO_OCLK",
|
||||
"CMT_PMV_WW2A2",
|
||||
"CMT_PMV_EL1BEG2",
|
||||
"CMT_PMV_SE4BEG0",
|
||||
"CMT_PMV_LOGIC_OUTS21",
|
||||
"CMT_PMV_IMUX22",
|
||||
"CMT_PMV_LOGIC_OUTS12",
|
||||
"CMT_PMV_WW4B1",
|
||||
"CMT_PMV_FAN0",
|
||||
"L_TERM_INT_PHASER_TO_IO_ICLKDIV",
|
||||
"CMT_PMV_WW2A3",
|
||||
"L_TERM_INT_PHASER_TO_IO_ICLK",
|
||||
"L_TERM_INT_PHASER_TO_IO_OCLK1X_90",
|
||||
"CMT_PMV_WW4C3",
|
||||
"CMT_PMV_CLK0",
|
||||
"CMT_PMV_WR1END2",
|
||||
"CMT_PMV_LH10",
|
||||
"CMT_PMV_EE2A0",
|
||||
"CMT_PMV_IMUX32",
|
||||
"CMT_PMV_EE4B0",
|
||||
"CMT_PMV_IMUX12",
|
||||
"CMT_PMV_IMUX19",
|
||||
"CMT_PMV_SW4A3",
|
||||
"CMT_PMV_LH3",
|
||||
"CMT_PMV_BYP2",
|
||||
"CMT_PMV_LH2",
|
||||
"CMT_PMV_LH11",
|
||||
"CMT_PMV_LOGIC_OUTS19",
|
||||
"CMT_PMV_IMUX41",
|
||||
"CMT_PMV_NE4BEG1",
|
||||
"CMT_PMV_LOGIC_OUTS9",
|
||||
"CMT_PMV_SW2A1",
|
||||
"CMT_PMV_EE4C0",
|
||||
"CMT_PMV_EE2BEG1",
|
||||
"CMT_PMV_WW4A2",
|
||||
"CMT_PMV_IMUX45",
|
||||
"CMT_PMV_BYP0",
|
||||
"CMT_PMV_WW4C0",
|
||||
"CMT_PMV_EE4BEG1",
|
||||
"CMT_PMV_NW4END0",
|
||||
"CMT_PMV_LOGIC_OUTS21",
|
||||
"CMT_PMV_IMUX30",
|
||||
"CMT_PMV_ER1BEG1",
|
||||
"CMT_PMV_NW2A1",
|
||||
"CMT_PMV_IMUX3",
|
||||
"CMT_PMV_CTRL0",
|
||||
"CMT_PMV_WW4END1",
|
||||
"CMT_PMV_EE4B3",
|
||||
"CMT_PMV_LH10",
|
||||
"CMT_PMV_BYP6",
|
||||
"CMT_PMV_LOGIC_OUTS5",
|
||||
"CMT_PMV_LOGIC_OUTS0",
|
||||
"CMT_PMV_EE4BEG3",
|
||||
"CMT_PMV_WW2END2",
|
||||
"CMT_PMV_BYP1",
|
||||
"CMT_PMV_BYP2",
|
||||
"CMT_PMV_IMUX35",
|
||||
"CMT_PMV_IMUX8",
|
||||
"CMT_PMV_LH11",
|
||||
"CMT_PMV_NE4BEG2",
|
||||
"CMT_PMV_WW4A1",
|
||||
"CMT_PMV_NW2A3",
|
||||
"CMT_PMV_CLK1",
|
||||
"CMT_PMV_WW4B1",
|
||||
"CMT_PMV_IMUX6",
|
||||
"CMT_PMV_NW4END2",
|
||||
"CMT_PMV_SE4BEG1",
|
||||
"CMT_PMV_EL1BEG0",
|
||||
"CMT_PMV_IMUX13",
|
||||
"CMT_PMV_NW4A2",
|
||||
"CMT_PMV_EE2BEG0",
|
||||
"CMT_PMV_IMUX15",
|
||||
"CMT_PMV_WR1END0",
|
||||
"CMT_PMV_SE2A2",
|
||||
"CMT_PMV_LOGIC_OUTS10",
|
||||
"CMT_PMV_SE4C0",
|
||||
"CMT_PMV_IMUX11",
|
||||
"CMT_PMV_FAN3",
|
||||
"CMT_PMV_IMUX40",
|
||||
"CMT_PMV_SE4C1",
|
||||
"CMT_PMV_EL1BEG1",
|
||||
"CMT_PMV_LH7",
|
||||
"CMT_PMV_NE2A3",
|
||||
"CMT_PMV_EL1BEG3",
|
||||
"CMT_PMV_EE2BEG2",
|
||||
"CMT_PMV_IMUX21",
|
||||
"CMT_PMV_CLK1",
|
||||
"CMT_PMV_WL1END3",
|
||||
"CMT_PMV_EE2A2",
|
||||
"CMT_PMV_IMUX34",
|
||||
"CMT_PMV_FAN2",
|
||||
"CMT_PMV_IMUX14",
|
||||
"CMT_PMV_LH12",
|
||||
"CMT_PMV_IMUX4",
|
||||
"CMT_PMV_LOGIC_OUTS0",
|
||||
"CMT_PMV_LOGIC_OUTS17",
|
||||
"CMT_PMV_LOGIC_OUTS6",
|
||||
"CMT_PMV_BYP1",
|
||||
"CMT_PMV_NE4BEG2",
|
||||
"CMT_PMV_SW4A0",
|
||||
"CMT_PMV_LOGIC_OUTS20",
|
||||
"CMT_PMV_LH4",
|
||||
"CMT_PMV_IMUX40",
|
||||
"CMT_PMV_IMUX17",
|
||||
"CMT_PMV_IMUX2",
|
||||
"CMT_PMV_WW4END3",
|
||||
"CMT_PMV_IMUX35",
|
||||
"CMT_PMV_IMUX43",
|
||||
"CMT_PMV_EE2A3",
|
||||
"CMT_PMV_EE4BEG3",
|
||||
"CMT_PMV_LOGIC_OUTS14",
|
||||
"CMT_PMV_WW2A0",
|
||||
"CMT_PMV_IMUX33",
|
||||
"CMT_PMV_WW4A0",
|
||||
"CMT_PMV_EE4BEG0",
|
||||
"CMT_PMV_SE4C3",
|
||||
"CMT_PMV_BYP3",
|
||||
"CMT_PMV_EE4BEG2",
|
||||
"CMT_PMV_BYP7",
|
||||
"CMT_PMV_IMUX1",
|
||||
"CMT_PMV_FAN5",
|
||||
"CMT_PMV_LH5",
|
||||
"CMT_PMV_NW2A1",
|
||||
"CMT_PMV_IMUX16",
|
||||
"CMT_PMV_NE4C0",
|
||||
"CMT_PMV_IMUX11",
|
||||
"CMT_PMV_ER1BEG3",
|
||||
"CMT_PMV_EE4C1",
|
||||
"CMT_PMV_LH3",
|
||||
"CMT_PMV_LOGIC_OUTS2",
|
||||
"CMT_PMV_LOGIC_OUTS15",
|
||||
"CMT_PMV_LOGIC_OUTS13",
|
||||
"CMT_PMV_LOGIC_OUTS18",
|
||||
"CMT_PMV_WW4A3",
|
||||
"CMT_PMV_IMUX36",
|
||||
"CMT_PMV_IMUX0",
|
||||
"CMT_PMV_ER1BEG0",
|
||||
"CMT_PMV_IMUX24",
|
||||
"CMT_PMV_LH6",
|
||||
"CMT_PMV_IMUX33",
|
||||
"CMT_PMV_WL1END2",
|
||||
"CMT_PMV_LOGIC_OUTS6",
|
||||
"CMT_PMV_IMUX5",
|
||||
"CMT_PMV_ER1BEG1",
|
||||
"CMT_PMV_WR1END3",
|
||||
"CMT_PMV_IMUX44",
|
||||
"L_TERM_INT_PHASER_TO_IO_OCLKDIV",
|
||||
"CMT_PMV_EE4B1",
|
||||
"CMT_PMV_LH8",
|
||||
"CMT_PMV_IMUX29",
|
||||
"CMT_PMV_EE4BEG1",
|
||||
"CMT_PMV_NE4BEG1",
|
||||
"CMT_PMV_IMUX27",
|
||||
"CMT_PMV_EE4A3",
|
||||
"CMT_PMV_FAN7",
|
||||
"CMT_PMV_SE4C3",
|
||||
"CMT_PMV_IMUX43",
|
||||
"CMT_PMV_SE4BEG0",
|
||||
"CMT_PMV_LH1",
|
||||
"CMT_PMV_EE2A0",
|
||||
"CMT_PMV_BYP0",
|
||||
"CMT_PMV_IMUX34",
|
||||
"CMT_PMV_SE2A3",
|
||||
"CMT_PMV_FAN4",
|
||||
"CMT_PMV_SE4BEG3",
|
||||
"CMT_PMV_IMUX0",
|
||||
"CMT_PMV_IMUX17",
|
||||
"CMT_PMV_IMUX36",
|
||||
"CMT_PMV_IMUX2",
|
||||
"CMT_PMV_IMUX22",
|
||||
"CMT_PMV_SW4END1",
|
||||
"CMT_PMV_WL1END0",
|
||||
"CMT_PMV_EL1BEG3",
|
||||
"CMT_PMV_ER1BEG0",
|
||||
"CMT_PMV_NW2A2",
|
||||
"CMT_PMV_SW4A0",
|
||||
"CMT_PMV_WW2A1",
|
||||
"CMT_PMV_IMUX1",
|
||||
"CMT_PMV_WL1END1",
|
||||
"CMT_PMV_LOGIC_OUTS7",
|
||||
"CMT_PMV_EE4B2",
|
||||
"CMT_PMV_BYP7",
|
||||
"CMT_PMV_FAN6",
|
||||
"CMT_PMV_SE2A0",
|
||||
"CMT_PMV_NE4C1",
|
||||
"CMT_PMV_IMUX26",
|
||||
"CMT_PMV_NW4A2",
|
||||
"CMT_PMV_SW4END3",
|
||||
"CMT_PMV_IMUX10",
|
||||
"CMT_PMV_IMUX32",
|
||||
"CMT_PMV_NE2A3",
|
||||
"CMT_PMV_LOGIC_OUTS3",
|
||||
"CMT_PMV_IMUX31",
|
||||
"CMT_PMV_NW4A0",
|
||||
"CMT_PMV_LOGIC_OUTS8",
|
||||
"CMT_PMV_IMUX19",
|
||||
"L_TERM_INT_PHASER_TO_IO_ICLK",
|
||||
"CMT_PMV_LOGIC_OUTS19",
|
||||
"CMT_PMV_WW4END3",
|
||||
"CMT_PMV_IMUX37",
|
||||
"CMT_PMV_LOGIC_OUTS4",
|
||||
"CMT_PMV_BYP4",
|
||||
"CMT_PMV_SW4A3",
|
||||
"CMT_PMV_NE2A0",
|
||||
"CMT_PMV_IMUX16",
|
||||
"CMT_PMV_SW2A3",
|
||||
"CMT_PMV_IMUX9",
|
||||
"CMT_PMV_WW4B2",
|
||||
"CMT_PMV_IMUX21",
|
||||
"CMT_PMV_EE4C2",
|
||||
"CMT_PMV_MONITOR_P",
|
||||
"CMT_PMV_WW4B0",
|
||||
"CMT_PMV_IMUX14",
|
||||
"CMT_PMV_NE4C3",
|
||||
"CMT_PMV_EE4BEG2",
|
||||
"CMT_PMV_NE4BEG0",
|
||||
"CMT_PMV_IMUX4",
|
||||
"CMT_PMV_EE2A1",
|
||||
"CMT_PMV_IMUX12",
|
||||
"CMT_PMV_WW2END0",
|
||||
"CMT_PMV_LOGIC_OUTS23",
|
||||
"CMT_PMV_EE4A1",
|
||||
"CMT_PMV_WR1END2",
|
||||
"CMT_PMV_EE2A2",
|
||||
"CMT_PMV_LOGIC_OUTS9",
|
||||
"CMT_PMV_LH9",
|
||||
"CMT_PMV_WW4C0",
|
||||
"CMT_PMV_NW4END3",
|
||||
"CMT_PMV_WW4A0",
|
||||
"CMT_PMV_EE2BEG2",
|
||||
"CMT_PMV_LH12",
|
||||
"CMT_PMV_WW4C2",
|
||||
"CMT_PMV_SW4END2",
|
||||
"CMT_PMV_LOGIC_OUTS14",
|
||||
"CMT_PMV_IMUX46",
|
||||
"CMT_PMV_WW2END1",
|
||||
"CMT_PMV_EE2BEG1",
|
||||
"CMT_PMV_LOGIC_OUTS1",
|
||||
"CMT_PMV_CTRL1",
|
||||
"CMT_PMV_WR1END1"
|
||||
"CMT_PMV_WW4END2",
|
||||
"CMT_PMV_LH2",
|
||||
"L_TERM_INT_PHASER_TO_IO_OCLK1X_90",
|
||||
"CMT_PMV_SE4BEG2",
|
||||
"CMT_PMV_LOGIC_OUTS20",
|
||||
"CMT_PMV_SW2A2",
|
||||
"CMT_PMV_NW4END1",
|
||||
"CMT_PMV_NW4A3",
|
||||
"CMT_PMV_LOGIC_OUTS11",
|
||||
"CMT_PMV_FAN5",
|
||||
"CMT_PMV_WL1END3",
|
||||
"CMT_PMV_WW4C3",
|
||||
"CMT_PMV_EE4A2",
|
||||
"CMT_PMV_WW2A2",
|
||||
"CMT_PMV_LOGIC_OUTS22",
|
||||
"CMT_PMV_IMUX7",
|
||||
"CMT_PMV_LH4",
|
||||
"CMT_PMV_ER1BEG3",
|
||||
"CMT_PMV_SE2A1",
|
||||
"CMT_PMV_WW4B3",
|
||||
"CMT_PMV_EE4C3",
|
||||
"L_TERM_INT_PHASER_TO_IO_ICLKDIV",
|
||||
"CMT_PMV_WW2END3",
|
||||
"CMT_PMV_FAN0",
|
||||
"CMT_PMV_NW4A1",
|
||||
"CMT_PMV_IMUX38",
|
||||
"CMT_PMV_IMUX20",
|
||||
"CMT_PMV_BYP3",
|
||||
"CMT_PMV_NW2A0",
|
||||
"CMT_PMV_EE4BEG0",
|
||||
"L_TERM_INT_PHASER_TO_IO_OCLKDIV",
|
||||
"CMT_PMV_SW4A2",
|
||||
"CMT_PMV_IMUX42",
|
||||
"CMT_PMV_NE2A1",
|
||||
"L_TERM_INT_PHASER_TO_IO_OCLK",
|
||||
"CMT_PMV_IMUX28",
|
||||
"CMT_PMV_WW2A0",
|
||||
"CMT_PMV_NE2A2",
|
||||
"CMT_PMV_SW2A1",
|
||||
"CMT_PMV_WW4END0",
|
||||
"CMT_PMV_IMUX39",
|
||||
"CMT_PMV_LH5",
|
||||
"CMT_PMV_SE4C2",
|
||||
"CMT_PMV_SW2A0",
|
||||
"CMT_PMV_IMUX45",
|
||||
"CMT_PMV_ER1BEG2",
|
||||
"CMT_PMV_WR1END1",
|
||||
"CMT_PMV_FAN1",
|
||||
"CMT_PMV_EL1BEG0",
|
||||
"CMT_PMV_SE4BEG1",
|
||||
"CMT_PMV_IMUX23",
|
||||
"CMT_PMV_IMUX13",
|
||||
"CMT_PMV_IMUX47",
|
||||
"CMT_PMV_WW4A2",
|
||||
"CMT_PMV_EE4B0",
|
||||
"CMT_PMV_SW4END0",
|
||||
"CMT_PMV_LOGIC_OUTS12",
|
||||
"CMT_PMV_EE2BEG3",
|
||||
"CMT_PMV_LOGIC_OUTS16",
|
||||
"CMT_PMV_MONITOR_N",
|
||||
"CMT_PMV_NE4BEG3",
|
||||
"CMT_PMV_WR1END3",
|
||||
"CMT_PMV_EE2A3",
|
||||
"CMT_PMV_LOGIC_OUTS17",
|
||||
"CMT_PMV_EL1BEG2",
|
||||
"CMT_PMV_WW2A3",
|
||||
"CMT_PMV_SW4A1",
|
||||
"CMT_PMV_EE4A0",
|
||||
"CMT_PMV_IMUX44",
|
||||
"CMT_PMV_WW4A3",
|
||||
"CMT_PMV_EE4C0",
|
||||
"CMT_PMV_NE4C0",
|
||||
"CMT_PMV_IMUX25",
|
||||
"CMT_PMV_NE4C2",
|
||||
"CMT_PMV_WW4C1",
|
||||
"CMT_PMV_IMUX18",
|
||||
"CMT_PMV_FAN2"
|
||||
],
|
||||
"tile_type": "CMT_PMV",
|
||||
"sites": []
|
||||
}
|
||||
|
|
@ -1,230 +1,230 @@
|
|||
{
|
||||
"tile_type": "CMT_PMV_L",
|
||||
"pips": {},
|
||||
"wires": [
|
||||
"CMT_PMV_IMUX37",
|
||||
"CMT_PMV_IMUX42",
|
||||
"CMT_PMV_WW4END1",
|
||||
"CMT_PMV_WW4A1",
|
||||
"CMT_PMV_FAN1",
|
||||
"CMT_PMV_IMUX38",
|
||||
"CMT_PMV_LOGIC_OUTS3",
|
||||
"CMT_PMV_SW4A1",
|
||||
"CMT_PMV_SE4C2",
|
||||
"CMT_PMV_FAN6",
|
||||
"CMT_PMV_WL1END2",
|
||||
"CMT_PMV_EE4C3",
|
||||
"CMT_PMV_SW2A0",
|
||||
"CMT_PMV_LOGIC_OUTS4",
|
||||
"CMT_PMV_MONITOR_N",
|
||||
"CMT_PMV_NW4END1",
|
||||
"CMT_PMV_NW2A0",
|
||||
"CMT_PMV_EE4C1",
|
||||
"CMT_PMV_LOGIC_OUTS11",
|
||||
"CMT_PMV_EE2A1",
|
||||
"CMT_PMV_IMUX46",
|
||||
"CMT_PMV_LOGIC_OUTS7",
|
||||
"CMT_PMV_WL1END0",
|
||||
"CMT_PMV_IMUX6",
|
||||
"CMT_PMV_NW4A3",
|
||||
"CMT_PMV_WW4B3",
|
||||
"CMT_PMV_SW2A2",
|
||||
"CMT_PMV_IMUX47",
|
||||
"CMT_PMV_SE2A2",
|
||||
"CMT_PMV_NE4C2",
|
||||
"CMT_PMV_NE4C1",
|
||||
"CMT_PMV_EE4B3",
|
||||
"CMT_PMV_WW2A1",
|
||||
"CMT_PMV_NE4BEG0",
|
||||
"CMT_PMV_SW2A3",
|
||||
"CMT_PMV_EE2BEG3",
|
||||
"CMT_PMV_IMUX15",
|
||||
"CMT_PMV_FAN4",
|
||||
"CMT_PMV_WW4C1",
|
||||
"CMT_PMV_EE2BEG0",
|
||||
"CMT_PMV_EE4C2",
|
||||
"CMT_PMV_LOGIC_OUTS8",
|
||||
"CMT_PMV_LOGIC_OUTS2",
|
||||
"CMT_PMV_NW4A0",
|
||||
"CMT_PMV_WW4B0",
|
||||
"CMT_PMV_WW4B2",
|
||||
"CMT_PMV_BYP4",
|
||||
"CMT_PMV_IMUX20",
|
||||
"CMT_PMV_IMUX7",
|
||||
"CMT_PMV_WW4C2",
|
||||
"CMT_PMV_NW4A1",
|
||||
"CMT_PMV_LOGIC_OUTS16",
|
||||
"CMT_PMV_WW4END2",
|
||||
"CMT_PMV_IMUX25",
|
||||
"CMT_PMV_SW4END3",
|
||||
"CMT_PMV_LOGIC_OUTS23",
|
||||
"CMT_PMV_WW4END0",
|
||||
"CMT_PMV_IMUX39",
|
||||
"CMT_PMV_IMUX9",
|
||||
"CMT_PMV_SE2A0",
|
||||
"CMT_PMV_LOGIC_OUTS22",
|
||||
"CMT_PMV_BYP6",
|
||||
"CMT_PMV_LH9",
|
||||
"CMT_PMV_LOGIC_OUTS10",
|
||||
"CMT_PMV_IMUX31",
|
||||
"CMT_PMV_EE4B1",
|
||||
"CMT_PMV_LOGIC_OUTS1",
|
||||
"CMT_PMV_SW4A2",
|
||||
"CMT_PMV_WL1END1",
|
||||
"CMT_PMV_IMUX28",
|
||||
"CMT_PMV_IMUX27",
|
||||
"CMT_PMV_LOGIC_OUTS5",
|
||||
"CMT_PMV_SE2A3",
|
||||
"CMT_PMV_WR1END0",
|
||||
"CMT_PMV_SW4END1",
|
||||
"CMT_PMV_SW4END2",
|
||||
"CMT_PMV_IMUX23",
|
||||
"CMT_PMV_NW4END0",
|
||||
"CMT_PMV_EE4A3",
|
||||
"CMT_PMV_EE4A1",
|
||||
"CMT_PMV_NW2A3",
|
||||
"CMT_PMV_IMUX30",
|
||||
"CMT_PMV_SE4BEG3",
|
||||
"CMT_PMV_CTRL0",
|
||||
"CMT_PMV_IMUX3",
|
||||
"CMT_PMV_NW2A2",
|
||||
"CMT_PMV_ER1BEG2",
|
||||
"CMT_PMV_IMUX26",
|
||||
"CMT_PMV_NE4BEG3",
|
||||
"CMT_PMV_EE4A0",
|
||||
"CMT_PMV_LH6",
|
||||
"CMT_PMV_NE2A0",
|
||||
"CMT_PMV_WW2END3",
|
||||
"CMT_PMV_FAN7",
|
||||
"CMT_PMV_LOGIC_OUTS13",
|
||||
"CMT_PMV_IMUX10",
|
||||
"CMT_PMV_SE4C1",
|
||||
"CMT_PMV_NE4C3",
|
||||
"CMT_PMV_LH1",
|
||||
"CMT_PMV_EE4A2",
|
||||
"CMT_PMV_FAN3",
|
||||
"CMT_PMV_WW2END2",
|
||||
"CMT_PMV_LOGIC_OUTS15",
|
||||
"CMT_PMV_SW4END0",
|
||||
"CMT_PMV_IMUX29",
|
||||
"CMT_PMV_NE2A2",
|
||||
"CMT_PMV_BYP5",
|
||||
"CMT_PMV_MONITOR_P",
|
||||
"CMT_PMV_SE2A1",
|
||||
"CMT_PMV_EE4B2",
|
||||
"CMT_PMV_LH8",
|
||||
"CMT_PMV_NW4END3",
|
||||
"CMT_PMV_NE2A1",
|
||||
"CMT_PMV_SE4BEG2",
|
||||
"CMT_PMV_IMUX8",
|
||||
"CMT_PMV_IMUX24",
|
||||
"CMT_PMV_IMUX18",
|
||||
"CMT_PMV_WW2END1",
|
||||
"CMT_PMV_WW2END0",
|
||||
"CMT_PMV_SE4C0",
|
||||
"L_TERM_INT_PHASER_TO_IO_OCLK",
|
||||
"CMT_PMV_WW2A2",
|
||||
"CMT_PMV_EL1BEG2",
|
||||
"CMT_PMV_SE4BEG0",
|
||||
"CMT_PMV_LOGIC_OUTS21",
|
||||
"CMT_PMV_IMUX22",
|
||||
"CMT_PMV_LOGIC_OUTS12",
|
||||
"CMT_PMV_WW4B1",
|
||||
"CMT_PMV_FAN0",
|
||||
"L_TERM_INT_PHASER_TO_IO_ICLKDIV",
|
||||
"CMT_PMV_WW2A3",
|
||||
"L_TERM_INT_PHASER_TO_IO_ICLK",
|
||||
"L_TERM_INT_PHASER_TO_IO_OCLK1X_90",
|
||||
"CMT_PMV_WW4C3",
|
||||
"CMT_PMV_CLK0",
|
||||
"CMT_PMV_WR1END2",
|
||||
"CMT_PMV_LH10",
|
||||
"CMT_PMV_EE2A0",
|
||||
"CMT_PMV_IMUX32",
|
||||
"CMT_PMV_EE4B0",
|
||||
"CMT_PMV_IMUX12",
|
||||
"CMT_PMV_IMUX19",
|
||||
"CMT_PMV_SW4A3",
|
||||
"CMT_PMV_LH3",
|
||||
"CMT_PMV_BYP2",
|
||||
"CMT_PMV_LH2",
|
||||
"CMT_PMV_LH11",
|
||||
"CMT_PMV_LOGIC_OUTS19",
|
||||
"CMT_PMV_IMUX41",
|
||||
"CMT_PMV_NE4BEG1",
|
||||
"CMT_PMV_LOGIC_OUTS9",
|
||||
"CMT_PMV_SW2A1",
|
||||
"CMT_PMV_EE4C0",
|
||||
"CMT_PMV_EE2BEG1",
|
||||
"CMT_PMV_WW4A2",
|
||||
"CMT_PMV_IMUX45",
|
||||
"CMT_PMV_BYP0",
|
||||
"CMT_PMV_WW4C0",
|
||||
"CMT_PMV_EE4BEG1",
|
||||
"CMT_PMV_NW4END0",
|
||||
"CMT_PMV_LOGIC_OUTS21",
|
||||
"CMT_PMV_IMUX30",
|
||||
"CMT_PMV_ER1BEG1",
|
||||
"CMT_PMV_NW2A1",
|
||||
"CMT_PMV_IMUX3",
|
||||
"CMT_PMV_CTRL0",
|
||||
"CMT_PMV_WW4END1",
|
||||
"CMT_PMV_EE4B3",
|
||||
"CMT_PMV_LH10",
|
||||
"CMT_PMV_BYP6",
|
||||
"CMT_PMV_LOGIC_OUTS5",
|
||||
"CMT_PMV_LOGIC_OUTS0",
|
||||
"CMT_PMV_EE4BEG3",
|
||||
"CMT_PMV_WW2END2",
|
||||
"CMT_PMV_BYP1",
|
||||
"CMT_PMV_BYP2",
|
||||
"CMT_PMV_IMUX35",
|
||||
"CMT_PMV_IMUX8",
|
||||
"CMT_PMV_LH11",
|
||||
"CMT_PMV_NE4BEG2",
|
||||
"CMT_PMV_WW4A1",
|
||||
"CMT_PMV_NW2A3",
|
||||
"CMT_PMV_CLK1",
|
||||
"CMT_PMV_WW4B1",
|
||||
"CMT_PMV_IMUX6",
|
||||
"CMT_PMV_NW4END2",
|
||||
"CMT_PMV_SE4BEG1",
|
||||
"CMT_PMV_EL1BEG0",
|
||||
"CMT_PMV_IMUX13",
|
||||
"CMT_PMV_NW4A2",
|
||||
"CMT_PMV_EE2BEG0",
|
||||
"CMT_PMV_IMUX15",
|
||||
"CMT_PMV_WR1END0",
|
||||
"CMT_PMV_SE2A2",
|
||||
"CMT_PMV_LOGIC_OUTS10",
|
||||
"CMT_PMV_SE4C0",
|
||||
"CMT_PMV_IMUX11",
|
||||
"CMT_PMV_FAN3",
|
||||
"CMT_PMV_IMUX40",
|
||||
"CMT_PMV_SE4C1",
|
||||
"CMT_PMV_EL1BEG1",
|
||||
"CMT_PMV_LH7",
|
||||
"CMT_PMV_NE2A3",
|
||||
"CMT_PMV_EL1BEG3",
|
||||
"CMT_PMV_EE2BEG2",
|
||||
"CMT_PMV_IMUX21",
|
||||
"CMT_PMV_CLK1",
|
||||
"CMT_PMV_WL1END3",
|
||||
"CMT_PMV_EE2A2",
|
||||
"CMT_PMV_IMUX34",
|
||||
"CMT_PMV_FAN2",
|
||||
"CMT_PMV_IMUX14",
|
||||
"CMT_PMV_LH12",
|
||||
"CMT_PMV_IMUX4",
|
||||
"CMT_PMV_LOGIC_OUTS0",
|
||||
"CMT_PMV_LOGIC_OUTS17",
|
||||
"CMT_PMV_LOGIC_OUTS6",
|
||||
"CMT_PMV_BYP1",
|
||||
"CMT_PMV_NE4BEG2",
|
||||
"CMT_PMV_SW4A0",
|
||||
"CMT_PMV_LOGIC_OUTS20",
|
||||
"CMT_PMV_LH4",
|
||||
"CMT_PMV_IMUX40",
|
||||
"CMT_PMV_IMUX17",
|
||||
"CMT_PMV_IMUX2",
|
||||
"CMT_PMV_WW4END3",
|
||||
"CMT_PMV_IMUX35",
|
||||
"CMT_PMV_IMUX43",
|
||||
"CMT_PMV_EE2A3",
|
||||
"CMT_PMV_EE4BEG3",
|
||||
"CMT_PMV_LOGIC_OUTS14",
|
||||
"CMT_PMV_WW2A0",
|
||||
"CMT_PMV_IMUX33",
|
||||
"CMT_PMV_WW4A0",
|
||||
"CMT_PMV_EE4BEG0",
|
||||
"CMT_PMV_SE4C3",
|
||||
"CMT_PMV_BYP3",
|
||||
"CMT_PMV_EE4BEG2",
|
||||
"CMT_PMV_BYP7",
|
||||
"CMT_PMV_IMUX1",
|
||||
"CMT_PMV_FAN5",
|
||||
"CMT_PMV_LH5",
|
||||
"CMT_PMV_NW2A1",
|
||||
"CMT_PMV_IMUX16",
|
||||
"CMT_PMV_NE4C0",
|
||||
"CMT_PMV_IMUX11",
|
||||
"CMT_PMV_ER1BEG3",
|
||||
"CMT_PMV_EE4C1",
|
||||
"CMT_PMV_LH3",
|
||||
"CMT_PMV_LOGIC_OUTS2",
|
||||
"CMT_PMV_LOGIC_OUTS15",
|
||||
"CMT_PMV_LOGIC_OUTS13",
|
||||
"CMT_PMV_LOGIC_OUTS18",
|
||||
"CMT_PMV_WW4A3",
|
||||
"CMT_PMV_IMUX36",
|
||||
"CMT_PMV_IMUX0",
|
||||
"CMT_PMV_ER1BEG0",
|
||||
"CMT_PMV_IMUX24",
|
||||
"CMT_PMV_LH6",
|
||||
"CMT_PMV_IMUX33",
|
||||
"CMT_PMV_WL1END2",
|
||||
"CMT_PMV_LOGIC_OUTS6",
|
||||
"CMT_PMV_IMUX5",
|
||||
"CMT_PMV_ER1BEG1",
|
||||
"CMT_PMV_WR1END3",
|
||||
"CMT_PMV_IMUX44",
|
||||
"L_TERM_INT_PHASER_TO_IO_OCLKDIV",
|
||||
"CMT_PMV_EE4B1",
|
||||
"CMT_PMV_LH8",
|
||||
"CMT_PMV_IMUX29",
|
||||
"CMT_PMV_EE4BEG1",
|
||||
"CMT_PMV_NE4BEG1",
|
||||
"CMT_PMV_IMUX27",
|
||||
"CMT_PMV_EE4A3",
|
||||
"CMT_PMV_FAN7",
|
||||
"CMT_PMV_SE4C3",
|
||||
"CMT_PMV_IMUX43",
|
||||
"CMT_PMV_SE4BEG0",
|
||||
"CMT_PMV_LH1",
|
||||
"CMT_PMV_EE2A0",
|
||||
"CMT_PMV_BYP0",
|
||||
"CMT_PMV_IMUX34",
|
||||
"CMT_PMV_SE2A3",
|
||||
"CMT_PMV_FAN4",
|
||||
"CMT_PMV_SE4BEG3",
|
||||
"CMT_PMV_IMUX0",
|
||||
"CMT_PMV_IMUX17",
|
||||
"CMT_PMV_IMUX36",
|
||||
"CMT_PMV_IMUX2",
|
||||
"CMT_PMV_IMUX22",
|
||||
"CMT_PMV_SW4END1",
|
||||
"CMT_PMV_WL1END0",
|
||||
"CMT_PMV_EL1BEG3",
|
||||
"CMT_PMV_ER1BEG0",
|
||||
"CMT_PMV_NW2A2",
|
||||
"CMT_PMV_SW4A0",
|
||||
"CMT_PMV_WW2A1",
|
||||
"CMT_PMV_IMUX1",
|
||||
"CMT_PMV_WL1END1",
|
||||
"CMT_PMV_LOGIC_OUTS7",
|
||||
"CMT_PMV_EE4B2",
|
||||
"CMT_PMV_BYP7",
|
||||
"CMT_PMV_FAN6",
|
||||
"CMT_PMV_SE2A0",
|
||||
"CMT_PMV_NE4C1",
|
||||
"CMT_PMV_IMUX26",
|
||||
"CMT_PMV_NW4A2",
|
||||
"CMT_PMV_SW4END3",
|
||||
"CMT_PMV_IMUX10",
|
||||
"CMT_PMV_IMUX32",
|
||||
"CMT_PMV_NE2A3",
|
||||
"CMT_PMV_LOGIC_OUTS3",
|
||||
"CMT_PMV_IMUX31",
|
||||
"CMT_PMV_NW4A0",
|
||||
"CMT_PMV_LOGIC_OUTS8",
|
||||
"CMT_PMV_IMUX19",
|
||||
"L_TERM_INT_PHASER_TO_IO_ICLK",
|
||||
"CMT_PMV_LOGIC_OUTS19",
|
||||
"CMT_PMV_WW4END3",
|
||||
"CMT_PMV_IMUX37",
|
||||
"CMT_PMV_LOGIC_OUTS4",
|
||||
"CMT_PMV_BYP4",
|
||||
"CMT_PMV_SW4A3",
|
||||
"CMT_PMV_NE2A0",
|
||||
"CMT_PMV_IMUX16",
|
||||
"CMT_PMV_SW2A3",
|
||||
"CMT_PMV_IMUX9",
|
||||
"CMT_PMV_WW4B2",
|
||||
"CMT_PMV_IMUX21",
|
||||
"CMT_PMV_EE4C2",
|
||||
"CMT_PMV_MONITOR_P",
|
||||
"CMT_PMV_WW4B0",
|
||||
"CMT_PMV_IMUX14",
|
||||
"CMT_PMV_NE4C3",
|
||||
"CMT_PMV_EE4BEG2",
|
||||
"CMT_PMV_NE4BEG0",
|
||||
"CMT_PMV_IMUX4",
|
||||
"CMT_PMV_EE2A1",
|
||||
"CMT_PMV_IMUX12",
|
||||
"CMT_PMV_WW2END0",
|
||||
"CMT_PMV_LOGIC_OUTS23",
|
||||
"CMT_PMV_EE4A1",
|
||||
"CMT_PMV_WR1END2",
|
||||
"CMT_PMV_EE2A2",
|
||||
"CMT_PMV_LOGIC_OUTS9",
|
||||
"CMT_PMV_LH9",
|
||||
"CMT_PMV_WW4C0",
|
||||
"CMT_PMV_NW4END3",
|
||||
"CMT_PMV_WW4A0",
|
||||
"CMT_PMV_EE2BEG2",
|
||||
"CMT_PMV_LH12",
|
||||
"CMT_PMV_WW4C2",
|
||||
"CMT_PMV_SW4END2",
|
||||
"CMT_PMV_LOGIC_OUTS14",
|
||||
"CMT_PMV_IMUX46",
|
||||
"CMT_PMV_WW2END1",
|
||||
"CMT_PMV_EE2BEG1",
|
||||
"CMT_PMV_LOGIC_OUTS1",
|
||||
"CMT_PMV_CTRL1",
|
||||
"CMT_PMV_WR1END1"
|
||||
"CMT_PMV_WW4END2",
|
||||
"CMT_PMV_LH2",
|
||||
"L_TERM_INT_PHASER_TO_IO_OCLK1X_90",
|
||||
"CMT_PMV_SE4BEG2",
|
||||
"CMT_PMV_LOGIC_OUTS20",
|
||||
"CMT_PMV_SW2A2",
|
||||
"CMT_PMV_NW4END1",
|
||||
"CMT_PMV_NW4A3",
|
||||
"CMT_PMV_LOGIC_OUTS11",
|
||||
"CMT_PMV_FAN5",
|
||||
"CMT_PMV_WL1END3",
|
||||
"CMT_PMV_WW4C3",
|
||||
"CMT_PMV_EE4A2",
|
||||
"CMT_PMV_WW2A2",
|
||||
"CMT_PMV_LOGIC_OUTS22",
|
||||
"CMT_PMV_IMUX7",
|
||||
"CMT_PMV_LH4",
|
||||
"CMT_PMV_ER1BEG3",
|
||||
"CMT_PMV_SE2A1",
|
||||
"CMT_PMV_WW4B3",
|
||||
"CMT_PMV_EE4C3",
|
||||
"L_TERM_INT_PHASER_TO_IO_ICLKDIV",
|
||||
"CMT_PMV_WW2END3",
|
||||
"CMT_PMV_FAN0",
|
||||
"CMT_PMV_NW4A1",
|
||||
"CMT_PMV_IMUX38",
|
||||
"CMT_PMV_IMUX20",
|
||||
"CMT_PMV_BYP3",
|
||||
"CMT_PMV_NW2A0",
|
||||
"CMT_PMV_EE4BEG0",
|
||||
"L_TERM_INT_PHASER_TO_IO_OCLKDIV",
|
||||
"CMT_PMV_SW4A2",
|
||||
"CMT_PMV_IMUX42",
|
||||
"CMT_PMV_NE2A1",
|
||||
"L_TERM_INT_PHASER_TO_IO_OCLK",
|
||||
"CMT_PMV_IMUX28",
|
||||
"CMT_PMV_WW2A0",
|
||||
"CMT_PMV_NE2A2",
|
||||
"CMT_PMV_SW2A1",
|
||||
"CMT_PMV_WW4END0",
|
||||
"CMT_PMV_IMUX39",
|
||||
"CMT_PMV_LH5",
|
||||
"CMT_PMV_SE4C2",
|
||||
"CMT_PMV_SW2A0",
|
||||
"CMT_PMV_IMUX45",
|
||||
"CMT_PMV_ER1BEG2",
|
||||
"CMT_PMV_WR1END1",
|
||||
"CMT_PMV_FAN1",
|
||||
"CMT_PMV_EL1BEG0",
|
||||
"CMT_PMV_SE4BEG1",
|
||||
"CMT_PMV_IMUX23",
|
||||
"CMT_PMV_IMUX13",
|
||||
"CMT_PMV_IMUX47",
|
||||
"CMT_PMV_WW4A2",
|
||||
"CMT_PMV_EE4B0",
|
||||
"CMT_PMV_SW4END0",
|
||||
"CMT_PMV_LOGIC_OUTS12",
|
||||
"CMT_PMV_EE2BEG3",
|
||||
"CMT_PMV_LOGIC_OUTS16",
|
||||
"CMT_PMV_MONITOR_N",
|
||||
"CMT_PMV_NE4BEG3",
|
||||
"CMT_PMV_WR1END3",
|
||||
"CMT_PMV_EE2A3",
|
||||
"CMT_PMV_LOGIC_OUTS17",
|
||||
"CMT_PMV_EL1BEG2",
|
||||
"CMT_PMV_WW2A3",
|
||||
"CMT_PMV_SW4A1",
|
||||
"CMT_PMV_EE4A0",
|
||||
"CMT_PMV_IMUX44",
|
||||
"CMT_PMV_WW4A3",
|
||||
"CMT_PMV_EE4C0",
|
||||
"CMT_PMV_NE4C0",
|
||||
"CMT_PMV_IMUX25",
|
||||
"CMT_PMV_NE4C2",
|
||||
"CMT_PMV_WW4C1",
|
||||
"CMT_PMV_IMUX18",
|
||||
"CMT_PMV_FAN2"
|
||||
],
|
||||
"tile_type": "CMT_PMV_L",
|
||||
"sites": []
|
||||
}
|
||||
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Reference in New Issue