Updating all based on "Merge pull request #1383 from andrewb1999/json-add-explicit-type".

See [Info File](Info.md) for details. Signed-off-by: Tim 'mithro' Ansell <me@mith.ro>
2020-07-02 14:40:10 -07:00 · 2020-07-02 14:40:10 -07:00 · e45604d941
parent 20adf09d39
commit e45604d941
38 changed files with 2797 additions and 2665 deletions
--- a/Info.md
+++ b/Info.md
@ -37,20 +37,20 @@ These files are released under the very permissive [CC0 1.0 Universal](COPYING).

 # Details

-Last updated on Fri May 29 22:38:36 UTC 2020 (2020-05-29T22:38:36+00:00).
+Last updated on Thu 02 Jul 2020 09:39:45 PM UTC (2020-07-02T21:39:45+00:00).

-Created using [Project X-Ray](https://github.com/SymbiFlow/prjxray) version [1f410829](https://github.com/SymbiFlow/prjxray/commit/1f410829371e774e0cfa0e01bd3c46d85dbb49b6).
+Created using [Project X-Ray](https://github.com/SymbiFlow/prjxray) version [b0432d14](https://github.com/SymbiFlow/prjxray/commit/b0432d14d5806f379bd56fe2e967a553bf11287f).

 Latest commit was;
 ```
-commit 1f410829371e774e0cfa0e01bd3c46d85dbb49b6
-Merge: a3615354 f0d4a713
-Author: Tim Ansell <me@mith.ro>
-Date:   Tue May 26 09:01:50 2020 -0700
+commit b0432d14d5806f379bd56fe2e967a553bf11287f
+Merge: 9749d6d5 30f35f97
+Author: litghost <537074+litghost@users.noreply.github.com>
+Date:   Wed Jul 1 15:59:30 2020 -0700

-    Merge pull request #1301 from antmicro/licensing
+    Merge pull request #1383 from andrewb1999/json-add-explicit-type
    
-    Updating copyright headers to match current best practices
+    Add dedicated port type to harness design.json
 ```


@ -59,7 +59,7 @@ Date:   Tue May 26 09:01:50 2020 -0700

 ### Settings

-Created using following [settings/artix7.sh (sha256: 56ee1f9747510a62c9ea078738b273f4dcbaeca49aa98334db6ef1a9ececa9a7)](https://github.com/SymbiFlow/prjxray/blob/1f410829371e774e0cfa0e01bd3c46d85dbb49b6/settings/artix7.sh)
+Created using following [settings/artix7.sh (sha256: 56ee1f9747510a62c9ea078738b273f4dcbaeca49aa98334db6ef1a9ececa9a7)](https://github.com/SymbiFlow/prjxray/blob/b0432d14d5806f379bd56fe2e967a553bf11287f/settings/artix7.sh)
 ```shell
 # Copyright (C) 2017-2020  The Project X-Ray Authors.
 #
@ -116,19 +116,19 @@ Results have checksums;
 * [`2b18b3806f0e58024469eac1fe11749d04c6b035d2c2eafa7d2f30bf57173fa9  ./artix7/harness/README.md`](./artix7/harness/README.md)
 * [`560f255b569fd4798989f45104d4a511b51380418d4ca6fc53201141b36b20aa  ./artix7/harness/arty-a7/pmod/design.bit`](./artix7/harness/arty-a7/pmod/design.bit)
 * [`1d8a121c3aa3bca7893429cfb08a8748206134271432daa52cdc9d3f5593bda0  ./artix7/harness/arty-a7/pmod/design.dcp`](./artix7/harness/arty-a7/pmod/design.dcp)
- * [`12b513bf78373030d43b0d226acb8ad3c7b447acae0255844583bf5001525ce6  ./artix7/harness/arty-a7/pmod/design.json`](./artix7/harness/arty-a7/pmod/design.json)
+ * [`2e1218b8f453bd62e1b69859cd436e9a6d3c2f04869bd2e55ebd6af88e3a6e77  ./artix7/harness/arty-a7/pmod/design.json`](./artix7/harness/arty-a7/pmod/design.json)
 * [`fb90ad5fe10750f33d5802e1409ebc2406f7b0adab4bf6ef12b53c0e100b43ea  ./artix7/harness/arty-a7/pmod/design.txt`](./artix7/harness/arty-a7/pmod/design.txt)
 * [`931c1598b75005a8a8e5b2225cc7454c2c7be451cb907bc4c047cb04db99772d  ./artix7/harness/arty-a7/swbut/design.bit`](./artix7/harness/arty-a7/swbut/design.bit)
 * [`5d06132c788097344a9bca7040a08dd0e1632e177ed8def1d7445132020cc768  ./artix7/harness/arty-a7/swbut/design.dcp`](./artix7/harness/arty-a7/swbut/design.dcp)
- * [`af2bf70bb44cc93c53b344b7bdd9ded859142a1960130434d1418554204c6db2  ./artix7/harness/arty-a7/swbut/design.json`](./artix7/harness/arty-a7/swbut/design.json)
+ * [`ce44232b3e0b287a7a619a4f2fcb7122470113ef39895b13d630669c23ed94e5  ./artix7/harness/arty-a7/swbut/design.json`](./artix7/harness/arty-a7/swbut/design.json)
 * [`884af447661ff1cb653cd8280602c2348435366b35bf2627e2221af34899d191  ./artix7/harness/arty-a7/swbut/design.txt`](./artix7/harness/arty-a7/swbut/design.txt)
 * [`128e73ee026cf2238a35c7e993b845e3551919c90fc77b277635bc5098d59741  ./artix7/harness/arty-a7/uart/design.bit`](./artix7/harness/arty-a7/uart/design.bit)
 * [`955daed70c5728c13865eddc9bd7001d93183a50c560559a7b6628aa85b1fbbe  ./artix7/harness/arty-a7/uart/design.dcp`](./artix7/harness/arty-a7/uart/design.dcp)
- * [`063a775ffd3c7fdd198c1f8c9298cfd33ab550af8eccd1f1c7ecf92054dc87ba  ./artix7/harness/arty-a7/uart/design.json`](./artix7/harness/arty-a7/uart/design.json)
+ * [`6034ab6f509608b5357863697002138aff70b431d3c3055adc7ef8527ca1e973  ./artix7/harness/arty-a7/uart/design.json`](./artix7/harness/arty-a7/uart/design.json)
 * [`0583aa7502ee7a0303510c524f5500d8e1b9598aa26016d3d0e4e9623bf8ab8d  ./artix7/harness/arty-a7/uart/design.txt`](./artix7/harness/arty-a7/uart/design.txt)
 * [`d3109010f8fced3be08e720741a157d08b7042359e84d04bbe677f50cbf10a04  ./artix7/harness/basys3/swbut/design.bit`](./artix7/harness/basys3/swbut/design.bit)
 * [`abedfa7f2ee5a4dbc51b582ebae62dd20489f745a4a239e49b18ba3e02be019f  ./artix7/harness/basys3/swbut/design.dcp`](./artix7/harness/basys3/swbut/design.dcp)
- * [`96d20a9d5715460c6ac4bd75b761acb5b797ae3f5d573f9f1ee32420844aa9ea  ./artix7/harness/basys3/swbut/design.json`](./artix7/harness/basys3/swbut/design.json)
+ * [`de3d1db452b8f23caad69b7dda8f1562eea189990af09ac3f86e53b465d92942  ./artix7/harness/basys3/swbut/design.json`](./artix7/harness/basys3/swbut/design.json)
 * [`9df8eac3c11e57d81b4bf4a927ade787f881f0ef46c8ab610ca529f35e887689  ./artix7/harness/basys3/swbut/design.txt`](./artix7/harness/basys3/swbut/design.txt)
 * [`3ad62b024991225f1565e84159f2eb59d08e9fc6cf2577ea1698952b5dc0e4ec  ./artix7/harness/basys3/swbut_50/design.bit`](./artix7/harness/basys3/swbut_50/design.bit)
 * [`773fe43b4974ab353bde87e544abb6b541cdcb280de40df76afa96f7fa23db46  ./artix7/harness/basys3/swbut_50/design.dcp`](./artix7/harness/basys3/swbut_50/design.dcp)
@ -166,13 +166,13 @@ Results have checksums;
 * [`76d1e0bd4b7ad492cf3fe8698b2b5f46f7dcc5fe446984e5dccae373c63edafd  ./artix7/mask_hclk_r.db`](./artix7/mask_hclk_r.db)
 * [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855  ./artix7/mask_hclk_r.origin_info.db`](./artix7/mask_hclk_r.origin_info.db)
 * [`a0777dc0808e70052a6f6b2e1056f6e9dd225032c01195919d927be7ba1b97d6  ./artix7/mask_liob33.db`](./artix7/mask_liob33.db)
- * [`f665e297181be0a1ed08f33873068b4fe4cefcb85118e30b85548c117d5fa63c  ./artix7/mask_lioi3.db`](./artix7/mask_lioi3.db)
- * [`f665e297181be0a1ed08f33873068b4fe4cefcb85118e30b85548c117d5fa63c  ./artix7/mask_lioi3_tbytesrc.db`](./artix7/mask_lioi3_tbytesrc.db)
- * [`f665e297181be0a1ed08f33873068b4fe4cefcb85118e30b85548c117d5fa63c  ./artix7/mask_lioi3_tbyteterm.db`](./artix7/mask_lioi3_tbyteterm.db)
+ * [`5ce5815a27e861034d00cf44b4480757b648f946c0a90ca51cd1ccd7166b023f  ./artix7/mask_lioi3.db`](./artix7/mask_lioi3.db)
+ * [`5ce5815a27e861034d00cf44b4480757b648f946c0a90ca51cd1ccd7166b023f  ./artix7/mask_lioi3_tbytesrc.db`](./artix7/mask_lioi3_tbytesrc.db)
+ * [`5ce5815a27e861034d00cf44b4480757b648f946c0a90ca51cd1ccd7166b023f  ./artix7/mask_lioi3_tbyteterm.db`](./artix7/mask_lioi3_tbyteterm.db)
 * [`a0777dc0808e70052a6f6b2e1056f6e9dd225032c01195919d927be7ba1b97d6  ./artix7/mask_riob33.db`](./artix7/mask_riob33.db)
- * [`f665e297181be0a1ed08f33873068b4fe4cefcb85118e30b85548c117d5fa63c  ./artix7/mask_rioi3.db`](./artix7/mask_rioi3.db)
- * [`f665e297181be0a1ed08f33873068b4fe4cefcb85118e30b85548c117d5fa63c  ./artix7/mask_rioi3_tbytesrc.db`](./artix7/mask_rioi3_tbytesrc.db)
- * [`f665e297181be0a1ed08f33873068b4fe4cefcb85118e30b85548c117d5fa63c  ./artix7/mask_rioi3_tbyteterm.db`](./artix7/mask_rioi3_tbyteterm.db)
+ * [`5ce5815a27e861034d00cf44b4480757b648f946c0a90ca51cd1ccd7166b023f  ./artix7/mask_rioi3.db`](./artix7/mask_rioi3.db)
+ * [`5ce5815a27e861034d00cf44b4480757b648f946c0a90ca51cd1ccd7166b023f  ./artix7/mask_rioi3_tbytesrc.db`](./artix7/mask_rioi3_tbytesrc.db)
+ * [`5ce5815a27e861034d00cf44b4480757b648f946c0a90ca51cd1ccd7166b023f  ./artix7/mask_rioi3_tbyteterm.db`](./artix7/mask_rioi3_tbyteterm.db)
 * [`d94e4d13df16da498224f0e94deaa310fbf471b6f9ec0ec8b2308fe62fa2eeaf  ./artix7/ppips_bram_int_interface_l.db`](./artix7/ppips_bram_int_interface_l.db)
 * [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855  ./artix7/ppips_bram_int_interface_l.origin_info.db`](./artix7/ppips_bram_int_interface_l.origin_info.db)
 * [`b48d766ac6f9dd0e21280d3a04dd448ea39016143309c0c7867fc00d730a59ae  ./artix7/ppips_bram_int_interface_r.db`](./artix7/ppips_bram_int_interface_r.db)
@ -275,9 +275,9 @@ Results have checksums;
 * [`51288ec0be63172fcb2a12a92853150c62a21e894c2d42a2586046c462bf57a9  ./artix7/segbits_hclk_r.db`](./artix7/segbits_hclk_r.db)
 * [`61d05145f3613042e8f0c1d97d63f6c185cfb66df609b621b44422ebb27c77a0  ./artix7/segbits_hclk_r.origin_info.db`](./artix7/segbits_hclk_r.origin_info.db)
 * [`0ea44e8dfaf97ed200f30b2afe117e94e1a68bdb26af2e09e69e855414779520  ./artix7/segbits_int_l.db`](./artix7/segbits_int_l.db)
- * [`2121c60583cfd3e540e8e221062347bf3c8832ab2f48cd6aaa093a6b98faeb5f  ./artix7/segbits_int_l.origin_info.db`](./artix7/segbits_int_l.origin_info.db)
- * [`1541c7832dd161c5b3b5745d08fe0ee6f92bfbd372b76c12f54afc032c888556  ./artix7/segbits_int_r.db`](./artix7/segbits_int_r.db)
- * [`dfc24f85f911506d462d789aa76a80f0441544ca0b83f2473859b5697521dfa3  ./artix7/segbits_int_r.origin_info.db`](./artix7/segbits_int_r.origin_info.db)
+ * [`4c74f917fa6c914e8ea8e44155fc8b1f52c51274d4ec4cb75d3053bad0b798ab  ./artix7/segbits_int_l.origin_info.db`](./artix7/segbits_int_l.origin_info.db)
+ * [`9c7b94275c440e0bb0634ae2c347e92b605a77e29bb28c04f8bba126ba808f60  ./artix7/segbits_int_r.db`](./artix7/segbits_int_r.db)
+ * [`5ccdf716246053de58c1d0f7c350ed09e117bc44695aa69bdd2d1357d09aff2a  ./artix7/segbits_int_r.origin_info.db`](./artix7/segbits_int_r.origin_info.db)
 * [`392e91def4df6eebb3ce5ed15570c01f6090be793a79054e1880549082eb6f23  ./artix7/segbits_liob33.db`](./artix7/segbits_liob33.db)
 * [`0fca9c6530589b14c77b738e68c63ed4246713e44e1e699e153b69907e77e09e  ./artix7/segbits_liob33.origin_info.db`](./artix7/segbits_liob33.origin_info.db)
 * [`c9dfa75f8b565b3c47813cdf7f1df2aa7c59402f41396e939dd97ec68f7638d8  ./artix7/segbits_lioi3.db`](./artix7/segbits_lioi3.db)
@ -489,8 +489,8 @@ Results have checksums;
 * [`bda848e132cf93158addf5db6e449dd5d79050155bd2ba52ccad7bd3c1607ec4  ./artix7/timings/CMT_TOP_R_LOWER_T.sdf`](./artix7/timings/CMT_TOP_R_LOWER_T.sdf)
 * [`e56222b18e7fabf7473656f7446958e93373a3bf956ca75968d26f9c652fa14e  ./artix7/timings/CMT_TOP_R_UPPER_B.sdf`](./artix7/timings/CMT_TOP_R_UPPER_B.sdf)
 * [`24408756edd72f9c82dc2badb3e94e372916c00c407e86a88db1274f8951d721  ./artix7/timings/CMT_TOP_R_UPPER_T.sdf`](./artix7/timings/CMT_TOP_R_UPPER_T.sdf)
- * [`bff896002fa72a5edd01102cc54fbf658e8c6df5b5d1d5c82da379809b443fc6  ./artix7/timings/DSP_L.sdf`](./artix7/timings/DSP_L.sdf)
- * [`bff896002fa72a5edd01102cc54fbf658e8c6df5b5d1d5c82da379809b443fc6  ./artix7/timings/DSP_R.sdf`](./artix7/timings/DSP_R.sdf)
+ * [`a1945d3cc9f7a422691d7cad098dc61cf6804bdbb8df8c572576d651e0f44c44  ./artix7/timings/DSP_L.sdf`](./artix7/timings/DSP_L.sdf)
+ * [`a1945d3cc9f7a422691d7cad098dc61cf6804bdbb8df8c572576d651e0f44c44  ./artix7/timings/DSP_R.sdf`](./artix7/timings/DSP_R.sdf)
 * [`fd93513fb5389752c1f1716bf15c2d3d118666e9f968533bb50d845504deb5ff  ./artix7/timings/GTP_CHANNEL_0.sdf`](./artix7/timings/GTP_CHANNEL_0.sdf)
 * [`fd93513fb5389752c1f1716bf15c2d3d118666e9f968533bb50d845504deb5ff  ./artix7/timings/GTP_CHANNEL_1.sdf`](./artix7/timings/GTP_CHANNEL_1.sdf)
 * [`fd93513fb5389752c1f1716bf15c2d3d118666e9f968533bb50d845504deb5ff  ./artix7/timings/GTP_CHANNEL_2.sdf`](./artix7/timings/GTP_CHANNEL_2.sdf)
@ -515,8 +515,8 @@ Results have checksums;
 * [`3bb5a39c36bcd83a540200072baa4c36057960fa1e35f5fcba875f2a755c34a1  ./artix7/timings/RIOI3_TBYTETERM.sdf`](./artix7/timings/RIOI3_TBYTETERM.sdf)
 * [`feb5cf787894379d158c5218ba44af20458c8008a1e75e30df00adde8aa97108  ./artix7/timings/carry4_slicel.sdf`](./artix7/timings/carry4_slicel.sdf)
 * [`626d9e188a1c4874f7ac657e82c64df8d52f819624e8ee4f9ed9e557d85ad3f2  ./artix7/timings/carry4_slicem.sdf`](./artix7/timings/carry4_slicem.sdf)
- * [`fd31d66077f869d01f13d9fabbd0dcd38b4aab0322179ecf9ac190a3b70c5456  ./artix7/timings/slicel.sdf`](./artix7/timings/slicel.sdf)
- * [`3d2da5714d8c81165fa51403fb719b3ddd9e7ea7ab79280ae4e157d11a29172e  ./artix7/timings/slicem.sdf`](./artix7/timings/slicem.sdf)
+ * [`ee750af8a355de7fdbcee19e3c216068912f5502b9ad342090a35ba9cce90038  ./artix7/timings/slicel.sdf`](./artix7/timings/slicel.sdf)
+ * [`37f7377698f69c400e009e7134fd5752fb93724ffa74dde46d076fb23ef914bb  ./artix7/timings/slicem.sdf`](./artix7/timings/slicem.sdf)
 * [`3f202fefbd0f36761f08eb58737a42754c65c965968174421df0374198e31daa  ./artix7/xc7a100tcsg324-1/package_pins.csv`](./artix7/xc7a100tcsg324-1/package_pins.csv)
 * [`277906907e43846ac8a52115983cd0ece673b2310d8d10c9b2253d6537bf1a02  ./artix7/xc7a100tcsg324-1/part.json`](./artix7/xc7a100tcsg324-1/part.json)
 * [`4e1f153303270ed3727ca40af3179020f74271ff63c4d771556020b1d3037b92  ./artix7/xc7a100tcsg324-1/part.yaml`](./artix7/xc7a100tcsg324-1/part.yaml)
@ -563,7 +563,7 @@ Results have checksums;

 ### Settings

-Created using following [settings/kintex7.sh (sha256: 8c4c506cbdc6a25696436bbe6359e3617c82a11931ad6e406a1c433b263527c4)](https://github.com/SymbiFlow/prjxray/blob/1f410829371e774e0cfa0e01bd3c46d85dbb49b6/settings/kintex7.sh)
+Created using following [settings/kintex7.sh (sha256: 8c4c506cbdc6a25696436bbe6359e3617c82a11931ad6e406a1c433b263527c4)](https://github.com/SymbiFlow/prjxray/blob/b0432d14d5806f379bd56fe2e967a553bf11287f/settings/kintex7.sh)
 ```shell
 # Copyright (C) 2017-2020  The Project X-Ray Authors.
 #
@ -642,13 +642,13 @@ Results have checksums;
 * [`76d1e0bd4b7ad492cf3fe8698b2b5f46f7dcc5fe446984e5dccae373c63edafd  ./kintex7/mask_hclk_r.db`](./kintex7/mask_hclk_r.db)
 * [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855  ./kintex7/mask_hclk_r.origin_info.db`](./kintex7/mask_hclk_r.origin_info.db)
 * [`a0777dc0808e70052a6f6b2e1056f6e9dd225032c01195919d927be7ba1b97d6  ./kintex7/mask_liob33.db`](./kintex7/mask_liob33.db)
- * [`e9c5e8644b7f426944df2adaecb6e4813097034cfe78ab469d9b675e169b60d4  ./kintex7/mask_lioi3.db`](./kintex7/mask_lioi3.db)
- * [`e9c5e8644b7f426944df2adaecb6e4813097034cfe78ab469d9b675e169b60d4  ./kintex7/mask_lioi3_tbytesrc.db`](./kintex7/mask_lioi3_tbytesrc.db)
- * [`e9c5e8644b7f426944df2adaecb6e4813097034cfe78ab469d9b675e169b60d4  ./kintex7/mask_lioi3_tbyteterm.db`](./kintex7/mask_lioi3_tbyteterm.db)
+ * [`3570fd1c1fde57ee0f64aa815176edfaf65043920bba3cf2484e8f6b14c13064  ./kintex7/mask_lioi3.db`](./kintex7/mask_lioi3.db)
+ * [`3570fd1c1fde57ee0f64aa815176edfaf65043920bba3cf2484e8f6b14c13064  ./kintex7/mask_lioi3_tbytesrc.db`](./kintex7/mask_lioi3_tbytesrc.db)
+ * [`3570fd1c1fde57ee0f64aa815176edfaf65043920bba3cf2484e8f6b14c13064  ./kintex7/mask_lioi3_tbyteterm.db`](./kintex7/mask_lioi3_tbyteterm.db)
 * [`a0777dc0808e70052a6f6b2e1056f6e9dd225032c01195919d927be7ba1b97d6  ./kintex7/mask_riob33.db`](./kintex7/mask_riob33.db)
- * [`e9c5e8644b7f426944df2adaecb6e4813097034cfe78ab469d9b675e169b60d4  ./kintex7/mask_rioi3.db`](./kintex7/mask_rioi3.db)
- * [`e9c5e8644b7f426944df2adaecb6e4813097034cfe78ab469d9b675e169b60d4  ./kintex7/mask_rioi3_tbytesrc.db`](./kintex7/mask_rioi3_tbytesrc.db)
- * [`e9c5e8644b7f426944df2adaecb6e4813097034cfe78ab469d9b675e169b60d4  ./kintex7/mask_rioi3_tbyteterm.db`](./kintex7/mask_rioi3_tbyteterm.db)
+ * [`3570fd1c1fde57ee0f64aa815176edfaf65043920bba3cf2484e8f6b14c13064  ./kintex7/mask_rioi3.db`](./kintex7/mask_rioi3.db)
+ * [`3570fd1c1fde57ee0f64aa815176edfaf65043920bba3cf2484e8f6b14c13064  ./kintex7/mask_rioi3_tbytesrc.db`](./kintex7/mask_rioi3_tbytesrc.db)
+ * [`3570fd1c1fde57ee0f64aa815176edfaf65043920bba3cf2484e8f6b14c13064  ./kintex7/mask_rioi3_tbyteterm.db`](./kintex7/mask_rioi3_tbyteterm.db)
 * [`d94e4d13df16da498224f0e94deaa310fbf471b6f9ec0ec8b2308fe62fa2eeaf  ./kintex7/ppips_bram_int_interface_l.db`](./kintex7/ppips_bram_int_interface_l.db)
 * [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855  ./kintex7/ppips_bram_int_interface_l.origin_info.db`](./kintex7/ppips_bram_int_interface_l.origin_info.db)
 * [`b48d766ac6f9dd0e21280d3a04dd448ea39016143309c0c7867fc00d730a59ae  ./kintex7/ppips_bram_int_interface_r.db`](./kintex7/ppips_bram_int_interface_r.db)
@ -747,9 +747,9 @@ Results have checksums;
 * [`51288ec0be63172fcb2a12a92853150c62a21e894c2d42a2586046c462bf57a9  ./kintex7/segbits_hclk_r.db`](./kintex7/segbits_hclk_r.db)
 * [`61d05145f3613042e8f0c1d97d63f6c185cfb66df609b621b44422ebb27c77a0  ./kintex7/segbits_hclk_r.origin_info.db`](./kintex7/segbits_hclk_r.origin_info.db)
 * [`0ea44e8dfaf97ed200f30b2afe117e94e1a68bdb26af2e09e69e855414779520  ./kintex7/segbits_int_l.db`](./kintex7/segbits_int_l.db)
- * [`f1cf867719f47f3a0f3e001e9f94884d670b85b44f2eec8395054da046f95e38  ./kintex7/segbits_int_l.origin_info.db`](./kintex7/segbits_int_l.origin_info.db)
+ * [`185771cfd6d029ded688a2df21d1b304acecaa4dddab3f2e5325fe754455f568  ./kintex7/segbits_int_l.origin_info.db`](./kintex7/segbits_int_l.origin_info.db)
 * [`1541c7832dd161c5b3b5745d08fe0ee6f92bfbd372b76c12f54afc032c888556  ./kintex7/segbits_int_r.db`](./kintex7/segbits_int_r.db)
- * [`a7d2db6a3ebf7252638dc77dc9c558ff8d792ceeb50f3cd585a88d9231c9651f  ./kintex7/segbits_int_r.origin_info.db`](./kintex7/segbits_int_r.origin_info.db)
+ * [`5c07d9ae1e280ed7398df52234004717e61ce017b2f92f43242bc845b955c6d6  ./kintex7/segbits_int_r.origin_info.db`](./kintex7/segbits_int_r.origin_info.db)
 * [`392e91def4df6eebb3ce5ed15570c01f6090be793a79054e1880549082eb6f23  ./kintex7/segbits_liob33.db`](./kintex7/segbits_liob33.db)
 * [`0fca9c6530589b14c77b738e68c63ed4246713e44e1e699e153b69907e77e09e  ./kintex7/segbits_liob33.origin_info.db`](./kintex7/segbits_liob33.origin_info.db)
 * [`c9dfa75f8b565b3c47813cdf7f1df2aa7c59402f41396e939dd97ec68f7638d8  ./kintex7/segbits_lioi3.db`](./kintex7/segbits_lioi3.db)
@ -942,7 +942,7 @@ Results have checksums;

 ### Settings

-Created using following [settings/zynq7.sh (sha256: 790d0886285b195daff0950f82ddb42635257c7c6400dcc5c7fb5b13f66ee6ba)](https://github.com/SymbiFlow/prjxray/blob/1f410829371e774e0cfa0e01bd3c46d85dbb49b6/settings/zynq7.sh)
+Created using following [settings/zynq7.sh (sha256: 790d0886285b195daff0950f82ddb42635257c7c6400dcc5c7fb5b13f66ee6ba)](https://github.com/SymbiFlow/prjxray/blob/b0432d14d5806f379bd56fe2e967a553bf11287f/settings/zynq7.sh)
 ```shell
 # Copyright (C) 2017-2020  The Project X-Ray Authors.
 #
@ -1024,13 +1024,13 @@ Results have checksums;
 * [`76d1e0bd4b7ad492cf3fe8698b2b5f46f7dcc5fe446984e5dccae373c63edafd  ./zynq7/mask_hclk_r.db`](./zynq7/mask_hclk_r.db)
 * [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855  ./zynq7/mask_hclk_r.origin_info.db`](./zynq7/mask_hclk_r.origin_info.db)
 * [`a0777dc0808e70052a6f6b2e1056f6e9dd225032c01195919d927be7ba1b97d6  ./zynq7/mask_liob33.db`](./zynq7/mask_liob33.db)
- * [`04905dcedfe5b075d28c7ca2af92f4c3b9677675fc27d64813c43b8569f493ae  ./zynq7/mask_lioi3.db`](./zynq7/mask_lioi3.db)
- * [`04905dcedfe5b075d28c7ca2af92f4c3b9677675fc27d64813c43b8569f493ae  ./zynq7/mask_lioi3_tbytesrc.db`](./zynq7/mask_lioi3_tbytesrc.db)
- * [`04905dcedfe5b075d28c7ca2af92f4c3b9677675fc27d64813c43b8569f493ae  ./zynq7/mask_lioi3_tbyteterm.db`](./zynq7/mask_lioi3_tbyteterm.db)
+ * [`4b2e654db21ea7a65cd107929aee1d5944b71fdc83bc5f4fc62037f38961b763  ./zynq7/mask_lioi3.db`](./zynq7/mask_lioi3.db)
+ * [`4b2e654db21ea7a65cd107929aee1d5944b71fdc83bc5f4fc62037f38961b763  ./zynq7/mask_lioi3_tbytesrc.db`](./zynq7/mask_lioi3_tbytesrc.db)
+ * [`4b2e654db21ea7a65cd107929aee1d5944b71fdc83bc5f4fc62037f38961b763  ./zynq7/mask_lioi3_tbyteterm.db`](./zynq7/mask_lioi3_tbyteterm.db)
 * [`a0777dc0808e70052a6f6b2e1056f6e9dd225032c01195919d927be7ba1b97d6  ./zynq7/mask_riob33.db`](./zynq7/mask_riob33.db)
- * [`04905dcedfe5b075d28c7ca2af92f4c3b9677675fc27d64813c43b8569f493ae  ./zynq7/mask_rioi3.db`](./zynq7/mask_rioi3.db)
- * [`04905dcedfe5b075d28c7ca2af92f4c3b9677675fc27d64813c43b8569f493ae  ./zynq7/mask_rioi3_tbytesrc.db`](./zynq7/mask_rioi3_tbytesrc.db)
- * [`04905dcedfe5b075d28c7ca2af92f4c3b9677675fc27d64813c43b8569f493ae  ./zynq7/mask_rioi3_tbyteterm.db`](./zynq7/mask_rioi3_tbyteterm.db)
+ * [`4b2e654db21ea7a65cd107929aee1d5944b71fdc83bc5f4fc62037f38961b763  ./zynq7/mask_rioi3.db`](./zynq7/mask_rioi3.db)
+ * [`4b2e654db21ea7a65cd107929aee1d5944b71fdc83bc5f4fc62037f38961b763  ./zynq7/mask_rioi3_tbytesrc.db`](./zynq7/mask_rioi3_tbytesrc.db)
+ * [`4b2e654db21ea7a65cd107929aee1d5944b71fdc83bc5f4fc62037f38961b763  ./zynq7/mask_rioi3_tbyteterm.db`](./zynq7/mask_rioi3_tbyteterm.db)
 * [`d94e4d13df16da498224f0e94deaa310fbf471b6f9ec0ec8b2308fe62fa2eeaf  ./zynq7/ppips_bram_int_interface_l.db`](./zynq7/ppips_bram_int_interface_l.db)
 * [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855  ./zynq7/ppips_bram_int_interface_l.origin_info.db`](./zynq7/ppips_bram_int_interface_l.origin_info.db)
 * [`b48d766ac6f9dd0e21280d3a04dd448ea39016143309c0c7867fc00d730a59ae  ./zynq7/ppips_bram_int_interface_r.db`](./zynq7/ppips_bram_int_interface_r.db)
@ -1140,9 +1140,9 @@ Results have checksums;
 * [`51288ec0be63172fcb2a12a92853150c62a21e894c2d42a2586046c462bf57a9  ./zynq7/segbits_hclk_r.db`](./zynq7/segbits_hclk_r.db)
 * [`61d05145f3613042e8f0c1d97d63f6c185cfb66df609b621b44422ebb27c77a0  ./zynq7/segbits_hclk_r.origin_info.db`](./zynq7/segbits_hclk_r.origin_info.db)
 * [`0ea44e8dfaf97ed200f30b2afe117e94e1a68bdb26af2e09e69e855414779520  ./zynq7/segbits_int_l.db`](./zynq7/segbits_int_l.db)
- * [`c259e0cb3929fbf24bf0cef837f01e29d8699d414d980cf4c52e01509910bed9  ./zynq7/segbits_int_l.origin_info.db`](./zynq7/segbits_int_l.origin_info.db)
+ * [`57c86786f96c79410d6b4587c60b26dab0f404d9a41a0665ff2d4091f7a96fb4  ./zynq7/segbits_int_l.origin_info.db`](./zynq7/segbits_int_l.origin_info.db)
 * [`1541c7832dd161c5b3b5745d08fe0ee6f92bfbd372b76c12f54afc032c888556  ./zynq7/segbits_int_r.db`](./zynq7/segbits_int_r.db)
- * [`0d43700acd573ea0556a19f4e418b10a62398a828476233e83c95aa733be3fe0  ./zynq7/segbits_int_r.origin_info.db`](./zynq7/segbits_int_r.origin_info.db)
+ * [`66008bbd9dac18783ce0c3d698f37771ced2a5e291ccc55a1a4f55bb23e80e1e  ./zynq7/segbits_int_r.origin_info.db`](./zynq7/segbits_int_r.origin_info.db)
 * [`392e91def4df6eebb3ce5ed15570c01f6090be793a79054e1880549082eb6f23  ./zynq7/segbits_liob33.db`](./zynq7/segbits_liob33.db)
 * [`0fca9c6530589b14c77b738e68c63ed4246713e44e1e699e153b69907e77e09e  ./zynq7/segbits_liob33.origin_info.db`](./zynq7/segbits_liob33.origin_info.db)
 * [`c9dfa75f8b565b3c47813cdf7f1df2aa7c59402f41396e939dd97ec68f7638d8  ./zynq7/segbits_lioi3.db`](./zynq7/segbits_lioi3.db)
@ -1330,8 +1330,8 @@ Results have checksums;
 * [`bda848e132cf93158addf5db6e449dd5d79050155bd2ba52ccad7bd3c1607ec4  ./zynq7/timings/CMT_TOP_R_LOWER_T.sdf`](./zynq7/timings/CMT_TOP_R_LOWER_T.sdf)
 * [`e56222b18e7fabf7473656f7446958e93373a3bf956ca75968d26f9c652fa14e  ./zynq7/timings/CMT_TOP_R_UPPER_B.sdf`](./zynq7/timings/CMT_TOP_R_UPPER_B.sdf)
 * [`24408756edd72f9c82dc2badb3e94e372916c00c407e86a88db1274f8951d721  ./zynq7/timings/CMT_TOP_R_UPPER_T.sdf`](./zynq7/timings/CMT_TOP_R_UPPER_T.sdf)
- * [`3f9923d175379d32f859a8d3e07992c0174cabe3b260c14b69394009fa1d0569  ./zynq7/timings/DSP_L.sdf`](./zynq7/timings/DSP_L.sdf)
- * [`3f9923d175379d32f859a8d3e07992c0174cabe3b260c14b69394009fa1d0569  ./zynq7/timings/DSP_R.sdf`](./zynq7/timings/DSP_R.sdf)
+ * [`f9dc790354ec061813a023ae9e01a80d6db8f0800d7550e86966aea5be26f903  ./zynq7/timings/DSP_L.sdf`](./zynq7/timings/DSP_L.sdf)
+ * [`f9dc790354ec061813a023ae9e01a80d6db8f0800d7550e86966aea5be26f903  ./zynq7/timings/DSP_R.sdf`](./zynq7/timings/DSP_R.sdf)
 * [`5afccb72fdc7e9a452988e5db5dd7517ab38792ba21af020f9f1885f686ae5a3  ./zynq7/timings/HCLK_CMT.sdf`](./zynq7/timings/HCLK_CMT.sdf)
 * [`5afccb72fdc7e9a452988e5db5dd7517ab38792ba21af020f9f1885f686ae5a3  ./zynq7/timings/HCLK_CMT_L.sdf`](./zynq7/timings/HCLK_CMT_L.sdf)
 * [`b5d5ca72d453879fca2bf2470fb0a670ebfb38d6e85cdbfdb3967e2e4f59ee73  ./zynq7/timings/HCLK_IOI3.sdf`](./zynq7/timings/HCLK_IOI3.sdf)
@ -1351,8 +1351,8 @@ Results have checksums;
 * [`3bb5a39c36bcd83a540200072baa4c36057960fa1e35f5fcba875f2a755c34a1  ./zynq7/timings/RIOI3_TBYTETERM.sdf`](./zynq7/timings/RIOI3_TBYTETERM.sdf)
 * [`feb5cf787894379d158c5218ba44af20458c8008a1e75e30df00adde8aa97108  ./zynq7/timings/carry4_slicel.sdf`](./zynq7/timings/carry4_slicel.sdf)
 * [`626d9e188a1c4874f7ac657e82c64df8d52f819624e8ee4f9ed9e557d85ad3f2  ./zynq7/timings/carry4_slicem.sdf`](./zynq7/timings/carry4_slicem.sdf)
- * [`fd31d66077f869d01f13d9fabbd0dcd38b4aab0322179ecf9ac190a3b70c5456  ./zynq7/timings/slicel.sdf`](./zynq7/timings/slicel.sdf)
- * [`3d2da5714d8c81165fa51403fb719b3ddd9e7ea7ab79280ae4e157d11a29172e  ./zynq7/timings/slicem.sdf`](./zynq7/timings/slicem.sdf)
+ * [`ee750af8a355de7fdbcee19e3c216068912f5502b9ad342090a35ba9cce90038  ./zynq7/timings/slicel.sdf`](./zynq7/timings/slicel.sdf)
+ * [`37f7377698f69c400e009e7134fd5752fb93724ffa74dde46d076fb23ef914bb  ./zynq7/timings/slicem.sdf`](./zynq7/timings/slicem.sdf)
 * [`2e714cd17c9768566a3a262edf9665a5bdb3e5bfa9d4756ac6d224b44f24a107  ./zynq7/xc7z010clg400-1/package_pins.csv`](./zynq7/xc7z010clg400-1/package_pins.csv)
 * [`1754ec1c7a8e0447a116984505cc422819d3be06389527de96bf192c5175d095  ./zynq7/xc7z010clg400-1/part.json`](./zynq7/xc7z010clg400-1/part.json)
 * [`43a136f26603c51bd97e9489d223bbc80f278fcc234225ed9fde404402f22683  ./zynq7/xc7z010clg400-1/part.yaml`](./zynq7/xc7z010clg400-1/part.yaml)
--- a/artix7/harness/arty-a7/pmod/design.json
+++ b/artix7/harness/arty-a7/pmod/design.json
@ -10,12 +10,14 @@
            "name": "clk",
            "node": "CLK_HROW_TOP_R_X60Y130/CLK_HROW_CK_BUFHCLK_L0",
            "pin": "G13",
+            "type": "clk",
            "wire": "HCLK_VBRK_X34Y130/HCLK_VBRK_CK_BUFHCLK0"
        },
        {
            "name": "din[0]",
            "node": "INT_L_X0Y102/EE2BEG2",
            "pin": "E15",
+            "type": "in",
            "wire": "VBRK_X9Y107/VBRK_EE2A2",
            "wires_outside_roi": [
                "BRKH_INT_X0Y99/BRKH_INT_L_LV15",
@ -89,6 +91,7 @@
            "name": "din[1]",
            "node": "INT_L_X0Y104/EE2BEG2",
            "pin": "E16",
+            "type": "in",
            "wire": "VBRK_X9Y109/VBRK_EE2A2",
            "wires_outside_roi": [
                "BRKH_INT_X0Y99/BRKH_INT_L_LV16",
@ -161,6 +164,7 @@
            "name": "din[2]",
            "node": "INT_L_X0Y106/EE2BEG2",
            "pin": "D15",
+            "type": "in",
            "wire": "VBRK_X9Y111/VBRK_EE2A2",
            "wires_outside_roi": [
                "BRKH_INT_X0Y99/BRKH_INT_L_LV17",
@ -233,6 +237,7 @@
            "name": "din[3]",
            "node": "INT_L_X0Y108/EE2BEG2",
            "pin": "C15",
+            "type": "in",
            "wire": "VBRK_X9Y113/VBRK_EE2A2",
            "wires_outside_roi": [
                "BRKH_INT_X0Y99/BRKH_INT_NN6BEG3",
@ -297,6 +302,7 @@
            "name": "din[4]",
            "node": "INT_L_X0Y110/EE2BEG2",
            "pin": "J17",
+            "type": "in",
            "wire": "VBRK_X9Y115/VBRK_EE2A2",
            "wires_outside_roi": [
                "BRKH_INT_X0Y99/BRKH_INT_LVB_L9",
@ -385,6 +391,7 @@
            "name": "din[5]",
            "node": "INT_L_X0Y112/EE2BEG2",
            "pin": "J18",
+            "type": "in",
            "wire": "VBRK_X9Y117/VBRK_EE2A2",
            "wires_outside_roi": [
                "BRKH_INT_X0Y99/BRKH_INT_L_LV9",
@ -489,6 +496,7 @@
            "name": "din[6]",
            "node": "INT_L_X0Y114/EE2BEG2",
            "pin": "K15",
+            "type": "in",
            "wire": "VBRK_X9Y119/VBRK_EE2A2",
            "wires_outside_roi": [
                "BRKH_INT_X0Y99/BRKH_INT_L_LV10",
@ -583,6 +591,7 @@
            "name": "din[7]",
            "node": "INT_L_X0Y116/EE2BEG2",
            "pin": "J15",
+            "type": "in",
            "wire": "VBRK_X9Y121/VBRK_EE2A2",
            "wires_outside_roi": [
                "BRKH_INT_X0Y99/BRKH_INT_L_LV11",
@ -691,6 +700,7 @@
            "name": "dout[0]",
            "node": "INT_L_X2Y133/SW6BEG0",
            "pin": "U12",
+            "type": "out",
            "wire": "VBRK_X9Y139/VBRK_SW4A0",
            "wires_outside_roi": [
                "CMT_FIFO_R_X7Y137/CMT_FIFO_SW4A0_8",
@ -709,6 +719,7 @@
            "name": "dout[1]",
            "node": "INT_L_X2Y135/SW6BEG0",
            "pin": "V12",
+            "type": "out",
            "wire": "VBRK_X9Y141/VBRK_SW4A0",
            "wires_outside_roi": [
                "CMT_FIFO_R_X7Y137/CMT_FIFO_SW4A0_10",
@ -727,6 +738,7 @@
            "name": "dout[2]",
            "node": "INT_L_X2Y137/SW6BEG0",
            "pin": "V10",
+            "type": "out",
            "wire": "VBRK_X9Y143/VBRK_SW4A0",
            "wires_outside_roi": [
                "CMT_FIFO_R_X7Y149/CMT_FIFO_SW4A0_0",
@ -745,6 +757,7 @@
            "name": "dout[3]",
            "node": "INT_L_X2Y139/SW6BEG0",
            "pin": "V11",
+            "type": "out",
            "wire": "VBRK_X9Y145/VBRK_SW4A0",
            "wires_outside_roi": [
                "CMT_FIFO_R_X7Y149/CMT_FIFO_SW4A0_2",
@ -763,6 +776,7 @@
            "name": "dout[4]",
            "node": "INT_L_X2Y141/SW6BEG0",
            "pin": "U14",
+            "type": "out",
            "wire": "VBRK_X9Y147/VBRK_SW4A0",
            "wires_outside_roi": [
                "CMT_FIFO_R_X7Y149/CMT_FIFO_SW4A0_4",
@ -781,6 +795,7 @@
            "name": "dout[5]",
            "node": "INT_L_X2Y143/SW6BEG0",
            "pin": "V14",
+            "type": "out",
            "wire": "VBRK_X9Y149/VBRK_SW4A0",
            "wires_outside_roi": [
                "CMT_FIFO_R_X7Y149/CMT_FIFO_SW4A0_6",
@ -799,6 +814,7 @@
            "name": "dout[6]",
            "node": "INT_L_X2Y145/SW6BEG0",
            "pin": "T13",
+            "type": "out",
            "wire": "VBRK_X9Y151/VBRK_SW4A0",
            "wires_outside_roi": [
                "CMT_FIFO_R_X7Y149/CMT_FIFO_SW4A0_8",
@ -817,6 +833,7 @@
            "name": "dout[7]",
            "node": "INT_L_X2Y147/SW6BEG0",
            "pin": "U13",
+            "type": "out",
            "wire": "VBRK_X9Y153/VBRK_SW4A0",
            "wires_outside_roi": [
                "CMT_FIFO_R_X7Y149/CMT_FIFO_SW4A0_10",
--- a/artix7/harness/arty-a7/swbut/design.json
+++ b/artix7/harness/arty-a7/swbut/design.json
@ -10,12 +10,14 @@
            "name": "clk",
            "node": "CLK_HROW_TOP_R_X60Y130/CLK_HROW_CK_BUFHCLK_L0",
            "pin": "E3",
+            "type": "clk",
            "wire": "HCLK_VBRK_X34Y130/HCLK_VBRK_CK_BUFHCLK0"
        },
        {
            "name": "din[0]",
            "node": "INT_L_X0Y104/EE2BEG2",
            "pin": "A8",
+            "type": "in",
            "wire": "VBRK_X9Y109/VBRK_EE2A2",
            "wires_outside_roi": [
                "BRKH_INT_X0Y99/BRKH_INT_LVB_L4",
@ -87,6 +89,7 @@
            "name": "din[1]",
            "node": "INT_L_X0Y108/EE2BEG2",
            "pin": "C11",
+            "type": "in",
            "wire": "VBRK_X9Y113/VBRK_EE2A2",
            "wires_outside_roi": [
                "CMT_FIFO_R_X7Y112/CMT_FIFO_EE2A2_7",
@ -139,6 +142,7 @@
            "name": "din[2]",
            "node": "INT_L_X0Y112/EE2BEG2",
            "pin": "C10",
+            "type": "in",
            "wire": "VBRK_X9Y117/VBRK_EE2A2",
            "wires_outside_roi": [
                "CMT_FIFO_R_X7Y112/CMT_FIFO_EE2A2_11",
@ -189,6 +193,7 @@
            "name": "din[3]",
            "node": "INT_L_X0Y116/EE2BEG2",
            "pin": "A10",
+            "type": "in",
            "wire": "VBRK_X9Y121/VBRK_EE2A2",
            "wires_outside_roi": [
                "CMT_FIFO_R_X7Y124/CMT_FIFO_EE2A2_3",
@ -238,6 +243,7 @@
            "name": "din[4]",
            "node": "INT_L_X0Y120/EE2BEG2",
            "pin": "C9",
+            "type": "in",
            "wire": "VBRK_X9Y125/VBRK_EE2A2",
            "wires_outside_roi": [
                "CMT_FIFO_R_X7Y124/CMT_FIFO_EE2A2_7",
@ -283,6 +289,7 @@
            "name": "din[5]",
            "node": "INT_L_X0Y124/EE2BEG2",
            "pin": "B9",
+            "type": "in",
            "wire": "VBRK_X9Y129/VBRK_EE2A2",
            "wires_outside_roi": [
                "CMT_FIFO_R_X7Y124/CMT_FIFO_EE2A2_11",
@ -324,6 +331,7 @@
            "name": "din[6]",
            "node": "INT_L_X0Y128/EE2BEG2",
            "pin": "B8",
+            "type": "in",
            "wire": "VBRK_X9Y134/VBRK_EE2A2",
            "wires_outside_roi": [
                "CMT_FIFO_R_X7Y137/CMT_FIFO_EE2A2_3",
@ -353,6 +361,7 @@
            "name": "din[7]",
            "node": "INT_L_X0Y132/EE2BEG2",
            "pin": "D9",
+            "type": "in",
            "wire": "VBRK_X9Y138/VBRK_EE2A2",
            "wires_outside_roi": [
                "CMT_FIFO_R_X7Y137/CMT_FIFO_EE2A2_7",
@ -396,6 +405,7 @@
            "name": "dout[0]",
            "node": "INT_R_X23Y117/LH12",
            "pin": "H5",
+            "type": "out",
            "wire": "VBRK_X61Y122/VBRK_LH12",
            "wires_outside_roi": [
                "CLBLL_L_X24Y117/CLBLL_LH12",
@ -435,6 +445,7 @@
            "name": "dout[1]",
            "node": "INT_R_X23Y121/LH12",
            "pin": "J5",
+            "type": "out",
            "wire": "VBRK_X61Y126/VBRK_LH12",
            "wires_outside_roi": [
                "CLBLL_L_X24Y121/CLBLL_LH12",
@ -474,6 +485,7 @@
            "name": "dout[2]",
            "node": "INT_L_X2Y117/SW6BEG0",
            "pin": "T9",
+            "type": "out",
            "wire": "VBRK_X9Y122/VBRK_SW4A0",
            "wires_outside_roi": [
                "CMT_FIFO_R_X7Y124/CMT_FIFO_SW4A0_4",
@ -492,6 +504,7 @@
            "name": "dout[3]",
            "node": "INT_L_X2Y121/SW6BEG0",
            "pin": "T10",
+            "type": "out",
            "wire": "VBRK_X9Y126/VBRK_SW4A0",
            "wires_outside_roi": [
                "CMT_FIFO_R_X7Y124/CMT_FIFO_SW4A0_8",
@ -510,6 +523,7 @@
            "name": "dout[4]",
            "node": "INT_R_X23Y125/LH12",
            "pin": "F6",
+            "type": "out",
            "wire": "VBRK_X61Y131/VBRK_LH12",
            "wires_outside_roi": [
                "BRAM_INT_INTERFACE_L_X30Y125/INT_INTERFACE_LH6",
@ -549,6 +563,7 @@
            "name": "dout[5]",
            "node": "INT_R_X23Y129/LH12",
            "pin": "J4",
+            "type": "out",
            "wire": "VBRK_X61Y135/VBRK_LH12",
            "wires_outside_roi": [
                "BRAM_INT_INTERFACE_L_X30Y129/INT_INTERFACE_LH6",
@ -588,6 +603,7 @@
            "name": "dout[6]",
            "node": "INT_R_X23Y133/LH12",
            "pin": "J2",
+            "type": "out",
            "wire": "VBRK_X61Y139/VBRK_LH12",
            "wires_outside_roi": [
                "BRAM_INT_INTERFACE_L_X30Y133/INT_INTERFACE_LH6",
@ -627,6 +643,7 @@
            "name": "dout[7]",
            "node": "INT_R_X23Y137/LH12",
            "pin": "H6",
+            "type": "out",
            "wire": "VBRK_X61Y143/VBRK_LH12",
            "wires_outside_roi": [
                "BRAM_INT_INTERFACE_L_X30Y137/INT_INTERFACE_LH6",
--- a/artix7/harness/arty-a7/uart/design.json
+++ b/artix7/harness/arty-a7/uart/design.json
@ -10,12 +10,14 @@
            "name": "clk",
            "node": "CLK_HROW_TOP_R_X60Y130/CLK_HROW_CK_BUFHCLK_L0",
            "pin": "E3",
+            "type": "clk",
            "wire": "HCLK_VBRK_X34Y130/HCLK_VBRK_CK_BUFHCLK0"
        },
        {
            "name": "din[0]",
            "node": "INT_R_X25Y126/WW2BEG1",
            "pin": "C2",
+            "type": "in",
            "wire": "VBRK_X61Y132/VBRK_WW2END1",
            "wires_outside_roi": [
                "BRAM_INT_INTERFACE_R_X37Y87/INT_INTERFACE_LH6",
@ -151,6 +153,7 @@
            "name": "din[1]",
            "node": "INT_L_X0Y102/EE2BEG2",
            "pin": "A9",
+            "type": "in",
            "wire": "VBRK_X9Y107/VBRK_EE2A2",
            "wires_outside_roi": [
                "CMT_FIFO_R_X7Y112/CMT_FIFO_EE2A2_1",
@ -213,6 +216,7 @@
            "name": "dout[0]",
            "node": "INT_L_X2Y145/SW6BEG0",
            "pin": "T10",
+            "type": "out",
            "wire": "VBRK_X9Y151/VBRK_SW4A0",
            "wires_outside_roi": [
                "CMT_FIFO_R_X7Y149/CMT_FIFO_SW4A0_8",
@ -231,6 +235,7 @@
            "name": "dout[1]",
            "node": "INT_L_X2Y147/SW6BEG0",
            "pin": "D10",
+            "type": "out",
            "wire": "VBRK_X9Y153/VBRK_SW4A0",
            "wires_outside_roi": [
                "CMT_FIFO_R_X7Y149/CMT_FIFO_SW4A0_10",
--- a/artix7/harness/basys3/swbut/design.json
+++ b/artix7/harness/basys3/swbut/design.json
@ -10,12 +10,14 @@
            "name": "clk",
            "node": "CLK_HROW_TOP_R_X60Y130/CLK_HROW_CK_BUFHCLK_L0",
            "pin": "W5",
+            "type": "clk",
            "wire": "HCLK_VBRK_X34Y130/HCLK_VBRK_CK_BUFHCLK0"
        },
        {
            "name": "din[0]",
            "node": "INT_L_X0Y102/EE2BEG2",
            "pin": "V17",
+            "type": "in",
            "wire": "VBRK_X9Y107/VBRK_EE2A2",
            "wires_outside_roi": [
                "BRKH_INT_X0Y49/BRKH_INT_L_LV1",
@ -142,6 +144,7 @@
            "name": "din[1]",
            "node": "INT_L_X0Y104/EE2BEG2",
            "pin": "V16",
+            "type": "in",
            "wire": "VBRK_X9Y109/VBRK_EE2A2",
            "wires_outside_roi": [
                "BRKH_INT_X0Y49/BRKH_INT_L_LV0",
@ -270,6 +273,7 @@
            "name": "din[2]",
            "node": "INT_L_X0Y106/EE2BEG2",
            "pin": "W16",
+            "type": "in",
            "wire": "VBRK_X9Y111/VBRK_EE2A2",
            "wires_outside_roi": [
                "BRKH_INT_X0Y49/BRKH_INT_L_LV2",
@ -410,6 +414,7 @@
            "name": "din[3]",
            "node": "INT_L_X0Y108/EE2BEG2",
            "pin": "W17",
+            "type": "in",
            "wire": "VBRK_X9Y113/VBRK_EE2A2",
            "wires_outside_roi": [
                "BRKH_INT_X0Y49/BRKH_INT_L_LV3",
@ -546,6 +551,7 @@
            "name": "din[4]",
            "node": "INT_L_X0Y110/EE2BEG2",
            "pin": "W15",
+            "type": "in",
            "wire": "VBRK_X9Y115/VBRK_EE2A2",
            "wires_outside_roi": [
                "BRKH_INT_X0Y49/BRKH_INT_L_LV5",
@ -685,6 +691,7 @@
            "name": "din[5]",
            "node": "INT_L_X0Y112/EE2BEG2",
            "pin": "V15",
+            "type": "in",
            "wire": "VBRK_X9Y117/VBRK_EE2A2",
            "wires_outside_roi": [
                "BRKH_INT_X0Y49/BRKH_INT_L_LV4",
@ -826,6 +833,7 @@
            "name": "din[6]",
            "node": "INT_L_X0Y114/EE2BEG2",
            "pin": "W14",
+            "type": "in",
            "wire": "VBRK_X9Y119/VBRK_EE2A2",
            "wires_outside_roi": [
                "BRKH_INT_X0Y49/BRKH_INT_L_LV7",
@ -971,6 +979,7 @@
            "name": "din[7]",
            "node": "INT_L_X0Y116/EE2BEG2",
            "pin": "W13",
+            "type": "in",
            "wire": "VBRK_X9Y121/VBRK_EE2A2",
            "wires_outside_roi": [
                "BRKH_INT_X0Y49/BRKH_INT_L_LV6",
@ -1118,6 +1127,7 @@
            "name": "din[8]",
            "node": "INT_R_X25Y126/WW2BEG1",
            "pin": "V2",
+            "type": "in",
            "wire": "VBRK_X61Y132/VBRK_WW2END1",
            "wires_outside_roi": [
                "BRAM_INT_INTERFACE_L_X30Y129/INT_INTERFACE_NW4END2",
@ -1298,6 +1308,7 @@
            "name": "din[9]",
            "node": "INT_R_X25Y128/WW2BEG1",
            "pin": "T3",
+            "type": "in",
            "wire": "VBRK_X61Y134/VBRK_WW2END1",
            "wires_outside_roi": [
                "BRAM_INT_INTERFACE_L_X30Y128/INT_INTERFACE_NW4END2",
@ -1464,6 +1475,7 @@
            "name": "din[10]",
            "node": "INT_R_X25Y130/WW2BEG1",
            "pin": "T2",
+            "type": "in",
            "wire": "VBRK_X61Y136/VBRK_WW2END1",
            "wires_outside_roi": [
                "BRAM_INT_INTERFACE_L_X30Y130/INT_INTERFACE_NW4END2",
@ -1630,6 +1642,7 @@
            "name": "din[11]",
            "node": "INT_R_X25Y132/WW2BEG1",
            "pin": "R3",
+            "type": "in",
            "wire": "VBRK_X61Y138/VBRK_WW2END1",
            "wires_outside_roi": [
                "BRAM_INT_INTERFACE_L_X30Y129/INT_INTERFACE_NW4END3",
@ -1810,6 +1823,7 @@
            "name": "din[12]",
            "node": "INT_R_X25Y134/WW2BEG1",
            "pin": "W2",
+            "type": "in",
            "wire": "VBRK_X61Y140/VBRK_WW2END1",
            "wires_outside_roi": [
                "BRAM_INT_INTERFACE_L_X30Y134/INT_INTERFACE_NW4END3",
@ -2002,6 +2016,7 @@
            "name": "din[13]",
            "node": "INT_R_X25Y136/WW2BEG1",
            "pin": "U1",
+            "type": "in",
            "wire": "VBRK_X61Y142/VBRK_WW2END1",
            "wires_outside_roi": [
                "BRAM_INT_INTERFACE_L_X30Y132/INT_INTERFACE_NW4END2",
@ -2179,6 +2194,7 @@
            "name": "din[14]",
            "node": "INT_R_X25Y138/WW2BEG1",
            "pin": "T1",
+            "type": "in",
            "wire": "VBRK_X61Y144/VBRK_WW2END1",
            "wires_outside_roi": [
                "BRAM_INT_INTERFACE_L_X30Y135/INT_INTERFACE_LH2",
@ -2384,6 +2400,7 @@
            "name": "din[15]",
            "node": "INT_R_X25Y140/WW2BEG1",
            "pin": "R2",
+            "type": "in",
            "wire": "VBRK_X61Y146/VBRK_WW2END1",
            "wires_outside_roi": [
                "BRAM_INT_INTERFACE_L_X30Y139/INT_INTERFACE_WW4B3",
@ -2560,6 +2577,7 @@
            "name": "din[16]",
            "node": "INT_L_X0Y118/EE2BEG2",
            "pin": "B18",
+            "type": "in",
            "wire": "VBRK_X9Y123/VBRK_EE2A2",
            "wires_outside_roi": [
                "CMT_FIFO_R_X7Y124/CMT_FIFO_EE2A2_5",
@ -2607,6 +2625,7 @@
            "name": "dout[0]",
            "node": "INT_L_X2Y115/SW6BEG0",
            "pin": "U16",
+            "type": "out",
            "wire": "VBRK_X9Y120/VBRK_SW4A0",
            "wires_outside_roi": [
                "CMT_FIFO_R_X7Y124/CMT_FIFO_SW4A0_2",
@ -2625,6 +2644,7 @@
            "name": "dout[1]",
            "node": "INT_L_X2Y117/SW6BEG0",
            "pin": "E19",
+            "type": "out",
            "wire": "VBRK_X9Y122/VBRK_SW4A0",
            "wires_outside_roi": [
                "CMT_FIFO_R_X7Y124/CMT_FIFO_SW4A0_4",
@ -2643,6 +2663,7 @@
            "name": "dout[2]",
            "node": "INT_L_X2Y119/SW6BEG0",
            "pin": "U19",
+            "type": "out",
            "wire": "VBRK_X9Y124/VBRK_SW4A0",
            "wires_outside_roi": [
                "CMT_FIFO_R_X7Y124/CMT_FIFO_SW4A0_6",
@ -2661,6 +2682,7 @@
            "name": "dout[3]",
            "node": "INT_L_X2Y121/SW6BEG0",
            "pin": "V19",
+            "type": "out",
            "wire": "VBRK_X9Y126/VBRK_SW4A0",
            "wires_outside_roi": [
                "CMT_FIFO_R_X7Y124/CMT_FIFO_SW4A0_8",
@ -2679,6 +2701,7 @@
            "name": "dout[4]",
            "node": "INT_L_X2Y123/SW6BEG0",
            "pin": "W18",
+            "type": "out",
            "wire": "VBRK_X9Y128/VBRK_SW4A0",
            "wires_outside_roi": [
                "CMT_FIFO_R_X7Y124/CMT_FIFO_SW4A0_10",
@ -2697,6 +2720,7 @@
            "name": "dout[5]",
            "node": "INT_L_X2Y125/SW6BEG0",
            "pin": "U15",
+            "type": "out",
            "wire": "VBRK_X9Y131/VBRK_SW4A0",
            "wires_outside_roi": [
                "CMT_FIFO_R_X7Y137/CMT_FIFO_SW4A0_0",
@ -2716,6 +2740,7 @@
            "name": "dout[6]",
            "node": "INT_L_X2Y127/SW6BEG0",
            "pin": "U14",
+            "type": "out",
            "wire": "VBRK_X9Y133/VBRK_SW4A0",
            "wires_outside_roi": [
                "CMT_FIFO_R_X7Y137/CMT_FIFO_SW4A0_2",
@ -2735,6 +2760,7 @@
            "name": "dout[7]",
            "node": "INT_L_X2Y129/SW6BEG0",
            "pin": "V14",
+            "type": "out",
            "wire": "VBRK_X9Y135/VBRK_SW4A0",
            "wires_outside_roi": [
                "CMT_FIFO_R_X7Y137/CMT_FIFO_SW4A0_4",
@ -2753,6 +2779,7 @@
            "name": "dout[8]",
            "node": "INT_L_X2Y131/SW6BEG0",
            "pin": "V13",
+            "type": "out",
            "wire": "VBRK_X9Y137/VBRK_SW4A0",
            "wires_outside_roi": [
                "CMT_FIFO_R_X7Y137/CMT_FIFO_SW4A0_6",
@ -2771,6 +2798,7 @@
            "name": "dout[9]",
            "node": "INT_R_X23Y115/LH12",
            "pin": "V3",
+            "type": "out",
            "wire": "VBRK_X61Y120/VBRK_LH12",
            "wires_outside_roi": [
                "CLBLL_L_X24Y115/CLBLL_LH12",
@ -2810,6 +2838,7 @@
            "name": "dout[10]",
            "node": "INT_R_X23Y117/LH12",
            "pin": "W3",
+            "type": "out",
            "wire": "VBRK_X61Y122/VBRK_LH12",
            "wires_outside_roi": [
                "CLBLL_L_X24Y117/CLBLL_LH12",
@ -2849,6 +2878,7 @@
            "name": "dout[11]",
            "node": "INT_R_X23Y119/LH12",
            "pin": "U3",
+            "type": "out",
            "wire": "VBRK_X61Y124/VBRK_LH12",
            "wires_outside_roi": [
                "CLBLL_L_X24Y119/CLBLL_LH12",
@ -2888,6 +2918,7 @@
            "name": "dout[12]",
            "node": "INT_R_X23Y121/LH12",
            "pin": "P3",
+            "type": "out",
            "wire": "VBRK_X61Y126/VBRK_LH12",
            "wires_outside_roi": [
                "CLBLL_L_X24Y121/CLBLL_LH12",
@ -2927,6 +2958,7 @@
            "name": "dout[13]",
            "node": "INT_R_X23Y123/LH12",
            "pin": "N3",
+            "type": "out",
            "wire": "VBRK_X61Y128/VBRK_LH12",
            "wires_outside_roi": [
                "CLBLL_L_X24Y123/CLBLL_LH12",
@ -2966,6 +2998,7 @@
            "name": "dout[14]",
            "node": "INT_R_X23Y125/LH12",
            "pin": "P1",
+            "type": "out",
            "wire": "VBRK_X61Y131/VBRK_LH12",
            "wires_outside_roi": [
                "BRAM_INT_INTERFACE_L_X30Y125/INT_INTERFACE_LH6",
@ -3005,6 +3038,7 @@
            "name": "dout[15]",
            "node": "INT_R_X23Y127/LH12",
            "pin": "L1",
+            "type": "out",
            "wire": "VBRK_X61Y133/VBRK_LH12",
            "wires_outside_roi": [
                "BRAM_INT_INTERFACE_L_X30Y127/INT_INTERFACE_LH6",
@ -3044,6 +3078,7 @@
            "name": "dout[16]",
            "node": "INT_L_X2Y133/SW6BEG0",
            "pin": "A18",
+            "type": "out",
            "wire": "VBRK_X9Y139/VBRK_SW4A0",
            "wires_outside_roi": [
                "CMT_FIFO_R_X7Y137/CMT_FIFO_SW4A0_8",
--- a/artix7/mask_lioi3.db
+++ b/artix7/mask_lioi3.db
@ -1,11 +1,11 @@
 bit 25_07
 bit 25_20
 bit 25_21
-bit 25_23
 bit 25_31
 bit 25_32
 bit 25_34
 bit 25_35
+bit 25_39
 bit 25_47
 bit 25_48
 bit 25_51
@ -16,7 +16,6 @@ bit 25_71
 bit 25_84
 bit 25_85
 bit 25_95
-bit 25_96
 bit 25_98
 bit 25_99
 bit 25_111
--- a/artix7/mask_lioi3_tbytesrc.db
+++ b/artix7/mask_lioi3_tbytesrc.db
@ -1,11 +1,11 @@
 bit 25_07
 bit 25_20
 bit 25_21
-bit 25_23
 bit 25_31
 bit 25_32
 bit 25_34
 bit 25_35
+bit 25_39
 bit 25_47
 bit 25_48
 bit 25_51
@ -16,7 +16,6 @@ bit 25_71
 bit 25_84
 bit 25_85
 bit 25_95
-bit 25_96
 bit 25_98
 bit 25_99
 bit 25_111
--- a/artix7/mask_lioi3_tbyteterm.db
+++ b/artix7/mask_lioi3_tbyteterm.db
@ -1,11 +1,11 @@
 bit 25_07
 bit 25_20
 bit 25_21
-bit 25_23
 bit 25_31
 bit 25_32
 bit 25_34
 bit 25_35
+bit 25_39
 bit 25_47
 bit 25_48
 bit 25_51
@ -16,7 +16,6 @@ bit 25_71
 bit 25_84
 bit 25_85
 bit 25_95
-bit 25_96
 bit 25_98
 bit 25_99
 bit 25_111
--- a/artix7/mask_rioi3.db
+++ b/artix7/mask_rioi3.db
@ -1,11 +1,11 @@
 bit 25_07
 bit 25_20
 bit 25_21
-bit 25_23
 bit 25_31
 bit 25_32
 bit 25_34
 bit 25_35
+bit 25_39
 bit 25_47
 bit 25_48
 bit 25_51
@ -16,7 +16,6 @@ bit 25_71
 bit 25_84
 bit 25_85
 bit 25_95
-bit 25_96
 bit 25_98
 bit 25_99
 bit 25_111
--- a/artix7/mask_rioi3_tbytesrc.db
+++ b/artix7/mask_rioi3_tbytesrc.db
@ -1,11 +1,11 @@
 bit 25_07
 bit 25_20
 bit 25_21
-bit 25_23
 bit 25_31
 bit 25_32
 bit 25_34
 bit 25_35
+bit 25_39
 bit 25_47
 bit 25_48
 bit 25_51
@ -16,7 +16,6 @@ bit 25_71
 bit 25_84
 bit 25_85
 bit 25_95
-bit 25_96
 bit 25_98
 bit 25_99
 bit 25_111
--- a/artix7/mask_rioi3_tbyteterm.db
+++ b/artix7/mask_rioi3_tbyteterm.db
@ -1,11 +1,11 @@
 bit 25_07
 bit 25_20
 bit 25_21
-bit 25_23
 bit 25_31
 bit 25_32
 bit 25_34
 bit 25_35
+bit 25_39
 bit 25_47
 bit 25_48
 bit 25_51
@ -16,7 +16,6 @@ bit 25_71
 bit 25_84
 bit 25_85
 bit 25_95
-bit 25_96
 bit 25_98
 bit 25_99
 bit 25_111
--- a/artix7/segbits_int_l.origin_info.db
+++ b/artix7/segbits_int_l.origin_info.db
@ -170,7 +170,7 @@ INT_L.BYP_ALT7.BYP_BOUNCE2 origin:050-pip-seed !22_63 !23_63 !24_63 21_63 25_63
 INT_L.BYP_ALT7.BYP_BOUNCE6 origin:050-pip-seed !22_63 !23_63 !25_63 21_63 24_63
 INT_L.BYP_ALT7.EL1END_S3_0 origin:050-pip-seed !23_63 17_63 22_63 24_63 25_63
 INT_L.BYP_ALT7.FAN_BOUNCE_S3_4 origin:050-pip-seed !23_63 21_63 22_63 24_63 25_63
-INT_L.BYP_ALT7.FAN_BOUNCE_S3_6 origin:050-pip-seed !22_63 21_63 23_63 24_63 25_63
+INT_L.BYP_ALT7.FAN_BOUNCE_S3_6 origin:056-pip-rem !22_63 21_63 23_63 24_63 25_63
 INT_L.BYP_ALT7.LOGIC_OUTS_L3 origin:051-pip-imuxlout-bypalts !22_63 20_63 23_63 24_63 25_63
 INT_L.BYP_ALT7.LOGIC_OUTS_L15 origin:051-pip-imuxlout-bypalts !23_63 20_63 22_63 24_63 25_63
 INT_L.BYP_ALT7.LOGIC_OUTS_L21 origin:051-pip-imuxlout-bypalts !22_63 !23_63 !24_63 20_63 25_63
@ -392,7 +392,7 @@ INT_L.FAN_ALT3.WR1END3 origin:050-pip-seed !23_56 16_56 22_56 24_56 25_56
 INT_L.FAN_ALT3.WW2END3 origin:050-pip-seed !22_56 !23_56 !24_56 19_57 25_56
 INT_L.FAN_ALT4.BYP_BOUNCE_N3_3 origin:059-pip-byp-bounce !22_08 !23_08 !24_08 20_08 25_08
 INT_L.FAN_ALT4.BYP_BOUNCE_N3_7 origin:059-pip-byp-bounce !22_08 !23_08 !25_08 20_08 24_08
-INT_L.FAN_ALT4.FAN_BOUNCE2 origin:056-pip-rem !23_08 20_08 22_08 24_08 25_08
+INT_L.FAN_ALT4.FAN_BOUNCE2 origin:050-pip-seed !23_08 20_08 22_08 24_08 25_08
 INT_L.FAN_ALT4.FAN_BOUNCE7 origin:056-pip-rem !22_08 20_08 23_08 24_08 25_08
 INT_L.FAN_ALT4.LOGIC_OUTS_L4 origin:050-pip-seed !23_08 21_08 22_08 24_08 25_08
 INT_L.FAN_ALT4.LOGIC_OUTS_L8 origin:050-pip-seed !22_08 21_08 23_08 24_08 25_08
@ -1897,7 +1897,7 @@ INT_L.EE4BEG1.SE6END1 origin:050-pip-seed 03_25 06_24
 INT_L.EE4BEG1.SS2END1 origin:050-pip-seed 03_24 05_27
 INT_L.EE4BEG1.SS6END1 origin:050-pip-seed 05_27 06_24
 INT_L.EE4BEG1.SW2END1 origin:050-pip-seed 02_25 05_27
-INT_L.EE4BEG1.SW6END1 origin:056-pip-rem 05_24 05_27
+INT_L.EE4BEG1.SW6END1 origin:050-pip-seed 05_24 05_27
 INT_L.EE4BEG2.LOGIC_OUTS_L2 origin:050-pip-seed 02_41 04_42
 INT_L.EE4BEG2.LOGIC_OUTS_L6 origin:050-pip-seed 02_41 07_41
 INT_L.EE4BEG2.LOGIC_OUTS_L10 origin:050-pip-seed 03_40 07_41
@ -1917,7 +1917,7 @@ INT_L.EE4BEG2.SE6END2 origin:050-pip-seed 03_41 06_40
 INT_L.EE4BEG2.SS2END2 origin:050-pip-seed 03_40 05_43
 INT_L.EE4BEG2.SS6END2 origin:050-pip-seed 05_43 06_40
 INT_L.EE4BEG2.SW2END2 origin:050-pip-seed 02_41 05_43
-INT_L.EE4BEG2.SW6END2 origin:056-pip-rem 05_40 05_43
+INT_L.EE4BEG2.SW6END2 origin:050-pip-seed 05_40 05_43
 INT_L.EE4BEG3.LOGIC_OUTS_L3 origin:050-pip-seed 02_57 07_57
 INT_L.EE4BEG3.LOGIC_OUTS_L7 origin:050-pip-seed 02_57 04_58
 INT_L.EE4BEG3.LOGIC_OUTS_L11 origin:050-pip-seed 03_56 04_58
@ -2273,7 +2273,7 @@ INT_L.NE6BEG3.NW6END3 origin:050-pip-seed 04_53 06_52
 INT_L.NE6BEG3.SE2END3 origin:050-pip-seed 02_53 05_55
 INT_L.NE6BEG3.SE6END3 origin:050-pip-seed 05_55 06_52
 INT_L.NE6BEG3.WW2END2 origin:050-pip-seed 03_52 04_53
-INT_L.NE6BEG3.WW4END3 origin:050-pip-seed 04_53 05_52
+INT_L.NE6BEG3.WW4END3 origin:056-pip-rem 04_53 05_52
 INT_L.NL1BEG0.LOGIC_OUTS_L1 origin:050-pip-seed 07_16 14_17
 INT_L.NL1BEG0.LOGIC_OUTS_L5 origin:050-pip-seed 11_17 14_17
 INT_L.NL1BEG0.LOGIC_OUTS_L9 origin:050-pip-seed 10_17 13_17
@ -2491,7 +2491,7 @@ INT_L.NN6BEG3.NN6END3 origin:050-pip-seed 02_54 07_55
 INT_L.NN6BEG3.NW2END3 origin:050-pip-seed 03_54 04_52
 INT_L.NN6BEG3.NW6END3 origin:050-pip-seed 04_52 07_55
 INT_L.NN6BEG3.SE2END3 origin:050-pip-seed 03_54 05_54
-INT_L.NN6BEG3.SE6END3 origin:056-pip-rem 05_54 07_55
+INT_L.NN6BEG3.SE6END3 origin:050-pip-seed 05_54 07_55
 INT_L.NN6BEG3.WW2END2 origin:050-pip-seed 02_55 04_52
 INT_L.NN6BEG3.WW4END3 origin:050-pip-seed 04_52 04_55
 INT_L.NR1BEG0.LOGIC_OUTS_L0 origin:050-pip-seed 11_07 14_07
@ -2662,7 +2662,7 @@ INT_L.NW6BEG0.LOGIC_OUTS_L18 origin:050-pip-seed 05_01 07_03
 INT_L.NW6BEG0.LOGIC_OUTS_L22 origin:050-pip-seed 06_02 07_03
 INT_L.NW6BEG0.LV_L0 origin:056-pip-rem 04_03 06_02
 INT_L.NW6BEG0.SS2END_N0_3 origin:050-pip-seed 02_03 04_00
-INT_L.NW6BEG0.SS6END_N0_3 origin:050-pip-seed 04_00 07_03
+INT_L.NW6BEG0.SS6END_N0_3 origin:056-pip-rem 04_00 07_03
 INT_L.NW6BEG0.SW2END_N0_3 origin:050-pip-seed 03_02 04_00
 INT_L.NW6BEG0.SW6END_N0_3 origin:050-pip-seed 04_00 04_03
 INT_L.NW6BEG0.WW2END_N0_3 origin:050-pip-seed 02_02 02_03
@ -3583,7 +3583,7 @@ INT_L.WW4BEG1.LOGIC_OUTS_L23 origin:050-pip-seed 06_16 07_17
 INT_L.WW4BEG1.LV_L9 origin:056-pip-rem 04_18 05_16
 INT_L.WW4BEG1.LH6 origin:056-pip-rem 05_16 07_17
 INT_L.WW4BEG1.NE2END1 origin:050-pip-seed 02_17 05_19
-INT_L.WW4BEG1.NE6END1 origin:056-pip-rem 05_16 05_19
+INT_L.WW4BEG1.NE6END1 origin:050-pip-seed 05_16 05_19
 INT_L.WW4BEG1.NN2END1 origin:050-pip-seed 03_16 05_19
 INT_L.WW4BEG1.NN6END1 origin:050-pip-seed 05_19 06_16
 INT_L.WW4BEG1.NW2END1 origin:050-pip-seed 02_17 03_17
--- a/artix7/segbits_int_r.db
+++ b/artix7/segbits_int_r.db
@ -1916,7 +1916,7 @@ INT_R.IMUX43.FAN_BOUNCE3 20_30 !22_30 23_30 24_30 25_30
 INT_R.IMUX43.FAN_BOUNCE5 20_30 22_30 !23_30 24_30 25_30
 INT_R.IMUX43.LOGIC_OUTS1 21_30 22_30 !23_30 24_30 25_30
 INT_R.IMUX43.LOGIC_OUTS13 21_30 !22_30 23_30 24_30 25_30
-INT_R.IMUX43.LOGIC_OUTS23 21_30 !22_30 !23_30 24_30 !25_30
+INT_R.IMUX43.LOGIC_OUTS23 20_00 21_30 !22_30 !23_30 24_30 !25_30
 INT_R.IMUX43.EE2END1 19_31 !22_30 !23_30 !24_30 25_30
 INT_R.IMUX43.EL1END2 19_31 !22_30 23_30 24_30 25_30
 INT_R.IMUX43.ER1END1 18_31 22_30 !23_30 24_30 25_30
--- a/artix7/segbits_int_r.origin_info.db
+++ b/artix7/segbits_int_r.origin_info.db
@ -328,11 +328,11 @@ INT_R.FAN_ALT3.WR1END3 origin:050-pip-seed !23_56 16_56 22_56 24_56 25_56
 INT_R.FAN_ALT3.WW2END3 origin:050-pip-seed !22_56 !23_56 !24_56 19_57 25_56
 INT_R.FAN_ALT4.BYP_BOUNCE_N3_3 origin:059-pip-byp-bounce !22_08 !23_08 !24_08 20_08 25_08
 INT_R.FAN_ALT4.BYP_BOUNCE_N3_7 origin:059-pip-byp-bounce !22_08 !23_08 !25_08 20_08 24_08
-INT_R.FAN_ALT4.FAN_BOUNCE2 origin:050-pip-seed !23_08 20_08 22_08 24_08 25_08
+INT_R.FAN_ALT4.FAN_BOUNCE2 origin:056-pip-rem !23_08 20_08 22_08 24_08 25_08
 INT_R.FAN_ALT4.FAN_BOUNCE7 origin:056-pip-rem !22_08 20_08 23_08 24_08 25_08
 INT_R.FAN_ALT4.LOGIC_OUTS4 origin:050-pip-seed !23_08 21_08 22_08 24_08 25_08
 INT_R.FAN_ALT4.LOGIC_OUTS8 origin:050-pip-seed !22_08 21_08 23_08 24_08 25_08
-INT_R.FAN_ALT4.LOGIC_OUTS18 origin:050-pip-seed !22_08 !23_08 !25_08 21_08 24_08
+INT_R.FAN_ALT4.LOGIC_OUTS18 origin:056-pip-rem !22_08 !23_08 !25_08 21_08 24_08
 INT_R.FAN_ALT4.SR1BEG_S0 origin:050-pip-seed !23_08 19_09 22_08 24_08 25_08
 INT_R.FAN_ALT4.EE2END0 origin:050-pip-seed !22_08 !23_08 !24_08 16_08 25_08
 INT_R.FAN_ALT4.EL1END0 origin:050-pip-seed !22_08 16_08 23_08 24_08 25_08
@ -665,7 +665,7 @@ INT_R.EE4BEG0.SE6END0 origin:050-pip-seed 03_09 06_08
 INT_R.EE4BEG0.SS2END0 origin:050-pip-seed 03_08 05_11
 INT_R.EE4BEG0.SS6END0 origin:050-pip-seed 05_11 06_08
 INT_R.EE4BEG0.SW2END0 origin:050-pip-seed 02_09 05_11
-INT_R.EE4BEG0.SW6END0 origin:050-pip-seed 05_08 05_11
+INT_R.EE4BEG0.SW6END0 origin:056-pip-rem 05_08 05_11
 INT_R.EE4BEG1.LOGIC_OUTS1 origin:050-pip-seed 02_25 07_25
 INT_R.EE4BEG1.LOGIC_OUTS5 origin:050-pip-seed 02_25 04_26
 INT_R.EE4BEG1.LOGIC_OUTS9 origin:050-pip-seed 03_24 04_26
@ -685,7 +685,7 @@ INT_R.EE4BEG1.SE6END1 origin:050-pip-seed 03_25 06_24
 INT_R.EE4BEG1.SS2END1 origin:050-pip-seed 03_24 05_27
 INT_R.EE4BEG1.SS6END1 origin:050-pip-seed 05_27 06_24
 INT_R.EE4BEG1.SW2END1 origin:050-pip-seed 02_25 05_27
-INT_R.EE4BEG1.SW6END1 origin:056-pip-rem 05_24 05_27
+INT_R.EE4BEG1.SW6END1 origin:050-pip-seed 05_24 05_27
 INT_R.EE4BEG2.LOGIC_OUTS2 origin:050-pip-seed 02_41 04_42
 INT_R.EE4BEG2.LOGIC_OUTS6 origin:050-pip-seed 02_41 07_41
 INT_R.EE4BEG2.LOGIC_OUTS10 origin:050-pip-seed 03_40 07_41
@ -1916,7 +1916,7 @@ INT_R.IMUX43.FAN_BOUNCE3 origin:050-pip-seed !22_30 20_30 23_30 24_30 25_30
 INT_R.IMUX43.FAN_BOUNCE5 origin:050-pip-seed !23_30 20_30 22_30 24_30 25_30
 INT_R.IMUX43.LOGIC_OUTS1 origin:051-pip-imuxlout-bypalts !23_30 21_30 22_30 24_30 25_30
 INT_R.IMUX43.LOGIC_OUTS13 origin:051-pip-imuxlout-bypalts !22_30 21_30 23_30 24_30 25_30
-INT_R.IMUX43.LOGIC_OUTS23 origin:051-pip-imuxlout-bypalts !22_30 !23_30 !25_30 21_30 24_30
+INT_R.IMUX43.LOGIC_OUTS23 origin:051-pip-imuxlout-bypalts !22_30 !23_30 !25_30 20_00 21_30 24_30
 INT_R.IMUX43.EE2END1 origin:050-pip-seed !22_30 !23_30 !24_30 19_31 25_30
 INT_R.IMUX43.EL1END2 origin:050-pip-seed !22_30 19_31 23_30 24_30 25_30
 INT_R.IMUX43.ER1END1 origin:050-pip-seed !23_30 18_31 22_30 24_30 25_30
@ -2491,7 +2491,7 @@ INT_R.NN6BEG3.NN6END3 origin:050-pip-seed 02_54 07_55
 INT_R.NN6BEG3.NW2END3 origin:050-pip-seed 03_54 04_52
 INT_R.NN6BEG3.NW6END3 origin:050-pip-seed 04_52 07_55
 INT_R.NN6BEG3.SE2END3 origin:050-pip-seed 03_54 05_54
-INT_R.NN6BEG3.SE6END3 origin:056-pip-rem 05_54 07_55
+INT_R.NN6BEG3.SE6END3 origin:050-pip-seed 05_54 07_55
 INT_R.NN6BEG3.WW2END2 origin:050-pip-seed 02_55 04_52
 INT_R.NN6BEG3.WW4END3 origin:050-pip-seed 04_52 04_55
 INT_R.NR1BEG0.LOGIC_OUTS0 origin:050-pip-seed 11_07 14_07
@ -3321,7 +3321,7 @@ INT_R.SW6BEG2.LOGIC_OUTS14 origin:050-pip-seed 03_44 07_45
 INT_R.SW6BEG2.LOGIC_OUTS16 origin:050-pip-seed 04_46 06_44
 INT_R.SW6BEG2.LOGIC_OUTS20 origin:050-pip-seed 06_44 07_45
 INT_R.SW6BEG2.EE2END2 origin:050-pip-seed 03_44 04_45
-INT_R.SW6BEG2.EE4END2 origin:056-pip-rem 04_45 05_44
+INT_R.SW6BEG2.EE4END2 origin:050-pip-seed 04_45 05_44
 INT_R.SW6BEG2.LVB0 origin:056-pip-rem 04_46 05_44
 INT_R.SW6BEG2.LVB12 origin:056-pip-rem 05_44 07_45
 INT_R.SW6BEG2.NW2END3 origin:050-pip-seed 02_45 05_47
@ -3568,7 +3568,7 @@ INT_R.WW4BEG0.WW2END_N0_3 origin:050-pip-seed 03_00 03_01
 INT_R.WW4BEG0.LH12 origin:056-pip-rem 05_00 07_01
 INT_R.WW4BEG0.LV0 origin:056-pip-rem 04_02 05_00
 INT_R.WW4BEG0.NE2END0 origin:050-pip-seed 02_01 05_03
-INT_R.WW4BEG0.NE6END0 origin:050-pip-seed 05_00 05_03
+INT_R.WW4BEG0.NE6END0 origin:056-pip-rem 05_00 05_03
 INT_R.WW4BEG0.NN2END0 origin:050-pip-seed 03_00 05_03
 INT_R.WW4BEG0.NN6END0 origin:050-pip-seed 05_03 06_00
 INT_R.WW4BEG0.NW2END0 origin:050-pip-seed 02_01 03_01
--- a/artix7/timings/DSP_L.sdf
+++ b/artix7/timings/DSP_L.sdf
@ -260,13 +260,13 @@
        (INSTANCE DSP48E1)
        (DELAY
            (ABSOLUTE
-                (IOPATH D CARRYCASCOUT (0.596::2.268)(1.345::5.400))
-                (IOPATH D CARRYOUT (0.580::2.133)(1.334::5.046))
-                (IOPATH D MULTSIGNOUT (0.592::2.140)(1.323::5.029))
-                (IOPATH D P (0.587::2.142)(1.346::5.070))
-                (IOPATH D PATTERNBDETECT (0.628::2.339)(1.430::5.636))
-                (IOPATH D PATTERNDETECT (0.628::2.339)(1.430::5.636))
-                (IOPATH D PCOUT (0.580::2.133)(1.334::5.046))
+                (IOPATH A CARRYCASCOUT (0.596::2.268)(1.345::5.400))
+                (IOPATH A CARRYOUT (0.580::2.133)(1.334::5.046))
+                (IOPATH A MULTSIGNOUT (0.592::2.140)(1.323::5.029))
+                (IOPATH A P (0.587::2.142)(1.346::5.070))
+                (IOPATH A PATTERNBDETECT (0.628::2.339)(1.430::5.636))
+                (IOPATH A PATTERNDETECT (0.628::2.339)(1.430::5.636))
+                (IOPATH A PCOUT (0.580::2.133)(1.334::5.046))
            )
        )
    )
@ -275,13 +275,13 @@
        (INSTANCE DSP48E1)
        (DELAY
            (ABSOLUTE
-                (IOPATH D CARRYCASCOUT (0.596::2.268)(1.345::5.400))
-                (IOPATH D CARRYOUT (0.580::2.133)(1.334::5.046))
-                (IOPATH D MULTSIGNOUT (0.592::2.140)(1.323::5.029))
-                (IOPATH D P (0.587::2.142)(1.346::5.070))
-                (IOPATH D PATTERNBDETECT (0.628::2.339)(1.430::5.636))
-                (IOPATH D PATTERNDETECT (0.628::2.339)(1.430::5.636))
-                (IOPATH D PCOUT (0.580::2.133)(1.334::5.046))
+                (IOPATH A CARRYCASCOUT (0.596::2.268)(1.345::5.400))
+                (IOPATH A CARRYOUT (0.580::2.133)(1.334::5.046))
+                (IOPATH A MULTSIGNOUT (0.592::2.140)(1.323::5.029))
+                (IOPATH A P (0.587::2.142)(1.346::5.070))
+                (IOPATH A PATTERNBDETECT (0.628::2.339)(1.430::5.636))
+                (IOPATH A PATTERNDETECT (0.628::2.339)(1.430::5.636))
+                (IOPATH A PCOUT (0.580::2.133)(1.334::5.046))
            )
        )
    )
@ -289,32 +289,32 @@
        (CELLTYPE "DSP48E1_ADREG_0_DREG_0_MREG_0_PREG_1_USE_DPORT_TRUE_USE_MULT_DYNAMIC_USE_PATTERN_DETECT_NO_PATDET")
        (INSTANCE DSP48E1)
        (TIMINGCHECK
-            (HOLD D (posedge CLK) (-4.951::-0.994))
-            (SETUP D (posedge CLK) (0.994::4.951))
+            (HOLD A (posedge CLK) (-4.951::-0.994))
+            (SETUP A (posedge CLK) (0.994::4.951))
        )
    )
    (CELL
        (CELLTYPE "DSP48E1_ADREG_0_DREG_0_MREG_0_PREG_1_USE_DPORT_TRUE_USE_MULT_DYNAMIC_USE_PATTERN_DETECT_PATDET")
        (INSTANCE DSP48E1)
        (TIMINGCHECK
-            (HOLD D (posedge CLK) (-5.342::-1.063))
-            (SETUP D (posedge CLK) (1.063::5.342))
+            (HOLD A (posedge CLK) (-5.342::-1.063))
+            (SETUP A (posedge CLK) (1.063::5.342))
        )
    )
    (CELL
        (CELLTYPE "DSP48E1_ADREG_0_DREG_0_MREG_0_PREG_1_USE_DPORT_TRUE_USE_MULT_MULTIPLY_USE_PATTERN_DETECT_NO_PATDET")
        (INSTANCE DSP48E1)
        (TIMINGCHECK
-            (HOLD D (posedge CLK) (-4.951::-0.994))
-            (SETUP D (posedge CLK) (0.994::4.951))
+            (HOLD A (posedge CLK) (-4.951::-0.994))
+            (SETUP A (posedge CLK) (0.994::4.951))
        )
    )
    (CELL
        (CELLTYPE "DSP48E1_ADREG_0_DREG_0_MREG_0_PREG_1_USE_DPORT_TRUE_USE_MULT_MULTIPLY_USE_PATTERN_DETECT_PATDET")
        (INSTANCE DSP48E1)
        (TIMINGCHECK
-            (HOLD D (posedge CLK) (-5.342::-1.063))
-            (SETUP D (posedge CLK) (1.063::5.342))
+            (HOLD A (posedge CLK) (-5.342::-1.063))
+            (SETUP A (posedge CLK) (1.063::5.342))
        )
    )
    (CELL
@ -1837,12 +1837,8 @@
        (INSTANCE DSP48E1)
        (DELAY
            (ABSOLUTE
-                (IOPATH CLK CARRYCASCOUT (0.705::2.375)(1.531::5.650))
                (IOPATH CLK CARRYOUT (0.688::2.241)(1.522::5.297))
-                (IOPATH CLK MULTSIGNOUT (0.700::2.248)(1.510::5.279))
                (IOPATH CLK P (0.696::2.251)(1.533::5.320))
-                (IOPATH CLK PATTERNBDETECT (0.736::2.447)(1.618::5.885))
-                (IOPATH CLK PATTERNDETECT (0.736::2.447)(1.618::5.885))
                (IOPATH CLK PCOUT (0.717::2.334)(1.575::5.515))
            )
        )
@ -1852,14 +1848,34 @@
        (INSTANCE DSP48E1)
        (DELAY
            (ABSOLUTE
-                (IOPATH CLK CARRYCASCOUT (0.705::2.375)(1.531::5.650))
                (IOPATH CLK CARRYOUT (0.688::2.241)(1.522::5.297))
-                (IOPATH CLK MULTSIGNOUT (0.700::2.248)(1.510::5.279))
                (IOPATH CLK P (0.696::2.251)(1.533::5.320))
-                (IOPATH CLK PATTERNBDETECT (0.736::2.447)(1.618::5.885))
-                (IOPATH CLK PATTERNDETECT (0.736::2.447)(1.618::5.885))
                (IOPATH CLK PCOUT (0.717::2.334)(1.575::5.515))
            )
        )
    )
+    (CELL
+        (CELLTYPE "DSP48E1DREG_1_A_ADREG_0_DREG_0_MREG_0_PREG_0_USE_DPORT_TRUE_USE_MULT_DYNAMIC")
+        (INSTANCE DSP48E1)
+        (DELAY
+            (ABSOLUTE
+                (IOPATH CLK CARRYCASCOUT (0.705::2.375)(1.531::5.650))
+                (IOPATH CLK MULTSIGNOUT (0.700::2.248)(1.510::5.279))
+                (IOPATH CLK PATTERNBDETECT (0.736::2.447)(1.618::5.885))
+                (IOPATH CLK PATTERNDETECT (0.736::2.447)(1.618::5.885))
+            )
+        )
+    )
+    (CELL
+        (CELLTYPE "DSP48E1DREG_1_A_ADREG_0_DREG_0_MREG_0_PREG_0_USE_DPORT_TRUE_USE_MULT_MULTIPLY")
+        (INSTANCE DSP48E1)
+        (DELAY
+            (ABSOLUTE
+                (IOPATH CLK CARRYCASCOUT (0.705::2.375)(1.531::5.650))
+                (IOPATH CLK MULTSIGNOUT (0.700::2.248)(1.510::5.279))
+                (IOPATH CLK PATTERNBDETECT (0.736::2.447)(1.618::5.885))
+                (IOPATH CLK PATTERNDETECT (0.736::2.447)(1.618::5.885))
+            )
+        )
+    )
 )
--- a/artix7/timings/DSP_R.sdf
+++ b/artix7/timings/DSP_R.sdf
@ -260,13 +260,13 @@
        (INSTANCE DSP48E1)
        (DELAY
            (ABSOLUTE
-                (IOPATH D CARRYCASCOUT (0.596::2.268)(1.345::5.400))
-                (IOPATH D CARRYOUT (0.580::2.133)(1.334::5.046))
-                (IOPATH D MULTSIGNOUT (0.592::2.140)(1.323::5.029))
-                (IOPATH D P (0.587::2.142)(1.346::5.070))
-                (IOPATH D PATTERNBDETECT (0.628::2.339)(1.430::5.636))
-                (IOPATH D PATTERNDETECT (0.628::2.339)(1.430::5.636))
-                (IOPATH D PCOUT (0.580::2.133)(1.334::5.046))
+                (IOPATH A CARRYCASCOUT (0.596::2.268)(1.345::5.400))
+                (IOPATH A CARRYOUT (0.580::2.133)(1.334::5.046))
+                (IOPATH A MULTSIGNOUT (0.592::2.140)(1.323::5.029))
+                (IOPATH A P (0.587::2.142)(1.346::5.070))
+                (IOPATH A PATTERNBDETECT (0.628::2.339)(1.430::5.636))
+                (IOPATH A PATTERNDETECT (0.628::2.339)(1.430::5.636))
+                (IOPATH A PCOUT (0.580::2.133)(1.334::5.046))
            )
        )
    )
@ -275,13 +275,13 @@
        (INSTANCE DSP48E1)
        (DELAY
            (ABSOLUTE
-                (IOPATH D CARRYCASCOUT (0.596::2.268)(1.345::5.400))
-                (IOPATH D CARRYOUT (0.580::2.133)(1.334::5.046))
-                (IOPATH D MULTSIGNOUT (0.592::2.140)(1.323::5.029))
-                (IOPATH D P (0.587::2.142)(1.346::5.070))
-                (IOPATH D PATTERNBDETECT (0.628::2.339)(1.430::5.636))
-                (IOPATH D PATTERNDETECT (0.628::2.339)(1.430::5.636))
-                (IOPATH D PCOUT (0.580::2.133)(1.334::5.046))
+                (IOPATH A CARRYCASCOUT (0.596::2.268)(1.345::5.400))
+                (IOPATH A CARRYOUT (0.580::2.133)(1.334::5.046))
+                (IOPATH A MULTSIGNOUT (0.592::2.140)(1.323::5.029))
+                (IOPATH A P (0.587::2.142)(1.346::5.070))
+                (IOPATH A PATTERNBDETECT (0.628::2.339)(1.430::5.636))
+                (IOPATH A PATTERNDETECT (0.628::2.339)(1.430::5.636))
+                (IOPATH A PCOUT (0.580::2.133)(1.334::5.046))
            )
        )
    )
@ -289,32 +289,32 @@
        (CELLTYPE "DSP48E1_ADREG_0_DREG_0_MREG_0_PREG_1_USE_DPORT_TRUE_USE_MULT_DYNAMIC_USE_PATTERN_DETECT_NO_PATDET")
        (INSTANCE DSP48E1)
        (TIMINGCHECK
-            (HOLD D (posedge CLK) (-4.951::-0.994))
-            (SETUP D (posedge CLK) (0.994::4.951))
+            (HOLD A (posedge CLK) (-4.951::-0.994))
+            (SETUP A (posedge CLK) (0.994::4.951))
        )
    )
    (CELL
        (CELLTYPE "DSP48E1_ADREG_0_DREG_0_MREG_0_PREG_1_USE_DPORT_TRUE_USE_MULT_DYNAMIC_USE_PATTERN_DETECT_PATDET")
        (INSTANCE DSP48E1)
        (TIMINGCHECK
-            (HOLD D (posedge CLK) (-5.342::-1.063))
-            (SETUP D (posedge CLK) (1.063::5.342))
+            (HOLD A (posedge CLK) (-5.342::-1.063))
+            (SETUP A (posedge CLK) (1.063::5.342))
        )
    )
    (CELL
        (CELLTYPE "DSP48E1_ADREG_0_DREG_0_MREG_0_PREG_1_USE_DPORT_TRUE_USE_MULT_MULTIPLY_USE_PATTERN_DETECT_NO_PATDET")
        (INSTANCE DSP48E1)
        (TIMINGCHECK
-            (HOLD D (posedge CLK) (-4.951::-0.994))
-            (SETUP D (posedge CLK) (0.994::4.951))
+            (HOLD A (posedge CLK) (-4.951::-0.994))
+            (SETUP A (posedge CLK) (0.994::4.951))
        )
    )
    (CELL
        (CELLTYPE "DSP48E1_ADREG_0_DREG_0_MREG_0_PREG_1_USE_DPORT_TRUE_USE_MULT_MULTIPLY_USE_PATTERN_DETECT_PATDET")
        (INSTANCE DSP48E1)
        (TIMINGCHECK
-            (HOLD D (posedge CLK) (-5.342::-1.063))
-            (SETUP D (posedge CLK) (1.063::5.342))
+            (HOLD A (posedge CLK) (-5.342::-1.063))
+            (SETUP A (posedge CLK) (1.063::5.342))
        )
    )
    (CELL
@ -1837,12 +1837,8 @@
        (INSTANCE DSP48E1)
        (DELAY
            (ABSOLUTE
-                (IOPATH CLK CARRYCASCOUT (0.705::2.375)(1.531::5.650))
                (IOPATH CLK CARRYOUT (0.688::2.241)(1.522::5.297))
-                (IOPATH CLK MULTSIGNOUT (0.700::2.248)(1.510::5.279))
                (IOPATH CLK P (0.696::2.251)(1.533::5.320))
-                (IOPATH CLK PATTERNBDETECT (0.736::2.447)(1.618::5.885))
-                (IOPATH CLK PATTERNDETECT (0.736::2.447)(1.618::5.885))
                (IOPATH CLK PCOUT (0.717::2.334)(1.575::5.515))
            )
        )
@ -1852,14 +1848,34 @@
        (INSTANCE DSP48E1)
        (DELAY
            (ABSOLUTE
-                (IOPATH CLK CARRYCASCOUT (0.705::2.375)(1.531::5.650))
                (IOPATH CLK CARRYOUT (0.688::2.241)(1.522::5.297))
-                (IOPATH CLK MULTSIGNOUT (0.700::2.248)(1.510::5.279))
                (IOPATH CLK P (0.696::2.251)(1.533::5.320))
-                (IOPATH CLK PATTERNBDETECT (0.736::2.447)(1.618::5.885))
-                (IOPATH CLK PATTERNDETECT (0.736::2.447)(1.618::5.885))
                (IOPATH CLK PCOUT (0.717::2.334)(1.575::5.515))
            )
        )
    )
+    (CELL
+        (CELLTYPE "DSP48E1DREG_1_A_ADREG_0_DREG_0_MREG_0_PREG_0_USE_DPORT_TRUE_USE_MULT_DYNAMIC")
+        (INSTANCE DSP48E1)
+        (DELAY
+            (ABSOLUTE
+                (IOPATH CLK CARRYCASCOUT (0.705::2.375)(1.531::5.650))
+                (IOPATH CLK MULTSIGNOUT (0.700::2.248)(1.510::5.279))
+                (IOPATH CLK PATTERNBDETECT (0.736::2.447)(1.618::5.885))
+                (IOPATH CLK PATTERNDETECT (0.736::2.447)(1.618::5.885))
+            )
+        )
+    )
+    (CELL
+        (CELLTYPE "DSP48E1DREG_1_A_ADREG_0_DREG_0_MREG_0_PREG_0_USE_DPORT_TRUE_USE_MULT_MULTIPLY")
+        (INSTANCE DSP48E1)
+        (DELAY
+            (ABSOLUTE
+                (IOPATH CLK CARRYCASCOUT (0.705::2.375)(1.531::5.650))
+                (IOPATH CLK MULTSIGNOUT (0.700::2.248)(1.510::5.279))
+                (IOPATH CLK PATTERNBDETECT (0.736::2.447)(1.618::5.885))
+                (IOPATH CLK PATTERNDETECT (0.736::2.447)(1.618::5.885))
+            )
+        )
+    )
 )
--- a/artix7/timings/slicel.sdf
+++ b/artix7/timings/slicel.sdf
--- a/artix7/timings/slicem.sdf
+++ b/artix7/timings/slicem.sdf
--- a/kintex7/mask_lioi3.db
+++ b/kintex7/mask_lioi3.db
@ -1,4 +1,5 @@
 bit 25_07
+bit 25_16
 bit 25_20
 bit 25_21
 bit 25_31
--- a/kintex7/mask_lioi3_tbytesrc.db
+++ b/kintex7/mask_lioi3_tbytesrc.db
@ -1,4 +1,5 @@
 bit 25_07
+bit 25_16
 bit 25_20
 bit 25_21
 bit 25_31
--- a/kintex7/mask_lioi3_tbyteterm.db
+++ b/kintex7/mask_lioi3_tbyteterm.db
@ -1,4 +1,5 @@
 bit 25_07
+bit 25_16
 bit 25_20
 bit 25_21
 bit 25_31
--- a/kintex7/mask_rioi3.db
+++ b/kintex7/mask_rioi3.db
@ -1,4 +1,5 @@
 bit 25_07
+bit 25_16
 bit 25_20
 bit 25_21
 bit 25_31
--- a/kintex7/mask_rioi3_tbytesrc.db
+++ b/kintex7/mask_rioi3_tbytesrc.db
@ -1,4 +1,5 @@
 bit 25_07
+bit 25_16
 bit 25_20
 bit 25_21
 bit 25_31
--- a/kintex7/mask_rioi3_tbyteterm.db
+++ b/kintex7/mask_rioi3_tbyteterm.db
@ -1,4 +1,5 @@
 bit 25_07
+bit 25_16
 bit 25_20
 bit 25_21
 bit 25_31
--- a/kintex7/segbits_int_l.origin_info.db
+++ b/kintex7/segbits_int_l.origin_info.db
@ -170,7 +170,7 @@ INT_L.BYP_ALT7.BYP_BOUNCE2 origin:050-pip-seed !22_63 !23_63 !24_63 21_63 25_63
 INT_L.BYP_ALT7.BYP_BOUNCE6 origin:050-pip-seed !22_63 !23_63 !25_63 21_63 24_63
 INT_L.BYP_ALT7.EL1END_S3_0 origin:050-pip-seed !23_63 17_63 22_63 24_63 25_63
 INT_L.BYP_ALT7.FAN_BOUNCE_S3_4 origin:050-pip-seed !23_63 21_63 22_63 24_63 25_63
-INT_L.BYP_ALT7.FAN_BOUNCE_S3_6 origin:050-pip-seed !22_63 21_63 23_63 24_63 25_63
+INT_L.BYP_ALT7.FAN_BOUNCE_S3_6 origin:056-pip-rem !22_63 21_63 23_63 24_63 25_63
 INT_L.BYP_ALT7.LOGIC_OUTS_L3 origin:051-pip-imuxlout-bypalts !22_63 20_63 23_63 24_63 25_63
 INT_L.BYP_ALT7.LOGIC_OUTS_L15 origin:051-pip-imuxlout-bypalts !23_63 20_63 22_63 24_63 25_63
 INT_L.BYP_ALT7.LOGIC_OUTS_L21 origin:051-pip-imuxlout-bypalts !22_63 !23_63 !24_63 20_63 25_63
@ -393,7 +393,7 @@ INT_L.FAN_ALT3.WW2END3 origin:050-pip-seed !22_56 !23_56 !24_56 19_57 25_56
 INT_L.FAN_ALT4.BYP_BOUNCE_N3_3 origin:059-pip-byp-bounce !22_08 !23_08 !24_08 20_08 25_08
 INT_L.FAN_ALT4.BYP_BOUNCE_N3_7 origin:059-pip-byp-bounce !22_08 !23_08 !25_08 20_08 24_08
 INT_L.FAN_ALT4.FAN_BOUNCE2 origin:050-pip-seed !23_08 20_08 22_08 24_08 25_08
-INT_L.FAN_ALT4.FAN_BOUNCE7 origin:056-pip-rem !22_08 20_08 23_08 24_08 25_08
+INT_L.FAN_ALT4.FAN_BOUNCE7 origin:050-pip-seed !22_08 20_08 23_08 24_08 25_08
 INT_L.FAN_ALT4.LOGIC_OUTS_L4 origin:050-pip-seed !23_08 21_08 22_08 24_08 25_08
 INT_L.FAN_ALT4.LOGIC_OUTS_L8 origin:050-pip-seed !22_08 21_08 23_08 24_08 25_08
 INT_L.FAN_ALT4.LOGIC_OUTS_L18 origin:050-pip-seed !22_08 !23_08 !25_08 21_08 24_08
@ -1897,7 +1897,7 @@ INT_L.EE4BEG1.SE6END1 origin:050-pip-seed 03_25 06_24
 INT_L.EE4BEG1.SS2END1 origin:050-pip-seed 03_24 05_27
 INT_L.EE4BEG1.SS6END1 origin:050-pip-seed 05_27 06_24
 INT_L.EE4BEG1.SW2END1 origin:050-pip-seed 02_25 05_27
-INT_L.EE4BEG1.SW6END1 origin:050-pip-seed 05_24 05_27
+INT_L.EE4BEG1.SW6END1 origin:056-pip-rem 05_24 05_27
 INT_L.EE4BEG2.LOGIC_OUTS_L2 origin:050-pip-seed 02_41 04_42
 INT_L.EE4BEG2.LOGIC_OUTS_L6 origin:050-pip-seed 02_41 07_41
 INT_L.EE4BEG2.LOGIC_OUTS_L10 origin:050-pip-seed 03_40 07_41
@ -1917,7 +1917,7 @@ INT_L.EE4BEG2.SE6END2 origin:050-pip-seed 03_41 06_40
 INT_L.EE4BEG2.SS2END2 origin:050-pip-seed 03_40 05_43
 INT_L.EE4BEG2.SS6END2 origin:050-pip-seed 05_43 06_40
 INT_L.EE4BEG2.SW2END2 origin:050-pip-seed 02_41 05_43
-INT_L.EE4BEG2.SW6END2 origin:056-pip-rem 05_40 05_43
+INT_L.EE4BEG2.SW6END2 origin:050-pip-seed 05_40 05_43
 INT_L.EE4BEG3.LOGIC_OUTS_L3 origin:050-pip-seed 02_57 07_57
 INT_L.EE4BEG3.LOGIC_OUTS_L7 origin:050-pip-seed 02_57 04_58
 INT_L.EE4BEG3.LOGIC_OUTS_L11 origin:050-pip-seed 03_56 04_58
@ -2273,7 +2273,7 @@ INT_L.NE6BEG3.NW6END3 origin:050-pip-seed 04_53 06_52
 INT_L.NE6BEG3.SE2END3 origin:050-pip-seed 02_53 05_55
 INT_L.NE6BEG3.SE6END3 origin:050-pip-seed 05_55 06_52
 INT_L.NE6BEG3.WW2END2 origin:050-pip-seed 03_52 04_53
-INT_L.NE6BEG3.WW4END3 origin:050-pip-seed 04_53 05_52
+INT_L.NE6BEG3.WW4END3 origin:056-pip-rem 04_53 05_52
 INT_L.NL1BEG0.LOGIC_OUTS_L1 origin:050-pip-seed 07_16 14_17
 INT_L.NL1BEG0.LOGIC_OUTS_L5 origin:050-pip-seed 11_17 14_17
 INT_L.NL1BEG0.LOGIC_OUTS_L9 origin:050-pip-seed 10_17 13_17
@ -3345,7 +3345,7 @@ INT_L.SW6BEG3.NW2END_S0_0 origin:050-pip-seed 02_61 05_63
 INT_L.SW6BEG3.NW6END_S0_0 origin:050-pip-seed 05_63 06_60
 INT_L.SW6BEG3.WW4END_S0_0 origin:050-pip-seed 05_60 05_63
 INT_L.SW6BEG3.EE2END3 origin:050-pip-seed 03_60 04_61
-INT_L.SW6BEG3.EE4END3 origin:056-pip-rem 04_61 05_60
+INT_L.SW6BEG3.EE4END3 origin:050-pip-seed 04_61 05_60
 INT_L.SW6BEG3.LH0 origin:056-pip-rem 04_62 05_60
 INT_L.SW6BEG3.SE2END3 origin:050-pip-seed 02_61 04_61
 INT_L.SW6BEG3.SE6END3 origin:050-pip-seed 04_61 06_60
@ -3603,7 +3603,7 @@ INT_L.WW4BEG2.LOGIC_OUTS_L20 origin:050-pip-seed 04_34 06_32
 INT_L.WW4BEG2.LVB_L0 origin:056-pip-rem 04_34 05_32
 INT_L.WW4BEG2.LVB_L12 origin:056-pip-rem 05_32 07_33
 INT_L.WW4BEG2.NE2END2 origin:050-pip-seed 02_33 05_35
-INT_L.WW4BEG2.NE6END2 origin:050-pip-seed 05_32 05_35
+INT_L.WW4BEG2.NE6END2 origin:056-pip-rem 05_32 05_35
 INT_L.WW4BEG2.NN2END2 origin:050-pip-seed 03_32 05_35
 INT_L.WW4BEG2.NN6END2 origin:050-pip-seed 05_35 06_32
 INT_L.WW4BEG2.NW2END2 origin:050-pip-seed 02_33 03_33
@ -3623,7 +3623,7 @@ INT_L.WW4BEG3.LOGIC_OUTS_L21 origin:050-pip-seed 06_48 07_49
 INT_L.WW4BEG3.LV_L18 origin:056-pip-rem 05_48 07_49
 INT_L.WW4BEG3.LH0 origin:056-pip-rem 04_50 05_48
 INT_L.WW4BEG3.NE2END3 origin:050-pip-seed 02_49 05_51
-INT_L.WW4BEG3.NE6END3 origin:056-pip-rem 05_48 05_51
+INT_L.WW4BEG3.NE6END3 origin:050-pip-seed 05_48 05_51
 INT_L.WW4BEG3.NN2END3 origin:050-pip-seed 03_48 05_51
 INT_L.WW4BEG3.NN6END3 origin:050-pip-seed 05_51 06_48
 INT_L.WW4BEG3.NW2END3 origin:050-pip-seed 02_49 03_49
--- a/kintex7/segbits_int_r.origin_info.db
+++ b/kintex7/segbits_int_r.origin_info.db
@ -329,7 +329,7 @@ INT_R.FAN_ALT3.WW2END3 origin:050-pip-seed !22_56 !23_56 !24_56 19_57 25_56
 INT_R.FAN_ALT4.BYP_BOUNCE_N3_3 origin:059-pip-byp-bounce !22_08 !23_08 !24_08 20_08 25_08
 INT_R.FAN_ALT4.BYP_BOUNCE_N3_7 origin:059-pip-byp-bounce !22_08 !23_08 !25_08 20_08 24_08
 INT_R.FAN_ALT4.FAN_BOUNCE2 origin:050-pip-seed !23_08 20_08 22_08 24_08 25_08
-INT_R.FAN_ALT4.FAN_BOUNCE7 origin:056-pip-rem !22_08 20_08 23_08 24_08 25_08
+INT_R.FAN_ALT4.FAN_BOUNCE7 origin:050-pip-seed !22_08 20_08 23_08 24_08 25_08
 INT_R.FAN_ALT4.LOGIC_OUTS4 origin:050-pip-seed !23_08 21_08 22_08 24_08 25_08
 INT_R.FAN_ALT4.LOGIC_OUTS8 origin:050-pip-seed !22_08 21_08 23_08 24_08 25_08
 INT_R.FAN_ALT4.LOGIC_OUTS18 origin:050-pip-seed !22_08 !23_08 !25_08 21_08 24_08
@ -685,7 +685,7 @@ INT_R.EE4BEG1.SE6END1 origin:050-pip-seed 03_25 06_24
 INT_R.EE4BEG1.SS2END1 origin:050-pip-seed 03_24 05_27
 INT_R.EE4BEG1.SS6END1 origin:050-pip-seed 05_27 06_24
 INT_R.EE4BEG1.SW2END1 origin:050-pip-seed 02_25 05_27
-INT_R.EE4BEG1.SW6END1 origin:056-pip-rem 05_24 05_27
+INT_R.EE4BEG1.SW6END1 origin:050-pip-seed 05_24 05_27
 INT_R.EE4BEG2.LOGIC_OUTS2 origin:050-pip-seed 02_41 04_42
 INT_R.EE4BEG2.LOGIC_OUTS6 origin:050-pip-seed 02_41 07_41
 INT_R.EE4BEG2.LOGIC_OUTS10 origin:050-pip-seed 03_40 07_41
@ -2273,7 +2273,7 @@ INT_R.NE6BEG3.NW6END3 origin:050-pip-seed 04_53 06_52
 INT_R.NE6BEG3.SE2END3 origin:050-pip-seed 02_53 05_55
 INT_R.NE6BEG3.SE6END3 origin:050-pip-seed 05_55 06_52
 INT_R.NE6BEG3.WW2END2 origin:050-pip-seed 03_52 04_53
-INT_R.NE6BEG3.WW4END3 origin:056-pip-rem 04_53 05_52
+INT_R.NE6BEG3.WW4END3 origin:050-pip-seed 04_53 05_52
 INT_R.NL1BEG0.LOGIC_OUTS1 origin:050-pip-seed 07_16 14_17
 INT_R.NL1BEG0.LOGIC_OUTS5 origin:050-pip-seed 11_17 14_17
 INT_R.NL1BEG0.LOGIC_OUTS9 origin:050-pip-seed 10_17 13_17
@ -3623,7 +3623,7 @@ INT_R.WW4BEG3.LOGIC_OUTS21 origin:050-pip-seed 06_48 07_49
 INT_R.WW4BEG3.LH0 origin:056-pip-rem 04_50 05_48
 INT_R.WW4BEG3.LV18 origin:056-pip-rem 05_48 07_49
 INT_R.WW4BEG3.NE2END3 origin:050-pip-seed 02_49 05_51
-INT_R.WW4BEG3.NE6END3 origin:050-pip-seed 05_48 05_51
+INT_R.WW4BEG3.NE6END3 origin:056-pip-rem 05_48 05_51
 INT_R.WW4BEG3.NN2END3 origin:050-pip-seed 03_48 05_51
 INT_R.WW4BEG3.NN6END3 origin:050-pip-seed 05_51 06_48
 INT_R.WW4BEG3.NW2END3 origin:050-pip-seed 02_49 03_49
--- a/zynq7/mask_lioi3.db
+++ b/zynq7/mask_lioi3.db
@ -21,7 +21,6 @@ bit 25_95
 bit 25_96
 bit 25_98
 bit 25_99
-bit 25_111
 bit 25_112
 bit 25_115
 bit 25_116
--- a/zynq7/mask_lioi3_tbytesrc.db
+++ b/zynq7/mask_lioi3_tbytesrc.db
@ -21,7 +21,6 @@ bit 25_95
 bit 25_96
 bit 25_98
 bit 25_99
-bit 25_111
 bit 25_112
 bit 25_115
 bit 25_116
--- a/zynq7/mask_lioi3_tbyteterm.db
+++ b/zynq7/mask_lioi3_tbyteterm.db
@ -21,7 +21,6 @@ bit 25_95
 bit 25_96
 bit 25_98
 bit 25_99
-bit 25_111
 bit 25_112
 bit 25_115
 bit 25_116
--- a/zynq7/mask_rioi3.db
+++ b/zynq7/mask_rioi3.db
@ -21,7 +21,6 @@ bit 25_95
 bit 25_96
 bit 25_98
 bit 25_99
-bit 25_111
 bit 25_112
 bit 25_115
 bit 25_116
--- a/zynq7/mask_rioi3_tbytesrc.db
+++ b/zynq7/mask_rioi3_tbytesrc.db
@ -21,7 +21,6 @@ bit 25_95
 bit 25_96
 bit 25_98
 bit 25_99
-bit 25_111
 bit 25_112
 bit 25_115
 bit 25_116
--- a/zynq7/mask_rioi3_tbyteterm.db
+++ b/zynq7/mask_rioi3_tbyteterm.db
@ -21,7 +21,6 @@ bit 25_95
 bit 25_96
 bit 25_98
 bit 25_99
-bit 25_111
 bit 25_112
 bit 25_115
 bit 25_116
--- a/zynq7/segbits_int_l.origin_info.db
+++ b/zynq7/segbits_int_l.origin_info.db
@ -170,7 +170,7 @@ INT_L.BYP_ALT7.BYP_BOUNCE2 origin:050-pip-seed !22_63 !23_63 !24_63 21_63 25_63
 INT_L.BYP_ALT7.BYP_BOUNCE6 origin:050-pip-seed !22_63 !23_63 !25_63 21_63 24_63
 INT_L.BYP_ALT7.EL1END_S3_0 origin:050-pip-seed !23_63 17_63 22_63 24_63 25_63
 INT_L.BYP_ALT7.FAN_BOUNCE_S3_4 origin:050-pip-seed !23_63 21_63 22_63 24_63 25_63
-INT_L.BYP_ALT7.FAN_BOUNCE_S3_6 origin:050-pip-seed !22_63 21_63 23_63 24_63 25_63
+INT_L.BYP_ALT7.FAN_BOUNCE_S3_6 origin:056-pip-rem !22_63 21_63 23_63 24_63 25_63
 INT_L.BYP_ALT7.LOGIC_OUTS_L3 origin:051-pip-imuxlout-bypalts !22_63 20_63 23_63 24_63 25_63
 INT_L.BYP_ALT7.LOGIC_OUTS_L15 origin:051-pip-imuxlout-bypalts !23_63 20_63 22_63 24_63 25_63
 INT_L.BYP_ALT7.LOGIC_OUTS_L21 origin:051-pip-imuxlout-bypalts !22_63 !23_63 !24_63 20_63 25_63
@ -2273,7 +2273,7 @@ INT_L.NE6BEG3.NW6END3 origin:050-pip-seed 04_53 06_52
 INT_L.NE6BEG3.SE2END3 origin:050-pip-seed 02_53 05_55
 INT_L.NE6BEG3.SE6END3 origin:050-pip-seed 05_55 06_52
 INT_L.NE6BEG3.WW2END2 origin:050-pip-seed 03_52 04_53
-INT_L.NE6BEG3.WW4END3 origin:050-pip-seed 04_53 05_52
+INT_L.NE6BEG3.WW4END3 origin:056-pip-rem 04_53 05_52
 INT_L.NL1BEG0.LOGIC_OUTS_L1 origin:050-pip-seed 07_16 14_17
 INT_L.NL1BEG0.LOGIC_OUTS_L5 origin:050-pip-seed 11_17 14_17
 INT_L.NL1BEG0.LOGIC_OUTS_L9 origin:050-pip-seed 10_17 13_17
@ -2662,7 +2662,7 @@ INT_L.NW6BEG0.LOGIC_OUTS_L18 origin:050-pip-seed 05_01 07_03
 INT_L.NW6BEG0.LOGIC_OUTS_L22 origin:050-pip-seed 06_02 07_03
 INT_L.NW6BEG0.LV_L0 origin:056-pip-rem 04_03 06_02
 INT_L.NW6BEG0.SS2END_N0_3 origin:050-pip-seed 02_03 04_00
-INT_L.NW6BEG0.SS6END_N0_3 origin:050-pip-seed 04_00 07_03
+INT_L.NW6BEG0.SS6END_N0_3 origin:056-pip-rem 04_00 07_03
 INT_L.NW6BEG0.SW2END_N0_3 origin:050-pip-seed 03_02 04_00
 INT_L.NW6BEG0.SW6END_N0_3 origin:050-pip-seed 04_00 04_03
 INT_L.NW6BEG0.WW2END_N0_3 origin:050-pip-seed 02_02 02_03
@ -2729,7 +2729,7 @@ INT_L.NW6BEG3.NN6END3 origin:050-pip-seed 05_50 07_51
 INT_L.NW6BEG3.NW2END3 origin:050-pip-seed 02_50 03_50
 INT_L.NW6BEG3.NW6END3 origin:050-pip-seed 02_50 07_51
 INT_L.NW6BEG3.SS2END2 origin:050-pip-seed 02_51 04_48
-INT_L.NW6BEG3.SS6END2 origin:050-pip-seed 04_48 07_51
+INT_L.NW6BEG3.SS6END2 origin:056-pip-rem 04_48 07_51
 INT_L.NW6BEG3.SW2END2 origin:050-pip-seed 03_50 04_48
 INT_L.NW6BEG3.SW6END2 origin:050-pip-seed 04_48 04_51
 INT_L.NW6BEG3.WW2END2 origin:050-pip-seed 02_50 02_51
@ -2887,7 +2887,7 @@ INT_L.SE6BEG3.LH0 origin:056-pip-rem 04_59 06_58
 INT_L.SE6BEG3.NE2END3 origin:050-pip-seed 03_58 04_56
 INT_L.SE6BEG3.NE6END3 origin:050-pip-seed 04_56 04_59
 INT_L.SE6BEG3.NN2END3 origin:050-pip-seed 02_59 04_56
-INT_L.SE6BEG3.NN6END3 origin:050-pip-seed 04_56 07_59
+INT_L.SE6BEG3.NN6END3 origin:056-pip-rem 04_56 07_59
 INT_L.SE6BEG3.SE2END3 origin:050-pip-seed 02_58 03_58
 INT_L.SE6BEG3.SE6END3 origin:050-pip-seed 02_58 07_59
 INT_L.SE6BEG3.SS2END3 origin:050-pip-seed 02_59 05_58
@ -3323,7 +3323,7 @@ INT_L.SW6BEG2.LOGIC_OUTS_L20 origin:050-pip-seed 06_44 07_45
 INT_L.SW6BEG2.LVB_L0 origin:056-pip-rem 04_46 05_44
 INT_L.SW6BEG2.LVB_L12 origin:056-pip-rem 05_44 07_45
 INT_L.SW6BEG2.EE2END2 origin:050-pip-seed 03_44 04_45
-INT_L.SW6BEG2.EE4END2 origin:050-pip-seed 04_45 05_44
+INT_L.SW6BEG2.EE4END2 origin:056-pip-rem 04_45 05_44
 INT_L.SW6BEG2.NW2END3 origin:050-pip-seed 02_45 05_47
 INT_L.SW6BEG2.NW6END3 origin:050-pip-seed 05_47 06_44
 INT_L.SW6BEG2.SE2END2 origin:050-pip-seed 02_45 04_45
@ -3345,7 +3345,7 @@ INT_L.SW6BEG3.NW2END_S0_0 origin:050-pip-seed 02_61 05_63
 INT_L.SW6BEG3.NW6END_S0_0 origin:050-pip-seed 05_63 06_60
 INT_L.SW6BEG3.WW4END_S0_0 origin:050-pip-seed 05_60 05_63
 INT_L.SW6BEG3.EE2END3 origin:050-pip-seed 03_60 04_61
-INT_L.SW6BEG3.EE4END3 origin:050-pip-seed 04_61 05_60
+INT_L.SW6BEG3.EE4END3 origin:056-pip-rem 04_61 05_60
 INT_L.SW6BEG3.LH0 origin:056-pip-rem 04_62 05_60
 INT_L.SW6BEG3.SE2END3 origin:050-pip-seed 02_61 04_61
 INT_L.SW6BEG3.SE6END3 origin:050-pip-seed 04_61 06_60
@ -3603,7 +3603,7 @@ INT_L.WW4BEG2.LOGIC_OUTS_L20 origin:050-pip-seed 04_34 06_32
 INT_L.WW4BEG2.LVB_L0 origin:056-pip-rem 04_34 05_32
 INT_L.WW4BEG2.LVB_L12 origin:056-pip-rem 05_32 07_33
 INT_L.WW4BEG2.NE2END2 origin:050-pip-seed 02_33 05_35
-INT_L.WW4BEG2.NE6END2 origin:050-pip-seed 05_32 05_35
+INT_L.WW4BEG2.NE6END2 origin:056-pip-rem 05_32 05_35
 INT_L.WW4BEG2.NN2END2 origin:050-pip-seed 03_32 05_35
 INT_L.WW4BEG2.NN6END2 origin:050-pip-seed 05_35 06_32
 INT_L.WW4BEG2.NW2END2 origin:050-pip-seed 02_33 03_33
--- a/zynq7/segbits_int_r.origin_info.db
+++ b/zynq7/segbits_int_r.origin_info.db
@ -705,7 +705,7 @@ INT_R.EE4BEG2.SE6END2 origin:050-pip-seed 03_41 06_40
 INT_R.EE4BEG2.SS2END2 origin:050-pip-seed 03_40 05_43
 INT_R.EE4BEG2.SS6END2 origin:050-pip-seed 05_43 06_40
 INT_R.EE4BEG2.SW2END2 origin:050-pip-seed 02_41 05_43
-INT_R.EE4BEG2.SW6END2 origin:050-pip-seed 05_40 05_43
+INT_R.EE4BEG2.SW6END2 origin:056-pip-rem 05_40 05_43
 INT_R.EE4BEG3.LOGIC_OUTS3 origin:050-pip-seed 02_57 07_57
 INT_R.EE4BEG3.LOGIC_OUTS7 origin:050-pip-seed 02_57 04_58
 INT_R.EE4BEG3.LOGIC_OUTS11 origin:050-pip-seed 03_56 04_58
@ -725,7 +725,7 @@ INT_R.EE4BEG3.SE6END3 origin:050-pip-seed 03_57 06_56
 INT_R.EE4BEG3.SS2END3 origin:050-pip-seed 03_56 05_59
 INT_R.EE4BEG3.SS6END3 origin:050-pip-seed 05_59 06_56
 INT_R.EE4BEG3.SW2END3 origin:050-pip-seed 02_57 05_59
-INT_R.EE4BEG3.SW6END3 origin:050-pip-seed 05_56 05_59
+INT_R.EE4BEG3.SW6END3 origin:056-pip-rem 05_56 05_59
 INT_R.EL1BEG0.LOGIC_OUTS1 origin:050-pip-seed 07_20 14_21
 INT_R.EL1BEG0.LOGIC_OUTS5 origin:050-pip-seed 11_21 14_21
 INT_R.EL1BEG0.LOGIC_OUTS9 origin:050-pip-seed 10_21 13_21
@ -2273,7 +2273,7 @@ INT_R.NE6BEG3.NW6END3 origin:050-pip-seed 04_53 06_52
 INT_R.NE6BEG3.SE2END3 origin:050-pip-seed 02_53 05_55
 INT_R.NE6BEG3.SE6END3 origin:050-pip-seed 05_55 06_52
 INT_R.NE6BEG3.WW2END2 origin:050-pip-seed 03_52 04_53
-INT_R.NE6BEG3.WW4END3 origin:050-pip-seed 04_53 05_52
+INT_R.NE6BEG3.WW4END3 origin:056-pip-rem 04_53 05_52
 INT_R.NL1BEG0.LOGIC_OUTS1 origin:050-pip-seed 07_16 14_17
 INT_R.NL1BEG0.LOGIC_OUTS5 origin:050-pip-seed 11_17 14_17
 INT_R.NL1BEG0.LOGIC_OUTS9 origin:050-pip-seed 10_17 13_17
@ -2471,7 +2471,7 @@ INT_R.NN6BEG2.NN6END2 origin:050-pip-seed 02_38 07_39
 INT_R.NN6BEG2.NW2END2 origin:050-pip-seed 03_38 04_36
 INT_R.NN6BEG2.NW6END2 origin:050-pip-seed 04_36 07_39
 INT_R.NN6BEG2.SE2END2 origin:050-pip-seed 03_38 05_38
-INT_R.NN6BEG2.SE6END2 origin:050-pip-seed 05_38 07_39
+INT_R.NN6BEG2.SE6END2 origin:056-pip-rem 05_38 07_39
 INT_R.NN6BEG2.WW2END1 origin:050-pip-seed 02_39 04_36
 INT_R.NN6BEG2.WW4END2 origin:050-pip-seed 04_36 04_39
 INT_R.NN6BEG3.LOGIC_OUTS3 origin:050-pip-seed 03_54 06_54
@ -3321,7 +3321,7 @@ INT_R.SW6BEG2.LOGIC_OUTS14 origin:050-pip-seed 03_44 07_45
 INT_R.SW6BEG2.LOGIC_OUTS16 origin:050-pip-seed 04_46 06_44
 INT_R.SW6BEG2.LOGIC_OUTS20 origin:050-pip-seed 06_44 07_45
 INT_R.SW6BEG2.EE2END2 origin:050-pip-seed 03_44 04_45
-INT_R.SW6BEG2.EE4END2 origin:050-pip-seed 04_45 05_44
+INT_R.SW6BEG2.EE4END2 origin:056-pip-rem 04_45 05_44
 INT_R.SW6BEG2.LVB0 origin:056-pip-rem 04_46 05_44
 INT_R.SW6BEG2.LVB12 origin:056-pip-rem 05_44 07_45
 INT_R.SW6BEG2.NW2END3 origin:050-pip-seed 02_45 05_47
@ -3603,7 +3603,7 @@ INT_R.WW4BEG2.LOGIC_OUTS20 origin:050-pip-seed 04_34 06_32
 INT_R.WW4BEG2.LVB0 origin:056-pip-rem 04_34 05_32
 INT_R.WW4BEG2.LVB12 origin:056-pip-rem 05_32 07_33
 INT_R.WW4BEG2.NE2END2 origin:050-pip-seed 02_33 05_35
-INT_R.WW4BEG2.NE6END2 origin:050-pip-seed 05_32 05_35
+INT_R.WW4BEG2.NE6END2 origin:056-pip-rem 05_32 05_35
 INT_R.WW4BEG2.NN2END2 origin:050-pip-seed 03_32 05_35
 INT_R.WW4BEG2.NN6END2 origin:050-pip-seed 05_35 06_32
 INT_R.WW4BEG2.NW2END2 origin:050-pip-seed 02_33 03_33
--- a/zynq7/timings/DSP_L.sdf
+++ b/zynq7/timings/DSP_L.sdf
@ -1837,12 +1837,8 @@
        (INSTANCE DSP48E1)
        (DELAY
            (ABSOLUTE
-                (IOPATH CLK CARRYCASCOUT (0.705::2.375)(1.531::5.650))
                (IOPATH CLK CARRYOUT (0.688::2.241)(1.522::5.297))
-                (IOPATH CLK MULTSIGNOUT (0.700::2.248)(1.510::5.279))
                (IOPATH CLK P (0.696::2.251)(1.533::5.320))
-                (IOPATH CLK PATTERNBDETECT (0.736::2.447)(1.618::5.885))
-                (IOPATH CLK PATTERNDETECT (0.736::2.447)(1.618::5.885))
                (IOPATH CLK PCOUT (0.717::2.334)(1.575::5.515))
            )
        )
@ -1852,14 +1848,34 @@
        (INSTANCE DSP48E1)
        (DELAY
            (ABSOLUTE
-                (IOPATH CLK CARRYCASCOUT (0.705::2.375)(1.531::5.650))
                (IOPATH CLK CARRYOUT (0.688::2.241)(1.522::5.297))
-                (IOPATH CLK MULTSIGNOUT (0.700::2.248)(1.510::5.279))
                (IOPATH CLK P (0.696::2.251)(1.533::5.320))
-                (IOPATH CLK PATTERNBDETECT (0.736::2.447)(1.618::5.885))
-                (IOPATH CLK PATTERNDETECT (0.736::2.447)(1.618::5.885))
                (IOPATH CLK PCOUT (0.717::2.334)(1.575::5.515))
            )
        )
    )
+    (CELL
+        (CELLTYPE "DSP48E1DREG_1_A_ADREG_0_DREG_0_MREG_0_PREG_0_USE_DPORT_TRUE_USE_MULT_DYNAMIC")
+        (INSTANCE DSP48E1)
+        (DELAY
+            (ABSOLUTE
+                (IOPATH CLK CARRYCASCOUT (0.705::2.375)(1.531::5.650))
+                (IOPATH CLK MULTSIGNOUT (0.700::2.248)(1.510::5.279))
+                (IOPATH CLK PATTERNBDETECT (0.736::2.447)(1.618::5.885))
+                (IOPATH CLK PATTERNDETECT (0.736::2.447)(1.618::5.885))
+            )
+        )
+    )
+    (CELL
+        (CELLTYPE "DSP48E1DREG_1_A_ADREG_0_DREG_0_MREG_0_PREG_0_USE_DPORT_TRUE_USE_MULT_MULTIPLY")
+        (INSTANCE DSP48E1)
+        (DELAY
+            (ABSOLUTE
+                (IOPATH CLK CARRYCASCOUT (0.705::2.375)(1.531::5.650))
+                (IOPATH CLK MULTSIGNOUT (0.700::2.248)(1.510::5.279))
+                (IOPATH CLK PATTERNBDETECT (0.736::2.447)(1.618::5.885))
+                (IOPATH CLK PATTERNDETECT (0.736::2.447)(1.618::5.885))
+            )
+        )
+    )
 )
--- a/zynq7/timings/DSP_R.sdf
+++ b/zynq7/timings/DSP_R.sdf
@ -1837,12 +1837,8 @@
        (INSTANCE DSP48E1)
        (DELAY
            (ABSOLUTE
-                (IOPATH CLK CARRYCASCOUT (0.705::2.375)(1.531::5.650))
                (IOPATH CLK CARRYOUT (0.688::2.241)(1.522::5.297))
-                (IOPATH CLK MULTSIGNOUT (0.700::2.248)(1.510::5.279))
                (IOPATH CLK P (0.696::2.251)(1.533::5.320))
-                (IOPATH CLK PATTERNBDETECT (0.736::2.447)(1.618::5.885))
-                (IOPATH CLK PATTERNDETECT (0.736::2.447)(1.618::5.885))
                (IOPATH CLK PCOUT (0.717::2.334)(1.575::5.515))
            )
        )
@ -1852,14 +1848,34 @@
        (INSTANCE DSP48E1)
        (DELAY
            (ABSOLUTE
-                (IOPATH CLK CARRYCASCOUT (0.705::2.375)(1.531::5.650))
                (IOPATH CLK CARRYOUT (0.688::2.241)(1.522::5.297))
-                (IOPATH CLK MULTSIGNOUT (0.700::2.248)(1.510::5.279))
                (IOPATH CLK P (0.696::2.251)(1.533::5.320))
-                (IOPATH CLK PATTERNBDETECT (0.736::2.447)(1.618::5.885))
-                (IOPATH CLK PATTERNDETECT (0.736::2.447)(1.618::5.885))
                (IOPATH CLK PCOUT (0.717::2.334)(1.575::5.515))
            )
        )
    )
+    (CELL
+        (CELLTYPE "DSP48E1DREG_1_A_ADREG_0_DREG_0_MREG_0_PREG_0_USE_DPORT_TRUE_USE_MULT_DYNAMIC")
+        (INSTANCE DSP48E1)
+        (DELAY
+            (ABSOLUTE
+                (IOPATH CLK CARRYCASCOUT (0.705::2.375)(1.531::5.650))
+                (IOPATH CLK MULTSIGNOUT (0.700::2.248)(1.510::5.279))
+                (IOPATH CLK PATTERNBDETECT (0.736::2.447)(1.618::5.885))
+                (IOPATH CLK PATTERNDETECT (0.736::2.447)(1.618::5.885))
+            )
+        )
+    )
+    (CELL
+        (CELLTYPE "DSP48E1DREG_1_A_ADREG_0_DREG_0_MREG_0_PREG_0_USE_DPORT_TRUE_USE_MULT_MULTIPLY")
+        (INSTANCE DSP48E1)
+        (DELAY
+            (ABSOLUTE
+                (IOPATH CLK CARRYCASCOUT (0.705::2.375)(1.531::5.650))
+                (IOPATH CLK MULTSIGNOUT (0.700::2.248)(1.510::5.279))
+                (IOPATH CLK PATTERNBDETECT (0.736::2.447)(1.618::5.885))
+                (IOPATH CLK PATTERNDETECT (0.736::2.447)(1.618::5.885))
+            )
+        )
+    )
 )
--- a/zynq7/timings/slicel.sdf
+++ b/zynq7/timings/slicel.sdf
--- a/zynq7/timings/slicem.sdf
+++ b/zynq7/timings/slicem.sdf