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Add UART to Basys3 harness. 

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
This commit is contained in:
Keith Rothman 2019-01-09 12:59:30 -08:00 committed by Tim 'mithro' Ansell
parent aa178c3e2f
commit e396cb3cc2
4 changed files with 3000 additions and 51 deletions
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artix7/harness/basys3/swbut/design.bit
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artix7/harness/basys3/swbut/design.dcp
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artix7/harness/basys3/swbut/design.json
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artix7/harness/basys3/swbut/design.txt
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@ -1,18 +1,36 @@
name node pin wire
clk CLK_HROW_TOP_R_X60Y130/CLK_HROW_CK_BUFHCLK_L0 W5 HCLK_VBRK_X34Y130/HCLK_VBRK_CK_BUFHCLK0
din[0] INT_R_X9Y102/NE2BEG3 V17 VBRK_X29Y108/VBRK_NE2A3
din[1] INT_R_X9Y105/NE2BEG3 V16 VBRK_X29Y111/VBRK_NE2A3
din[2] INT_R_X9Y108/NE2BEG3 W16 VBRK_X29Y114/VBRK_NE2A3
din[3] INT_R_X9Y111/NE2BEG3 W17 VBRK_X29Y117/VBRK_NE2A3
din[4] INT_R_X9Y114/NE2BEG3 W15 VBRK_X29Y120/VBRK_NE2A3
din[5] INT_R_X9Y117/NE2BEG3 V15 VBRK_X29Y123/VBRK_NE2A3
din[6] INT_R_X9Y120/NE2BEG3 W14 VBRK_X29Y126/VBRK_NE2A3
din[7] INT_R_X9Y123/NE2BEG3 W13 VBRK_X29Y129/VBRK_NE2A3
dout[0] INT_L_X10Y125/SW6BEG0 U16 VBRK_X29Y131/VBRK_SW4A0
dout[1] INT_L_X10Y128/SW6BEG0 E19 VBRK_X29Y134/VBRK_SW4A0
dout[2] INT_L_X10Y131/SW6BEG0 U19 VBRK_X29Y137/VBRK_SW4A0
dout[3] INT_L_X10Y134/SW6BEG0 V19 VBRK_X29Y140/VBRK_SW4A0
dout[4] INT_L_X10Y137/SW6BEG0 W18 VBRK_X29Y143/VBRK_SW4A0
dout[5] INT_L_X10Y140/SW6BEG0 U15 VBRK_X29Y146/VBRK_SW4A0
dout[6] INT_L_X10Y143/SW6BEG0 U14 VBRK_X29Y149/VBRK_SW4A0
dout[7] INT_L_X10Y146/SW6BEG0 V14 VBRK_X29Y152/VBRK_SW4A0
din[0] INT_L_X0Y102/EE2BEG2 V17 VBRK_X9Y107/VBRK_EE2A2
din[1] INT_L_X0Y104/EE2BEG2 V16 VBRK_X9Y109/VBRK_EE2A2
din[2] INT_L_X0Y106/EE2BEG2 W16 VBRK_X9Y111/VBRK_EE2A2
din[3] INT_L_X0Y108/EE2BEG2 W17 VBRK_X9Y113/VBRK_EE2A2
din[4] INT_L_X0Y110/EE2BEG2 W15 VBRK_X9Y115/VBRK_EE2A2
din[5] INT_L_X0Y112/EE2BEG2 V15 VBRK_X9Y117/VBRK_EE2A2
din[6] INT_L_X0Y114/EE2BEG2 W14 VBRK_X9Y119/VBRK_EE2A2
din[7] INT_L_X0Y116/EE2BEG2 W13 VBRK_X9Y121/VBRK_EE2A2
din[8] INT_R_X25Y126/WW2BEG1 V2 VBRK_X61Y132/VBRK_WW2END1
din[9] INT_R_X25Y128/WW2BEG1 T3 VBRK_X61Y134/VBRK_WW2END1
din[10] INT_R_X25Y130/WW2BEG1 T2 VBRK_X61Y136/VBRK_WW2END1
din[11] INT_R_X25Y132/WW2BEG1 R3 VBRK_X61Y138/VBRK_WW2END1
din[12] INT_R_X25Y134/WW2BEG1 W2 VBRK_X61Y140/VBRK_WW2END1
din[13] INT_R_X25Y136/WW2BEG1 U1 VBRK_X61Y142/VBRK_WW2END1
din[14] INT_R_X25Y138/WW2BEG1 T1 VBRK_X61Y144/VBRK_WW2END1
din[15] INT_R_X25Y140/WW2BEG1 R2 VBRK_X61Y146/VBRK_WW2END1
din[16] INT_L_X0Y118/EE2BEG2 B18 VBRK_X9Y123/VBRK_EE2A2
dout[0] INT_L_X2Y115/SW6BEG0 U16 VBRK_X9Y120/VBRK_SW4A0
dout[1] INT_L_X2Y117/SW6BEG0 E19 VBRK_X9Y122/VBRK_SW4A0
dout[2] INT_L_X2Y119/SW6BEG0 U19 VBRK_X9Y124/VBRK_SW4A0
dout[3] INT_L_X2Y121/SW6BEG0 V19 VBRK_X9Y126/VBRK_SW4A0
dout[4] INT_L_X2Y123/SW6BEG0 W18 VBRK_X9Y128/VBRK_SW4A0
dout[5] INT_L_X2Y125/SW6BEG0 U15 VBRK_X9Y131/VBRK_SW4A0
dout[6] INT_L_X2Y127/SW6BEG0 U14 VBRK_X9Y133/VBRK_SW4A0
dout[7] INT_L_X2Y129/SW6BEG0 V14 VBRK_X9Y135/VBRK_SW4A0
dout[8] INT_L_X2Y131/SW6BEG0 V13 VBRK_X9Y137/VBRK_SW4A0
dout[9] INT_R_X23Y115/LH12 V3 VBRK_X61Y120/VBRK_LH12
dout[10] INT_R_X23Y117/LH12 W3 VBRK_X61Y122/VBRK_LH12
dout[11] INT_R_X23Y119/LH12 U3 VBRK_X61Y124/VBRK_LH12
dout[12] INT_R_X23Y121/LH12 P3 VBRK_X61Y126/VBRK_LH12
dout[13] INT_R_X23Y123/LH12 N3 VBRK_X61Y128/VBRK_LH12
dout[14] INT_R_X23Y125/LH12 P1 VBRK_X61Y131/VBRK_LH12
dout[15] INT_R_X23Y127/LH12 L1 VBRK_X61Y133/VBRK_LH12
dout[16] INT_L_X2Y133/SW6BEG0 A18 VBRK_X9Y139/VBRK_SW4A0