diff --git a/artix7/harness/basys3/swbut/design.bit b/artix7/harness/basys3/swbut/design.bit index 6867d81..a06e67c 100644 Binary files a/artix7/harness/basys3/swbut/design.bit and b/artix7/harness/basys3/swbut/design.bit differ diff --git a/artix7/harness/basys3/swbut/design.dcp b/artix7/harness/basys3/swbut/design.dcp index cdd6a2b..19cf84d 100644 Binary files a/artix7/harness/basys3/swbut/design.dcp and b/artix7/harness/basys3/swbut/design.dcp differ diff --git a/artix7/harness/basys3/swbut/design.json b/artix7/harness/basys3/swbut/design.json index 37f536c..c7338b4 100644 --- a/artix7/harness/basys3/swbut/design.json +++ b/artix7/harness/basys3/swbut/design.json @@ -1,7 +1,7 @@ { "info": { - "GRID_X_MAX": 47, - "GRID_X_MIN": 18, + "GRID_X_MAX": 58, + "GRID_X_MIN": 9, "GRID_Y_MAX": 52, "GRID_Y_MIN": 0 }, @@ -14,99 +14,3030 @@ }, { "name": "din[0]", - "node": "INT_R_X9Y102/NE2BEG3", + "node": "INT_L_X0Y102/EE2BEG2", "pin": "V17", - "wire": "VBRK_X29Y108/VBRK_NE2A3" + "wire": "VBRK_X9Y107/VBRK_EE2A2", + "wires_outside_roi": [ + "BRKH_INT_X0Y49/BRKH_INT_L_LV1", + "BRKH_INT_X0Y99/BRKH_INT_NN6C2", + "CMT_FIFO_R_X7Y112/CMT_FIFO_EE2A2_1", + "CMT_TOP_R_LOWER_B_X8Y113/CMT_TOP_EE2A2_2", + "HCLK_L_X4Y26/HCLK_LV12", + "HCLK_L_X4Y78/HCLK_LV8", + "INT_INTERFACE_R_X1Y102/INT_INTERFACE_EE2A2", + "INT_L_X0Y100/NN6D2", + "INT_L_X0Y101/NN6E2", + "INT_L_X0Y102/EE2BEG2", + "INT_L_X0Y102/NN6END2", + "INT_L_X0Y11/LOGIC_OUTS_L18", + "INT_L_X0Y11/NR1BEG0", + "INT_L_X0Y12/LV_L0", + "INT_L_X0Y12/NR1END0", + "INT_L_X0Y13/LV_L1", + "INT_L_X0Y14/LV_L2", + "INT_L_X0Y15/LV_L3", + "INT_L_X0Y16/LV_L4", + "INT_L_X0Y17/LV_L5", + "INT_L_X0Y18/LV_L6", + "INT_L_X0Y19/LV_L7", + "INT_L_X0Y20/LV_L8", + "INT_L_X0Y21/LV_L9", + "INT_L_X0Y22/LV_L10", + "INT_L_X0Y23/LV_L11", + "INT_L_X0Y24/LV_L12", + "INT_L_X0Y25/LV_L13", + "INT_L_X0Y26/LV_L14", + "INT_L_X0Y27/LV_L15", + "INT_L_X0Y28/LV_L16", + "INT_L_X0Y29/LV_L17", + "INT_L_X0Y30/LV_L0", + "INT_L_X0Y30/LV_L18", + "INT_L_X0Y31/LV_L1", + "INT_L_X0Y32/LV_L2", + "INT_L_X0Y33/LV_L3", + "INT_L_X0Y34/LV_L4", + "INT_L_X0Y35/LV_L5", + "INT_L_X0Y36/LV_L6", + "INT_L_X0Y37/LV_L7", + "INT_L_X0Y38/LV_L8", + "INT_L_X0Y39/LV_L9", + "INT_L_X0Y40/LV_L10", + "INT_L_X0Y41/LV_L11", + "INT_L_X0Y42/LV_L12", + "INT_L_X0Y43/LV_L13", + "INT_L_X0Y44/LV_L14", + "INT_L_X0Y45/LV_L15", + "INT_L_X0Y46/LV_L16", + "INT_L_X0Y47/LV_L17", + "INT_L_X0Y48/LV_L0", + "INT_L_X0Y48/LV_L18", + "INT_L_X0Y49/LV_L1", + "INT_L_X0Y50/LV_L2", + "INT_L_X0Y51/LV_L3", + "INT_L_X0Y52/LV_L4", + "INT_L_X0Y53/LV_L5", + "INT_L_X0Y54/LV_L6", + "INT_L_X0Y55/LV_L7", + "INT_L_X0Y56/LV_L8", + "INT_L_X0Y57/LV_L9", + "INT_L_X0Y58/LV_L10", + "INT_L_X0Y59/LV_L11", + "INT_L_X0Y60/LV_L12", + "INT_L_X0Y61/LV_L13", + "INT_L_X0Y62/LV_L14", + "INT_L_X0Y63/LV_L15", + "INT_L_X0Y64/LV_L16", + "INT_L_X0Y65/LV_L17", + "INT_L_X0Y66/LV_L0", + "INT_L_X0Y66/LV_L18", + "INT_L_X0Y67/LV_L1", + "INT_L_X0Y68/LV_L2", + "INT_L_X0Y69/LV_L3", + "INT_L_X0Y70/LV_L4", + "INT_L_X0Y71/LV_L5", + "INT_L_X0Y72/LV_L6", + "INT_L_X0Y73/LV_L7", + "INT_L_X0Y74/LV_L8", + "INT_L_X0Y75/LV_L9", + "INT_L_X0Y76/LV_L10", + "INT_L_X0Y77/LV_L11", + "INT_L_X0Y78/LV_L12", + "INT_L_X0Y79/LV_L13", + "INT_L_X0Y80/LV_L14", + "INT_L_X0Y81/LV_L15", + "INT_L_X0Y82/LV_L16", + "INT_L_X0Y83/LV_L17", + "INT_L_X0Y84/LVB_L0", + "INT_L_X0Y84/LV_L18", + "INT_L_X0Y85/LVB_L1", + "INT_L_X0Y86/LVB_L2", + "INT_L_X0Y87/LVB_L3", + "INT_L_X0Y88/LVB_L4", + "INT_L_X0Y89/LVB_L5", + "INT_L_X0Y90/LVB_L6", + "INT_L_X0Y91/LVB_L7", + "INT_L_X0Y92/LVB_L8", + "INT_L_X0Y93/LVB_L9", + "INT_L_X0Y94/LVB_L10", + "INT_L_X0Y95/LVB_L11", + "INT_L_X0Y96/LVB_L12", + "INT_L_X0Y96/NN6BEG2", + "INT_L_X0Y97/NN6A2", + "INT_L_X0Y98/NN6B2", + "INT_L_X0Y99/NN6C2", + "INT_R_X1Y102/EE2A2", + "IO_INT_INTERFACE_L_X0Y11/INT_INTERFACE_LOGIC_OUTS_L18", + "IO_INT_INTERFACE_L_X0Y11/INT_INTERFACE_LOGIC_OUTS_L_B18", + "LIOB33_X0Y11/IOB_IBUF1", + "LIOI3_X0Y11/IOI_ILOGIC1_O", + "LIOI3_X0Y11/IOI_LOGIC_OUTS18_0", + "LIOI3_X0Y11/LIOI_I1", + "LIOI3_X0Y11/LIOI_IBUF1", + "LIOI3_X0Y11/LIOI_ILOGIC1_D", + "L_TERM_INT_X2Y12/TERM_INT_LOGIC_OUTS_L_B18" + ] }, { "name": "din[1]", - "node": "INT_R_X9Y105/NE2BEG3", + "node": "INT_L_X0Y104/EE2BEG2", "pin": "V16", - "wire": "VBRK_X29Y111/VBRK_NE2A3" + "wire": "VBRK_X9Y109/VBRK_EE2A2", + "wires_outside_roi": [ + "BRKH_INT_X0Y49/BRKH_INT_L_LV0", + "BRKH_INT_X0Y99/BRKH_INT_NN6B2", + "CMT_FIFO_R_X7Y112/CMT_FIFO_EE2A2_3", + "CMT_TOP_R_LOWER_B_X8Y113/CMT_TOP_EE2A2_4", + "HCLK_L_X4Y26/HCLK_LV11", + "HCLK_L_X4Y78/HCLK_LV7", + "INT_INTERFACE_R_X1Y104/INT_INTERFACE_EE2A2", + "INT_L_X0Y100/NN6C2", + "INT_L_X0Y101/NN6D2", + "INT_L_X0Y102/NN6E2", + "INT_L_X0Y103/NN6END2", + "INT_L_X0Y103/NR1BEG2", + "INT_L_X0Y104/EE2BEG2", + "INT_L_X0Y104/NR1END2", + "INT_L_X0Y12/LOGIC_OUTS_L18", + "INT_L_X0Y12/NR1BEG0", + "INT_L_X0Y13/LV_L0", + "INT_L_X0Y13/NR1END0", + "INT_L_X0Y14/LV_L1", + "INT_L_X0Y15/LV_L2", + "INT_L_X0Y16/LV_L3", + "INT_L_X0Y17/LV_L4", + "INT_L_X0Y18/LV_L5", + "INT_L_X0Y19/LV_L6", + "INT_L_X0Y20/LV_L7", + "INT_L_X0Y21/LV_L8", + "INT_L_X0Y22/LV_L9", + "INT_L_X0Y23/LV_L10", + "INT_L_X0Y24/LV_L11", + "INT_L_X0Y25/LV_L12", + "INT_L_X0Y26/LV_L13", + "INT_L_X0Y27/LV_L14", + "INT_L_X0Y28/LV_L15", + "INT_L_X0Y29/LV_L16", + "INT_L_X0Y30/LV_L17", + "INT_L_X0Y31/LV_L0", + "INT_L_X0Y31/LV_L18", + "INT_L_X0Y32/LV_L1", + "INT_L_X0Y33/LV_L2", + "INT_L_X0Y34/LV_L3", + "INT_L_X0Y35/LV_L4", + "INT_L_X0Y36/LV_L5", + "INT_L_X0Y37/LV_L6", + "INT_L_X0Y38/LV_L7", + "INT_L_X0Y39/LV_L8", + "INT_L_X0Y40/LV_L9", + "INT_L_X0Y41/LV_L10", + "INT_L_X0Y42/LV_L11", + "INT_L_X0Y43/LV_L12", + "INT_L_X0Y44/LV_L13", + "INT_L_X0Y45/LV_L14", + "INT_L_X0Y46/LV_L15", + "INT_L_X0Y47/LV_L16", + "INT_L_X0Y48/LV_L17", + "INT_L_X0Y49/LV_L0", + "INT_L_X0Y49/LV_L18", + "INT_L_X0Y50/LV_L1", + "INT_L_X0Y51/LV_L2", + "INT_L_X0Y52/LV_L3", + "INT_L_X0Y53/LV_L4", + "INT_L_X0Y54/LV_L5", + "INT_L_X0Y55/LV_L6", + "INT_L_X0Y56/LV_L7", + "INT_L_X0Y57/LV_L8", + "INT_L_X0Y58/LV_L9", + "INT_L_X0Y59/LV_L10", + "INT_L_X0Y60/LV_L11", + "INT_L_X0Y61/LV_L12", + "INT_L_X0Y62/LV_L13", + "INT_L_X0Y63/LV_L14", + "INT_L_X0Y64/LV_L15", + "INT_L_X0Y65/LV_L16", + "INT_L_X0Y66/LV_L17", + "INT_L_X0Y67/LV_L0", + "INT_L_X0Y67/LV_L18", + "INT_L_X0Y68/LV_L1", + "INT_L_X0Y69/LV_L2", + "INT_L_X0Y70/LV_L3", + "INT_L_X0Y71/LV_L4", + "INT_L_X0Y72/LV_L5", + "INT_L_X0Y73/LV_L6", + "INT_L_X0Y74/LV_L7", + "INT_L_X0Y75/LV_L8", + "INT_L_X0Y76/LV_L9", + "INT_L_X0Y77/LV_L10", + "INT_L_X0Y78/LV_L11", + "INT_L_X0Y79/LV_L12", + "INT_L_X0Y80/LV_L13", + "INT_L_X0Y81/LV_L14", + "INT_L_X0Y82/LV_L15", + "INT_L_X0Y83/LV_L16", + "INT_L_X0Y84/LV_L17", + "INT_L_X0Y85/LVB_L0", + "INT_L_X0Y85/LV_L18", + "INT_L_X0Y86/LVB_L1", + "INT_L_X0Y87/LVB_L2", + "INT_L_X0Y88/LVB_L3", + "INT_L_X0Y89/LVB_L4", + "INT_L_X0Y90/LVB_L5", + "INT_L_X0Y91/LVB_L6", + "INT_L_X0Y92/LVB_L7", + "INT_L_X0Y93/LVB_L8", + "INT_L_X0Y94/LVB_L9", + "INT_L_X0Y95/LVB_L10", + "INT_L_X0Y96/LVB_L11", + "INT_L_X0Y97/LVB_L12", + "INT_L_X0Y97/NN6BEG2", + "INT_L_X0Y98/NN6A2", + "INT_L_X0Y99/NN6B2", + "INT_R_X1Y104/EE2A2", + "IO_INT_INTERFACE_L_X0Y12/INT_INTERFACE_LOGIC_OUTS_L18", + "IO_INT_INTERFACE_L_X0Y12/INT_INTERFACE_LOGIC_OUTS_L_B18", + "LIOB33_X0Y11/IOB_IBUF0", + "LIOI3_X0Y11/IOI_ILOGIC0_O", + "LIOI3_X0Y11/IOI_LOGIC_OUTS18_1", + "LIOI3_X0Y11/LIOI_I0", + "LIOI3_X0Y11/LIOI_IBUF0", + "LIOI3_X0Y11/LIOI_ILOGIC0_D", + "L_TERM_INT_X2Y13/TERM_INT_LOGIC_OUTS_L_B18" + ] }, { "name": "din[2]", - "node": "INT_R_X9Y108/NE2BEG3", + "node": "INT_L_X0Y106/EE2BEG2", "pin": "W16", - "wire": "VBRK_X29Y114/VBRK_NE2A3" + "wire": "VBRK_X9Y111/VBRK_EE2A2", + "wires_outside_roi": [ + "BRKH_INT_X0Y49/BRKH_INT_L_LV2", + "BRKH_INT_X0Y99/BRKH_INT_L_LV16", + "CMT_FIFO_R_X7Y112/CMT_FIFO_EE2A2_5", + "CMT_TOP_R_LOWER_B_X8Y113/CMT_TOP_EE2A2_6", + "HCLK_L_X4Y26/HCLK_LV13", + "HCLK_L_X4Y78/HCLK_LV9", + "INT_INTERFACE_R_X1Y106/INT_INTERFACE_EE2A2", + "INT_L_X0Y10/LOGIC_OUTS_L18", + "INT_L_X0Y10/NR1BEG0", + "INT_L_X0Y100/LV_L17", + "INT_L_X0Y101/LV_L18", + "INT_L_X0Y101/NN6BEG3", + "INT_L_X0Y102/NN6A3", + "INT_L_X0Y103/NN6B3", + "INT_L_X0Y104/NN6C3", + "INT_L_X0Y105/NN6D3", + "INT_L_X0Y106/EE2BEG2", + "INT_L_X0Y106/EL1END2", + "INT_L_X0Y106/NN6E3", + "INT_L_X0Y106/SR1END3", + "INT_L_X0Y106/WL1BEG2", + "INT_L_X0Y107/NN6END3", + "INT_L_X0Y107/SR1BEG3", + "INT_L_X0Y107/SR1END_N3_3", + "INT_L_X0Y11/LV_L0", + "INT_L_X0Y11/NR1END0", + "INT_L_X0Y12/LV_L1", + "INT_L_X0Y13/LV_L2", + "INT_L_X0Y14/LV_L3", + "INT_L_X0Y15/LV_L4", + "INT_L_X0Y16/LV_L5", + "INT_L_X0Y17/LV_L6", + "INT_L_X0Y18/LV_L7", + "INT_L_X0Y19/LV_L8", + "INT_L_X0Y20/LV_L9", + "INT_L_X0Y21/LV_L10", + "INT_L_X0Y22/LV_L11", + "INT_L_X0Y23/LV_L12", + "INT_L_X0Y24/LV_L13", + "INT_L_X0Y25/LV_L14", + "INT_L_X0Y26/LV_L15", + "INT_L_X0Y27/LV_L16", + "INT_L_X0Y28/LV_L17", + "INT_L_X0Y29/LV_L0", + "INT_L_X0Y29/LV_L18", + "INT_L_X0Y30/LV_L1", + "INT_L_X0Y31/LV_L2", + "INT_L_X0Y32/LV_L3", + "INT_L_X0Y33/LV_L4", + "INT_L_X0Y34/LV_L5", + "INT_L_X0Y35/LV_L6", + "INT_L_X0Y36/LV_L7", + "INT_L_X0Y37/LV_L8", + "INT_L_X0Y38/LV_L9", + "INT_L_X0Y39/LV_L10", + "INT_L_X0Y40/LV_L11", + "INT_L_X0Y41/LV_L12", + "INT_L_X0Y42/LV_L13", + "INT_L_X0Y43/LV_L14", + "INT_L_X0Y44/LV_L15", + "INT_L_X0Y45/LV_L16", + "INT_L_X0Y46/LV_L17", + "INT_L_X0Y47/LV_L0", + "INT_L_X0Y47/LV_L18", + "INT_L_X0Y48/LV_L1", + "INT_L_X0Y49/LV_L2", + "INT_L_X0Y50/LV_L3", + "INT_L_X0Y51/LV_L4", + "INT_L_X0Y52/LV_L5", + "INT_L_X0Y53/LV_L6", + "INT_L_X0Y54/LV_L7", + "INT_L_X0Y55/LV_L8", + "INT_L_X0Y56/LV_L9", + "INT_L_X0Y57/LV_L10", + "INT_L_X0Y58/LV_L11", + "INT_L_X0Y59/LV_L12", + "INT_L_X0Y60/LV_L13", + "INT_L_X0Y61/LV_L14", + "INT_L_X0Y62/LV_L15", + "INT_L_X0Y63/LV_L16", + "INT_L_X0Y64/LV_L17", + "INT_L_X0Y65/LV_L0", + "INT_L_X0Y65/LV_L18", + "INT_L_X0Y66/LV_L1", + "INT_L_X0Y67/LV_L2", + "INT_L_X0Y68/LV_L3", + "INT_L_X0Y69/LV_L4", + "INT_L_X0Y70/LV_L5", + "INT_L_X0Y71/LV_L6", + "INT_L_X0Y72/LV_L7", + "INT_L_X0Y73/LV_L8", + "INT_L_X0Y74/LV_L9", + "INT_L_X0Y75/LV_L10", + "INT_L_X0Y76/LV_L11", + "INT_L_X0Y77/LV_L12", + "INT_L_X0Y78/LV_L13", + "INT_L_X0Y79/LV_L14", + "INT_L_X0Y80/LV_L15", + "INT_L_X0Y81/LV_L16", + "INT_L_X0Y82/LV_L17", + "INT_L_X0Y83/LV_L0", + "INT_L_X0Y83/LV_L18", + "INT_L_X0Y84/LV_L1", + "INT_L_X0Y85/LV_L2", + "INT_L_X0Y86/LV_L3", + "INT_L_X0Y87/LV_L4", + "INT_L_X0Y88/LV_L5", + "INT_L_X0Y89/LV_L6", + "INT_L_X0Y90/LV_L7", + "INT_L_X0Y91/LV_L8", + "INT_L_X0Y92/LV_L9", + "INT_L_X0Y93/LV_L10", + "INT_L_X0Y94/LV_L11", + "INT_L_X0Y95/LV_L12", + "INT_L_X0Y96/LV_L13", + "INT_L_X0Y97/LV_L14", + "INT_L_X0Y98/LV_L15", + "INT_L_X0Y99/LV_L16", + "INT_R_X1Y106/EE2A2", + "IO_INT_INTERFACE_L_X0Y10/INT_INTERFACE_LOGIC_OUTS_L18", + "IO_INT_INTERFACE_L_X0Y10/INT_INTERFACE_LOGIC_OUTS_L_B18", + "IO_INT_INTERFACE_L_X0Y106/INT_INTERFACE_EL1BEG2", + "IO_INT_INTERFACE_L_X0Y106/INT_INTERFACE_WL1END2", + "LIOB33_X0Y9/IOB_IBUF0", + "LIOI3_X0Y9/IOI_ILOGIC0_O", + "LIOI3_X0Y9/IOI_LOGIC_OUTS18_1", + "LIOI3_X0Y9/LIOI_I0", + "LIOI3_X0Y9/LIOI_IBUF0", + "LIOI3_X0Y9/LIOI_ILOGIC0_D", + "L_TERM_INT_X2Y11/TERM_INT_LOGIC_OUTS_L_B18", + "L_TERM_INT_X2Y111/L_TERM_INT_WL1BEG2" + ] }, { "name": "din[3]", - "node": "INT_R_X9Y111/NE2BEG3", + "node": "INT_L_X0Y108/EE2BEG2", "pin": "W17", - "wire": "VBRK_X29Y117/VBRK_NE2A3" + "wire": "VBRK_X9Y113/VBRK_EE2A2", + "wires_outside_roi": [ + "BRKH_INT_X0Y49/BRKH_INT_L_LV3", + "BRKH_INT_X0Y99/BRKH_INT_L_LV17", + "CMT_FIFO_R_X7Y112/CMT_FIFO_EE2A2_7", + "CMT_TOP_R_LOWER_B_X8Y113/CMT_TOP_EE2A2_8", + "HCLK_L_X4Y26/HCLK_LV14", + "HCLK_L_X4Y78/HCLK_LV10", + "INT_INTERFACE_R_X1Y108/INT_INTERFACE_EE2A2", + "INT_L_X0Y10/LV_L0", + "INT_L_X0Y10/NR1END0", + "INT_L_X0Y100/LV_L18", + "INT_L_X0Y100/NN6BEG3", + "INT_L_X0Y101/NN6A3", + "INT_L_X0Y102/NN6B3", + "INT_L_X0Y103/NN6C3", + "INT_L_X0Y104/NN6D3", + "INT_L_X0Y105/NN6E3", + "INT_L_X0Y106/NN6END3", + "INT_L_X0Y106/NR1BEG3", + "INT_L_X0Y107/NL1BEG2", + "INT_L_X0Y107/NR1END3", + "INT_L_X0Y108/EE2BEG2", + "INT_L_X0Y108/NL1END2", + "INT_L_X0Y11/LV_L1", + "INT_L_X0Y12/LV_L2", + "INT_L_X0Y13/LV_L3", + "INT_L_X0Y14/LV_L4", + "INT_L_X0Y15/LV_L5", + "INT_L_X0Y16/LV_L6", + "INT_L_X0Y17/LV_L7", + "INT_L_X0Y18/LV_L8", + "INT_L_X0Y19/LV_L9", + "INT_L_X0Y20/LV_L10", + "INT_L_X0Y21/LV_L11", + "INT_L_X0Y22/LV_L12", + "INT_L_X0Y23/LV_L13", + "INT_L_X0Y24/LV_L14", + "INT_L_X0Y25/LV_L15", + "INT_L_X0Y26/LV_L16", + "INT_L_X0Y27/LV_L17", + "INT_L_X0Y28/LV_L0", + "INT_L_X0Y28/LV_L18", + "INT_L_X0Y29/LV_L1", + "INT_L_X0Y30/LV_L2", + "INT_L_X0Y31/LV_L3", + "INT_L_X0Y32/LV_L4", + "INT_L_X0Y33/LV_L5", + "INT_L_X0Y34/LV_L6", + "INT_L_X0Y35/LV_L7", + "INT_L_X0Y36/LV_L8", + "INT_L_X0Y37/LV_L9", + "INT_L_X0Y38/LV_L10", + "INT_L_X0Y39/LV_L11", + "INT_L_X0Y40/LV_L12", + "INT_L_X0Y41/LV_L13", + "INT_L_X0Y42/LV_L14", + "INT_L_X0Y43/LV_L15", + "INT_L_X0Y44/LV_L16", + "INT_L_X0Y45/LV_L17", + "INT_L_X0Y46/LV_L0", + "INT_L_X0Y46/LV_L18", + "INT_L_X0Y47/LV_L1", + "INT_L_X0Y48/LV_L2", + "INT_L_X0Y49/LV_L3", + "INT_L_X0Y50/LV_L4", + "INT_L_X0Y51/LV_L5", + "INT_L_X0Y52/LV_L6", + "INT_L_X0Y53/LV_L7", + "INT_L_X0Y54/LV_L8", + "INT_L_X0Y55/LV_L9", + "INT_L_X0Y56/LV_L10", + "INT_L_X0Y57/LV_L11", + "INT_L_X0Y58/LV_L12", + "INT_L_X0Y59/LV_L13", + "INT_L_X0Y60/LV_L14", + "INT_L_X0Y61/LV_L15", + "INT_L_X0Y62/LV_L16", + "INT_L_X0Y63/LV_L17", + "INT_L_X0Y64/LV_L0", + "INT_L_X0Y64/LV_L18", + "INT_L_X0Y65/LV_L1", + "INT_L_X0Y66/LV_L2", + "INT_L_X0Y67/LV_L3", + "INT_L_X0Y68/LV_L4", + "INT_L_X0Y69/LV_L5", + "INT_L_X0Y70/LV_L6", + "INT_L_X0Y71/LV_L7", + "INT_L_X0Y72/LV_L8", + "INT_L_X0Y73/LV_L9", + "INT_L_X0Y74/LV_L10", + "INT_L_X0Y75/LV_L11", + "INT_L_X0Y76/LV_L12", + "INT_L_X0Y77/LV_L13", + "INT_L_X0Y78/LV_L14", + "INT_L_X0Y79/LV_L15", + "INT_L_X0Y80/LV_L16", + "INT_L_X0Y81/LV_L17", + "INT_L_X0Y82/LV_L0", + "INT_L_X0Y82/LV_L18", + "INT_L_X0Y83/LV_L1", + "INT_L_X0Y84/LV_L2", + "INT_L_X0Y85/LV_L3", + "INT_L_X0Y86/LV_L4", + "INT_L_X0Y87/LV_L5", + "INT_L_X0Y88/LV_L6", + "INT_L_X0Y89/LV_L7", + "INT_L_X0Y9/LOGIC_OUTS_L18", + "INT_L_X0Y9/NR1BEG0", + "INT_L_X0Y90/LV_L8", + "INT_L_X0Y91/LV_L9", + "INT_L_X0Y92/LV_L10", + "INT_L_X0Y93/LV_L11", + "INT_L_X0Y94/LV_L12", + "INT_L_X0Y95/LV_L13", + "INT_L_X0Y96/LV_L14", + "INT_L_X0Y97/LV_L15", + "INT_L_X0Y98/LV_L16", + "INT_L_X0Y99/LV_L17", + "INT_R_X1Y108/EE2A2", + "IO_INT_INTERFACE_L_X0Y9/INT_INTERFACE_LOGIC_OUTS_L18", + "IO_INT_INTERFACE_L_X0Y9/INT_INTERFACE_LOGIC_OUTS_L_B18", + "LIOB33_X0Y9/IOB_IBUF1", + "LIOI3_X0Y9/IOI_ILOGIC1_O", + "LIOI3_X0Y9/IOI_LOGIC_OUTS18_0", + "LIOI3_X0Y9/LIOI_I1", + "LIOI3_X0Y9/LIOI_IBUF1", + "LIOI3_X0Y9/LIOI_ILOGIC1_D", + "L_TERM_INT_X2Y10/TERM_INT_LOGIC_OUTS_L_B18" + ] }, { "name": "din[4]", - "node": "INT_R_X9Y114/NE2BEG3", + "node": "INT_L_X0Y110/EE2BEG2", "pin": "W15", - "wire": "VBRK_X29Y120/VBRK_NE2A3" + "wire": "VBRK_X9Y115/VBRK_EE2A2", + "wires_outside_roi": [ + "BRKH_INT_X0Y49/BRKH_INT_L_LV5", + "BRKH_INT_X0Y99/BRKH_INT_LVB_L8", + "CMT_FIFO_R_X7Y112/CMT_FIFO_EE2A2_9", + "CMT_TOP_R_LOWER_B_X8Y113/CMT_TOP_EE2A2_10", + "HCLK_L_X4Y26/HCLK_LV16", + "HCLK_L_X4Y78/HCLK_LV12", + "INT_INTERFACE_R_X1Y110/INT_INTERFACE_EE2A2", + "INT_L_X0Y10/LV_L2", + "INT_L_X0Y100/LVB_L8", + "INT_L_X0Y101/LVB_L9", + "INT_L_X0Y102/LVB_L10", + "INT_L_X0Y103/LVB_L11", + "INT_L_X0Y104/LVB_L12", + "INT_L_X0Y104/NN6BEG2", + "INT_L_X0Y105/NN6A2", + "INT_L_X0Y106/NN6B2", + "INT_L_X0Y107/NN6C2", + "INT_L_X0Y108/NN6D2", + "INT_L_X0Y109/NN6E2", + "INT_L_X0Y11/LV_L3", + "INT_L_X0Y110/EE2BEG2", + "INT_L_X0Y110/NN6END2", + "INT_L_X0Y12/LV_L4", + "INT_L_X0Y13/LV_L5", + "INT_L_X0Y14/LV_L6", + "INT_L_X0Y15/LV_L7", + "INT_L_X0Y16/LV_L8", + "INT_L_X0Y17/LV_L9", + "INT_L_X0Y18/LV_L10", + "INT_L_X0Y19/LV_L11", + "INT_L_X0Y20/LV_L12", + "INT_L_X0Y21/LV_L13", + "INT_L_X0Y22/LV_L14", + "INT_L_X0Y23/LV_L15", + "INT_L_X0Y24/LV_L16", + "INT_L_X0Y25/LV_L17", + "INT_L_X0Y26/LV_L0", + "INT_L_X0Y26/LV_L18", + "INT_L_X0Y27/LV_L1", + "INT_L_X0Y28/LV_L2", + "INT_L_X0Y29/LV_L3", + "INT_L_X0Y30/LV_L4", + "INT_L_X0Y31/LV_L5", + "INT_L_X0Y32/LV_L6", + "INT_L_X0Y33/LV_L7", + "INT_L_X0Y34/LV_L8", + "INT_L_X0Y35/LV_L9", + "INT_L_X0Y36/LV_L10", + "INT_L_X0Y37/LV_L11", + "INT_L_X0Y38/LV_L12", + "INT_L_X0Y39/LV_L13", + "INT_L_X0Y40/LV_L14", + "INT_L_X0Y41/LV_L15", + "INT_L_X0Y42/LV_L16", + "INT_L_X0Y43/LV_L17", + "INT_L_X0Y44/LV_L0", + "INT_L_X0Y44/LV_L18", + "INT_L_X0Y45/LV_L1", + "INT_L_X0Y46/LV_L2", + "INT_L_X0Y47/LV_L3", + "INT_L_X0Y48/LV_L4", + "INT_L_X0Y49/LV_L5", + "INT_L_X0Y50/LV_L6", + "INT_L_X0Y51/LV_L7", + "INT_L_X0Y52/LV_L8", + "INT_L_X0Y53/LV_L9", + "INT_L_X0Y54/LV_L10", + "INT_L_X0Y55/LV_L11", + "INT_L_X0Y56/LV_L12", + "INT_L_X0Y57/LV_L13", + "INT_L_X0Y58/LV_L14", + "INT_L_X0Y59/LV_L15", + "INT_L_X0Y60/LV_L16", + "INT_L_X0Y61/LV_L17", + "INT_L_X0Y62/LV_L0", + "INT_L_X0Y62/LV_L18", + "INT_L_X0Y63/LV_L1", + "INT_L_X0Y64/LV_L2", + "INT_L_X0Y65/LV_L3", + "INT_L_X0Y66/LV_L4", + "INT_L_X0Y67/LV_L5", + "INT_L_X0Y68/LV_L6", + "INT_L_X0Y69/LV_L7", + "INT_L_X0Y7/LOGIC_OUTS_L18", + "INT_L_X0Y7/NR1BEG0", + "INT_L_X0Y70/LV_L8", + "INT_L_X0Y71/LV_L9", + "INT_L_X0Y72/LV_L10", + "INT_L_X0Y73/LV_L11", + "INT_L_X0Y74/LV_L12", + "INT_L_X0Y75/LV_L13", + "INT_L_X0Y76/LV_L14", + "INT_L_X0Y77/LV_L15", + "INT_L_X0Y78/LV_L16", + "INT_L_X0Y79/LV_L17", + "INT_L_X0Y8/LV_L0", + "INT_L_X0Y8/NR1END0", + "INT_L_X0Y80/LVB_L0", + "INT_L_X0Y80/LV_L18", + "INT_L_X0Y81/LVB_L1", + "INT_L_X0Y82/LVB_L2", + "INT_L_X0Y83/LVB_L3", + "INT_L_X0Y84/LVB_L4", + "INT_L_X0Y85/LVB_L5", + "INT_L_X0Y86/LVB_L6", + "INT_L_X0Y87/LVB_L7", + "INT_L_X0Y88/LVB_L8", + "INT_L_X0Y89/LVB_L9", + "INT_L_X0Y9/LV_L1", + "INT_L_X0Y90/LVB_L10", + "INT_L_X0Y91/LVB_L11", + "INT_L_X0Y92/LVB_L0", + "INT_L_X0Y92/LVB_L12", + "INT_L_X0Y93/LVB_L1", + "INT_L_X0Y94/LVB_L2", + "INT_L_X0Y95/LVB_L3", + "INT_L_X0Y96/LVB_L4", + "INT_L_X0Y97/LVB_L5", + "INT_L_X0Y98/LVB_L6", + "INT_L_X0Y99/LVB_L7", + "INT_R_X1Y110/EE2A2", + "IO_INT_INTERFACE_L_X0Y7/INT_INTERFACE_LOGIC_OUTS_L18", + "IO_INT_INTERFACE_L_X0Y7/INT_INTERFACE_LOGIC_OUTS_L_B18", + "LIOB33_X0Y7/IOB_IBUF1", + "LIOI3_TBYTESRC_X0Y7/IOI_ILOGIC1_O", + "LIOI3_TBYTESRC_X0Y7/IOI_LOGIC_OUTS18_0", + "LIOI3_TBYTESRC_X0Y7/LIOI_I1", + "LIOI3_TBYTESRC_X0Y7/LIOI_IBUF1", + "LIOI3_TBYTESRC_X0Y7/LIOI_ILOGIC1_D", + "L_TERM_INT_X2Y8/TERM_INT_LOGIC_OUTS_L_B18" + ] }, { "name": "din[5]", - "node": "INT_R_X9Y117/NE2BEG3", + "node": "INT_L_X0Y112/EE2BEG2", "pin": "V15", - "wire": "VBRK_X29Y123/VBRK_NE2A3" + "wire": "VBRK_X9Y117/VBRK_EE2A2", + "wires_outside_roi": [ + "BRKH_INT_X0Y49/BRKH_INT_L_LV4", + "BRKH_INT_X0Y99/BRKH_INT_NN6BEG3", + "CMT_FIFO_R_X7Y112/CMT_FIFO_EE2A2_11", + "CMT_TOP_R_LOWER_B_X8Y113/CMT_TOP_EE2A2_12", + "HCLK_L_X4Y26/HCLK_LV15", + "HCLK_L_X4Y78/HCLK_LV11", + "INT_INTERFACE_R_X1Y112/INT_INTERFACE_EE2A2", + "INT_L_X0Y10/LV_L1", + "INT_L_X0Y100/NN6A3", + "INT_L_X0Y101/NN6B3", + "INT_L_X0Y102/NN6C3", + "INT_L_X0Y103/NN6D3", + "INT_L_X0Y104/NN6E3", + "INT_L_X0Y105/NN6BEG3", + "INT_L_X0Y105/NN6END3", + "INT_L_X0Y106/NN6A3", + "INT_L_X0Y107/NN6B3", + "INT_L_X0Y108/NN6C3", + "INT_L_X0Y109/NN6D3", + "INT_L_X0Y11/LV_L2", + "INT_L_X0Y110/NN6E3", + "INT_L_X0Y111/NL1BEG2", + "INT_L_X0Y111/NN6END3", + "INT_L_X0Y112/EE2BEG2", + "INT_L_X0Y112/NL1END2", + "INT_L_X0Y12/LV_L3", + "INT_L_X0Y13/LV_L4", + "INT_L_X0Y14/LV_L5", + "INT_L_X0Y15/LV_L6", + "INT_L_X0Y16/LV_L7", + "INT_L_X0Y17/LV_L8", + "INT_L_X0Y18/LV_L9", + "INT_L_X0Y19/LV_L10", + "INT_L_X0Y20/LV_L11", + "INT_L_X0Y21/LV_L12", + "INT_L_X0Y22/LV_L13", + "INT_L_X0Y23/LV_L14", + "INT_L_X0Y24/LV_L15", + "INT_L_X0Y25/LV_L16", + "INT_L_X0Y26/LV_L17", + "INT_L_X0Y27/LV_L0", + "INT_L_X0Y27/LV_L18", + "INT_L_X0Y28/LV_L1", + "INT_L_X0Y29/LV_L2", + "INT_L_X0Y30/LV_L3", + "INT_L_X0Y31/LV_L4", + "INT_L_X0Y32/LV_L5", + "INT_L_X0Y33/LV_L6", + "INT_L_X0Y34/LV_L7", + "INT_L_X0Y35/LV_L8", + "INT_L_X0Y36/LV_L9", + "INT_L_X0Y37/LV_L10", + "INT_L_X0Y38/LV_L11", + "INT_L_X0Y39/LV_L12", + "INT_L_X0Y40/LV_L13", + "INT_L_X0Y41/LV_L14", + "INT_L_X0Y42/LV_L15", + "INT_L_X0Y43/LV_L16", + "INT_L_X0Y44/LV_L17", + "INT_L_X0Y45/LV_L0", + "INT_L_X0Y45/LV_L18", + "INT_L_X0Y46/LV_L1", + "INT_L_X0Y47/LV_L2", + "INT_L_X0Y48/LV_L3", + "INT_L_X0Y49/LV_L4", + "INT_L_X0Y50/LV_L5", + "INT_L_X0Y51/LV_L6", + "INT_L_X0Y52/LV_L7", + "INT_L_X0Y53/LV_L8", + "INT_L_X0Y54/LV_L9", + "INT_L_X0Y55/LV_L10", + "INT_L_X0Y56/LV_L11", + "INT_L_X0Y57/LV_L12", + "INT_L_X0Y58/LV_L13", + "INT_L_X0Y59/LV_L14", + "INT_L_X0Y60/LV_L15", + "INT_L_X0Y61/LV_L16", + "INT_L_X0Y62/LV_L17", + "INT_L_X0Y63/LV_L0", + "INT_L_X0Y63/LV_L18", + "INT_L_X0Y64/LV_L1", + "INT_L_X0Y65/LV_L2", + "INT_L_X0Y66/LV_L3", + "INT_L_X0Y67/LV_L4", + "INT_L_X0Y68/LV_L5", + "INT_L_X0Y69/LV_L6", + "INT_L_X0Y70/LV_L7", + "INT_L_X0Y71/LV_L8", + "INT_L_X0Y72/LV_L9", + "INT_L_X0Y73/LV_L10", + "INT_L_X0Y74/LV_L11", + "INT_L_X0Y75/LV_L12", + "INT_L_X0Y76/LV_L13", + "INT_L_X0Y77/LV_L14", + "INT_L_X0Y78/LV_L15", + "INT_L_X0Y79/LV_L16", + "INT_L_X0Y8/LOGIC_OUTS_L18", + "INT_L_X0Y8/NR1BEG0", + "INT_L_X0Y80/LV_L17", + "INT_L_X0Y81/LV_L0", + "INT_L_X0Y81/LV_L18", + "INT_L_X0Y82/LV_L1", + "INT_L_X0Y83/LV_L2", + "INT_L_X0Y84/LV_L3", + "INT_L_X0Y85/LV_L4", + "INT_L_X0Y86/LV_L5", + "INT_L_X0Y87/LV_L6", + "INT_L_X0Y88/LV_L7", + "INT_L_X0Y89/LV_L8", + "INT_L_X0Y9/LV_L0", + "INT_L_X0Y9/NR1END0", + "INT_L_X0Y90/LV_L9", + "INT_L_X0Y91/LV_L10", + "INT_L_X0Y92/LV_L11", + "INT_L_X0Y93/LV_L12", + "INT_L_X0Y94/LV_L13", + "INT_L_X0Y95/LV_L14", + "INT_L_X0Y96/LV_L15", + "INT_L_X0Y97/LV_L16", + "INT_L_X0Y98/LV_L17", + "INT_L_X0Y99/LV_L18", + "INT_L_X0Y99/NN6BEG3", + "INT_R_X1Y112/EE2A2", + "IO_INT_INTERFACE_L_X0Y8/INT_INTERFACE_LOGIC_OUTS_L18", + "IO_INT_INTERFACE_L_X0Y8/INT_INTERFACE_LOGIC_OUTS_L_B18", + "LIOB33_X0Y7/IOB_IBUF0", + "LIOI3_TBYTESRC_X0Y7/IOI_ILOGIC0_O", + "LIOI3_TBYTESRC_X0Y7/IOI_LOGIC_OUTS18_1", + "LIOI3_TBYTESRC_X0Y7/LIOI_I0", + "LIOI3_TBYTESRC_X0Y7/LIOI_IBUF0", + "LIOI3_TBYTESRC_X0Y7/LIOI_ILOGIC0_D", + "L_TERM_INT_X2Y9/TERM_INT_LOGIC_OUTS_L_B18" + ] }, { "name": "din[6]", - "node": "INT_R_X9Y120/NE2BEG3", + "node": "INT_L_X0Y114/EE2BEG2", "pin": "W14", - "wire": "VBRK_X29Y126/VBRK_NE2A3" + "wire": "VBRK_X9Y119/VBRK_EE2A2", + "wires_outside_roi": [ + "BRKH_INT_X0Y49/BRKH_INT_L_LV7", + "BRKH_INT_X0Y99/BRKH_INT_LVB_L4", + "CMT_FIFO_R_X7Y124/CMT_FIFO_EE2A2_1", + "CMT_TOP_R_LOWER_B_X8Y113/CMT_TOP_EE2A2_14", + "HCLK_L_X4Y26/HCLK_LV0", + "HCLK_L_X4Y78/HCLK_LV14", + "INT_INTERFACE_R_X1Y114/INT_INTERFACE_EE2A2", + "INT_L_X0Y10/LV_L4", + "INT_L_X0Y100/LVB_L4", + "INT_L_X0Y101/LVB_L5", + "INT_L_X0Y102/LVB_L6", + "INT_L_X0Y103/LVB_L7", + "INT_L_X0Y104/LVB_L8", + "INT_L_X0Y105/LVB_L9", + "INT_L_X0Y106/LVB_L10", + "INT_L_X0Y107/LVB_L11", + "INT_L_X0Y108/LVB_L12", + "INT_L_X0Y108/NN6BEG2", + "INT_L_X0Y109/NN6A2", + "INT_L_X0Y11/LV_L5", + "INT_L_X0Y110/NN6B2", + "INT_L_X0Y111/NN6C2", + "INT_L_X0Y112/NN6D2", + "INT_L_X0Y113/NN6E2", + "INT_L_X0Y114/EE2BEG2", + "INT_L_X0Y114/NN6END2", + "INT_L_X0Y12/LV_L6", + "INT_L_X0Y13/LV_L7", + "INT_L_X0Y14/LV_L8", + "INT_L_X0Y15/LV_L9", + "INT_L_X0Y16/LV_L10", + "INT_L_X0Y17/LV_L11", + "INT_L_X0Y18/LV_L12", + "INT_L_X0Y19/LV_L13", + "INT_L_X0Y20/LV_L14", + "INT_L_X0Y21/LV_L15", + "INT_L_X0Y22/LV_L16", + "INT_L_X0Y23/LV_L17", + "INT_L_X0Y24/LV_L0", + "INT_L_X0Y24/LV_L18", + "INT_L_X0Y25/LV_L1", + "INT_L_X0Y26/LV_L2", + "INT_L_X0Y27/LV_L3", + "INT_L_X0Y28/LV_L4", + "INT_L_X0Y29/LV_L5", + "INT_L_X0Y30/LV_L6", + "INT_L_X0Y31/LV_L7", + "INT_L_X0Y32/LV_L8", + "INT_L_X0Y33/LV_L9", + "INT_L_X0Y34/LV_L10", + "INT_L_X0Y35/LV_L11", + "INT_L_X0Y36/LV_L12", + "INT_L_X0Y37/LV_L13", + "INT_L_X0Y38/LV_L14", + "INT_L_X0Y39/LV_L15", + "INT_L_X0Y40/LV_L16", + "INT_L_X0Y41/LV_L17", + "INT_L_X0Y42/LV_L0", + "INT_L_X0Y42/LV_L18", + "INT_L_X0Y43/LV_L1", + "INT_L_X0Y44/LV_L2", + "INT_L_X0Y45/LV_L3", + "INT_L_X0Y46/LV_L4", + "INT_L_X0Y47/LV_L5", + "INT_L_X0Y48/LV_L6", + "INT_L_X0Y49/LV_L7", + "INT_L_X0Y5/LOGIC_OUTS_L18", + "INT_L_X0Y5/NR1BEG0", + "INT_L_X0Y50/LV_L8", + "INT_L_X0Y51/LV_L9", + "INT_L_X0Y52/LV_L10", + "INT_L_X0Y53/LV_L11", + "INT_L_X0Y54/LV_L12", + "INT_L_X0Y55/LV_L13", + "INT_L_X0Y56/LV_L14", + "INT_L_X0Y57/LV_L15", + "INT_L_X0Y58/LV_L16", + "INT_L_X0Y59/LV_L17", + "INT_L_X0Y6/LV_L0", + "INT_L_X0Y6/NR1END0", + "INT_L_X0Y60/LV_L0", + "INT_L_X0Y60/LV_L18", + "INT_L_X0Y61/LV_L1", + "INT_L_X0Y62/LV_L2", + "INT_L_X0Y63/LV_L3", + "INT_L_X0Y64/LV_L4", + "INT_L_X0Y65/LV_L5", + "INT_L_X0Y66/LV_L6", + "INT_L_X0Y67/LV_L7", + "INT_L_X0Y68/LV_L8", + "INT_L_X0Y69/LV_L9", + "INT_L_X0Y7/LV_L1", + "INT_L_X0Y70/LV_L10", + "INT_L_X0Y71/LV_L11", + "INT_L_X0Y72/LV_L12", + "INT_L_X0Y73/LV_L13", + "INT_L_X0Y74/LV_L14", + "INT_L_X0Y75/LV_L15", + "INT_L_X0Y76/LV_L16", + "INT_L_X0Y77/LV_L17", + "INT_L_X0Y78/LV_L0", + "INT_L_X0Y78/LV_L18", + "INT_L_X0Y79/LV_L1", + "INT_L_X0Y8/LV_L2", + "INT_L_X0Y80/LV_L2", + "INT_L_X0Y81/LV_L3", + "INT_L_X0Y82/LV_L4", + "INT_L_X0Y83/LV_L5", + "INT_L_X0Y84/LV_L6", + "INT_L_X0Y85/LV_L7", + "INT_L_X0Y86/LV_L8", + "INT_L_X0Y87/LV_L9", + "INT_L_X0Y88/LV_L10", + "INT_L_X0Y89/LV_L11", + "INT_L_X0Y9/LV_L3", + "INT_L_X0Y90/LV_L12", + "INT_L_X0Y91/LV_L13", + "INT_L_X0Y92/LV_L14", + "INT_L_X0Y93/LV_L15", + "INT_L_X0Y94/LV_L16", + "INT_L_X0Y95/LV_L17", + "INT_L_X0Y96/LVB_L0", + "INT_L_X0Y96/LV_L18", + "INT_L_X0Y97/LVB_L1", + "INT_L_X0Y98/LVB_L2", + "INT_L_X0Y99/LVB_L3", + "INT_R_X1Y114/EE2A2", + "IO_INT_INTERFACE_L_X0Y5/INT_INTERFACE_LOGIC_OUTS_L18", + "IO_INT_INTERFACE_L_X0Y5/INT_INTERFACE_LOGIC_OUTS_L_B18", + "LIOB33_X0Y5/IOB_IBUF1", + "LIOI3_X0Y5/IOI_ILOGIC1_O", + "LIOI3_X0Y5/IOI_LOGIC_OUTS18_0", + "LIOI3_X0Y5/LIOI_I1", + "LIOI3_X0Y5/LIOI_IBUF1", + "LIOI3_X0Y5/LIOI_ILOGIC1_D", + "L_TERM_INT_X2Y6/TERM_INT_LOGIC_OUTS_L_B18" + ] }, { "name": "din[7]", - "node": "INT_R_X9Y123/NE2BEG3", + "node": "INT_L_X0Y116/EE2BEG2", "pin": "W13", - "wire": "VBRK_X29Y129/VBRK_NE2A3" + "wire": "VBRK_X9Y121/VBRK_EE2A2", + "wires_outside_roi": [ + "BRKH_INT_X0Y49/BRKH_INT_L_LV6", + "BRKH_INT_X0Y99/BRKH_INT_LVB_L3", + "CMT_FIFO_R_X7Y124/CMT_FIFO_EE2A2_3", + "CMT_TOP_R_LOWER_T_X8Y122/CMT_TOP_EE2A2_0", + "HCLK_L_X4Y26/HCLK_LV17", + "HCLK_L_X4Y78/HCLK_LV13", + "INT_INTERFACE_R_X1Y116/INT_INTERFACE_EE2A2", + "INT_L_X0Y10/LV_L3", + "INT_L_X0Y100/LVB_L3", + "INT_L_X0Y101/LVB_L4", + "INT_L_X0Y102/LVB_L5", + "INT_L_X0Y103/LVB_L6", + "INT_L_X0Y104/LVB_L7", + "INT_L_X0Y105/LVB_L8", + "INT_L_X0Y106/LVB_L9", + "INT_L_X0Y107/LVB_L10", + "INT_L_X0Y108/LVB_L11", + "INT_L_X0Y109/LVB_L12", + "INT_L_X0Y109/NN6BEG2", + "INT_L_X0Y11/LV_L4", + "INT_L_X0Y110/NN6A2", + "INT_L_X0Y111/NN6B2", + "INT_L_X0Y112/NN6C2", + "INT_L_X0Y113/NN6D2", + "INT_L_X0Y114/NN6E2", + "INT_L_X0Y115/NN6END2", + "INT_L_X0Y115/NR1BEG2", + "INT_L_X0Y116/EE2BEG2", + "INT_L_X0Y116/NR1END2", + "INT_L_X0Y12/LV_L5", + "INT_L_X0Y13/LV_L6", + "INT_L_X0Y14/LV_L7", + "INT_L_X0Y15/LV_L8", + "INT_L_X0Y16/LV_L9", + "INT_L_X0Y17/LV_L10", + "INT_L_X0Y18/LV_L11", + "INT_L_X0Y19/LV_L12", + "INT_L_X0Y20/LV_L13", + "INT_L_X0Y21/LV_L14", + "INT_L_X0Y22/LV_L15", + "INT_L_X0Y23/LV_L16", + "INT_L_X0Y24/LV_L17", + "INT_L_X0Y25/LV_L0", + "INT_L_X0Y25/LV_L18", + "INT_L_X0Y26/LV_L1", + "INT_L_X0Y27/LV_L2", + "INT_L_X0Y28/LV_L3", + "INT_L_X0Y29/LV_L4", + "INT_L_X0Y30/LV_L5", + "INT_L_X0Y31/LV_L6", + "INT_L_X0Y32/LV_L7", + "INT_L_X0Y33/LV_L8", + "INT_L_X0Y34/LV_L9", + "INT_L_X0Y35/LV_L10", + "INT_L_X0Y36/LV_L11", + "INT_L_X0Y37/LV_L12", + "INT_L_X0Y38/LV_L13", + "INT_L_X0Y39/LV_L14", + "INT_L_X0Y40/LV_L15", + "INT_L_X0Y41/LV_L16", + "INT_L_X0Y42/LV_L17", + "INT_L_X0Y43/LV_L0", + "INT_L_X0Y43/LV_L18", + "INT_L_X0Y44/LV_L1", + "INT_L_X0Y45/LV_L2", + "INT_L_X0Y46/LV_L3", + "INT_L_X0Y47/LV_L4", + "INT_L_X0Y48/LV_L5", + "INT_L_X0Y49/LV_L6", + "INT_L_X0Y50/LV_L7", + "INT_L_X0Y51/LV_L8", + "INT_L_X0Y52/LV_L9", + "INT_L_X0Y53/LV_L10", + "INT_L_X0Y54/LV_L11", + "INT_L_X0Y55/LV_L12", + "INT_L_X0Y56/LV_L13", + "INT_L_X0Y57/LV_L14", + "INT_L_X0Y58/LV_L15", + "INT_L_X0Y59/LV_L16", + "INT_L_X0Y6/LOGIC_OUTS_L18", + "INT_L_X0Y6/NR1BEG0", + "INT_L_X0Y60/LV_L17", + "INT_L_X0Y61/LV_L0", + "INT_L_X0Y61/LV_L18", + "INT_L_X0Y62/LV_L1", + "INT_L_X0Y63/LV_L2", + "INT_L_X0Y64/LV_L3", + "INT_L_X0Y65/LV_L4", + "INT_L_X0Y66/LV_L5", + "INT_L_X0Y67/LV_L6", + "INT_L_X0Y68/LV_L7", + "INT_L_X0Y69/LV_L8", + "INT_L_X0Y7/LV_L0", + "INT_L_X0Y7/NR1END0", + "INT_L_X0Y70/LV_L9", + "INT_L_X0Y71/LV_L10", + "INT_L_X0Y72/LV_L11", + "INT_L_X0Y73/LV_L12", + "INT_L_X0Y74/LV_L13", + "INT_L_X0Y75/LV_L14", + "INT_L_X0Y76/LV_L15", + "INT_L_X0Y77/LV_L16", + "INT_L_X0Y78/LV_L17", + "INT_L_X0Y79/LV_L0", + "INT_L_X0Y79/LV_L18", + "INT_L_X0Y8/LV_L1", + "INT_L_X0Y80/LV_L1", + "INT_L_X0Y81/LV_L2", + "INT_L_X0Y82/LV_L3", + "INT_L_X0Y83/LV_L4", + "INT_L_X0Y84/LV_L5", + "INT_L_X0Y85/LV_L6", + "INT_L_X0Y86/LV_L7", + "INT_L_X0Y87/LV_L8", + "INT_L_X0Y88/LV_L9", + "INT_L_X0Y89/LV_L10", + "INT_L_X0Y9/LV_L2", + "INT_L_X0Y90/LV_L11", + "INT_L_X0Y91/LV_L12", + "INT_L_X0Y92/LV_L13", + "INT_L_X0Y93/LV_L14", + "INT_L_X0Y94/LV_L15", + "INT_L_X0Y95/LV_L16", + "INT_L_X0Y96/LV_L17", + "INT_L_X0Y97/LVB_L0", + "INT_L_X0Y97/LV_L18", + "INT_L_X0Y98/LVB_L1", + "INT_L_X0Y99/LVB_L2", + "INT_R_X1Y116/EE2A2", + "IO_INT_INTERFACE_L_X0Y6/INT_INTERFACE_LOGIC_OUTS_L18", + "IO_INT_INTERFACE_L_X0Y6/INT_INTERFACE_LOGIC_OUTS_L_B18", + "LIOB33_X0Y5/IOB_IBUF0", + "LIOI3_X0Y5/IOI_ILOGIC0_O", + "LIOI3_X0Y5/IOI_LOGIC_OUTS18_1", + "LIOI3_X0Y5/LIOI_I0", + "LIOI3_X0Y5/LIOI_IBUF0", + "LIOI3_X0Y5/LIOI_ILOGIC0_D", + "L_TERM_INT_X2Y7/TERM_INT_LOGIC_OUTS_L_B18" + ] + }, + { + "name": "din[8]", + "node": "INT_R_X25Y126/WW2BEG1", + "pin": "V2", + "wire": "VBRK_X61Y132/VBRK_WW2END1", + "wires_outside_roi": [ + "BRAM_INT_INTERFACE_L_X30Y129/INT_INTERFACE_NW4END2", + "BRAM_INT_INTERFACE_R_X37Y59/INT_INTERFACE_LH6", + "BRAM_L_X30Y125/BRAM_NW4END2_4", + "BRAM_R_X37Y55/BRAM_LH6_4", + "BRKH_INT_X31Y99/BRKH_INT_LV4", + "BRKH_INT_X43Y49/BRKH_INT_LV8", + "CLBLL_L_X24Y126/CLBLL_WW2END1", + "CLBLL_L_X26Y126/CLBLL_WW4END2", + "CLBLL_L_X28Y126/CLBLL_WW4B2", + "CLBLL_L_X38Y59/CLBLL_LH6", + "CLBLL_L_X40Y59/CLBLL_LH4", + "CLBLL_R_X31Y59/CLBLL_LH12", + "CLBLM_L_X32Y59/CLBLM_LH12", + "CLBLM_L_X36Y59/CLBLM_LH8", + "CLBLM_R_X25Y126/CLBLM_WW4END2", + "CLBLM_R_X27Y126/CLBLM_WW4B2", + "CLBLM_R_X29Y129/CLBLM_NW4END2", + "CLBLM_R_X33Y59/CLBLM_LH10", + "CLBLM_R_X35Y59/CLBLM_LH8", + "CLBLM_R_X39Y59/CLBLM_LH4", + "CLBLM_R_X41Y59/CLBLM_LH2", + "CLK_HROW_TOP_R_X60Y130/CLK_HROW_WW2END1_5", + "CMT_FIFO_L_X107Y60/CMT_FIFO_LH2_8", + "CMT_TOP_L_LOWER_B_X106Y61/CMT_TOP_LH2_9", + "DSP_L_X34Y55/DSP_LH10_4", + "HCLK_R_BOT_UTURN_X73Y130/B_TERM_UTURN_INT_SS6D1", + "HCLK_R_X78Y130/HCLK_LVB12", + "HCLK_R_X78Y78/HCLK_LV15", + "INT_INTERFACE_L_X34Y59/INT_INTERFACE_LH10", + "INT_INTERFACE_L_X42Y59/INT_INTERFACE_LH2", + "INT_INTERFACE_R_X23Y126/INT_INTERFACE_WW2END1", + "INT_L_X24Y126/WW2A1", + "INT_L_X26Y126/WW4C2", + "INT_L_X28Y126/WW4A2", + "INT_L_X30Y125/NW6A2", + "INT_L_X30Y126/NW6B2", + "INT_L_X30Y127/NW6C2", + "INT_L_X30Y128/NW6D2", + "INT_L_X30Y129/NW6E2", + "INT_L_X32Y59/LH11", + "INT_L_X34Y59/LH9", + "INT_L_X36Y59/LH7", + "INT_L_X38Y59/LH5", + "INT_L_X40Y59/LH3", + "INT_L_X42Y59/LH1", + "INT_R_X25Y126/WW2BEG1", + "INT_R_X25Y126/WW4END2", + "INT_R_X27Y126/WW4B2", + "INT_R_X29Y125/NN6E2", + "INT_R_X29Y125/SS6D1", + "INT_R_X29Y126/NN6END2", + "INT_R_X29Y126/SS6C1", + "INT_R_X29Y126/WW4BEG2", + "INT_R_X29Y127/SS6B1", + "INT_R_X29Y128/SS6A1", + "INT_R_X29Y129/NW6END2", + "INT_R_X29Y129/SS6BEG1", + "INT_R_X31Y100/LV5", + "INT_R_X31Y101/LV6", + "INT_R_X31Y102/LV7", + "INT_R_X31Y103/LV8", + "INT_R_X31Y104/LV9", + "INT_R_X31Y105/LV10", + "INT_R_X31Y106/LV11", + "INT_R_X31Y107/LV12", + "INT_R_X31Y108/LV13", + "INT_R_X31Y109/LV14", + "INT_R_X31Y110/LV15", + "INT_R_X31Y111/LV16", + "INT_R_X31Y112/LV17", + "INT_R_X31Y113/LV18", + "INT_R_X31Y113/LVB0", + "INT_R_X31Y114/LVB1", + "INT_R_X31Y115/LVB2", + "INT_R_X31Y116/LVB3", + "INT_R_X31Y117/LVB4", + "INT_R_X31Y118/LVB5", + "INT_R_X31Y119/LVB6", + "INT_R_X31Y120/LVB7", + "INT_R_X31Y121/LVB8", + "INT_R_X31Y122/LVB9", + "INT_R_X31Y123/LVB10", + "INT_R_X31Y124/LVB11", + "INT_R_X31Y125/LVB12", + "INT_R_X31Y125/NW6BEG2", + "INT_R_X31Y59/LH12", + "INT_R_X31Y59/LV0", + "INT_R_X31Y60/LV1", + "INT_R_X31Y61/LV2", + "INT_R_X31Y62/LV3", + "INT_R_X31Y63/LV4", + "INT_R_X31Y64/LV5", + "INT_R_X31Y65/LV6", + "INT_R_X31Y66/LV7", + "INT_R_X31Y67/LV8", + "INT_R_X31Y68/LV9", + "INT_R_X31Y69/LV10", + "INT_R_X31Y70/LV11", + "INT_R_X31Y71/LV12", + "INT_R_X31Y72/LV13", + "INT_R_X31Y73/LV14", + "INT_R_X31Y74/LV15", + "INT_R_X31Y75/LV16", + "INT_R_X31Y76/LV17", + "INT_R_X31Y77/LV0", + "INT_R_X31Y77/LV18", + "INT_R_X31Y78/LV1", + "INT_R_X31Y79/LV2", + "INT_R_X31Y80/LV3", + "INT_R_X31Y81/LV4", + "INT_R_X31Y82/LV5", + "INT_R_X31Y83/LV6", + "INT_R_X31Y84/LV7", + "INT_R_X31Y85/LV8", + "INT_R_X31Y86/LV9", + "INT_R_X31Y87/LV10", + "INT_R_X31Y88/LV11", + "INT_R_X31Y89/LV12", + "INT_R_X31Y90/LV13", + "INT_R_X31Y91/LV14", + "INT_R_X31Y92/LV15", + "INT_R_X31Y93/LV16", + "INT_R_X31Y94/LV17", + "INT_R_X31Y95/LV0", + "INT_R_X31Y95/LV18", + "INT_R_X31Y96/LV1", + "INT_R_X31Y97/LV2", + "INT_R_X31Y98/LV3", + "INT_R_X31Y99/LV4", + "INT_R_X33Y59/LH10", + "INT_R_X35Y59/LH8", + "INT_R_X37Y59/LH6", + "INT_R_X39Y59/LH4", + "INT_R_X41Y59/LH2", + "INT_R_X43Y40/LOGIC_OUTS18", + "INT_R_X43Y40/NR1BEG0", + "INT_R_X43Y41/LV0", + "INT_R_X43Y41/NR1END0", + "INT_R_X43Y42/LV1", + "INT_R_X43Y43/LV2", + "INT_R_X43Y44/LV3", + "INT_R_X43Y45/LV4", + "INT_R_X43Y46/LV5", + "INT_R_X43Y47/LV6", + "INT_R_X43Y48/LV7", + "INT_R_X43Y49/LV8", + "INT_R_X43Y50/LV9", + "INT_R_X43Y51/LV10", + "INT_R_X43Y52/LV11", + "INT_R_X43Y53/LV12", + "INT_R_X43Y54/LV13", + "INT_R_X43Y55/LV14", + "INT_R_X43Y56/LV15", + "INT_R_X43Y57/LV16", + "INT_R_X43Y58/LV17", + "INT_R_X43Y59/LH0", + "INT_R_X43Y59/LV18", + "IO_INT_INTERFACE_R_X43Y40/INT_INTERFACE_LOGIC_OUTS18", + "IO_INT_INTERFACE_R_X43Y40/INT_INTERFACE_LOGIC_OUTS_B18", + "RIOB33_X43Y39/IOB_IBUF0", + "RIOI3_X43Y39/IOI_ILOGIC0_O", + "RIOI3_X43Y39/IOI_LOGIC_OUTS18_1", + "RIOI3_X43Y39/RIOI_I0", + "RIOI3_X43Y39/RIOI_IBUF0", + "RIOI3_X43Y39/RIOI_ILOGIC0_D", + "R_TERM_INT_X112Y42/TERM_INT_LOGIC_OUTS_L_B18", + "VBRK_X105Y62/VBRK_LH2", + "VBRK_X61Y132/VBRK_WW2END1", + "VBRK_X66Y132/VBRK_WW4END2", + "VBRK_X80Y62/VBRK_LH12", + "VBRK_X85Y62/VBRK_LH10", + "VBRK_X96Y62/VBRK_LH6" + ] + }, + { + "name": "din[9]", + "node": "INT_R_X25Y128/WW2BEG1", + "pin": "T3", + "wire": "VBRK_X61Y134/VBRK_WW2END1", + "wires_outside_roi": [ + "BRAM_INT_INTERFACE_L_X30Y128/INT_INTERFACE_NW4END2", + "BRAM_INT_INTERFACE_R_X37Y64/INT_INTERFACE_LH6", + "BRAM_L_X30Y125/BRAM_NW4END2_3", + "BRAM_R_X37Y60/BRAM_LH6_4", + "BRKH_INT_X31Y99/BRKH_INT_LV17", + "BRKH_INT_X43Y49/BRKH_INT_LV3", + "CLBLL_L_X24Y128/CLBLL_WW2END1", + "CLBLL_L_X26Y128/CLBLL_WW4END2", + "CLBLL_L_X28Y128/CLBLL_WW4B2", + "CLBLL_L_X38Y64/CLBLL_LH6", + "CLBLL_L_X40Y64/CLBLL_LH4", + "CLBLL_R_X31Y64/CLBLL_LH12", + "CLBLM_L_X32Y64/CLBLM_LH12", + "CLBLM_L_X36Y64/CLBLM_LH8", + "CLBLM_R_X25Y128/CLBLM_WW4END2", + "CLBLM_R_X27Y128/CLBLM_WW4B2", + "CLBLM_R_X29Y128/CLBLM_NW4END2", + "CLBLM_R_X33Y64/CLBLM_LH10", + "CLBLM_R_X35Y64/CLBLM_LH8", + "CLBLM_R_X39Y64/CLBLM_LH4", + "CLBLM_R_X41Y64/CLBLM_LH2", + "CLK_HROW_TOP_R_X60Y130/CLK_HROW_WW2END1_7", + "CMT_FIFO_L_X107Y72/CMT_FIFO_LH2_1", + "CMT_TOP_L_LOWER_B_X106Y61/CMT_TOP_LH2_14", + "DSP_L_X34Y60/DSP_LH10_4", + "HCLK_L_X77Y130/HCLK_NW6A2", + "HCLK_R_X78Y78/HCLK_LV10", + "INT_INTERFACE_L_X34Y64/INT_INTERFACE_LH10", + "INT_INTERFACE_L_X42Y64/INT_INTERFACE_LH2", + "INT_INTERFACE_R_X23Y128/INT_INTERFACE_WW2END1", + "INT_L_X24Y128/WW2A1", + "INT_L_X26Y128/WW4C2", + "INT_L_X28Y128/WW4A2", + "INT_L_X30Y124/NW6A2", + "INT_L_X30Y125/NW6B2", + "INT_L_X30Y126/NW6C2", + "INT_L_X30Y127/NW6D2", + "INT_L_X30Y128/NW6E2", + "INT_L_X32Y64/LH11", + "INT_L_X34Y64/LH9", + "INT_L_X36Y64/LH7", + "INT_L_X38Y64/LH5", + "INT_L_X40Y64/LH3", + "INT_L_X42Y64/LH1", + "INT_R_X25Y128/WW2BEG1", + "INT_R_X25Y128/WW4END2", + "INT_R_X27Y128/WW4B2", + "INT_R_X29Y128/NW6END2", + "INT_R_X29Y128/WW4BEG2", + "INT_R_X31Y100/LV18", + "INT_R_X31Y100/LVB0", + "INT_R_X31Y101/LVB1", + "INT_R_X31Y102/LVB2", + "INT_R_X31Y103/LVB3", + "INT_R_X31Y104/LVB4", + "INT_R_X31Y105/LVB5", + "INT_R_X31Y106/LVB6", + "INT_R_X31Y107/LVB7", + "INT_R_X31Y108/LVB8", + "INT_R_X31Y109/LVB9", + "INT_R_X31Y110/LVB10", + "INT_R_X31Y111/LVB11", + "INT_R_X31Y112/LVB0", + "INT_R_X31Y112/LVB12", + "INT_R_X31Y113/LVB1", + "INT_R_X31Y114/LVB2", + "INT_R_X31Y115/LVB3", + "INT_R_X31Y116/LVB4", + "INT_R_X31Y117/LVB5", + "INT_R_X31Y118/LVB6", + "INT_R_X31Y119/LVB7", + "INT_R_X31Y120/LVB8", + "INT_R_X31Y121/LVB9", + "INT_R_X31Y122/LVB10", + "INT_R_X31Y123/LVB11", + "INT_R_X31Y124/LVB12", + "INT_R_X31Y124/NW6BEG2", + "INT_R_X31Y64/LH12", + "INT_R_X31Y64/LV0", + "INT_R_X31Y65/LV1", + "INT_R_X31Y66/LV2", + "INT_R_X31Y67/LV3", + "INT_R_X31Y68/LV4", + "INT_R_X31Y69/LV5", + "INT_R_X31Y70/LV6", + "INT_R_X31Y71/LV7", + "INT_R_X31Y72/LV8", + "INT_R_X31Y73/LV9", + "INT_R_X31Y74/LV10", + "INT_R_X31Y75/LV11", + "INT_R_X31Y76/LV12", + "INT_R_X31Y77/LV13", + "INT_R_X31Y78/LV14", + "INT_R_X31Y79/LV15", + "INT_R_X31Y80/LV16", + "INT_R_X31Y81/LV17", + "INT_R_X31Y82/LV0", + "INT_R_X31Y82/LV18", + "INT_R_X31Y83/LV1", + "INT_R_X31Y84/LV2", + "INT_R_X31Y85/LV3", + "INT_R_X31Y86/LV4", + "INT_R_X31Y87/LV5", + "INT_R_X31Y88/LV6", + "INT_R_X31Y89/LV7", + "INT_R_X31Y90/LV8", + "INT_R_X31Y91/LV9", + "INT_R_X31Y92/LV10", + "INT_R_X31Y93/LV11", + "INT_R_X31Y94/LV12", + "INT_R_X31Y95/LV13", + "INT_R_X31Y96/LV14", + "INT_R_X31Y97/LV15", + "INT_R_X31Y98/LV16", + "INT_R_X31Y99/LV17", + "INT_R_X33Y64/LH10", + "INT_R_X35Y64/LH8", + "INT_R_X37Y64/LH6", + "INT_R_X39Y64/LH4", + "INT_R_X41Y64/LH2", + "INT_R_X43Y45/LOGIC_OUTS18", + "INT_R_X43Y45/NR1BEG0", + "INT_R_X43Y46/LV0", + "INT_R_X43Y46/NR1END0", + "INT_R_X43Y47/LV1", + "INT_R_X43Y48/LV2", + "INT_R_X43Y49/LV3", + "INT_R_X43Y50/LV4", + "INT_R_X43Y51/LV5", + "INT_R_X43Y52/LV6", + "INT_R_X43Y53/LV7", + "INT_R_X43Y54/LV8", + "INT_R_X43Y55/LV9", + "INT_R_X43Y56/LV10", + "INT_R_X43Y57/LV11", + "INT_R_X43Y58/LV12", + "INT_R_X43Y59/LV13", + "INT_R_X43Y60/LV14", + "INT_R_X43Y61/LV15", + "INT_R_X43Y62/LV16", + "INT_R_X43Y63/LV17", + "INT_R_X43Y64/LH0", + "INT_R_X43Y64/LV18", + "IO_INT_INTERFACE_R_X43Y45/INT_INTERFACE_LOGIC_OUTS18", + "IO_INT_INTERFACE_R_X43Y45/INT_INTERFACE_LOGIC_OUTS_B18", + "RIOB33_X43Y45/IOB_IBUF1", + "RIOI3_X43Y45/IOI_ILOGIC1_O", + "RIOI3_X43Y45/IOI_LOGIC_OUTS18_0", + "RIOI3_X43Y45/RIOI_I1", + "RIOI3_X43Y45/RIOI_IBUF1", + "RIOI3_X43Y45/RIOI_ILOGIC1_D", + "R_TERM_INT_X112Y47/TERM_INT_LOGIC_OUTS_L_B18", + "VBRK_X105Y67/VBRK_LH2", + "VBRK_X61Y134/VBRK_WW2END1", + "VBRK_X66Y134/VBRK_WW4END2", + "VBRK_X80Y67/VBRK_LH12", + "VBRK_X85Y67/VBRK_LH10", + "VBRK_X96Y67/VBRK_LH6" + ] + }, + { + "name": "din[10]", + "node": "INT_R_X25Y130/WW2BEG1", + "pin": "T2", + "wire": "VBRK_X61Y136/VBRK_WW2END1", + "wires_outside_roi": [ + "BRAM_INT_INTERFACE_L_X30Y130/INT_INTERFACE_NW4END2", + "BRAM_INT_INTERFACE_R_X37Y66/INT_INTERFACE_LH6", + "BRAM_L_X30Y130/BRAM_NW4END2_0", + "BRAM_R_X37Y65/BRAM_LH6_1", + "BRKH_INT_X31Y99/BRKH_INT_LV15", + "BRKH_INT_X43Y49/BRKH_INT_LV1", + "CLBLL_L_X24Y130/CLBLL_WW2END1", + "CLBLL_L_X26Y130/CLBLL_WW4END2", + "CLBLL_L_X28Y130/CLBLL_WW4B2", + "CLBLL_L_X38Y66/CLBLL_LH6", + "CLBLL_L_X40Y66/CLBLL_LH4", + "CLBLL_R_X31Y66/CLBLL_LH12", + "CLBLM_L_X32Y66/CLBLM_LH12", + "CLBLM_L_X36Y66/CLBLM_LH8", + "CLBLM_R_X25Y130/CLBLM_WW4END2", + "CLBLM_R_X27Y130/CLBLM_WW4B2", + "CLBLM_R_X29Y130/CLBLM_NW4END2", + "CLBLM_R_X33Y66/CLBLM_LH10", + "CLBLM_R_X35Y66/CLBLM_LH8", + "CLBLM_R_X39Y66/CLBLM_LH4", + "CLBLM_R_X41Y66/CLBLM_LH2", + "CLK_FEED_X60Y136/CLK_FEED_WW2END1", + "CMT_FIFO_L_X107Y72/CMT_FIFO_LH2_3", + "CMT_TOP_L_LOWER_T_X106Y70/CMT_TOP_LH2_0", + "DSP_L_X34Y65/DSP_LH10_1", + "HCLK_R_X78Y130/HCLK_LVB11", + "HCLK_R_X78Y78/HCLK_LV8", + "INT_INTERFACE_L_X34Y66/INT_INTERFACE_LH10", + "INT_INTERFACE_L_X42Y66/INT_INTERFACE_LH2", + "INT_INTERFACE_R_X23Y130/INT_INTERFACE_WW2END1", + "INT_L_X24Y130/WW2A1", + "INT_L_X26Y130/WW4C2", + "INT_L_X28Y130/WW4A2", + "INT_L_X30Y126/NW6A2", + "INT_L_X30Y127/NW6B2", + "INT_L_X30Y128/NW6C2", + "INT_L_X30Y129/NW6D2", + "INT_L_X30Y130/NW6E2", + "INT_L_X32Y66/LH11", + "INT_L_X34Y66/LH9", + "INT_L_X36Y66/LH7", + "INT_L_X38Y66/LH5", + "INT_L_X40Y66/LH3", + "INT_L_X42Y66/LH1", + "INT_R_X25Y130/WW2BEG1", + "INT_R_X25Y130/WW4END2", + "INT_R_X27Y130/WW4B2", + "INT_R_X29Y130/NW6END2", + "INT_R_X29Y130/WW4BEG2", + "INT_R_X31Y100/LV16", + "INT_R_X31Y101/LV17", + "INT_R_X31Y102/LV18", + "INT_R_X31Y102/LVB0", + "INT_R_X31Y103/LVB1", + "INT_R_X31Y104/LVB2", + "INT_R_X31Y105/LVB3", + "INT_R_X31Y106/LVB4", + "INT_R_X31Y107/LVB5", + "INT_R_X31Y108/LVB6", + "INT_R_X31Y109/LVB7", + "INT_R_X31Y110/LVB8", + "INT_R_X31Y111/LVB9", + "INT_R_X31Y112/LVB10", + "INT_R_X31Y113/LVB11", + "INT_R_X31Y114/LVB0", + "INT_R_X31Y114/LVB12", + "INT_R_X31Y115/LVB1", + "INT_R_X31Y116/LVB2", + "INT_R_X31Y117/LVB3", + "INT_R_X31Y118/LVB4", + "INT_R_X31Y119/LVB5", + "INT_R_X31Y120/LVB6", + "INT_R_X31Y121/LVB7", + "INT_R_X31Y122/LVB8", + "INT_R_X31Y123/LVB9", + "INT_R_X31Y124/LVB10", + "INT_R_X31Y125/LVB11", + "INT_R_X31Y126/LVB12", + "INT_R_X31Y126/NW6BEG2", + "INT_R_X31Y66/LH12", + "INT_R_X31Y66/LV0", + "INT_R_X31Y67/LV1", + "INT_R_X31Y68/LV2", + "INT_R_X31Y69/LV3", + "INT_R_X31Y70/LV4", + "INT_R_X31Y71/LV5", + "INT_R_X31Y72/LV6", + "INT_R_X31Y73/LV7", + "INT_R_X31Y74/LV8", + "INT_R_X31Y75/LV9", + "INT_R_X31Y76/LV10", + "INT_R_X31Y77/LV11", + "INT_R_X31Y78/LV12", + "INT_R_X31Y79/LV13", + "INT_R_X31Y80/LV14", + "INT_R_X31Y81/LV15", + "INT_R_X31Y82/LV16", + "INT_R_X31Y83/LV17", + "INT_R_X31Y84/LV0", + "INT_R_X31Y84/LV18", + "INT_R_X31Y85/LV1", + "INT_R_X31Y86/LV2", + "INT_R_X31Y87/LV3", + "INT_R_X31Y88/LV4", + "INT_R_X31Y89/LV5", + "INT_R_X31Y90/LV6", + "INT_R_X31Y91/LV7", + "INT_R_X31Y92/LV8", + "INT_R_X31Y93/LV9", + "INT_R_X31Y94/LV10", + "INT_R_X31Y95/LV11", + "INT_R_X31Y96/LV12", + "INT_R_X31Y97/LV13", + "INT_R_X31Y98/LV14", + "INT_R_X31Y99/LV15", + "INT_R_X33Y66/LH10", + "INT_R_X35Y66/LH8", + "INT_R_X37Y66/LH6", + "INT_R_X39Y66/LH4", + "INT_R_X41Y66/LH2", + "INT_R_X43Y47/LOGIC_OUTS18", + "INT_R_X43Y47/NR1BEG0", + "INT_R_X43Y48/LV0", + "INT_R_X43Y48/NR1END0", + "INT_R_X43Y49/LV1", + "INT_R_X43Y50/LV2", + "INT_R_X43Y51/LV3", + "INT_R_X43Y52/LV4", + "INT_R_X43Y53/LV5", + "INT_R_X43Y54/LV6", + "INT_R_X43Y55/LV7", + "INT_R_X43Y56/LV8", + "INT_R_X43Y57/LV9", + "INT_R_X43Y58/LV10", + "INT_R_X43Y59/LV11", + "INT_R_X43Y60/LV12", + "INT_R_X43Y61/LV13", + "INT_R_X43Y62/LV14", + "INT_R_X43Y63/LV15", + "INT_R_X43Y64/LV16", + "INT_R_X43Y65/LV17", + "INT_R_X43Y66/LH0", + "INT_R_X43Y66/LV18", + "IO_INT_INTERFACE_R_X43Y47/INT_INTERFACE_LOGIC_OUTS18", + "IO_INT_INTERFACE_R_X43Y47/INT_INTERFACE_LOGIC_OUTS_B18", + "RIOB33_X43Y47/IOB_IBUF1", + "RIOI3_X43Y47/IOI_ILOGIC1_O", + "RIOI3_X43Y47/IOI_LOGIC_OUTS18_0", + "RIOI3_X43Y47/RIOI_I1", + "RIOI3_X43Y47/RIOI_IBUF1", + "RIOI3_X43Y47/RIOI_ILOGIC1_D", + "R_TERM_INT_X112Y49/TERM_INT_LOGIC_OUTS_L_B18", + "VBRK_X105Y69/VBRK_LH2", + "VBRK_X61Y136/VBRK_WW2END1", + "VBRK_X66Y136/VBRK_WW4END2", + "VBRK_X80Y69/VBRK_LH12", + "VBRK_X85Y69/VBRK_LH10", + "VBRK_X96Y69/VBRK_LH6" + ] + }, + { + "name": "din[11]", + "node": "INT_R_X25Y132/WW2BEG1", + "pin": "R3", + "wire": "VBRK_X61Y138/VBRK_WW2END1", + "wires_outside_roi": [ + "BRAM_INT_INTERFACE_L_X30Y129/INT_INTERFACE_NW4END3", + "BRAM_INT_INTERFACE_R_X37Y65/INT_INTERFACE_LH6", + "BRAM_L_X30Y125/BRAM_NW4END3_4", + "BRAM_R_X37Y65/BRAM_LH6_0", + "BRKH_INT_X31Y99/BRKH_INT_LV16", + "BRKH_INT_X43Y49/BRKH_INT_LV2", + "CLBLL_L_X24Y132/CLBLL_WW2END1", + "CLBLL_L_X26Y132/CLBLL_WW4END2", + "CLBLL_L_X28Y132/CLBLL_WW4B2", + "CLBLL_L_X38Y65/CLBLL_LH6", + "CLBLL_L_X40Y65/CLBLL_LH4", + "CLBLL_R_X31Y65/CLBLL_LH12", + "CLBLM_L_X32Y65/CLBLM_LH12", + "CLBLM_L_X36Y65/CLBLM_LH8", + "CLBLM_R_X25Y132/CLBLM_WW4END2", + "CLBLM_R_X27Y132/CLBLM_WW4B2", + "CLBLM_R_X29Y129/CLBLM_NW4END3", + "CLBLM_R_X33Y65/CLBLM_LH10", + "CLBLM_R_X35Y65/CLBLM_LH8", + "CLBLM_R_X39Y65/CLBLM_LH4", + "CLBLM_R_X41Y65/CLBLM_LH2", + "CLK_FEED_X60Y138/CLK_FEED_WW2END1", + "CMT_FIFO_L_X107Y72/CMT_FIFO_LH2_2", + "CMT_TOP_L_LOWER_B_X106Y61/CMT_TOP_LH2_15", + "DSP_L_X34Y65/DSP_LH10_0", + "HCLK_R_BOT_UTURN_X73Y130/B_TERM_UTURN_INT_LVB4", + "HCLK_R_X78Y130/HCLK_NN6E3", + "HCLK_R_X78Y78/HCLK_LV9", + "INT_INTERFACE_L_X34Y65/INT_INTERFACE_LH10", + "INT_INTERFACE_L_X42Y65/INT_INTERFACE_LH2", + "INT_INTERFACE_R_X23Y132/INT_INTERFACE_WW2END1", + "INT_L_X24Y132/WW2A1", + "INT_L_X26Y132/WW4C2", + "INT_L_X28Y132/WW4A2", + "INT_L_X30Y125/NW6A3", + "INT_L_X30Y126/NW6B3", + "INT_L_X30Y127/NW6C3", + "INT_L_X30Y128/NW6D3", + "INT_L_X30Y129/NW6E3", + "INT_L_X32Y65/LH11", + "INT_L_X34Y65/LH9", + "INT_L_X36Y65/LH7", + "INT_L_X38Y65/LH5", + "INT_L_X40Y65/LH3", + "INT_L_X42Y65/LH1", + "INT_R_X25Y132/WW2BEG1", + "INT_R_X25Y132/WW4END2", + "INT_R_X27Y132/WW4B2", + "INT_R_X29Y125/LVB5", + "INT_R_X29Y125/LVB8", + "INT_R_X29Y126/LVB6", + "INT_R_X29Y126/LVB9", + "INT_R_X29Y127/LVB10", + "INT_R_X29Y127/LVB7", + "INT_R_X29Y128/LVB11", + "INT_R_X29Y128/LVB8", + "INT_R_X29Y129/LVB12", + "INT_R_X29Y129/LVB9", + "INT_R_X29Y129/NW6END3", + "INT_R_X29Y130/LVB10", + "INT_R_X29Y131/LVB11", + "INT_R_X29Y132/LVB12", + "INT_R_X29Y132/WW4BEG2", + "INT_R_X31Y100/LV17", + "INT_R_X31Y101/LV0", + "INT_R_X31Y101/LV18", + "INT_R_X31Y102/LV1", + "INT_R_X31Y103/LV2", + "INT_R_X31Y104/LV3", + "INT_R_X31Y105/LV4", + "INT_R_X31Y106/LV5", + "INT_R_X31Y107/LV6", + "INT_R_X31Y108/LV7", + "INT_R_X31Y109/LV8", + "INT_R_X31Y110/LV9", + "INT_R_X31Y111/LV10", + "INT_R_X31Y112/LV11", + "INT_R_X31Y113/LV12", + "INT_R_X31Y114/LV13", + "INT_R_X31Y115/LV14", + "INT_R_X31Y116/LV15", + "INT_R_X31Y117/LV16", + "INT_R_X31Y118/LV17", + "INT_R_X31Y119/LV18", + "INT_R_X31Y119/NN6BEG3", + "INT_R_X31Y120/NN6A3", + "INT_R_X31Y121/NN6B3", + "INT_R_X31Y122/NN6C3", + "INT_R_X31Y123/NN6D3", + "INT_R_X31Y124/NN6E3", + "INT_R_X31Y125/NN6END3", + "INT_R_X31Y125/NW6BEG3", + "INT_R_X31Y65/LH12", + "INT_R_X31Y65/LV0", + "INT_R_X31Y66/LV1", + "INT_R_X31Y67/LV2", + "INT_R_X31Y68/LV3", + "INT_R_X31Y69/LV4", + "INT_R_X31Y70/LV5", + "INT_R_X31Y71/LV6", + "INT_R_X31Y72/LV7", + "INT_R_X31Y73/LV8", + "INT_R_X31Y74/LV9", + "INT_R_X31Y75/LV10", + "INT_R_X31Y76/LV11", + "INT_R_X31Y77/LV12", + "INT_R_X31Y78/LV13", + "INT_R_X31Y79/LV14", + "INT_R_X31Y80/LV15", + "INT_R_X31Y81/LV16", + "INT_R_X31Y82/LV17", + "INT_R_X31Y83/LV0", + "INT_R_X31Y83/LV18", + "INT_R_X31Y84/LV1", + "INT_R_X31Y85/LV2", + "INT_R_X31Y86/LV3", + "INT_R_X31Y87/LV4", + "INT_R_X31Y88/LV5", + "INT_R_X31Y89/LV6", + "INT_R_X31Y90/LV7", + "INT_R_X31Y91/LV8", + "INT_R_X31Y92/LV9", + "INT_R_X31Y93/LV10", + "INT_R_X31Y94/LV11", + "INT_R_X31Y95/LV12", + "INT_R_X31Y96/LV13", + "INT_R_X31Y97/LV14", + "INT_R_X31Y98/LV15", + "INT_R_X31Y99/LV16", + "INT_R_X33Y65/LH10", + "INT_R_X35Y65/LH8", + "INT_R_X37Y65/LH6", + "INT_R_X39Y65/LH4", + "INT_R_X41Y65/LH2", + "INT_R_X43Y46/LOGIC_OUTS18", + "INT_R_X43Y46/NR1BEG0", + "INT_R_X43Y47/LV0", + "INT_R_X43Y47/NR1END0", + "INT_R_X43Y48/LV1", + "INT_R_X43Y49/LV2", + "INT_R_X43Y50/LV3", + "INT_R_X43Y51/LV4", + "INT_R_X43Y52/LV5", + "INT_R_X43Y53/LV6", + "INT_R_X43Y54/LV7", + "INT_R_X43Y55/LV8", + "INT_R_X43Y56/LV9", + "INT_R_X43Y57/LV10", + "INT_R_X43Y58/LV11", + "INT_R_X43Y59/LV12", + "INT_R_X43Y60/LV13", + "INT_R_X43Y61/LV14", + "INT_R_X43Y62/LV15", + "INT_R_X43Y63/LV16", + "INT_R_X43Y64/LV17", + "INT_R_X43Y65/LH0", + "INT_R_X43Y65/LV18", + "IO_INT_INTERFACE_R_X43Y46/INT_INTERFACE_LOGIC_OUTS18", + "IO_INT_INTERFACE_R_X43Y46/INT_INTERFACE_LOGIC_OUTS_B18", + "RIOB33_X43Y45/IOB_IBUF0", + "RIOI3_X43Y45/IOI_ILOGIC0_O", + "RIOI3_X43Y45/IOI_LOGIC_OUTS18_1", + "RIOI3_X43Y45/RIOI_I0", + "RIOI3_X43Y45/RIOI_IBUF0", + "RIOI3_X43Y45/RIOI_ILOGIC0_D", + "R_TERM_INT_X112Y48/TERM_INT_LOGIC_OUTS_L_B18", + "VBRK_X105Y68/VBRK_LH2", + "VBRK_X61Y138/VBRK_WW2END1", + "VBRK_X66Y138/VBRK_WW4END2", + "VBRK_X80Y68/VBRK_LH12", + "VBRK_X85Y68/VBRK_LH10", + "VBRK_X96Y68/VBRK_LH6" + ] + }, + { + "name": "din[12]", + "node": "INT_R_X25Y134/WW2BEG1", + "pin": "W2", + "wire": "VBRK_X61Y140/VBRK_WW2END1", + "wires_outside_roi": [ + "BRAM_INT_INTERFACE_L_X30Y134/INT_INTERFACE_NW4END3", + "BRAM_INT_INTERFACE_R_X37Y58/INT_INTERFACE_LH6", + "BRAM_L_X30Y130/BRAM_NW4END3_4", + "BRAM_R_X37Y55/BRAM_LH6_3", + "BRKH_INT_X31Y99/BRKH_INT_LV5", + "BRKH_INT_X43Y49/BRKH_INT_LV9", + "CLBLL_L_X24Y134/CLBLL_WW2END1", + "CLBLL_L_X26Y134/CLBLL_WW4END2", + "CLBLL_L_X28Y134/CLBLL_WW4B2", + "CLBLL_L_X38Y58/CLBLL_LH6", + "CLBLL_L_X40Y58/CLBLL_LH4", + "CLBLL_R_X31Y58/CLBLL_LH12", + "CLBLM_L_X32Y58/CLBLM_LH12", + "CLBLM_L_X36Y58/CLBLM_LH8", + "CLBLM_R_X25Y134/CLBLM_WW4END2", + "CLBLM_R_X27Y134/CLBLM_WW4B2", + "CLBLM_R_X29Y134/CLBLM_NW4END3", + "CLBLM_R_X33Y58/CLBLM_LH10", + "CLBLM_R_X35Y58/CLBLM_LH8", + "CLBLM_R_X39Y58/CLBLM_LH4", + "CLBLM_R_X41Y58/CLBLM_LH2", + "CLK_FEED_X60Y140/CLK_FEED_WW2END1", + "CMT_FIFO_L_X107Y60/CMT_FIFO_LH2_7", + "CMT_TOP_L_LOWER_B_X106Y61/CMT_TOP_LH2_8", + "DSP_L_X34Y55/DSP_LH10_3", + "HCLK_R_BOT_UTURN_X73Y130/B_TERM_UTURN_INT_LVB2", + "HCLK_R_X78Y130/HCLK_LV12", + "HCLK_R_X78Y78/HCLK_LV16", + "INT_INTERFACE_L_X34Y58/INT_INTERFACE_LH10", + "INT_INTERFACE_L_X42Y58/INT_INTERFACE_LH2", + "INT_INTERFACE_R_X23Y134/INT_INTERFACE_WW2END1", + "INT_L_X24Y134/WW2A1", + "INT_L_X26Y134/WW4C2", + "INT_L_X28Y134/WW4A2", + "INT_L_X30Y130/NW6A3", + "INT_L_X30Y131/NW6B3", + "INT_L_X30Y132/NW6C3", + "INT_L_X30Y133/NW6D3", + "INT_L_X30Y134/NW6E3", + "INT_L_X32Y58/LH11", + "INT_L_X34Y58/LH9", + "INT_L_X36Y58/LH7", + "INT_L_X38Y58/LH5", + "INT_L_X40Y58/LH3", + "INT_L_X42Y58/LH1", + "INT_R_X25Y134/WW2BEG1", + "INT_R_X25Y134/WW4END2", + "INT_R_X27Y134/WW4B2", + "INT_R_X29Y125/LVB10", + "INT_R_X29Y125/LVB3", + "INT_R_X29Y126/LVB11", + "INT_R_X29Y126/LVB4", + "INT_R_X29Y127/LVB12", + "INT_R_X29Y127/LVB5", + "INT_R_X29Y128/LVB6", + "INT_R_X29Y129/LVB7", + "INT_R_X29Y130/LVB8", + "INT_R_X29Y131/LVB9", + "INT_R_X29Y132/LVB10", + "INT_R_X29Y133/LVB11", + "INT_R_X29Y134/LVB12", + "INT_R_X29Y134/NW6END3", + "INT_R_X29Y134/WW4BEG2", + "INT_R_X31Y100/LV6", + "INT_R_X31Y101/LV7", + "INT_R_X31Y102/LV8", + "INT_R_X31Y103/LV9", + "INT_R_X31Y104/LV10", + "INT_R_X31Y105/LV11", + "INT_R_X31Y106/LV12", + "INT_R_X31Y107/LV13", + "INT_R_X31Y108/LV14", + "INT_R_X31Y109/LV15", + "INT_R_X31Y110/LV16", + "INT_R_X31Y111/LV17", + "INT_R_X31Y112/LV0", + "INT_R_X31Y112/LV18", + "INT_R_X31Y113/LV1", + "INT_R_X31Y114/LV2", + "INT_R_X31Y115/LV3", + "INT_R_X31Y116/LV4", + "INT_R_X31Y117/LV5", + "INT_R_X31Y118/LV6", + "INT_R_X31Y119/LV7", + "INT_R_X31Y120/LV8", + "INT_R_X31Y121/LV9", + "INT_R_X31Y122/LV10", + "INT_R_X31Y123/LV11", + "INT_R_X31Y124/LV12", + "INT_R_X31Y125/LV13", + "INT_R_X31Y126/LV14", + "INT_R_X31Y127/LV15", + "INT_R_X31Y128/LV16", + "INT_R_X31Y129/LV17", + "INT_R_X31Y130/LV18", + "INT_R_X31Y130/NW6BEG3", + "INT_R_X31Y58/LH12", + "INT_R_X31Y58/LV0", + "INT_R_X31Y59/LV1", + "INT_R_X31Y60/LV2", + "INT_R_X31Y61/LV3", + "INT_R_X31Y62/LV4", + "INT_R_X31Y63/LV5", + "INT_R_X31Y64/LV6", + "INT_R_X31Y65/LV7", + "INT_R_X31Y66/LV8", + "INT_R_X31Y67/LV9", + "INT_R_X31Y68/LV10", + "INT_R_X31Y69/LV11", + "INT_R_X31Y70/LV12", + "INT_R_X31Y71/LV13", + "INT_R_X31Y72/LV14", + "INT_R_X31Y73/LV15", + "INT_R_X31Y74/LV16", + "INT_R_X31Y75/LV17", + "INT_R_X31Y76/LV0", + "INT_R_X31Y76/LV18", + "INT_R_X31Y77/LV1", + "INT_R_X31Y78/LV2", + "INT_R_X31Y79/LV3", + "INT_R_X31Y80/LV4", + "INT_R_X31Y81/LV5", + "INT_R_X31Y82/LV6", + "INT_R_X31Y83/LV7", + "INT_R_X31Y84/LV8", + "INT_R_X31Y85/LV9", + "INT_R_X31Y86/LV10", + "INT_R_X31Y87/LV11", + "INT_R_X31Y88/LV12", + "INT_R_X31Y89/LV13", + "INT_R_X31Y90/LV14", + "INT_R_X31Y91/LV15", + "INT_R_X31Y92/LV16", + "INT_R_X31Y93/LV17", + "INT_R_X31Y94/LV0", + "INT_R_X31Y94/LV18", + "INT_R_X31Y95/LV1", + "INT_R_X31Y96/LV2", + "INT_R_X31Y97/LV3", + "INT_R_X31Y98/LV4", + "INT_R_X31Y99/LV5", + "INT_R_X33Y58/LH10", + "INT_R_X35Y58/LH8", + "INT_R_X37Y58/LH6", + "INT_R_X39Y58/LH4", + "INT_R_X41Y58/LH2", + "INT_R_X43Y39/LOGIC_OUTS18", + "INT_R_X43Y39/NR1BEG0", + "INT_R_X43Y40/LV0", + "INT_R_X43Y40/NR1END0", + "INT_R_X43Y41/LV1", + "INT_R_X43Y42/LV2", + "INT_R_X43Y43/LV3", + "INT_R_X43Y44/LV4", + "INT_R_X43Y45/LV5", + "INT_R_X43Y46/LV6", + "INT_R_X43Y47/LV7", + "INT_R_X43Y48/LV8", + "INT_R_X43Y49/LV9", + "INT_R_X43Y50/LV10", + "INT_R_X43Y51/LV11", + "INT_R_X43Y52/LV12", + "INT_R_X43Y53/LV13", + "INT_R_X43Y54/LV14", + "INT_R_X43Y55/LV15", + "INT_R_X43Y56/LV16", + "INT_R_X43Y57/LV17", + "INT_R_X43Y58/LH0", + "INT_R_X43Y58/LV18", + "IO_INT_INTERFACE_R_X43Y39/INT_INTERFACE_LOGIC_OUTS18", + "IO_INT_INTERFACE_R_X43Y39/INT_INTERFACE_LOGIC_OUTS_B18", + "RIOB33_X43Y39/IOB_IBUF1", + "RIOI3_X43Y39/IOI_ILOGIC1_O", + "RIOI3_X43Y39/IOI_LOGIC_OUTS18_0", + "RIOI3_X43Y39/RIOI_I1", + "RIOI3_X43Y39/RIOI_IBUF1", + "RIOI3_X43Y39/RIOI_ILOGIC1_D", + "R_TERM_INT_X112Y41/TERM_INT_LOGIC_OUTS_L_B18", + "VBRK_X105Y61/VBRK_LH2", + "VBRK_X61Y140/VBRK_WW2END1", + "VBRK_X66Y140/VBRK_WW4END2", + "VBRK_X80Y61/VBRK_LH12", + "VBRK_X85Y61/VBRK_LH10", + "VBRK_X96Y61/VBRK_LH6" + ] + }, + { + "name": "din[13]", + "node": "INT_R_X25Y136/WW2BEG1", + "pin": "U1", + "wire": "VBRK_X61Y142/VBRK_WW2END1", + "wires_outside_roi": [ + "BRAM_INT_INTERFACE_L_X30Y132/INT_INTERFACE_NW4END2", + "BRAM_INT_INTERFACE_R_X37Y62/INT_INTERFACE_LH6", + "BRAM_L_X30Y130/BRAM_NW4END2_2", + "BRAM_R_X37Y60/BRAM_LH6_2", + "BRKH_INT_X31Y99/BRKH_INT_LV1", + "BRKH_INT_X43Y49/BRKH_INT_LV5", + "CLBLL_L_X24Y136/CLBLL_WW2END1", + "CLBLL_L_X26Y136/CLBLL_WW2END1", + "CLBLL_L_X28Y136/CLBLL_NW4END2", + "CLBLL_L_X38Y62/CLBLL_LH6", + "CLBLL_L_X40Y62/CLBLL_LH4", + "CLBLL_R_X31Y62/CLBLL_LH12", + "CLBLM_L_X32Y62/CLBLM_LH12", + "CLBLM_L_X36Y62/CLBLM_LH8", + "CLBLM_R_X25Y136/CLBLM_WW2END1", + "CLBLM_R_X27Y136/CLBLM_NW4END2", + "CLBLM_R_X29Y132/CLBLM_NW4END2", + "CLBLM_R_X33Y62/CLBLM_LH10", + "CLBLM_R_X35Y62/CLBLM_LH8", + "CLBLM_R_X39Y62/CLBLM_LH4", + "CLBLM_R_X41Y62/CLBLM_LH2", + "CLK_BUFG_REBUF_X60Y142/CLK_BUFG_REBUF_WW2END1_0", + "CMT_FIFO_L_X107Y60/CMT_FIFO_LH2_11", + "CMT_TOP_L_LOWER_B_X106Y61/CMT_TOP_LH2_12", + "DSP_L_X34Y60/DSP_LH10_2", + "HCLK_R_X78Y130/HCLK_LVB9", + "HCLK_R_X78Y78/HCLK_LV12", + "INT_INTERFACE_L_X34Y62/INT_INTERFACE_LH10", + "INT_INTERFACE_L_X42Y62/INT_INTERFACE_LH2", + "INT_INTERFACE_R_X23Y136/INT_INTERFACE_WW2END1", + "INT_L_X24Y136/WW2A1", + "INT_L_X26Y136/WW2A1", + "INT_L_X28Y132/NW6A2", + "INT_L_X28Y133/NW6B2", + "INT_L_X28Y134/NW6C2", + "INT_L_X28Y135/NW6D2", + "INT_L_X28Y136/NW6E2", + "INT_L_X30Y128/NW6A2", + "INT_L_X30Y129/NW6B2", + "INT_L_X30Y130/NW6C2", + "INT_L_X30Y131/NW6D2", + "INT_L_X30Y132/NW6E2", + "INT_L_X32Y62/LH11", + "INT_L_X34Y62/LH9", + "INT_L_X36Y62/LH7", + "INT_L_X38Y62/LH5", + "INT_L_X40Y62/LH3", + "INT_L_X42Y62/LH1", + "INT_R_X25Y136/WW2BEG1", + "INT_R_X25Y136/WW2END1", + "INT_R_X27Y136/NW6END2", + "INT_R_X27Y136/WW2BEG1", + "INT_R_X29Y132/NW6BEG2", + "INT_R_X29Y132/NW6END2", + "INT_R_X31Y100/LV2", + "INT_R_X31Y101/LV3", + "INT_R_X31Y102/LV4", + "INT_R_X31Y103/LV5", + "INT_R_X31Y104/LV6", + "INT_R_X31Y105/LV7", + "INT_R_X31Y106/LV8", + "INT_R_X31Y107/LV9", + "INT_R_X31Y108/LV10", + "INT_R_X31Y109/LV11", + "INT_R_X31Y110/LV12", + "INT_R_X31Y111/LV13", + "INT_R_X31Y112/LV14", + "INT_R_X31Y113/LV15", + "INT_R_X31Y114/LV16", + "INT_R_X31Y115/LV17", + "INT_R_X31Y116/LV18", + "INT_R_X31Y116/LVB0", + "INT_R_X31Y117/LVB1", + "INT_R_X31Y118/LVB2", + "INT_R_X31Y119/LVB3", + "INT_R_X31Y120/LVB4", + "INT_R_X31Y121/LVB5", + "INT_R_X31Y122/LVB6", + "INT_R_X31Y123/LVB7", + "INT_R_X31Y124/LVB8", + "INT_R_X31Y125/LVB9", + "INT_R_X31Y126/LVB10", + "INT_R_X31Y127/LVB11", + "INT_R_X31Y128/LVB12", + "INT_R_X31Y128/NW6BEG2", + "INT_R_X31Y62/LH12", + "INT_R_X31Y62/LV0", + "INT_R_X31Y63/LV1", + "INT_R_X31Y64/LV2", + "INT_R_X31Y65/LV3", + "INT_R_X31Y66/LV4", + "INT_R_X31Y67/LV5", + "INT_R_X31Y68/LV6", + "INT_R_X31Y69/LV7", + "INT_R_X31Y70/LV8", + "INT_R_X31Y71/LV9", + "INT_R_X31Y72/LV10", + "INT_R_X31Y73/LV11", + "INT_R_X31Y74/LV12", + "INT_R_X31Y75/LV13", + "INT_R_X31Y76/LV14", + "INT_R_X31Y77/LV15", + "INT_R_X31Y78/LV16", + "INT_R_X31Y79/LV17", + "INT_R_X31Y80/LV0", + "INT_R_X31Y80/LV18", + "INT_R_X31Y81/LV1", + "INT_R_X31Y82/LV2", + "INT_R_X31Y83/LV3", + "INT_R_X31Y84/LV4", + "INT_R_X31Y85/LV5", + "INT_R_X31Y86/LV6", + "INT_R_X31Y87/LV7", + "INT_R_X31Y88/LV8", + "INT_R_X31Y89/LV9", + "INT_R_X31Y90/LV10", + "INT_R_X31Y91/LV11", + "INT_R_X31Y92/LV12", + "INT_R_X31Y93/LV13", + "INT_R_X31Y94/LV14", + "INT_R_X31Y95/LV15", + "INT_R_X31Y96/LV16", + "INT_R_X31Y97/LV17", + "INT_R_X31Y98/LV0", + "INT_R_X31Y98/LV18", + "INT_R_X31Y99/LV1", + "INT_R_X33Y62/LH10", + "INT_R_X35Y62/LH8", + "INT_R_X37Y62/LH6", + "INT_R_X39Y62/LH4", + "INT_R_X41Y62/LH2", + "INT_R_X43Y43/LOGIC_OUTS18", + "INT_R_X43Y43/NR1BEG0", + "INT_R_X43Y44/LV0", + "INT_R_X43Y44/NR1END0", + "INT_R_X43Y45/LV1", + "INT_R_X43Y46/LV2", + "INT_R_X43Y47/LV3", + "INT_R_X43Y48/LV4", + "INT_R_X43Y49/LV5", + "INT_R_X43Y50/LV6", + "INT_R_X43Y51/LV7", + "INT_R_X43Y52/LV8", + "INT_R_X43Y53/LV9", + "INT_R_X43Y54/LV10", + "INT_R_X43Y55/LV11", + "INT_R_X43Y56/LV12", + "INT_R_X43Y57/LV13", + "INT_R_X43Y58/LV14", + "INT_R_X43Y59/LV15", + "INT_R_X43Y60/LV16", + "INT_R_X43Y61/LV17", + "INT_R_X43Y62/LH0", + "INT_R_X43Y62/LV18", + "IO_INT_INTERFACE_R_X43Y43/INT_INTERFACE_LOGIC_OUTS18", + "IO_INT_INTERFACE_R_X43Y43/INT_INTERFACE_LOGIC_OUTS_B18", + "RIOB33_X43Y43/IOB_IBUF1", + "RIOI3_TBYTESRC_X43Y43/IOI_ILOGIC1_O", + "RIOI3_TBYTESRC_X43Y43/IOI_LOGIC_OUTS18_0", + "RIOI3_TBYTESRC_X43Y43/RIOI_I1", + "RIOI3_TBYTESRC_X43Y43/RIOI_IBUF1", + "RIOI3_TBYTESRC_X43Y43/RIOI_ILOGIC1_D", + "R_TERM_INT_X112Y45/TERM_INT_LOGIC_OUTS_L_B18", + "VBRK_X105Y65/VBRK_LH2", + "VBRK_X61Y142/VBRK_WW2END1", + "VBRK_X66Y142/VBRK_WW2END1", + "VBRK_X80Y65/VBRK_LH12", + "VBRK_X85Y65/VBRK_LH10", + "VBRK_X96Y65/VBRK_LH6" + ] + }, + { + "name": "din[14]", + "node": "INT_R_X25Y138/WW2BEG1", + "pin": "T1", + "wire": "VBRK_X61Y144/VBRK_WW2END1", + "wires_outside_roi": [ + "BRAM_INT_INTERFACE_L_X30Y135/INT_INTERFACE_LH2", + "BRAM_INT_INTERFACE_R_X37Y63/INT_INTERFACE_LH6", + "BRAM_L_X30Y135/BRAM_LH2_0", + "BRAM_R_X37Y60/BRAM_LH6_3", + "BRKH_INT_X31Y99/BRKH_INT_LV0", + "BRKH_INT_X43Y49/BRKH_INT_LV4", + "CLBLL_L_X24Y135/CLBLL_LH8", + "CLBLL_L_X24Y138/CLBLL_WW2END1", + "CLBLL_L_X26Y135/CLBLL_LH6", + "CLBLL_L_X28Y135/CLBLL_LH4", + "CLBLL_L_X38Y63/CLBLL_LH6", + "CLBLL_L_X40Y63/CLBLL_LH4", + "CLBLL_R_X31Y63/CLBLL_LH12", + "CLBLM_L_X32Y63/CLBLM_LH12", + "CLBLM_L_X36Y63/CLBLM_LH8", + "CLBLM_R_X25Y135/CLBLM_LH6", + "CLBLM_R_X27Y135/CLBLM_LH4", + "CLBLM_R_X29Y135/CLBLM_LH2", + "CLBLM_R_X33Y63/CLBLM_LH10", + "CLBLM_R_X35Y63/CLBLM_LH8", + "CLBLM_R_X39Y63/CLBLM_LH4", + "CLBLM_R_X41Y63/CLBLM_LH2", + "CLK_FEED_X60Y141/CLK_FEED_LH8", + "CLK_FEED_X60Y144/CLK_FEED_WW2END1", + "CMT_FIFO_L_X107Y72/CMT_FIFO_LH2_0", + "CMT_TOP_L_LOWER_B_X106Y61/CMT_TOP_LH2_13", + "DSP_L_X34Y60/DSP_LH10_3", + "HCLK_R_X78Y130/HCLK_LV7", + "HCLK_R_X78Y78/HCLK_LV11", + "INT_INTERFACE_L_X34Y63/INT_INTERFACE_LH10", + "INT_INTERFACE_L_X42Y63/INT_INTERFACE_LH2", + "INT_INTERFACE_R_X23Y135/INT_INTERFACE_LH8", + "INT_INTERFACE_R_X23Y138/INT_INTERFACE_WW2END1", + "INT_L_X24Y135/LH7", + "INT_L_X24Y138/WW2A1", + "INT_L_X26Y135/LH5", + "INT_L_X28Y135/LH3", + "INT_L_X30Y135/LH1", + "INT_L_X32Y63/LH11", + "INT_L_X34Y63/LH9", + "INT_L_X36Y63/LH7", + "INT_L_X38Y63/LH5", + "INT_L_X40Y63/LH3", + "INT_L_X42Y63/LH1", + "INT_R_X25Y135/LH6", + "INT_R_X25Y135/LV0", + "INT_R_X25Y136/LV1", + "INT_R_X25Y137/LV2", + "INT_R_X25Y138/LV3", + "INT_R_X25Y138/SS6END1", + "INT_R_X25Y138/WW2BEG1", + "INT_R_X25Y139/LV4", + "INT_R_X25Y139/SS6E1", + "INT_R_X25Y140/LV5", + "INT_R_X25Y140/SS6D1", + "INT_R_X25Y141/LV6", + "INT_R_X25Y141/SS6C1", + "INT_R_X25Y142/LV7", + "INT_R_X25Y142/SS6B1", + "INT_R_X25Y143/LV8", + "INT_R_X25Y143/SS6A1", + "INT_R_X25Y144/LV9", + "INT_R_X25Y144/SS6BEG1", + "INT_R_X25Y145/LV10", + "INT_R_X25Y146/LV0", + "INT_R_X25Y146/LV11", + "INT_R_X25Y147/LV1", + "INT_R_X25Y147/LV12", + "INT_R_X25Y148/LV13", + "INT_R_X25Y148/LV2", + "INT_R_X25Y149/LV14", + "INT_R_X25Y149/LV3", + "INT_R_X27Y135/LH4", + "INT_R_X29Y135/LH2", + "INT_R_X31Y100/LV1", + "INT_R_X31Y101/LV2", + "INT_R_X31Y102/LV3", + "INT_R_X31Y103/LV4", + "INT_R_X31Y104/LV5", + "INT_R_X31Y105/LV6", + "INT_R_X31Y106/LV7", + "INT_R_X31Y107/LV8", + "INT_R_X31Y108/LV9", + "INT_R_X31Y109/LV10", + "INT_R_X31Y110/LV11", + "INT_R_X31Y111/LV12", + "INT_R_X31Y112/LV13", + "INT_R_X31Y113/LV14", + "INT_R_X31Y114/LV15", + "INT_R_X31Y115/LV16", + "INT_R_X31Y116/LV17", + "INT_R_X31Y117/LV0", + "INT_R_X31Y117/LV18", + "INT_R_X31Y118/LV1", + "INT_R_X31Y119/LV2", + "INT_R_X31Y120/LV3", + "INT_R_X31Y121/LV4", + "INT_R_X31Y122/LV5", + "INT_R_X31Y123/LV6", + "INT_R_X31Y124/LV7", + "INT_R_X31Y125/LV8", + "INT_R_X31Y126/LV9", + "INT_R_X31Y127/LV10", + "INT_R_X31Y128/LV11", + "INT_R_X31Y129/LV12", + "INT_R_X31Y130/LV13", + "INT_R_X31Y131/LV14", + "INT_R_X31Y132/LV15", + "INT_R_X31Y133/LV16", + "INT_R_X31Y134/LV17", + "INT_R_X31Y135/LH0", + "INT_R_X31Y135/LV18", + "INT_R_X31Y63/LH12", + "INT_R_X31Y63/LV0", + "INT_R_X31Y64/LV1", + "INT_R_X31Y65/LV2", + "INT_R_X31Y66/LV3", + "INT_R_X31Y67/LV4", + "INT_R_X31Y68/LV5", + "INT_R_X31Y69/LV6", + "INT_R_X31Y70/LV7", + "INT_R_X31Y71/LV8", + "INT_R_X31Y72/LV9", + "INT_R_X31Y73/LV10", + "INT_R_X31Y74/LV11", + "INT_R_X31Y75/LV12", + "INT_R_X31Y76/LV13", + "INT_R_X31Y77/LV14", + "INT_R_X31Y78/LV15", + "INT_R_X31Y79/LV16", + "INT_R_X31Y80/LV17", + "INT_R_X31Y81/LV0", + "INT_R_X31Y81/LV18", + "INT_R_X31Y82/LV1", + "INT_R_X31Y83/LV2", + "INT_R_X31Y84/LV3", + "INT_R_X31Y85/LV4", + "INT_R_X31Y86/LV5", + "INT_R_X31Y87/LV6", + "INT_R_X31Y88/LV7", + "INT_R_X31Y89/LV8", + "INT_R_X31Y90/LV9", + "INT_R_X31Y91/LV10", + "INT_R_X31Y92/LV11", + "INT_R_X31Y93/LV12", + "INT_R_X31Y94/LV13", + "INT_R_X31Y95/LV14", + "INT_R_X31Y96/LV15", + "INT_R_X31Y97/LV16", + "INT_R_X31Y98/LV17", + "INT_R_X31Y99/LV0", + "INT_R_X31Y99/LV18", + "INT_R_X33Y63/LH10", + "INT_R_X35Y63/LH8", + "INT_R_X37Y63/LH6", + "INT_R_X39Y63/LH4", + "INT_R_X41Y63/LH2", + "INT_R_X43Y44/LOGIC_OUTS18", + "INT_R_X43Y44/NR1BEG0", + "INT_R_X43Y45/LV0", + "INT_R_X43Y45/NR1END0", + "INT_R_X43Y46/LV1", + "INT_R_X43Y47/LV2", + "INT_R_X43Y48/LV3", + "INT_R_X43Y49/LV4", + "INT_R_X43Y50/LV5", + "INT_R_X43Y51/LV6", + "INT_R_X43Y52/LV7", + "INT_R_X43Y53/LV8", + "INT_R_X43Y54/LV9", + "INT_R_X43Y55/LV10", + "INT_R_X43Y56/LV11", + "INT_R_X43Y57/LV12", + "INT_R_X43Y58/LV13", + "INT_R_X43Y59/LV14", + "INT_R_X43Y60/LV15", + "INT_R_X43Y61/LV16", + "INT_R_X43Y62/LV17", + "INT_R_X43Y63/LH0", + "INT_R_X43Y63/LV18", + "IO_INT_INTERFACE_R_X43Y44/INT_INTERFACE_LOGIC_OUTS18", + "IO_INT_INTERFACE_R_X43Y44/INT_INTERFACE_LOGIC_OUTS_B18", + "RIOB33_X43Y43/IOB_IBUF0", + "RIOI3_TBYTESRC_X43Y43/IOI_ILOGIC0_O", + "RIOI3_TBYTESRC_X43Y43/IOI_LOGIC_OUTS18_1", + "RIOI3_TBYTESRC_X43Y43/RIOI_I0", + "RIOI3_TBYTESRC_X43Y43/RIOI_IBUF0", + "RIOI3_TBYTESRC_X43Y43/RIOI_ILOGIC0_D", + "R_TERM_INT_X112Y46/TERM_INT_LOGIC_OUTS_L_B18", + "T_TERM_INT_X64Y156/T_TERM_INT_UTURN_LV_R3", + "VBRK_X105Y66/VBRK_LH2", + "VBRK_X61Y141/VBRK_LH8", + "VBRK_X61Y144/VBRK_WW2END1", + "VBRK_X66Y141/VBRK_LH6", + "VBRK_X80Y66/VBRK_LH12", + "VBRK_X85Y66/VBRK_LH10", + "VBRK_X96Y66/VBRK_LH6" + ] + }, + { + "name": "din[15]", + "node": "INT_R_X25Y140/WW2BEG1", + "pin": "R2", + "wire": "VBRK_X61Y146/VBRK_WW2END1", + "wires_outside_roi": [ + "BRAM_INT_INTERFACE_L_X30Y139/INT_INTERFACE_WW4B3", + "BRAM_INT_INTERFACE_R_X37Y67/INT_INTERFACE_LH6", + "BRAM_L_X30Y135/BRAM_WW4B3_4", + "BRAM_R_X37Y65/BRAM_LH6_2", + "BRKH_INT_X31Y99/BRKH_INT_LV14", + "BRKH_INT_X43Y49/BRKH_INT_LV0", + "CLBLL_L_X24Y140/CLBLL_WW2END1", + "CLBLL_L_X26Y140/CLBLL_WL1END1", + "CLBLL_L_X28Y139/CLBLL_WW4END3", + "CLBLL_L_X38Y67/CLBLL_LH6", + "CLBLL_L_X40Y67/CLBLL_LH4", + "CLBLL_R_X31Y67/CLBLL_LH12", + "CLBLM_L_X32Y67/CLBLM_LH12", + "CLBLM_L_X36Y67/CLBLM_LH8", + "CLBLM_R_X25Y140/CLBLM_WL1END1", + "CLBLM_R_X27Y139/CLBLM_WW4END3", + "CLBLM_R_X29Y139/CLBLM_WW4B3", + "CLBLM_R_X33Y67/CLBLM_LH10", + "CLBLM_R_X35Y67/CLBLM_LH8", + "CLBLM_R_X39Y67/CLBLM_LH4", + "CLBLM_R_X41Y67/CLBLM_LH2", + "CLK_FEED_X60Y146/CLK_FEED_WW2END1", + "CMT_FIFO_L_X107Y72/CMT_FIFO_LH2_4", + "CMT_TOP_L_LOWER_T_X106Y70/CMT_TOP_LH2_1", + "DSP_L_X34Y65/DSP_LH10_2", + "HCLK_R_X78Y130/HCLK_LV3", + "HCLK_R_X78Y78/HCLK_LV7", + "INT_INTERFACE_L_X34Y67/INT_INTERFACE_LH10", + "INT_INTERFACE_L_X42Y67/INT_INTERFACE_LH2", + "INT_INTERFACE_R_X23Y140/INT_INTERFACE_WW2END1", + "INT_L_X24Y140/WW2A1", + "INT_L_X26Y140/NW2END3", + "INT_L_X26Y140/WL1BEG1", + "INT_L_X28Y139/WW4C3", + "INT_L_X30Y139/WW4A3", + "INT_L_X32Y67/LH11", + "INT_L_X34Y67/LH9", + "INT_L_X36Y67/LH7", + "INT_L_X38Y67/LH5", + "INT_L_X40Y67/LH3", + "INT_L_X42Y67/LH1", + "INT_R_X25Y140/WL1END1", + "INT_R_X25Y140/WW2BEG1", + "INT_R_X27Y139/NW2BEG3", + "INT_R_X27Y139/WW4END3", + "INT_R_X27Y140/NW2A3", + "INT_R_X29Y139/WW4B3", + "INT_R_X31Y100/LV15", + "INT_R_X31Y101/LV16", + "INT_R_X31Y102/LV17", + "INT_R_X31Y103/LV0", + "INT_R_X31Y103/LV18", + "INT_R_X31Y104/LV1", + "INT_R_X31Y105/LV2", + "INT_R_X31Y106/LV3", + "INT_R_X31Y107/LV4", + "INT_R_X31Y108/LV5", + "INT_R_X31Y109/LV6", + "INT_R_X31Y110/LV7", + "INT_R_X31Y111/LV8", + "INT_R_X31Y112/LV9", + "INT_R_X31Y113/LV10", + "INT_R_X31Y114/LV11", + "INT_R_X31Y115/LV12", + "INT_R_X31Y116/LV13", + "INT_R_X31Y117/LV14", + "INT_R_X31Y118/LV15", + "INT_R_X31Y119/LV16", + "INT_R_X31Y120/LV17", + "INT_R_X31Y121/LV0", + "INT_R_X31Y121/LV18", + "INT_R_X31Y122/LV1", + "INT_R_X31Y123/LV2", + "INT_R_X31Y124/LV3", + "INT_R_X31Y125/LV4", + "INT_R_X31Y126/LV5", + "INT_R_X31Y127/LV6", + "INT_R_X31Y128/LV7", + "INT_R_X31Y129/LV8", + "INT_R_X31Y130/LV9", + "INT_R_X31Y131/LV10", + "INT_R_X31Y132/LV11", + "INT_R_X31Y133/LV12", + "INT_R_X31Y134/LV13", + "INT_R_X31Y135/LV14", + "INT_R_X31Y136/LV15", + "INT_R_X31Y137/LV16", + "INT_R_X31Y138/LV17", + "INT_R_X31Y139/LV18", + "INT_R_X31Y139/WW4BEG3", + "INT_R_X31Y67/LH12", + "INT_R_X31Y67/LV0", + "INT_R_X31Y68/LV1", + "INT_R_X31Y69/LV2", + "INT_R_X31Y70/LV3", + "INT_R_X31Y71/LV4", + "INT_R_X31Y72/LV5", + "INT_R_X31Y73/LV6", + "INT_R_X31Y74/LV7", + "INT_R_X31Y75/LV8", + "INT_R_X31Y76/LV9", + "INT_R_X31Y77/LV10", + "INT_R_X31Y78/LV11", + "INT_R_X31Y79/LV12", + "INT_R_X31Y80/LV13", + "INT_R_X31Y81/LV14", + "INT_R_X31Y82/LV15", + "INT_R_X31Y83/LV16", + "INT_R_X31Y84/LV17", + "INT_R_X31Y85/LV0", + "INT_R_X31Y85/LV18", + "INT_R_X31Y86/LV1", + "INT_R_X31Y87/LV2", + "INT_R_X31Y88/LV3", + "INT_R_X31Y89/LV4", + "INT_R_X31Y90/LV5", + "INT_R_X31Y91/LV6", + "INT_R_X31Y92/LV7", + "INT_R_X31Y93/LV8", + "INT_R_X31Y94/LV9", + "INT_R_X31Y95/LV10", + "INT_R_X31Y96/LV11", + "INT_R_X31Y97/LV12", + "INT_R_X31Y98/LV13", + "INT_R_X31Y99/LV14", + "INT_R_X33Y67/LH10", + "INT_R_X35Y67/LH8", + "INT_R_X37Y67/LH6", + "INT_R_X39Y67/LH4", + "INT_R_X41Y67/LH2", + "INT_R_X43Y48/LOGIC_OUTS18", + "INT_R_X43Y48/NR1BEG0", + "INT_R_X43Y49/LV0", + "INT_R_X43Y49/NR1END0", + "INT_R_X43Y50/LV1", + "INT_R_X43Y51/LV2", + "INT_R_X43Y52/LV3", + "INT_R_X43Y53/LV4", + "INT_R_X43Y54/LV5", + "INT_R_X43Y55/LV6", + "INT_R_X43Y56/LV7", + "INT_R_X43Y57/LV8", + "INT_R_X43Y58/LV9", + "INT_R_X43Y59/LV10", + "INT_R_X43Y60/LV11", + "INT_R_X43Y61/LV12", + "INT_R_X43Y62/LV13", + "INT_R_X43Y63/LV14", + "INT_R_X43Y64/LV15", + "INT_R_X43Y65/LV16", + "INT_R_X43Y66/LV17", + "INT_R_X43Y67/LH0", + "INT_R_X43Y67/LV18", + "IO_INT_INTERFACE_R_X43Y48/INT_INTERFACE_LOGIC_OUTS18", + "IO_INT_INTERFACE_R_X43Y48/INT_INTERFACE_LOGIC_OUTS_B18", + "RIOB33_X43Y47/IOB_IBUF0", + "RIOI3_X43Y47/IOI_ILOGIC0_O", + "RIOI3_X43Y47/IOI_LOGIC_OUTS18_1", + "RIOI3_X43Y47/RIOI_I0", + "RIOI3_X43Y47/RIOI_IBUF0", + "RIOI3_X43Y47/RIOI_ILOGIC0_D", + "R_TERM_INT_X112Y50/TERM_INT_LOGIC_OUTS_L_B18", + "VBRK_X105Y70/VBRK_LH2", + "VBRK_X61Y146/VBRK_WW2END1", + "VBRK_X66Y146/VBRK_WL1END1", + "VBRK_X80Y70/VBRK_LH12", + "VBRK_X85Y70/VBRK_LH10", + "VBRK_X96Y70/VBRK_LH6" + ] + }, + { + "name": "din[16]", + "node": "INT_L_X0Y118/EE2BEG2", + "pin": "B18", + "wire": "VBRK_X9Y123/VBRK_EE2A2", + "wires_outside_roi": [ + "CMT_FIFO_R_X7Y124/CMT_FIFO_EE2A2_5", + "CMT_TOP_R_LOWER_T_X8Y122/CMT_TOP_EE2A2_2", + "INT_INTERFACE_R_X1Y118/INT_INTERFACE_EE2A2", + "INT_L_X0Y112/LOGIC_OUTS_L18", + "INT_L_X0Y112/NE6A0", + "INT_L_X0Y112/NW6BEG0", + "INT_L_X0Y113/NE6B0", + "INT_L_X0Y114/NE6C0", + "INT_L_X0Y115/NE6D0", + "INT_L_X0Y116/NE6E0", + "INT_L_X0Y118/EE2BEG2", + "INT_L_X0Y118/EL1END2", + "INT_L_X0Y118/NW2END_S0_0", + "INT_L_X0Y118/WL1BEG2", + "INT_L_X0Y119/NW2END0", + "INT_R_X1Y116/NE6END0", + "INT_R_X1Y116/NN2BEG0", + "INT_R_X1Y117/NN2A0", + "INT_R_X1Y117/NN2END_S2_0", + "INT_R_X1Y118/EE2A2", + "INT_R_X1Y118/NN2END0", + "INT_R_X1Y118/NW2BEG0", + "INT_R_X1Y119/NW2A0", + "IO_INT_INTERFACE_L_X0Y112/INT_INTERFACE_LOGIC_OUTS_L18", + "IO_INT_INTERFACE_L_X0Y112/INT_INTERFACE_LOGIC_OUTS_L_B18", + "IO_INT_INTERFACE_L_X0Y112/INT_INTERFACE_NE4BEG0", + "IO_INT_INTERFACE_L_X0Y112/INT_INTERFACE_NW4A0", + "IO_INT_INTERFACE_L_X0Y118/INT_INTERFACE_EL1BEG2", + "IO_INT_INTERFACE_L_X0Y118/INT_INTERFACE_WL1END2", + "LIOB33_X0Y111/IOB_IBUF0", + "LIOI3_X0Y111/IOI_ILOGIC0_O", + "LIOI3_X0Y111/IOI_LOGIC_OUTS18_1", + "LIOI3_X0Y111/LIOI_I0", + "LIOI3_X0Y111/LIOI_IBUF0", + "LIOI3_X0Y111/LIOI_ILOGIC0_D", + "L_TERM_INT_X2Y117/L_TERM_INT_NW4BEG0", + "L_TERM_INT_X2Y117/TERM_INT_LOGIC_OUTS_L_B18", + "L_TERM_INT_X2Y123/L_TERM_INT_WL1BEG2" + ] }, { "name": "dout[0]", - "node": "INT_L_X10Y125/SW6BEG0", + "node": "INT_L_X2Y115/SW6BEG0", "pin": "U16", - "wire": "VBRK_X29Y131/VBRK_SW4A0" + "wire": "VBRK_X9Y120/VBRK_SW4A0", + "wires_outside_roi": [ + "CMT_FIFO_R_X7Y124/CMT_FIFO_SW4A0_2", + "CMT_TOP_R_LOWER_B_X8Y113/CMT_TOP_SW4A0_15", + "INT_INTERFACE_R_X1Y115/INT_INTERFACE_SW4A0", + "INT_L_X0Y111/SW6END0", + "INT_R_X1Y111/SW6E0", + "INT_R_X1Y112/SW6D0", + "INT_R_X1Y113/SW6C0", + "INT_R_X1Y114/SW6B0", + "INT_R_X1Y115/SW6A0" + ] }, { "name": "dout[1]", - "node": "INT_L_X10Y128/SW6BEG0", + "node": "INT_L_X2Y117/SW6BEG0", "pin": "E19", - "wire": "VBRK_X29Y134/VBRK_SW4A0" + "wire": "VBRK_X9Y122/VBRK_SW4A0", + "wires_outside_roi": [ + "CMT_FIFO_R_X7Y124/CMT_FIFO_SW4A0_4", + "CMT_TOP_R_LOWER_T_X8Y122/CMT_TOP_SW4A0_1", + "INT_INTERFACE_R_X1Y117/INT_INTERFACE_SW4A0", + "INT_L_X0Y113/SW6END0", + "INT_R_X1Y113/SW6E0", + "INT_R_X1Y114/SW6D0", + "INT_R_X1Y115/SW6C0", + "INT_R_X1Y116/SW6B0", + "INT_R_X1Y117/SW6A0" + ] }, { "name": "dout[2]", - "node": "INT_L_X10Y131/SW6BEG0", + "node": "INT_L_X2Y119/SW6BEG0", "pin": "U19", - "wire": "VBRK_X29Y137/VBRK_SW4A0" + "wire": "VBRK_X9Y124/VBRK_SW4A0", + "wires_outside_roi": [ + "CMT_FIFO_R_X7Y124/CMT_FIFO_SW4A0_6", + "CMT_TOP_R_LOWER_T_X8Y122/CMT_TOP_SW4A0_3", + "INT_INTERFACE_R_X1Y119/INT_INTERFACE_SW4A0", + "INT_L_X0Y115/SW6END0", + "INT_R_X1Y115/SW6E0", + "INT_R_X1Y116/SW6D0", + "INT_R_X1Y117/SW6C0", + "INT_R_X1Y118/SW6B0", + "INT_R_X1Y119/SW6A0" + ] }, { "name": "dout[3]", - "node": "INT_L_X10Y134/SW6BEG0", + "node": "INT_L_X2Y121/SW6BEG0", "pin": "V19", - "wire": "VBRK_X29Y140/VBRK_SW4A0" + "wire": "VBRK_X9Y126/VBRK_SW4A0", + "wires_outside_roi": [ + "CMT_FIFO_R_X7Y124/CMT_FIFO_SW4A0_8", + "CMT_TOP_R_LOWER_T_X8Y122/CMT_TOP_SW4A0_5", + "INT_INTERFACE_R_X1Y121/INT_INTERFACE_SW4A0", + "INT_L_X0Y117/SW6END0", + "INT_R_X1Y117/SW6E0", + "INT_R_X1Y118/SW6D0", + "INT_R_X1Y119/SW6C0", + "INT_R_X1Y120/SW6B0", + "INT_R_X1Y121/SW6A0" + ] }, { "name": "dout[4]", - "node": "INT_L_X10Y137/SW6BEG0", + "node": "INT_L_X2Y123/SW6BEG0", "pin": "W18", - "wire": "VBRK_X29Y143/VBRK_SW4A0" + "wire": "VBRK_X9Y128/VBRK_SW4A0", + "wires_outside_roi": [ + "CMT_FIFO_R_X7Y124/CMT_FIFO_SW4A0_10", + "CMT_TOP_R_LOWER_T_X8Y122/CMT_TOP_SW4A0_7", + "INT_INTERFACE_R_X1Y123/INT_INTERFACE_SW4A0", + "INT_L_X0Y119/SW6END0", + "INT_R_X1Y119/SW6E0", + "INT_R_X1Y120/SW6D0", + "INT_R_X1Y121/SW6C0", + "INT_R_X1Y122/SW6B0", + "INT_R_X1Y123/SW6A0" + ] }, { "name": "dout[5]", - "node": "INT_L_X10Y140/SW6BEG0", + "node": "INT_L_X2Y125/SW6BEG0", "pin": "U15", - "wire": "VBRK_X29Y146/VBRK_SW4A0" + "wire": "VBRK_X9Y131/VBRK_SW4A0", + "wires_outside_roi": [ + "CMT_FIFO_R_X7Y137/CMT_FIFO_SW4A0_0", + "CMT_TOP_R_UPPER_B_X8Y135/CMT_TOP_SW4A0_0", + "HCLK_R_X5Y130/HCLK_SW6B0", + "INT_INTERFACE_R_X1Y125/INT_INTERFACE_SW4A0", + "INT_L_X0Y121/SW6END0", + "INT_R_X1Y121/SW6E0", + "INT_R_X1Y122/SW6D0", + "INT_R_X1Y123/SW6C0", + "INT_R_X1Y124/SW6B0", + "INT_R_X1Y125/SW6A0" + ] }, { "name": "dout[6]", - "node": "INT_L_X10Y143/SW6BEG0", + "node": "INT_L_X2Y127/SW6BEG0", "pin": "U14", - "wire": "VBRK_X29Y149/VBRK_SW4A0" + "wire": "VBRK_X9Y133/VBRK_SW4A0", + "wires_outside_roi": [ + "CMT_FIFO_R_X7Y137/CMT_FIFO_SW4A0_2", + "CMT_TOP_R_UPPER_B_X8Y135/CMT_TOP_SW4A0_2", + "HCLK_R_X5Y130/HCLK_SW6D0", + "INT_INTERFACE_R_X1Y127/INT_INTERFACE_SW4A0", + "INT_L_X0Y123/SW6END0", + "INT_R_X1Y123/SW6E0", + "INT_R_X1Y124/SW6D0", + "INT_R_X1Y125/SW6C0", + "INT_R_X1Y126/SW6B0", + "INT_R_X1Y127/SW6A0" + ] }, { "name": "dout[7]", - "node": "INT_L_X10Y146/SW6BEG0", + "node": "INT_L_X2Y129/SW6BEG0", "pin": "V14", - "wire": "VBRK_X29Y152/VBRK_SW4A0" + "wire": "VBRK_X9Y135/VBRK_SW4A0", + "wires_outside_roi": [ + "CMT_FIFO_R_X7Y137/CMT_FIFO_SW4A0_4", + "CMT_TOP_R_UPPER_B_X8Y135/CMT_TOP_SW4A0_4", + "INT_INTERFACE_R_X1Y129/INT_INTERFACE_SW4A0", + "INT_L_X0Y125/SW6END0", + "INT_R_X1Y125/SW6E0", + "INT_R_X1Y126/SW6D0", + "INT_R_X1Y127/SW6C0", + "INT_R_X1Y128/SW6B0", + "INT_R_X1Y129/SW6A0" + ] + }, + { + "name": "dout[8]", + "node": "INT_L_X2Y131/SW6BEG0", + "pin": "V13", + "wire": "VBRK_X9Y137/VBRK_SW4A0", + "wires_outside_roi": [ + "CMT_FIFO_R_X7Y137/CMT_FIFO_SW4A0_6", + "CMT_TOP_R_UPPER_B_X8Y135/CMT_TOP_SW4A0_6", + "INT_INTERFACE_R_X1Y131/INT_INTERFACE_SW4A0", + "INT_L_X0Y127/SW6END0", + "INT_R_X1Y127/SW6E0", + "INT_R_X1Y128/SW6D0", + "INT_R_X1Y129/SW6C0", + "INT_R_X1Y130/SW6B0", + "INT_R_X1Y131/SW6A0" + ] + }, + { + "name": "dout[9]", + "node": "INT_R_X23Y115/LH12", + "pin": "V3", + "wire": "VBRK_X61Y120/VBRK_LH12", + "wires_outside_roi": [ + "CLBLL_L_X24Y115/CLBLL_LH12", + "CLBLL_L_X26Y115/CLBLL_LH10", + "CLBLL_R_X31Y115/CLBLL_LH6", + "CLBLM_L_X32Y115/CLBLM_LH6", + "CLBLM_L_X36Y115/CLBLM_LH2", + "CLBLM_R_X25Y115/CLBLM_LH10", + "CLBLM_R_X33Y115/CLBLM_LH4", + "CLBLM_R_X35Y115/CLBLM_LH2", + "CLK_FEED_X60Y120/CLK_FEED_LH12", + "DSP_L_X34Y115/DSP_LH4_0", + "INT_INTERFACE_L_X34Y115/INT_INTERFACE_LH4", + "INT_INTERFACE_R_X23Y115/INT_INTERFACE_LH12", + "INT_L_X24Y115/LH11", + "INT_L_X26Y115/LH9", + "INT_L_X30Y115/LH7", + "INT_L_X32Y115/LH5", + "INT_L_X34Y115/LH3", + "INT_L_X36Y115/LH1", + "INT_R_X25Y115/LH10", + "INT_R_X27Y115/LH8", + "INT_R_X31Y115/LH6", + "INT_R_X33Y115/LH4", + "INT_R_X35Y115/LH2", + "INT_R_X37Y115/LH0", + "PCIE_BOT_X71Y115/PCIE_LH8_15", + "PCIE_INT_INTERFACE_L_X30Y115/INT_INTERFACE_LH8", + "PCIE_INT_INTERFACE_R_X27Y115/INT_INTERFACE_LH8", + "VBRK_X61Y120/VBRK_LH12", + "VBRK_X66Y120/VBRK_LH10", + "VBRK_X80Y120/VBRK_LH6", + "VBRK_X85Y120/VBRK_LH4" + ] + }, + { + "name": "dout[10]", + "node": "INT_R_X23Y117/LH12", + "pin": "W3", + "wire": "VBRK_X61Y122/VBRK_LH12", + "wires_outside_roi": [ + "CLBLL_L_X24Y117/CLBLL_LH12", + "CLBLL_L_X26Y117/CLBLL_LH10", + "CLBLL_R_X31Y117/CLBLL_LH6", + "CLBLM_L_X32Y117/CLBLM_LH6", + "CLBLM_L_X36Y117/CLBLM_LH2", + "CLBLM_R_X25Y117/CLBLM_LH10", + "CLBLM_R_X33Y117/CLBLM_LH4", + "CLBLM_R_X35Y117/CLBLM_LH2", + "CLK_FEED_X60Y122/CLK_FEED_LH12", + "DSP_L_X34Y115/DSP_LH4_2", + "INT_INTERFACE_L_X34Y117/INT_INTERFACE_LH4", + "INT_INTERFACE_R_X23Y117/INT_INTERFACE_LH12", + "INT_L_X24Y117/LH11", + "INT_L_X26Y117/LH9", + "INT_L_X30Y117/LH7", + "INT_L_X32Y117/LH5", + "INT_L_X34Y117/LH3", + "INT_L_X36Y117/LH1", + "INT_R_X25Y117/LH10", + "INT_R_X27Y117/LH8", + "INT_R_X31Y117/LH6", + "INT_R_X33Y117/LH4", + "INT_R_X35Y117/LH2", + "INT_R_X37Y117/LH0", + "PCIE_BOT_X71Y115/PCIE_LH8_17", + "PCIE_INT_INTERFACE_L_X30Y117/INT_INTERFACE_LH8", + "PCIE_INT_INTERFACE_R_X27Y117/INT_INTERFACE_LH8", + "VBRK_X61Y122/VBRK_LH12", + "VBRK_X66Y122/VBRK_LH10", + "VBRK_X80Y122/VBRK_LH6", + "VBRK_X85Y122/VBRK_LH4" + ] + }, + { + "name": "dout[11]", + "node": "INT_R_X23Y119/LH12", + "pin": "U3", + "wire": "VBRK_X61Y124/VBRK_LH12", + "wires_outside_roi": [ + "CLBLL_L_X24Y119/CLBLL_LH12", + "CLBLL_L_X26Y119/CLBLL_LH10", + "CLBLL_R_X31Y119/CLBLL_LH6", + "CLBLM_L_X32Y119/CLBLM_LH6", + "CLBLM_L_X36Y119/CLBLM_LH2", + "CLBLM_R_X25Y119/CLBLM_LH10", + "CLBLM_R_X33Y119/CLBLM_LH4", + "CLBLM_R_X35Y119/CLBLM_LH2", + "CLK_FEED_X60Y124/CLK_FEED_LH12", + "DSP_L_X34Y115/DSP_LH4_4", + "INT_INTERFACE_L_X34Y119/INT_INTERFACE_LH4", + "INT_INTERFACE_R_X23Y119/INT_INTERFACE_LH12", + "INT_L_X24Y119/LH11", + "INT_L_X26Y119/LH9", + "INT_L_X30Y119/LH7", + "INT_L_X32Y119/LH5", + "INT_L_X34Y119/LH3", + "INT_L_X36Y119/LH1", + "INT_R_X25Y119/LH10", + "INT_R_X27Y119/LH8", + "INT_R_X31Y119/LH6", + "INT_R_X33Y119/LH4", + "INT_R_X35Y119/LH2", + "INT_R_X37Y119/LH0", + "PCIE_BOT_X71Y115/PCIE_LH8_19", + "PCIE_INT_INTERFACE_L_X30Y119/INT_INTERFACE_LH8", + "PCIE_INT_INTERFACE_R_X27Y119/INT_INTERFACE_LH8", + "VBRK_X61Y124/VBRK_LH12", + "VBRK_X66Y124/VBRK_LH10", + "VBRK_X80Y124/VBRK_LH6", + "VBRK_X85Y124/VBRK_LH4" + ] + }, + { + "name": "dout[12]", + "node": "INT_R_X23Y121/LH12", + "pin": "P3", + "wire": "VBRK_X61Y126/VBRK_LH12", + "wires_outside_roi": [ + "CLBLL_L_X24Y121/CLBLL_LH12", + "CLBLL_L_X26Y121/CLBLL_LH10", + "CLBLL_R_X31Y121/CLBLL_LH6", + "CLBLM_L_X32Y121/CLBLM_LH6", + "CLBLM_L_X36Y121/CLBLM_LH2", + "CLBLM_R_X25Y121/CLBLM_LH10", + "CLBLM_R_X33Y121/CLBLM_LH4", + "CLBLM_R_X35Y121/CLBLM_LH2", + "CLK_HROW_TOP_R_X60Y130/CLK_HROW_LH12_0", + "DSP_L_X34Y120/DSP_LH4_1", + "INT_INTERFACE_L_X34Y121/INT_INTERFACE_LH4", + "INT_INTERFACE_R_X23Y121/INT_INTERFACE_LH12", + "INT_L_X24Y121/LH11", + "INT_L_X26Y121/LH9", + "INT_L_X30Y121/LH7", + "INT_L_X32Y121/LH5", + "INT_L_X34Y121/LH3", + "INT_L_X36Y121/LH1", + "INT_R_X25Y121/LH10", + "INT_R_X27Y121/LH8", + "INT_R_X31Y121/LH6", + "INT_R_X33Y121/LH4", + "INT_R_X35Y121/LH2", + "INT_R_X37Y121/LH0", + "PCIE_INT_INTERFACE_L_X30Y121/INT_INTERFACE_LH8", + "PCIE_INT_INTERFACE_R_X27Y121/INT_INTERFACE_LH8", + "PCIE_TOP_X71Y125/PCIE_LH8_1", + "VBRK_X61Y126/VBRK_LH12", + "VBRK_X66Y126/VBRK_LH10", + "VBRK_X80Y126/VBRK_LH6", + "VBRK_X85Y126/VBRK_LH4" + ] + }, + { + "name": "dout[13]", + "node": "INT_R_X23Y123/LH12", + "pin": "N3", + "wire": "VBRK_X61Y128/VBRK_LH12", + "wires_outside_roi": [ + "CLBLL_L_X24Y123/CLBLL_LH12", + "CLBLL_L_X26Y123/CLBLL_LH10", + "CLBLL_R_X31Y123/CLBLL_LH6", + "CLBLM_L_X32Y123/CLBLM_LH6", + "CLBLM_L_X36Y123/CLBLM_LH2", + "CLBLM_R_X25Y123/CLBLM_LH10", + "CLBLM_R_X33Y123/CLBLM_LH4", + "CLBLM_R_X35Y123/CLBLM_LH2", + "CLK_HROW_TOP_R_X60Y130/CLK_HROW_LH12_2", + "DSP_L_X34Y120/DSP_LH4_3", + "INT_INTERFACE_L_X34Y123/INT_INTERFACE_LH4", + "INT_INTERFACE_R_X23Y123/INT_INTERFACE_LH12", + "INT_L_X24Y123/LH11", + "INT_L_X26Y123/LH9", + "INT_L_X30Y123/LH7", + "INT_L_X32Y123/LH5", + "INT_L_X34Y123/LH3", + "INT_L_X36Y123/LH1", + "INT_R_X25Y123/LH10", + "INT_R_X27Y123/LH8", + "INT_R_X31Y123/LH6", + "INT_R_X33Y123/LH4", + "INT_R_X35Y123/LH2", + "INT_R_X37Y123/LH0", + "PCIE_INT_INTERFACE_L_X30Y123/INT_INTERFACE_LH8", + "PCIE_INT_INTERFACE_R_X27Y123/INT_INTERFACE_LH8", + "PCIE_TOP_X71Y125/PCIE_LH8_3", + "VBRK_X61Y128/VBRK_LH12", + "VBRK_X66Y128/VBRK_LH10", + "VBRK_X80Y128/VBRK_LH6", + "VBRK_X85Y128/VBRK_LH4" + ] + }, + { + "name": "dout[14]", + "node": "INT_R_X23Y125/LH12", + "pin": "P1", + "wire": "VBRK_X61Y131/VBRK_LH12", + "wires_outside_roi": [ + "BRAM_INT_INTERFACE_L_X30Y125/INT_INTERFACE_LH6", + "BRAM_L_X30Y125/BRAM_LH6_0", + "CLBLL_L_X24Y125/CLBLL_LH12", + "CLBLL_L_X26Y125/CLBLL_LH10", + "CLBLL_L_X28Y125/CLBLL_LH8", + "CLBLL_R_X31Y125/CLBLL_LH4", + "CLBLM_L_X32Y125/CLBLM_LH4", + "CLBLM_R_X25Y125/CLBLM_LH10", + "CLBLM_R_X27Y125/CLBLM_LH8", + "CLBLM_R_X29Y125/CLBLM_LH6", + "CLBLM_R_X33Y125/CLBLM_LH2", + "CLK_HROW_TOP_R_X60Y130/CLK_HROW_LH12_4", + "DSP_L_X34Y125/DSP_LH2_0", + "INT_INTERFACE_L_X34Y125/INT_INTERFACE_LH2", + "INT_INTERFACE_R_X23Y125/INT_INTERFACE_LH12", + "INT_L_X24Y125/LH11", + "INT_L_X26Y125/LH9", + "INT_L_X28Y125/LH7", + "INT_L_X30Y125/LH5", + "INT_L_X32Y125/LH3", + "INT_L_X34Y125/LH1", + "INT_R_X25Y125/LH10", + "INT_R_X27Y125/LH8", + "INT_R_X29Y125/LH6", + "INT_R_X31Y125/LH4", + "INT_R_X33Y125/LH2", + "INT_R_X35Y125/LH0", + "VBRK_X61Y131/VBRK_LH12", + "VBRK_X66Y131/VBRK_LH10", + "VBRK_X80Y131/VBRK_LH4", + "VBRK_X85Y131/VBRK_LH2" + ] + }, + { + "name": "dout[15]", + "node": "INT_R_X23Y127/LH12", + "pin": "L1", + "wire": "VBRK_X61Y133/VBRK_LH12", + "wires_outside_roi": [ + "BRAM_INT_INTERFACE_L_X30Y127/INT_INTERFACE_LH6", + "BRAM_L_X30Y125/BRAM_LH6_2", + "CLBLL_L_X24Y127/CLBLL_LH12", + "CLBLL_L_X26Y127/CLBLL_LH10", + "CLBLL_L_X28Y127/CLBLL_LH8", + "CLBLL_R_X31Y127/CLBLL_LH4", + "CLBLM_L_X32Y127/CLBLM_LH4", + "CLBLM_R_X25Y127/CLBLM_LH10", + "CLBLM_R_X27Y127/CLBLM_LH8", + "CLBLM_R_X29Y127/CLBLM_LH6", + "CLBLM_R_X33Y127/CLBLM_LH2", + "CLK_HROW_TOP_R_X60Y130/CLK_HROW_LH12_6", + "DSP_L_X34Y125/DSP_LH2_2", + "INT_INTERFACE_L_X34Y127/INT_INTERFACE_LH2", + "INT_INTERFACE_R_X23Y127/INT_INTERFACE_LH12", + "INT_L_X24Y127/LH11", + "INT_L_X26Y127/LH9", + "INT_L_X28Y127/LH7", + "INT_L_X30Y127/LH5", + "INT_L_X32Y127/LH3", + "INT_L_X34Y127/LH1", + "INT_R_X25Y127/LH10", + "INT_R_X27Y127/LH8", + "INT_R_X29Y127/LH6", + "INT_R_X31Y127/LH4", + "INT_R_X33Y127/LH2", + "INT_R_X35Y127/LH0", + "VBRK_X61Y133/VBRK_LH12", + "VBRK_X66Y133/VBRK_LH10", + "VBRK_X80Y133/VBRK_LH4", + "VBRK_X85Y133/VBRK_LH2" + ] + }, + { + "name": "dout[16]", + "node": "INT_L_X2Y133/SW6BEG0", + "pin": "A18", + "wire": "VBRK_X9Y139/VBRK_SW4A0", + "wires_outside_roi": [ + "CMT_FIFO_R_X7Y137/CMT_FIFO_SW4A0_8", + "CMT_TOP_R_UPPER_B_X8Y135/CMT_TOP_SW4A0_8", + "INT_INTERFACE_R_X1Y133/INT_INTERFACE_SW4A0", + "INT_L_X0Y129/SW6END0", + "INT_R_X1Y129/SW6E0", + "INT_R_X1Y130/SW6D0", + "INT_R_X1Y131/SW6C0", + "INT_R_X1Y132/SW6B0", + "INT_R_X1Y133/SW6A0" + ] } ] -} \ No newline at end of file +} diff --git a/artix7/harness/basys3/swbut/design.txt b/artix7/harness/basys3/swbut/design.txt index 8a63b52..8cf3900 100644 --- a/artix7/harness/basys3/swbut/design.txt +++ b/artix7/harness/basys3/swbut/design.txt @@ -1,18 +1,36 @@ name node pin wire clk CLK_HROW_TOP_R_X60Y130/CLK_HROW_CK_BUFHCLK_L0 W5 HCLK_VBRK_X34Y130/HCLK_VBRK_CK_BUFHCLK0 -din[0] INT_R_X9Y102/NE2BEG3 V17 VBRK_X29Y108/VBRK_NE2A3 -din[1] INT_R_X9Y105/NE2BEG3 V16 VBRK_X29Y111/VBRK_NE2A3 -din[2] INT_R_X9Y108/NE2BEG3 W16 VBRK_X29Y114/VBRK_NE2A3 -din[3] INT_R_X9Y111/NE2BEG3 W17 VBRK_X29Y117/VBRK_NE2A3 -din[4] INT_R_X9Y114/NE2BEG3 W15 VBRK_X29Y120/VBRK_NE2A3 -din[5] INT_R_X9Y117/NE2BEG3 V15 VBRK_X29Y123/VBRK_NE2A3 -din[6] INT_R_X9Y120/NE2BEG3 W14 VBRK_X29Y126/VBRK_NE2A3 -din[7] INT_R_X9Y123/NE2BEG3 W13 VBRK_X29Y129/VBRK_NE2A3 -dout[0] INT_L_X10Y125/SW6BEG0 U16 VBRK_X29Y131/VBRK_SW4A0 -dout[1] INT_L_X10Y128/SW6BEG0 E19 VBRK_X29Y134/VBRK_SW4A0 -dout[2] INT_L_X10Y131/SW6BEG0 U19 VBRK_X29Y137/VBRK_SW4A0 -dout[3] INT_L_X10Y134/SW6BEG0 V19 VBRK_X29Y140/VBRK_SW4A0 -dout[4] INT_L_X10Y137/SW6BEG0 W18 VBRK_X29Y143/VBRK_SW4A0 -dout[5] INT_L_X10Y140/SW6BEG0 U15 VBRK_X29Y146/VBRK_SW4A0 -dout[6] INT_L_X10Y143/SW6BEG0 U14 VBRK_X29Y149/VBRK_SW4A0 -dout[7] INT_L_X10Y146/SW6BEG0 V14 VBRK_X29Y152/VBRK_SW4A0 +din[0] INT_L_X0Y102/EE2BEG2 V17 VBRK_X9Y107/VBRK_EE2A2 +din[1] INT_L_X0Y104/EE2BEG2 V16 VBRK_X9Y109/VBRK_EE2A2 +din[2] INT_L_X0Y106/EE2BEG2 W16 VBRK_X9Y111/VBRK_EE2A2 +din[3] INT_L_X0Y108/EE2BEG2 W17 VBRK_X9Y113/VBRK_EE2A2 +din[4] INT_L_X0Y110/EE2BEG2 W15 VBRK_X9Y115/VBRK_EE2A2 +din[5] INT_L_X0Y112/EE2BEG2 V15 VBRK_X9Y117/VBRK_EE2A2 +din[6] INT_L_X0Y114/EE2BEG2 W14 VBRK_X9Y119/VBRK_EE2A2 +din[7] INT_L_X0Y116/EE2BEG2 W13 VBRK_X9Y121/VBRK_EE2A2 +din[8] INT_R_X25Y126/WW2BEG1 V2 VBRK_X61Y132/VBRK_WW2END1 +din[9] INT_R_X25Y128/WW2BEG1 T3 VBRK_X61Y134/VBRK_WW2END1 +din[10] INT_R_X25Y130/WW2BEG1 T2 VBRK_X61Y136/VBRK_WW2END1 +din[11] INT_R_X25Y132/WW2BEG1 R3 VBRK_X61Y138/VBRK_WW2END1 +din[12] INT_R_X25Y134/WW2BEG1 W2 VBRK_X61Y140/VBRK_WW2END1 +din[13] INT_R_X25Y136/WW2BEG1 U1 VBRK_X61Y142/VBRK_WW2END1 +din[14] INT_R_X25Y138/WW2BEG1 T1 VBRK_X61Y144/VBRK_WW2END1 +din[15] INT_R_X25Y140/WW2BEG1 R2 VBRK_X61Y146/VBRK_WW2END1 +din[16] INT_L_X0Y118/EE2BEG2 B18 VBRK_X9Y123/VBRK_EE2A2 +dout[0] INT_L_X2Y115/SW6BEG0 U16 VBRK_X9Y120/VBRK_SW4A0 +dout[1] INT_L_X2Y117/SW6BEG0 E19 VBRK_X9Y122/VBRK_SW4A0 +dout[2] INT_L_X2Y119/SW6BEG0 U19 VBRK_X9Y124/VBRK_SW4A0 +dout[3] INT_L_X2Y121/SW6BEG0 V19 VBRK_X9Y126/VBRK_SW4A0 +dout[4] INT_L_X2Y123/SW6BEG0 W18 VBRK_X9Y128/VBRK_SW4A0 +dout[5] INT_L_X2Y125/SW6BEG0 U15 VBRK_X9Y131/VBRK_SW4A0 +dout[6] INT_L_X2Y127/SW6BEG0 U14 VBRK_X9Y133/VBRK_SW4A0 +dout[7] INT_L_X2Y129/SW6BEG0 V14 VBRK_X9Y135/VBRK_SW4A0 +dout[8] INT_L_X2Y131/SW6BEG0 V13 VBRK_X9Y137/VBRK_SW4A0 +dout[9] INT_R_X23Y115/LH12 V3 VBRK_X61Y120/VBRK_LH12 +dout[10] INT_R_X23Y117/LH12 W3 VBRK_X61Y122/VBRK_LH12 +dout[11] INT_R_X23Y119/LH12 U3 VBRK_X61Y124/VBRK_LH12 +dout[12] INT_R_X23Y121/LH12 P3 VBRK_X61Y126/VBRK_LH12 +dout[13] INT_R_X23Y123/LH12 N3 VBRK_X61Y128/VBRK_LH12 +dout[14] INT_R_X23Y125/LH12 P1 VBRK_X61Y131/VBRK_LH12 +dout[15] INT_R_X23Y127/LH12 L1 VBRK_X61Y133/VBRK_LH12 +dout[16] INT_L_X2Y133/SW6BEG0 A18 VBRK_X9Y139/VBRK_SW4A0