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Updating zynq7 based on "Merge pull request #879 from litghost/avoid_full_dict_build". 

See [Info File](Info.md) for details.

Signed-off-by: Tim 'mithro' Ansell <me@mith.ro>
This commit is contained in:
Tim 'mithro' Ansell 2019-06-12 13:21:02 +02:00
parent 43705aae2c
commit c81749430a
126 changed files with 1032181 additions and 109888 deletions
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Info.md
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@ -37,7 +37,7 @@ These files are released under the very permissive [CC0 1.0 Universal](COPYING).
# Details
Last updated on Wed 12 Jun 2019 11:15:19 AM UTC (2019-06-12T11:15:19+00:00).
Last updated on Wed 12 Jun 2019 11:20:54 AM UTC (2019-06-12T11:20:54+00:00).
Created using [Project X-Ray](https://github.com/SymbiFlow/prjxray) version [d31319cc](https://github.com/SymbiFlow/prjxray/commit/d31319ccaa6f6fc4d1106890f9d72d908fa03b52).
@ -857,8 +857,8 @@ Results have checksums;
* [`be757fb834be7ff84a2873c0ac6621c909a5e85362b397667760edde86616f84 ./zynq7/mask_hclk_cmt_l.db`](./zynq7/mask_hclk_cmt_l.db)
* [`76d1e0bd4b7ad492cf3fe8698b2b5f46f7dcc5fe446984e5dccae373c63edafd ./zynq7/mask_hclk_l.db`](./zynq7/mask_hclk_l.db)
* [`76d1e0bd4b7ad492cf3fe8698b2b5f46f7dcc5fe446984e5dccae373c63edafd ./zynq7/mask_hclk_r.db`](./zynq7/mask_hclk_r.db)
* [`13dcba800fad00a8a87930bae3b302b32fd875c1a55e156616eadbb04e92ba58 ./zynq7/mask_liob33.db`](./zynq7/mask_liob33.db)
* [`c45d74a80ffc51ec9ea12767877602de8432be7d5a11b5d1f4d81ad74e159d17 ./zynq7/mask_riob33.db`](./zynq7/mask_riob33.db)
* [`6e99ef6017891939248e9f03c630155243a819a2e0c4c51b4d78dc5b248c8dea ./zynq7/mask_liob33.db`](./zynq7/mask_liob33.db)
* [`ec6a38f311c53e65c876693548e585b534afa92f4fbee54d61e06729257cb2ec ./zynq7/mask_riob33.db`](./zynq7/mask_riob33.db)
* [`d94e4d13df16da498224f0e94deaa310fbf471b6f9ec0ec8b2308fe62fa2eeaf ./zynq7/ppips_bram_int_interface_l.db`](./zynq7/ppips_bram_int_interface_l.db)
* [`b48d766ac6f9dd0e21280d3a04dd448ea39016143309c0c7867fc00d730a59ae ./zynq7/ppips_bram_int_interface_r.db`](./zynq7/ppips_bram_int_interface_r.db)
* [`2c68f8b128aeb79197013c3a1774522143a3507a8fa595a98c22dba2553fd5ce ./zynq7/ppips_bram_l.db`](./zynq7/ppips_bram_l.db)
@ -884,27 +884,49 @@ Results have checksums;
* [`76c5978b345f11a9e46733a98875a6c419b75cf863a0e42d05e9ac94f9795bfc ./zynq7/ppips_rioi3_tbytesrc.db`](./zynq7/ppips_rioi3_tbytesrc.db)
* [`a9705cd0ffc8f972a6c0981d65b200a93f0b0069327133bad2aff80a6fce08ab ./zynq7/ppips_rioi3_tbyteterm.db`](./zynq7/ppips_rioi3_tbyteterm.db)
* [`8a2136e564ac92c06b226ef8715a122050fcabbb063f69eeaf46cfee5c89670f ./zynq7/segbits_bram_l.block_ram.db`](./zynq7/segbits_bram_l.block_ram.db)
* [`65b0fa7162231e9d1a9e30c64e9aad87bb3b8feaa40cf76055f96a7750d1e1da ./zynq7/segbits_bram_l.block_ram.origin_info.db`](./zynq7/segbits_bram_l.block_ram.origin_info.db)
* [`53d975bf59b763b9f764106db362ee7f6a753e9e72a5e2be334041658a5ea4ba ./zynq7/segbits_bram_l.db`](./zynq7/segbits_bram_l.db)
* [`89afef6aeb8c2450530809968dce1dcafe51d63fdea282df97e7dc5878e375e2 ./zynq7/segbits_bram_l.origin_info.db`](./zynq7/segbits_bram_l.origin_info.db)
* [`a635577b55878c69df492c16b67a1dfbd1d4b786a695abe3e95a62d9540ecea5 ./zynq7/segbits_bram_r.block_ram.db`](./zynq7/segbits_bram_r.block_ram.db)
* [`9b40402550b3a34067109372c2217e6bbef0744db204c38e4d7439f3ccba2474 ./zynq7/segbits_bram_r.block_ram.origin_info.db`](./zynq7/segbits_bram_r.block_ram.origin_info.db)
* [`b826680f3768091cb345ca6e62e3210ffb53a88ebdfdf4ca70f466f80cdacb1f ./zynq7/segbits_bram_r.db`](./zynq7/segbits_bram_r.db)
* [`83d0ac8050043e2aa67aa0dc2ba60692eef30daf9256503ff70b3e3a6475e3ba ./zynq7/segbits_bram_r.origin_info.db`](./zynq7/segbits_bram_r.origin_info.db)
* [`ef6706ef033396c75469738223e66d1b5f38b832e27b5bb80f07efd571e28fb7 ./zynq7/segbits_clbll_l.db`](./zynq7/segbits_clbll_l.db)
* [`4ddab18383430522a3aa8d49688487dd0c3895f36f2b9f1fecabfb695d0105e4 ./zynq7/segbits_clbll_l.origin_info.db`](./zynq7/segbits_clbll_l.origin_info.db)
* [`53c0ea2b05a2c4ddf2b6cce38073534d0c21b893fc5783dc777d97de2f2d6a9e ./zynq7/segbits_clbll_r.db`](./zynq7/segbits_clbll_r.db)
* [`50987c8e8ff9a66860f88e0f3531e92c5738a11613bee61720bae862e04b7787 ./zynq7/segbits_clbll_r.origin_info.db`](./zynq7/segbits_clbll_r.origin_info.db)
* [`e6459c01d0c1c7724fa02716103fd02a3e2a75d6b7326f4c937f158a264ffe85 ./zynq7/segbits_clblm_l.db`](./zynq7/segbits_clblm_l.db)
* [`467377976169e66212833dd5a92a1b0b19eae348b3fb113f0ea363097872c654 ./zynq7/segbits_clblm_l.origin_info.db`](./zynq7/segbits_clblm_l.origin_info.db)
* [`5862b402a5e0a95be5f140112678fd39e1dc039bc339fda0e58111ca1ee9cb6e ./zynq7/segbits_clblm_r.db`](./zynq7/segbits_clblm_r.db)
* [`20c664e6d20851c1b05e851ed278958a8d0f8d06697afb5caa70c62d07622575 ./zynq7/segbits_clblm_r.origin_info.db`](./zynq7/segbits_clblm_r.origin_info.db)
* [`8d43bd09b2f7127ff9ed4803b92303d72c827d10b8b8d943c295343257b3e818 ./zynq7/segbits_clk_bufg_bot_r.db`](./zynq7/segbits_clk_bufg_bot_r.db)
* [`8d17f7e9f3cdf3419760d2b74cd23c04ee560f2f2bc942b718201c445a922c34 ./zynq7/segbits_clk_bufg_bot_r.origin_info.db`](./zynq7/segbits_clk_bufg_bot_r.origin_info.db)
* [`d094c55a62408bd79c2606a8fc10839b23d979e4e924ced0d4276d285db7810f ./zynq7/segbits_clk_bufg_rebuf.db`](./zynq7/segbits_clk_bufg_rebuf.db)
* [`8e5cb983e044d31803253720c5496b368d0edb6705008c4cda61c213f9d44511 ./zynq7/segbits_clk_bufg_rebuf.origin_info.db`](./zynq7/segbits_clk_bufg_rebuf.origin_info.db)
* [`6da9671e724a74e370b805ddd47e04eefd89daa0af4331e841720f7586d7eb2a ./zynq7/segbits_clk_bufg_top_r.db`](./zynq7/segbits_clk_bufg_top_r.db)
* [`7497f9e1eb6208c157c3c1caeca7b94172a6bb4896e7cd6e3d28cf23c38c2281 ./zynq7/segbits_clk_bufg_top_r.origin_info.db`](./zynq7/segbits_clk_bufg_top_r.origin_info.db)
* [`4383aafad32f56f21404c5e6092811874f869c920e23a02b57da8c3e739fe2a9 ./zynq7/segbits_clk_hrow_bot_r.db`](./zynq7/segbits_clk_hrow_bot_r.db)
* [`5b5c62b9cf274038a8f58aee5b1dfa715368a20912e0b909ff062b3a328a41a1 ./zynq7/segbits_clk_hrow_bot_r.origin_info.db`](./zynq7/segbits_clk_hrow_bot_r.origin_info.db)
* [`972ea949e0bc360892d15ec0313d04e416a10a10fa594f3c361d37c357d59992 ./zynq7/segbits_clk_hrow_top_r.db`](./zynq7/segbits_clk_hrow_top_r.db)
* [`04051d28841ff3ec719ebae1182d13ca817cf5eadb039f76a2e12647e1abcf85 ./zynq7/segbits_clk_hrow_top_r.origin_info.db`](./zynq7/segbits_clk_hrow_top_r.origin_info.db)
* [`0c4a6e4bc385a8b3a43d05a06d8e87c8822cf2cc1742593167244ff194af4a5e ./zynq7/segbits_dsp_l.db`](./zynq7/segbits_dsp_l.db)
* [`85105e324b53c9b8a3d60a3631e125c2e6dc1329e017636232313c4aa8e1576d ./zynq7/segbits_dsp_l.origin_info.db`](./zynq7/segbits_dsp_l.origin_info.db)
* [`b014d7e2b101b0b0540a539cb74a76ccbe3a494e225e8e510bf258a457b18685 ./zynq7/segbits_dsp_r.db`](./zynq7/segbits_dsp_r.db)
* [`ec2c0e9896fc373927b2c1f3028aad90fa7126c76e99c8c29c2a86a35149aa81 ./zynq7/segbits_dsp_r.origin_info.db`](./zynq7/segbits_dsp_r.origin_info.db)
* [`65c83253dc05bb790d71edc7f868f2f8c7e4d4c7817f073b9c853c1ac2e075b0 ./zynq7/segbits_hclk_cmt_l.db`](./zynq7/segbits_hclk_cmt_l.db)
* [`b9c2e06ffd7c000cc02ac06dba94ceef3c2cb150b32c4e69e7290b47ff0cbe3b ./zynq7/segbits_hclk_cmt_l.origin_info.db`](./zynq7/segbits_hclk_cmt_l.origin_info.db)
* [`1c2c7229781a4a1d51bbbdeea76238b10497c043aaadf2a76de783041a201878 ./zynq7/segbits_hclk_l.db`](./zynq7/segbits_hclk_l.db)
* [`39179dfde43c6dd677c705082e1e7373d1866390cae064062f6eee50e7cd6ef6 ./zynq7/segbits_hclk_l.origin_info.db`](./zynq7/segbits_hclk_l.origin_info.db)
* [`51288ec0be63172fcb2a12a92853150c62a21e894c2d42a2586046c462bf57a9 ./zynq7/segbits_hclk_r.db`](./zynq7/segbits_hclk_r.db)
* [`ebcb17bbb3ae3ea76b20e86ad7efda9a36b2ee024c4b08e6d5e8bbf4bc7838cc ./zynq7/segbits_int_l.db`](./zynq7/segbits_int_l.db)
* [`90ac156ad102fd7f83f22f4cbbef5e1216b057c8c92fc1eec957f3c69c8b4368 ./zynq7/segbits_int_r.db`](./zynq7/segbits_int_r.db)
* [`0e9b5da6def4776e2ca8dd59af8f4334bf5cfb88d99b323be25dd6ba2e3386f7 ./zynq7/segbits_hclk_r.origin_info.db`](./zynq7/segbits_hclk_r.origin_info.db)
* [`0ea44e8dfaf97ed200f30b2afe117e94e1a68bdb26af2e09e69e855414779520 ./zynq7/segbits_int_l.db`](./zynq7/segbits_int_l.db)
* [`df08da95cd2a0e27b13cb69daed140b50865dd3863d155178a23b85681bf7a39 ./zynq7/segbits_int_l.origin_info.db`](./zynq7/segbits_int_l.origin_info.db)
* [`1541c7832dd161c5b3b5745d08fe0ee6f92bfbd372b76c12f54afc032c888556 ./zynq7/segbits_int_r.db`](./zynq7/segbits_int_r.db)
* [`51e9f1cfd54a13565e631837d12482bfaf9f0bb29f6c500b7c2aba27a1290387 ./zynq7/segbits_int_r.origin_info.db`](./zynq7/segbits_int_r.origin_info.db)
* [`d1ad493bd149ba47ac50a68fef57809d21a1ef36db63725317a12df9266ca8d8 ./zynq7/segbits_liob33.db`](./zynq7/segbits_liob33.db)
* [`32cae09e1ab0ba143570d702cfee2a3e04948c131f6511e6040c684638c67ed4 ./zynq7/segbits_riob33.db`](./zynq7/segbits_riob33.db)
* [`caaa32eadfca7d6417a09d5357f8c1eea23bdb325164857de03b8798bdf252bb ./zynq7/segbits_liob33.origin_info.db`](./zynq7/segbits_liob33.origin_info.db)
* [`a674ba036253f38ac8fd6ab2e10039f3d8ecd2a670c50c0610100a9f2a9028c7 ./zynq7/segbits_riob33.db`](./zynq7/segbits_riob33.db)
* [`35c3e42e279228ea12f3e27a874c52d1b1a7169403b3e9a28642698a80b63a3b ./zynq7/segbits_riob33.origin_info.db`](./zynq7/segbits_riob33.origin_info.db)
* [`ee26e7dbf78c2a37118c49ce7edb5fa44afd51850a24824ba8b68e34366f0787 ./zynq7/settings.sh`](./zynq7/settings.sh)
* [`ac6ba9ad814503f0fdc1dabb4292aaccd1a2195f5b348276cfee12aed3d96a70 ./zynq7/site_type_BSCAN.json`](./zynq7/site_type_BSCAN.json)
* [`64724ba2f8af98df5e1d92e5c2da2e6d5a41eec6580f796405e271dadb4e63be ./zynq7/site_type_BUFGCTRL.json`](./zynq7/site_type_BUFGCTRL.json)
@ -947,98 +969,98 @@ Results have checksums;
* [`8e5baf846e629316cefb781c26c09b6a39ca509d03dd381967c3e92f429dbda3 ./zynq7/site_type_TIEOFF.json`](./zynq7/site_type_TIEOFF.json)
* [`4a52214be0712e1f5e3746c304d3299fd2bfa9e578956df1d6fcd6128614da12 ./zynq7/site_type_USR_ACCESS.json`](./zynq7/site_type_USR_ACCESS.json)
* [`f711f285e16aa11d4827ce8504e9413c8ccf87f9f86d108740738ae6cbb4f388 ./zynq7/site_type_XADC.json`](./zynq7/site_type_XADC.json)
* [`0bfdad62f04128ca4d469aa18b179cbd3bf78e40c6af50450c9ca85bfffd746f ./zynq7/tile_type_BRAM_INT_INTERFACE_L.json`](./zynq7/tile_type_BRAM_INT_INTERFACE_L.json)
* [`fd0b3b31118249e66193fa06633a58aa5d86820bed16d3f85497b886d2282845 ./zynq7/tile_type_BRAM_INT_INTERFACE_R.json`](./zynq7/tile_type_BRAM_INT_INTERFACE_R.json)
* [`23af85ab67092eb90d6b05c3bff539499494eaecb07b5063baa2aa494063a1ec ./zynq7/tile_type_BRAM_L.json`](./zynq7/tile_type_BRAM_L.json)
* [`3f080d03ca1d85aa81c2bae209cb401b8dcddd6e115ea8d16d735f2b4e6fc892 ./zynq7/tile_type_BRAM_R.json`](./zynq7/tile_type_BRAM_R.json)
* [`29e4879a736ff9d43178ba3887ba47b8f1190464dabf4eef7c8fe8d8d23647c2 ./zynq7/tile_type_BRKH_BRAM.json`](./zynq7/tile_type_BRKH_BRAM.json)
* [`1adbede824487b01b77eed4443ff5434c9473a067dae3c620df3ccca800951ac ./zynq7/tile_type_BRKH_CLB.json`](./zynq7/tile_type_BRKH_CLB.json)
* [`d036cb35cb1bb3237b76f2e755fd3e5902e4588b03e565e4c01ecaa6429457fa ./zynq7/tile_type_BRKH_CLK.json`](./zynq7/tile_type_BRKH_CLK.json)
* [`ec60392fdf039d697e2de0b6c856d118a52ac7fb5bc50da206802f98a8967ea6 ./zynq7/tile_type_BRKH_CMT.json`](./zynq7/tile_type_BRKH_CMT.json)
* [`721f0a9fab25908b7ae0da9b94903a8ca1cb63d42dc5119d7b143309d27156fd ./zynq7/tile_type_BRKH_DSP_L.json`](./zynq7/tile_type_BRKH_DSP_L.json)
* [`db175274054c15c1cf7093a5117628fb30f27ddd50a29eabcc894e39236f95d8 ./zynq7/tile_type_BRKH_DSP_R.json`](./zynq7/tile_type_BRKH_DSP_R.json)
* [`68c36646e682266cb3aecade1627160b22112d72b5859f4aae3cd32df488422a ./zynq7/tile_type_BRKH_INT.json`](./zynq7/tile_type_BRKH_INT.json)
* [`b3700d8432a5ea4375fab4419bba143bc79dfd137a7110117ea085d79a2dd766 ./zynq7/tile_type_B_TERM_INT.json`](./zynq7/tile_type_B_TERM_INT.json)
* [`db3f1d44e0db5cf61bc97ee1c2002584e4588c473d412ca6739132fedabfa08b ./zynq7/tile_type_B_TERM_INT_PSS.json`](./zynq7/tile_type_B_TERM_INT_PSS.json)
* [`89e6d861ce30aaeb1df937f32aac00d4121de3089ea2bfa74945f93f1c4303b4 ./zynq7/tile_type_B_TERM_VBRK.json`](./zynq7/tile_type_B_TERM_VBRK.json)
* [`606581f9ab6d5c8ded71371ea6806e741b0739e5e32e69c503e4ebddc9544ec9 ./zynq7/tile_type_CFG_CENTER_BOT.json`](./zynq7/tile_type_CFG_CENTER_BOT.json)
* [`820a133d2cdab23ca7c64570daa391e3329826759fa82b2d12914878676274ce ./zynq7/tile_type_CFG_CENTER_MID.json`](./zynq7/tile_type_CFG_CENTER_MID.json)
* [`cc6b420c4804236a1b2928e5c86cfa6f6143b93843e40081d14c2bfd5d5e76a8 ./zynq7/tile_type_CFG_CENTER_TOP.json`](./zynq7/tile_type_CFG_CENTER_TOP.json)
* [`9fc927b122dbb55a74c48f846abf42ffc92537365d5524866b47d2217f70067f ./zynq7/tile_type_CFG_SECURITY_BOT_PELE1.json`](./zynq7/tile_type_CFG_SECURITY_BOT_PELE1.json)
* [`8eaac15316c7feb9da13a331e52d3c5f140fd92b4bcde5ceb5495fc35bef2c4d ./zynq7/tile_type_CFG_SECURITY_MID_PELE1.json`](./zynq7/tile_type_CFG_SECURITY_MID_PELE1.json)
* [`9f229626a932dd9ea0db5f82d923089f8d14f7495e2db348a9bcd4413528591b ./zynq7/tile_type_CFG_SECURITY_TOP_PELE1.json`](./zynq7/tile_type_CFG_SECURITY_TOP_PELE1.json)
* [`0cf36c0ab629c583c01ae9efa04093e0644da71b7b0dfbc175dfcf9ed56650d5 ./zynq7/tile_type_CLBLL_L.json`](./zynq7/tile_type_CLBLL_L.json)
* [`3607f851807c3b420d21b4fe0c0b26b91db19d1384ba39d45f4c771f7251544e ./zynq7/tile_type_CLBLL_R.json`](./zynq7/tile_type_CLBLL_R.json)
* [`8f91f81d6f549d0f728dbab89baca64bae44491b1b0df30ae6ca4193b6eed951 ./zynq7/tile_type_CLBLM_L.json`](./zynq7/tile_type_CLBLM_L.json)
* [`50812dbe755a110f8e33285728a9b565d46d1e71e76e63085fc6d1dea4f4dee7 ./zynq7/tile_type_CLBLM_R.json`](./zynq7/tile_type_CLBLM_R.json)
* [`3ab28fa68486317ac22e260c8d0ac81bcccc0b214cff21b66cda2cf0974d62bb ./zynq7/tile_type_CLK_BUFG_BOT_R.json`](./zynq7/tile_type_CLK_BUFG_BOT_R.json)
* [`7e7b949435c6724c886ab674148e7a241d7761b63d8b700fbeb2b3f4105329bb ./zynq7/tile_type_CLK_BUFG_REBUF.json`](./zynq7/tile_type_CLK_BUFG_REBUF.json)
* [`b1fdae383da0691975b3836a0a66fa566165de094e4bd416d664dc32f2d010c8 ./zynq7/tile_type_CLK_BUFG_TOP_R.json`](./zynq7/tile_type_CLK_BUFG_TOP_R.json)
* [`9900c1d7c03b75bb765c57b00b20fbefd09efeccb325afba72901b941d5db0de ./zynq7/tile_type_CLK_FEED.json`](./zynq7/tile_type_CLK_FEED.json)
* [`fa0923a2169819ecc93697c7255aef24e9dbee2a3c5d8c1df3f86956e0bc8b08 ./zynq7/tile_type_CLK_HROW_BOT_R.json`](./zynq7/tile_type_CLK_HROW_BOT_R.json)
* [`71f60f081cb9718ca95f3c004034dde427a1323ae4f71f94c68f3ecb961f1d2f ./zynq7/tile_type_CLK_HROW_TOP_R.json`](./zynq7/tile_type_CLK_HROW_TOP_R.json)
* [`3d200f97f5d0608d4577dcaf9ae59c34be18f4d1406aa71815d56327fc2a3564 ./zynq7/tile_type_CLK_MTBF2.json`](./zynq7/tile_type_CLK_MTBF2.json)
* [`0163ab8305f14d439e303fc072bf980549efd65c42494e468bc2b2e0bd3ff0a6 ./zynq7/tile_type_CLK_PMV.json`](./zynq7/tile_type_CLK_PMV.json)
* [`1e08a2d1f2c7e0ec12b0eec202c3759fbfc82fab01b9d0b5d1658299d8ac5506 ./zynq7/tile_type_CLK_PMV2.json`](./zynq7/tile_type_CLK_PMV2.json)
* [`bf52b93861ca5856dab593dde196a21ab8a9522b4eb58f13fe206beaba8c78f2 ./zynq7/tile_type_CLK_PMV2_SVT.json`](./zynq7/tile_type_CLK_PMV2_SVT.json)
* [`e7123b7dbeba2ebbf4a6ae04fb87bd114548befc9bb812d7bf4bee3401aa44fa ./zynq7/tile_type_CLK_PMVIOB.json`](./zynq7/tile_type_CLK_PMVIOB.json)
* [`42236b4ea5a40883822299aef2c5eb6ef2adb30c715145a9c36c5dd9e84e102e ./zynq7/tile_type_CLK_TERM.json`](./zynq7/tile_type_CLK_TERM.json)
* [`f985c5c1c1186eb314e1bd727b4195b88f69739fcb991efbafee963310b880f9 ./zynq7/tile_type_CMT_FIFO_L.json`](./zynq7/tile_type_CMT_FIFO_L.json)
* [`9207ebd19f94b6a3a9d8ea08f1fe78dcf592d3b5b5f541694a23d5dc1a9163e3 ./zynq7/tile_type_CMT_PMV_L.json`](./zynq7/tile_type_CMT_PMV_L.json)
* [`63d8187207a325d174e8d509014200531f3e11236e5064c2675871ca42fbbffa ./zynq7/tile_type_CMT_TOP_L_LOWER_B.json`](./zynq7/tile_type_CMT_TOP_L_LOWER_B.json)
* [`129c5c28dee6d7cc79263d280a391c07b5db326124ad1e973582643d9eadff3a ./zynq7/tile_type_CMT_TOP_L_LOWER_T.json`](./zynq7/tile_type_CMT_TOP_L_LOWER_T.json)
* [`3c645c7e32529af66b278c8c06734bb052d1be00ff801772d28147b1e62da2ff ./zynq7/tile_type_CMT_TOP_L_UPPER_B.json`](./zynq7/tile_type_CMT_TOP_L_UPPER_B.json)
* [`e008d249e1f1dafa57e4ac276826c60e24b7fd29ec4e5acafd078c0604631afc ./zynq7/tile_type_CMT_TOP_L_UPPER_T.json`](./zynq7/tile_type_CMT_TOP_L_UPPER_T.json)
* [`4ddd2c3e96995a4acf4320877f3ab6ade22d9b475eb8b2e46cb64c325b92e386 ./zynq7/tile_type_DSP_L.json`](./zynq7/tile_type_DSP_L.json)
* [`b7f2ec5fcaf13becd7a73baa9271370dd80ccc24a1dc52bbe4ec2a450aabd7ad ./zynq7/tile_type_DSP_R.json`](./zynq7/tile_type_DSP_R.json)
* [`05eb17dc54b29fac95e4b2ac067139b528c1bc7f5cb78b672e6941a2966ec7bb ./zynq7/tile_type_HCLK_BRAM.json`](./zynq7/tile_type_HCLK_BRAM.json)
* [`307db3c561c03036e0460d24af8d435631bbacef7f81c0385f6179673d818d50 ./zynq7/tile_type_HCLK_CLB.json`](./zynq7/tile_type_HCLK_CLB.json)
* [`4af6db5c406dd683670c77fe2dbfcfd64b0d079e59e3082cfc4e578789cddf45 ./zynq7/tile_type_HCLK_CMT_L.json`](./zynq7/tile_type_HCLK_CMT_L.json)
* [`cbcd13d3b6a78888a73e22e1e33e56c80b5fcb23c4d1baf938b4b6daa02173f7 ./zynq7/tile_type_HCLK_DSP_L.json`](./zynq7/tile_type_HCLK_DSP_L.json)
* [`dacc707f9e2db1d6752f833cf0559536423baf915a848b3ff641373f4762793f ./zynq7/tile_type_HCLK_DSP_R.json`](./zynq7/tile_type_HCLK_DSP_R.json)
* [`c1d33fee3af7b2ba311bad50d6f8b771303ebd8241e617ec638b1fcb8d2c4ee0 ./zynq7/tile_type_HCLK_FEEDTHRU_1.json`](./zynq7/tile_type_HCLK_FEEDTHRU_1.json)
* [`2c887222cc585d9f90588029f5076f4a6dc8b7449928f5ba1d919845076c0b9d ./zynq7/tile_type_HCLK_FEEDTHRU_1_PELE.json`](./zynq7/tile_type_HCLK_FEEDTHRU_1_PELE.json)
* [`0e991e5fc85e54835a7de8da8456ee1300d97d798fb12d16c521a9163500a20c ./zynq7/tile_type_HCLK_FEEDTHRU_2.json`](./zynq7/tile_type_HCLK_FEEDTHRU_2.json)
* [`1631fbdf6e3158d6e372508b55e32e3e638b270e0ca606359b4ad060f6337cea ./zynq7/tile_type_HCLK_FIFO_L.json`](./zynq7/tile_type_HCLK_FIFO_L.json)
* [`6a66fa18fdad81ae738e61f650066415a2adc7d15b15ab87b5080faff3edb9e1 ./zynq7/tile_type_HCLK_INT_INTERFACE.json`](./zynq7/tile_type_HCLK_INT_INTERFACE.json)
* [`51fbaa9613664a08814f372c5791189ceb855720997334f55e52872cc6d4c46f ./zynq7/tile_type_HCLK_IOB.json`](./zynq7/tile_type_HCLK_IOB.json)
* [`5e15b63a15fd7864d838d448599718e5f82e8caafa8fd316eb19374e20c0d89c ./zynq7/tile_type_HCLK_IOI3.json`](./zynq7/tile_type_HCLK_IOI3.json)
* [`2c39172c06f58c30f92d140c6c7c060777b1b3f397a23b9cf82a41a656da82ef ./zynq7/tile_type_HCLK_L.json`](./zynq7/tile_type_HCLK_L.json)
* [`782d62d7a78ca8282570a945739057b1801795271764120ff4f20696a36e9354 ./zynq7/tile_type_HCLK_R.json`](./zynq7/tile_type_HCLK_R.json)
* [`5b459ee856bd5417b0c61831120d27cebb7f5c6ae4952470bdc6dc6bad6c5b49 ./zynq7/tile_type_HCLK_TERM.json`](./zynq7/tile_type_HCLK_TERM.json)
* [`e706c7cf142b8e806283d3cf030f89e30149bad7b2f156e739e2f41247922792 ./zynq7/tile_type_HCLK_VBRK.json`](./zynq7/tile_type_HCLK_VBRK.json)
* [`acabe2c19ef9286451b67f889608af10b57c4149be795c7b9e96c700e673741a ./zynq7/tile_type_HCLK_VFRAME.json`](./zynq7/tile_type_HCLK_VFRAME.json)
* [`fe9a6b9109c94abc0860142566f1d6c292b5313f2ebe641dbd3f4d41671d05a2 ./zynq7/tile_type_INT_FEEDTHRU_1.json`](./zynq7/tile_type_INT_FEEDTHRU_1.json)
* [`1ff618718c404f469eed1fc7499db1a7bcfa90bf152b317b07511d1e070d7622 ./zynq7/tile_type_INT_FEEDTHRU_2.json`](./zynq7/tile_type_INT_FEEDTHRU_2.json)
* [`08db2bc2bc634b16af1988b445a896ffdbe75e2275647657dd44dbc9e436ec9f ./zynq7/tile_type_INT_INTERFACE_L.json`](./zynq7/tile_type_INT_INTERFACE_L.json)
* [`39d9152faf8afe07a8605aaf0e775b2668dca2eed3a46e4c1b6d444f594308db ./zynq7/tile_type_INT_INTERFACE_PSS_L.json`](./zynq7/tile_type_INT_INTERFACE_PSS_L.json)
* [`3f04e660e8a477ae99b5349c70d4bb420ed61c823ead17915a2900cc2210ad46 ./zynq7/tile_type_INT_INTERFACE_R.json`](./zynq7/tile_type_INT_INTERFACE_R.json)
* [`cc47a410209b8beb6140d0216de2b298547116a90f4cd7cf9674785e838f4c36 ./zynq7/tile_type_INT_L.json`](./zynq7/tile_type_INT_L.json)
* [`784502f54f667eb147924b061bc62829588d0e43673f32fd9d45113b6f740457 ./zynq7/tile_type_INT_R.json`](./zynq7/tile_type_INT_R.json)
* [`cf049a6c528634761c6067610f50110102caadc782a33b855f4059df8ed064d9 ./zynq7/tile_type_IO_INT_INTERFACE_R.json`](./zynq7/tile_type_IO_INT_INTERFACE_R.json)
* [`ec029a5a1ca3912c5582864edab9b46e0e955e901a8f08264bf9ec3fba0aca0d ./zynq7/tile_type_MONITOR_BOT_PELE1.json`](./zynq7/tile_type_MONITOR_BOT_PELE1.json)
* [`6ead1217a6413d2ce272c1447b230031b508d1cc897ec80260d4afb03f66dcdf ./zynq7/tile_type_MONITOR_MID_PELE1.json`](./zynq7/tile_type_MONITOR_MID_PELE1.json)
* [`1c88d8e7f113af2e568b2ddaa0f0a7da71bd5fcb97a19aca2caef1d963e60e3a ./zynq7/tile_type_MONITOR_TOP_PELE1.json`](./zynq7/tile_type_MONITOR_TOP_PELE1.json)
* [`880cdcd99af7ea01e4ee142860e0900c6c3503da3b3582837fedba1a2cafa852 ./zynq7/tile_type_NULL.json`](./zynq7/tile_type_NULL.json)
* [`944d9c69913b23cac150f0c80c14284d57fab43f69202a6cc63afaddce23221b ./zynq7/tile_type_PCIE_NULL.json`](./zynq7/tile_type_PCIE_NULL.json)
* [`a122f8026a2a5edab39eabc9117a63bc29fb1d2aeaf7b1afd2b40d1b493afa4d ./zynq7/tile_type_PSS0.json`](./zynq7/tile_type_PSS0.json)
* [`178db0b66318b31f8852f82297ab39d02287feca33c4fd8284f1c0e19791082a ./zynq7/tile_type_PSS1.json`](./zynq7/tile_type_PSS1.json)
* [`930dab9d5b0aab1594cb0ef933495683925bde169d9c1128304d5a0062a7906d ./zynq7/tile_type_PSS2.json`](./zynq7/tile_type_PSS2.json)
* [`a40337531311fa9e1bc0371b0deee86008a7cba18f3924a62b0e684f9f1b4537 ./zynq7/tile_type_PSS3.json`](./zynq7/tile_type_PSS3.json)
* [`bda246d0e8ea8ca946ba6877502428ed0fd52240fb6fc5339d9b263653c0cf93 ./zynq7/tile_type_PSS4.json`](./zynq7/tile_type_PSS4.json)
* [`a01a9bfa1d6ac7762d56b57487ab1f4efa8f53e77c6fa452adfa3aff120811fb ./zynq7/tile_type_RIOB33.json`](./zynq7/tile_type_RIOB33.json)
* [`66ea3a8940b40915699e7e2fa37b3d65403e7f5d51afe0daf14537e662da9385 ./zynq7/tile_type_RIOB33_SING.json`](./zynq7/tile_type_RIOB33_SING.json)
* [`96029c4d8a29149b3aa063bbcd3a64bbbf28f987e8e491d2630f7e78d47354b2 ./zynq7/tile_type_RIOI3.json`](./zynq7/tile_type_RIOI3.json)
* [`6c8c8745a8bcd8ebcf6396dfda55fd7b958b2de19ac1a926e412716b7d8dd2b2 ./zynq7/tile_type_RIOI3_SING.json`](./zynq7/tile_type_RIOI3_SING.json)
* [`89b4d83a435609119ca878a4cdbfc3fc31c8c30d66459bf3d84b4c8c012c1139 ./zynq7/tile_type_RIOI3_TBYTESRC.json`](./zynq7/tile_type_RIOI3_TBYTESRC.json)
* [`e188cfd52a8cd3edb869bd29a02e95e8cfc06688727982f9c364c54b5d20c409 ./zynq7/tile_type_RIOI3_TBYTETERM.json`](./zynq7/tile_type_RIOI3_TBYTETERM.json)
* [`16627ffc9c74acf89474ad03993367d2210f40d4ab07a8c71c98d9ad652f2ca8 ./zynq7/tile_type_R_TERM_INT.json`](./zynq7/tile_type_R_TERM_INT.json)
* [`19503481fb531f7ddc5f92fdc7c97a817ce1cf550e128604041c771f2234b7fa ./zynq7/tile_type_TERM_CMT.json`](./zynq7/tile_type_TERM_CMT.json)
* [`f5ebbeee5575e5fbc1fb5d532f021e4ee8647de21b3874caac655d8c849a9ff3 ./zynq7/tile_type_T_TERM_INT.json`](./zynq7/tile_type_T_TERM_INT.json)
* [`dee783006fa5b5964d20457323cad59171a60397d730e9fe0840389587695727 ./zynq7/tile_type_VBRK.json`](./zynq7/tile_type_VBRK.json)
* [`004efcd7f9e172780ca7b8c379ec329bcfc52f86beaa1d997f41dbef7ac4a242 ./zynq7/tile_type_VFRAME.json`](./zynq7/tile_type_VFRAME.json)
* [`f24ee0973df88b1dd73e1937a350b09e1dac35d72e57f3f246c267d2426d63b6 ./zynq7/tile_type_BRAM_INT_INTERFACE_L.json`](./zynq7/tile_type_BRAM_INT_INTERFACE_L.json)
* [`c95ac9e2d604c8cc8783732fd378f5aee563db5161265ee56ba2ae8410e9bdbb ./zynq7/tile_type_BRAM_INT_INTERFACE_R.json`](./zynq7/tile_type_BRAM_INT_INTERFACE_R.json)
* [`73ea54de75eaff030c2ee02aa6791bba283c0a91bf6c37fbdd878fdf3b76f88b ./zynq7/tile_type_BRAM_L.json`](./zynq7/tile_type_BRAM_L.json)
* [`85c92e649e0bb187a1fda5861f5b596a5023db1743824b19f7a2f6d326ba8b06 ./zynq7/tile_type_BRAM_R.json`](./zynq7/tile_type_BRAM_R.json)
* [`5fed21fa51d7da12161c39f1f348bdf80b08df28c01d106959e9125c2bbc2ea6 ./zynq7/tile_type_BRKH_BRAM.json`](./zynq7/tile_type_BRKH_BRAM.json)
* [`f3c6f6f895b114fce5aa917dad371892926a80f34cac8e7a084561ad2fe22579 ./zynq7/tile_type_BRKH_CLB.json`](./zynq7/tile_type_BRKH_CLB.json)
* [`f4a1d3eac4ed9046f4b4df9d925b62080d70ac295cd492c008bdd543b5714a7f ./zynq7/tile_type_BRKH_CLK.json`](./zynq7/tile_type_BRKH_CLK.json)
* [`1a81bf9fbc72eb95ba686a6f0ebdcf5afd305ebc4c45a22d38857e83933ce3c1 ./zynq7/tile_type_BRKH_CMT.json`](./zynq7/tile_type_BRKH_CMT.json)
* [`7865b3f082f74329f8d795eda8497ab16f35436dec393ec60fb827127e6858e7 ./zynq7/tile_type_BRKH_DSP_L.json`](./zynq7/tile_type_BRKH_DSP_L.json)
* [`7b3184855f2fcaf13bc7a835b14fd35bc11c72841f2240e51703434ead3e2da3 ./zynq7/tile_type_BRKH_DSP_R.json`](./zynq7/tile_type_BRKH_DSP_R.json)
* [`6ca4696204303eb6a546a453513c87241480b9a273e99cf2c5512dd7abcca82c ./zynq7/tile_type_BRKH_INT.json`](./zynq7/tile_type_BRKH_INT.json)
* [`569bab17633b363bedb66f1e55da4e36edac937a6653933863ee0a95832c4ccf ./zynq7/tile_type_B_TERM_INT.json`](./zynq7/tile_type_B_TERM_INT.json)
* [`9b10dc51a32b2113193337807fa4bb0ff9e51ffb10e24f96a4e3070fc0a90c6e ./zynq7/tile_type_B_TERM_INT_PSS.json`](./zynq7/tile_type_B_TERM_INT_PSS.json)
* [`8a63872373a1adf0b60871588272f24b946f9b3dfeee7d951159e50f4758b003 ./zynq7/tile_type_B_TERM_VBRK.json`](./zynq7/tile_type_B_TERM_VBRK.json)
* [`ef7ff05b9b709a8d4cd368e264e796b1fcdd774065e247e584f42a746eb48576 ./zynq7/tile_type_CFG_CENTER_BOT.json`](./zynq7/tile_type_CFG_CENTER_BOT.json)
* [`375a0d6b8c33de1436c8efaa580c611874c10ab6b1dc575bad879d3a9bd3700e ./zynq7/tile_type_CFG_CENTER_MID.json`](./zynq7/tile_type_CFG_CENTER_MID.json)
* [`e4aafa355a8534302dd7ba06fd8ece448b09b7c85b148c6374ee555c8174550c ./zynq7/tile_type_CFG_CENTER_TOP.json`](./zynq7/tile_type_CFG_CENTER_TOP.json)
* [`af89c0ce6f4d15929ece7fb2bd3775a1040550a07b4a64b876d4b05e9fb689f9 ./zynq7/tile_type_CFG_SECURITY_BOT_PELE1.json`](./zynq7/tile_type_CFG_SECURITY_BOT_PELE1.json)
* [`88822baff15e6d783118322eddf5a01179e1e1e94dd8a16c0e1c5059d5977ac7 ./zynq7/tile_type_CFG_SECURITY_MID_PELE1.json`](./zynq7/tile_type_CFG_SECURITY_MID_PELE1.json)
* [`a6707c7d0a9e9bb98fe398f6dd70d8327ed9b9c647c3fb6ce7b7959730c1b646 ./zynq7/tile_type_CFG_SECURITY_TOP_PELE1.json`](./zynq7/tile_type_CFG_SECURITY_TOP_PELE1.json)
* [`4abb229d18ed0c58cefd8d2d8955f083e047f92e6367829c0b394ade6ce01f1a ./zynq7/tile_type_CLBLL_L.json`](./zynq7/tile_type_CLBLL_L.json)
* [`88f100fbac0edb7bcbbdbef5daddcc6c4e217826311b395c6d386ff42054f7c4 ./zynq7/tile_type_CLBLL_R.json`](./zynq7/tile_type_CLBLL_R.json)
* [`98ec1f4221138e2d443de313e460541c69dc1ff3708dbaa60b5afcb4b113d94a ./zynq7/tile_type_CLBLM_L.json`](./zynq7/tile_type_CLBLM_L.json)
* [`b0d76a7bd251d5053988f836dc9a3d0bf6aa6b0b88a5ac5da7978884f8568323 ./zynq7/tile_type_CLBLM_R.json`](./zynq7/tile_type_CLBLM_R.json)
* [`f3bd053eac4e788954750834c04cc59fb6b993770b00317b6b00cc1cbed16b44 ./zynq7/tile_type_CLK_BUFG_BOT_R.json`](./zynq7/tile_type_CLK_BUFG_BOT_R.json)
* [`a2670c56315bfa6d2c7b264a00bd9f94fc57707070fafa016723052c2ea6c7c7 ./zynq7/tile_type_CLK_BUFG_REBUF.json`](./zynq7/tile_type_CLK_BUFG_REBUF.json)
* [`92682bfae56bc36eff0dd8e507b4fbf49945f1f612b2951a8a09006f1b947635 ./zynq7/tile_type_CLK_BUFG_TOP_R.json`](./zynq7/tile_type_CLK_BUFG_TOP_R.json)
* [`4511dcbf42306a70f8413845560367a11c4ebef76732738cfe339cc7cbf7a332 ./zynq7/tile_type_CLK_FEED.json`](./zynq7/tile_type_CLK_FEED.json)
* [`9532d9fbc982b2b37d91b08e4cf675ab3c363ab62d0656d341e3a507d51b1d37 ./zynq7/tile_type_CLK_HROW_BOT_R.json`](./zynq7/tile_type_CLK_HROW_BOT_R.json)
* [`34bb254ff5e7d4564d592dfddc57caeb55e26dfd1add81ae47732c1c49324f2b ./zynq7/tile_type_CLK_HROW_TOP_R.json`](./zynq7/tile_type_CLK_HROW_TOP_R.json)
* [`0ab174146714c57d124b00d710e4b61451fd7616330659df7854542a9266cd3f ./zynq7/tile_type_CLK_MTBF2.json`](./zynq7/tile_type_CLK_MTBF2.json)
* [`7465e9e40a7564598e859620faf75bc9c230b5d41a6141c0fc58f1ea7fce7bf2 ./zynq7/tile_type_CLK_PMV.json`](./zynq7/tile_type_CLK_PMV.json)
* [`c7fa3a115807b7a7e26648bfd754df16098aeb40d835cf03355d8ff361f25872 ./zynq7/tile_type_CLK_PMV2.json`](./zynq7/tile_type_CLK_PMV2.json)
* [`b41f19caae976764c738da165f14ee36df6d6c99296fcb829e359b4dce884367 ./zynq7/tile_type_CLK_PMV2_SVT.json`](./zynq7/tile_type_CLK_PMV2_SVT.json)
* [`fbe2edf0894ee5fe23f5aec0e34dce567a2cdaa22805ac6ac1f834b52259522b ./zynq7/tile_type_CLK_PMVIOB.json`](./zynq7/tile_type_CLK_PMVIOB.json)
* [`1dfd3414cd2cd1225ae057f91a904dbac0d868e8a674066e1a0c180743524b9c ./zynq7/tile_type_CLK_TERM.json`](./zynq7/tile_type_CLK_TERM.json)
* [`61eb6b1524330329616ab023459f9e006da8da1d25b64cbbfd48b0b78f6ba4e0 ./zynq7/tile_type_CMT_FIFO_L.json`](./zynq7/tile_type_CMT_FIFO_L.json)
* [`1591ab4ac65220fbd23662787457ece5aa0705bc829a6bdf61b44884809ba811 ./zynq7/tile_type_CMT_PMV_L.json`](./zynq7/tile_type_CMT_PMV_L.json)
* [`e26ded0ddb634d45048c646d1e701c50168c3ec9d675fca06b696290e0e7ac98 ./zynq7/tile_type_CMT_TOP_L_LOWER_B.json`](./zynq7/tile_type_CMT_TOP_L_LOWER_B.json)
* [`f5cf9ae4fdaa79041c8c65dba614a38bae621a8549a095b5c6ee99da05c3a912 ./zynq7/tile_type_CMT_TOP_L_LOWER_T.json`](./zynq7/tile_type_CMT_TOP_L_LOWER_T.json)
* [`bc7de806ba96818d8e1a1a3937467deee3e1377e45afafdeb37bd83a1779da2f ./zynq7/tile_type_CMT_TOP_L_UPPER_B.json`](./zynq7/tile_type_CMT_TOP_L_UPPER_B.json)
* [`2c7422216c30cb832ef5bb6cca33a4a9c2e9825c941b39e576a0d978831c59ea ./zynq7/tile_type_CMT_TOP_L_UPPER_T.json`](./zynq7/tile_type_CMT_TOP_L_UPPER_T.json)
* [`059ef3a432f033abc56178ce73ffbf2c03e6ca623a3db200674f84a11bd9b5e4 ./zynq7/tile_type_DSP_L.json`](./zynq7/tile_type_DSP_L.json)
* [`2aa2188d24628bde1cb14094a0ad8d7bde2c8f09194dccdaa798b83854faac69 ./zynq7/tile_type_DSP_R.json`](./zynq7/tile_type_DSP_R.json)
* [`fe27db14b76b461aa9b21f596df89860456b63da3d040bc1491cc5ebcd9e21c6 ./zynq7/tile_type_HCLK_BRAM.json`](./zynq7/tile_type_HCLK_BRAM.json)
* [`6a207032a32081ca4119b306e1144b4e0e9bfc890413aac65c558ba14c3fb5ca ./zynq7/tile_type_HCLK_CLB.json`](./zynq7/tile_type_HCLK_CLB.json)
* [`c76a6ac4dd79b5f45c574bd050cb4043ba6c03f147c31b7618b3e67f1b519ac6 ./zynq7/tile_type_HCLK_CMT_L.json`](./zynq7/tile_type_HCLK_CMT_L.json)
* [`1ee8f9b2ca6f84824725705c135db8e8f21ee0a0c66c034123c2dae5c7b392ba ./zynq7/tile_type_HCLK_DSP_L.json`](./zynq7/tile_type_HCLK_DSP_L.json)
* [`2a121fb98cb89927421fd60fde2d893ff22d32003b6f79279724fa1230459185 ./zynq7/tile_type_HCLK_DSP_R.json`](./zynq7/tile_type_HCLK_DSP_R.json)
* [`7756e9585aa1e0eb50790b1efa4984474fe16fe01d2a2d243f42d7f36123c0ac ./zynq7/tile_type_HCLK_FEEDTHRU_1.json`](./zynq7/tile_type_HCLK_FEEDTHRU_1.json)
* [`82747ca0ce2ce448e81c2402edbc144fd466ca0e22e566d6a864e45a699cf1c2 ./zynq7/tile_type_HCLK_FEEDTHRU_1_PELE.json`](./zynq7/tile_type_HCLK_FEEDTHRU_1_PELE.json)
* [`bce1ef5bdc632645054a57fa0bc022a3f3c85717a80c1daba3eb9f777836333d ./zynq7/tile_type_HCLK_FEEDTHRU_2.json`](./zynq7/tile_type_HCLK_FEEDTHRU_2.json)
* [`20ffd03177494bd2a2c4565268c345b76802bfbdf711cf863626c104778991ba ./zynq7/tile_type_HCLK_FIFO_L.json`](./zynq7/tile_type_HCLK_FIFO_L.json)
* [`979fb1ba45151227f96a4b15cc647fcfe3384e36a334cfadb0c60773b09eca78 ./zynq7/tile_type_HCLK_INT_INTERFACE.json`](./zynq7/tile_type_HCLK_INT_INTERFACE.json)
* [`b168549e91632121e51d99b9e681d975bf1aecf04b38600ee834ad318053e3a6 ./zynq7/tile_type_HCLK_IOB.json`](./zynq7/tile_type_HCLK_IOB.json)
* [`9548b7c8b0659ec49597d5502bad6b4040fe8e9e4cb2b560e514cd00ab61f286 ./zynq7/tile_type_HCLK_IOI3.json`](./zynq7/tile_type_HCLK_IOI3.json)
* [`6025a2c09f21c52b05c9c7e73af7b86e742dd7ca542834fc7d242e7a17fb8ac8 ./zynq7/tile_type_HCLK_L.json`](./zynq7/tile_type_HCLK_L.json)
* [`1af49f83d7b2e46a77a0b7f5c2601a68584d85810524c395a35b1eb83b234184 ./zynq7/tile_type_HCLK_R.json`](./zynq7/tile_type_HCLK_R.json)
* [`2df032665e26af5c97a814575440731c0d7b2bac733e1b0dcfe42d3870d9d1d7 ./zynq7/tile_type_HCLK_TERM.json`](./zynq7/tile_type_HCLK_TERM.json)
* [`4b43030e650607a9c5473a03827fdfbf990d241aa48f4093c71572ff86bf0183 ./zynq7/tile_type_HCLK_VBRK.json`](./zynq7/tile_type_HCLK_VBRK.json)
* [`8f70b2cefb458f2d3ff09123e58a891bd7ece80ae7cab637d738659799709318 ./zynq7/tile_type_HCLK_VFRAME.json`](./zynq7/tile_type_HCLK_VFRAME.json)
* [`432c6ad451ebf276da839671059c761584a6092cac75a4e14ff8f8de71bc923c ./zynq7/tile_type_INT_FEEDTHRU_1.json`](./zynq7/tile_type_INT_FEEDTHRU_1.json)
* [`938be9bbb0126fef543f27913c463e26edd5a8031067ff1a0e961e06823ae7f5 ./zynq7/tile_type_INT_FEEDTHRU_2.json`](./zynq7/tile_type_INT_FEEDTHRU_2.json)
* [`312ea0c10c73169aedd6e53a9465c2a597e922067d0c32a7c0f06a341f044f45 ./zynq7/tile_type_INT_INTERFACE_L.json`](./zynq7/tile_type_INT_INTERFACE_L.json)
* [`cbe641b878935eca85afb55a4c3aa3f31d423898bbf3e1826d90ba2472ee6be8 ./zynq7/tile_type_INT_INTERFACE_PSS_L.json`](./zynq7/tile_type_INT_INTERFACE_PSS_L.json)
* [`20258948fa358760722361c879658b898a6739c2ba9c9bd83bf7eb776a15792c ./zynq7/tile_type_INT_INTERFACE_R.json`](./zynq7/tile_type_INT_INTERFACE_R.json)
* [`bd1bd64243d040c0414b7f17007dcde384dfedfd59fa60b795bc8971d04f881c ./zynq7/tile_type_INT_L.json`](./zynq7/tile_type_INT_L.json)
* [`dc8af3f4e2e58cf2f43e234e599c8efaf7a89a7814d2421e60c416ad74bb7e43 ./zynq7/tile_type_INT_R.json`](./zynq7/tile_type_INT_R.json)
* [`eee676d3887fb0d19ba1054ed73fe691745d524b3852053d0a5544f907e240c8 ./zynq7/tile_type_IO_INT_INTERFACE_R.json`](./zynq7/tile_type_IO_INT_INTERFACE_R.json)
* [`8e492b13c6437353e40f655351183be17b9c44f0e1030a3af0c1882ccecd1eab ./zynq7/tile_type_MONITOR_BOT_PELE1.json`](./zynq7/tile_type_MONITOR_BOT_PELE1.json)
* [`016410ef9c50838aa42030a63770c706c7d8e40a29838da88e3f465710461266 ./zynq7/tile_type_MONITOR_MID_PELE1.json`](./zynq7/tile_type_MONITOR_MID_PELE1.json)
* [`26ceeec9bd470c21d8fa3c07beb22cef67c5b373085d2425ec6bf3eacc765a31 ./zynq7/tile_type_MONITOR_TOP_PELE1.json`](./zynq7/tile_type_MONITOR_TOP_PELE1.json)
* [`d430688c70e289f09318774410f2f55e53639c3544fca8a3c98d420f714b0c2f ./zynq7/tile_type_NULL.json`](./zynq7/tile_type_NULL.json)
* [`a246242840607ca7b8e3b45d44d7cf7fcc145fad4c973536575742c8b9bc9a42 ./zynq7/tile_type_PCIE_NULL.json`](./zynq7/tile_type_PCIE_NULL.json)
* [`69f71a0851833685555bbbd829f42f13b9f699f1909591e1fff1a920e86b27d6 ./zynq7/tile_type_PSS0.json`](./zynq7/tile_type_PSS0.json)
* [`7a17b0d5ac0fe2753441a4cd3e3479b7cba2dace3e11b2ac3bc1615cefe6cce0 ./zynq7/tile_type_PSS1.json`](./zynq7/tile_type_PSS1.json)
* [`daec77be7e5c046d4de49cf4c94a804a3c90745ce71f20714bfe764733d21f85 ./zynq7/tile_type_PSS2.json`](./zynq7/tile_type_PSS2.json)
* [`e7dd99a5210eb44a7e2c537447f5feff9c68de8385e1bdde4ef65b20af9deb59 ./zynq7/tile_type_PSS3.json`](./zynq7/tile_type_PSS3.json)
* [`04febdb8b183f1b976da61333fd10c39479390f3d4c7671ae727438f0c517f64 ./zynq7/tile_type_PSS4.json`](./zynq7/tile_type_PSS4.json)
* [`7469d05ba321c92ed72125d2894f717b5741ce7444a8265ae51cc6a2c547a491 ./zynq7/tile_type_RIOB33.json`](./zynq7/tile_type_RIOB33.json)
* [`73eb4020bd019345fcab4dec38d9a2347699435966caa4bd63cecf87a7b8a637 ./zynq7/tile_type_RIOB33_SING.json`](./zynq7/tile_type_RIOB33_SING.json)
* [`dd554abb6ca027deef90d6245a59d7bbc5e5701f3d0e304c434edf0f3f1015ea ./zynq7/tile_type_RIOI3.json`](./zynq7/tile_type_RIOI3.json)
* [`990370b5daec491bb4fb3549436d509ae7ffed104931775a60e4c9adf5000386 ./zynq7/tile_type_RIOI3_SING.json`](./zynq7/tile_type_RIOI3_SING.json)
* [`9d00ddd84a1656989bf77e826b07676f2d6195a521066fa2aac18a7afcdc831b ./zynq7/tile_type_RIOI3_TBYTESRC.json`](./zynq7/tile_type_RIOI3_TBYTESRC.json)
* [`00fc92093158507c654f566d2a18b5206e26e62f1527ef0c790e098c7602ee9e ./zynq7/tile_type_RIOI3_TBYTETERM.json`](./zynq7/tile_type_RIOI3_TBYTETERM.json)
* [`f8636b98f24c07c250ea284be61826439e4557a3d75c8571cc3c00bc47d61f8c ./zynq7/tile_type_R_TERM_INT.json`](./zynq7/tile_type_R_TERM_INT.json)
* [`fc909565278739a6beeb94d5bcb0780a6ec3dfa2d0f83389699974abc3d0427a ./zynq7/tile_type_TERM_CMT.json`](./zynq7/tile_type_TERM_CMT.json)
* [`372e4b47e58b79d8d6d587ee1459a576edbd7eebad7e8a49eba3e2c71cf3a536 ./zynq7/tile_type_T_TERM_INT.json`](./zynq7/tile_type_T_TERM_INT.json)
* [`9d6388021982de6d4a676c2c2fe6543029a2f44db45d290f4e827d35b91a2a6b ./zynq7/tile_type_VBRK.json`](./zynq7/tile_type_VBRK.json)
* [`63851d7ed48855486ee7e04a6332935799e8d2f3524ec6d627ea6e5d2e7cbfa4 ./zynq7/tile_type_VFRAME.json`](./zynq7/tile_type_VFRAME.json)
* [`e6d0ebf9b27f60f4afdab85a357bff4d7cf2cd77c3a6c0f2d887022cda874066 ./zynq7/tileconn.json`](./zynq7/tileconn.json)
* [`93ae29cf7cd85ac8baf94a8e98cc7857d3cdd7ac0ad5720a42d6da1597b6d773 ./zynq7/tilegrid.json`](./zynq7/tilegrid.json)
* [`15e8ed87d38b9f9b84b52c768df922e5f5be4d860670a768e9230ad8cdca3787 ./zynq7/tilegrid.json`](./zynq7/tilegrid.json)
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/BRAM_INT_INTERFACE_L.sdf`](./zynq7/timings/BRAM_INT_INTERFACE_L.sdf)
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/BRAM_INT_INTERFACE_R.sdf`](./zynq7/timings/BRAM_INT_INTERFACE_R.sdf)
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/BRAM_L.sdf`](./zynq7/timings/BRAM_L.sdf)
@ -1077,7 +1099,7 @@ Results have checksums;
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/CLK_TERM.sdf`](./zynq7/timings/CLK_TERM.sdf)
* [`366802adb3810a1cecf1674f01fe1a97f1338a7455d7a6e4796aa004311b9c8a ./zynq7/timings/CMT_FIFO_L.sdf`](./zynq7/timings/CMT_FIFO_L.sdf)
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/CMT_PMV_L.sdf`](./zynq7/timings/CMT_PMV_L.sdf)
* [`c2e66425da5018d6e7aa2b0aec721bcecfdba26bfa26016598cd28e3112fffc4 ./zynq7/timings/CMT_TOP_L_LOWER_B.sdf`](./zynq7/timings/CMT_TOP_L_LOWER_B.sdf)
* [`8c641a845fdd56842eec7c5fe72ddbd26654593313516137b88dcb5ea83a1920 ./zynq7/timings/CMT_TOP_L_LOWER_B.sdf`](./zynq7/timings/CMT_TOP_L_LOWER_B.sdf)
* [`35863307207f2f40fdbf61f5a5065b0112305594d5375a758491ee52e2a848a8 ./zynq7/timings/CMT_TOP_L_LOWER_T.sdf`](./zynq7/timings/CMT_TOP_L_LOWER_T.sdf)
* [`e8fdd4747aa8be4e39fe2ae27f51c8442c754485c8506fc5b021150f08289e95 ./zynq7/timings/CMT_TOP_L_UPPER_B.sdf`](./zynq7/timings/CMT_TOP_L_UPPER_B.sdf)
* [`5a70eb78c2a91cef8d2322645ac12acef53241d264ce548017620963e396a8a9 ./zynq7/timings/CMT_TOP_L_UPPER_T.sdf`](./zynq7/timings/CMT_TOP_L_UPPER_T.sdf)
@ -1117,17 +1139,17 @@ Results have checksums;
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/PSS4.sdf`](./zynq7/timings/PSS4.sdf)
* [`9313a012de7cbb7120baf15fe30bf8d44b238cad6226ece1a9776746e2857863 ./zynq7/timings/RIOB33.sdf`](./zynq7/timings/RIOB33.sdf)
* [`0fdaf6a593346b5cac8899eebf4f62d1732d6d6fb0a17c9f4b6a4e54e03c3523 ./zynq7/timings/RIOB33_SING.sdf`](./zynq7/timings/RIOB33_SING.sdf)
* [`fcde8675e577127516c2362f39a19ae75e6674eb53662a31b42ffddefdd8e8e4 ./zynq7/timings/RIOI3.sdf`](./zynq7/timings/RIOI3.sdf)
* [`fcde8675e577127516c2362f39a19ae75e6674eb53662a31b42ffddefdd8e8e4 ./zynq7/timings/RIOI3_SING.sdf`](./zynq7/timings/RIOI3_SING.sdf)
* [`fcde8675e577127516c2362f39a19ae75e6674eb53662a31b42ffddefdd8e8e4 ./zynq7/timings/RIOI3_TBYTESRC.sdf`](./zynq7/timings/RIOI3_TBYTESRC.sdf)
* [`fcde8675e577127516c2362f39a19ae75e6674eb53662a31b42ffddefdd8e8e4 ./zynq7/timings/RIOI3_TBYTETERM.sdf`](./zynq7/timings/RIOI3_TBYTETERM.sdf)
* [`582431f616d6cba090545c71cea3ed3de7e1d07ee21820a2258bc9f397bb5083 ./zynq7/timings/RIOI3.sdf`](./zynq7/timings/RIOI3.sdf)
* [`582431f616d6cba090545c71cea3ed3de7e1d07ee21820a2258bc9f397bb5083 ./zynq7/timings/RIOI3_SING.sdf`](./zynq7/timings/RIOI3_SING.sdf)
* [`582431f616d6cba090545c71cea3ed3de7e1d07ee21820a2258bc9f397bb5083 ./zynq7/timings/RIOI3_TBYTESRC.sdf`](./zynq7/timings/RIOI3_TBYTESRC.sdf)
* [`582431f616d6cba090545c71cea3ed3de7e1d07ee21820a2258bc9f397bb5083 ./zynq7/timings/RIOI3_TBYTETERM.sdf`](./zynq7/timings/RIOI3_TBYTETERM.sdf)
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/R_TERM_INT.sdf`](./zynq7/timings/R_TERM_INT.sdf)
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/TERM_CMT.sdf`](./zynq7/timings/TERM_CMT.sdf)
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/T_TERM_INT.sdf`](./zynq7/timings/T_TERM_INT.sdf)
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/VBRK.sdf`](./zynq7/timings/VBRK.sdf)
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/VFRAME.sdf`](./zynq7/timings/VFRAME.sdf)
* [`ca3e3a61d6070397ffa76245f3435a036adefb318e29172580725f7f0b8eb2b6 ./zynq7/timings/slicel.sdf`](./zynq7/timings/slicel.sdf)
* [`0877c0b0d5c6dd87b2a75221fa5245f537605682b67ae4d0a064e005e701de1e ./zynq7/timings/slicem.sdf`](./zynq7/timings/slicem.sdf)
* [`bbdb8b53bb1343cefbc977089069d67ef277fa758ae77e06d50aa8de6e503ae2 ./zynq7/timings/slicel.sdf`](./zynq7/timings/slicel.sdf)
* [`b0a63e17e651071eec70a4048fc3321d79a8b0f6d430ad323eebc8b624418b0a ./zynq7/timings/slicem.sdf`](./zynq7/timings/slicem.sdf)
* [`f3704845c7559e0289c9a1c6f42a7874be6d5d7aef3e0f285647b8ca62a154b3 ./zynq7/xc7z010clg400-1.json`](./zynq7/xc7z010clg400-1.json)
* [`43a136f26603c51bd97e9489d223bbc80f278fcc234225ed9fde404402f22683 ./zynq7/xc7z010clg400-1.yaml`](./zynq7/xc7z010clg400-1.yaml)
* [`d9914c14b3a8d59c76dd5992c4727e4002acd5e14b32c1afe49f7be8798e4db9 ./zynq7/xc7z010clg400-1_package_pins.csv`](./zynq7/xc7z010clg400-1_package_pins.csv)

137
zynq7/mask_liob33.db
View File

@ -1,3 +1,4 @@
bit 00_01
bit 00_02
bit 00_03
bit 00_06
@ -13,7 +14,6 @@ bit 00_35
bit 00_38
bit 00_39
bit 00_42
bit 00_45
bit 00_46
bit 00_65
bit 00_67
@ -57,6 +57,8 @@ bit 01_101
bit 01_102
bit 01_104
bit 01_105
bit 02_02
bit 02_03
bit 02_05
bit 02_06
bit 02_07
@ -67,7 +69,6 @@ bit 02_14
bit 02_15
bit 02_22
bit 02_23
bit 02_26
bit 02_30
bit 02_31
bit 02_42
@ -96,25 +97,24 @@ bit 02_93
bit 02_94
bit 02_95
bit 02_102
bit 02_103
bit 02_106
bit 02_110
bit 02_111
bit 02_118
bit 02_125
bit 02_126
bit 02_127
bit 03_02
bit 03_04
bit 03_05
bit 03_06
bit 03_10
bit 03_12
bit 03_13
bit 03_14
bit 03_21
bit 03_29
bit 03_44
bit 03_45
bit 03_52
bit 03_53
bit 03_60
bit 03_61
@ -130,6 +130,7 @@ bit 03_93
bit 03_109
bit 03_110
bit 03_116
bit 03_125
bit 03_126
bit 04_06
bit 04_07
@ -138,6 +139,7 @@ bit 04_12
bit 04_13
bit 04_14
bit 04_15
bit 04_19
bit 04_28
bit 04_29
bit 04_30
@ -149,23 +151,21 @@ bit 04_59
bit 04_60
bit 04_61
bit 04_63
bit 04_70
bit 04_71
bit 04_75
bit 04_76
bit 04_77
bit 04_78
bit 04_79
bit 04_83
bit 04_87
bit 04_92
bit 04_93
bit 04_94
bit 04_103
bit 04_108
bit 04_111
bit 04_115
bit 04_119
bit 04_124
bit 04_125
bit 04_127
bit 05_01
bit 05_02
@ -173,6 +173,7 @@ bit 05_05
bit 05_07
bit 05_10
bit 05_13
bit 05_17
bit 05_18
bit 05_42
bit 05_49
@ -187,13 +188,15 @@ bit 05_65
bit 05_66
bit 05_68
bit 05_69
bit 05_70
bit 05_73
bit 05_74
bit 05_76
bit 05_77
bit 05_78
bit 05_81
bit 05_82
bit 05_86
bit 05_102
bit 05_110
bit 05_113
bit 05_114
@ -214,11 +217,10 @@ bit 06_13
bit 06_14
bit 06_15
bit 06_17
bit 06_20
bit 06_22
bit 06_23
bit 06_27
bit 06_28
bit 06_29
bit 06_30
bit 06_31
bit 06_39
@ -227,14 +229,12 @@ bit 06_44
bit 06_45
bit 06_46
bit 06_49
bit 06_52
bit 06_53
bit 06_59
bit 06_60
bit 06_61
bit 06_63
bit 06_65
bit 06_66
bit 06_68
bit 06_70
bit 06_71
bit 06_74
@ -250,18 +250,23 @@ bit 06_91
bit 06_92
bit 06_93
bit 06_94
bit 06_95
bit 06_103
bit 06_107
bit 06_108
bit 06_121
bit 06_123
bit 06_124
bit 06_125
bit 07_00
bit 07_02
bit 07_03
bit 07_04
bit 07_05
bit 07_06
bit 07_07
bit 07_08
bit 07_10
bit 07_11
bit 07_13
bit 07_14
@ -272,8 +277,6 @@ bit 07_20
bit 07_22
bit 07_23
bit 07_24
bit 07_27
bit 07_28
bit 07_30
bit 07_31
bit 07_32
@ -294,6 +297,7 @@ bit 07_59
bit 07_62
bit 07_63
bit 07_64
bit 07_66
bit 07_67
bit 07_68
bit 07_69
@ -306,12 +310,12 @@ bit 07_78
bit 07_79
bit 07_80
bit 07_83
bit 07_84
bit 07_86
bit 07_87
bit 07_88
bit 07_94
bit 07_95
bit 07_96
bit 07_100
bit 07_102
bit 07_103
@ -323,7 +327,6 @@ bit 07_111
bit 07_112
bit 07_115
bit 07_118
bit 07_119
bit 07_120
bit 07_126
bit 07_127
@ -352,6 +355,7 @@ bit 08_25
bit 08_26
bit 08_27
bit 08_28
bit 08_29
bit 08_30
bit 08_31
bit 08_32
@ -365,7 +369,6 @@ bit 08_43
bit 08_46
bit 08_47
bit 08_49
bit 08_53
bit 08_54
bit 08_55
bit 08_56
@ -377,7 +380,6 @@ bit 08_63
bit 08_64
bit 08_65
bit 08_66
bit 08_68
bit 08_69
bit 08_70
bit 08_71
@ -397,6 +399,7 @@ bit 08_87
bit 08_88
bit 08_89
bit 08_90
bit 08_91
bit 08_92
bit 08_93
bit 08_94
@ -421,6 +424,7 @@ bit 08_120
bit 08_121
bit 08_122
bit 08_123
bit 08_125
bit 08_126
bit 08_127
bit 09_00
@ -432,13 +436,13 @@ bit 09_05
bit 09_06
bit 09_07
bit 09_08
bit 09_10
bit 09_11
bit 09_13
bit 09_15
bit 09_16
bit 09_19
bit 09_20
bit 09_21
bit 09_22
bit 09_23
bit 09_24
@ -459,7 +463,6 @@ bit 09_53
bit 09_56
bit 09_57
bit 09_58
bit 09_59
bit 09_63
bit 09_64
bit 09_65
@ -470,10 +473,10 @@ bit 09_69
bit 09_75
bit 09_77
bit 09_79
bit 09_80
bit 09_82
bit 09_83
bit 09_84
bit 09_89
bit 09_91
bit 09_98
bit 09_99
@ -486,15 +489,17 @@ bit 09_114
bit 09_115
bit 09_116
bit 09_120
bit 09_121
bit 09_122
bit 09_123
bit 09_127
bit 10_00
bit 10_01
bit 10_02
bit 10_03
bit 10_05
bit 10_06
bit 10_07
bit 10_08
bit 10_09
bit 10_10
bit 10_11
@ -522,11 +527,11 @@ bit 10_42
bit 10_43
bit 10_46
bit 10_47
bit 10_49
bit 10_50
bit 10_52
bit 10_51
bit 10_53
bit 10_55
bit 10_56
bit 10_57
bit 10_58
bit 10_59
@ -548,12 +553,12 @@ bit 10_79
bit 10_80
bit 10_81
bit 10_82
bit 10_83
bit 10_85
bit 10_87
bit 10_88
bit 10_89
bit 10_90
bit 10_91
bit 10_92
bit 10_94
bit 10_95
@ -566,7 +571,6 @@ bit 10_107
bit 10_110
bit 10_111
bit 10_114
bit 10_115
bit 10_117
bit 10_119
bit 10_120
@ -587,6 +591,7 @@ bit 11_15
bit 11_17
bit 11_18
bit 11_19
bit 11_20
bit 11_21
bit 11_23
bit 11_24
@ -595,12 +600,14 @@ bit 11_26
bit 11_27
bit 11_31
bit 11_33
bit 11_36
bit 11_37
bit 11_39
bit 11_40
bit 11_41
bit 11_42
bit 11_43
bit 11_44
bit 11_47
bit 11_49
bit 11_50
@ -616,7 +623,6 @@ bit 11_63
bit 11_65
bit 11_66
bit 11_67
bit 11_68
bit 11_69
bit 11_71
bit 11_73
@ -626,16 +632,13 @@ bit 11_77
bit 11_79
bit 11_81
bit 11_82
bit 11_83
bit 11_87
bit 11_90
bit 11_91
bit 11_95
bit 11_97
bit 11_100
bit 11_101
bit 11_103
bit 11_104
bit 11_105
bit 11_106
bit 11_107
@ -644,11 +647,9 @@ bit 11_113
bit 11_116
bit 11_117
bit 11_119
bit 11_120
bit 11_121
bit 11_122
bit 11_123
bit 11_125
bit 11_127
bit 12_00
bit 12_01
@ -665,12 +666,13 @@ bit 12_14
bit 12_15
bit 12_16
bit 12_17
bit 12_20
bit 12_21
bit 12_23
bit 12_24
bit 12_25
bit 12_26
bit 12_27
bit 12_29
bit 12_30
bit 12_31
bit 12_33
@ -684,7 +686,8 @@ bit 12_46
bit 12_47
bit 12_48
bit 12_49
bit 12_52
bit 12_50
bit 12_51
bit 12_53
bit 12_55
bit 12_57
@ -704,13 +707,12 @@ bit 12_78
bit 12_79
bit 12_81
bit 12_82
bit 12_83
bit 12_85
bit 12_87
bit 12_88
bit 12_89
bit 12_90
bit 12_91
bit 12_93
bit 12_94
bit 12_95
bit 12_97
@ -725,7 +727,6 @@ bit 12_110
bit 12_111
bit 12_113
bit 12_114
bit 12_115
bit 12_117
bit 12_119
bit 12_120
@ -749,16 +750,17 @@ bit 13_12
bit 13_13
bit 13_14
bit 13_15
bit 13_16
bit 13_17
bit 13_18
bit 13_19
bit 13_20
bit 13_22
bit 13_23
bit 13_24
bit 13_25
bit 13_26
bit 13_28
bit 13_29
bit 13_30
bit 13_31
bit 13_33
bit 13_34
@ -781,10 +783,12 @@ bit 13_57
bit 13_58
bit 13_59
bit 13_60
bit 13_62
bit 13_63
bit 13_64
bit 13_65
bit 13_66
bit 13_67
bit 13_68
bit 13_69
bit 13_70
@ -797,9 +801,9 @@ bit 13_76
bit 13_77
bit 13_78
bit 13_79
bit 13_80
bit 13_81
bit 13_82
bit 13_83
bit 13_86
bit 13_87
bit 13_88
@ -811,7 +815,6 @@ bit 13_94
bit 13_95
bit 13_97
bit 13_98
bit 13_100
bit 13_101
bit 13_102
bit 13_103
@ -829,13 +832,16 @@ bit 13_120
bit 13_121
bit 13_122
bit 13_123
bit 13_126
bit 13_124
bit 13_125
bit 13_127
bit 14_00
bit 14_01
bit 14_02
bit 14_03
bit 14_04
bit 14_05
bit 14_07
bit 14_09
bit 14_10
bit 14_11
@ -847,19 +853,17 @@ bit 14_16
bit 14_18
bit 14_19
bit 14_20
bit 14_23
bit 14_25
bit 14_26
bit 14_28
bit 14_29
bit 14_30
bit 14_31
bit 14_34
bit 14_36
bit 14_42
bit 14_46
bit 14_50
bit 14_52
bit 14_56
bit 14_58
bit 14_64
bit 14_66
@ -869,6 +873,7 @@ bit 14_69
bit 14_71
bit 14_73
bit 14_74
bit 14_76
bit 14_77
bit 14_78
bit 14_79
@ -878,25 +883,27 @@ bit 14_84
bit 14_87
bit 14_88
bit 14_89
bit 14_90
bit 14_93
bit 14_94
bit 14_95
bit 14_98
bit 14_100
bit 14_106
bit 14_114
bit 14_116
bit 14_120
bit 14_122
bit 14_126
bit 15_00
bit 15_01
bit 15_02
bit 15_03
bit 15_04
bit 15_05
bit 15_06
bit 15_07
bit 15_08
bit 15_09
bit 15_10
bit 15_11
bit 15_12
bit 15_13
bit 15_14
@ -927,7 +934,6 @@ bit 15_63
bit 15_64
bit 15_65
bit 15_66
bit 15_68
bit 15_69
bit 15_71
bit 15_72
@ -941,7 +947,6 @@ bit 15_79
bit 15_80
bit 15_81
bit 15_82
bit 15_85
bit 15_87
bit 15_89
bit 15_90
@ -960,7 +965,6 @@ bit 15_113
bit 15_119
bit 15_121
bit 15_123
bit 15_125
bit 15_127
bit 16_02
bit 16_06
@ -973,6 +977,7 @@ bit 16_23
bit 16_24
bit 16_30
bit 16_31
bit 16_32
bit 16_35
bit 16_38
bit 16_40
@ -1002,7 +1007,6 @@ bit 16_94
bit 16_95
bit 16_99
bit 16_102
bit 16_103
bit 16_104
bit 16_106
bit 16_107
@ -1029,9 +1033,9 @@ bit 17_23
bit 17_24
bit 17_30
bit 17_31
bit 17_32
bit 17_35
bit 17_38
bit 17_39
bit 17_40
bit 17_42
bit 17_43
@ -1048,11 +1052,14 @@ bit 17_60
bit 17_62
bit 17_66
bit 17_70
bit 17_71
bit 17_73
bit 17_79
bit 17_80
bit 17_85
bit 17_86
bit 17_87
bit 17_88
bit 17_94
bit 17_95
bit 17_99
@ -1084,7 +1091,6 @@ bit 18_23
bit 18_25
bit 18_30
bit 18_31
bit 18_33
bit 18_34
bit 18_38
bit 18_39
@ -1116,6 +1122,7 @@ bit 18_97
bit 18_98
bit 18_102
bit 18_103
bit 18_105
bit 18_106
bit 18_107
bit 18_109
@ -1133,6 +1140,7 @@ bit 19_01
bit 19_03
bit 19_07
bit 19_08
bit 19_09
bit 19_14
bit 19_17
bit 19_20
@ -1152,6 +1160,7 @@ bit 19_46
bit 19_47
bit 19_49
bit 19_50
bit 19_54
bit 19_55
bit 19_56
bit 19_57
@ -1182,6 +1191,7 @@ bit 19_113
bit 19_114
bit 19_119
bit 19_120
bit 19_121
bit 19_123
bit 19_125
bit 19_127
@ -1256,6 +1266,7 @@ bit 21_85
bit 21_86
bit 21_94
bit 21_98
bit 21_99
bit 21_102
bit 21_106
bit 21_107
@ -1277,8 +1288,10 @@ bit 22_22
bit 22_23
bit 22_30
bit 22_31
bit 22_32
bit 22_35
bit 22_38
bit 22_40
bit 22_42
bit 22_43
bit 22_44
@ -1287,6 +1300,7 @@ bit 22_47
bit 22_48
bit 22_51
bit 22_54
bit 22_55
bit 22_56
bit 22_57
bit 22_58
@ -1294,21 +1308,22 @@ bit 22_60
bit 22_62
bit 22_66
bit 22_70
bit 22_71
bit 22_73
bit 22_79
bit 22_85
bit 22_86
bit 22_87
bit 22_94
bit 22_95
bit 22_96
bit 22_99
bit 22_102
bit 22_103
bit 22_106
bit 22_107
bit 22_108
bit 22_110
bit 22_111
bit 22_112
bit 22_115
bit 22_118
bit 22_121
@ -1330,7 +1345,6 @@ bit 23_31
bit 23_32
bit 23_35
bit 23_38
bit 23_39
bit 23_40
bit 23_42
bit 23_43
@ -1421,6 +1435,7 @@ bit 24_84
bit 24_85
bit 24_86
bit 24_87
bit 24_88
bit 24_94
bit 24_95
bit 24_96
@ -1446,6 +1461,7 @@ bit 25_00
bit 25_02
bit 25_06
bit 25_07
bit 25_08
bit 25_09
bit 25_15
bit 25_16
@ -1471,6 +1487,7 @@ bit 25_48
bit 25_51
bit 25_52
bit 25_54
bit 25_55
bit 25_56
bit 25_57
bit 25_58

137
zynq7/mask_riob33.db
View File

@ -1,3 +1,4 @@
bit 00_01
bit 00_02
bit 00_03
bit 00_06
@ -13,7 +14,6 @@ bit 00_35
bit 00_38
bit 00_39
bit 00_42
bit 00_45
bit 00_46
bit 00_65
bit 00_67
@ -57,6 +57,8 @@ bit 01_101
bit 01_102
bit 01_104
bit 01_105
bit 02_02
bit 02_03
bit 02_05
bit 02_06
bit 02_07
@ -67,7 +69,6 @@ bit 02_14
bit 02_15
bit 02_22
bit 02_23
bit 02_26
bit 02_30
bit 02_31
bit 02_42
@ -96,25 +97,24 @@ bit 02_93
bit 02_94
bit 02_95
bit 02_102
bit 02_103
bit 02_106
bit 02_110
bit 02_111
bit 02_118
bit 02_125
bit 02_126
bit 02_127
bit 03_02
bit 03_04
bit 03_05
bit 03_06
bit 03_10
bit 03_12
bit 03_13
bit 03_14
bit 03_21
bit 03_29
bit 03_44
bit 03_45
bit 03_52
bit 03_53
bit 03_60
bit 03_61
@ -130,6 +130,7 @@ bit 03_93
bit 03_109
bit 03_110
bit 03_116
bit 03_125
bit 03_126
bit 04_06
bit 04_07
@ -138,6 +139,7 @@ bit 04_12
bit 04_13
bit 04_14
bit 04_15
bit 04_19
bit 04_28
bit 04_29
bit 04_30
@ -149,23 +151,21 @@ bit 04_59
bit 04_60
bit 04_61
bit 04_63
bit 04_70
bit 04_71
bit 04_75
bit 04_76
bit 04_77
bit 04_78
bit 04_79
bit 04_83
bit 04_87
bit 04_92
bit 04_93
bit 04_94
bit 04_103
bit 04_108
bit 04_111
bit 04_115
bit 04_119
bit 04_124
bit 04_125
bit 04_127
bit 05_01
bit 05_02
@ -173,6 +173,7 @@ bit 05_05
bit 05_07
bit 05_10
bit 05_13
bit 05_17
bit 05_18
bit 05_42
bit 05_49
@ -187,13 +188,15 @@ bit 05_65
bit 05_66
bit 05_68
bit 05_69
bit 05_70
bit 05_73
bit 05_74
bit 05_76
bit 05_77
bit 05_78
bit 05_81
bit 05_82
bit 05_86
bit 05_102
bit 05_110
bit 05_113
bit 05_114
@ -214,11 +217,10 @@ bit 06_13
bit 06_14
bit 06_15
bit 06_17
bit 06_20
bit 06_22
bit 06_23
bit 06_27
bit 06_28
bit 06_29
bit 06_30
bit 06_31
bit 06_39
@ -227,14 +229,12 @@ bit 06_44
bit 06_45
bit 06_46
bit 06_49
bit 06_52
bit 06_53
bit 06_59
bit 06_60
bit 06_61
bit 06_63
bit 06_65
bit 06_66
bit 06_68
bit 06_70
bit 06_71
bit 06_74
@ -250,18 +250,23 @@ bit 06_91
bit 06_92
bit 06_93
bit 06_94
bit 06_95
bit 06_103
bit 06_107
bit 06_108
bit 06_121
bit 06_123
bit 06_124
bit 06_125
bit 07_00
bit 07_02
bit 07_03
bit 07_04
bit 07_05
bit 07_06
bit 07_07
bit 07_08
bit 07_10
bit 07_11
bit 07_13
bit 07_14
@ -272,8 +277,6 @@ bit 07_20
bit 07_22
bit 07_23
bit 07_24
bit 07_27
bit 07_28
bit 07_30
bit 07_31
bit 07_32
@ -294,6 +297,7 @@ bit 07_59
bit 07_62
bit 07_63
bit 07_64
bit 07_66
bit 07_67
bit 07_68
bit 07_69
@ -306,12 +310,12 @@ bit 07_78
bit 07_79
bit 07_80
bit 07_83
bit 07_84
bit 07_86
bit 07_87
bit 07_88
bit 07_94
bit 07_95
bit 07_96
bit 07_100
bit 07_102
bit 07_103
@ -323,7 +327,6 @@ bit 07_111
bit 07_112
bit 07_115
bit 07_118
bit 07_119
bit 07_120
bit 07_126
bit 07_127
@ -352,6 +355,7 @@ bit 08_25
bit 08_26
bit 08_27
bit 08_28
bit 08_29
bit 08_30
bit 08_31
bit 08_32
@ -365,7 +369,6 @@ bit 08_43
bit 08_46
bit 08_47
bit 08_49
bit 08_53
bit 08_54
bit 08_55
bit 08_56
@ -377,7 +380,6 @@ bit 08_63
bit 08_64
bit 08_65
bit 08_66
bit 08_68
bit 08_69
bit 08_70
bit 08_71
@ -397,6 +399,7 @@ bit 08_87
bit 08_88
bit 08_89
bit 08_90
bit 08_91
bit 08_92
bit 08_93
bit 08_94
@ -421,6 +424,7 @@ bit 08_120
bit 08_121
bit 08_122
bit 08_123
bit 08_125
bit 08_126
bit 08_127
bit 09_00
@ -432,13 +436,13 @@ bit 09_05
bit 09_06
bit 09_07
bit 09_08
bit 09_10
bit 09_11
bit 09_13
bit 09_15
bit 09_16
bit 09_19
bit 09_20
bit 09_21
bit 09_22
bit 09_23
bit 09_24
@ -459,7 +463,6 @@ bit 09_53
bit 09_56
bit 09_57
bit 09_58
bit 09_59
bit 09_63
bit 09_64
bit 09_65
@ -470,10 +473,10 @@ bit 09_69
bit 09_75
bit 09_77
bit 09_79
bit 09_80
bit 09_82
bit 09_83
bit 09_84
bit 09_89
bit 09_91
bit 09_98
bit 09_99
@ -486,15 +489,17 @@ bit 09_114
bit 09_115
bit 09_116
bit 09_120
bit 09_121
bit 09_122
bit 09_123
bit 09_127
bit 10_00
bit 10_01
bit 10_02
bit 10_03
bit 10_05
bit 10_06
bit 10_07
bit 10_08
bit 10_09
bit 10_10
bit 10_11
@ -522,11 +527,11 @@ bit 10_42
bit 10_43
bit 10_46
bit 10_47
bit 10_49
bit 10_50
bit 10_52
bit 10_51
bit 10_53
bit 10_55
bit 10_56
bit 10_57
bit 10_58
bit 10_59
@ -548,12 +553,12 @@ bit 10_79
bit 10_80
bit 10_81
bit 10_82
bit 10_83
bit 10_85
bit 10_87
bit 10_88
bit 10_89
bit 10_90
bit 10_91
bit 10_92
bit 10_94
bit 10_95
@ -566,7 +571,6 @@ bit 10_107
bit 10_110
bit 10_111
bit 10_114
bit 10_115
bit 10_117
bit 10_119
bit 10_120
@ -587,6 +591,7 @@ bit 11_15
bit 11_17
bit 11_18
bit 11_19
bit 11_20
bit 11_21
bit 11_23
bit 11_24
@ -595,12 +600,14 @@ bit 11_26
bit 11_27
bit 11_31
bit 11_33
bit 11_36
bit 11_37
bit 11_39
bit 11_40
bit 11_41
bit 11_42
bit 11_43
bit 11_44
bit 11_47
bit 11_49
bit 11_50
@ -616,7 +623,6 @@ bit 11_63
bit 11_65
bit 11_66
bit 11_67
bit 11_68
bit 11_69
bit 11_71
bit 11_73
@ -626,16 +632,13 @@ bit 11_77
bit 11_79
bit 11_81
bit 11_82
bit 11_83
bit 11_87
bit 11_90
bit 11_91
bit 11_95
bit 11_97
bit 11_100
bit 11_101
bit 11_103
bit 11_104
bit 11_105
bit 11_106
bit 11_107
@ -644,11 +647,9 @@ bit 11_113
bit 11_116
bit 11_117
bit 11_119
bit 11_120
bit 11_121
bit 11_122
bit 11_123
bit 11_125
bit 11_127
bit 12_00
bit 12_01
@ -665,12 +666,13 @@ bit 12_14
bit 12_15
bit 12_16
bit 12_17
bit 12_20
bit 12_21
bit 12_23
bit 12_24
bit 12_25
bit 12_26
bit 12_27
bit 12_29
bit 12_30
bit 12_31
bit 12_33
@ -684,7 +686,8 @@ bit 12_46
bit 12_47
bit 12_48
bit 12_49
bit 12_52
bit 12_50
bit 12_51
bit 12_53
bit 12_55
bit 12_57
@ -704,13 +707,12 @@ bit 12_78
bit 12_79
bit 12_81
bit 12_82
bit 12_83
bit 12_85
bit 12_87
bit 12_88
bit 12_89
bit 12_90
bit 12_91
bit 12_93
bit 12_94
bit 12_95
bit 12_97
@ -725,7 +727,6 @@ bit 12_110
bit 12_111
bit 12_113
bit 12_114
bit 12_115
bit 12_117
bit 12_119
bit 12_120
@ -749,16 +750,17 @@ bit 13_12
bit 13_13
bit 13_14
bit 13_15
bit 13_16
bit 13_17
bit 13_18
bit 13_19
bit 13_20
bit 13_22
bit 13_23
bit 13_24
bit 13_25
bit 13_26
bit 13_28
bit 13_29
bit 13_30
bit 13_31
bit 13_33
bit 13_34
@ -781,10 +783,12 @@ bit 13_57
bit 13_58
bit 13_59
bit 13_60
bit 13_62
bit 13_63
bit 13_64
bit 13_65
bit 13_66
bit 13_67
bit 13_68
bit 13_69
bit 13_70
@ -797,9 +801,9 @@ bit 13_76
bit 13_77
bit 13_78
bit 13_79
bit 13_80
bit 13_81
bit 13_82
bit 13_83
bit 13_86
bit 13_87
bit 13_88
@ -811,7 +815,6 @@ bit 13_94
bit 13_95
bit 13_97
bit 13_98
bit 13_100
bit 13_101
bit 13_102
bit 13_103
@ -829,13 +832,16 @@ bit 13_120
bit 13_121
bit 13_122
bit 13_123
bit 13_126
bit 13_124
bit 13_125
bit 13_127
bit 14_00
bit 14_01
bit 14_02
bit 14_03
bit 14_04
bit 14_05
bit 14_07
bit 14_09
bit 14_10
bit 14_11
@ -847,19 +853,17 @@ bit 14_16
bit 14_18
bit 14_19
bit 14_20
bit 14_23
bit 14_25
bit 14_26
bit 14_28
bit 14_29
bit 14_30
bit 14_31
bit 14_34
bit 14_36
bit 14_42
bit 14_46
bit 14_50
bit 14_52
bit 14_56
bit 14_58
bit 14_64
bit 14_66
@ -869,6 +873,7 @@ bit 14_69
bit 14_71
bit 14_73
bit 14_74
bit 14_76
bit 14_77
bit 14_78
bit 14_79
@ -878,25 +883,27 @@ bit 14_84
bit 14_87
bit 14_88
bit 14_89
bit 14_90
bit 14_93
bit 14_94
bit 14_95
bit 14_98
bit 14_100
bit 14_106
bit 14_114
bit 14_116
bit 14_120
bit 14_122
bit 14_126
bit 15_00
bit 15_01
bit 15_02
bit 15_03
bit 15_04
bit 15_05
bit 15_06
bit 15_07
bit 15_08
bit 15_09
bit 15_10
bit 15_11
bit 15_12
bit 15_13
bit 15_14
@ -927,7 +934,6 @@ bit 15_63
bit 15_64
bit 15_65
bit 15_66
bit 15_68
bit 15_69
bit 15_71
bit 15_72
@ -941,7 +947,6 @@ bit 15_79
bit 15_80
bit 15_81
bit 15_82
bit 15_85
bit 15_87
bit 15_89
bit 15_90
@ -960,7 +965,6 @@ bit 15_113
bit 15_119
bit 15_121
bit 15_123
bit 15_125
bit 15_127
bit 16_02
bit 16_06
@ -973,6 +977,7 @@ bit 16_23
bit 16_24
bit 16_30
bit 16_31
bit 16_32
bit 16_35
bit 16_38
bit 16_40
@ -1002,7 +1007,6 @@ bit 16_94
bit 16_95
bit 16_99
bit 16_102
bit 16_103
bit 16_104
bit 16_106
bit 16_107
@ -1029,9 +1033,9 @@ bit 17_23
bit 17_24
bit 17_30
bit 17_31
bit 17_32
bit 17_35
bit 17_38
bit 17_39
bit 17_40
bit 17_42
bit 17_43
@ -1048,11 +1052,14 @@ bit 17_60
bit 17_62
bit 17_66
bit 17_70
bit 17_71
bit 17_73
bit 17_79
bit 17_80
bit 17_85
bit 17_86
bit 17_87
bit 17_88
bit 17_94
bit 17_95
bit 17_99
@ -1084,7 +1091,6 @@ bit 18_23
bit 18_25
bit 18_30
bit 18_31
bit 18_33
bit 18_34
bit 18_38
bit 18_39
@ -1116,6 +1122,7 @@ bit 18_97
bit 18_98
bit 18_102
bit 18_103
bit 18_105
bit 18_106
bit 18_107
bit 18_109
@ -1133,6 +1140,7 @@ bit 19_01
bit 19_03
bit 19_07
bit 19_08
bit 19_09
bit 19_14
bit 19_17
bit 19_20
@ -1152,6 +1160,7 @@ bit 19_46
bit 19_47
bit 19_49
bit 19_50
bit 19_54
bit 19_55
bit 19_56
bit 19_57
@ -1182,6 +1191,7 @@ bit 19_113
bit 19_114
bit 19_119
bit 19_120
bit 19_121
bit 19_123
bit 19_125
bit 19_127
@ -1256,6 +1266,7 @@ bit 21_85
bit 21_86
bit 21_94
bit 21_98
bit 21_99
bit 21_102
bit 21_106
bit 21_107
@ -1277,8 +1288,10 @@ bit 22_22
bit 22_23
bit 22_30
bit 22_31
bit 22_32
bit 22_35
bit 22_38
bit 22_40
bit 22_42
bit 22_43
bit 22_44
@ -1287,6 +1300,7 @@ bit 22_47
bit 22_48
bit 22_51
bit 22_54
bit 22_55
bit 22_56
bit 22_57
bit 22_58
@ -1294,21 +1308,22 @@ bit 22_60
bit 22_62
bit 22_66
bit 22_70
bit 22_71
bit 22_73
bit 22_79
bit 22_85
bit 22_86
bit 22_87
bit 22_94
bit 22_95
bit 22_96
bit 22_99
bit 22_102
bit 22_103
bit 22_106
bit 22_107
bit 22_108
bit 22_110
bit 22_111
bit 22_112
bit 22_115
bit 22_118
bit 22_121
@ -1330,7 +1345,6 @@ bit 23_31
bit 23_32
bit 23_35
bit 23_38
bit 23_39
bit 23_40
bit 23_42
bit 23_43
@ -1421,6 +1435,7 @@ bit 24_84
bit 24_85
bit 24_86
bit 24_87
bit 24_88
bit 24_94
bit 24_95
bit 24_96
@ -1446,6 +1461,7 @@ bit 25_00
bit 25_02
bit 25_06
bit 25_07
bit 25_08
bit 25_09
bit 25_15
bit 25_16
@ -1471,6 +1487,7 @@ bit 25_48
bit 25_51
bit 25_52
bit 25_54
bit 25_55
bit 25_56
bit 25_57
bit 25_58

36864
zynq7/segbits_bram_l.block_ram.origin_info.db Normal file
View File

File diff suppressed because it is too large Load Diff

452
zynq7/segbits_bram_l.origin_info.db Normal file
View File

@ -0,0 +1,452 @@
BRAM_L.BRAM_ADDRARDADDRL0.BRAM_CASCINBOT_ADDRARDADDRU0 origin:060-bram-cascades !26_33 26_32 26_35
BRAM_L.BRAM_ADDRARDADDRL0.BRAM_CASCINTOP_ADDRARDADDRU0 origin:060-bram-cascades !26_35 26_32 26_33
BRAM_L.BRAM_ADDRARDADDRL0.BRAM_IMUX_ADDRARDADDRL0 origin:060-bram-cascades !26_32 !26_33 !26_35
BRAM_L.BRAM_ADDRARDADDRL1.BRAM_CASCINBOT_ADDRARDADDRU1 origin:060-bram-cascades !26_49 26_48 26_51
BRAM_L.BRAM_ADDRARDADDRL1.BRAM_CASCINTOP_ADDRARDADDRU1 origin:060-bram-cascades !26_51 26_48 26_49
BRAM_L.BRAM_ADDRARDADDRL1.BRAM_IMUX_ADDRARDADDRL1 origin:060-bram-cascades !26_48 !26_49 !26_51
BRAM_L.BRAM_ADDRARDADDRL10.BRAM_CASCINBOT_ADDRARDADDRU10 origin:060-bram-cascades !26_145 26_144 26_147
BRAM_L.BRAM_ADDRARDADDRL10.BRAM_CASCINTOP_ADDRARDADDRU10 origin:060-bram-cascades !26_147 26_144 26_145
BRAM_L.BRAM_ADDRARDADDRL10.BRAM_IMUX_ADDRARDADDRL10 origin:060-bram-cascades !26_144 !26_145 !26_147
BRAM_L.BRAM_ADDRARDADDRL11.BRAM_CASCINBOT_ADDRARDADDRU11 origin:060-bram-cascades !26_113 26_112 26_115
BRAM_L.BRAM_ADDRARDADDRL11.BRAM_CASCINTOP_ADDRARDADDRU11 origin:060-bram-cascades !26_115 26_112 26_113
BRAM_L.BRAM_ADDRARDADDRL11.BRAM_IMUX_ADDRARDADDRL11 origin:060-bram-cascades !26_112 !26_113 !26_115
BRAM_L.BRAM_ADDRARDADDRL12.BRAM_CASCINBOT_ADDRARDADDRU12 origin:060-bram-cascades !26_241 26_240 26_243
BRAM_L.BRAM_ADDRARDADDRL12.BRAM_CASCINTOP_ADDRARDADDRU12 origin:060-bram-cascades !26_243 26_240 26_241
BRAM_L.BRAM_ADDRARDADDRL12.BRAM_IMUX_ADDRARDADDRL12 origin:060-bram-cascades !26_240 !26_241 !26_243
BRAM_L.BRAM_ADDRARDADDRL13.BRAM_CASCINBOT_ADDRARDADDRU13 origin:060-bram-cascades !26_129 26_128 26_131
BRAM_L.BRAM_ADDRARDADDRL13.BRAM_CASCINTOP_ADDRARDADDRU13 origin:060-bram-cascades !26_131 26_128 26_129
BRAM_L.BRAM_ADDRARDADDRL13.BRAM_IMUX_ADDRARDADDRL13 origin:060-bram-cascades !26_128 !26_129 !26_131
BRAM_L.BRAM_ADDRARDADDRL14.BRAM_CASCINBOT_ADDRARDADDRU14 origin:060-bram-cascades !26_257 26_256 26_259
BRAM_L.BRAM_ADDRARDADDRL14.BRAM_CASCINTOP_ADDRARDADDRU14 origin:060-bram-cascades !26_259 26_256 26_257
BRAM_L.BRAM_ADDRARDADDRL14.BRAM_IMUX_ADDRARDADDRL14 origin:060-bram-cascades !26_256 !26_257 !26_259
BRAM_L.BRAM_ADDRARDADDRL2.BRAM_CASCINBOT_ADDRARDADDRU2 origin:060-bram-cascades !26_65 26_64 26_67
BRAM_L.BRAM_ADDRARDADDRL2.BRAM_CASCINTOP_ADDRARDADDRU2 origin:060-bram-cascades !26_67 26_64 26_65
BRAM_L.BRAM_ADDRARDADDRL2.BRAM_IMUX_ADDRARDADDRL2 origin:060-bram-cascades !26_64 !26_65 !26_67
BRAM_L.BRAM_ADDRARDADDRL3.BRAM_CASCINBOT_ADDRARDADDRU3 origin:060-bram-cascades !26_193 26_192 26_195
BRAM_L.BRAM_ADDRARDADDRL3.BRAM_CASCINTOP_ADDRARDADDRU3 origin:060-bram-cascades !26_195 26_192 26_193
BRAM_L.BRAM_ADDRARDADDRL3.BRAM_IMUX_ADDRARDADDRL3 origin:060-bram-cascades !26_192 !26_193 !26_195
BRAM_L.BRAM_ADDRARDADDRL4.BRAM_CASCINBOT_ADDRARDADDRU4 origin:060-bram-cascades !26_97 26_96 26_99
BRAM_L.BRAM_ADDRARDADDRL4.BRAM_CASCINTOP_ADDRARDADDRU4 origin:060-bram-cascades !26_99 26_96 26_97
BRAM_L.BRAM_ADDRARDADDRL4.BRAM_IMUX_ADDRARDADDRL4 origin:060-bram-cascades !26_96 !26_97 !26_99
BRAM_L.BRAM_ADDRARDADDRL5.BRAM_CASCINBOT_ADDRARDADDRU5 origin:060-bram-cascades !26_225 26_224 26_227
BRAM_L.BRAM_ADDRARDADDRL5.BRAM_CASCINTOP_ADDRARDADDRU5 origin:060-bram-cascades !26_227 26_224 26_225
BRAM_L.BRAM_ADDRARDADDRL5.BRAM_IMUX_ADDRARDADDRL5 origin:060-bram-cascades !26_224 !26_225 !26_227
BRAM_L.BRAM_ADDRARDADDRL6.BRAM_CASCINBOT_ADDRARDADDRU6 origin:060-bram-cascades !26_161 26_160 26_163
BRAM_L.BRAM_ADDRARDADDRL6.BRAM_CASCINTOP_ADDRARDADDRU6 origin:060-bram-cascades !26_163 26_160 26_161
BRAM_L.BRAM_ADDRARDADDRL6.BRAM_IMUX_ADDRARDADDRL6 origin:060-bram-cascades !26_160 !26_161 !26_163
BRAM_L.BRAM_ADDRARDADDRL7.BRAM_CASCINBOT_ADDRARDADDRU7 origin:060-bram-cascades !26_177 26_176 26_179
BRAM_L.BRAM_ADDRARDADDRL7.BRAM_CASCINTOP_ADDRARDADDRU7 origin:060-bram-cascades !26_179 26_176 26_177
BRAM_L.BRAM_ADDRARDADDRL7.BRAM_IMUX_ADDRARDADDRL7 origin:060-bram-cascades !26_176 !26_177 !26_179
BRAM_L.BRAM_ADDRARDADDRL8.BRAM_CASCINBOT_ADDRARDADDRU8 origin:060-bram-cascades !26_81 26_80 26_83
BRAM_L.BRAM_ADDRARDADDRL8.BRAM_CASCINTOP_ADDRARDADDRU8 origin:060-bram-cascades !26_83 26_80 26_81
BRAM_L.BRAM_ADDRARDADDRL8.BRAM_IMUX_ADDRARDADDRL8 origin:060-bram-cascades !26_80 !26_81 !26_83
BRAM_L.BRAM_ADDRARDADDRL9.BRAM_CASCINBOT_ADDRARDADDRU9 origin:060-bram-cascades !26_209 26_208 26_211
BRAM_L.BRAM_ADDRARDADDRL9.BRAM_CASCINTOP_ADDRARDADDRU9 origin:060-bram-cascades !26_211 26_208 26_209
BRAM_L.BRAM_ADDRARDADDRL9.BRAM_IMUX_ADDRARDADDRL9 origin:060-bram-cascades !26_208 !26_209 !26_211
BRAM_L.BRAM_ADDRARDADDRU0.BRAM_CASCINBOT_ADDRARDADDRU0 origin:060-bram-cascades !26_38 26_37 26_39
BRAM_L.BRAM_ADDRARDADDRU0.BRAM_CASCINTOP_ADDRARDADDRU0 origin:060-bram-cascades !26_37 26_38 26_39
BRAM_L.BRAM_ADDRARDADDRU0.BRAM_IMUX_ADDRARDADDRU0 origin:060-bram-cascades !26_37 !26_38 !26_39
BRAM_L.BRAM_ADDRARDADDRU1.BRAM_CASCINBOT_ADDRARDADDRU1 origin:060-bram-cascades !26_54 26_53 26_55
BRAM_L.BRAM_ADDRARDADDRU1.BRAM_CASCINTOP_ADDRARDADDRU1 origin:060-bram-cascades !26_53 26_54 26_55
BRAM_L.BRAM_ADDRARDADDRU1.BRAM_IMUX_ADDRARDADDRU1 origin:060-bram-cascades !26_53 !26_54 !26_55
BRAM_L.BRAM_ADDRARDADDRU10.BRAM_CASCINBOT_ADDRARDADDRU10 origin:060-bram-cascades !26_150 26_149 26_151
BRAM_L.BRAM_ADDRARDADDRU10.BRAM_CASCINTOP_ADDRARDADDRU10 origin:060-bram-cascades !26_149 26_150 26_151
BRAM_L.BRAM_ADDRARDADDRU10.BRAM_IMUX_ADDRARDADDRU10 origin:060-bram-cascades !26_149 !26_150 !26_151
BRAM_L.BRAM_ADDRARDADDRU11.BRAM_CASCINBOT_ADDRARDADDRU11 origin:060-bram-cascades !26_118 26_117 26_119
BRAM_L.BRAM_ADDRARDADDRU11.BRAM_CASCINTOP_ADDRARDADDRU11 origin:060-bram-cascades !26_117 26_118 26_119
BRAM_L.BRAM_ADDRARDADDRU11.BRAM_IMUX_ADDRARDADDRU11 origin:060-bram-cascades !26_117 !26_118 !26_119
BRAM_L.BRAM_ADDRARDADDRU12.BRAM_CASCINBOT_ADDRARDADDRU12 origin:060-bram-cascades !26_246 26_245 26_247
BRAM_L.BRAM_ADDRARDADDRU12.BRAM_CASCINTOP_ADDRARDADDRU12 origin:060-bram-cascades !26_245 26_246 26_247
BRAM_L.BRAM_ADDRARDADDRU12.BRAM_IMUX_ADDRARDADDRU12 origin:060-bram-cascades !26_245 !26_246 !26_247
BRAM_L.BRAM_ADDRARDADDRU13.BRAM_CASCINBOT_ADDRARDADDRU13 origin:060-bram-cascades !26_134 26_133 26_135
BRAM_L.BRAM_ADDRARDADDRU13.BRAM_CASCINTOP_ADDRARDADDRU13 origin:060-bram-cascades !26_133 26_134 26_135
BRAM_L.BRAM_ADDRARDADDRU13.BRAM_IMUX_ADDRARDADDRU13 origin:060-bram-cascades !26_133 !26_134 !26_135
BRAM_L.BRAM_ADDRARDADDRU14.BRAM_CASCINBOT_ADDRARDADDRU14 origin:060-bram-cascades !26_262 26_261 26_263
BRAM_L.BRAM_ADDRARDADDRU14.BRAM_CASCINTOP_ADDRARDADDRU14 origin:060-bram-cascades !26_261 26_262 26_263
BRAM_L.BRAM_ADDRARDADDRU14.BRAM_IMUX_ADDRARDADDRU14 origin:060-bram-cascades !26_261 !26_262 !26_263
BRAM_L.BRAM_ADDRARDADDRU2.BRAM_CASCINBOT_ADDRARDADDRU2 origin:060-bram-cascades !26_70 26_69 26_71
BRAM_L.BRAM_ADDRARDADDRU2.BRAM_CASCINTOP_ADDRARDADDRU2 origin:060-bram-cascades !26_69 26_70 26_71
BRAM_L.BRAM_ADDRARDADDRU2.BRAM_IMUX_ADDRARDADDRU2 origin:060-bram-cascades !26_69 !26_70 !26_71
BRAM_L.BRAM_ADDRARDADDRU3.BRAM_CASCINBOT_ADDRARDADDRU3 origin:060-bram-cascades !26_198 26_197 26_199
BRAM_L.BRAM_ADDRARDADDRU3.BRAM_CASCINTOP_ADDRARDADDRU3 origin:060-bram-cascades !26_197 26_198 26_199
BRAM_L.BRAM_ADDRARDADDRU3.BRAM_IMUX_ADDRARDADDRU3 origin:060-bram-cascades !26_197 !26_198 !26_199
BRAM_L.BRAM_ADDRARDADDRU4.BRAM_CASCINBOT_ADDRARDADDRU4 origin:060-bram-cascades !26_102 26_101 26_103
BRAM_L.BRAM_ADDRARDADDRU4.BRAM_CASCINTOP_ADDRARDADDRU4 origin:060-bram-cascades !26_101 26_102 26_103
BRAM_L.BRAM_ADDRARDADDRU4.BRAM_IMUX_ADDRARDADDRU4 origin:060-bram-cascades !26_101 !26_102 !26_103
BRAM_L.BRAM_ADDRARDADDRU5.BRAM_CASCINBOT_ADDRARDADDRU5 origin:060-bram-cascades !26_230 26_229 26_231
BRAM_L.BRAM_ADDRARDADDRU5.BRAM_CASCINTOP_ADDRARDADDRU5 origin:060-bram-cascades !26_229 26_230 26_231
BRAM_L.BRAM_ADDRARDADDRU5.BRAM_IMUX_ADDRARDADDRU5 origin:060-bram-cascades !26_229 !26_230 !26_231
BRAM_L.BRAM_ADDRARDADDRU6.BRAM_CASCINBOT_ADDRARDADDRU6 origin:060-bram-cascades !26_166 26_165 26_167
BRAM_L.BRAM_ADDRARDADDRU6.BRAM_CASCINTOP_ADDRARDADDRU6 origin:060-bram-cascades !26_165 26_166 26_167
BRAM_L.BRAM_ADDRARDADDRU6.BRAM_IMUX_ADDRARDADDRU6 origin:060-bram-cascades !26_165 !26_166 !26_167
BRAM_L.BRAM_ADDRARDADDRU7.BRAM_CASCINBOT_ADDRARDADDRU7 origin:060-bram-cascades !26_182 26_181 26_183
BRAM_L.BRAM_ADDRARDADDRU7.BRAM_CASCINTOP_ADDRARDADDRU7 origin:060-bram-cascades !26_181 26_182 26_183
BRAM_L.BRAM_ADDRARDADDRU7.BRAM_IMUX_ADDRARDADDRU7 origin:060-bram-cascades !26_181 !26_182 !26_183
BRAM_L.BRAM_ADDRARDADDRU8.BRAM_CASCINBOT_ADDRARDADDRU8 origin:060-bram-cascades !26_86 26_85 26_87
BRAM_L.BRAM_ADDRARDADDRU8.BRAM_CASCINTOP_ADDRARDADDRU8 origin:060-bram-cascades !26_85 26_86 26_87
BRAM_L.BRAM_ADDRARDADDRU8.BRAM_IMUX_ADDRARDADDRU8 origin:060-bram-cascades !26_85 !26_86 !26_87
BRAM_L.BRAM_ADDRARDADDRU9.BRAM_CASCINBOT_ADDRARDADDRU9 origin:060-bram-cascades !26_214 26_213 26_215
BRAM_L.BRAM_ADDRARDADDRU9.BRAM_CASCINTOP_ADDRARDADDRU9 origin:060-bram-cascades !26_213 26_214 26_215
BRAM_L.BRAM_ADDRARDADDRU9.BRAM_IMUX_ADDRARDADDRU9 origin:060-bram-cascades !26_213 !26_214 !26_215
BRAM_L.BRAM_ADDRBWRADDRL0.BRAM_CASCINBOT_ADDRBWRADDRU0 origin:060-bram-cascades !26_41 26_40 26_43
BRAM_L.BRAM_ADDRBWRADDRL0.BRAM_CASCINTOP_ADDRBWRADDRU0 origin:060-bram-cascades !26_43 26_40 26_41
BRAM_L.BRAM_ADDRBWRADDRL0.BRAM_IMUX_ADDRBWRADDRL0 origin:060-bram-cascades !26_40 !26_41 !26_43
BRAM_L.BRAM_ADDRBWRADDRL1.BRAM_CASCINBOT_ADDRBWRADDRU1 origin:060-bram-cascades !26_57 26_56 26_59
BRAM_L.BRAM_ADDRBWRADDRL1.BRAM_CASCINTOP_ADDRBWRADDRU1 origin:060-bram-cascades !26_59 26_56 26_57
BRAM_L.BRAM_ADDRBWRADDRL1.BRAM_IMUX_ADDRBWRADDRL1 origin:060-bram-cascades !26_56 !26_57 !26_59
BRAM_L.BRAM_ADDRBWRADDRL10.BRAM_CASCINBOT_ADDRBWRADDRU10 origin:060-bram-cascades !26_153 26_152 26_155
BRAM_L.BRAM_ADDRBWRADDRL10.BRAM_CASCINTOP_ADDRBWRADDRU10 origin:060-bram-cascades !26_155 26_152 26_153
BRAM_L.BRAM_ADDRBWRADDRL10.BRAM_IMUX_ADDRBWRADDRL10 origin:060-bram-cascades !26_152 !26_153 !26_155
BRAM_L.BRAM_ADDRBWRADDRL11.BRAM_CASCINBOT_ADDRBWRADDRU11 origin:060-bram-cascades !26_121 26_120 26_123
BRAM_L.BRAM_ADDRBWRADDRL11.BRAM_CASCINTOP_ADDRBWRADDRU11 origin:060-bram-cascades !26_123 26_120 26_121
BRAM_L.BRAM_ADDRBWRADDRL11.BRAM_IMUX_ADDRBWRADDRL11 origin:060-bram-cascades !26_120 !26_121 !26_123
BRAM_L.BRAM_ADDRBWRADDRL12.BRAM_CASCINBOT_ADDRBWRADDRU12 origin:060-bram-cascades !26_249 26_248 26_251
BRAM_L.BRAM_ADDRBWRADDRL12.BRAM_CASCINTOP_ADDRBWRADDRU12 origin:060-bram-cascades !26_251 26_248 26_249
BRAM_L.BRAM_ADDRBWRADDRL12.BRAM_IMUX_ADDRBWRADDRL12 origin:060-bram-cascades !26_248 !26_249 !26_251
BRAM_L.BRAM_ADDRBWRADDRL13.BRAM_CASCINBOT_ADDRBWRADDRU13 origin:060-bram-cascades !26_137 26_136 26_139
BRAM_L.BRAM_ADDRBWRADDRL13.BRAM_CASCINTOP_ADDRBWRADDRU13 origin:060-bram-cascades !26_139 26_136 26_137
BRAM_L.BRAM_ADDRBWRADDRL13.BRAM_IMUX_ADDRBWRADDRL13 origin:060-bram-cascades !26_136 !26_137 !26_139
BRAM_L.BRAM_ADDRBWRADDRL14.BRAM_CASCINBOT_ADDRBWRADDRU14 origin:060-bram-cascades !26_265 26_264 26_267
BRAM_L.BRAM_ADDRBWRADDRL14.BRAM_CASCINTOP_ADDRBWRADDRU14 origin:060-bram-cascades !26_267 26_264 26_265
BRAM_L.BRAM_ADDRBWRADDRL14.BRAM_IMUX_ADDRBWRADDRL14 origin:060-bram-cascades !26_264 !26_265 !26_267
BRAM_L.BRAM_ADDRBWRADDRL2.BRAM_CASCINBOT_ADDRBWRADDRU2 origin:060-bram-cascades !26_73 26_72 26_75
BRAM_L.BRAM_ADDRBWRADDRL2.BRAM_CASCINTOP_ADDRBWRADDRU2 origin:060-bram-cascades !26_75 26_72 26_73
BRAM_L.BRAM_ADDRBWRADDRL2.BRAM_IMUX_ADDRBWRADDRL2 origin:060-bram-cascades !26_72 !26_73 !26_75
BRAM_L.BRAM_ADDRBWRADDRL3.BRAM_CASCINBOT_ADDRBWRADDRU3 origin:060-bram-cascades !26_201 26_200 26_203
BRAM_L.BRAM_ADDRBWRADDRL3.BRAM_CASCINTOP_ADDRBWRADDRU3 origin:060-bram-cascades !26_203 26_200 26_201
BRAM_L.BRAM_ADDRBWRADDRL3.BRAM_IMUX_ADDRBWRADDRL3 origin:060-bram-cascades !26_200 !26_201 !26_203
BRAM_L.BRAM_ADDRBWRADDRL4.BRAM_CASCINBOT_ADDRBWRADDRU4 origin:060-bram-cascades !26_105 26_104 26_107
BRAM_L.BRAM_ADDRBWRADDRL4.BRAM_CASCINTOP_ADDRBWRADDRU4 origin:060-bram-cascades !26_107 26_104 26_105
BRAM_L.BRAM_ADDRBWRADDRL4.BRAM_IMUX_ADDRBWRADDRL4 origin:060-bram-cascades !26_104 !26_105 !26_107
BRAM_L.BRAM_ADDRBWRADDRL5.BRAM_CASCINBOT_ADDRBWRADDRU5 origin:060-bram-cascades !26_233 26_232 26_235
BRAM_L.BRAM_ADDRBWRADDRL5.BRAM_CASCINTOP_ADDRBWRADDRU5 origin:060-bram-cascades !26_235 26_232 26_233
BRAM_L.BRAM_ADDRBWRADDRL5.BRAM_IMUX_ADDRBWRADDRL5 origin:060-bram-cascades !26_232 !26_233 !26_235
BRAM_L.BRAM_ADDRBWRADDRL6.BRAM_CASCINBOT_ADDRBWRADDRU6 origin:060-bram-cascades !26_169 26_168 26_171
BRAM_L.BRAM_ADDRBWRADDRL6.BRAM_CASCINTOP_ADDRBWRADDRU6 origin:060-bram-cascades !26_171 26_168 26_169
BRAM_L.BRAM_ADDRBWRADDRL6.BRAM_IMUX_ADDRBWRADDRL6 origin:060-bram-cascades !26_168 !26_169 !26_171
BRAM_L.BRAM_ADDRBWRADDRL7.BRAM_CASCINBOT_ADDRBWRADDRU7 origin:060-bram-cascades !26_185 26_184 26_187
BRAM_L.BRAM_ADDRBWRADDRL7.BRAM_CASCINTOP_ADDRBWRADDRU7 origin:060-bram-cascades !26_187 26_184 26_185
BRAM_L.BRAM_ADDRBWRADDRL7.BRAM_IMUX_ADDRBWRADDRL7 origin:060-bram-cascades !26_184 !26_185 !26_187
BRAM_L.BRAM_ADDRBWRADDRL8.BRAM_CASCINBOT_ADDRBWRADDRU8 origin:060-bram-cascades !26_89 26_88 26_91
BRAM_L.BRAM_ADDRBWRADDRL8.BRAM_CASCINTOP_ADDRBWRADDRU8 origin:060-bram-cascades !26_91 26_88 26_89
BRAM_L.BRAM_ADDRBWRADDRL8.BRAM_IMUX_ADDRBWRADDRL8 origin:060-bram-cascades !26_88 !26_89 !26_91
BRAM_L.BRAM_ADDRBWRADDRL9.BRAM_CASCINBOT_ADDRBWRADDRU9 origin:060-bram-cascades !26_217 26_216 26_219
BRAM_L.BRAM_ADDRBWRADDRL9.BRAM_CASCINTOP_ADDRBWRADDRU9 origin:060-bram-cascades !26_219 26_216 26_217
BRAM_L.BRAM_ADDRBWRADDRL9.BRAM_IMUX_ADDRBWRADDRL9 origin:060-bram-cascades !26_216 !26_217 !26_219
BRAM_L.BRAM_ADDRBWRADDRU0.BRAM_CASCINBOT_ADDRBWRADDRU0 origin:060-bram-cascades !26_46 26_45 26_47
BRAM_L.BRAM_ADDRBWRADDRU0.BRAM_CASCINTOP_ADDRBWRADDRU0 origin:060-bram-cascades !26_45 26_46 26_47
BRAM_L.BRAM_ADDRBWRADDRU0.BRAM_IMUX_ADDRBWRADDRU0 origin:060-bram-cascades !26_45 !26_46 !26_47
BRAM_L.BRAM_ADDRBWRADDRU1.BRAM_CASCINBOT_ADDRBWRADDRU1 origin:060-bram-cascades !26_62 26_61 26_63
BRAM_L.BRAM_ADDRBWRADDRU1.BRAM_CASCINTOP_ADDRBWRADDRU1 origin:060-bram-cascades !26_61 26_62 26_63
BRAM_L.BRAM_ADDRBWRADDRU1.BRAM_IMUX_ADDRBWRADDRU1 origin:060-bram-cascades !26_61 !26_62 !26_63
BRAM_L.BRAM_ADDRBWRADDRU10.BRAM_CASCINBOT_ADDRBWRADDRU10 origin:060-bram-cascades !26_158 26_157 26_159
BRAM_L.BRAM_ADDRBWRADDRU10.BRAM_CASCINTOP_ADDRBWRADDRU10 origin:060-bram-cascades !26_157 26_158 26_159
BRAM_L.BRAM_ADDRBWRADDRU10.BRAM_IMUX_ADDRBWRADDRU10 origin:060-bram-cascades !26_157 !26_158 !26_159
BRAM_L.BRAM_ADDRBWRADDRU11.BRAM_CASCINBOT_ADDRBWRADDRU11 origin:060-bram-cascades !26_126 26_125 26_127
BRAM_L.BRAM_ADDRBWRADDRU11.BRAM_CASCINTOP_ADDRBWRADDRU11 origin:060-bram-cascades !26_125 26_126 26_127
BRAM_L.BRAM_ADDRBWRADDRU11.BRAM_IMUX_ADDRBWRADDRU11 origin:060-bram-cascades !26_125 !26_126 !26_127
BRAM_L.BRAM_ADDRBWRADDRU12.BRAM_CASCINBOT_ADDRBWRADDRU12 origin:060-bram-cascades !26_254 26_253 26_255
BRAM_L.BRAM_ADDRBWRADDRU12.BRAM_CASCINTOP_ADDRBWRADDRU12 origin:060-bram-cascades !26_253 26_254 26_255
BRAM_L.BRAM_ADDRBWRADDRU12.BRAM_IMUX_ADDRBWRADDRU12 origin:060-bram-cascades !26_253 !26_254 !26_255
BRAM_L.BRAM_ADDRBWRADDRU13.BRAM_CASCINBOT_ADDRBWRADDRU13 origin:060-bram-cascades !26_142 26_141 26_143
BRAM_L.BRAM_ADDRBWRADDRU13.BRAM_CASCINTOP_ADDRBWRADDRU13 origin:060-bram-cascades !26_141 26_142 26_143
BRAM_L.BRAM_ADDRBWRADDRU13.BRAM_IMUX_ADDRBWRADDRU13 origin:060-bram-cascades !26_141 !26_142 !26_143
BRAM_L.BRAM_ADDRBWRADDRU14.BRAM_CASCINBOT_ADDRBWRADDRU14 origin:060-bram-cascades !26_270 26_269 26_271
BRAM_L.BRAM_ADDRBWRADDRU14.BRAM_CASCINTOP_ADDRBWRADDRU14 origin:060-bram-cascades !26_269 26_270 26_271
BRAM_L.BRAM_ADDRBWRADDRU14.BRAM_IMUX_ADDRBWRADDRU14 origin:060-bram-cascades !26_269 !26_270 !26_271
BRAM_L.BRAM_ADDRBWRADDRU2.BRAM_CASCINBOT_ADDRBWRADDRU2 origin:060-bram-cascades !26_78 26_77 26_79
BRAM_L.BRAM_ADDRBWRADDRU2.BRAM_CASCINTOP_ADDRBWRADDRU2 origin:060-bram-cascades !26_77 26_78 26_79
BRAM_L.BRAM_ADDRBWRADDRU2.BRAM_IMUX_ADDRBWRADDRU2 origin:060-bram-cascades !26_77 !26_78 !26_79
BRAM_L.BRAM_ADDRBWRADDRU3.BRAM_CASCINBOT_ADDRBWRADDRU3 origin:060-bram-cascades !26_206 26_205 26_207
BRAM_L.BRAM_ADDRBWRADDRU3.BRAM_CASCINTOP_ADDRBWRADDRU3 origin:060-bram-cascades !26_205 26_206 26_207
BRAM_L.BRAM_ADDRBWRADDRU3.BRAM_IMUX_ADDRBWRADDRU3 origin:060-bram-cascades !26_205 !26_206 !26_207
BRAM_L.BRAM_ADDRBWRADDRU4.BRAM_CASCINBOT_ADDRBWRADDRU4 origin:060-bram-cascades !26_110 26_109 26_111
BRAM_L.BRAM_ADDRBWRADDRU4.BRAM_CASCINTOP_ADDRBWRADDRU4 origin:060-bram-cascades !26_109 26_110 26_111
BRAM_L.BRAM_ADDRBWRADDRU4.BRAM_IMUX_ADDRBWRADDRU4 origin:060-bram-cascades !26_109 !26_110 !26_111
BRAM_L.BRAM_ADDRBWRADDRU5.BRAM_CASCINBOT_ADDRBWRADDRU5 origin:060-bram-cascades !26_238 26_237 26_239
BRAM_L.BRAM_ADDRBWRADDRU5.BRAM_CASCINTOP_ADDRBWRADDRU5 origin:060-bram-cascades !26_237 26_238 26_239
BRAM_L.BRAM_ADDRBWRADDRU5.BRAM_IMUX_ADDRBWRADDRU5 origin:060-bram-cascades !26_237 !26_238 !26_239
BRAM_L.BRAM_ADDRBWRADDRU6.BRAM_CASCINBOT_ADDRBWRADDRU6 origin:060-bram-cascades !26_174 26_173 26_175
BRAM_L.BRAM_ADDRBWRADDRU6.BRAM_CASCINTOP_ADDRBWRADDRU6 origin:060-bram-cascades !26_173 26_174 26_175
BRAM_L.BRAM_ADDRBWRADDRU6.BRAM_IMUX_ADDRBWRADDRU6 origin:060-bram-cascades !26_173 !26_174 !26_175
BRAM_L.BRAM_ADDRBWRADDRU7.BRAM_CASCINBOT_ADDRBWRADDRU7 origin:060-bram-cascades !26_190 26_189 26_191
BRAM_L.BRAM_ADDRBWRADDRU7.BRAM_CASCINTOP_ADDRBWRADDRU7 origin:060-bram-cascades !26_189 26_190 26_191
BRAM_L.BRAM_ADDRBWRADDRU7.BRAM_IMUX_ADDRBWRADDRU7 origin:060-bram-cascades !26_189 !26_190 !26_191
BRAM_L.BRAM_ADDRBWRADDRU8.BRAM_CASCINBOT_ADDRBWRADDRU8 origin:060-bram-cascades !26_94 26_93 26_95
BRAM_L.BRAM_ADDRBWRADDRU8.BRAM_CASCINTOP_ADDRBWRADDRU8 origin:060-bram-cascades !26_93 26_94 26_95
BRAM_L.BRAM_ADDRBWRADDRU8.BRAM_IMUX_ADDRBWRADDRU8 origin:060-bram-cascades !26_93 !26_94 !26_95
BRAM_L.BRAM_ADDRBWRADDRU9.BRAM_CASCINBOT_ADDRBWRADDRU9 origin:060-bram-cascades !26_222 26_221 26_223
BRAM_L.BRAM_ADDRBWRADDRU9.BRAM_CASCINTOP_ADDRBWRADDRU9 origin:060-bram-cascades !26_221 26_222 26_223
BRAM_L.BRAM_ADDRBWRADDRU9.BRAM_IMUX_ADDRBWRADDRU9 origin:060-bram-cascades !26_221 !26_222 !26_223
BRAM_L.CASCOUT_ARD_ACTIVE origin:060-bram-cascades 26_170
BRAM_L.CASCOUT_BWR_ACTIVE origin:060-bram-cascades 26_172
BRAM_L.EN_SYN origin:028-fifo-config 27_171
BRAM_L.FIRST_WORD_FALL_THROUGH origin:028-fifo-config 27_170
BRAM_L.RAMB18_Y0.DOA_REG origin:025-bram-config 27_69
BRAM_L.RAMB18_Y0.DOB_REG origin:025-bram-config 27_72
BRAM_L.RAMB18_Y0.FIFO_MODE origin:029-bram-fifo-config 27_150
BRAM_L.RAMB18_Y0.IN_USE origin:029-bram-fifo-config 27_100 27_99
BRAM_L.RAMB18_Y0.RDADDR_COLLISION_HWCONFIG_DELAYED_WRITE origin:025-bram-config !27_96
BRAM_L.RAMB18_Y0.RDADDR_COLLISION_HWCONFIG_PERFORMANCE origin:025-bram-config 27_96
BRAM_L.RAMB18_Y0.READ_WIDTH_A_1 origin:025-bram-config !27_35 !27_36 !27_37
BRAM_L.RAMB18_Y0.READ_WIDTH_A_18 origin:025-bram-config !27_35 !27_36 27_37
BRAM_L.RAMB18_Y0.READ_WIDTH_A_2 origin:025-bram-config !27_36 !27_37 27_35
BRAM_L.RAMB18_Y0.READ_WIDTH_A_4 origin:025-bram-config !27_35 !27_37 27_36
BRAM_L.RAMB18_Y0.READ_WIDTH_A_9 origin:025-bram-config !27_37 27_35 27_36
BRAM_L.RAMB18_Y0.READ_WIDTH_B_1 origin:025-bram-config !27_43 !27_44 !27_45
BRAM_L.RAMB18_Y0.READ_WIDTH_B_18 origin:025-bram-config !27_43 !27_44 27_45
BRAM_L.RAMB18_Y0.READ_WIDTH_B_2 origin:025-bram-config !27_44 !27_45 27_43
BRAM_L.RAMB18_Y0.READ_WIDTH_B_4 origin:025-bram-config !27_43 !27_45 27_44
BRAM_L.RAMB18_Y0.READ_WIDTH_B_9 origin:025-bram-config !27_45 27_43 27_44
BRAM_L.RAMB18_Y0.RSTREG_PRIORITY_A_REGCE origin:025-bram-config 27_124
BRAM_L.RAMB18_Y0.RSTREG_PRIORITY_A_RSTREG origin:025-bram-config !27_124
BRAM_L.RAMB18_Y0.RSTREG_PRIORITY_B_REGCE origin:025-bram-config 27_125
BRAM_L.RAMB18_Y0.RSTREG_PRIORITY_B_RSTREG origin:025-bram-config !27_125
BRAM_L.RAMB18_Y0.SDP_READ_WIDTH_36 origin:025-bram-config 27_48
BRAM_L.RAMB18_Y0.SDP_WRITE_WIDTH_36 origin:025-bram-config 27_40
BRAM_L.RAMB18_Y0.WRITE_MODE_A_NO_CHANGE origin:025-bram-config 27_64
BRAM_L.RAMB18_Y0.WRITE_MODE_A_READ_FIRST origin:025-bram-config 27_56
BRAM_L.RAMB18_Y0.WRITE_MODE_B_NO_CHANGE origin:025-bram-config 27_68
BRAM_L.RAMB18_Y0.WRITE_MODE_B_READ_FIRST origin:025-bram-config 27_67
BRAM_L.RAMB18_Y0.WRITE_WIDTH_A_1 origin:025-bram-config !27_51 !27_52 !27_53
BRAM_L.RAMB18_Y0.WRITE_WIDTH_A_18 origin:025-bram-config !27_51 !27_52 27_53
BRAM_L.RAMB18_Y0.WRITE_WIDTH_A_2 origin:025-bram-config !27_52 !27_53 27_51
BRAM_L.RAMB18_Y0.WRITE_WIDTH_A_4 origin:025-bram-config !27_51 !27_53 27_52
BRAM_L.RAMB18_Y0.WRITE_WIDTH_A_9 origin:025-bram-config !27_53 27_51 27_52
BRAM_L.RAMB18_Y0.WRITE_WIDTH_B_1 origin:025-bram-config !27_59 !27_60 !27_61
BRAM_L.RAMB18_Y0.WRITE_WIDTH_B_18 origin:025-bram-config !27_59 !27_60 27_61
BRAM_L.RAMB18_Y0.WRITE_WIDTH_B_2 origin:025-bram-config !27_60 !27_61 27_59
BRAM_L.RAMB18_Y0.WRITE_WIDTH_B_4 origin:025-bram-config !27_59 !27_61 27_60
BRAM_L.RAMB18_Y0.WRITE_WIDTH_B_9 origin:025-bram-config !27_61 27_59 27_60
BRAM_L.RAMB18_Y0.ZINIT_A[0] origin:025-bram-config 27_73
BRAM_L.RAMB18_Y0.ZINIT_A[10] origin:025-bram-config 27_129
BRAM_L.RAMB18_Y0.ZINIT_A[11] origin:025-bram-config 27_113
BRAM_L.RAMB18_Y0.ZINIT_A[12] origin:025-bram-config 27_97
BRAM_L.RAMB18_Y0.ZINIT_A[13] origin:025-bram-config 27_81
BRAM_L.RAMB18_Y0.ZINIT_A[14] origin:025-bram-config 27_49
BRAM_L.RAMB18_Y0.ZINIT_A[15] origin:025-bram-config 27_33
BRAM_L.RAMB18_Y0.ZINIT_A[16] origin:025-bram-config 27_17
BRAM_L.RAMB18_Y0.ZINIT_A[17] origin:025-bram-config 27_01
BRAM_L.RAMB18_Y0.ZINIT_A[1] origin:025-bram-config 27_65
BRAM_L.RAMB18_Y0.ZINIT_A[2] origin:025-bram-config 27_137
BRAM_L.RAMB18_Y0.ZINIT_A[3] origin:025-bram-config 27_121
BRAM_L.RAMB18_Y0.ZINIT_A[4] origin:025-bram-config 27_105
BRAM_L.RAMB18_Y0.ZINIT_A[5] origin:025-bram-config 27_89
BRAM_L.RAMB18_Y0.ZINIT_A[6] origin:025-bram-config 27_57
BRAM_L.RAMB18_Y0.ZINIT_A[7] origin:025-bram-config 27_41
BRAM_L.RAMB18_Y0.ZINIT_A[8] origin:025-bram-config 27_25
BRAM_L.RAMB18_Y0.ZINIT_A[9] origin:025-bram-config 27_09
BRAM_L.RAMB18_Y0.ZINIT_B[0] origin:025-bram-config 27_79
BRAM_L.RAMB18_Y0.ZINIT_B[10] origin:025-bram-config 27_135
BRAM_L.RAMB18_Y0.ZINIT_B[11] origin:025-bram-config 27_119
BRAM_L.RAMB18_Y0.ZINIT_B[12] origin:025-bram-config 27_103
BRAM_L.RAMB18_Y0.ZINIT_B[13] origin:025-bram-config 27_87
BRAM_L.RAMB18_Y0.ZINIT_B[14] origin:025-bram-config 27_55
BRAM_L.RAMB18_Y0.ZINIT_B[15] origin:025-bram-config 27_39
BRAM_L.RAMB18_Y0.ZINIT_B[16] origin:025-bram-config 27_23
BRAM_L.RAMB18_Y0.ZINIT_B[17] origin:025-bram-config 27_07
BRAM_L.RAMB18_Y0.ZINIT_B[1] origin:025-bram-config 27_71
BRAM_L.RAMB18_Y0.ZINIT_B[2] origin:025-bram-config 27_143
BRAM_L.RAMB18_Y0.ZINIT_B[3] origin:025-bram-config 27_127
BRAM_L.RAMB18_Y0.ZINIT_B[4] origin:025-bram-config 27_111
BRAM_L.RAMB18_Y0.ZINIT_B[5] origin:025-bram-config 27_95
BRAM_L.RAMB18_Y0.ZINIT_B[6] origin:025-bram-config 27_63
BRAM_L.RAMB18_Y0.ZINIT_B[7] origin:025-bram-config 27_47
BRAM_L.RAMB18_Y0.ZINIT_B[8] origin:025-bram-config 27_31
BRAM_L.RAMB18_Y0.ZINIT_B[9] origin:025-bram-config 27_15
BRAM_L.RAMB18_Y0.ZINV_CLKARDCLK origin:025-bram-config 27_107
BRAM_L.RAMB18_Y0.ZINV_CLKBWRCLK origin:025-bram-config 27_109
BRAM_L.RAMB18_Y0.ZINV_ENARDEN origin:025-bram-config 27_112
BRAM_L.RAMB18_Y0.ZINV_ENBWREN origin:025-bram-config 27_115
BRAM_L.RAMB18_Y0.ZINV_REGCLKARDRCLK origin:025-bram-config 27_104
BRAM_L.RAMB18_Y0.ZINV_REGCLKB origin:025-bram-config 27_108
BRAM_L.RAMB18_Y0.ZINV_RSTRAMARSTRAM origin:025-bram-config 27_116
BRAM_L.RAMB18_Y0.ZINV_RSTRAMB origin:025-bram-config 27_117
BRAM_L.RAMB18_Y0.ZINV_RSTREGARSTREG origin:025-bram-config 27_120
BRAM_L.RAMB18_Y0.ZINV_RSTREGB origin:025-bram-config 27_123
BRAM_L.RAMB18_Y0.ZSRVAL_A[0] origin:025-bram-config 27_74
BRAM_L.RAMB18_Y0.ZSRVAL_A[10] origin:025-bram-config 27_130
BRAM_L.RAMB18_Y0.ZSRVAL_A[11] origin:025-bram-config 27_114
BRAM_L.RAMB18_Y0.ZSRVAL_A[12] origin:025-bram-config 27_98
BRAM_L.RAMB18_Y0.ZSRVAL_A[13] origin:025-bram-config 27_82
BRAM_L.RAMB18_Y0.ZSRVAL_A[14] origin:025-bram-config 27_50
BRAM_L.RAMB18_Y0.ZSRVAL_A[15] origin:025-bram-config 27_34
BRAM_L.RAMB18_Y0.ZSRVAL_A[16] origin:025-bram-config 27_18
BRAM_L.RAMB18_Y0.ZSRVAL_A[17] origin:025-bram-config 27_02
BRAM_L.RAMB18_Y0.ZSRVAL_A[1] origin:025-bram-config 27_66
BRAM_L.RAMB18_Y0.ZSRVAL_A[2] origin:025-bram-config 27_138
BRAM_L.RAMB18_Y0.ZSRVAL_A[3] origin:025-bram-config 27_122
BRAM_L.RAMB18_Y0.ZSRVAL_A[4] origin:025-bram-config 27_106
BRAM_L.RAMB18_Y0.ZSRVAL_A[5] origin:025-bram-config 27_90
BRAM_L.RAMB18_Y0.ZSRVAL_A[6] origin:025-bram-config 27_58
BRAM_L.RAMB18_Y0.ZSRVAL_A[7] origin:025-bram-config 27_42
BRAM_L.RAMB18_Y0.ZSRVAL_A[8] origin:025-bram-config 27_26
BRAM_L.RAMB18_Y0.ZSRVAL_A[9] origin:025-bram-config 27_10
BRAM_L.RAMB18_Y0.ZSRVAL_B[0] origin:025-bram-config 27_78
BRAM_L.RAMB18_Y0.ZSRVAL_B[10] origin:025-bram-config 27_134
BRAM_L.RAMB18_Y0.ZSRVAL_B[11] origin:025-bram-config 27_118
BRAM_L.RAMB18_Y0.ZSRVAL_B[12] origin:025-bram-config 27_102
BRAM_L.RAMB18_Y0.ZSRVAL_B[13] origin:025-bram-config 27_86
BRAM_L.RAMB18_Y0.ZSRVAL_B[14] origin:025-bram-config 27_54
BRAM_L.RAMB18_Y0.ZSRVAL_B[15] origin:025-bram-config 27_38
BRAM_L.RAMB18_Y0.ZSRVAL_B[16] origin:025-bram-config 27_22
BRAM_L.RAMB18_Y0.ZSRVAL_B[17] origin:025-bram-config 27_06
BRAM_L.RAMB18_Y0.ZSRVAL_B[1] origin:025-bram-config 27_70
BRAM_L.RAMB18_Y0.ZSRVAL_B[2] origin:025-bram-config 27_142
BRAM_L.RAMB18_Y0.ZSRVAL_B[3] origin:025-bram-config 27_126
BRAM_L.RAMB18_Y0.ZSRVAL_B[4] origin:025-bram-config 27_110
BRAM_L.RAMB18_Y0.ZSRVAL_B[5] origin:025-bram-config 27_94
BRAM_L.RAMB18_Y0.ZSRVAL_B[6] origin:025-bram-config 27_62
BRAM_L.RAMB18_Y0.ZSRVAL_B[7] origin:025-bram-config 27_46
BRAM_L.RAMB18_Y0.ZSRVAL_B[8] origin:025-bram-config 27_30
BRAM_L.RAMB18_Y0.ZSRVAL_B[9] origin:025-bram-config 27_14
BRAM_L.RAMB18_Y1.DOA_REG origin:025-bram-config 27_251
BRAM_L.RAMB18_Y1.DOB_REG origin:025-bram-config 27_248
BRAM_L.RAMB18_Y1.FIFO_MODE origin:029-bram-fifo-config 27_169
BRAM_L.RAMB18_Y1.IN_USE origin:029-bram-fifo-config 27_220 27_221
BRAM_L.RAMB18_Y1.RDADDR_COLLISION_HWCONFIG_DELAYED_WRITE origin:025-bram-config !27_224
BRAM_L.RAMB18_Y1.RDADDR_COLLISION_HWCONFIG_PERFORMANCE origin:025-bram-config 27_224
BRAM_L.RAMB18_Y1.READ_WIDTH_A_1 origin:025-bram-config !27_283 !27_284 !27_285
BRAM_L.RAMB18_Y1.READ_WIDTH_A_18 origin:025-bram-config !27_284 !27_285 27_283
BRAM_L.RAMB18_Y1.READ_WIDTH_A_2 origin:025-bram-config !27_283 !27_284 27_285
BRAM_L.RAMB18_Y1.READ_WIDTH_A_4 origin:025-bram-config !27_283 !27_285 27_284
BRAM_L.RAMB18_Y1.READ_WIDTH_A_9 origin:025-bram-config !27_283 27_284 27_285
BRAM_L.RAMB18_Y1.READ_WIDTH_B_1 origin:025-bram-config !27_275 !27_276 !27_277
BRAM_L.RAMB18_Y1.READ_WIDTH_B_18 origin:025-bram-config !27_276 !27_277 27_275
BRAM_L.RAMB18_Y1.READ_WIDTH_B_2 origin:025-bram-config !27_275 !27_276 27_277
BRAM_L.RAMB18_Y1.READ_WIDTH_B_4 origin:025-bram-config !27_275 !27_277 27_276
BRAM_L.RAMB18_Y1.READ_WIDTH_B_9 origin:025-bram-config !27_275 27_276 27_277
BRAM_L.RAMB18_Y1.RSTREG_PRIORITY_A_REGCE origin:025-bram-config 27_196
BRAM_L.RAMB18_Y1.RSTREG_PRIORITY_A_RSTREG origin:025-bram-config !27_196
BRAM_L.RAMB18_Y1.RSTREG_PRIORITY_B_REGCE origin:025-bram-config 27_195
BRAM_L.RAMB18_Y1.RSTREG_PRIORITY_B_RSTREG origin:025-bram-config !27_195
BRAM_L.RAMB18_Y1.SDP_READ_WIDTH_36 origin:025-bram-config 27_272
BRAM_L.RAMB18_Y1.SDP_WRITE_WIDTH_36 origin:025-bram-config 27_280
BRAM_L.RAMB18_Y1.WRITE_MODE_A_NO_CHANGE origin:025-bram-config 27_256
BRAM_L.RAMB18_Y1.WRITE_MODE_A_READ_FIRST origin:025-bram-config 27_264
BRAM_L.RAMB18_Y1.WRITE_MODE_B_NO_CHANGE origin:025-bram-config 27_252
BRAM_L.RAMB18_Y1.WRITE_MODE_B_READ_FIRST origin:025-bram-config 27_253
BRAM_L.RAMB18_Y1.WRITE_WIDTH_A_1 origin:025-bram-config !27_267 !27_268 !27_269
BRAM_L.RAMB18_Y1.WRITE_WIDTH_A_18 origin:025-bram-config !27_268 !27_269 27_267
BRAM_L.RAMB18_Y1.WRITE_WIDTH_A_2 origin:025-bram-config !27_267 !27_268 27_269
BRAM_L.RAMB18_Y1.WRITE_WIDTH_A_4 origin:025-bram-config !27_267 !27_269 27_268
BRAM_L.RAMB18_Y1.WRITE_WIDTH_A_9 origin:025-bram-config !27_267 27_268 27_269
BRAM_L.RAMB18_Y1.WRITE_WIDTH_B_1 origin:025-bram-config !27_259 !27_260 !27_261
BRAM_L.RAMB18_Y1.WRITE_WIDTH_B_18 origin:025-bram-config !27_260 !27_261 27_259
BRAM_L.RAMB18_Y1.WRITE_WIDTH_B_2 origin:025-bram-config !27_259 !27_260 27_261
BRAM_L.RAMB18_Y1.WRITE_WIDTH_B_4 origin:025-bram-config !27_259 !27_261 27_260
BRAM_L.RAMB18_Y1.WRITE_WIDTH_B_9 origin:025-bram-config !27_259 27_260 27_261
BRAM_L.RAMB18_Y1.ZINIT_A[0] origin:025-bram-config 27_249
BRAM_L.RAMB18_Y1.ZINIT_A[10] origin:025-bram-config 27_305
BRAM_L.RAMB18_Y1.ZINIT_A[11] origin:025-bram-config 27_289
BRAM_L.RAMB18_Y1.ZINIT_A[12] origin:025-bram-config 27_273
BRAM_L.RAMB18_Y1.ZINIT_A[13] origin:025-bram-config 27_257
BRAM_L.RAMB18_Y1.ZINIT_A[14] origin:025-bram-config 27_225
BRAM_L.RAMB18_Y1.ZINIT_A[15] origin:025-bram-config 27_209
BRAM_L.RAMB18_Y1.ZINIT_A[16] origin:025-bram-config 27_193
BRAM_L.RAMB18_Y1.ZINIT_A[17] origin:025-bram-config 27_177
BRAM_L.RAMB18_Y1.ZINIT_A[1] origin:025-bram-config 27_241
BRAM_L.RAMB18_Y1.ZINIT_A[2] origin:025-bram-config 27_313
BRAM_L.RAMB18_Y1.ZINIT_A[3] origin:025-bram-config 27_297
BRAM_L.RAMB18_Y1.ZINIT_A[4] origin:025-bram-config 27_281
BRAM_L.RAMB18_Y1.ZINIT_A[5] origin:025-bram-config 27_265
BRAM_L.RAMB18_Y1.ZINIT_A[6] origin:025-bram-config 27_233
BRAM_L.RAMB18_Y1.ZINIT_A[7] origin:025-bram-config 27_217
BRAM_L.RAMB18_Y1.ZINIT_A[8] origin:025-bram-config 27_201
BRAM_L.RAMB18_Y1.ZINIT_A[9] origin:025-bram-config 27_185
BRAM_L.RAMB18_Y1.ZINIT_B[0] origin:025-bram-config 27_255
BRAM_L.RAMB18_Y1.ZINIT_B[10] origin:025-bram-config 27_311
BRAM_L.RAMB18_Y1.ZINIT_B[11] origin:025-bram-config 27_295
BRAM_L.RAMB18_Y1.ZINIT_B[12] origin:025-bram-config 27_279
BRAM_L.RAMB18_Y1.ZINIT_B[13] origin:025-bram-config 27_263
BRAM_L.RAMB18_Y1.ZINIT_B[14] origin:025-bram-config 27_231
BRAM_L.RAMB18_Y1.ZINIT_B[15] origin:025-bram-config 27_215
BRAM_L.RAMB18_Y1.ZINIT_B[16] origin:025-bram-config 27_199
BRAM_L.RAMB18_Y1.ZINIT_B[17] origin:025-bram-config 27_183
BRAM_L.RAMB18_Y1.ZINIT_B[1] origin:025-bram-config 27_247
BRAM_L.RAMB18_Y1.ZINIT_B[2] origin:025-bram-config 27_319
BRAM_L.RAMB18_Y1.ZINIT_B[3] origin:025-bram-config 27_303
BRAM_L.RAMB18_Y1.ZINIT_B[4] origin:025-bram-config 27_287
BRAM_L.RAMB18_Y1.ZINIT_B[5] origin:025-bram-config 27_271
BRAM_L.RAMB18_Y1.ZINIT_B[6] origin:025-bram-config 27_239
BRAM_L.RAMB18_Y1.ZINIT_B[7] origin:025-bram-config 27_223
BRAM_L.RAMB18_Y1.ZINIT_B[8] origin:025-bram-config 27_207
BRAM_L.RAMB18_Y1.ZINIT_B[9] origin:025-bram-config 27_191
BRAM_L.RAMB18_Y1.ZINV_CLKARDCLK origin:025-bram-config 27_213
BRAM_L.RAMB18_Y1.ZINV_CLKBWRCLK origin:025-bram-config 27_211
BRAM_L.RAMB18_Y1.ZINV_ENARDEN origin:025-bram-config 27_208
BRAM_L.RAMB18_Y1.ZINV_ENBWREN origin:025-bram-config 27_205
BRAM_L.RAMB18_Y1.ZINV_REGCLKARDRCLK origin:025-bram-config 27_216
BRAM_L.RAMB18_Y1.ZINV_REGCLKB origin:025-bram-config 27_212
BRAM_L.RAMB18_Y1.ZINV_RSTRAMARSTRAM origin:025-bram-config 27_204
BRAM_L.RAMB18_Y1.ZINV_RSTRAMB origin:025-bram-config 27_203
BRAM_L.RAMB18_Y1.ZINV_RSTREGARSTREG origin:025-bram-config 27_200
BRAM_L.RAMB18_Y1.ZINV_RSTREGB origin:025-bram-config 27_197
BRAM_L.RAMB18_Y1.ZSRVAL_A[0] origin:025-bram-config 27_250
BRAM_L.RAMB18_Y1.ZSRVAL_A[10] origin:025-bram-config 27_306
BRAM_L.RAMB18_Y1.ZSRVAL_A[11] origin:025-bram-config 27_290
BRAM_L.RAMB18_Y1.ZSRVAL_A[12] origin:025-bram-config 27_274
BRAM_L.RAMB18_Y1.ZSRVAL_A[13] origin:025-bram-config 27_258
BRAM_L.RAMB18_Y1.ZSRVAL_A[14] origin:025-bram-config 27_226
BRAM_L.RAMB18_Y1.ZSRVAL_A[15] origin:025-bram-config 27_210
BRAM_L.RAMB18_Y1.ZSRVAL_A[16] origin:025-bram-config 27_194
BRAM_L.RAMB18_Y1.ZSRVAL_A[17] origin:025-bram-config 27_178
BRAM_L.RAMB18_Y1.ZSRVAL_A[1] origin:025-bram-config 27_242
BRAM_L.RAMB18_Y1.ZSRVAL_A[2] origin:025-bram-config 27_314
BRAM_L.RAMB18_Y1.ZSRVAL_A[3] origin:025-bram-config 27_298
BRAM_L.RAMB18_Y1.ZSRVAL_A[4] origin:025-bram-config 27_282
BRAM_L.RAMB18_Y1.ZSRVAL_A[5] origin:025-bram-config 27_266
BRAM_L.RAMB18_Y1.ZSRVAL_A[6] origin:025-bram-config 27_234
BRAM_L.RAMB18_Y1.ZSRVAL_A[7] origin:025-bram-config 27_218
BRAM_L.RAMB18_Y1.ZSRVAL_A[8] origin:025-bram-config 27_202
BRAM_L.RAMB18_Y1.ZSRVAL_A[9] origin:025-bram-config 27_186
BRAM_L.RAMB18_Y1.ZSRVAL_B[0] origin:025-bram-config 27_254
BRAM_L.RAMB18_Y1.ZSRVAL_B[10] origin:025-bram-config 27_310
BRAM_L.RAMB18_Y1.ZSRVAL_B[11] origin:025-bram-config 27_294
BRAM_L.RAMB18_Y1.ZSRVAL_B[12] origin:025-bram-config 27_278
BRAM_L.RAMB18_Y1.ZSRVAL_B[13] origin:025-bram-config 27_262
BRAM_L.RAMB18_Y1.ZSRVAL_B[14] origin:025-bram-config 27_230
BRAM_L.RAMB18_Y1.ZSRVAL_B[15] origin:025-bram-config 27_214
BRAM_L.RAMB18_Y1.ZSRVAL_B[16] origin:025-bram-config 27_198
BRAM_L.RAMB18_Y1.ZSRVAL_B[17] origin:025-bram-config 27_182
BRAM_L.RAMB18_Y1.ZSRVAL_B[1] origin:025-bram-config 27_246
BRAM_L.RAMB18_Y1.ZSRVAL_B[2] origin:025-bram-config 27_318
BRAM_L.RAMB18_Y1.ZSRVAL_B[3] origin:025-bram-config 27_302
BRAM_L.RAMB18_Y1.ZSRVAL_B[4] origin:025-bram-config 27_286
BRAM_L.RAMB18_Y1.ZSRVAL_B[5] origin:025-bram-config 27_270
BRAM_L.RAMB18_Y1.ZSRVAL_B[6] origin:025-bram-config 27_238
BRAM_L.RAMB18_Y1.ZSRVAL_B[7] origin:025-bram-config 27_222
BRAM_L.RAMB18_Y1.ZSRVAL_B[8] origin:025-bram-config 27_206
BRAM_L.RAMB18_Y1.ZSRVAL_B[9] origin:025-bram-config 27_190
BRAM_L.RAMB36.EN_ECC_READ origin:027-bram36-config 27_175
BRAM_L.RAMB36.EN_ECC_WRITE origin:027-bram36-config 27_162
BRAM_L.RAMB36.RAM_EXTENSION_A_LOWER origin:027-bram36-config 27_188
BRAM_L.RAMB36.RAM_EXTENSION_A_NONE_OR_UPPER origin:027-bram36-config !27_188
BRAM_L.RAMB36.RAM_EXTENSION_B_LOWER origin:027-bram36-config 27_187
BRAM_L.RAMB36.RAM_EXTENSION_B_NONE_OR_UPPER origin:027-bram36-config !27_187
BRAM_L.ZALMOST_EMPTY_OFFSET[0] origin:028-fifo-config 27_288
BRAM_L.ZALMOST_EMPTY_OFFSET[10] origin:028-fifo-config 27_308
BRAM_L.ZALMOST_EMPTY_OFFSET[11] origin:028-fifo-config 27_309
BRAM_L.ZALMOST_EMPTY_OFFSET[12] origin:028-fifo-config 27_312
BRAM_L.ZALMOST_EMPTY_OFFSET[1] origin:028-fifo-config 27_291
BRAM_L.ZALMOST_EMPTY_OFFSET[2] origin:028-fifo-config 27_292
BRAM_L.ZALMOST_EMPTY_OFFSET[3] origin:028-fifo-config 27_293
BRAM_L.ZALMOST_EMPTY_OFFSET[4] origin:028-fifo-config 27_296
BRAM_L.ZALMOST_EMPTY_OFFSET[5] origin:028-fifo-config 27_299
BRAM_L.ZALMOST_EMPTY_OFFSET[6] origin:028-fifo-config 27_300
BRAM_L.ZALMOST_EMPTY_OFFSET[7] origin:028-fifo-config 27_301
BRAM_L.ZALMOST_EMPTY_OFFSET[8] origin:028-fifo-config 27_304
BRAM_L.ZALMOST_EMPTY_OFFSET[9] origin:028-fifo-config 27_307
BRAM_L.ZALMOST_FULL_OFFSET[0] origin:028-fifo-config 27_32
BRAM_L.ZALMOST_FULL_OFFSET[10] origin:028-fifo-config 27_12
BRAM_L.ZALMOST_FULL_OFFSET[11] origin:028-fifo-config 27_11
BRAM_L.ZALMOST_FULL_OFFSET[12] origin:028-fifo-config 27_08
BRAM_L.ZALMOST_FULL_OFFSET[1] origin:028-fifo-config 27_29
BRAM_L.ZALMOST_FULL_OFFSET[2] origin:028-fifo-config 27_28
BRAM_L.ZALMOST_FULL_OFFSET[3] origin:028-fifo-config 27_27
BRAM_L.ZALMOST_FULL_OFFSET[4] origin:028-fifo-config 27_24
BRAM_L.ZALMOST_FULL_OFFSET[5] origin:028-fifo-config 27_21
BRAM_L.ZALMOST_FULL_OFFSET[6] origin:028-fifo-config 27_20
BRAM_L.ZALMOST_FULL_OFFSET[7] origin:028-fifo-config 27_19
BRAM_L.ZALMOST_FULL_OFFSET[8] origin:028-fifo-config 27_16
BRAM_L.ZALMOST_FULL_OFFSET[9] origin:028-fifo-config 27_13

36864
zynq7/segbits_bram_r.block_ram.origin_info.db Normal file
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zynq7/segbits_bram_r.origin_info.db Normal file
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BRAM_R.BRAM_ADDRARDADDRL0.BRAM_CASCINBOT_ADDRARDADDRU0 origin:060-bram-cascades !26_33 26_32 26_35
BRAM_R.BRAM_ADDRARDADDRL0.BRAM_CASCINTOP_ADDRARDADDRU0 origin:060-bram-cascades !26_35 26_32 26_33
BRAM_R.BRAM_ADDRARDADDRL0.BRAM_R_IMUX_ADDRARDADDRL0 origin:060-bram-cascades !26_32 !26_33 !26_35
BRAM_R.BRAM_ADDRARDADDRL1.BRAM_CASCINBOT_ADDRARDADDRU1 origin:060-bram-cascades !26_49 26_48 26_51
BRAM_R.BRAM_ADDRARDADDRL1.BRAM_CASCINTOP_ADDRARDADDRU1 origin:060-bram-cascades !26_51 26_48 26_49
BRAM_R.BRAM_ADDRARDADDRL1.BRAM_R_IMUX_ADDRARDADDRL1 origin:060-bram-cascades !26_48 !26_49 !26_51
BRAM_R.BRAM_ADDRARDADDRL10.BRAM_CASCINBOT_ADDRARDADDRU10 origin:060-bram-cascades !26_145 26_144 26_147
BRAM_R.BRAM_ADDRARDADDRL10.BRAM_CASCINTOP_ADDRARDADDRU10 origin:060-bram-cascades !26_147 26_144 26_145
BRAM_R.BRAM_ADDRARDADDRL10.BRAM_R_IMUX_ADDRARDADDRL10 origin:060-bram-cascades !26_144 !26_145 !26_147
BRAM_R.BRAM_ADDRARDADDRL11.BRAM_CASCINBOT_ADDRARDADDRU11 origin:060-bram-cascades !26_113 26_112 26_115
BRAM_R.BRAM_ADDRARDADDRL11.BRAM_CASCINTOP_ADDRARDADDRU11 origin:060-bram-cascades !26_115 26_112 26_113
BRAM_R.BRAM_ADDRARDADDRL11.BRAM_R_IMUX_ADDRARDADDRL11 origin:060-bram-cascades !26_112 !26_113 !26_115
BRAM_R.BRAM_ADDRARDADDRL12.BRAM_CASCINBOT_ADDRARDADDRU12 origin:060-bram-cascades !26_241 26_240 26_243
BRAM_R.BRAM_ADDRARDADDRL12.BRAM_CASCINTOP_ADDRARDADDRU12 origin:060-bram-cascades !26_243 26_240 26_241
BRAM_R.BRAM_ADDRARDADDRL12.BRAM_R_IMUX_ADDRARDADDRL12 origin:060-bram-cascades !26_240 !26_241 !26_243
BRAM_R.BRAM_ADDRARDADDRL13.BRAM_CASCINBOT_ADDRARDADDRU13 origin:060-bram-cascades !26_129 26_128 26_131
BRAM_R.BRAM_ADDRARDADDRL13.BRAM_CASCINTOP_ADDRARDADDRU13 origin:060-bram-cascades !26_131 26_128 26_129
BRAM_R.BRAM_ADDRARDADDRL13.BRAM_R_IMUX_ADDRARDADDRL13 origin:060-bram-cascades !26_128 !26_129 !26_131
BRAM_R.BRAM_ADDRARDADDRL14.BRAM_CASCINBOT_ADDRARDADDRU14 origin:060-bram-cascades !26_257 26_256 26_259
BRAM_R.BRAM_ADDRARDADDRL14.BRAM_CASCINTOP_ADDRARDADDRU14 origin:060-bram-cascades !26_259 26_256 26_257
BRAM_R.BRAM_ADDRARDADDRL14.BRAM_R_IMUX_ADDRARDADDRL14 origin:060-bram-cascades !26_256 !26_257 !26_259
BRAM_R.BRAM_ADDRARDADDRL2.BRAM_CASCINBOT_ADDRARDADDRU2 origin:060-bram-cascades !26_65 26_64 26_67
BRAM_R.BRAM_ADDRARDADDRL2.BRAM_CASCINTOP_ADDRARDADDRU2 origin:060-bram-cascades !26_67 26_64 26_65
BRAM_R.BRAM_ADDRARDADDRL2.BRAM_R_IMUX_ADDRARDADDRL2 origin:060-bram-cascades !26_64 !26_65 !26_67
BRAM_R.BRAM_ADDRARDADDRL3.BRAM_CASCINBOT_ADDRARDADDRU3 origin:060-bram-cascades !26_193 26_192 26_195
BRAM_R.BRAM_ADDRARDADDRL3.BRAM_CASCINTOP_ADDRARDADDRU3 origin:060-bram-cascades !26_195 26_192 26_193
BRAM_R.BRAM_ADDRARDADDRL3.BRAM_R_IMUX_ADDRARDADDRL3 origin:060-bram-cascades !26_192 !26_193 !26_195
BRAM_R.BRAM_ADDRARDADDRL4.BRAM_CASCINBOT_ADDRARDADDRU4 origin:060-bram-cascades !26_97 26_96 26_99
BRAM_R.BRAM_ADDRARDADDRL4.BRAM_CASCINTOP_ADDRARDADDRU4 origin:060-bram-cascades !26_99 26_96 26_97
BRAM_R.BRAM_ADDRARDADDRL4.BRAM_R_IMUX_ADDRARDADDRL4 origin:060-bram-cascades !26_96 !26_97 !26_99
BRAM_R.BRAM_ADDRARDADDRL5.BRAM_CASCINBOT_ADDRARDADDRU5 origin:060-bram-cascades !26_225 26_224 26_227
BRAM_R.BRAM_ADDRARDADDRL5.BRAM_CASCINTOP_ADDRARDADDRU5 origin:060-bram-cascades !26_227 26_224 26_225
BRAM_R.BRAM_ADDRARDADDRL5.BRAM_R_IMUX_ADDRARDADDRL5 origin:060-bram-cascades !26_224 !26_225 !26_227
BRAM_R.BRAM_ADDRARDADDRL6.BRAM_CASCINBOT_ADDRARDADDRU6 origin:060-bram-cascades !26_161 26_160 26_163
BRAM_R.BRAM_ADDRARDADDRL6.BRAM_CASCINTOP_ADDRARDADDRU6 origin:060-bram-cascades !26_163 26_160 26_161
BRAM_R.BRAM_ADDRARDADDRL6.BRAM_R_IMUX_ADDRARDADDRL6 origin:060-bram-cascades !26_160 !26_161 !26_163
BRAM_R.BRAM_ADDRARDADDRL7.BRAM_CASCINBOT_ADDRARDADDRU7 origin:060-bram-cascades !26_177 26_176 26_179
BRAM_R.BRAM_ADDRARDADDRL7.BRAM_CASCINTOP_ADDRARDADDRU7 origin:060-bram-cascades !26_179 26_176 26_177
BRAM_R.BRAM_ADDRARDADDRL7.BRAM_R_IMUX_ADDRARDADDRL7 origin:060-bram-cascades !26_176 !26_177 !26_179
BRAM_R.BRAM_ADDRARDADDRL8.BRAM_CASCINBOT_ADDRARDADDRU8 origin:060-bram-cascades !26_81 26_80 26_83
BRAM_R.BRAM_ADDRARDADDRL8.BRAM_CASCINTOP_ADDRARDADDRU8 origin:060-bram-cascades !26_83 26_80 26_81
BRAM_R.BRAM_ADDRARDADDRL8.BRAM_R_IMUX_ADDRARDADDRL8 origin:060-bram-cascades !26_80 !26_81 !26_83
BRAM_R.BRAM_ADDRARDADDRL9.BRAM_CASCINBOT_ADDRARDADDRU9 origin:060-bram-cascades !26_209 26_208 26_211
BRAM_R.BRAM_ADDRARDADDRL9.BRAM_CASCINTOP_ADDRARDADDRU9 origin:060-bram-cascades !26_211 26_208 26_209
BRAM_R.BRAM_ADDRARDADDRL9.BRAM_R_IMUX_ADDRARDADDRL9 origin:060-bram-cascades !26_208 !26_209 !26_211
BRAM_R.BRAM_ADDRARDADDRU0.BRAM_CASCINBOT_ADDRARDADDRU0 origin:060-bram-cascades !26_38 26_37 26_39
BRAM_R.BRAM_ADDRARDADDRU0.BRAM_CASCINTOP_ADDRARDADDRU0 origin:060-bram-cascades !26_37 26_38 26_39
BRAM_R.BRAM_ADDRARDADDRU0.BRAM_R_IMUX_ADDRARDADDRU0 origin:060-bram-cascades !26_37 !26_38 !26_39
BRAM_R.BRAM_ADDRARDADDRU1.BRAM_CASCINBOT_ADDRARDADDRU1 origin:060-bram-cascades !26_54 26_53 26_55
BRAM_R.BRAM_ADDRARDADDRU1.BRAM_CASCINTOP_ADDRARDADDRU1 origin:060-bram-cascades !26_53 26_54 26_55
BRAM_R.BRAM_ADDRARDADDRU1.BRAM_R_IMUX_ADDRARDADDRU1 origin:060-bram-cascades !26_53 !26_54 !26_55
BRAM_R.BRAM_ADDRARDADDRU10.BRAM_CASCINBOT_ADDRARDADDRU10 origin:060-bram-cascades !26_150 26_149 26_151
BRAM_R.BRAM_ADDRARDADDRU10.BRAM_CASCINTOP_ADDRARDADDRU10 origin:060-bram-cascades !26_149 26_150 26_151
BRAM_R.BRAM_ADDRARDADDRU10.BRAM_R_IMUX_ADDRARDADDRU10 origin:060-bram-cascades !26_149 !26_150 !26_151
BRAM_R.BRAM_ADDRARDADDRU11.BRAM_CASCINBOT_ADDRARDADDRU11 origin:060-bram-cascades !26_118 26_117 26_119
BRAM_R.BRAM_ADDRARDADDRU11.BRAM_CASCINTOP_ADDRARDADDRU11 origin:060-bram-cascades !26_117 26_118 26_119
BRAM_R.BRAM_ADDRARDADDRU11.BRAM_R_IMUX_ADDRARDADDRU11 origin:060-bram-cascades !26_117 !26_118 !26_119
BRAM_R.BRAM_ADDRARDADDRU12.BRAM_CASCINBOT_ADDRARDADDRU12 origin:060-bram-cascades !26_246 26_245 26_247
BRAM_R.BRAM_ADDRARDADDRU12.BRAM_CASCINTOP_ADDRARDADDRU12 origin:060-bram-cascades !26_245 26_246 26_247
BRAM_R.BRAM_ADDRARDADDRU12.BRAM_R_IMUX_ADDRARDADDRU12 origin:060-bram-cascades !26_245 !26_246 !26_247
BRAM_R.BRAM_ADDRARDADDRU13.BRAM_CASCINBOT_ADDRARDADDRU13 origin:060-bram-cascades !26_134 26_133 26_135
BRAM_R.BRAM_ADDRARDADDRU13.BRAM_CASCINTOP_ADDRARDADDRU13 origin:060-bram-cascades !26_133 26_134 26_135
BRAM_R.BRAM_ADDRARDADDRU13.BRAM_R_IMUX_ADDRARDADDRU13 origin:060-bram-cascades !26_133 !26_134 !26_135
BRAM_R.BRAM_ADDRARDADDRU14.BRAM_CASCINBOT_ADDRARDADDRU14 origin:060-bram-cascades !26_262 26_261 26_263
BRAM_R.BRAM_ADDRARDADDRU14.BRAM_CASCINTOP_ADDRARDADDRU14 origin:060-bram-cascades !26_261 26_262 26_263
BRAM_R.BRAM_ADDRARDADDRU14.BRAM_R_IMUX_ADDRARDADDRU14 origin:060-bram-cascades !26_261 !26_262 !26_263
BRAM_R.BRAM_ADDRARDADDRU2.BRAM_CASCINBOT_ADDRARDADDRU2 origin:060-bram-cascades !26_70 26_69 26_71
BRAM_R.BRAM_ADDRARDADDRU2.BRAM_CASCINTOP_ADDRARDADDRU2 origin:060-bram-cascades !26_69 26_70 26_71
BRAM_R.BRAM_ADDRARDADDRU2.BRAM_R_IMUX_ADDRARDADDRU2 origin:060-bram-cascades !26_69 !26_70 !26_71
BRAM_R.BRAM_ADDRARDADDRU3.BRAM_CASCINBOT_ADDRARDADDRU3 origin:060-bram-cascades !26_198 26_197 26_199
BRAM_R.BRAM_ADDRARDADDRU3.BRAM_CASCINTOP_ADDRARDADDRU3 origin:060-bram-cascades !26_197 26_198 26_199
BRAM_R.BRAM_ADDRARDADDRU3.BRAM_R_IMUX_ADDRARDADDRU3 origin:060-bram-cascades !26_197 !26_198 !26_199
BRAM_R.BRAM_ADDRARDADDRU4.BRAM_CASCINBOT_ADDRARDADDRU4 origin:060-bram-cascades !26_102 26_101 26_103
BRAM_R.BRAM_ADDRARDADDRU4.BRAM_CASCINTOP_ADDRARDADDRU4 origin:060-bram-cascades !26_101 26_102 26_103
BRAM_R.BRAM_ADDRARDADDRU4.BRAM_R_IMUX_ADDRARDADDRU4 origin:060-bram-cascades !26_101 !26_102 !26_103
BRAM_R.BRAM_ADDRARDADDRU5.BRAM_CASCINBOT_ADDRARDADDRU5 origin:060-bram-cascades !26_230 26_229 26_231
BRAM_R.BRAM_ADDRARDADDRU5.BRAM_CASCINTOP_ADDRARDADDRU5 origin:060-bram-cascades !26_229 26_230 26_231
BRAM_R.BRAM_ADDRARDADDRU5.BRAM_R_IMUX_ADDRARDADDRU5 origin:060-bram-cascades !26_229 !26_230 !26_231
BRAM_R.BRAM_ADDRARDADDRU6.BRAM_CASCINBOT_ADDRARDADDRU6 origin:060-bram-cascades !26_166 26_165 26_167
BRAM_R.BRAM_ADDRARDADDRU6.BRAM_CASCINTOP_ADDRARDADDRU6 origin:060-bram-cascades !26_165 26_166 26_167
BRAM_R.BRAM_ADDRARDADDRU6.BRAM_R_IMUX_ADDRARDADDRU6 origin:060-bram-cascades !26_165 !26_166 !26_167
BRAM_R.BRAM_ADDRARDADDRU7.BRAM_CASCINBOT_ADDRARDADDRU7 origin:060-bram-cascades !26_182 26_181 26_183
BRAM_R.BRAM_ADDRARDADDRU7.BRAM_CASCINTOP_ADDRARDADDRU7 origin:060-bram-cascades !26_181 26_182 26_183
BRAM_R.BRAM_ADDRARDADDRU7.BRAM_R_IMUX_ADDRARDADDRU7 origin:060-bram-cascades !26_181 !26_182 !26_183
BRAM_R.BRAM_ADDRARDADDRU8.BRAM_CASCINBOT_ADDRARDADDRU8 origin:060-bram-cascades !26_86 26_85 26_87
BRAM_R.BRAM_ADDRARDADDRU8.BRAM_CASCINTOP_ADDRARDADDRU8 origin:060-bram-cascades !26_85 26_86 26_87
BRAM_R.BRAM_ADDRARDADDRU8.BRAM_R_IMUX_ADDRARDADDRU8 origin:060-bram-cascades !26_85 !26_86 !26_87
BRAM_R.BRAM_ADDRARDADDRU9.BRAM_CASCINBOT_ADDRARDADDRU9 origin:060-bram-cascades !26_214 26_213 26_215
BRAM_R.BRAM_ADDRARDADDRU9.BRAM_CASCINTOP_ADDRARDADDRU9 origin:060-bram-cascades !26_213 26_214 26_215
BRAM_R.BRAM_ADDRARDADDRU9.BRAM_R_IMUX_ADDRARDADDRU9 origin:060-bram-cascades !26_213 !26_214 !26_215
BRAM_R.BRAM_ADDRBWRADDRL0.BRAM_CASCINBOT_ADDRBWRADDRU0 origin:060-bram-cascades !26_41 26_40 26_43
BRAM_R.BRAM_ADDRBWRADDRL0.BRAM_CASCINTOP_ADDRBWRADDRU0 origin:060-bram-cascades !26_43 26_40 26_41
BRAM_R.BRAM_ADDRBWRADDRL0.BRAM_R_IMUX_ADDRBWRADDRL0 origin:060-bram-cascades !26_40 !26_41 !26_43
BRAM_R.BRAM_ADDRBWRADDRL1.BRAM_CASCINBOT_ADDRBWRADDRU1 origin:060-bram-cascades !26_57 26_56 26_59
BRAM_R.BRAM_ADDRBWRADDRL1.BRAM_CASCINTOP_ADDRBWRADDRU1 origin:060-bram-cascades !26_59 26_56 26_57
BRAM_R.BRAM_ADDRBWRADDRL1.BRAM_R_IMUX_ADDRBWRADDRL1 origin:060-bram-cascades !26_56 !26_57 !26_59
BRAM_R.BRAM_ADDRBWRADDRL10.BRAM_CASCINBOT_ADDRBWRADDRU10 origin:060-bram-cascades !26_153 26_152 26_155
BRAM_R.BRAM_ADDRBWRADDRL10.BRAM_CASCINTOP_ADDRBWRADDRU10 origin:060-bram-cascades !26_155 26_152 26_153
BRAM_R.BRAM_ADDRBWRADDRL10.BRAM_R_IMUX_ADDRBWRADDRL10 origin:060-bram-cascades !26_152 !26_153 !26_155
BRAM_R.BRAM_ADDRBWRADDRL11.BRAM_CASCINBOT_ADDRBWRADDRU11 origin:060-bram-cascades !26_121 26_120 26_123
BRAM_R.BRAM_ADDRBWRADDRL11.BRAM_CASCINTOP_ADDRBWRADDRU11 origin:060-bram-cascades !26_123 26_120 26_121
BRAM_R.BRAM_ADDRBWRADDRL11.BRAM_R_IMUX_ADDRBWRADDRL11 origin:060-bram-cascades !26_120 !26_121 !26_123
BRAM_R.BRAM_ADDRBWRADDRL12.BRAM_CASCINBOT_ADDRBWRADDRU12 origin:060-bram-cascades !26_249 26_248 26_251
BRAM_R.BRAM_ADDRBWRADDRL12.BRAM_CASCINTOP_ADDRBWRADDRU12 origin:060-bram-cascades !26_251 26_248 26_249
BRAM_R.BRAM_ADDRBWRADDRL12.BRAM_R_IMUX_ADDRBWRADDRL12 origin:060-bram-cascades !26_248 !26_249 !26_251
BRAM_R.BRAM_ADDRBWRADDRL13.BRAM_CASCINBOT_ADDRBWRADDRU13 origin:060-bram-cascades !26_137 26_136 26_139
BRAM_R.BRAM_ADDRBWRADDRL13.BRAM_CASCINTOP_ADDRBWRADDRU13 origin:060-bram-cascades !26_139 26_136 26_137
BRAM_R.BRAM_ADDRBWRADDRL13.BRAM_R_IMUX_ADDRBWRADDRL13 origin:060-bram-cascades !26_136 !26_137 !26_139
BRAM_R.BRAM_ADDRBWRADDRL14.BRAM_CASCINBOT_ADDRBWRADDRU14 origin:060-bram-cascades !26_265 26_264 26_267
BRAM_R.BRAM_ADDRBWRADDRL14.BRAM_CASCINTOP_ADDRBWRADDRU14 origin:060-bram-cascades !26_267 26_264 26_265
BRAM_R.BRAM_ADDRBWRADDRL14.BRAM_R_IMUX_ADDRBWRADDRL14 origin:060-bram-cascades !26_264 !26_265 !26_267
BRAM_R.BRAM_ADDRBWRADDRL2.BRAM_CASCINBOT_ADDRBWRADDRU2 origin:060-bram-cascades !26_73 26_72 26_75
BRAM_R.BRAM_ADDRBWRADDRL2.BRAM_CASCINTOP_ADDRBWRADDRU2 origin:060-bram-cascades !26_75 26_72 26_73
BRAM_R.BRAM_ADDRBWRADDRL2.BRAM_R_IMUX_ADDRBWRADDRL2 origin:060-bram-cascades !26_72 !26_73 !26_75
BRAM_R.BRAM_ADDRBWRADDRL3.BRAM_CASCINBOT_ADDRBWRADDRU3 origin:060-bram-cascades !26_201 26_200 26_203
BRAM_R.BRAM_ADDRBWRADDRL3.BRAM_CASCINTOP_ADDRBWRADDRU3 origin:060-bram-cascades !26_203 26_200 26_201
BRAM_R.BRAM_ADDRBWRADDRL3.BRAM_R_IMUX_ADDRBWRADDRL3 origin:060-bram-cascades !26_200 !26_201 !26_203
BRAM_R.BRAM_ADDRBWRADDRL4.BRAM_CASCINBOT_ADDRBWRADDRU4 origin:060-bram-cascades !26_105 26_104 26_107
BRAM_R.BRAM_ADDRBWRADDRL4.BRAM_CASCINTOP_ADDRBWRADDRU4 origin:060-bram-cascades !26_107 26_104 26_105
BRAM_R.BRAM_ADDRBWRADDRL4.BRAM_R_IMUX_ADDRBWRADDRL4 origin:060-bram-cascades !26_104 !26_105 !26_107
BRAM_R.BRAM_ADDRBWRADDRL5.BRAM_CASCINBOT_ADDRBWRADDRU5 origin:060-bram-cascades !26_233 26_232 26_235
BRAM_R.BRAM_ADDRBWRADDRL5.BRAM_CASCINTOP_ADDRBWRADDRU5 origin:060-bram-cascades !26_235 26_232 26_233
BRAM_R.BRAM_ADDRBWRADDRL5.BRAM_R_IMUX_ADDRBWRADDRL5 origin:060-bram-cascades !26_232 !26_233 !26_235
BRAM_R.BRAM_ADDRBWRADDRL6.BRAM_CASCINBOT_ADDRBWRADDRU6 origin:060-bram-cascades !26_169 26_168 26_171
BRAM_R.BRAM_ADDRBWRADDRL6.BRAM_CASCINTOP_ADDRBWRADDRU6 origin:060-bram-cascades !26_171 26_168 26_169
BRAM_R.BRAM_ADDRBWRADDRL6.BRAM_R_IMUX_ADDRBWRADDRL6 origin:060-bram-cascades !26_168 !26_169 !26_171
BRAM_R.BRAM_ADDRBWRADDRL7.BRAM_CASCINBOT_ADDRBWRADDRU7 origin:060-bram-cascades !26_185 26_184 26_187
BRAM_R.BRAM_ADDRBWRADDRL7.BRAM_CASCINTOP_ADDRBWRADDRU7 origin:060-bram-cascades !26_187 26_184 26_185
BRAM_R.BRAM_ADDRBWRADDRL7.BRAM_R_IMUX_ADDRBWRADDRL7 origin:060-bram-cascades !26_184 !26_185 !26_187
BRAM_R.BRAM_ADDRBWRADDRL8.BRAM_CASCINBOT_ADDRBWRADDRU8 origin:060-bram-cascades !26_89 26_88 26_91
BRAM_R.BRAM_ADDRBWRADDRL8.BRAM_CASCINTOP_ADDRBWRADDRU8 origin:060-bram-cascades !26_91 26_88 26_89
BRAM_R.BRAM_ADDRBWRADDRL8.BRAM_R_IMUX_ADDRBWRADDRL8 origin:060-bram-cascades !26_88 !26_89 !26_91
BRAM_R.BRAM_ADDRBWRADDRL9.BRAM_CASCINBOT_ADDRBWRADDRU9 origin:060-bram-cascades !26_217 26_216 26_219
BRAM_R.BRAM_ADDRBWRADDRL9.BRAM_CASCINTOP_ADDRBWRADDRU9 origin:060-bram-cascades !26_219 26_216 26_217
BRAM_R.BRAM_ADDRBWRADDRL9.BRAM_R_IMUX_ADDRBWRADDRL9 origin:060-bram-cascades !26_216 !26_217 !26_219
BRAM_R.BRAM_ADDRBWRADDRU0.BRAM_CASCINBOT_ADDRBWRADDRU0 origin:060-bram-cascades !26_46 26_45 26_47
BRAM_R.BRAM_ADDRBWRADDRU0.BRAM_CASCINTOP_ADDRBWRADDRU0 origin:060-bram-cascades !26_45 26_46 26_47
BRAM_R.BRAM_ADDRBWRADDRU0.BRAM_R_IMUX_ADDRBWRADDRU0 origin:060-bram-cascades !26_45 !26_46 !26_47
BRAM_R.BRAM_ADDRBWRADDRU1.BRAM_CASCINBOT_ADDRBWRADDRU1 origin:060-bram-cascades !26_62 26_61 26_63
BRAM_R.BRAM_ADDRBWRADDRU1.BRAM_CASCINTOP_ADDRBWRADDRU1 origin:060-bram-cascades !26_61 26_62 26_63
BRAM_R.BRAM_ADDRBWRADDRU1.BRAM_R_IMUX_ADDRBWRADDRU1 origin:060-bram-cascades !26_61 !26_62 !26_63
BRAM_R.BRAM_ADDRBWRADDRU10.BRAM_CASCINBOT_ADDRBWRADDRU10 origin:060-bram-cascades !26_158 26_157 26_159
BRAM_R.BRAM_ADDRBWRADDRU10.BRAM_CASCINTOP_ADDRBWRADDRU10 origin:060-bram-cascades !26_157 26_158 26_159
BRAM_R.BRAM_ADDRBWRADDRU10.BRAM_R_IMUX_ADDRBWRADDRU10 origin:060-bram-cascades !26_157 !26_158 !26_159
BRAM_R.BRAM_ADDRBWRADDRU11.BRAM_CASCINBOT_ADDRBWRADDRU11 origin:060-bram-cascades !26_126 26_125 26_127
BRAM_R.BRAM_ADDRBWRADDRU11.BRAM_CASCINTOP_ADDRBWRADDRU11 origin:060-bram-cascades !26_125 26_126 26_127
BRAM_R.BRAM_ADDRBWRADDRU11.BRAM_R_IMUX_ADDRBWRADDRU11 origin:060-bram-cascades !26_125 !26_126 !26_127
BRAM_R.BRAM_ADDRBWRADDRU12.BRAM_CASCINBOT_ADDRBWRADDRU12 origin:060-bram-cascades !26_254 26_253 26_255
BRAM_R.BRAM_ADDRBWRADDRU12.BRAM_CASCINTOP_ADDRBWRADDRU12 origin:060-bram-cascades !26_253 26_254 26_255
BRAM_R.BRAM_ADDRBWRADDRU12.BRAM_R_IMUX_ADDRBWRADDRU12 origin:060-bram-cascades !26_253 !26_254 !26_255
BRAM_R.BRAM_ADDRBWRADDRU13.BRAM_CASCINBOT_ADDRBWRADDRU13 origin:060-bram-cascades !26_142 26_141 26_143
BRAM_R.BRAM_ADDRBWRADDRU13.BRAM_CASCINTOP_ADDRBWRADDRU13 origin:060-bram-cascades !26_141 26_142 26_143
BRAM_R.BRAM_ADDRBWRADDRU13.BRAM_R_IMUX_ADDRBWRADDRU13 origin:060-bram-cascades !26_141 !26_142 !26_143
BRAM_R.BRAM_ADDRBWRADDRU14.BRAM_CASCINBOT_ADDRBWRADDRU14 origin:060-bram-cascades !26_270 26_269 26_271
BRAM_R.BRAM_ADDRBWRADDRU14.BRAM_CASCINTOP_ADDRBWRADDRU14 origin:060-bram-cascades !26_269 26_270 26_271
BRAM_R.BRAM_ADDRBWRADDRU14.BRAM_R_IMUX_ADDRBWRADDRU14 origin:060-bram-cascades !26_269 !26_270 !26_271
BRAM_R.BRAM_ADDRBWRADDRU2.BRAM_CASCINBOT_ADDRBWRADDRU2 origin:060-bram-cascades !26_78 26_77 26_79
BRAM_R.BRAM_ADDRBWRADDRU2.BRAM_CASCINTOP_ADDRBWRADDRU2 origin:060-bram-cascades !26_77 26_78 26_79
BRAM_R.BRAM_ADDRBWRADDRU2.BRAM_R_IMUX_ADDRBWRADDRU2 origin:060-bram-cascades !26_77 !26_78 !26_79
BRAM_R.BRAM_ADDRBWRADDRU3.BRAM_CASCINBOT_ADDRBWRADDRU3 origin:060-bram-cascades !26_206 26_205 26_207
BRAM_R.BRAM_ADDRBWRADDRU3.BRAM_CASCINTOP_ADDRBWRADDRU3 origin:060-bram-cascades !26_205 26_206 26_207
BRAM_R.BRAM_ADDRBWRADDRU3.BRAM_R_IMUX_ADDRBWRADDRU3 origin:060-bram-cascades !26_205 !26_206 !26_207
BRAM_R.BRAM_ADDRBWRADDRU4.BRAM_CASCINBOT_ADDRBWRADDRU4 origin:060-bram-cascades !26_110 26_109 26_111
BRAM_R.BRAM_ADDRBWRADDRU4.BRAM_CASCINTOP_ADDRBWRADDRU4 origin:060-bram-cascades !26_109 26_110 26_111
BRAM_R.BRAM_ADDRBWRADDRU4.BRAM_R_IMUX_ADDRBWRADDRU4 origin:060-bram-cascades !26_109 !26_110 !26_111
BRAM_R.BRAM_ADDRBWRADDRU5.BRAM_CASCINBOT_ADDRBWRADDRU5 origin:060-bram-cascades !26_238 26_237 26_239
BRAM_R.BRAM_ADDRBWRADDRU5.BRAM_CASCINTOP_ADDRBWRADDRU5 origin:060-bram-cascades !26_237 26_238 26_239
BRAM_R.BRAM_ADDRBWRADDRU5.BRAM_R_IMUX_ADDRBWRADDRU5 origin:060-bram-cascades !26_237 !26_238 !26_239
BRAM_R.BRAM_ADDRBWRADDRU6.BRAM_CASCINBOT_ADDRBWRADDRU6 origin:060-bram-cascades !26_174 26_173 26_175
BRAM_R.BRAM_ADDRBWRADDRU6.BRAM_CASCINTOP_ADDRBWRADDRU6 origin:060-bram-cascades !26_173 26_174 26_175
BRAM_R.BRAM_ADDRBWRADDRU6.BRAM_R_IMUX_ADDRBWRADDRU6 origin:060-bram-cascades !26_173 !26_174 !26_175
BRAM_R.BRAM_ADDRBWRADDRU7.BRAM_CASCINBOT_ADDRBWRADDRU7 origin:060-bram-cascades !26_190 26_189 26_191
BRAM_R.BRAM_ADDRBWRADDRU7.BRAM_CASCINTOP_ADDRBWRADDRU7 origin:060-bram-cascades !26_189 26_190 26_191
BRAM_R.BRAM_ADDRBWRADDRU7.BRAM_R_IMUX_ADDRBWRADDRU7 origin:060-bram-cascades !26_189 !26_190 !26_191
BRAM_R.BRAM_ADDRBWRADDRU8.BRAM_CASCINBOT_ADDRBWRADDRU8 origin:060-bram-cascades !26_94 26_93 26_95
BRAM_R.BRAM_ADDRBWRADDRU8.BRAM_CASCINTOP_ADDRBWRADDRU8 origin:060-bram-cascades !26_93 26_94 26_95
BRAM_R.BRAM_ADDRBWRADDRU8.BRAM_R_IMUX_ADDRBWRADDRU8 origin:060-bram-cascades !26_93 !26_94 !26_95
BRAM_R.BRAM_ADDRBWRADDRU9.BRAM_CASCINBOT_ADDRBWRADDRU9 origin:060-bram-cascades !26_222 26_221 26_223
BRAM_R.BRAM_ADDRBWRADDRU9.BRAM_CASCINTOP_ADDRBWRADDRU9 origin:060-bram-cascades !26_221 26_222 26_223
BRAM_R.BRAM_ADDRBWRADDRU9.BRAM_R_IMUX_ADDRBWRADDRU9 origin:060-bram-cascades !26_221 !26_222 !26_223
BRAM_R.CASCOUT_ARD_ACTIVE origin:060-bram-cascades 26_170
BRAM_R.CASCOUT_BWR_ACTIVE origin:060-bram-cascades 26_172
BRAM_R.EN_SYN origin:028-fifo-config 27_171
BRAM_R.FIRST_WORD_FALL_THROUGH origin:028-fifo-config 27_170
BRAM_R.RAMB18_Y0.DOA_REG origin:025-bram-config 27_69
BRAM_R.RAMB18_Y0.DOB_REG origin:025-bram-config 27_72
BRAM_R.RAMB18_Y0.FIFO_MODE origin:029-bram-fifo-config 27_150
BRAM_R.RAMB18_Y0.IN_USE origin:029-bram-fifo-config 27_100 27_99
BRAM_R.RAMB18_Y0.RDADDR_COLLISION_HWCONFIG_DELAYED_WRITE origin:025-bram-config !27_96
BRAM_R.RAMB18_Y0.RDADDR_COLLISION_HWCONFIG_PERFORMANCE origin:025-bram-config 27_96
BRAM_R.RAMB18_Y0.READ_WIDTH_A_1 origin:025-bram-config !27_35 !27_36 !27_37
BRAM_R.RAMB18_Y0.READ_WIDTH_A_18 origin:025-bram-config !27_35 !27_36 27_37
BRAM_R.RAMB18_Y0.READ_WIDTH_A_2 origin:025-bram-config !27_36 !27_37 27_35
BRAM_R.RAMB18_Y0.READ_WIDTH_A_4 origin:025-bram-config !27_35 !27_37 27_36
BRAM_R.RAMB18_Y0.READ_WIDTH_A_9 origin:025-bram-config !27_37 27_35 27_36
BRAM_R.RAMB18_Y0.READ_WIDTH_B_1 origin:025-bram-config !27_43 !27_44 !27_45
BRAM_R.RAMB18_Y0.READ_WIDTH_B_18 origin:025-bram-config !27_43 !27_44 27_45
BRAM_R.RAMB18_Y0.READ_WIDTH_B_2 origin:025-bram-config !27_44 !27_45 27_43
BRAM_R.RAMB18_Y0.READ_WIDTH_B_4 origin:025-bram-config !27_43 !27_45 27_44
BRAM_R.RAMB18_Y0.READ_WIDTH_B_9 origin:025-bram-config !27_45 27_43 27_44
BRAM_R.RAMB18_Y0.RSTREG_PRIORITY_A_REGCE origin:025-bram-config 27_124
BRAM_R.RAMB18_Y0.RSTREG_PRIORITY_A_RSTREG origin:025-bram-config !27_124
BRAM_R.RAMB18_Y0.RSTREG_PRIORITY_B_REGCE origin:025-bram-config 27_125
BRAM_R.RAMB18_Y0.RSTREG_PRIORITY_B_RSTREG origin:025-bram-config !27_125
BRAM_R.RAMB18_Y0.SDP_READ_WIDTH_36 origin:025-bram-config 27_48
BRAM_R.RAMB18_Y0.SDP_WRITE_WIDTH_36 origin:025-bram-config 27_40
BRAM_R.RAMB18_Y0.WRITE_MODE_A_NO_CHANGE origin:025-bram-config 27_64
BRAM_R.RAMB18_Y0.WRITE_MODE_A_READ_FIRST origin:025-bram-config 27_56
BRAM_R.RAMB18_Y0.WRITE_MODE_B_NO_CHANGE origin:025-bram-config 27_68
BRAM_R.RAMB18_Y0.WRITE_MODE_B_READ_FIRST origin:025-bram-config 27_67
BRAM_R.RAMB18_Y0.WRITE_WIDTH_A_1 origin:025-bram-config !27_51 !27_52 !27_53
BRAM_R.RAMB18_Y0.WRITE_WIDTH_A_18 origin:025-bram-config !27_51 !27_52 27_53
BRAM_R.RAMB18_Y0.WRITE_WIDTH_A_2 origin:025-bram-config !27_52 !27_53 27_51
BRAM_R.RAMB18_Y0.WRITE_WIDTH_A_4 origin:025-bram-config !27_51 !27_53 27_52
BRAM_R.RAMB18_Y0.WRITE_WIDTH_A_9 origin:025-bram-config !27_53 27_51 27_52
BRAM_R.RAMB18_Y0.WRITE_WIDTH_B_1 origin:025-bram-config !27_59 !27_60 !27_61
BRAM_R.RAMB18_Y0.WRITE_WIDTH_B_18 origin:025-bram-config !27_59 !27_60 27_61
BRAM_R.RAMB18_Y0.WRITE_WIDTH_B_2 origin:025-bram-config !27_60 !27_61 27_59
BRAM_R.RAMB18_Y0.WRITE_WIDTH_B_4 origin:025-bram-config !27_59 !27_61 27_60
BRAM_R.RAMB18_Y0.WRITE_WIDTH_B_9 origin:025-bram-config !27_61 27_59 27_60
BRAM_R.RAMB18_Y0.ZINIT_A[0] origin:025-bram-config 27_73
BRAM_R.RAMB18_Y0.ZINIT_A[10] origin:025-bram-config 27_129
BRAM_R.RAMB18_Y0.ZINIT_A[11] origin:025-bram-config 27_113
BRAM_R.RAMB18_Y0.ZINIT_A[12] origin:025-bram-config 27_97
BRAM_R.RAMB18_Y0.ZINIT_A[13] origin:025-bram-config 27_81
BRAM_R.RAMB18_Y0.ZINIT_A[14] origin:025-bram-config 27_49
BRAM_R.RAMB18_Y0.ZINIT_A[15] origin:025-bram-config 27_33
BRAM_R.RAMB18_Y0.ZINIT_A[16] origin:025-bram-config 27_17
BRAM_R.RAMB18_Y0.ZINIT_A[17] origin:025-bram-config 27_01
BRAM_R.RAMB18_Y0.ZINIT_A[1] origin:025-bram-config 27_65
BRAM_R.RAMB18_Y0.ZINIT_A[2] origin:025-bram-config 27_137
BRAM_R.RAMB18_Y0.ZINIT_A[3] origin:025-bram-config 27_121
BRAM_R.RAMB18_Y0.ZINIT_A[4] origin:025-bram-config 27_105
BRAM_R.RAMB18_Y0.ZINIT_A[5] origin:025-bram-config 27_89
BRAM_R.RAMB18_Y0.ZINIT_A[6] origin:025-bram-config 27_57
BRAM_R.RAMB18_Y0.ZINIT_A[7] origin:025-bram-config 27_41
BRAM_R.RAMB18_Y0.ZINIT_A[8] origin:025-bram-config 27_25
BRAM_R.RAMB18_Y0.ZINIT_A[9] origin:025-bram-config 27_09
BRAM_R.RAMB18_Y0.ZINIT_B[0] origin:025-bram-config 27_79
BRAM_R.RAMB18_Y0.ZINIT_B[10] origin:025-bram-config 27_135
BRAM_R.RAMB18_Y0.ZINIT_B[11] origin:025-bram-config 27_119
BRAM_R.RAMB18_Y0.ZINIT_B[12] origin:025-bram-config 27_103
BRAM_R.RAMB18_Y0.ZINIT_B[13] origin:025-bram-config 27_87
BRAM_R.RAMB18_Y0.ZINIT_B[14] origin:025-bram-config 27_55
BRAM_R.RAMB18_Y0.ZINIT_B[15] origin:025-bram-config 27_39
BRAM_R.RAMB18_Y0.ZINIT_B[16] origin:025-bram-config 27_23
BRAM_R.RAMB18_Y0.ZINIT_B[17] origin:025-bram-config 27_07
BRAM_R.RAMB18_Y0.ZINIT_B[1] origin:025-bram-config 27_71
BRAM_R.RAMB18_Y0.ZINIT_B[2] origin:025-bram-config 27_143
BRAM_R.RAMB18_Y0.ZINIT_B[3] origin:025-bram-config 27_127
BRAM_R.RAMB18_Y0.ZINIT_B[4] origin:025-bram-config 27_111
BRAM_R.RAMB18_Y0.ZINIT_B[5] origin:025-bram-config 27_95
BRAM_R.RAMB18_Y0.ZINIT_B[6] origin:025-bram-config 27_63
BRAM_R.RAMB18_Y0.ZINIT_B[7] origin:025-bram-config 27_47
BRAM_R.RAMB18_Y0.ZINIT_B[8] origin:025-bram-config 27_31
BRAM_R.RAMB18_Y0.ZINIT_B[9] origin:025-bram-config 27_15
BRAM_R.RAMB18_Y0.ZINV_CLKARDCLK origin:025-bram-config 27_107
BRAM_R.RAMB18_Y0.ZINV_CLKBWRCLK origin:025-bram-config 27_109
BRAM_R.RAMB18_Y0.ZINV_ENARDEN origin:025-bram-config 27_112
BRAM_R.RAMB18_Y0.ZINV_ENBWREN origin:025-bram-config 27_115
BRAM_R.RAMB18_Y0.ZINV_REGCLKARDRCLK origin:025-bram-config 27_104
BRAM_R.RAMB18_Y0.ZINV_REGCLKB origin:025-bram-config 27_108
BRAM_R.RAMB18_Y0.ZINV_RSTRAMARSTRAM origin:025-bram-config 27_116
BRAM_R.RAMB18_Y0.ZINV_RSTRAMB origin:025-bram-config 27_117
BRAM_R.RAMB18_Y0.ZINV_RSTREGARSTREG origin:025-bram-config 27_120
BRAM_R.RAMB18_Y0.ZINV_RSTREGB origin:025-bram-config 27_123
BRAM_R.RAMB18_Y0.ZSRVAL_A[0] origin:025-bram-config 27_74
BRAM_R.RAMB18_Y0.ZSRVAL_A[10] origin:025-bram-config 27_130
BRAM_R.RAMB18_Y0.ZSRVAL_A[11] origin:025-bram-config 27_114
BRAM_R.RAMB18_Y0.ZSRVAL_A[12] origin:025-bram-config 27_98
BRAM_R.RAMB18_Y0.ZSRVAL_A[13] origin:025-bram-config 27_82
BRAM_R.RAMB18_Y0.ZSRVAL_A[14] origin:025-bram-config 27_50
BRAM_R.RAMB18_Y0.ZSRVAL_A[15] origin:025-bram-config 27_34
BRAM_R.RAMB18_Y0.ZSRVAL_A[16] origin:025-bram-config 27_18
BRAM_R.RAMB18_Y0.ZSRVAL_A[17] origin:025-bram-config 27_02
BRAM_R.RAMB18_Y0.ZSRVAL_A[1] origin:025-bram-config 27_66
BRAM_R.RAMB18_Y0.ZSRVAL_A[2] origin:025-bram-config 27_138
BRAM_R.RAMB18_Y0.ZSRVAL_A[3] origin:025-bram-config 27_122
BRAM_R.RAMB18_Y0.ZSRVAL_A[4] origin:025-bram-config 27_106
BRAM_R.RAMB18_Y0.ZSRVAL_A[5] origin:025-bram-config 27_90
BRAM_R.RAMB18_Y0.ZSRVAL_A[6] origin:025-bram-config 27_58
BRAM_R.RAMB18_Y0.ZSRVAL_A[7] origin:025-bram-config 27_42
BRAM_R.RAMB18_Y0.ZSRVAL_A[8] origin:025-bram-config 27_26
BRAM_R.RAMB18_Y0.ZSRVAL_A[9] origin:025-bram-config 27_10
BRAM_R.RAMB18_Y0.ZSRVAL_B[0] origin:025-bram-config 27_78
BRAM_R.RAMB18_Y0.ZSRVAL_B[10] origin:025-bram-config 27_134
BRAM_R.RAMB18_Y0.ZSRVAL_B[11] origin:025-bram-config 27_118
BRAM_R.RAMB18_Y0.ZSRVAL_B[12] origin:025-bram-config 27_102
BRAM_R.RAMB18_Y0.ZSRVAL_B[13] origin:025-bram-config 27_86
BRAM_R.RAMB18_Y0.ZSRVAL_B[14] origin:025-bram-config 27_54
BRAM_R.RAMB18_Y0.ZSRVAL_B[15] origin:025-bram-config 27_38
BRAM_R.RAMB18_Y0.ZSRVAL_B[16] origin:025-bram-config 27_22
BRAM_R.RAMB18_Y0.ZSRVAL_B[17] origin:025-bram-config 27_06
BRAM_R.RAMB18_Y0.ZSRVAL_B[1] origin:025-bram-config 27_70
BRAM_R.RAMB18_Y0.ZSRVAL_B[2] origin:025-bram-config 27_142
BRAM_R.RAMB18_Y0.ZSRVAL_B[3] origin:025-bram-config 27_126
BRAM_R.RAMB18_Y0.ZSRVAL_B[4] origin:025-bram-config 27_110
BRAM_R.RAMB18_Y0.ZSRVAL_B[5] origin:025-bram-config 27_94
BRAM_R.RAMB18_Y0.ZSRVAL_B[6] origin:025-bram-config 27_62
BRAM_R.RAMB18_Y0.ZSRVAL_B[7] origin:025-bram-config 27_46
BRAM_R.RAMB18_Y0.ZSRVAL_B[8] origin:025-bram-config 27_30
BRAM_R.RAMB18_Y0.ZSRVAL_B[9] origin:025-bram-config 27_14
BRAM_R.RAMB18_Y1.DOA_REG origin:025-bram-config 27_251
BRAM_R.RAMB18_Y1.DOB_REG origin:025-bram-config 27_248
BRAM_R.RAMB18_Y1.FIFO_MODE origin:029-bram-fifo-config 27_169
BRAM_R.RAMB18_Y1.IN_USE origin:029-bram-fifo-config 27_220 27_221
BRAM_R.RAMB18_Y1.RDADDR_COLLISION_HWCONFIG_DELAYED_WRITE origin:025-bram-config !27_224
BRAM_R.RAMB18_Y1.RDADDR_COLLISION_HWCONFIG_PERFORMANCE origin:025-bram-config 27_224
BRAM_R.RAMB18_Y1.READ_WIDTH_A_1 origin:025-bram-config !27_283 !27_284 !27_285
BRAM_R.RAMB18_Y1.READ_WIDTH_A_18 origin:025-bram-config !27_284 !27_285 27_283
BRAM_R.RAMB18_Y1.READ_WIDTH_A_2 origin:025-bram-config !27_283 !27_284 27_285
BRAM_R.RAMB18_Y1.READ_WIDTH_A_4 origin:025-bram-config !27_283 !27_285 27_284
BRAM_R.RAMB18_Y1.READ_WIDTH_A_9 origin:025-bram-config !27_283 27_284 27_285
BRAM_R.RAMB18_Y1.READ_WIDTH_B_1 origin:025-bram-config !27_275 !27_276 !27_277
BRAM_R.RAMB18_Y1.READ_WIDTH_B_18 origin:025-bram-config !27_276 !27_277 27_275
BRAM_R.RAMB18_Y1.READ_WIDTH_B_2 origin:025-bram-config !27_275 !27_276 27_277
BRAM_R.RAMB18_Y1.READ_WIDTH_B_4 origin:025-bram-config !27_275 !27_277 27_276
BRAM_R.RAMB18_Y1.READ_WIDTH_B_9 origin:025-bram-config !27_275 27_276 27_277
BRAM_R.RAMB18_Y1.RSTREG_PRIORITY_A_REGCE origin:025-bram-config 27_196
BRAM_R.RAMB18_Y1.RSTREG_PRIORITY_A_RSTREG origin:025-bram-config !27_196
BRAM_R.RAMB18_Y1.RSTREG_PRIORITY_B_REGCE origin:025-bram-config 27_195
BRAM_R.RAMB18_Y1.RSTREG_PRIORITY_B_RSTREG origin:025-bram-config !27_195
BRAM_R.RAMB18_Y1.SDP_READ_WIDTH_36 origin:025-bram-config 27_272
BRAM_R.RAMB18_Y1.SDP_WRITE_WIDTH_36 origin:025-bram-config 27_280
BRAM_R.RAMB18_Y1.WRITE_MODE_A_NO_CHANGE origin:025-bram-config 27_256
BRAM_R.RAMB18_Y1.WRITE_MODE_A_READ_FIRST origin:025-bram-config 27_264
BRAM_R.RAMB18_Y1.WRITE_MODE_B_NO_CHANGE origin:025-bram-config 27_252
BRAM_R.RAMB18_Y1.WRITE_MODE_B_READ_FIRST origin:025-bram-config 27_253
BRAM_R.RAMB18_Y1.WRITE_WIDTH_A_1 origin:025-bram-config !27_267 !27_268 !27_269
BRAM_R.RAMB18_Y1.WRITE_WIDTH_A_18 origin:025-bram-config !27_268 !27_269 27_267
BRAM_R.RAMB18_Y1.WRITE_WIDTH_A_2 origin:025-bram-config !27_267 !27_268 27_269
BRAM_R.RAMB18_Y1.WRITE_WIDTH_A_4 origin:025-bram-config !27_267 !27_269 27_268
BRAM_R.RAMB18_Y1.WRITE_WIDTH_A_9 origin:025-bram-config !27_267 27_268 27_269
BRAM_R.RAMB18_Y1.WRITE_WIDTH_B_1 origin:025-bram-config !27_259 !27_260 !27_261
BRAM_R.RAMB18_Y1.WRITE_WIDTH_B_18 origin:025-bram-config !27_260 !27_261 27_259
BRAM_R.RAMB18_Y1.WRITE_WIDTH_B_2 origin:025-bram-config !27_259 !27_260 27_261
BRAM_R.RAMB18_Y1.WRITE_WIDTH_B_4 origin:025-bram-config !27_259 !27_261 27_260
BRAM_R.RAMB18_Y1.WRITE_WIDTH_B_9 origin:025-bram-config !27_259 27_260 27_261
BRAM_R.RAMB18_Y1.ZINIT_A[0] origin:025-bram-config 27_249
BRAM_R.RAMB18_Y1.ZINIT_A[10] origin:025-bram-config 27_305
BRAM_R.RAMB18_Y1.ZINIT_A[11] origin:025-bram-config 27_289
BRAM_R.RAMB18_Y1.ZINIT_A[12] origin:025-bram-config 27_273
BRAM_R.RAMB18_Y1.ZINIT_A[13] origin:025-bram-config 27_257
BRAM_R.RAMB18_Y1.ZINIT_A[14] origin:025-bram-config 27_225
BRAM_R.RAMB18_Y1.ZINIT_A[15] origin:025-bram-config 27_209
BRAM_R.RAMB18_Y1.ZINIT_A[16] origin:025-bram-config 27_193
BRAM_R.RAMB18_Y1.ZINIT_A[17] origin:025-bram-config 27_177
BRAM_R.RAMB18_Y1.ZINIT_A[1] origin:025-bram-config 27_241
BRAM_R.RAMB18_Y1.ZINIT_A[2] origin:025-bram-config 27_313
BRAM_R.RAMB18_Y1.ZINIT_A[3] origin:025-bram-config 27_297
BRAM_R.RAMB18_Y1.ZINIT_A[4] origin:025-bram-config 27_281
BRAM_R.RAMB18_Y1.ZINIT_A[5] origin:025-bram-config 27_265
BRAM_R.RAMB18_Y1.ZINIT_A[6] origin:025-bram-config 27_233
BRAM_R.RAMB18_Y1.ZINIT_A[7] origin:025-bram-config 27_217
BRAM_R.RAMB18_Y1.ZINIT_A[8] origin:025-bram-config 27_201
BRAM_R.RAMB18_Y1.ZINIT_A[9] origin:025-bram-config 27_185
BRAM_R.RAMB18_Y1.ZINIT_B[0] origin:025-bram-config 27_255
BRAM_R.RAMB18_Y1.ZINIT_B[10] origin:025-bram-config 27_311
BRAM_R.RAMB18_Y1.ZINIT_B[11] origin:025-bram-config 27_295
BRAM_R.RAMB18_Y1.ZINIT_B[12] origin:025-bram-config 27_279
BRAM_R.RAMB18_Y1.ZINIT_B[13] origin:025-bram-config 27_263
BRAM_R.RAMB18_Y1.ZINIT_B[14] origin:025-bram-config 27_231
BRAM_R.RAMB18_Y1.ZINIT_B[15] origin:025-bram-config 27_215
BRAM_R.RAMB18_Y1.ZINIT_B[16] origin:025-bram-config 27_199
BRAM_R.RAMB18_Y1.ZINIT_B[17] origin:025-bram-config 27_183
BRAM_R.RAMB18_Y1.ZINIT_B[1] origin:025-bram-config 27_247
BRAM_R.RAMB18_Y1.ZINIT_B[2] origin:025-bram-config 27_319
BRAM_R.RAMB18_Y1.ZINIT_B[3] origin:025-bram-config 27_303
BRAM_R.RAMB18_Y1.ZINIT_B[4] origin:025-bram-config 27_287
BRAM_R.RAMB18_Y1.ZINIT_B[5] origin:025-bram-config 27_271
BRAM_R.RAMB18_Y1.ZINIT_B[6] origin:025-bram-config 27_239
BRAM_R.RAMB18_Y1.ZINIT_B[7] origin:025-bram-config 27_223
BRAM_R.RAMB18_Y1.ZINIT_B[8] origin:025-bram-config 27_207
BRAM_R.RAMB18_Y1.ZINIT_B[9] origin:025-bram-config 27_191
BRAM_R.RAMB18_Y1.ZINV_CLKARDCLK origin:025-bram-config 27_213
BRAM_R.RAMB18_Y1.ZINV_CLKBWRCLK origin:025-bram-config 27_211
BRAM_R.RAMB18_Y1.ZINV_ENARDEN origin:025-bram-config 27_208
BRAM_R.RAMB18_Y1.ZINV_ENBWREN origin:025-bram-config 27_205
BRAM_R.RAMB18_Y1.ZINV_REGCLKARDRCLK origin:025-bram-config 27_216
BRAM_R.RAMB18_Y1.ZINV_REGCLKB origin:025-bram-config 27_212
BRAM_R.RAMB18_Y1.ZINV_RSTRAMARSTRAM origin:025-bram-config 27_204
BRAM_R.RAMB18_Y1.ZINV_RSTRAMB origin:025-bram-config 27_203
BRAM_R.RAMB18_Y1.ZINV_RSTREGARSTREG origin:025-bram-config 27_200
BRAM_R.RAMB18_Y1.ZINV_RSTREGB origin:025-bram-config 27_197
BRAM_R.RAMB18_Y1.ZSRVAL_A[0] origin:025-bram-config 27_250
BRAM_R.RAMB18_Y1.ZSRVAL_A[10] origin:025-bram-config 27_306
BRAM_R.RAMB18_Y1.ZSRVAL_A[11] origin:025-bram-config 27_290
BRAM_R.RAMB18_Y1.ZSRVAL_A[12] origin:025-bram-config 27_274
BRAM_R.RAMB18_Y1.ZSRVAL_A[13] origin:025-bram-config 27_258
BRAM_R.RAMB18_Y1.ZSRVAL_A[14] origin:025-bram-config 27_226
BRAM_R.RAMB18_Y1.ZSRVAL_A[15] origin:025-bram-config 27_210
BRAM_R.RAMB18_Y1.ZSRVAL_A[16] origin:025-bram-config 27_194
BRAM_R.RAMB18_Y1.ZSRVAL_A[17] origin:025-bram-config 27_178
BRAM_R.RAMB18_Y1.ZSRVAL_A[1] origin:025-bram-config 27_242
BRAM_R.RAMB18_Y1.ZSRVAL_A[2] origin:025-bram-config 27_314
BRAM_R.RAMB18_Y1.ZSRVAL_A[3] origin:025-bram-config 27_298
BRAM_R.RAMB18_Y1.ZSRVAL_A[4] origin:025-bram-config 27_282
BRAM_R.RAMB18_Y1.ZSRVAL_A[5] origin:025-bram-config 27_266
BRAM_R.RAMB18_Y1.ZSRVAL_A[6] origin:025-bram-config 27_234
BRAM_R.RAMB18_Y1.ZSRVAL_A[7] origin:025-bram-config 27_218
BRAM_R.RAMB18_Y1.ZSRVAL_A[8] origin:025-bram-config 27_202
BRAM_R.RAMB18_Y1.ZSRVAL_A[9] origin:025-bram-config 27_186
BRAM_R.RAMB18_Y1.ZSRVAL_B[0] origin:025-bram-config 27_254
BRAM_R.RAMB18_Y1.ZSRVAL_B[10] origin:025-bram-config 27_310
BRAM_R.RAMB18_Y1.ZSRVAL_B[11] origin:025-bram-config 27_294
BRAM_R.RAMB18_Y1.ZSRVAL_B[12] origin:025-bram-config 27_278
BRAM_R.RAMB18_Y1.ZSRVAL_B[13] origin:025-bram-config 27_262
BRAM_R.RAMB18_Y1.ZSRVAL_B[14] origin:025-bram-config 27_230
BRAM_R.RAMB18_Y1.ZSRVAL_B[15] origin:025-bram-config 27_214
BRAM_R.RAMB18_Y1.ZSRVAL_B[16] origin:025-bram-config 27_198
BRAM_R.RAMB18_Y1.ZSRVAL_B[17] origin:025-bram-config 27_182
BRAM_R.RAMB18_Y1.ZSRVAL_B[1] origin:025-bram-config 27_246
BRAM_R.RAMB18_Y1.ZSRVAL_B[2] origin:025-bram-config 27_318
BRAM_R.RAMB18_Y1.ZSRVAL_B[3] origin:025-bram-config 27_302
BRAM_R.RAMB18_Y1.ZSRVAL_B[4] origin:025-bram-config 27_286
BRAM_R.RAMB18_Y1.ZSRVAL_B[5] origin:025-bram-config 27_270
BRAM_R.RAMB18_Y1.ZSRVAL_B[6] origin:025-bram-config 27_238
BRAM_R.RAMB18_Y1.ZSRVAL_B[7] origin:025-bram-config 27_222
BRAM_R.RAMB18_Y1.ZSRVAL_B[8] origin:025-bram-config 27_206
BRAM_R.RAMB18_Y1.ZSRVAL_B[9] origin:025-bram-config 27_190
BRAM_R.RAMB36.EN_ECC_READ origin:027-bram36-config 27_175
BRAM_R.RAMB36.EN_ECC_WRITE origin:027-bram36-config 27_162
BRAM_R.RAMB36.RAM_EXTENSION_A_LOWER origin:027-bram36-config 27_188
BRAM_R.RAMB36.RAM_EXTENSION_A_NONE_OR_UPPER origin:027-bram36-config !27_188
BRAM_R.RAMB36.RAM_EXTENSION_B_LOWER origin:027-bram36-config 27_187
BRAM_R.RAMB36.RAM_EXTENSION_B_NONE_OR_UPPER origin:027-bram36-config !27_187
BRAM_R.ZALMOST_EMPTY_OFFSET[0] origin:028-fifo-config 27_288
BRAM_R.ZALMOST_EMPTY_OFFSET[10] origin:028-fifo-config 27_308
BRAM_R.ZALMOST_EMPTY_OFFSET[11] origin:028-fifo-config 27_309
BRAM_R.ZALMOST_EMPTY_OFFSET[12] origin:028-fifo-config 27_312
BRAM_R.ZALMOST_EMPTY_OFFSET[1] origin:028-fifo-config 27_291
BRAM_R.ZALMOST_EMPTY_OFFSET[2] origin:028-fifo-config 27_292
BRAM_R.ZALMOST_EMPTY_OFFSET[3] origin:028-fifo-config 27_293
BRAM_R.ZALMOST_EMPTY_OFFSET[4] origin:028-fifo-config 27_296
BRAM_R.ZALMOST_EMPTY_OFFSET[5] origin:028-fifo-config 27_299
BRAM_R.ZALMOST_EMPTY_OFFSET[6] origin:028-fifo-config 27_300
BRAM_R.ZALMOST_EMPTY_OFFSET[7] origin:028-fifo-config 27_301
BRAM_R.ZALMOST_EMPTY_OFFSET[8] origin:028-fifo-config 27_304
BRAM_R.ZALMOST_EMPTY_OFFSET[9] origin:028-fifo-config 27_307
BRAM_R.ZALMOST_FULL_OFFSET[0] origin:028-fifo-config 27_32
BRAM_R.ZALMOST_FULL_OFFSET[10] origin:028-fifo-config 27_12
BRAM_R.ZALMOST_FULL_OFFSET[11] origin:028-fifo-config 27_11
BRAM_R.ZALMOST_FULL_OFFSET[12] origin:028-fifo-config 27_08
BRAM_R.ZALMOST_FULL_OFFSET[1] origin:028-fifo-config 27_29
BRAM_R.ZALMOST_FULL_OFFSET[2] origin:028-fifo-config 27_28
BRAM_R.ZALMOST_FULL_OFFSET[3] origin:028-fifo-config 27_27
BRAM_R.ZALMOST_FULL_OFFSET[4] origin:028-fifo-config 27_24
BRAM_R.ZALMOST_FULL_OFFSET[5] origin:028-fifo-config 27_21
BRAM_R.ZALMOST_FULL_OFFSET[6] origin:028-fifo-config 27_20
BRAM_R.ZALMOST_FULL_OFFSET[7] origin:028-fifo-config 27_19
BRAM_R.ZALMOST_FULL_OFFSET[8] origin:028-fifo-config 27_16
BRAM_R.ZALMOST_FULL_OFFSET[9] origin:028-fifo-config 27_13

678
zynq7/segbits_clbll_l.origin_info.db Normal file
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@ -0,0 +1,678 @@
CLBLL_L.SLICEL_X0.A5FF.ZINI origin:011-clb-ffconfig 31_06
CLBLL_L.SLICEL_X0.A5FF.ZRST origin:011-clb-ffconfig 01_07
CLBLL_L.SLICEL_X0.A5FFMUX.IN_A origin:012-clb-n5ffmux 30_09
CLBLL_L.SLICEL_X0.A5FFMUX.IN_B origin:012-clb-n5ffmux 30_10
CLBLL_L.SLICEL_X0.AFF.ZINI origin:011-clb-ffconfig 31_03
CLBLL_L.SLICEL_X0.AFF.ZRST origin:011-clb-ffconfig 30_12
CLBLL_L.SLICEL_X0.AFFMUX.AX origin:015-clb-nffmux !30_00 !30_02 !30_03 30_01
CLBLL_L.SLICEL_X0.AFFMUX.CY origin:015-clb-nffmux !30_01 !30_03 30_00 30_02
CLBLL_L.SLICEL_X0.AFFMUX.F7 origin:015-clb-nffmux !30_02 !30_03 30_00 30_01
CLBLL_L.SLICEL_X0.AFFMUX.O5 origin:015-clb-nffmux !30_01 !30_02 30_00 30_03
CLBLL_L.SLICEL_X0.AFFMUX.O6 origin:015-clb-nffmux !30_00 !30_01 !30_02 30_03
CLBLL_L.SLICEL_X0.AFFMUX.XOR origin:015-clb-nffmux !30_00 !30_01 !30_03 30_02
CLBLL_L.SLICEL_X0.ALUT.INIT[00] origin:010-clb-lutinit 32_15
CLBLL_L.SLICEL_X0.ALUT.INIT[01] origin:010-clb-lutinit 33_15
CLBLL_L.SLICEL_X0.ALUT.INIT[02] origin:010-clb-lutinit 32_14
CLBLL_L.SLICEL_X0.ALUT.INIT[03] origin:010-clb-lutinit 33_14
CLBLL_L.SLICEL_X0.ALUT.INIT[04] origin:010-clb-lutinit 32_13
CLBLL_L.SLICEL_X0.ALUT.INIT[05] origin:010-clb-lutinit 33_13
CLBLL_L.SLICEL_X0.ALUT.INIT[06] origin:010-clb-lutinit 32_12
CLBLL_L.SLICEL_X0.ALUT.INIT[07] origin:010-clb-lutinit 33_12
CLBLL_L.SLICEL_X0.ALUT.INIT[08] origin:010-clb-lutinit 35_15
CLBLL_L.SLICEL_X0.ALUT.INIT[09] origin:010-clb-lutinit 34_15
CLBLL_L.SLICEL_X0.ALUT.INIT[10] origin:010-clb-lutinit 35_14
CLBLL_L.SLICEL_X0.ALUT.INIT[11] origin:010-clb-lutinit 34_14
CLBLL_L.SLICEL_X0.ALUT.INIT[12] origin:010-clb-lutinit 35_13
CLBLL_L.SLICEL_X0.ALUT.INIT[13] origin:010-clb-lutinit 34_13
CLBLL_L.SLICEL_X0.ALUT.INIT[14] origin:010-clb-lutinit 35_12
CLBLL_L.SLICEL_X0.ALUT.INIT[15] origin:010-clb-lutinit 34_12
CLBLL_L.SLICEL_X0.ALUT.INIT[16] origin:010-clb-lutinit 32_11
CLBLL_L.SLICEL_X0.ALUT.INIT[17] origin:010-clb-lutinit 33_11
CLBLL_L.SLICEL_X0.ALUT.INIT[18] origin:010-clb-lutinit 32_10
CLBLL_L.SLICEL_X0.ALUT.INIT[19] origin:010-clb-lutinit 33_10
CLBLL_L.SLICEL_X0.ALUT.INIT[20] origin:010-clb-lutinit 32_09
CLBLL_L.SLICEL_X0.ALUT.INIT[21] origin:010-clb-lutinit 33_09
CLBLL_L.SLICEL_X0.ALUT.INIT[22] origin:010-clb-lutinit 32_08
CLBLL_L.SLICEL_X0.ALUT.INIT[23] origin:010-clb-lutinit 33_08
CLBLL_L.SLICEL_X0.ALUT.INIT[24] origin:010-clb-lutinit 35_11
CLBLL_L.SLICEL_X0.ALUT.INIT[25] origin:010-clb-lutinit 34_11
CLBLL_L.SLICEL_X0.ALUT.INIT[26] origin:010-clb-lutinit 35_10
CLBLL_L.SLICEL_X0.ALUT.INIT[27] origin:010-clb-lutinit 34_10
CLBLL_L.SLICEL_X0.ALUT.INIT[28] origin:010-clb-lutinit 35_09
CLBLL_L.SLICEL_X0.ALUT.INIT[29] origin:010-clb-lutinit 34_09
CLBLL_L.SLICEL_X0.ALUT.INIT[30] origin:010-clb-lutinit 35_08
CLBLL_L.SLICEL_X0.ALUT.INIT[31] origin:010-clb-lutinit 34_08
CLBLL_L.SLICEL_X0.ALUT.INIT[32] origin:010-clb-lutinit 32_07
CLBLL_L.SLICEL_X0.ALUT.INIT[33] origin:010-clb-lutinit 33_07
CLBLL_L.SLICEL_X0.ALUT.INIT[34] origin:010-clb-lutinit 32_06
CLBLL_L.SLICEL_X0.ALUT.INIT[35] origin:010-clb-lutinit 33_06
CLBLL_L.SLICEL_X0.ALUT.INIT[36] origin:010-clb-lutinit 32_05
CLBLL_L.SLICEL_X0.ALUT.INIT[37] origin:010-clb-lutinit 33_05
CLBLL_L.SLICEL_X0.ALUT.INIT[38] origin:010-clb-lutinit 32_04
CLBLL_L.SLICEL_X0.ALUT.INIT[39] origin:010-clb-lutinit 33_04
CLBLL_L.SLICEL_X0.ALUT.INIT[40] origin:010-clb-lutinit 35_07
CLBLL_L.SLICEL_X0.ALUT.INIT[41] origin:010-clb-lutinit 34_07
CLBLL_L.SLICEL_X0.ALUT.INIT[42] origin:010-clb-lutinit 35_06
CLBLL_L.SLICEL_X0.ALUT.INIT[43] origin:010-clb-lutinit 34_06
CLBLL_L.SLICEL_X0.ALUT.INIT[44] origin:010-clb-lutinit 35_05
CLBLL_L.SLICEL_X0.ALUT.INIT[45] origin:010-clb-lutinit 34_05
CLBLL_L.SLICEL_X0.ALUT.INIT[46] origin:010-clb-lutinit 35_04
CLBLL_L.SLICEL_X0.ALUT.INIT[47] origin:010-clb-lutinit 34_04
CLBLL_L.SLICEL_X0.ALUT.INIT[48] origin:010-clb-lutinit 32_03
CLBLL_L.SLICEL_X0.ALUT.INIT[49] origin:010-clb-lutinit 33_03
CLBLL_L.SLICEL_X0.ALUT.INIT[50] origin:010-clb-lutinit 32_02
CLBLL_L.SLICEL_X0.ALUT.INIT[51] origin:010-clb-lutinit 33_02
CLBLL_L.SLICEL_X0.ALUT.INIT[52] origin:010-clb-lutinit 32_01
CLBLL_L.SLICEL_X0.ALUT.INIT[53] origin:010-clb-lutinit 33_01
CLBLL_L.SLICEL_X0.ALUT.INIT[54] origin:010-clb-lutinit 32_00
CLBLL_L.SLICEL_X0.ALUT.INIT[55] origin:010-clb-lutinit 33_00
CLBLL_L.SLICEL_X0.ALUT.INIT[56] origin:010-clb-lutinit 35_03
CLBLL_L.SLICEL_X0.ALUT.INIT[57] origin:010-clb-lutinit 34_03
CLBLL_L.SLICEL_X0.ALUT.INIT[58] origin:010-clb-lutinit 35_02
CLBLL_L.SLICEL_X0.ALUT.INIT[59] origin:010-clb-lutinit 34_02
CLBLL_L.SLICEL_X0.ALUT.INIT[60] origin:010-clb-lutinit 35_01
CLBLL_L.SLICEL_X0.ALUT.INIT[61] origin:010-clb-lutinit 34_01
CLBLL_L.SLICEL_X0.ALUT.INIT[62] origin:010-clb-lutinit 35_00
CLBLL_L.SLICEL_X0.ALUT.INIT[63] origin:010-clb-lutinit 34_00
CLBLL_L.SLICEL_X0.AOUTMUX.A5Q origin:016-clb-noutmux !30_06 !30_08 !30_11 30_07
CLBLL_L.SLICEL_X0.AOUTMUX.CY origin:016-clb-noutmux !30_07 !30_11 30_06 30_08
CLBLL_L.SLICEL_X0.AOUTMUX.F7 origin:016-clb-noutmux !30_08 !30_11 30_06 30_07
CLBLL_L.SLICEL_X0.AOUTMUX.O5 origin:016-clb-noutmux !30_07 !30_08 30_06 30_11
CLBLL_L.SLICEL_X0.AOUTMUX.O6 origin:016-clb-noutmux !30_06 !30_07 !30_08 30_11
CLBLL_L.SLICEL_X0.AOUTMUX.XOR origin:016-clb-noutmux !30_06 !30_07 !30_11 30_08
CLBLL_L.SLICEL_X0.B5FF.ZINI origin:011-clb-ffconfig 31_22
CLBLL_L.SLICEL_X0.B5FF.ZRST origin:011-clb-ffconfig 01_19
CLBLL_L.SLICEL_X0.B5FFMUX.IN_A origin:012-clb-n5ffmux 30_19
CLBLL_L.SLICEL_X0.B5FFMUX.IN_B origin:012-clb-n5ffmux 30_18
CLBLL_L.SLICEL_X0.BFF.ZINI origin:011-clb-ffconfig 31_28
CLBLL_L.SLICEL_X0.BFF.ZRST origin:011-clb-ffconfig 30_30
CLBLL_L.SLICEL_X0.BFFMUX.BX origin:015-clb-nffmux !30_24 !30_25 !30_27 30_26
CLBLL_L.SLICEL_X0.BFFMUX.CY origin:015-clb-nffmux !30_24 !30_26 30_25 30_27
CLBLL_L.SLICEL_X0.BFFMUX.F8 origin:015-clb-nffmux !30_24 !30_25 30_26 30_27
CLBLL_L.SLICEL_X0.BFFMUX.O5 origin:015-clb-nffmux !30_25 !30_26 30_24 30_27
CLBLL_L.SLICEL_X0.BFFMUX.O6 origin:015-clb-nffmux !30_25 !30_26 !30_27 30_24
CLBLL_L.SLICEL_X0.BFFMUX.XOR origin:015-clb-nffmux !30_24 !30_26 !30_27 30_25
CLBLL_L.SLICEL_X0.BLUT.INIT[00] origin:010-clb-lutinit 32_31
CLBLL_L.SLICEL_X0.BLUT.INIT[01] origin:010-clb-lutinit 33_31
CLBLL_L.SLICEL_X0.BLUT.INIT[02] origin:010-clb-lutinit 32_30
CLBLL_L.SLICEL_X0.BLUT.INIT[03] origin:010-clb-lutinit 33_30
CLBLL_L.SLICEL_X0.BLUT.INIT[04] origin:010-clb-lutinit 32_29
CLBLL_L.SLICEL_X0.BLUT.INIT[05] origin:010-clb-lutinit 33_29
CLBLL_L.SLICEL_X0.BLUT.INIT[06] origin:010-clb-lutinit 32_28
CLBLL_L.SLICEL_X0.BLUT.INIT[07] origin:010-clb-lutinit 33_28
CLBLL_L.SLICEL_X0.BLUT.INIT[08] origin:010-clb-lutinit 35_31
CLBLL_L.SLICEL_X0.BLUT.INIT[09] origin:010-clb-lutinit 34_31
CLBLL_L.SLICEL_X0.BLUT.INIT[10] origin:010-clb-lutinit 35_30
CLBLL_L.SLICEL_X0.BLUT.INIT[11] origin:010-clb-lutinit 34_30
CLBLL_L.SLICEL_X0.BLUT.INIT[12] origin:010-clb-lutinit 35_29
CLBLL_L.SLICEL_X0.BLUT.INIT[13] origin:010-clb-lutinit 34_29
CLBLL_L.SLICEL_X0.BLUT.INIT[14] origin:010-clb-lutinit 35_28
CLBLL_L.SLICEL_X0.BLUT.INIT[15] origin:010-clb-lutinit 34_28
CLBLL_L.SLICEL_X0.BLUT.INIT[16] origin:010-clb-lutinit 32_27
CLBLL_L.SLICEL_X0.BLUT.INIT[17] origin:010-clb-lutinit 33_27
CLBLL_L.SLICEL_X0.BLUT.INIT[18] origin:010-clb-lutinit 32_26
CLBLL_L.SLICEL_X0.BLUT.INIT[19] origin:010-clb-lutinit 33_26
CLBLL_L.SLICEL_X0.BLUT.INIT[20] origin:010-clb-lutinit 32_25
CLBLL_L.SLICEL_X0.BLUT.INIT[21] origin:010-clb-lutinit 33_25
CLBLL_L.SLICEL_X0.BLUT.INIT[22] origin:010-clb-lutinit 32_24
CLBLL_L.SLICEL_X0.BLUT.INIT[23] origin:010-clb-lutinit 33_24
CLBLL_L.SLICEL_X0.BLUT.INIT[24] origin:010-clb-lutinit 35_27
CLBLL_L.SLICEL_X0.BLUT.INIT[25] origin:010-clb-lutinit 34_27
CLBLL_L.SLICEL_X0.BLUT.INIT[26] origin:010-clb-lutinit 35_26
CLBLL_L.SLICEL_X0.BLUT.INIT[27] origin:010-clb-lutinit 34_26
CLBLL_L.SLICEL_X0.BLUT.INIT[28] origin:010-clb-lutinit 35_25
CLBLL_L.SLICEL_X0.BLUT.INIT[29] origin:010-clb-lutinit 34_25
CLBLL_L.SLICEL_X0.BLUT.INIT[30] origin:010-clb-lutinit 35_24
CLBLL_L.SLICEL_X0.BLUT.INIT[31] origin:010-clb-lutinit 34_24
CLBLL_L.SLICEL_X0.BLUT.INIT[32] origin:010-clb-lutinit 32_23
CLBLL_L.SLICEL_X0.BLUT.INIT[33] origin:010-clb-lutinit 33_23
CLBLL_L.SLICEL_X0.BLUT.INIT[34] origin:010-clb-lutinit 32_22
CLBLL_L.SLICEL_X0.BLUT.INIT[35] origin:010-clb-lutinit 33_22
CLBLL_L.SLICEL_X0.BLUT.INIT[36] origin:010-clb-lutinit 32_21
CLBLL_L.SLICEL_X0.BLUT.INIT[37] origin:010-clb-lutinit 33_21
CLBLL_L.SLICEL_X0.BLUT.INIT[38] origin:010-clb-lutinit 32_20
CLBLL_L.SLICEL_X0.BLUT.INIT[39] origin:010-clb-lutinit 33_20
CLBLL_L.SLICEL_X0.BLUT.INIT[40] origin:010-clb-lutinit 35_23
CLBLL_L.SLICEL_X0.BLUT.INIT[41] origin:010-clb-lutinit 34_23
CLBLL_L.SLICEL_X0.BLUT.INIT[42] origin:010-clb-lutinit 35_22
CLBLL_L.SLICEL_X0.BLUT.INIT[43] origin:010-clb-lutinit 34_22
CLBLL_L.SLICEL_X0.BLUT.INIT[44] origin:010-clb-lutinit 35_21
CLBLL_L.SLICEL_X0.BLUT.INIT[45] origin:010-clb-lutinit 34_21
CLBLL_L.SLICEL_X0.BLUT.INIT[46] origin:010-clb-lutinit 35_20
CLBLL_L.SLICEL_X0.BLUT.INIT[47] origin:010-clb-lutinit 34_20
CLBLL_L.SLICEL_X0.BLUT.INIT[48] origin:010-clb-lutinit 32_19
CLBLL_L.SLICEL_X0.BLUT.INIT[49] origin:010-clb-lutinit 33_19
CLBLL_L.SLICEL_X0.BLUT.INIT[50] origin:010-clb-lutinit 32_18
CLBLL_L.SLICEL_X0.BLUT.INIT[51] origin:010-clb-lutinit 33_18
CLBLL_L.SLICEL_X0.BLUT.INIT[52] origin:010-clb-lutinit 32_17
CLBLL_L.SLICEL_X0.BLUT.INIT[53] origin:010-clb-lutinit 33_17
CLBLL_L.SLICEL_X0.BLUT.INIT[54] origin:010-clb-lutinit 32_16
CLBLL_L.SLICEL_X0.BLUT.INIT[55] origin:010-clb-lutinit 33_16
CLBLL_L.SLICEL_X0.BLUT.INIT[56] origin:010-clb-lutinit 35_19
CLBLL_L.SLICEL_X0.BLUT.INIT[57] origin:010-clb-lutinit 34_19
CLBLL_L.SLICEL_X0.BLUT.INIT[58] origin:010-clb-lutinit 35_18
CLBLL_L.SLICEL_X0.BLUT.INIT[59] origin:010-clb-lutinit 34_18
CLBLL_L.SLICEL_X0.BLUT.INIT[60] origin:010-clb-lutinit 35_17
CLBLL_L.SLICEL_X0.BLUT.INIT[61] origin:010-clb-lutinit 34_17
CLBLL_L.SLICEL_X0.BLUT.INIT[62] origin:010-clb-lutinit 35_16
CLBLL_L.SLICEL_X0.BLUT.INIT[63] origin:010-clb-lutinit 34_16
CLBLL_L.SLICEL_X0.BOUTMUX.B5Q origin:016-clb-noutmux !30_20 !30_21 !30_22 30_23
CLBLL_L.SLICEL_X0.BOUTMUX.CY origin:016-clb-noutmux !30_20 !30_23 30_21 30_22
CLBLL_L.SLICEL_X0.BOUTMUX.F8 origin:016-clb-noutmux !30_20 !30_21 30_22 30_23
CLBLL_L.SLICEL_X0.BOUTMUX.O5 origin:016-clb-noutmux !30_21 !30_23 30_20 30_22
CLBLL_L.SLICEL_X0.BOUTMUX.O6 origin:016-clb-noutmux !30_21 !30_22 !30_23 30_20
CLBLL_L.SLICEL_X0.BOUTMUX.XOR origin:016-clb-noutmux !30_20 !30_22 !30_23 30_21
CLBLL_L.SLICEL_X0.C5FF.ZINI origin:011-clb-ffconfig 31_41
CLBLL_L.SLICEL_X0.C5FF.ZRST origin:011-clb-ffconfig 01_47
CLBLL_L.SLICEL_X0.C5FFMUX.IN_A origin:012-clb-n5ffmux 31_45
CLBLL_L.SLICEL_X0.C5FFMUX.IN_B origin:012-clb-n5ffmux 30_39
CLBLL_L.SLICEL_X0.CARRY4.ACY0 origin:013-clb-ncy0 30_15
CLBLL_L.SLICEL_X0.CARRY4.BCY0 origin:013-clb-ncy0 01_15
CLBLL_L.SLICEL_X0.CARRY4.CCY0 origin:013-clb-ncy0 30_48
CLBLL_L.SLICEL_X0.CARRY4.DCY0 origin:013-clb-ncy0 30_49
CLBLL_L.SLICEL_X0.CEUSEDMUX origin:014-clb-ffsrcemux 01_39
CLBLL_L.SLICEL_X0.CFF.ZINI origin:011-clb-ffconfig 31_33
CLBLL_L.SLICEL_X0.CFF.ZRST origin:011-clb-ffconfig 30_33
CLBLL_L.SLICEL_X0.CFFMUX.CX origin:015-clb-nffmux !30_35 !30_37 !30_38 30_36
CLBLL_L.SLICEL_X0.CFFMUX.CY origin:015-clb-nffmux !30_36 !30_38 30_35 30_37
CLBLL_L.SLICEL_X0.CFFMUX.F7 origin:015-clb-nffmux !30_37 !30_38 30_35 30_36
CLBLL_L.SLICEL_X0.CFFMUX.O5 origin:015-clb-nffmux !30_36 !30_37 30_35 30_38
CLBLL_L.SLICEL_X0.CFFMUX.O6 origin:015-clb-nffmux !30_35 !30_36 !30_37 30_38
CLBLL_L.SLICEL_X0.CFFMUX.XOR origin:015-clb-nffmux !30_35 !30_36 !30_38 30_37
CLBLL_L.SLICEL_X0.CLKINV origin:011-clb-ffconfig 01_51
CLBLL_L.SLICEL_X0.CLUT.INIT[00] origin:010-clb-lutinit 32_47
CLBLL_L.SLICEL_X0.CLUT.INIT[01] origin:010-clb-lutinit 33_47
CLBLL_L.SLICEL_X0.CLUT.INIT[02] origin:010-clb-lutinit 32_46
CLBLL_L.SLICEL_X0.CLUT.INIT[03] origin:010-clb-lutinit 33_46
CLBLL_L.SLICEL_X0.CLUT.INIT[04] origin:010-clb-lutinit 32_45
CLBLL_L.SLICEL_X0.CLUT.INIT[05] origin:010-clb-lutinit 33_45
CLBLL_L.SLICEL_X0.CLUT.INIT[06] origin:010-clb-lutinit 32_44
CLBLL_L.SLICEL_X0.CLUT.INIT[07] origin:010-clb-lutinit 33_44
CLBLL_L.SLICEL_X0.CLUT.INIT[08] origin:010-clb-lutinit 35_47
CLBLL_L.SLICEL_X0.CLUT.INIT[09] origin:010-clb-lutinit 34_47
CLBLL_L.SLICEL_X0.CLUT.INIT[10] origin:010-clb-lutinit 35_46
CLBLL_L.SLICEL_X0.CLUT.INIT[11] origin:010-clb-lutinit 34_46
CLBLL_L.SLICEL_X0.CLUT.INIT[12] origin:010-clb-lutinit 35_45
CLBLL_L.SLICEL_X0.CLUT.INIT[13] origin:010-clb-lutinit 34_45
CLBLL_L.SLICEL_X0.CLUT.INIT[14] origin:010-clb-lutinit 35_44
CLBLL_L.SLICEL_X0.CLUT.INIT[15] origin:010-clb-lutinit 34_44
CLBLL_L.SLICEL_X0.CLUT.INIT[16] origin:010-clb-lutinit 32_43
CLBLL_L.SLICEL_X0.CLUT.INIT[17] origin:010-clb-lutinit 33_43
CLBLL_L.SLICEL_X0.CLUT.INIT[18] origin:010-clb-lutinit 32_42
CLBLL_L.SLICEL_X0.CLUT.INIT[19] origin:010-clb-lutinit 33_42
CLBLL_L.SLICEL_X0.CLUT.INIT[20] origin:010-clb-lutinit 32_41
CLBLL_L.SLICEL_X0.CLUT.INIT[21] origin:010-clb-lutinit 33_41
CLBLL_L.SLICEL_X0.CLUT.INIT[22] origin:010-clb-lutinit 32_40
CLBLL_L.SLICEL_X0.CLUT.INIT[23] origin:010-clb-lutinit 33_40
CLBLL_L.SLICEL_X0.CLUT.INIT[24] origin:010-clb-lutinit 35_43
CLBLL_L.SLICEL_X0.CLUT.INIT[25] origin:010-clb-lutinit 34_43
CLBLL_L.SLICEL_X0.CLUT.INIT[26] origin:010-clb-lutinit 35_42
CLBLL_L.SLICEL_X0.CLUT.INIT[27] origin:010-clb-lutinit 34_42
CLBLL_L.SLICEL_X0.CLUT.INIT[28] origin:010-clb-lutinit 35_41
CLBLL_L.SLICEL_X0.CLUT.INIT[29] origin:010-clb-lutinit 34_41
CLBLL_L.SLICEL_X0.CLUT.INIT[30] origin:010-clb-lutinit 35_40
CLBLL_L.SLICEL_X0.CLUT.INIT[31] origin:010-clb-lutinit 34_40
CLBLL_L.SLICEL_X0.CLUT.INIT[32] origin:010-clb-lutinit 32_39
CLBLL_L.SLICEL_X0.CLUT.INIT[33] origin:010-clb-lutinit 33_39
CLBLL_L.SLICEL_X0.CLUT.INIT[34] origin:010-clb-lutinit 32_38
CLBLL_L.SLICEL_X0.CLUT.INIT[35] origin:010-clb-lutinit 33_38
CLBLL_L.SLICEL_X0.CLUT.INIT[36] origin:010-clb-lutinit 32_37
CLBLL_L.SLICEL_X0.CLUT.INIT[37] origin:010-clb-lutinit 33_37
CLBLL_L.SLICEL_X0.CLUT.INIT[38] origin:010-clb-lutinit 32_36
CLBLL_L.SLICEL_X0.CLUT.INIT[39] origin:010-clb-lutinit 33_36
CLBLL_L.SLICEL_X0.CLUT.INIT[40] origin:010-clb-lutinit 35_39
CLBLL_L.SLICEL_X0.CLUT.INIT[41] origin:010-clb-lutinit 34_39
CLBLL_L.SLICEL_X0.CLUT.INIT[42] origin:010-clb-lutinit 35_38
CLBLL_L.SLICEL_X0.CLUT.INIT[43] origin:010-clb-lutinit 34_38
CLBLL_L.SLICEL_X0.CLUT.INIT[44] origin:010-clb-lutinit 35_37
CLBLL_L.SLICEL_X0.CLUT.INIT[45] origin:010-clb-lutinit 34_37
CLBLL_L.SLICEL_X0.CLUT.INIT[46] origin:010-clb-lutinit 35_36
CLBLL_L.SLICEL_X0.CLUT.INIT[47] origin:010-clb-lutinit 34_36
CLBLL_L.SLICEL_X0.CLUT.INIT[48] origin:010-clb-lutinit 32_35
CLBLL_L.SLICEL_X0.CLUT.INIT[49] origin:010-clb-lutinit 33_35
CLBLL_L.SLICEL_X0.CLUT.INIT[50] origin:010-clb-lutinit 32_34
CLBLL_L.SLICEL_X0.CLUT.INIT[51] origin:010-clb-lutinit 33_34
CLBLL_L.SLICEL_X0.CLUT.INIT[52] origin:010-clb-lutinit 32_33
CLBLL_L.SLICEL_X0.CLUT.INIT[53] origin:010-clb-lutinit 33_33
CLBLL_L.SLICEL_X0.CLUT.INIT[54] origin:010-clb-lutinit 32_32
CLBLL_L.SLICEL_X0.CLUT.INIT[55] origin:010-clb-lutinit 33_32
CLBLL_L.SLICEL_X0.CLUT.INIT[56] origin:010-clb-lutinit 35_35
CLBLL_L.SLICEL_X0.CLUT.INIT[57] origin:010-clb-lutinit 34_35
CLBLL_L.SLICEL_X0.CLUT.INIT[58] origin:010-clb-lutinit 35_34
CLBLL_L.SLICEL_X0.CLUT.INIT[59] origin:010-clb-lutinit 34_34
CLBLL_L.SLICEL_X0.CLUT.INIT[60] origin:010-clb-lutinit 35_33
CLBLL_L.SLICEL_X0.CLUT.INIT[61] origin:010-clb-lutinit 34_33
CLBLL_L.SLICEL_X0.CLUT.INIT[62] origin:010-clb-lutinit 35_32
CLBLL_L.SLICEL_X0.CLUT.INIT[63] origin:010-clb-lutinit 34_32
CLBLL_L.SLICEL_X0.COUTMUX.C5Q origin:016-clb-noutmux !30_40 !30_44 !30_45 30_43
CLBLL_L.SLICEL_X0.COUTMUX.CY origin:016-clb-noutmux !30_43 !30_45 30_40 30_44
CLBLL_L.SLICEL_X0.COUTMUX.F7 origin:016-clb-noutmux !30_44 !30_45 30_40 30_43
CLBLL_L.SLICEL_X0.COUTMUX.O5 origin:016-clb-noutmux !30_43 !30_44 30_40 30_45
CLBLL_L.SLICEL_X0.COUTMUX.O6 origin:016-clb-noutmux !30_40 !30_43 !30_44 30_45
CLBLL_L.SLICEL_X0.COUTMUX.XOR origin:016-clb-noutmux !30_40 !30_43 !30_45 30_44
CLBLL_L.SLICEL_X0.D5FF.ZINI origin:011-clb-ffconfig 31_51
CLBLL_L.SLICEL_X0.D5FF.ZRST origin:011-clb-ffconfig 01_55
CLBLL_L.SLICEL_X0.D5FFMUX.IN_A origin:012-clb-n5ffmux 30_55
CLBLL_L.SLICEL_X0.D5FFMUX.IN_B origin:012-clb-n5ffmux 30_54
CLBLL_L.SLICEL_X0.DFF.ZINI origin:011-clb-ffconfig 31_58
CLBLL_L.SLICEL_X0.DFF.ZRST origin:011-clb-ffconfig 30_50
CLBLL_L.SLICEL_X0.DFFMUX.CY origin:015-clb-nffmux !30_59 !30_61 30_60 30_62
CLBLL_L.SLICEL_X0.DFFMUX.DX origin:015-clb-nffmux !30_59 !30_60 !30_62 30_61
CLBLL_L.SLICEL_X0.DFFMUX.O5 origin:015-clb-nffmux !30_60 !30_61 30_59 30_62
CLBLL_L.SLICEL_X0.DFFMUX.O6 origin:015-clb-nffmux !30_60 !30_61 !30_62 30_59
CLBLL_L.SLICEL_X0.DFFMUX.XOR origin:015-clb-nffmux !30_59 !30_61 !30_62 30_60
CLBLL_L.SLICEL_X0.DLUT.INIT[00] origin:010-clb-lutinit 32_63
CLBLL_L.SLICEL_X0.DLUT.INIT[01] origin:010-clb-lutinit 33_63
CLBLL_L.SLICEL_X0.DLUT.INIT[02] origin:010-clb-lutinit 32_62
CLBLL_L.SLICEL_X0.DLUT.INIT[03] origin:010-clb-lutinit 33_62
CLBLL_L.SLICEL_X0.DLUT.INIT[04] origin:010-clb-lutinit 32_61
CLBLL_L.SLICEL_X0.DLUT.INIT[05] origin:010-clb-lutinit 33_61
CLBLL_L.SLICEL_X0.DLUT.INIT[06] origin:010-clb-lutinit 32_60
CLBLL_L.SLICEL_X0.DLUT.INIT[07] origin:010-clb-lutinit 33_60
CLBLL_L.SLICEL_X0.DLUT.INIT[08] origin:010-clb-lutinit 35_63
CLBLL_L.SLICEL_X0.DLUT.INIT[09] origin:010-clb-lutinit 34_63
CLBLL_L.SLICEL_X0.DLUT.INIT[10] origin:010-clb-lutinit 35_62
CLBLL_L.SLICEL_X0.DLUT.INIT[11] origin:010-clb-lutinit 34_62
CLBLL_L.SLICEL_X0.DLUT.INIT[12] origin:010-clb-lutinit 35_61
CLBLL_L.SLICEL_X0.DLUT.INIT[13] origin:010-clb-lutinit 34_61
CLBLL_L.SLICEL_X0.DLUT.INIT[14] origin:010-clb-lutinit 35_60
CLBLL_L.SLICEL_X0.DLUT.INIT[15] origin:010-clb-lutinit 34_60
CLBLL_L.SLICEL_X0.DLUT.INIT[16] origin:010-clb-lutinit 32_59
CLBLL_L.SLICEL_X0.DLUT.INIT[17] origin:010-clb-lutinit 33_59
CLBLL_L.SLICEL_X0.DLUT.INIT[18] origin:010-clb-lutinit 32_58
CLBLL_L.SLICEL_X0.DLUT.INIT[19] origin:010-clb-lutinit 33_58
CLBLL_L.SLICEL_X0.DLUT.INIT[20] origin:010-clb-lutinit 32_57
CLBLL_L.SLICEL_X0.DLUT.INIT[21] origin:010-clb-lutinit 33_57
CLBLL_L.SLICEL_X0.DLUT.INIT[22] origin:010-clb-lutinit 32_56
CLBLL_L.SLICEL_X0.DLUT.INIT[23] origin:010-clb-lutinit 33_56
CLBLL_L.SLICEL_X0.DLUT.INIT[24] origin:010-clb-lutinit 35_59
CLBLL_L.SLICEL_X0.DLUT.INIT[25] origin:010-clb-lutinit 34_59
CLBLL_L.SLICEL_X0.DLUT.INIT[26] origin:010-clb-lutinit 35_58
CLBLL_L.SLICEL_X0.DLUT.INIT[27] origin:010-clb-lutinit 34_58
CLBLL_L.SLICEL_X0.DLUT.INIT[28] origin:010-clb-lutinit 35_57
CLBLL_L.SLICEL_X0.DLUT.INIT[29] origin:010-clb-lutinit 34_57
CLBLL_L.SLICEL_X0.DLUT.INIT[30] origin:010-clb-lutinit 35_56
CLBLL_L.SLICEL_X0.DLUT.INIT[31] origin:010-clb-lutinit 34_56
CLBLL_L.SLICEL_X0.DLUT.INIT[32] origin:010-clb-lutinit 32_55
CLBLL_L.SLICEL_X0.DLUT.INIT[33] origin:010-clb-lutinit 33_55
CLBLL_L.SLICEL_X0.DLUT.INIT[34] origin:010-clb-lutinit 32_54
CLBLL_L.SLICEL_X0.DLUT.INIT[35] origin:010-clb-lutinit 33_54
CLBLL_L.SLICEL_X0.DLUT.INIT[36] origin:010-clb-lutinit 32_53
CLBLL_L.SLICEL_X0.DLUT.INIT[37] origin:010-clb-lutinit 33_53
CLBLL_L.SLICEL_X0.DLUT.INIT[38] origin:010-clb-lutinit 32_52
CLBLL_L.SLICEL_X0.DLUT.INIT[39] origin:010-clb-lutinit 33_52
CLBLL_L.SLICEL_X0.DLUT.INIT[40] origin:010-clb-lutinit 35_55
CLBLL_L.SLICEL_X0.DLUT.INIT[41] origin:010-clb-lutinit 34_55
CLBLL_L.SLICEL_X0.DLUT.INIT[42] origin:010-clb-lutinit 35_54
CLBLL_L.SLICEL_X0.DLUT.INIT[43] origin:010-clb-lutinit 34_54
CLBLL_L.SLICEL_X0.DLUT.INIT[44] origin:010-clb-lutinit 35_53
CLBLL_L.SLICEL_X0.DLUT.INIT[45] origin:010-clb-lutinit 34_53
CLBLL_L.SLICEL_X0.DLUT.INIT[46] origin:010-clb-lutinit 35_52
CLBLL_L.SLICEL_X0.DLUT.INIT[47] origin:010-clb-lutinit 34_52
CLBLL_L.SLICEL_X0.DLUT.INIT[48] origin:010-clb-lutinit 32_51
CLBLL_L.SLICEL_X0.DLUT.INIT[49] origin:010-clb-lutinit 33_51
CLBLL_L.SLICEL_X0.DLUT.INIT[50] origin:010-clb-lutinit 32_50
CLBLL_L.SLICEL_X0.DLUT.INIT[51] origin:010-clb-lutinit 33_50
CLBLL_L.SLICEL_X0.DLUT.INIT[52] origin:010-clb-lutinit 32_49
CLBLL_L.SLICEL_X0.DLUT.INIT[53] origin:010-clb-lutinit 33_49
CLBLL_L.SLICEL_X0.DLUT.INIT[54] origin:010-clb-lutinit 32_48
CLBLL_L.SLICEL_X0.DLUT.INIT[55] origin:010-clb-lutinit 33_48
CLBLL_L.SLICEL_X0.DLUT.INIT[56] origin:010-clb-lutinit 35_51
CLBLL_L.SLICEL_X0.DLUT.INIT[57] origin:010-clb-lutinit 34_51
CLBLL_L.SLICEL_X0.DLUT.INIT[58] origin:010-clb-lutinit 35_50
CLBLL_L.SLICEL_X0.DLUT.INIT[59] origin:010-clb-lutinit 34_50
CLBLL_L.SLICEL_X0.DLUT.INIT[60] origin:010-clb-lutinit 35_49
CLBLL_L.SLICEL_X0.DLUT.INIT[61] origin:010-clb-lutinit 34_49
CLBLL_L.SLICEL_X0.DLUT.INIT[62] origin:010-clb-lutinit 35_48
CLBLL_L.SLICEL_X0.DLUT.INIT[63] origin:010-clb-lutinit 34_48
CLBLL_L.SLICEL_X0.DOUTMUX.CY origin:016-clb-noutmux !30_56 !30_57 30_51 30_52
CLBLL_L.SLICEL_X0.DOUTMUX.D5Q origin:016-clb-noutmux !30_51 !30_52 !30_56 30_57
CLBLL_L.SLICEL_X0.DOUTMUX.O5 origin:016-clb-noutmux !30_51 !30_57 30_52 30_56
CLBLL_L.SLICEL_X0.DOUTMUX.O6 origin:016-clb-noutmux !30_51 !30_52 !30_57 30_56
CLBLL_L.SLICEL_X0.DOUTMUX.XOR origin:016-clb-noutmux !30_52 !30_56 !30_57 30_51
CLBLL_L.SLICEL_X0.FFSYNC origin:011-clb-ffconfig 00_48
CLBLL_L.SLICEL_X0.LATCH origin:011-clb-ffconfig 30_32
CLBLL_L.SLICEL_X0.PRECYINIT.AX origin:017-clb-precyinit !00_12 !30_13 30_14
CLBLL_L.SLICEL_X0.PRECYINIT.C0 origin:017-clb-precyinit !00_12 !30_13 !30_14
CLBLL_L.SLICEL_X0.PRECYINIT.C1 origin:017-clb-precyinit !30_13 !30_14 00_12
CLBLL_L.SLICEL_X0.PRECYINIT.CIN origin:017-clb-precyinit !00_12 !30_14 30_13
CLBLL_L.SLICEL_X0.SRUSEDMUX origin:014-clb-ffsrcemux 01_35
CLBLL_L.SLICEL_X1.A5FF.ZINI origin:011-clb-ffconfig 31_05
CLBLL_L.SLICEL_X1.A5FF.ZRST origin:011-clb-ffconfig 01_03
CLBLL_L.SLICEL_X1.A5FFMUX.IN_A origin:012-clb-n5ffmux 31_08
CLBLL_L.SLICEL_X1.A5FFMUX.IN_B origin:012-clb-n5ffmux 31_11
CLBLL_L.SLICEL_X1.AFF.ZINI origin:011-clb-ffconfig 31_04
CLBLL_L.SLICEL_X1.AFF.ZRST origin:011-clb-ffconfig 31_15
CLBLL_L.SLICEL_X1.AFFMUX.AX origin:015-clb-nffmux !30_04 !31_00 !31_02 31_01
CLBLL_L.SLICEL_X1.AFFMUX.CY origin:015-clb-nffmux !30_04 !31_01 31_00 31_02
CLBLL_L.SLICEL_X1.AFFMUX.F7 origin:015-clb-nffmux !30_04 !31_02 31_00 31_01
CLBLL_L.SLICEL_X1.AFFMUX.O5 origin:015-clb-nffmux !31_01 !31_02 30_04 31_00
CLBLL_L.SLICEL_X1.AFFMUX.O6 origin:015-clb-nffmux !31_00 !31_01 !31_02 30_04
CLBLL_L.SLICEL_X1.AFFMUX.XOR origin:015-clb-nffmux !30_04 !31_00 !31_01 31_02
CLBLL_L.SLICEL_X1.ALUT.INIT[00] origin:010-clb-lutinit 26_15
CLBLL_L.SLICEL_X1.ALUT.INIT[01] origin:010-clb-lutinit 27_15
CLBLL_L.SLICEL_X1.ALUT.INIT[02] origin:010-clb-lutinit 26_14
CLBLL_L.SLICEL_X1.ALUT.INIT[03] origin:010-clb-lutinit 27_14
CLBLL_L.SLICEL_X1.ALUT.INIT[04] origin:010-clb-lutinit 26_13
CLBLL_L.SLICEL_X1.ALUT.INIT[05] origin:010-clb-lutinit 27_13
CLBLL_L.SLICEL_X1.ALUT.INIT[06] origin:010-clb-lutinit 26_12
CLBLL_L.SLICEL_X1.ALUT.INIT[07] origin:010-clb-lutinit 27_12
CLBLL_L.SLICEL_X1.ALUT.INIT[08] origin:010-clb-lutinit 29_15
CLBLL_L.SLICEL_X1.ALUT.INIT[09] origin:010-clb-lutinit 28_15
CLBLL_L.SLICEL_X1.ALUT.INIT[10] origin:010-clb-lutinit 29_14
CLBLL_L.SLICEL_X1.ALUT.INIT[11] origin:010-clb-lutinit 28_14
CLBLL_L.SLICEL_X1.ALUT.INIT[12] origin:010-clb-lutinit 29_13
CLBLL_L.SLICEL_X1.ALUT.INIT[13] origin:010-clb-lutinit 28_13
CLBLL_L.SLICEL_X1.ALUT.INIT[14] origin:010-clb-lutinit 29_12
CLBLL_L.SLICEL_X1.ALUT.INIT[15] origin:010-clb-lutinit 28_12
CLBLL_L.SLICEL_X1.ALUT.INIT[16] origin:010-clb-lutinit 26_11
CLBLL_L.SLICEL_X1.ALUT.INIT[17] origin:010-clb-lutinit 27_11
CLBLL_L.SLICEL_X1.ALUT.INIT[18] origin:010-clb-lutinit 26_10
CLBLL_L.SLICEL_X1.ALUT.INIT[19] origin:010-clb-lutinit 27_10
CLBLL_L.SLICEL_X1.ALUT.INIT[20] origin:010-clb-lutinit 26_09
CLBLL_L.SLICEL_X1.ALUT.INIT[21] origin:010-clb-lutinit 27_09
CLBLL_L.SLICEL_X1.ALUT.INIT[22] origin:010-clb-lutinit 26_08
CLBLL_L.SLICEL_X1.ALUT.INIT[23] origin:010-clb-lutinit 27_08
CLBLL_L.SLICEL_X1.ALUT.INIT[24] origin:010-clb-lutinit 29_11
CLBLL_L.SLICEL_X1.ALUT.INIT[25] origin:010-clb-lutinit 28_11
CLBLL_L.SLICEL_X1.ALUT.INIT[26] origin:010-clb-lutinit 29_10
CLBLL_L.SLICEL_X1.ALUT.INIT[27] origin:010-clb-lutinit 28_10
CLBLL_L.SLICEL_X1.ALUT.INIT[28] origin:010-clb-lutinit 29_09
CLBLL_L.SLICEL_X1.ALUT.INIT[29] origin:010-clb-lutinit 28_09
CLBLL_L.SLICEL_X1.ALUT.INIT[30] origin:010-clb-lutinit 29_08
CLBLL_L.SLICEL_X1.ALUT.INIT[31] origin:010-clb-lutinit 28_08
CLBLL_L.SLICEL_X1.ALUT.INIT[32] origin:010-clb-lutinit 26_07
CLBLL_L.SLICEL_X1.ALUT.INIT[33] origin:010-clb-lutinit 27_07
CLBLL_L.SLICEL_X1.ALUT.INIT[34] origin:010-clb-lutinit 26_06
CLBLL_L.SLICEL_X1.ALUT.INIT[35] origin:010-clb-lutinit 27_06
CLBLL_L.SLICEL_X1.ALUT.INIT[36] origin:010-clb-lutinit 26_05
CLBLL_L.SLICEL_X1.ALUT.INIT[37] origin:010-clb-lutinit 27_05
CLBLL_L.SLICEL_X1.ALUT.INIT[38] origin:010-clb-lutinit 26_04
CLBLL_L.SLICEL_X1.ALUT.INIT[39] origin:010-clb-lutinit 27_04
CLBLL_L.SLICEL_X1.ALUT.INIT[40] origin:010-clb-lutinit 29_07
CLBLL_L.SLICEL_X1.ALUT.INIT[41] origin:010-clb-lutinit 28_07
CLBLL_L.SLICEL_X1.ALUT.INIT[42] origin:010-clb-lutinit 29_06
CLBLL_L.SLICEL_X1.ALUT.INIT[43] origin:010-clb-lutinit 28_06
CLBLL_L.SLICEL_X1.ALUT.INIT[44] origin:010-clb-lutinit 29_05
CLBLL_L.SLICEL_X1.ALUT.INIT[45] origin:010-clb-lutinit 28_05
CLBLL_L.SLICEL_X1.ALUT.INIT[46] origin:010-clb-lutinit 29_04
CLBLL_L.SLICEL_X1.ALUT.INIT[47] origin:010-clb-lutinit 28_04
CLBLL_L.SLICEL_X1.ALUT.INIT[48] origin:010-clb-lutinit 26_03
CLBLL_L.SLICEL_X1.ALUT.INIT[49] origin:010-clb-lutinit 27_03
CLBLL_L.SLICEL_X1.ALUT.INIT[50] origin:010-clb-lutinit 26_02
CLBLL_L.SLICEL_X1.ALUT.INIT[51] origin:010-clb-lutinit 27_02
CLBLL_L.SLICEL_X1.ALUT.INIT[52] origin:010-clb-lutinit 26_01
CLBLL_L.SLICEL_X1.ALUT.INIT[53] origin:010-clb-lutinit 27_01
CLBLL_L.SLICEL_X1.ALUT.INIT[54] origin:010-clb-lutinit 26_00
CLBLL_L.SLICEL_X1.ALUT.INIT[55] origin:010-clb-lutinit 27_00
CLBLL_L.SLICEL_X1.ALUT.INIT[56] origin:010-clb-lutinit 29_03
CLBLL_L.SLICEL_X1.ALUT.INIT[57] origin:010-clb-lutinit 28_03
CLBLL_L.SLICEL_X1.ALUT.INIT[58] origin:010-clb-lutinit 29_02
CLBLL_L.SLICEL_X1.ALUT.INIT[59] origin:010-clb-lutinit 28_02
CLBLL_L.SLICEL_X1.ALUT.INIT[60] origin:010-clb-lutinit 29_01
CLBLL_L.SLICEL_X1.ALUT.INIT[61] origin:010-clb-lutinit 28_01
CLBLL_L.SLICEL_X1.ALUT.INIT[62] origin:010-clb-lutinit 29_00
CLBLL_L.SLICEL_X1.ALUT.INIT[63] origin:010-clb-lutinit 28_00
CLBLL_L.SLICEL_X1.AOUTMUX.A5Q origin:016-clb-noutmux !31_07 !31_09 !31_10 30_05
CLBLL_L.SLICEL_X1.AOUTMUX.CY origin:016-clb-noutmux !30_05 !31_09 31_07 31_10
CLBLL_L.SLICEL_X1.AOUTMUX.F7 origin:016-clb-noutmux !31_07 !31_09 30_05 31_10
CLBLL_L.SLICEL_X1.AOUTMUX.O5 origin:016-clb-noutmux !30_05 !31_07 31_09 31_10
CLBLL_L.SLICEL_X1.AOUTMUX.O6 origin:016-clb-noutmux !30_05 !31_07 !31_10 31_09
CLBLL_L.SLICEL_X1.AOUTMUX.XOR origin:016-clb-noutmux !30_05 !31_09 !31_10 31_07
CLBLL_L.SLICEL_X1.B5FF.ZINI origin:011-clb-ffconfig 31_23
CLBLL_L.SLICEL_X1.B5FF.ZRST origin:011-clb-ffconfig 00_16
CLBLL_L.SLICEL_X1.B5FFMUX.IN_A origin:012-clb-n5ffmux 31_19
CLBLL_L.SLICEL_X1.B5FFMUX.IN_B origin:012-clb-n5ffmux 31_18
CLBLL_L.SLICEL_X1.BFF.ZINI origin:011-clb-ffconfig 31_29
CLBLL_L.SLICEL_X1.BFF.ZRST origin:011-clb-ffconfig 31_30
CLBLL_L.SLICEL_X1.BFFMUX.BX origin:015-clb-nffmux !31_24 !31_25 !31_26 31_27
CLBLL_L.SLICEL_X1.BFFMUX.CY origin:015-clb-nffmux !31_24 !31_27 31_25 31_26
CLBLL_L.SLICEL_X1.BFFMUX.F8 origin:015-clb-nffmux !31_24 !31_26 31_25 31_27
CLBLL_L.SLICEL_X1.BFFMUX.O5 origin:015-clb-nffmux !31_26 !31_27 31_24 31_25
CLBLL_L.SLICEL_X1.BFFMUX.O6 origin:015-clb-nffmux !31_25 !31_26 !31_27 31_24
CLBLL_L.SLICEL_X1.BFFMUX.XOR origin:015-clb-nffmux !31_24 !31_25 !31_27 31_26
CLBLL_L.SLICEL_X1.BLUT.INIT[00] origin:010-clb-lutinit 26_31
CLBLL_L.SLICEL_X1.BLUT.INIT[01] origin:010-clb-lutinit 27_31
CLBLL_L.SLICEL_X1.BLUT.INIT[02] origin:010-clb-lutinit 26_30
CLBLL_L.SLICEL_X1.BLUT.INIT[03] origin:010-clb-lutinit 27_30
CLBLL_L.SLICEL_X1.BLUT.INIT[04] origin:010-clb-lutinit 26_29
CLBLL_L.SLICEL_X1.BLUT.INIT[05] origin:010-clb-lutinit 27_29
CLBLL_L.SLICEL_X1.BLUT.INIT[06] origin:010-clb-lutinit 26_28
CLBLL_L.SLICEL_X1.BLUT.INIT[07] origin:010-clb-lutinit 27_28
CLBLL_L.SLICEL_X1.BLUT.INIT[08] origin:010-clb-lutinit 29_31
CLBLL_L.SLICEL_X1.BLUT.INIT[09] origin:010-clb-lutinit 28_31
CLBLL_L.SLICEL_X1.BLUT.INIT[10] origin:010-clb-lutinit 29_30
CLBLL_L.SLICEL_X1.BLUT.INIT[11] origin:010-clb-lutinit 28_30
CLBLL_L.SLICEL_X1.BLUT.INIT[12] origin:010-clb-lutinit 29_29
CLBLL_L.SLICEL_X1.BLUT.INIT[13] origin:010-clb-lutinit 28_29
CLBLL_L.SLICEL_X1.BLUT.INIT[14] origin:010-clb-lutinit 29_28
CLBLL_L.SLICEL_X1.BLUT.INIT[15] origin:010-clb-lutinit 28_28
CLBLL_L.SLICEL_X1.BLUT.INIT[16] origin:010-clb-lutinit 26_27
CLBLL_L.SLICEL_X1.BLUT.INIT[17] origin:010-clb-lutinit 27_27
CLBLL_L.SLICEL_X1.BLUT.INIT[18] origin:010-clb-lutinit 26_26
CLBLL_L.SLICEL_X1.BLUT.INIT[19] origin:010-clb-lutinit 27_26
CLBLL_L.SLICEL_X1.BLUT.INIT[20] origin:010-clb-lutinit 26_25
CLBLL_L.SLICEL_X1.BLUT.INIT[21] origin:010-clb-lutinit 27_25
CLBLL_L.SLICEL_X1.BLUT.INIT[22] origin:010-clb-lutinit 26_24
CLBLL_L.SLICEL_X1.BLUT.INIT[23] origin:010-clb-lutinit 27_24
CLBLL_L.SLICEL_X1.BLUT.INIT[24] origin:010-clb-lutinit 29_27
CLBLL_L.SLICEL_X1.BLUT.INIT[25] origin:010-clb-lutinit 28_27
CLBLL_L.SLICEL_X1.BLUT.INIT[26] origin:010-clb-lutinit 29_26
CLBLL_L.SLICEL_X1.BLUT.INIT[27] origin:010-clb-lutinit 28_26
CLBLL_L.SLICEL_X1.BLUT.INIT[28] origin:010-clb-lutinit 29_25
CLBLL_L.SLICEL_X1.BLUT.INIT[29] origin:010-clb-lutinit 28_25
CLBLL_L.SLICEL_X1.BLUT.INIT[30] origin:010-clb-lutinit 29_24
CLBLL_L.SLICEL_X1.BLUT.INIT[31] origin:010-clb-lutinit 28_24
CLBLL_L.SLICEL_X1.BLUT.INIT[32] origin:010-clb-lutinit 26_23
CLBLL_L.SLICEL_X1.BLUT.INIT[33] origin:010-clb-lutinit 27_23
CLBLL_L.SLICEL_X1.BLUT.INIT[34] origin:010-clb-lutinit 26_22
CLBLL_L.SLICEL_X1.BLUT.INIT[35] origin:010-clb-lutinit 27_22
CLBLL_L.SLICEL_X1.BLUT.INIT[36] origin:010-clb-lutinit 26_21
CLBLL_L.SLICEL_X1.BLUT.INIT[37] origin:010-clb-lutinit 27_21
CLBLL_L.SLICEL_X1.BLUT.INIT[38] origin:010-clb-lutinit 26_20
CLBLL_L.SLICEL_X1.BLUT.INIT[39] origin:010-clb-lutinit 27_20
CLBLL_L.SLICEL_X1.BLUT.INIT[40] origin:010-clb-lutinit 29_23
CLBLL_L.SLICEL_X1.BLUT.INIT[41] origin:010-clb-lutinit 28_23
CLBLL_L.SLICEL_X1.BLUT.INIT[42] origin:010-clb-lutinit 29_22
CLBLL_L.SLICEL_X1.BLUT.INIT[43] origin:010-clb-lutinit 28_22
CLBLL_L.SLICEL_X1.BLUT.INIT[44] origin:010-clb-lutinit 29_21
CLBLL_L.SLICEL_X1.BLUT.INIT[45] origin:010-clb-lutinit 28_21
CLBLL_L.SLICEL_X1.BLUT.INIT[46] origin:010-clb-lutinit 29_20
CLBLL_L.SLICEL_X1.BLUT.INIT[47] origin:010-clb-lutinit 28_20
CLBLL_L.SLICEL_X1.BLUT.INIT[48] origin:010-clb-lutinit 26_19
CLBLL_L.SLICEL_X1.BLUT.INIT[49] origin:010-clb-lutinit 27_19
CLBLL_L.SLICEL_X1.BLUT.INIT[50] origin:010-clb-lutinit 26_18
CLBLL_L.SLICEL_X1.BLUT.INIT[51] origin:010-clb-lutinit 27_18
CLBLL_L.SLICEL_X1.BLUT.INIT[52] origin:010-clb-lutinit 26_17
CLBLL_L.SLICEL_X1.BLUT.INIT[53] origin:010-clb-lutinit 27_17
CLBLL_L.SLICEL_X1.BLUT.INIT[54] origin:010-clb-lutinit 26_16
CLBLL_L.SLICEL_X1.BLUT.INIT[55] origin:010-clb-lutinit 27_16
CLBLL_L.SLICEL_X1.BLUT.INIT[56] origin:010-clb-lutinit 29_19
CLBLL_L.SLICEL_X1.BLUT.INIT[57] origin:010-clb-lutinit 28_19
CLBLL_L.SLICEL_X1.BLUT.INIT[58] origin:010-clb-lutinit 29_18
CLBLL_L.SLICEL_X1.BLUT.INIT[59] origin:010-clb-lutinit 28_18
CLBLL_L.SLICEL_X1.BLUT.INIT[60] origin:010-clb-lutinit 29_17
CLBLL_L.SLICEL_X1.BLUT.INIT[61] origin:010-clb-lutinit 28_17
CLBLL_L.SLICEL_X1.BLUT.INIT[62] origin:010-clb-lutinit 29_16
CLBLL_L.SLICEL_X1.BLUT.INIT[63] origin:010-clb-lutinit 28_16
CLBLL_L.SLICEL_X1.BOUTMUX.B5Q origin:016-clb-noutmux !30_28 !31_20 !31_21 30_29
CLBLL_L.SLICEL_X1.BOUTMUX.CY origin:016-clb-noutmux !30_29 !31_20 30_28 31_21
CLBLL_L.SLICEL_X1.BOUTMUX.F8 origin:016-clb-noutmux !30_28 !31_20 30_29 31_21
CLBLL_L.SLICEL_X1.BOUTMUX.O5 origin:016-clb-noutmux !30_28 !30_29 31_20 31_21
CLBLL_L.SLICEL_X1.BOUTMUX.O6 origin:016-clb-noutmux !30_28 !30_29 !31_21 31_20
CLBLL_L.SLICEL_X1.BOUTMUX.XOR origin:016-clb-noutmux !30_29 !31_20 !31_21 30_28
CLBLL_L.SLICEL_X1.C5FF.ZINI origin:011-clb-ffconfig 31_42
CLBLL_L.SLICEL_X1.C5FF.ZRST origin:011-clb-ffconfig 00_44
CLBLL_L.SLICEL_X1.C5FFMUX.IN_A origin:012-clb-n5ffmux 31_44
CLBLL_L.SLICEL_X1.C5FFMUX.IN_B origin:012-clb-n5ffmux 31_39
CLBLL_L.SLICEL_X1.CARRY4.ACY0 origin:013-clb-ncy0 31_14
CLBLL_L.SLICEL_X1.CARRY4.BCY0 origin:013-clb-ncy0 00_08
CLBLL_L.SLICEL_X1.CARRY4.CCY0 origin:013-clb-ncy0 31_48
CLBLL_L.SLICEL_X1.CARRY4.DCY0 origin:013-clb-ncy0 31_49
CLBLL_L.SLICEL_X1.CEUSEDMUX origin:014-clb-ffsrcemux 00_36
CLBLL_L.SLICEL_X1.CFF.ZINI origin:011-clb-ffconfig 31_34
CLBLL_L.SLICEL_X1.CFF.ZRST origin:011-clb-ffconfig 30_34
CLBLL_L.SLICEL_X1.CFFMUX.CX origin:015-clb-nffmux !31_35 !31_36 !31_37 31_38
CLBLL_L.SLICEL_X1.CFFMUX.CY origin:015-clb-nffmux !31_36 !31_38 31_35 31_37
CLBLL_L.SLICEL_X1.CFFMUX.F7 origin:015-clb-nffmux !31_36 !31_37 31_35 31_38
CLBLL_L.SLICEL_X1.CFFMUX.O5 origin:015-clb-nffmux !31_37 !31_38 31_35 31_36
CLBLL_L.SLICEL_X1.CFFMUX.O6 origin:015-clb-nffmux !31_35 !31_37 !31_38 31_36
CLBLL_L.SLICEL_X1.CFFMUX.XOR origin:015-clb-nffmux !31_35 !31_36 !31_38 31_37
CLBLL_L.SLICEL_X1.CLKINV origin:011-clb-ffconfig 00_52
CLBLL_L.SLICEL_X1.CLUT.INIT[00] origin:010-clb-lutinit 26_47
CLBLL_L.SLICEL_X1.CLUT.INIT[01] origin:010-clb-lutinit 27_47
CLBLL_L.SLICEL_X1.CLUT.INIT[02] origin:010-clb-lutinit 26_46
CLBLL_L.SLICEL_X1.CLUT.INIT[03] origin:010-clb-lutinit 27_46
CLBLL_L.SLICEL_X1.CLUT.INIT[04] origin:010-clb-lutinit 26_45
CLBLL_L.SLICEL_X1.CLUT.INIT[05] origin:010-clb-lutinit 27_45
CLBLL_L.SLICEL_X1.CLUT.INIT[06] origin:010-clb-lutinit 26_44
CLBLL_L.SLICEL_X1.CLUT.INIT[07] origin:010-clb-lutinit 27_44
CLBLL_L.SLICEL_X1.CLUT.INIT[08] origin:010-clb-lutinit 29_47
CLBLL_L.SLICEL_X1.CLUT.INIT[09] origin:010-clb-lutinit 28_47
CLBLL_L.SLICEL_X1.CLUT.INIT[10] origin:010-clb-lutinit 29_46
CLBLL_L.SLICEL_X1.CLUT.INIT[11] origin:010-clb-lutinit 28_46
CLBLL_L.SLICEL_X1.CLUT.INIT[12] origin:010-clb-lutinit 29_45
CLBLL_L.SLICEL_X1.CLUT.INIT[13] origin:010-clb-lutinit 28_45
CLBLL_L.SLICEL_X1.CLUT.INIT[14] origin:010-clb-lutinit 29_44
CLBLL_L.SLICEL_X1.CLUT.INIT[15] origin:010-clb-lutinit 28_44
CLBLL_L.SLICEL_X1.CLUT.INIT[16] origin:010-clb-lutinit 26_43
CLBLL_L.SLICEL_X1.CLUT.INIT[17] origin:010-clb-lutinit 27_43
CLBLL_L.SLICEL_X1.CLUT.INIT[18] origin:010-clb-lutinit 26_42
CLBLL_L.SLICEL_X1.CLUT.INIT[19] origin:010-clb-lutinit 27_42
CLBLL_L.SLICEL_X1.CLUT.INIT[20] origin:010-clb-lutinit 26_41
CLBLL_L.SLICEL_X1.CLUT.INIT[21] origin:010-clb-lutinit 27_41
CLBLL_L.SLICEL_X1.CLUT.INIT[22] origin:010-clb-lutinit 26_40
CLBLL_L.SLICEL_X1.CLUT.INIT[23] origin:010-clb-lutinit 27_40
CLBLL_L.SLICEL_X1.CLUT.INIT[24] origin:010-clb-lutinit 29_43
CLBLL_L.SLICEL_X1.CLUT.INIT[25] origin:010-clb-lutinit 28_43
CLBLL_L.SLICEL_X1.CLUT.INIT[26] origin:010-clb-lutinit 29_42
CLBLL_L.SLICEL_X1.CLUT.INIT[27] origin:010-clb-lutinit 28_42
CLBLL_L.SLICEL_X1.CLUT.INIT[28] origin:010-clb-lutinit 29_41
CLBLL_L.SLICEL_X1.CLUT.INIT[29] origin:010-clb-lutinit 28_41
CLBLL_L.SLICEL_X1.CLUT.INIT[30] origin:010-clb-lutinit 29_40
CLBLL_L.SLICEL_X1.CLUT.INIT[31] origin:010-clb-lutinit 28_40
CLBLL_L.SLICEL_X1.CLUT.INIT[32] origin:010-clb-lutinit 26_39
CLBLL_L.SLICEL_X1.CLUT.INIT[33] origin:010-clb-lutinit 27_39
CLBLL_L.SLICEL_X1.CLUT.INIT[34] origin:010-clb-lutinit 26_38
CLBLL_L.SLICEL_X1.CLUT.INIT[35] origin:010-clb-lutinit 27_38
CLBLL_L.SLICEL_X1.CLUT.INIT[36] origin:010-clb-lutinit 26_37
CLBLL_L.SLICEL_X1.CLUT.INIT[37] origin:010-clb-lutinit 27_37
CLBLL_L.SLICEL_X1.CLUT.INIT[38] origin:010-clb-lutinit 26_36
CLBLL_L.SLICEL_X1.CLUT.INIT[39] origin:010-clb-lutinit 27_36
CLBLL_L.SLICEL_X1.CLUT.INIT[40] origin:010-clb-lutinit 29_39
CLBLL_L.SLICEL_X1.CLUT.INIT[41] origin:010-clb-lutinit 28_39
CLBLL_L.SLICEL_X1.CLUT.INIT[42] origin:010-clb-lutinit 29_38
CLBLL_L.SLICEL_X1.CLUT.INIT[43] origin:010-clb-lutinit 28_38
CLBLL_L.SLICEL_X1.CLUT.INIT[44] origin:010-clb-lutinit 29_37
CLBLL_L.SLICEL_X1.CLUT.INIT[45] origin:010-clb-lutinit 28_37
CLBLL_L.SLICEL_X1.CLUT.INIT[46] origin:010-clb-lutinit 29_36
CLBLL_L.SLICEL_X1.CLUT.INIT[47] origin:010-clb-lutinit 28_36
CLBLL_L.SLICEL_X1.CLUT.INIT[48] origin:010-clb-lutinit 26_35
CLBLL_L.SLICEL_X1.CLUT.INIT[49] origin:010-clb-lutinit 27_35
CLBLL_L.SLICEL_X1.CLUT.INIT[50] origin:010-clb-lutinit 26_34
CLBLL_L.SLICEL_X1.CLUT.INIT[51] origin:010-clb-lutinit 27_34
CLBLL_L.SLICEL_X1.CLUT.INIT[52] origin:010-clb-lutinit 26_33
CLBLL_L.SLICEL_X1.CLUT.INIT[53] origin:010-clb-lutinit 27_33
CLBLL_L.SLICEL_X1.CLUT.INIT[54] origin:010-clb-lutinit 26_32
CLBLL_L.SLICEL_X1.CLUT.INIT[55] origin:010-clb-lutinit 27_32
CLBLL_L.SLICEL_X1.CLUT.INIT[56] origin:010-clb-lutinit 29_35
CLBLL_L.SLICEL_X1.CLUT.INIT[57] origin:010-clb-lutinit 28_35
CLBLL_L.SLICEL_X1.CLUT.INIT[58] origin:010-clb-lutinit 29_34
CLBLL_L.SLICEL_X1.CLUT.INIT[59] origin:010-clb-lutinit 28_34
CLBLL_L.SLICEL_X1.CLUT.INIT[60] origin:010-clb-lutinit 29_33
CLBLL_L.SLICEL_X1.CLUT.INIT[61] origin:010-clb-lutinit 28_33
CLBLL_L.SLICEL_X1.CLUT.INIT[62] origin:010-clb-lutinit 29_32
CLBLL_L.SLICEL_X1.CLUT.INIT[63] origin:010-clb-lutinit 28_32
CLBLL_L.SLICEL_X1.COUTMUX.C5Q origin:016-clb-noutmux !30_42 !31_40 !31_43 30_41
CLBLL_L.SLICEL_X1.COUTMUX.CY origin:016-clb-noutmux !30_41 !31_43 30_42 31_40
CLBLL_L.SLICEL_X1.COUTMUX.F7 origin:016-clb-noutmux !30_42 !31_43 30_41 31_40
CLBLL_L.SLICEL_X1.COUTMUX.O5 origin:016-clb-noutmux !30_41 !30_42 31_40 31_43
CLBLL_L.SLICEL_X1.COUTMUX.O6 origin:016-clb-noutmux !30_41 !30_42 !31_40 31_43
CLBLL_L.SLICEL_X1.COUTMUX.XOR origin:016-clb-noutmux !30_41 !31_40 !31_43 30_42
CLBLL_L.SLICEL_X1.D5FF.ZINI origin:011-clb-ffconfig 31_52
CLBLL_L.SLICEL_X1.D5FF.ZRST origin:011-clb-ffconfig 00_56
CLBLL_L.SLICEL_X1.D5FFMUX.IN_A origin:012-clb-n5ffmux 31_55
CLBLL_L.SLICEL_X1.D5FFMUX.IN_B origin:012-clb-n5ffmux 31_54
CLBLL_L.SLICEL_X1.DFF.ZINI origin:011-clb-ffconfig 31_59
CLBLL_L.SLICEL_X1.DFF.ZRST origin:011-clb-ffconfig 31_50
CLBLL_L.SLICEL_X1.DFFMUX.CY origin:015-clb-nffmux !31_60 !31_61 30_58 31_62
CLBLL_L.SLICEL_X1.DFFMUX.DX origin:015-clb-nffmux !30_58 !31_60 !31_62 31_61
CLBLL_L.SLICEL_X1.DFFMUX.O5 origin:015-clb-nffmux !31_61 !31_62 30_58 31_60
CLBLL_L.SLICEL_X1.DFFMUX.O6 origin:015-clb-nffmux !30_58 !31_61 !31_62 31_60
CLBLL_L.SLICEL_X1.DFFMUX.XOR origin:015-clb-nffmux !30_58 !31_60 !31_61 31_62
CLBLL_L.SLICEL_X1.DLUT.INIT[00] origin:010-clb-lutinit 26_63
CLBLL_L.SLICEL_X1.DLUT.INIT[01] origin:010-clb-lutinit 27_63
CLBLL_L.SLICEL_X1.DLUT.INIT[02] origin:010-clb-lutinit 26_62
CLBLL_L.SLICEL_X1.DLUT.INIT[03] origin:010-clb-lutinit 27_62
CLBLL_L.SLICEL_X1.DLUT.INIT[04] origin:010-clb-lutinit 26_61
CLBLL_L.SLICEL_X1.DLUT.INIT[05] origin:010-clb-lutinit 27_61
CLBLL_L.SLICEL_X1.DLUT.INIT[06] origin:010-clb-lutinit 26_60
CLBLL_L.SLICEL_X1.DLUT.INIT[07] origin:010-clb-lutinit 27_60
CLBLL_L.SLICEL_X1.DLUT.INIT[08] origin:010-clb-lutinit 29_63
CLBLL_L.SLICEL_X1.DLUT.INIT[09] origin:010-clb-lutinit 28_63
CLBLL_L.SLICEL_X1.DLUT.INIT[10] origin:010-clb-lutinit 29_62
CLBLL_L.SLICEL_X1.DLUT.INIT[11] origin:010-clb-lutinit 28_62
CLBLL_L.SLICEL_X1.DLUT.INIT[12] origin:010-clb-lutinit 29_61
CLBLL_L.SLICEL_X1.DLUT.INIT[13] origin:010-clb-lutinit 28_61
CLBLL_L.SLICEL_X1.DLUT.INIT[14] origin:010-clb-lutinit 29_60
CLBLL_L.SLICEL_X1.DLUT.INIT[15] origin:010-clb-lutinit 28_60
CLBLL_L.SLICEL_X1.DLUT.INIT[16] origin:010-clb-lutinit 26_59
CLBLL_L.SLICEL_X1.DLUT.INIT[17] origin:010-clb-lutinit 27_59
CLBLL_L.SLICEL_X1.DLUT.INIT[18] origin:010-clb-lutinit 26_58
CLBLL_L.SLICEL_X1.DLUT.INIT[19] origin:010-clb-lutinit 27_58
CLBLL_L.SLICEL_X1.DLUT.INIT[20] origin:010-clb-lutinit 26_57
CLBLL_L.SLICEL_X1.DLUT.INIT[21] origin:010-clb-lutinit 27_57
CLBLL_L.SLICEL_X1.DLUT.INIT[22] origin:010-clb-lutinit 26_56
CLBLL_L.SLICEL_X1.DLUT.INIT[23] origin:010-clb-lutinit 27_56
CLBLL_L.SLICEL_X1.DLUT.INIT[24] origin:010-clb-lutinit 29_59
CLBLL_L.SLICEL_X1.DLUT.INIT[25] origin:010-clb-lutinit 28_59
CLBLL_L.SLICEL_X1.DLUT.INIT[26] origin:010-clb-lutinit 29_58
CLBLL_L.SLICEL_X1.DLUT.INIT[27] origin:010-clb-lutinit 28_58
CLBLL_L.SLICEL_X1.DLUT.INIT[28] origin:010-clb-lutinit 29_57
CLBLL_L.SLICEL_X1.DLUT.INIT[29] origin:010-clb-lutinit 28_57
CLBLL_L.SLICEL_X1.DLUT.INIT[30] origin:010-clb-lutinit 29_56
CLBLL_L.SLICEL_X1.DLUT.INIT[31] origin:010-clb-lutinit 28_56
CLBLL_L.SLICEL_X1.DLUT.INIT[32] origin:010-clb-lutinit 26_55
CLBLL_L.SLICEL_X1.DLUT.INIT[33] origin:010-clb-lutinit 27_55
CLBLL_L.SLICEL_X1.DLUT.INIT[34] origin:010-clb-lutinit 26_54
CLBLL_L.SLICEL_X1.DLUT.INIT[35] origin:010-clb-lutinit 27_54
CLBLL_L.SLICEL_X1.DLUT.INIT[36] origin:010-clb-lutinit 26_53
CLBLL_L.SLICEL_X1.DLUT.INIT[37] origin:010-clb-lutinit 27_53
CLBLL_L.SLICEL_X1.DLUT.INIT[38] origin:010-clb-lutinit 26_52
CLBLL_L.SLICEL_X1.DLUT.INIT[39] origin:010-clb-lutinit 27_52
CLBLL_L.SLICEL_X1.DLUT.INIT[40] origin:010-clb-lutinit 29_55
CLBLL_L.SLICEL_X1.DLUT.INIT[41] origin:010-clb-lutinit 28_55
CLBLL_L.SLICEL_X1.DLUT.INIT[42] origin:010-clb-lutinit 29_54
CLBLL_L.SLICEL_X1.DLUT.INIT[43] origin:010-clb-lutinit 28_54
CLBLL_L.SLICEL_X1.DLUT.INIT[44] origin:010-clb-lutinit 29_53
CLBLL_L.SLICEL_X1.DLUT.INIT[45] origin:010-clb-lutinit 28_53
CLBLL_L.SLICEL_X1.DLUT.INIT[46] origin:010-clb-lutinit 29_52
CLBLL_L.SLICEL_X1.DLUT.INIT[47] origin:010-clb-lutinit 28_52
CLBLL_L.SLICEL_X1.DLUT.INIT[48] origin:010-clb-lutinit 26_51
CLBLL_L.SLICEL_X1.DLUT.INIT[49] origin:010-clb-lutinit 27_51
CLBLL_L.SLICEL_X1.DLUT.INIT[50] origin:010-clb-lutinit 26_50
CLBLL_L.SLICEL_X1.DLUT.INIT[51] origin:010-clb-lutinit 27_50
CLBLL_L.SLICEL_X1.DLUT.INIT[52] origin:010-clb-lutinit 26_49
CLBLL_L.SLICEL_X1.DLUT.INIT[53] origin:010-clb-lutinit 27_49
CLBLL_L.SLICEL_X1.DLUT.INIT[54] origin:010-clb-lutinit 26_48
CLBLL_L.SLICEL_X1.DLUT.INIT[55] origin:010-clb-lutinit 27_48
CLBLL_L.SLICEL_X1.DLUT.INIT[56] origin:010-clb-lutinit 29_51
CLBLL_L.SLICEL_X1.DLUT.INIT[57] origin:010-clb-lutinit 28_51
CLBLL_L.SLICEL_X1.DLUT.INIT[58] origin:010-clb-lutinit 29_50
CLBLL_L.SLICEL_X1.DLUT.INIT[59] origin:010-clb-lutinit 28_50
CLBLL_L.SLICEL_X1.DLUT.INIT[60] origin:010-clb-lutinit 29_49
CLBLL_L.SLICEL_X1.DLUT.INIT[61] origin:010-clb-lutinit 28_49
CLBLL_L.SLICEL_X1.DLUT.INIT[62] origin:010-clb-lutinit 29_48
CLBLL_L.SLICEL_X1.DLUT.INIT[63] origin:010-clb-lutinit 28_48
CLBLL_L.SLICEL_X1.DOUTMUX.CY origin:016-clb-noutmux !31_53 !31_56 30_53 31_57
CLBLL_L.SLICEL_X1.DOUTMUX.D5Q origin:016-clb-noutmux !30_53 !31_56 !31_57 31_53
CLBLL_L.SLICEL_X1.DOUTMUX.O5 origin:016-clb-noutmux !30_53 !31_53 31_56 31_57
CLBLL_L.SLICEL_X1.DOUTMUX.O6 origin:016-clb-noutmux !30_53 !31_53 !31_57 31_56
CLBLL_L.SLICEL_X1.DOUTMUX.XOR origin:016-clb-noutmux !31_53 !31_56 !31_57 30_53
CLBLL_L.SLICEL_X1.FFSYNC origin:011-clb-ffconfig 01_31
CLBLL_L.SLICEL_X1.LATCH origin:011-clb-ffconfig 31_32
CLBLL_L.SLICEL_X1.PRECYINIT.AX origin:017-clb-precyinit !01_11 !31_12 31_13
CLBLL_L.SLICEL_X1.PRECYINIT.C0 origin:017-clb-precyinit !01_11 !31_12 !31_13
CLBLL_L.SLICEL_X1.PRECYINIT.C1 origin:017-clb-precyinit !31_12 !31_13 01_11
CLBLL_L.SLICEL_X1.PRECYINIT.CIN origin:017-clb-precyinit !01_11 !31_13 31_12
CLBLL_L.SLICEL_X1.SRUSEDMUX origin:014-clb-ffsrcemux 00_32

678
zynq7/segbits_clbll_r.origin_info.db Normal file
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@ -0,0 +1,678 @@
CLBLL_R.SLICEL_X0.A5FF.ZINI origin:011-clb-ffconfig 31_06
CLBLL_R.SLICEL_X0.A5FF.ZRST origin:011-clb-ffconfig 01_07
CLBLL_R.SLICEL_X0.A5FFMUX.IN_A origin:012-clb-n5ffmux 30_09
CLBLL_R.SLICEL_X0.A5FFMUX.IN_B origin:012-clb-n5ffmux 30_10
CLBLL_R.SLICEL_X0.AFF.ZINI origin:011-clb-ffconfig 31_03
CLBLL_R.SLICEL_X0.AFF.ZRST origin:011-clb-ffconfig 30_12
CLBLL_R.SLICEL_X0.AFFMUX.AX origin:015-clb-nffmux !30_00 !30_02 !30_03 30_01
CLBLL_R.SLICEL_X0.AFFMUX.CY origin:015-clb-nffmux !30_01 !30_03 30_00 30_02
CLBLL_R.SLICEL_X0.AFFMUX.F7 origin:015-clb-nffmux !30_02 !30_03 30_00 30_01
CLBLL_R.SLICEL_X0.AFFMUX.O5 origin:015-clb-nffmux !30_01 !30_02 30_00 30_03
CLBLL_R.SLICEL_X0.AFFMUX.O6 origin:015-clb-nffmux !30_00 !30_01 !30_02 30_03
CLBLL_R.SLICEL_X0.AFFMUX.XOR origin:015-clb-nffmux !30_00 !30_01 !30_03 30_02
CLBLL_R.SLICEL_X0.ALUT.INIT[00] origin:010-clb-lutinit 32_15
CLBLL_R.SLICEL_X0.ALUT.INIT[01] origin:010-clb-lutinit 33_15
CLBLL_R.SLICEL_X0.ALUT.INIT[02] origin:010-clb-lutinit 32_14
CLBLL_R.SLICEL_X0.ALUT.INIT[03] origin:010-clb-lutinit 33_14
CLBLL_R.SLICEL_X0.ALUT.INIT[04] origin:010-clb-lutinit 32_13
CLBLL_R.SLICEL_X0.ALUT.INIT[05] origin:010-clb-lutinit 33_13
CLBLL_R.SLICEL_X0.ALUT.INIT[06] origin:010-clb-lutinit 32_12
CLBLL_R.SLICEL_X0.ALUT.INIT[07] origin:010-clb-lutinit 33_12
CLBLL_R.SLICEL_X0.ALUT.INIT[08] origin:010-clb-lutinit 35_15
CLBLL_R.SLICEL_X0.ALUT.INIT[09] origin:010-clb-lutinit 34_15
CLBLL_R.SLICEL_X0.ALUT.INIT[10] origin:010-clb-lutinit 35_14
CLBLL_R.SLICEL_X0.ALUT.INIT[11] origin:010-clb-lutinit 34_14
CLBLL_R.SLICEL_X0.ALUT.INIT[12] origin:010-clb-lutinit 35_13
CLBLL_R.SLICEL_X0.ALUT.INIT[13] origin:010-clb-lutinit 34_13
CLBLL_R.SLICEL_X0.ALUT.INIT[14] origin:010-clb-lutinit 35_12
CLBLL_R.SLICEL_X0.ALUT.INIT[15] origin:010-clb-lutinit 34_12
CLBLL_R.SLICEL_X0.ALUT.INIT[16] origin:010-clb-lutinit 32_11
CLBLL_R.SLICEL_X0.ALUT.INIT[17] origin:010-clb-lutinit 33_11
CLBLL_R.SLICEL_X0.ALUT.INIT[18] origin:010-clb-lutinit 32_10
CLBLL_R.SLICEL_X0.ALUT.INIT[19] origin:010-clb-lutinit 33_10
CLBLL_R.SLICEL_X0.ALUT.INIT[20] origin:010-clb-lutinit 32_09
CLBLL_R.SLICEL_X0.ALUT.INIT[21] origin:010-clb-lutinit 33_09
CLBLL_R.SLICEL_X0.ALUT.INIT[22] origin:010-clb-lutinit 32_08
CLBLL_R.SLICEL_X0.ALUT.INIT[23] origin:010-clb-lutinit 33_08
CLBLL_R.SLICEL_X0.ALUT.INIT[24] origin:010-clb-lutinit 35_11
CLBLL_R.SLICEL_X0.ALUT.INIT[25] origin:010-clb-lutinit 34_11
CLBLL_R.SLICEL_X0.ALUT.INIT[26] origin:010-clb-lutinit 35_10
CLBLL_R.SLICEL_X0.ALUT.INIT[27] origin:010-clb-lutinit 34_10
CLBLL_R.SLICEL_X0.ALUT.INIT[28] origin:010-clb-lutinit 35_09
CLBLL_R.SLICEL_X0.ALUT.INIT[29] origin:010-clb-lutinit 34_09
CLBLL_R.SLICEL_X0.ALUT.INIT[30] origin:010-clb-lutinit 35_08
CLBLL_R.SLICEL_X0.ALUT.INIT[31] origin:010-clb-lutinit 34_08
CLBLL_R.SLICEL_X0.ALUT.INIT[32] origin:010-clb-lutinit 32_07
CLBLL_R.SLICEL_X0.ALUT.INIT[33] origin:010-clb-lutinit 33_07
CLBLL_R.SLICEL_X0.ALUT.INIT[34] origin:010-clb-lutinit 32_06
CLBLL_R.SLICEL_X0.ALUT.INIT[35] origin:010-clb-lutinit 33_06
CLBLL_R.SLICEL_X0.ALUT.INIT[36] origin:010-clb-lutinit 32_05
CLBLL_R.SLICEL_X0.ALUT.INIT[37] origin:010-clb-lutinit 33_05
CLBLL_R.SLICEL_X0.ALUT.INIT[38] origin:010-clb-lutinit 32_04
CLBLL_R.SLICEL_X0.ALUT.INIT[39] origin:010-clb-lutinit 33_04
CLBLL_R.SLICEL_X0.ALUT.INIT[40] origin:010-clb-lutinit 35_07
CLBLL_R.SLICEL_X0.ALUT.INIT[41] origin:010-clb-lutinit 34_07
CLBLL_R.SLICEL_X0.ALUT.INIT[42] origin:010-clb-lutinit 35_06
CLBLL_R.SLICEL_X0.ALUT.INIT[43] origin:010-clb-lutinit 34_06
CLBLL_R.SLICEL_X0.ALUT.INIT[44] origin:010-clb-lutinit 35_05
CLBLL_R.SLICEL_X0.ALUT.INIT[45] origin:010-clb-lutinit 34_05
CLBLL_R.SLICEL_X0.ALUT.INIT[46] origin:010-clb-lutinit 35_04
CLBLL_R.SLICEL_X0.ALUT.INIT[47] origin:010-clb-lutinit 34_04
CLBLL_R.SLICEL_X0.ALUT.INIT[48] origin:010-clb-lutinit 32_03
CLBLL_R.SLICEL_X0.ALUT.INIT[49] origin:010-clb-lutinit 33_03
CLBLL_R.SLICEL_X0.ALUT.INIT[50] origin:010-clb-lutinit 32_02
CLBLL_R.SLICEL_X0.ALUT.INIT[51] origin:010-clb-lutinit 33_02
CLBLL_R.SLICEL_X0.ALUT.INIT[52] origin:010-clb-lutinit 32_01
CLBLL_R.SLICEL_X0.ALUT.INIT[53] origin:010-clb-lutinit 33_01
CLBLL_R.SLICEL_X0.ALUT.INIT[54] origin:010-clb-lutinit 32_00
CLBLL_R.SLICEL_X0.ALUT.INIT[55] origin:010-clb-lutinit 33_00
CLBLL_R.SLICEL_X0.ALUT.INIT[56] origin:010-clb-lutinit 35_03
CLBLL_R.SLICEL_X0.ALUT.INIT[57] origin:010-clb-lutinit 34_03
CLBLL_R.SLICEL_X0.ALUT.INIT[58] origin:010-clb-lutinit 35_02
CLBLL_R.SLICEL_X0.ALUT.INIT[59] origin:010-clb-lutinit 34_02
CLBLL_R.SLICEL_X0.ALUT.INIT[60] origin:010-clb-lutinit 35_01
CLBLL_R.SLICEL_X0.ALUT.INIT[61] origin:010-clb-lutinit 34_01
CLBLL_R.SLICEL_X0.ALUT.INIT[62] origin:010-clb-lutinit 35_00
CLBLL_R.SLICEL_X0.ALUT.INIT[63] origin:010-clb-lutinit 34_00
CLBLL_R.SLICEL_X0.AOUTMUX.A5Q origin:016-clb-noutmux !30_06 !30_08 !30_11 30_07
CLBLL_R.SLICEL_X0.AOUTMUX.CY origin:016-clb-noutmux !30_07 !30_11 30_06 30_08
CLBLL_R.SLICEL_X0.AOUTMUX.F7 origin:016-clb-noutmux !30_08 !30_11 30_06 30_07
CLBLL_R.SLICEL_X0.AOUTMUX.O5 origin:016-clb-noutmux !30_07 !30_08 30_06 30_11
CLBLL_R.SLICEL_X0.AOUTMUX.O6 origin:016-clb-noutmux !30_06 !30_07 !30_08 30_11
CLBLL_R.SLICEL_X0.AOUTMUX.XOR origin:016-clb-noutmux !30_06 !30_07 !30_11 30_08
CLBLL_R.SLICEL_X0.B5FF.ZINI origin:011-clb-ffconfig 31_22
CLBLL_R.SLICEL_X0.B5FF.ZRST origin:011-clb-ffconfig 01_19
CLBLL_R.SLICEL_X0.B5FFMUX.IN_A origin:012-clb-n5ffmux 30_19
CLBLL_R.SLICEL_X0.B5FFMUX.IN_B origin:012-clb-n5ffmux 30_18
CLBLL_R.SLICEL_X0.BFF.ZINI origin:011-clb-ffconfig 31_28
CLBLL_R.SLICEL_X0.BFF.ZRST origin:011-clb-ffconfig 30_30
CLBLL_R.SLICEL_X0.BFFMUX.BX origin:015-clb-nffmux !30_24 !30_25 !30_27 30_26
CLBLL_R.SLICEL_X0.BFFMUX.CY origin:015-clb-nffmux !30_24 !30_26 30_25 30_27
CLBLL_R.SLICEL_X0.BFFMUX.F8 origin:015-clb-nffmux !30_24 !30_25 30_26 30_27
CLBLL_R.SLICEL_X0.BFFMUX.O5 origin:015-clb-nffmux !30_25 !30_26 30_24 30_27
CLBLL_R.SLICEL_X0.BFFMUX.O6 origin:015-clb-nffmux !30_25 !30_26 !30_27 30_24
CLBLL_R.SLICEL_X0.BFFMUX.XOR origin:015-clb-nffmux !30_24 !30_26 !30_27 30_25
CLBLL_R.SLICEL_X0.BLUT.INIT[00] origin:010-clb-lutinit 32_31
CLBLL_R.SLICEL_X0.BLUT.INIT[01] origin:010-clb-lutinit 33_31
CLBLL_R.SLICEL_X0.BLUT.INIT[02] origin:010-clb-lutinit 32_30
CLBLL_R.SLICEL_X0.BLUT.INIT[03] origin:010-clb-lutinit 33_30
CLBLL_R.SLICEL_X0.BLUT.INIT[04] origin:010-clb-lutinit 32_29
CLBLL_R.SLICEL_X0.BLUT.INIT[05] origin:010-clb-lutinit 33_29
CLBLL_R.SLICEL_X0.BLUT.INIT[06] origin:010-clb-lutinit 32_28
CLBLL_R.SLICEL_X0.BLUT.INIT[07] origin:010-clb-lutinit 33_28
CLBLL_R.SLICEL_X0.BLUT.INIT[08] origin:010-clb-lutinit 35_31
CLBLL_R.SLICEL_X0.BLUT.INIT[09] origin:010-clb-lutinit 34_31
CLBLL_R.SLICEL_X0.BLUT.INIT[10] origin:010-clb-lutinit 35_30
CLBLL_R.SLICEL_X0.BLUT.INIT[11] origin:010-clb-lutinit 34_30
CLBLL_R.SLICEL_X0.BLUT.INIT[12] origin:010-clb-lutinit 35_29
CLBLL_R.SLICEL_X0.BLUT.INIT[13] origin:010-clb-lutinit 34_29
CLBLL_R.SLICEL_X0.BLUT.INIT[14] origin:010-clb-lutinit 35_28
CLBLL_R.SLICEL_X0.BLUT.INIT[15] origin:010-clb-lutinit 34_28
CLBLL_R.SLICEL_X0.BLUT.INIT[16] origin:010-clb-lutinit 32_27
CLBLL_R.SLICEL_X0.BLUT.INIT[17] origin:010-clb-lutinit 33_27
CLBLL_R.SLICEL_X0.BLUT.INIT[18] origin:010-clb-lutinit 32_26
CLBLL_R.SLICEL_X0.BLUT.INIT[19] origin:010-clb-lutinit 33_26
CLBLL_R.SLICEL_X0.BLUT.INIT[20] origin:010-clb-lutinit 32_25
CLBLL_R.SLICEL_X0.BLUT.INIT[21] origin:010-clb-lutinit 33_25
CLBLL_R.SLICEL_X0.BLUT.INIT[22] origin:010-clb-lutinit 32_24
CLBLL_R.SLICEL_X0.BLUT.INIT[23] origin:010-clb-lutinit 33_24
CLBLL_R.SLICEL_X0.BLUT.INIT[24] origin:010-clb-lutinit 35_27
CLBLL_R.SLICEL_X0.BLUT.INIT[25] origin:010-clb-lutinit 34_27
CLBLL_R.SLICEL_X0.BLUT.INIT[26] origin:010-clb-lutinit 35_26
CLBLL_R.SLICEL_X0.BLUT.INIT[27] origin:010-clb-lutinit 34_26
CLBLL_R.SLICEL_X0.BLUT.INIT[28] origin:010-clb-lutinit 35_25
CLBLL_R.SLICEL_X0.BLUT.INIT[29] origin:010-clb-lutinit 34_25
CLBLL_R.SLICEL_X0.BLUT.INIT[30] origin:010-clb-lutinit 35_24
CLBLL_R.SLICEL_X0.BLUT.INIT[31] origin:010-clb-lutinit 34_24
CLBLL_R.SLICEL_X0.BLUT.INIT[32] origin:010-clb-lutinit 32_23
CLBLL_R.SLICEL_X0.BLUT.INIT[33] origin:010-clb-lutinit 33_23
CLBLL_R.SLICEL_X0.BLUT.INIT[34] origin:010-clb-lutinit 32_22
CLBLL_R.SLICEL_X0.BLUT.INIT[35] origin:010-clb-lutinit 33_22
CLBLL_R.SLICEL_X0.BLUT.INIT[36] origin:010-clb-lutinit 32_21
CLBLL_R.SLICEL_X0.BLUT.INIT[37] origin:010-clb-lutinit 33_21
CLBLL_R.SLICEL_X0.BLUT.INIT[38] origin:010-clb-lutinit 32_20
CLBLL_R.SLICEL_X0.BLUT.INIT[39] origin:010-clb-lutinit 33_20
CLBLL_R.SLICEL_X0.BLUT.INIT[40] origin:010-clb-lutinit 35_23
CLBLL_R.SLICEL_X0.BLUT.INIT[41] origin:010-clb-lutinit 34_23
CLBLL_R.SLICEL_X0.BLUT.INIT[42] origin:010-clb-lutinit 35_22
CLBLL_R.SLICEL_X0.BLUT.INIT[43] origin:010-clb-lutinit 34_22
CLBLL_R.SLICEL_X0.BLUT.INIT[44] origin:010-clb-lutinit 35_21
CLBLL_R.SLICEL_X0.BLUT.INIT[45] origin:010-clb-lutinit 34_21
CLBLL_R.SLICEL_X0.BLUT.INIT[46] origin:010-clb-lutinit 35_20
CLBLL_R.SLICEL_X0.BLUT.INIT[47] origin:010-clb-lutinit 34_20
CLBLL_R.SLICEL_X0.BLUT.INIT[48] origin:010-clb-lutinit 32_19
CLBLL_R.SLICEL_X0.BLUT.INIT[49] origin:010-clb-lutinit 33_19
CLBLL_R.SLICEL_X0.BLUT.INIT[50] origin:010-clb-lutinit 32_18
CLBLL_R.SLICEL_X0.BLUT.INIT[51] origin:010-clb-lutinit 33_18
CLBLL_R.SLICEL_X0.BLUT.INIT[52] origin:010-clb-lutinit 32_17
CLBLL_R.SLICEL_X0.BLUT.INIT[53] origin:010-clb-lutinit 33_17
CLBLL_R.SLICEL_X0.BLUT.INIT[54] origin:010-clb-lutinit 32_16
CLBLL_R.SLICEL_X0.BLUT.INIT[55] origin:010-clb-lutinit 33_16
CLBLL_R.SLICEL_X0.BLUT.INIT[56] origin:010-clb-lutinit 35_19
CLBLL_R.SLICEL_X0.BLUT.INIT[57] origin:010-clb-lutinit 34_19
CLBLL_R.SLICEL_X0.BLUT.INIT[58] origin:010-clb-lutinit 35_18
CLBLL_R.SLICEL_X0.BLUT.INIT[59] origin:010-clb-lutinit 34_18
CLBLL_R.SLICEL_X0.BLUT.INIT[60] origin:010-clb-lutinit 35_17
CLBLL_R.SLICEL_X0.BLUT.INIT[61] origin:010-clb-lutinit 34_17
CLBLL_R.SLICEL_X0.BLUT.INIT[62] origin:010-clb-lutinit 35_16
CLBLL_R.SLICEL_X0.BLUT.INIT[63] origin:010-clb-lutinit 34_16
CLBLL_R.SLICEL_X0.BOUTMUX.B5Q origin:016-clb-noutmux !30_20 !30_21 !30_22 30_23
CLBLL_R.SLICEL_X0.BOUTMUX.CY origin:016-clb-noutmux !30_20 !30_23 30_21 30_22
CLBLL_R.SLICEL_X0.BOUTMUX.F8 origin:016-clb-noutmux !30_20 !30_21 30_22 30_23
CLBLL_R.SLICEL_X0.BOUTMUX.O5 origin:016-clb-noutmux !30_21 !30_23 30_20 30_22
CLBLL_R.SLICEL_X0.BOUTMUX.O6 origin:016-clb-noutmux !30_21 !30_22 !30_23 30_20
CLBLL_R.SLICEL_X0.BOUTMUX.XOR origin:016-clb-noutmux !30_20 !30_22 !30_23 30_21
CLBLL_R.SLICEL_X0.C5FF.ZINI origin:011-clb-ffconfig 31_41
CLBLL_R.SLICEL_X0.C5FF.ZRST origin:011-clb-ffconfig 01_47
CLBLL_R.SLICEL_X0.C5FFMUX.IN_A origin:012-clb-n5ffmux 31_45
CLBLL_R.SLICEL_X0.C5FFMUX.IN_B origin:012-clb-n5ffmux 30_39
CLBLL_R.SLICEL_X0.CARRY4.ACY0 origin:013-clb-ncy0 30_15
CLBLL_R.SLICEL_X0.CARRY4.BCY0 origin:013-clb-ncy0 01_15
CLBLL_R.SLICEL_X0.CARRY4.CCY0 origin:013-clb-ncy0 30_48
CLBLL_R.SLICEL_X0.CARRY4.DCY0 origin:013-clb-ncy0 30_49
CLBLL_R.SLICEL_X0.CEUSEDMUX origin:014-clb-ffsrcemux 01_39
CLBLL_R.SLICEL_X0.CFF.ZINI origin:011-clb-ffconfig 31_33
CLBLL_R.SLICEL_X0.CFF.ZRST origin:011-clb-ffconfig 30_33
CLBLL_R.SLICEL_X0.CFFMUX.CX origin:015-clb-nffmux !30_35 !30_37 !30_38 30_36
CLBLL_R.SLICEL_X0.CFFMUX.CY origin:015-clb-nffmux !30_36 !30_38 30_35 30_37
CLBLL_R.SLICEL_X0.CFFMUX.F7 origin:015-clb-nffmux !30_37 !30_38 30_35 30_36
CLBLL_R.SLICEL_X0.CFFMUX.O5 origin:015-clb-nffmux !30_36 !30_37 30_35 30_38
CLBLL_R.SLICEL_X0.CFFMUX.O6 origin:015-clb-nffmux !30_35 !30_36 !30_37 30_38
CLBLL_R.SLICEL_X0.CFFMUX.XOR origin:015-clb-nffmux !30_35 !30_36 !30_38 30_37
CLBLL_R.SLICEL_X0.CLKINV origin:011-clb-ffconfig 01_51
CLBLL_R.SLICEL_X0.CLUT.INIT[00] origin:010-clb-lutinit 32_47
CLBLL_R.SLICEL_X0.CLUT.INIT[01] origin:010-clb-lutinit 33_47
CLBLL_R.SLICEL_X0.CLUT.INIT[02] origin:010-clb-lutinit 32_46
CLBLL_R.SLICEL_X0.CLUT.INIT[03] origin:010-clb-lutinit 33_46
CLBLL_R.SLICEL_X0.CLUT.INIT[04] origin:010-clb-lutinit 32_45
CLBLL_R.SLICEL_X0.CLUT.INIT[05] origin:010-clb-lutinit 33_45
CLBLL_R.SLICEL_X0.CLUT.INIT[06] origin:010-clb-lutinit 32_44
CLBLL_R.SLICEL_X0.CLUT.INIT[07] origin:010-clb-lutinit 33_44
CLBLL_R.SLICEL_X0.CLUT.INIT[08] origin:010-clb-lutinit 35_47
CLBLL_R.SLICEL_X0.CLUT.INIT[09] origin:010-clb-lutinit 34_47
CLBLL_R.SLICEL_X0.CLUT.INIT[10] origin:010-clb-lutinit 35_46
CLBLL_R.SLICEL_X0.CLUT.INIT[11] origin:010-clb-lutinit 34_46
CLBLL_R.SLICEL_X0.CLUT.INIT[12] origin:010-clb-lutinit 35_45
CLBLL_R.SLICEL_X0.CLUT.INIT[13] origin:010-clb-lutinit 34_45
CLBLL_R.SLICEL_X0.CLUT.INIT[14] origin:010-clb-lutinit 35_44
CLBLL_R.SLICEL_X0.CLUT.INIT[15] origin:010-clb-lutinit 34_44
CLBLL_R.SLICEL_X0.CLUT.INIT[16] origin:010-clb-lutinit 32_43
CLBLL_R.SLICEL_X0.CLUT.INIT[17] origin:010-clb-lutinit 33_43
CLBLL_R.SLICEL_X0.CLUT.INIT[18] origin:010-clb-lutinit 32_42
CLBLL_R.SLICEL_X0.CLUT.INIT[19] origin:010-clb-lutinit 33_42
CLBLL_R.SLICEL_X0.CLUT.INIT[20] origin:010-clb-lutinit 32_41
CLBLL_R.SLICEL_X0.CLUT.INIT[21] origin:010-clb-lutinit 33_41
CLBLL_R.SLICEL_X0.CLUT.INIT[22] origin:010-clb-lutinit 32_40
CLBLL_R.SLICEL_X0.CLUT.INIT[23] origin:010-clb-lutinit 33_40
CLBLL_R.SLICEL_X0.CLUT.INIT[24] origin:010-clb-lutinit 35_43
CLBLL_R.SLICEL_X0.CLUT.INIT[25] origin:010-clb-lutinit 34_43
CLBLL_R.SLICEL_X0.CLUT.INIT[26] origin:010-clb-lutinit 35_42
CLBLL_R.SLICEL_X0.CLUT.INIT[27] origin:010-clb-lutinit 34_42
CLBLL_R.SLICEL_X0.CLUT.INIT[28] origin:010-clb-lutinit 35_41
CLBLL_R.SLICEL_X0.CLUT.INIT[29] origin:010-clb-lutinit 34_41
CLBLL_R.SLICEL_X0.CLUT.INIT[30] origin:010-clb-lutinit 35_40
CLBLL_R.SLICEL_X0.CLUT.INIT[31] origin:010-clb-lutinit 34_40
CLBLL_R.SLICEL_X0.CLUT.INIT[32] origin:010-clb-lutinit 32_39
CLBLL_R.SLICEL_X0.CLUT.INIT[33] origin:010-clb-lutinit 33_39
CLBLL_R.SLICEL_X0.CLUT.INIT[34] origin:010-clb-lutinit 32_38
CLBLL_R.SLICEL_X0.CLUT.INIT[35] origin:010-clb-lutinit 33_38
CLBLL_R.SLICEL_X0.CLUT.INIT[36] origin:010-clb-lutinit 32_37
CLBLL_R.SLICEL_X0.CLUT.INIT[37] origin:010-clb-lutinit 33_37
CLBLL_R.SLICEL_X0.CLUT.INIT[38] origin:010-clb-lutinit 32_36
CLBLL_R.SLICEL_X0.CLUT.INIT[39] origin:010-clb-lutinit 33_36
CLBLL_R.SLICEL_X0.CLUT.INIT[40] origin:010-clb-lutinit 35_39
CLBLL_R.SLICEL_X0.CLUT.INIT[41] origin:010-clb-lutinit 34_39
CLBLL_R.SLICEL_X0.CLUT.INIT[42] origin:010-clb-lutinit 35_38
CLBLL_R.SLICEL_X0.CLUT.INIT[43] origin:010-clb-lutinit 34_38
CLBLL_R.SLICEL_X0.CLUT.INIT[44] origin:010-clb-lutinit 35_37
CLBLL_R.SLICEL_X0.CLUT.INIT[45] origin:010-clb-lutinit 34_37
CLBLL_R.SLICEL_X0.CLUT.INIT[46] origin:010-clb-lutinit 35_36
CLBLL_R.SLICEL_X0.CLUT.INIT[47] origin:010-clb-lutinit 34_36
CLBLL_R.SLICEL_X0.CLUT.INIT[48] origin:010-clb-lutinit 32_35
CLBLL_R.SLICEL_X0.CLUT.INIT[49] origin:010-clb-lutinit 33_35
CLBLL_R.SLICEL_X0.CLUT.INIT[50] origin:010-clb-lutinit 32_34
CLBLL_R.SLICEL_X0.CLUT.INIT[51] origin:010-clb-lutinit 33_34
CLBLL_R.SLICEL_X0.CLUT.INIT[52] origin:010-clb-lutinit 32_33
CLBLL_R.SLICEL_X0.CLUT.INIT[53] origin:010-clb-lutinit 33_33
CLBLL_R.SLICEL_X0.CLUT.INIT[54] origin:010-clb-lutinit 32_32
CLBLL_R.SLICEL_X0.CLUT.INIT[55] origin:010-clb-lutinit 33_32
CLBLL_R.SLICEL_X0.CLUT.INIT[56] origin:010-clb-lutinit 35_35
CLBLL_R.SLICEL_X0.CLUT.INIT[57] origin:010-clb-lutinit 34_35
CLBLL_R.SLICEL_X0.CLUT.INIT[58] origin:010-clb-lutinit 35_34
CLBLL_R.SLICEL_X0.CLUT.INIT[59] origin:010-clb-lutinit 34_34
CLBLL_R.SLICEL_X0.CLUT.INIT[60] origin:010-clb-lutinit 35_33
CLBLL_R.SLICEL_X0.CLUT.INIT[61] origin:010-clb-lutinit 34_33
CLBLL_R.SLICEL_X0.CLUT.INIT[62] origin:010-clb-lutinit 35_32
CLBLL_R.SLICEL_X0.CLUT.INIT[63] origin:010-clb-lutinit 34_32
CLBLL_R.SLICEL_X0.COUTMUX.C5Q origin:016-clb-noutmux !30_40 !30_44 !30_45 30_43
CLBLL_R.SLICEL_X0.COUTMUX.CY origin:016-clb-noutmux !30_43 !30_45 30_40 30_44
CLBLL_R.SLICEL_X0.COUTMUX.F7 origin:016-clb-noutmux !30_44 !30_45 30_40 30_43
CLBLL_R.SLICEL_X0.COUTMUX.O5 origin:016-clb-noutmux !30_43 !30_44 30_40 30_45
CLBLL_R.SLICEL_X0.COUTMUX.O6 origin:016-clb-noutmux !30_40 !30_43 !30_44 30_45
CLBLL_R.SLICEL_X0.COUTMUX.XOR origin:016-clb-noutmux !30_40 !30_43 !30_45 30_44
CLBLL_R.SLICEL_X0.D5FF.ZINI origin:011-clb-ffconfig 31_51
CLBLL_R.SLICEL_X0.D5FF.ZRST origin:011-clb-ffconfig 01_55
CLBLL_R.SLICEL_X0.D5FFMUX.IN_A origin:012-clb-n5ffmux 30_55
CLBLL_R.SLICEL_X0.D5FFMUX.IN_B origin:012-clb-n5ffmux 30_54
CLBLL_R.SLICEL_X0.DFF.ZINI origin:011-clb-ffconfig 31_58
CLBLL_R.SLICEL_X0.DFF.ZRST origin:011-clb-ffconfig 30_50
CLBLL_R.SLICEL_X0.DFFMUX.CY origin:015-clb-nffmux !30_59 !30_61 30_60 30_62
CLBLL_R.SLICEL_X0.DFFMUX.DX origin:015-clb-nffmux !30_59 !30_60 !30_62 30_61
CLBLL_R.SLICEL_X0.DFFMUX.O5 origin:015-clb-nffmux !30_60 !30_61 30_59 30_62
CLBLL_R.SLICEL_X0.DFFMUX.O6 origin:015-clb-nffmux !30_60 !30_61 !30_62 30_59
CLBLL_R.SLICEL_X0.DFFMUX.XOR origin:015-clb-nffmux !30_59 !30_61 !30_62 30_60
CLBLL_R.SLICEL_X0.DLUT.INIT[00] origin:010-clb-lutinit 32_63
CLBLL_R.SLICEL_X0.DLUT.INIT[01] origin:010-clb-lutinit 33_63
CLBLL_R.SLICEL_X0.DLUT.INIT[02] origin:010-clb-lutinit 32_62
CLBLL_R.SLICEL_X0.DLUT.INIT[03] origin:010-clb-lutinit 33_62
CLBLL_R.SLICEL_X0.DLUT.INIT[04] origin:010-clb-lutinit 32_61
CLBLL_R.SLICEL_X0.DLUT.INIT[05] origin:010-clb-lutinit 33_61
CLBLL_R.SLICEL_X0.DLUT.INIT[06] origin:010-clb-lutinit 32_60
CLBLL_R.SLICEL_X0.DLUT.INIT[07] origin:010-clb-lutinit 33_60
CLBLL_R.SLICEL_X0.DLUT.INIT[08] origin:010-clb-lutinit 35_63
CLBLL_R.SLICEL_X0.DLUT.INIT[09] origin:010-clb-lutinit 34_63
CLBLL_R.SLICEL_X0.DLUT.INIT[10] origin:010-clb-lutinit 35_62
CLBLL_R.SLICEL_X0.DLUT.INIT[11] origin:010-clb-lutinit 34_62
CLBLL_R.SLICEL_X0.DLUT.INIT[12] origin:010-clb-lutinit 35_61
CLBLL_R.SLICEL_X0.DLUT.INIT[13] origin:010-clb-lutinit 34_61
CLBLL_R.SLICEL_X0.DLUT.INIT[14] origin:010-clb-lutinit 35_60
CLBLL_R.SLICEL_X0.DLUT.INIT[15] origin:010-clb-lutinit 34_60
CLBLL_R.SLICEL_X0.DLUT.INIT[16] origin:010-clb-lutinit 32_59
CLBLL_R.SLICEL_X0.DLUT.INIT[17] origin:010-clb-lutinit 33_59
CLBLL_R.SLICEL_X0.DLUT.INIT[18] origin:010-clb-lutinit 32_58
CLBLL_R.SLICEL_X0.DLUT.INIT[19] origin:010-clb-lutinit 33_58
CLBLL_R.SLICEL_X0.DLUT.INIT[20] origin:010-clb-lutinit 32_57
CLBLL_R.SLICEL_X0.DLUT.INIT[21] origin:010-clb-lutinit 33_57
CLBLL_R.SLICEL_X0.DLUT.INIT[22] origin:010-clb-lutinit 32_56
CLBLL_R.SLICEL_X0.DLUT.INIT[23] origin:010-clb-lutinit 33_56
CLBLL_R.SLICEL_X0.DLUT.INIT[24] origin:010-clb-lutinit 35_59
CLBLL_R.SLICEL_X0.DLUT.INIT[25] origin:010-clb-lutinit 34_59
CLBLL_R.SLICEL_X0.DLUT.INIT[26] origin:010-clb-lutinit 35_58
CLBLL_R.SLICEL_X0.DLUT.INIT[27] origin:010-clb-lutinit 34_58
CLBLL_R.SLICEL_X0.DLUT.INIT[28] origin:010-clb-lutinit 35_57
CLBLL_R.SLICEL_X0.DLUT.INIT[29] origin:010-clb-lutinit 34_57
CLBLL_R.SLICEL_X0.DLUT.INIT[30] origin:010-clb-lutinit 35_56
CLBLL_R.SLICEL_X0.DLUT.INIT[31] origin:010-clb-lutinit 34_56
CLBLL_R.SLICEL_X0.DLUT.INIT[32] origin:010-clb-lutinit 32_55
CLBLL_R.SLICEL_X0.DLUT.INIT[33] origin:010-clb-lutinit 33_55
CLBLL_R.SLICEL_X0.DLUT.INIT[34] origin:010-clb-lutinit 32_54
CLBLL_R.SLICEL_X0.DLUT.INIT[35] origin:010-clb-lutinit 33_54
CLBLL_R.SLICEL_X0.DLUT.INIT[36] origin:010-clb-lutinit 32_53
CLBLL_R.SLICEL_X0.DLUT.INIT[37] origin:010-clb-lutinit 33_53
CLBLL_R.SLICEL_X0.DLUT.INIT[38] origin:010-clb-lutinit 32_52
CLBLL_R.SLICEL_X0.DLUT.INIT[39] origin:010-clb-lutinit 33_52
CLBLL_R.SLICEL_X0.DLUT.INIT[40] origin:010-clb-lutinit 35_55
CLBLL_R.SLICEL_X0.DLUT.INIT[41] origin:010-clb-lutinit 34_55
CLBLL_R.SLICEL_X0.DLUT.INIT[42] origin:010-clb-lutinit 35_54
CLBLL_R.SLICEL_X0.DLUT.INIT[43] origin:010-clb-lutinit 34_54
CLBLL_R.SLICEL_X0.DLUT.INIT[44] origin:010-clb-lutinit 35_53
CLBLL_R.SLICEL_X0.DLUT.INIT[45] origin:010-clb-lutinit 34_53
CLBLL_R.SLICEL_X0.DLUT.INIT[46] origin:010-clb-lutinit 35_52
CLBLL_R.SLICEL_X0.DLUT.INIT[47] origin:010-clb-lutinit 34_52
CLBLL_R.SLICEL_X0.DLUT.INIT[48] origin:010-clb-lutinit 32_51
CLBLL_R.SLICEL_X0.DLUT.INIT[49] origin:010-clb-lutinit 33_51
CLBLL_R.SLICEL_X0.DLUT.INIT[50] origin:010-clb-lutinit 32_50
CLBLL_R.SLICEL_X0.DLUT.INIT[51] origin:010-clb-lutinit 33_50
CLBLL_R.SLICEL_X0.DLUT.INIT[52] origin:010-clb-lutinit 32_49
CLBLL_R.SLICEL_X0.DLUT.INIT[53] origin:010-clb-lutinit 33_49
CLBLL_R.SLICEL_X0.DLUT.INIT[54] origin:010-clb-lutinit 32_48
CLBLL_R.SLICEL_X0.DLUT.INIT[55] origin:010-clb-lutinit 33_48
CLBLL_R.SLICEL_X0.DLUT.INIT[56] origin:010-clb-lutinit 35_51
CLBLL_R.SLICEL_X0.DLUT.INIT[57] origin:010-clb-lutinit 34_51
CLBLL_R.SLICEL_X0.DLUT.INIT[58] origin:010-clb-lutinit 35_50
CLBLL_R.SLICEL_X0.DLUT.INIT[59] origin:010-clb-lutinit 34_50
CLBLL_R.SLICEL_X0.DLUT.INIT[60] origin:010-clb-lutinit 35_49
CLBLL_R.SLICEL_X0.DLUT.INIT[61] origin:010-clb-lutinit 34_49
CLBLL_R.SLICEL_X0.DLUT.INIT[62] origin:010-clb-lutinit 35_48
CLBLL_R.SLICEL_X0.DLUT.INIT[63] origin:010-clb-lutinit 34_48
CLBLL_R.SLICEL_X0.DOUTMUX.CY origin:016-clb-noutmux !30_56 !30_57 30_51 30_52
CLBLL_R.SLICEL_X0.DOUTMUX.D5Q origin:016-clb-noutmux !30_51 !30_52 !30_56 30_57
CLBLL_R.SLICEL_X0.DOUTMUX.O5 origin:016-clb-noutmux !30_51 !30_57 30_52 30_56
CLBLL_R.SLICEL_X0.DOUTMUX.O6 origin:016-clb-noutmux !30_51 !30_52 !30_57 30_56
CLBLL_R.SLICEL_X0.DOUTMUX.XOR origin:016-clb-noutmux !30_52 !30_56 !30_57 30_51
CLBLL_R.SLICEL_X0.FFSYNC origin:011-clb-ffconfig 00_48
CLBLL_R.SLICEL_X0.LATCH origin:011-clb-ffconfig 30_32
CLBLL_R.SLICEL_X0.PRECYINIT.AX origin:017-clb-precyinit !00_12 !30_13 30_14
CLBLL_R.SLICEL_X0.PRECYINIT.C0 origin:017-clb-precyinit !00_12 !30_13 !30_14
CLBLL_R.SLICEL_X0.PRECYINIT.C1 origin:017-clb-precyinit !30_13 !30_14 00_12
CLBLL_R.SLICEL_X0.PRECYINIT.CIN origin:017-clb-precyinit !00_12 !30_14 30_13
CLBLL_R.SLICEL_X0.SRUSEDMUX origin:014-clb-ffsrcemux 01_35
CLBLL_R.SLICEL_X1.A5FF.ZINI origin:011-clb-ffconfig 31_05
CLBLL_R.SLICEL_X1.A5FF.ZRST origin:011-clb-ffconfig 01_03
CLBLL_R.SLICEL_X1.A5FFMUX.IN_A origin:012-clb-n5ffmux 31_08
CLBLL_R.SLICEL_X1.A5FFMUX.IN_B origin:012-clb-n5ffmux 31_11
CLBLL_R.SLICEL_X1.AFF.ZINI origin:011-clb-ffconfig 31_04
CLBLL_R.SLICEL_X1.AFF.ZRST origin:011-clb-ffconfig 31_15
CLBLL_R.SLICEL_X1.AFFMUX.AX origin:015-clb-nffmux !30_04 !31_00 !31_02 31_01
CLBLL_R.SLICEL_X1.AFFMUX.CY origin:015-clb-nffmux !30_04 !31_01 31_00 31_02
CLBLL_R.SLICEL_X1.AFFMUX.F7 origin:015-clb-nffmux !30_04 !31_02 31_00 31_01
CLBLL_R.SLICEL_X1.AFFMUX.O5 origin:015-clb-nffmux !31_01 !31_02 30_04 31_00
CLBLL_R.SLICEL_X1.AFFMUX.O6 origin:015-clb-nffmux !31_00 !31_01 !31_02 30_04
CLBLL_R.SLICEL_X1.AFFMUX.XOR origin:015-clb-nffmux !30_04 !31_00 !31_01 31_02
CLBLL_R.SLICEL_X1.ALUT.INIT[00] origin:010-clb-lutinit 26_15
CLBLL_R.SLICEL_X1.ALUT.INIT[01] origin:010-clb-lutinit 27_15
CLBLL_R.SLICEL_X1.ALUT.INIT[02] origin:010-clb-lutinit 26_14
CLBLL_R.SLICEL_X1.ALUT.INIT[03] origin:010-clb-lutinit 27_14
CLBLL_R.SLICEL_X1.ALUT.INIT[04] origin:010-clb-lutinit 26_13
CLBLL_R.SLICEL_X1.ALUT.INIT[05] origin:010-clb-lutinit 27_13
CLBLL_R.SLICEL_X1.ALUT.INIT[06] origin:010-clb-lutinit 26_12
CLBLL_R.SLICEL_X1.ALUT.INIT[07] origin:010-clb-lutinit 27_12
CLBLL_R.SLICEL_X1.ALUT.INIT[08] origin:010-clb-lutinit 29_15
CLBLL_R.SLICEL_X1.ALUT.INIT[09] origin:010-clb-lutinit 28_15
CLBLL_R.SLICEL_X1.ALUT.INIT[10] origin:010-clb-lutinit 29_14
CLBLL_R.SLICEL_X1.ALUT.INIT[11] origin:010-clb-lutinit 28_14
CLBLL_R.SLICEL_X1.ALUT.INIT[12] origin:010-clb-lutinit 29_13
CLBLL_R.SLICEL_X1.ALUT.INIT[13] origin:010-clb-lutinit 28_13
CLBLL_R.SLICEL_X1.ALUT.INIT[14] origin:010-clb-lutinit 29_12
CLBLL_R.SLICEL_X1.ALUT.INIT[15] origin:010-clb-lutinit 28_12
CLBLL_R.SLICEL_X1.ALUT.INIT[16] origin:010-clb-lutinit 26_11
CLBLL_R.SLICEL_X1.ALUT.INIT[17] origin:010-clb-lutinit 27_11
CLBLL_R.SLICEL_X1.ALUT.INIT[18] origin:010-clb-lutinit 26_10
CLBLL_R.SLICEL_X1.ALUT.INIT[19] origin:010-clb-lutinit 27_10
CLBLL_R.SLICEL_X1.ALUT.INIT[20] origin:010-clb-lutinit 26_09
CLBLL_R.SLICEL_X1.ALUT.INIT[21] origin:010-clb-lutinit 27_09
CLBLL_R.SLICEL_X1.ALUT.INIT[22] origin:010-clb-lutinit 26_08
CLBLL_R.SLICEL_X1.ALUT.INIT[23] origin:010-clb-lutinit 27_08
CLBLL_R.SLICEL_X1.ALUT.INIT[24] origin:010-clb-lutinit 29_11
CLBLL_R.SLICEL_X1.ALUT.INIT[25] origin:010-clb-lutinit 28_11
CLBLL_R.SLICEL_X1.ALUT.INIT[26] origin:010-clb-lutinit 29_10
CLBLL_R.SLICEL_X1.ALUT.INIT[27] origin:010-clb-lutinit 28_10
CLBLL_R.SLICEL_X1.ALUT.INIT[28] origin:010-clb-lutinit 29_09
CLBLL_R.SLICEL_X1.ALUT.INIT[29] origin:010-clb-lutinit 28_09
CLBLL_R.SLICEL_X1.ALUT.INIT[30] origin:010-clb-lutinit 29_08
CLBLL_R.SLICEL_X1.ALUT.INIT[31] origin:010-clb-lutinit 28_08
CLBLL_R.SLICEL_X1.ALUT.INIT[32] origin:010-clb-lutinit 26_07
CLBLL_R.SLICEL_X1.ALUT.INIT[33] origin:010-clb-lutinit 27_07
CLBLL_R.SLICEL_X1.ALUT.INIT[34] origin:010-clb-lutinit 26_06
CLBLL_R.SLICEL_X1.ALUT.INIT[35] origin:010-clb-lutinit 27_06
CLBLL_R.SLICEL_X1.ALUT.INIT[36] origin:010-clb-lutinit 26_05
CLBLL_R.SLICEL_X1.ALUT.INIT[37] origin:010-clb-lutinit 27_05
CLBLL_R.SLICEL_X1.ALUT.INIT[38] origin:010-clb-lutinit 26_04
CLBLL_R.SLICEL_X1.ALUT.INIT[39] origin:010-clb-lutinit 27_04
CLBLL_R.SLICEL_X1.ALUT.INIT[40] origin:010-clb-lutinit 29_07
CLBLL_R.SLICEL_X1.ALUT.INIT[41] origin:010-clb-lutinit 28_07
CLBLL_R.SLICEL_X1.ALUT.INIT[42] origin:010-clb-lutinit 29_06
CLBLL_R.SLICEL_X1.ALUT.INIT[43] origin:010-clb-lutinit 28_06
CLBLL_R.SLICEL_X1.ALUT.INIT[44] origin:010-clb-lutinit 29_05
CLBLL_R.SLICEL_X1.ALUT.INIT[45] origin:010-clb-lutinit 28_05
CLBLL_R.SLICEL_X1.ALUT.INIT[46] origin:010-clb-lutinit 29_04
CLBLL_R.SLICEL_X1.ALUT.INIT[47] origin:010-clb-lutinit 28_04
CLBLL_R.SLICEL_X1.ALUT.INIT[48] origin:010-clb-lutinit 26_03
CLBLL_R.SLICEL_X1.ALUT.INIT[49] origin:010-clb-lutinit 27_03
CLBLL_R.SLICEL_X1.ALUT.INIT[50] origin:010-clb-lutinit 26_02
CLBLL_R.SLICEL_X1.ALUT.INIT[51] origin:010-clb-lutinit 27_02
CLBLL_R.SLICEL_X1.ALUT.INIT[52] origin:010-clb-lutinit 26_01
CLBLL_R.SLICEL_X1.ALUT.INIT[53] origin:010-clb-lutinit 27_01
CLBLL_R.SLICEL_X1.ALUT.INIT[54] origin:010-clb-lutinit 26_00
CLBLL_R.SLICEL_X1.ALUT.INIT[55] origin:010-clb-lutinit 27_00
CLBLL_R.SLICEL_X1.ALUT.INIT[56] origin:010-clb-lutinit 29_03
CLBLL_R.SLICEL_X1.ALUT.INIT[57] origin:010-clb-lutinit 28_03
CLBLL_R.SLICEL_X1.ALUT.INIT[58] origin:010-clb-lutinit 29_02
CLBLL_R.SLICEL_X1.ALUT.INIT[59] origin:010-clb-lutinit 28_02
CLBLL_R.SLICEL_X1.ALUT.INIT[60] origin:010-clb-lutinit 29_01
CLBLL_R.SLICEL_X1.ALUT.INIT[61] origin:010-clb-lutinit 28_01
CLBLL_R.SLICEL_X1.ALUT.INIT[62] origin:010-clb-lutinit 29_00
CLBLL_R.SLICEL_X1.ALUT.INIT[63] origin:010-clb-lutinit 28_00
CLBLL_R.SLICEL_X1.AOUTMUX.A5Q origin:016-clb-noutmux !31_07 !31_09 !31_10 30_05
CLBLL_R.SLICEL_X1.AOUTMUX.CY origin:016-clb-noutmux !30_05 !31_09 31_07 31_10
CLBLL_R.SLICEL_X1.AOUTMUX.F7 origin:016-clb-noutmux !31_07 !31_09 30_05 31_10
CLBLL_R.SLICEL_X1.AOUTMUX.O5 origin:016-clb-noutmux !30_05 !31_07 31_09 31_10
CLBLL_R.SLICEL_X1.AOUTMUX.O6 origin:016-clb-noutmux !30_05 !31_07 !31_10 31_09
CLBLL_R.SLICEL_X1.AOUTMUX.XOR origin:016-clb-noutmux !30_05 !31_09 !31_10 31_07
CLBLL_R.SLICEL_X1.B5FF.ZINI origin:011-clb-ffconfig 31_23
CLBLL_R.SLICEL_X1.B5FF.ZRST origin:011-clb-ffconfig 00_16
CLBLL_R.SLICEL_X1.B5FFMUX.IN_A origin:012-clb-n5ffmux 31_19
CLBLL_R.SLICEL_X1.B5FFMUX.IN_B origin:012-clb-n5ffmux 31_18
CLBLL_R.SLICEL_X1.BFF.ZINI origin:011-clb-ffconfig 31_29
CLBLL_R.SLICEL_X1.BFF.ZRST origin:011-clb-ffconfig 31_30
CLBLL_R.SLICEL_X1.BFFMUX.BX origin:015-clb-nffmux !31_24 !31_25 !31_26 31_27
CLBLL_R.SLICEL_X1.BFFMUX.CY origin:015-clb-nffmux !31_24 !31_27 31_25 31_26
CLBLL_R.SLICEL_X1.BFFMUX.F8 origin:015-clb-nffmux !31_24 !31_26 31_25 31_27
CLBLL_R.SLICEL_X1.BFFMUX.O5 origin:015-clb-nffmux !31_26 !31_27 31_24 31_25
CLBLL_R.SLICEL_X1.BFFMUX.O6 origin:015-clb-nffmux !31_25 !31_26 !31_27 31_24
CLBLL_R.SLICEL_X1.BFFMUX.XOR origin:015-clb-nffmux !31_24 !31_25 !31_27 31_26
CLBLL_R.SLICEL_X1.BLUT.INIT[00] origin:010-clb-lutinit 26_31
CLBLL_R.SLICEL_X1.BLUT.INIT[01] origin:010-clb-lutinit 27_31
CLBLL_R.SLICEL_X1.BLUT.INIT[02] origin:010-clb-lutinit 26_30
CLBLL_R.SLICEL_X1.BLUT.INIT[03] origin:010-clb-lutinit 27_30
CLBLL_R.SLICEL_X1.BLUT.INIT[04] origin:010-clb-lutinit 26_29
CLBLL_R.SLICEL_X1.BLUT.INIT[05] origin:010-clb-lutinit 27_29
CLBLL_R.SLICEL_X1.BLUT.INIT[06] origin:010-clb-lutinit 26_28
CLBLL_R.SLICEL_X1.BLUT.INIT[07] origin:010-clb-lutinit 27_28
CLBLL_R.SLICEL_X1.BLUT.INIT[08] origin:010-clb-lutinit 29_31
CLBLL_R.SLICEL_X1.BLUT.INIT[09] origin:010-clb-lutinit 28_31
CLBLL_R.SLICEL_X1.BLUT.INIT[10] origin:010-clb-lutinit 29_30
CLBLL_R.SLICEL_X1.BLUT.INIT[11] origin:010-clb-lutinit 28_30
CLBLL_R.SLICEL_X1.BLUT.INIT[12] origin:010-clb-lutinit 29_29
CLBLL_R.SLICEL_X1.BLUT.INIT[13] origin:010-clb-lutinit 28_29
CLBLL_R.SLICEL_X1.BLUT.INIT[14] origin:010-clb-lutinit 29_28
CLBLL_R.SLICEL_X1.BLUT.INIT[15] origin:010-clb-lutinit 28_28
CLBLL_R.SLICEL_X1.BLUT.INIT[16] origin:010-clb-lutinit 26_27
CLBLL_R.SLICEL_X1.BLUT.INIT[17] origin:010-clb-lutinit 27_27
CLBLL_R.SLICEL_X1.BLUT.INIT[18] origin:010-clb-lutinit 26_26
CLBLL_R.SLICEL_X1.BLUT.INIT[19] origin:010-clb-lutinit 27_26
CLBLL_R.SLICEL_X1.BLUT.INIT[20] origin:010-clb-lutinit 26_25
CLBLL_R.SLICEL_X1.BLUT.INIT[21] origin:010-clb-lutinit 27_25
CLBLL_R.SLICEL_X1.BLUT.INIT[22] origin:010-clb-lutinit 26_24
CLBLL_R.SLICEL_X1.BLUT.INIT[23] origin:010-clb-lutinit 27_24
CLBLL_R.SLICEL_X1.BLUT.INIT[24] origin:010-clb-lutinit 29_27
CLBLL_R.SLICEL_X1.BLUT.INIT[25] origin:010-clb-lutinit 28_27
CLBLL_R.SLICEL_X1.BLUT.INIT[26] origin:010-clb-lutinit 29_26
CLBLL_R.SLICEL_X1.BLUT.INIT[27] origin:010-clb-lutinit 28_26
CLBLL_R.SLICEL_X1.BLUT.INIT[28] origin:010-clb-lutinit 29_25
CLBLL_R.SLICEL_X1.BLUT.INIT[29] origin:010-clb-lutinit 28_25
CLBLL_R.SLICEL_X1.BLUT.INIT[30] origin:010-clb-lutinit 29_24
CLBLL_R.SLICEL_X1.BLUT.INIT[31] origin:010-clb-lutinit 28_24
CLBLL_R.SLICEL_X1.BLUT.INIT[32] origin:010-clb-lutinit 26_23
CLBLL_R.SLICEL_X1.BLUT.INIT[33] origin:010-clb-lutinit 27_23
CLBLL_R.SLICEL_X1.BLUT.INIT[34] origin:010-clb-lutinit 26_22
CLBLL_R.SLICEL_X1.BLUT.INIT[35] origin:010-clb-lutinit 27_22
CLBLL_R.SLICEL_X1.BLUT.INIT[36] origin:010-clb-lutinit 26_21
CLBLL_R.SLICEL_X1.BLUT.INIT[37] origin:010-clb-lutinit 27_21
CLBLL_R.SLICEL_X1.BLUT.INIT[38] origin:010-clb-lutinit 26_20
CLBLL_R.SLICEL_X1.BLUT.INIT[39] origin:010-clb-lutinit 27_20
CLBLL_R.SLICEL_X1.BLUT.INIT[40] origin:010-clb-lutinit 29_23
CLBLL_R.SLICEL_X1.BLUT.INIT[41] origin:010-clb-lutinit 28_23
CLBLL_R.SLICEL_X1.BLUT.INIT[42] origin:010-clb-lutinit 29_22
CLBLL_R.SLICEL_X1.BLUT.INIT[43] origin:010-clb-lutinit 28_22
CLBLL_R.SLICEL_X1.BLUT.INIT[44] origin:010-clb-lutinit 29_21
CLBLL_R.SLICEL_X1.BLUT.INIT[45] origin:010-clb-lutinit 28_21
CLBLL_R.SLICEL_X1.BLUT.INIT[46] origin:010-clb-lutinit 29_20
CLBLL_R.SLICEL_X1.BLUT.INIT[47] origin:010-clb-lutinit 28_20
CLBLL_R.SLICEL_X1.BLUT.INIT[48] origin:010-clb-lutinit 26_19
CLBLL_R.SLICEL_X1.BLUT.INIT[49] origin:010-clb-lutinit 27_19
CLBLL_R.SLICEL_X1.BLUT.INIT[50] origin:010-clb-lutinit 26_18
CLBLL_R.SLICEL_X1.BLUT.INIT[51] origin:010-clb-lutinit 27_18
CLBLL_R.SLICEL_X1.BLUT.INIT[52] origin:010-clb-lutinit 26_17
CLBLL_R.SLICEL_X1.BLUT.INIT[53] origin:010-clb-lutinit 27_17
CLBLL_R.SLICEL_X1.BLUT.INIT[54] origin:010-clb-lutinit 26_16
CLBLL_R.SLICEL_X1.BLUT.INIT[55] origin:010-clb-lutinit 27_16
CLBLL_R.SLICEL_X1.BLUT.INIT[56] origin:010-clb-lutinit 29_19
CLBLL_R.SLICEL_X1.BLUT.INIT[57] origin:010-clb-lutinit 28_19
CLBLL_R.SLICEL_X1.BLUT.INIT[58] origin:010-clb-lutinit 29_18
CLBLL_R.SLICEL_X1.BLUT.INIT[59] origin:010-clb-lutinit 28_18
CLBLL_R.SLICEL_X1.BLUT.INIT[60] origin:010-clb-lutinit 29_17
CLBLL_R.SLICEL_X1.BLUT.INIT[61] origin:010-clb-lutinit 28_17
CLBLL_R.SLICEL_X1.BLUT.INIT[62] origin:010-clb-lutinit 29_16
CLBLL_R.SLICEL_X1.BLUT.INIT[63] origin:010-clb-lutinit 28_16
CLBLL_R.SLICEL_X1.BOUTMUX.B5Q origin:016-clb-noutmux !30_28 !31_20 !31_21 30_29
CLBLL_R.SLICEL_X1.BOUTMUX.CY origin:016-clb-noutmux !30_29 !31_20 30_28 31_21
CLBLL_R.SLICEL_X1.BOUTMUX.F8 origin:016-clb-noutmux !30_28 !31_20 30_29 31_21
CLBLL_R.SLICEL_X1.BOUTMUX.O5 origin:016-clb-noutmux !30_28 !30_29 31_20 31_21
CLBLL_R.SLICEL_X1.BOUTMUX.O6 origin:016-clb-noutmux !30_28 !30_29 !31_21 31_20
CLBLL_R.SLICEL_X1.BOUTMUX.XOR origin:016-clb-noutmux !30_29 !31_20 !31_21 30_28
CLBLL_R.SLICEL_X1.C5FF.ZINI origin:011-clb-ffconfig 31_42
CLBLL_R.SLICEL_X1.C5FF.ZRST origin:011-clb-ffconfig 00_44
CLBLL_R.SLICEL_X1.C5FFMUX.IN_A origin:012-clb-n5ffmux 31_44
CLBLL_R.SLICEL_X1.C5FFMUX.IN_B origin:012-clb-n5ffmux 31_39
CLBLL_R.SLICEL_X1.CARRY4.ACY0 origin:013-clb-ncy0 31_14
CLBLL_R.SLICEL_X1.CARRY4.BCY0 origin:013-clb-ncy0 00_08
CLBLL_R.SLICEL_X1.CARRY4.CCY0 origin:013-clb-ncy0 31_48
CLBLL_R.SLICEL_X1.CARRY4.DCY0 origin:013-clb-ncy0 31_49
CLBLL_R.SLICEL_X1.CEUSEDMUX origin:014-clb-ffsrcemux 00_36
CLBLL_R.SLICEL_X1.CFF.ZINI origin:011-clb-ffconfig 31_34
CLBLL_R.SLICEL_X1.CFF.ZRST origin:011-clb-ffconfig 30_34
CLBLL_R.SLICEL_X1.CFFMUX.CX origin:015-clb-nffmux !31_35 !31_36 !31_37 31_38
CLBLL_R.SLICEL_X1.CFFMUX.CY origin:015-clb-nffmux !31_36 !31_38 31_35 31_37
CLBLL_R.SLICEL_X1.CFFMUX.F7 origin:015-clb-nffmux !31_36 !31_37 31_35 31_38
CLBLL_R.SLICEL_X1.CFFMUX.O5 origin:015-clb-nffmux !31_37 !31_38 31_35 31_36
CLBLL_R.SLICEL_X1.CFFMUX.O6 origin:015-clb-nffmux !31_35 !31_37 !31_38 31_36
CLBLL_R.SLICEL_X1.CFFMUX.XOR origin:015-clb-nffmux !31_35 !31_36 !31_38 31_37
CLBLL_R.SLICEL_X1.CLKINV origin:011-clb-ffconfig 00_52
CLBLL_R.SLICEL_X1.CLUT.INIT[00] origin:010-clb-lutinit 26_47
CLBLL_R.SLICEL_X1.CLUT.INIT[01] origin:010-clb-lutinit 27_47
CLBLL_R.SLICEL_X1.CLUT.INIT[02] origin:010-clb-lutinit 26_46
CLBLL_R.SLICEL_X1.CLUT.INIT[03] origin:010-clb-lutinit 27_46
CLBLL_R.SLICEL_X1.CLUT.INIT[04] origin:010-clb-lutinit 26_45
CLBLL_R.SLICEL_X1.CLUT.INIT[05] origin:010-clb-lutinit 27_45
CLBLL_R.SLICEL_X1.CLUT.INIT[06] origin:010-clb-lutinit 26_44
CLBLL_R.SLICEL_X1.CLUT.INIT[07] origin:010-clb-lutinit 27_44
CLBLL_R.SLICEL_X1.CLUT.INIT[08] origin:010-clb-lutinit 29_47
CLBLL_R.SLICEL_X1.CLUT.INIT[09] origin:010-clb-lutinit 28_47
CLBLL_R.SLICEL_X1.CLUT.INIT[10] origin:010-clb-lutinit 29_46
CLBLL_R.SLICEL_X1.CLUT.INIT[11] origin:010-clb-lutinit 28_46
CLBLL_R.SLICEL_X1.CLUT.INIT[12] origin:010-clb-lutinit 29_45
CLBLL_R.SLICEL_X1.CLUT.INIT[13] origin:010-clb-lutinit 28_45
CLBLL_R.SLICEL_X1.CLUT.INIT[14] origin:010-clb-lutinit 29_44
CLBLL_R.SLICEL_X1.CLUT.INIT[15] origin:010-clb-lutinit 28_44
CLBLL_R.SLICEL_X1.CLUT.INIT[16] origin:010-clb-lutinit 26_43
CLBLL_R.SLICEL_X1.CLUT.INIT[17] origin:010-clb-lutinit 27_43
CLBLL_R.SLICEL_X1.CLUT.INIT[18] origin:010-clb-lutinit 26_42
CLBLL_R.SLICEL_X1.CLUT.INIT[19] origin:010-clb-lutinit 27_42
CLBLL_R.SLICEL_X1.CLUT.INIT[20] origin:010-clb-lutinit 26_41
CLBLL_R.SLICEL_X1.CLUT.INIT[21] origin:010-clb-lutinit 27_41
CLBLL_R.SLICEL_X1.CLUT.INIT[22] origin:010-clb-lutinit 26_40
CLBLL_R.SLICEL_X1.CLUT.INIT[23] origin:010-clb-lutinit 27_40
CLBLL_R.SLICEL_X1.CLUT.INIT[24] origin:010-clb-lutinit 29_43
CLBLL_R.SLICEL_X1.CLUT.INIT[25] origin:010-clb-lutinit 28_43
CLBLL_R.SLICEL_X1.CLUT.INIT[26] origin:010-clb-lutinit 29_42
CLBLL_R.SLICEL_X1.CLUT.INIT[27] origin:010-clb-lutinit 28_42
CLBLL_R.SLICEL_X1.CLUT.INIT[28] origin:010-clb-lutinit 29_41
CLBLL_R.SLICEL_X1.CLUT.INIT[29] origin:010-clb-lutinit 28_41
CLBLL_R.SLICEL_X1.CLUT.INIT[30] origin:010-clb-lutinit 29_40
CLBLL_R.SLICEL_X1.CLUT.INIT[31] origin:010-clb-lutinit 28_40
CLBLL_R.SLICEL_X1.CLUT.INIT[32] origin:010-clb-lutinit 26_39
CLBLL_R.SLICEL_X1.CLUT.INIT[33] origin:010-clb-lutinit 27_39
CLBLL_R.SLICEL_X1.CLUT.INIT[34] origin:010-clb-lutinit 26_38
CLBLL_R.SLICEL_X1.CLUT.INIT[35] origin:010-clb-lutinit 27_38
CLBLL_R.SLICEL_X1.CLUT.INIT[36] origin:010-clb-lutinit 26_37
CLBLL_R.SLICEL_X1.CLUT.INIT[37] origin:010-clb-lutinit 27_37
CLBLL_R.SLICEL_X1.CLUT.INIT[38] origin:010-clb-lutinit 26_36
CLBLL_R.SLICEL_X1.CLUT.INIT[39] origin:010-clb-lutinit 27_36
CLBLL_R.SLICEL_X1.CLUT.INIT[40] origin:010-clb-lutinit 29_39
CLBLL_R.SLICEL_X1.CLUT.INIT[41] origin:010-clb-lutinit 28_39
CLBLL_R.SLICEL_X1.CLUT.INIT[42] origin:010-clb-lutinit 29_38
CLBLL_R.SLICEL_X1.CLUT.INIT[43] origin:010-clb-lutinit 28_38
CLBLL_R.SLICEL_X1.CLUT.INIT[44] origin:010-clb-lutinit 29_37
CLBLL_R.SLICEL_X1.CLUT.INIT[45] origin:010-clb-lutinit 28_37
CLBLL_R.SLICEL_X1.CLUT.INIT[46] origin:010-clb-lutinit 29_36
CLBLL_R.SLICEL_X1.CLUT.INIT[47] origin:010-clb-lutinit 28_36
CLBLL_R.SLICEL_X1.CLUT.INIT[48] origin:010-clb-lutinit 26_35
CLBLL_R.SLICEL_X1.CLUT.INIT[49] origin:010-clb-lutinit 27_35
CLBLL_R.SLICEL_X1.CLUT.INIT[50] origin:010-clb-lutinit 26_34
CLBLL_R.SLICEL_X1.CLUT.INIT[51] origin:010-clb-lutinit 27_34
CLBLL_R.SLICEL_X1.CLUT.INIT[52] origin:010-clb-lutinit 26_33
CLBLL_R.SLICEL_X1.CLUT.INIT[53] origin:010-clb-lutinit 27_33
CLBLL_R.SLICEL_X1.CLUT.INIT[54] origin:010-clb-lutinit 26_32
CLBLL_R.SLICEL_X1.CLUT.INIT[55] origin:010-clb-lutinit 27_32
CLBLL_R.SLICEL_X1.CLUT.INIT[56] origin:010-clb-lutinit 29_35
CLBLL_R.SLICEL_X1.CLUT.INIT[57] origin:010-clb-lutinit 28_35
CLBLL_R.SLICEL_X1.CLUT.INIT[58] origin:010-clb-lutinit 29_34
CLBLL_R.SLICEL_X1.CLUT.INIT[59] origin:010-clb-lutinit 28_34
CLBLL_R.SLICEL_X1.CLUT.INIT[60] origin:010-clb-lutinit 29_33
CLBLL_R.SLICEL_X1.CLUT.INIT[61] origin:010-clb-lutinit 28_33
CLBLL_R.SLICEL_X1.CLUT.INIT[62] origin:010-clb-lutinit 29_32
CLBLL_R.SLICEL_X1.CLUT.INIT[63] origin:010-clb-lutinit 28_32
CLBLL_R.SLICEL_X1.COUTMUX.C5Q origin:016-clb-noutmux !30_42 !31_40 !31_43 30_41
CLBLL_R.SLICEL_X1.COUTMUX.CY origin:016-clb-noutmux !30_41 !31_43 30_42 31_40
CLBLL_R.SLICEL_X1.COUTMUX.F7 origin:016-clb-noutmux !30_42 !31_43 30_41 31_40
CLBLL_R.SLICEL_X1.COUTMUX.O5 origin:016-clb-noutmux !30_41 !30_42 31_40 31_43
CLBLL_R.SLICEL_X1.COUTMUX.O6 origin:016-clb-noutmux !30_41 !30_42 !31_40 31_43
CLBLL_R.SLICEL_X1.COUTMUX.XOR origin:016-clb-noutmux !30_41 !31_40 !31_43 30_42
CLBLL_R.SLICEL_X1.D5FF.ZINI origin:011-clb-ffconfig 31_52
CLBLL_R.SLICEL_X1.D5FF.ZRST origin:011-clb-ffconfig 00_56
CLBLL_R.SLICEL_X1.D5FFMUX.IN_A origin:012-clb-n5ffmux 31_55
CLBLL_R.SLICEL_X1.D5FFMUX.IN_B origin:012-clb-n5ffmux 31_54
CLBLL_R.SLICEL_X1.DFF.ZINI origin:011-clb-ffconfig 31_59
CLBLL_R.SLICEL_X1.DFF.ZRST origin:011-clb-ffconfig 31_50
CLBLL_R.SLICEL_X1.DFFMUX.CY origin:015-clb-nffmux !31_60 !31_61 30_58 31_62
CLBLL_R.SLICEL_X1.DFFMUX.DX origin:015-clb-nffmux !30_58 !31_60 !31_62 31_61
CLBLL_R.SLICEL_X1.DFFMUX.O5 origin:015-clb-nffmux !31_61 !31_62 30_58 31_60
CLBLL_R.SLICEL_X1.DFFMUX.O6 origin:015-clb-nffmux !30_58 !31_61 !31_62 31_60
CLBLL_R.SLICEL_X1.DFFMUX.XOR origin:015-clb-nffmux !30_58 !31_60 !31_61 31_62
CLBLL_R.SLICEL_X1.DLUT.INIT[00] origin:010-clb-lutinit 26_63
CLBLL_R.SLICEL_X1.DLUT.INIT[01] origin:010-clb-lutinit 27_63
CLBLL_R.SLICEL_X1.DLUT.INIT[02] origin:010-clb-lutinit 26_62
CLBLL_R.SLICEL_X1.DLUT.INIT[03] origin:010-clb-lutinit 27_62
CLBLL_R.SLICEL_X1.DLUT.INIT[04] origin:010-clb-lutinit 26_61
CLBLL_R.SLICEL_X1.DLUT.INIT[05] origin:010-clb-lutinit 27_61
CLBLL_R.SLICEL_X1.DLUT.INIT[06] origin:010-clb-lutinit 26_60
CLBLL_R.SLICEL_X1.DLUT.INIT[07] origin:010-clb-lutinit 27_60
CLBLL_R.SLICEL_X1.DLUT.INIT[08] origin:010-clb-lutinit 29_63
CLBLL_R.SLICEL_X1.DLUT.INIT[09] origin:010-clb-lutinit 28_63
CLBLL_R.SLICEL_X1.DLUT.INIT[10] origin:010-clb-lutinit 29_62
CLBLL_R.SLICEL_X1.DLUT.INIT[11] origin:010-clb-lutinit 28_62
CLBLL_R.SLICEL_X1.DLUT.INIT[12] origin:010-clb-lutinit 29_61
CLBLL_R.SLICEL_X1.DLUT.INIT[13] origin:010-clb-lutinit 28_61
CLBLL_R.SLICEL_X1.DLUT.INIT[14] origin:010-clb-lutinit 29_60
CLBLL_R.SLICEL_X1.DLUT.INIT[15] origin:010-clb-lutinit 28_60
CLBLL_R.SLICEL_X1.DLUT.INIT[16] origin:010-clb-lutinit 26_59
CLBLL_R.SLICEL_X1.DLUT.INIT[17] origin:010-clb-lutinit 27_59
CLBLL_R.SLICEL_X1.DLUT.INIT[18] origin:010-clb-lutinit 26_58
CLBLL_R.SLICEL_X1.DLUT.INIT[19] origin:010-clb-lutinit 27_58
CLBLL_R.SLICEL_X1.DLUT.INIT[20] origin:010-clb-lutinit 26_57
CLBLL_R.SLICEL_X1.DLUT.INIT[21] origin:010-clb-lutinit 27_57
CLBLL_R.SLICEL_X1.DLUT.INIT[22] origin:010-clb-lutinit 26_56
CLBLL_R.SLICEL_X1.DLUT.INIT[23] origin:010-clb-lutinit 27_56
CLBLL_R.SLICEL_X1.DLUT.INIT[24] origin:010-clb-lutinit 29_59
CLBLL_R.SLICEL_X1.DLUT.INIT[25] origin:010-clb-lutinit 28_59
CLBLL_R.SLICEL_X1.DLUT.INIT[26] origin:010-clb-lutinit 29_58
CLBLL_R.SLICEL_X1.DLUT.INIT[27] origin:010-clb-lutinit 28_58
CLBLL_R.SLICEL_X1.DLUT.INIT[28] origin:010-clb-lutinit 29_57
CLBLL_R.SLICEL_X1.DLUT.INIT[29] origin:010-clb-lutinit 28_57
CLBLL_R.SLICEL_X1.DLUT.INIT[30] origin:010-clb-lutinit 29_56
CLBLL_R.SLICEL_X1.DLUT.INIT[31] origin:010-clb-lutinit 28_56
CLBLL_R.SLICEL_X1.DLUT.INIT[32] origin:010-clb-lutinit 26_55
CLBLL_R.SLICEL_X1.DLUT.INIT[33] origin:010-clb-lutinit 27_55
CLBLL_R.SLICEL_X1.DLUT.INIT[34] origin:010-clb-lutinit 26_54
CLBLL_R.SLICEL_X1.DLUT.INIT[35] origin:010-clb-lutinit 27_54
CLBLL_R.SLICEL_X1.DLUT.INIT[36] origin:010-clb-lutinit 26_53
CLBLL_R.SLICEL_X1.DLUT.INIT[37] origin:010-clb-lutinit 27_53
CLBLL_R.SLICEL_X1.DLUT.INIT[38] origin:010-clb-lutinit 26_52
CLBLL_R.SLICEL_X1.DLUT.INIT[39] origin:010-clb-lutinit 27_52
CLBLL_R.SLICEL_X1.DLUT.INIT[40] origin:010-clb-lutinit 29_55
CLBLL_R.SLICEL_X1.DLUT.INIT[41] origin:010-clb-lutinit 28_55
CLBLL_R.SLICEL_X1.DLUT.INIT[42] origin:010-clb-lutinit 29_54
CLBLL_R.SLICEL_X1.DLUT.INIT[43] origin:010-clb-lutinit 28_54
CLBLL_R.SLICEL_X1.DLUT.INIT[44] origin:010-clb-lutinit 29_53
CLBLL_R.SLICEL_X1.DLUT.INIT[45] origin:010-clb-lutinit 28_53
CLBLL_R.SLICEL_X1.DLUT.INIT[46] origin:010-clb-lutinit 29_52
CLBLL_R.SLICEL_X1.DLUT.INIT[47] origin:010-clb-lutinit 28_52
CLBLL_R.SLICEL_X1.DLUT.INIT[48] origin:010-clb-lutinit 26_51
CLBLL_R.SLICEL_X1.DLUT.INIT[49] origin:010-clb-lutinit 27_51
CLBLL_R.SLICEL_X1.DLUT.INIT[50] origin:010-clb-lutinit 26_50
CLBLL_R.SLICEL_X1.DLUT.INIT[51] origin:010-clb-lutinit 27_50
CLBLL_R.SLICEL_X1.DLUT.INIT[52] origin:010-clb-lutinit 26_49
CLBLL_R.SLICEL_X1.DLUT.INIT[53] origin:010-clb-lutinit 27_49
CLBLL_R.SLICEL_X1.DLUT.INIT[54] origin:010-clb-lutinit 26_48
CLBLL_R.SLICEL_X1.DLUT.INIT[55] origin:010-clb-lutinit 27_48
CLBLL_R.SLICEL_X1.DLUT.INIT[56] origin:010-clb-lutinit 29_51
CLBLL_R.SLICEL_X1.DLUT.INIT[57] origin:010-clb-lutinit 28_51
CLBLL_R.SLICEL_X1.DLUT.INIT[58] origin:010-clb-lutinit 29_50
CLBLL_R.SLICEL_X1.DLUT.INIT[59] origin:010-clb-lutinit 28_50
CLBLL_R.SLICEL_X1.DLUT.INIT[60] origin:010-clb-lutinit 29_49
CLBLL_R.SLICEL_X1.DLUT.INIT[61] origin:010-clb-lutinit 28_49
CLBLL_R.SLICEL_X1.DLUT.INIT[62] origin:010-clb-lutinit 29_48
CLBLL_R.SLICEL_X1.DLUT.INIT[63] origin:010-clb-lutinit 28_48
CLBLL_R.SLICEL_X1.DOUTMUX.CY origin:016-clb-noutmux !31_53 !31_56 30_53 31_57
CLBLL_R.SLICEL_X1.DOUTMUX.D5Q origin:016-clb-noutmux !30_53 !31_56 !31_57 31_53
CLBLL_R.SLICEL_X1.DOUTMUX.O5 origin:016-clb-noutmux !30_53 !31_53 31_56 31_57
CLBLL_R.SLICEL_X1.DOUTMUX.O6 origin:016-clb-noutmux !30_53 !31_53 !31_57 31_56
CLBLL_R.SLICEL_X1.DOUTMUX.XOR origin:016-clb-noutmux !31_53 !31_56 !31_57 30_53
CLBLL_R.SLICEL_X1.FFSYNC origin:011-clb-ffconfig 01_31
CLBLL_R.SLICEL_X1.LATCH origin:011-clb-ffconfig 31_32
CLBLL_R.SLICEL_X1.PRECYINIT.AX origin:017-clb-precyinit !01_11 !31_12 31_13
CLBLL_R.SLICEL_X1.PRECYINIT.C0 origin:017-clb-precyinit !01_11 !31_12 !31_13
CLBLL_R.SLICEL_X1.PRECYINIT.C1 origin:017-clb-precyinit !31_12 !31_13 01_11
CLBLL_R.SLICEL_X1.PRECYINIT.CIN origin:017-clb-precyinit !01_11 !31_13 31_12
CLBLL_R.SLICEL_X1.SRUSEDMUX origin:014-clb-ffsrcemux 00_32

696
zynq7/segbits_clblm_l.origin_info.db Normal file
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@ -0,0 +1,696 @@
CLBLM_L.SLICEL_X1.A5FF.ZINI origin:011-clb-ffconfig 31_05
CLBLM_L.SLICEL_X1.A5FF.ZRST origin:011-clb-ffconfig 01_03
CLBLM_L.SLICEL_X1.A5FFMUX.IN_A origin:012-clb-n5ffmux 31_08
CLBLM_L.SLICEL_X1.A5FFMUX.IN_B origin:012-clb-n5ffmux 31_11
CLBLM_L.SLICEL_X1.AFF.ZINI origin:011-clb-ffconfig 31_04
CLBLM_L.SLICEL_X1.AFF.ZRST origin:011-clb-ffconfig 31_15
CLBLM_L.SLICEL_X1.AFFMUX.AX origin:015-clb-nffmux !30_04 !31_00 !31_02 31_01
CLBLM_L.SLICEL_X1.AFFMUX.CY origin:015-clb-nffmux !30_04 !31_01 31_00 31_02
CLBLM_L.SLICEL_X1.AFFMUX.F7 origin:015-clb-nffmux !30_04 !31_02 31_00 31_01
CLBLM_L.SLICEL_X1.AFFMUX.O5 origin:015-clb-nffmux !31_01 !31_02 30_04 31_00
CLBLM_L.SLICEL_X1.AFFMUX.O6 origin:015-clb-nffmux !31_00 !31_01 !31_02 30_04
CLBLM_L.SLICEL_X1.AFFMUX.XOR origin:015-clb-nffmux !30_04 !31_00 !31_01 31_02
CLBLM_L.SLICEL_X1.ALUT.INIT[00] origin:010-clb-lutinit 26_15
CLBLM_L.SLICEL_X1.ALUT.INIT[01] origin:010-clb-lutinit 27_15
CLBLM_L.SLICEL_X1.ALUT.INIT[02] origin:010-clb-lutinit 26_14
CLBLM_L.SLICEL_X1.ALUT.INIT[03] origin:010-clb-lutinit 27_14
CLBLM_L.SLICEL_X1.ALUT.INIT[04] origin:010-clb-lutinit 26_13
CLBLM_L.SLICEL_X1.ALUT.INIT[05] origin:010-clb-lutinit 27_13
CLBLM_L.SLICEL_X1.ALUT.INIT[06] origin:010-clb-lutinit 26_12
CLBLM_L.SLICEL_X1.ALUT.INIT[07] origin:010-clb-lutinit 27_12
CLBLM_L.SLICEL_X1.ALUT.INIT[08] origin:010-clb-lutinit 29_15
CLBLM_L.SLICEL_X1.ALUT.INIT[09] origin:010-clb-lutinit 28_15
CLBLM_L.SLICEL_X1.ALUT.INIT[10] origin:010-clb-lutinit 29_14
CLBLM_L.SLICEL_X1.ALUT.INIT[11] origin:010-clb-lutinit 28_14
CLBLM_L.SLICEL_X1.ALUT.INIT[12] origin:010-clb-lutinit 29_13
CLBLM_L.SLICEL_X1.ALUT.INIT[13] origin:010-clb-lutinit 28_13
CLBLM_L.SLICEL_X1.ALUT.INIT[14] origin:010-clb-lutinit 29_12
CLBLM_L.SLICEL_X1.ALUT.INIT[15] origin:010-clb-lutinit 28_12
CLBLM_L.SLICEL_X1.ALUT.INIT[16] origin:010-clb-lutinit 26_11
CLBLM_L.SLICEL_X1.ALUT.INIT[17] origin:010-clb-lutinit 27_11
CLBLM_L.SLICEL_X1.ALUT.INIT[18] origin:010-clb-lutinit 26_10
CLBLM_L.SLICEL_X1.ALUT.INIT[19] origin:010-clb-lutinit 27_10
CLBLM_L.SLICEL_X1.ALUT.INIT[20] origin:010-clb-lutinit 26_09
CLBLM_L.SLICEL_X1.ALUT.INIT[21] origin:010-clb-lutinit 27_09
CLBLM_L.SLICEL_X1.ALUT.INIT[22] origin:010-clb-lutinit 26_08
CLBLM_L.SLICEL_X1.ALUT.INIT[23] origin:010-clb-lutinit 27_08
CLBLM_L.SLICEL_X1.ALUT.INIT[24] origin:010-clb-lutinit 29_11
CLBLM_L.SLICEL_X1.ALUT.INIT[25] origin:010-clb-lutinit 28_11
CLBLM_L.SLICEL_X1.ALUT.INIT[26] origin:010-clb-lutinit 29_10
CLBLM_L.SLICEL_X1.ALUT.INIT[27] origin:010-clb-lutinit 28_10
CLBLM_L.SLICEL_X1.ALUT.INIT[28] origin:010-clb-lutinit 29_09
CLBLM_L.SLICEL_X1.ALUT.INIT[29] origin:010-clb-lutinit 28_09
CLBLM_L.SLICEL_X1.ALUT.INIT[30] origin:010-clb-lutinit 29_08
CLBLM_L.SLICEL_X1.ALUT.INIT[31] origin:010-clb-lutinit 28_08
CLBLM_L.SLICEL_X1.ALUT.INIT[32] origin:010-clb-lutinit 26_07
CLBLM_L.SLICEL_X1.ALUT.INIT[33] origin:010-clb-lutinit 27_07
CLBLM_L.SLICEL_X1.ALUT.INIT[34] origin:010-clb-lutinit 26_06
CLBLM_L.SLICEL_X1.ALUT.INIT[35] origin:010-clb-lutinit 27_06
CLBLM_L.SLICEL_X1.ALUT.INIT[36] origin:010-clb-lutinit 26_05
CLBLM_L.SLICEL_X1.ALUT.INIT[37] origin:010-clb-lutinit 27_05
CLBLM_L.SLICEL_X1.ALUT.INIT[38] origin:010-clb-lutinit 26_04
CLBLM_L.SLICEL_X1.ALUT.INIT[39] origin:010-clb-lutinit 27_04
CLBLM_L.SLICEL_X1.ALUT.INIT[40] origin:010-clb-lutinit 29_07
CLBLM_L.SLICEL_X1.ALUT.INIT[41] origin:010-clb-lutinit 28_07
CLBLM_L.SLICEL_X1.ALUT.INIT[42] origin:010-clb-lutinit 29_06
CLBLM_L.SLICEL_X1.ALUT.INIT[43] origin:010-clb-lutinit 28_06
CLBLM_L.SLICEL_X1.ALUT.INIT[44] origin:010-clb-lutinit 29_05
CLBLM_L.SLICEL_X1.ALUT.INIT[45] origin:010-clb-lutinit 28_05
CLBLM_L.SLICEL_X1.ALUT.INIT[46] origin:010-clb-lutinit 29_04
CLBLM_L.SLICEL_X1.ALUT.INIT[47] origin:010-clb-lutinit 28_04
CLBLM_L.SLICEL_X1.ALUT.INIT[48] origin:010-clb-lutinit 26_03
CLBLM_L.SLICEL_X1.ALUT.INIT[49] origin:010-clb-lutinit 27_03
CLBLM_L.SLICEL_X1.ALUT.INIT[50] origin:010-clb-lutinit 26_02
CLBLM_L.SLICEL_X1.ALUT.INIT[51] origin:010-clb-lutinit 27_02
CLBLM_L.SLICEL_X1.ALUT.INIT[52] origin:010-clb-lutinit 26_01
CLBLM_L.SLICEL_X1.ALUT.INIT[53] origin:010-clb-lutinit 27_01
CLBLM_L.SLICEL_X1.ALUT.INIT[54] origin:010-clb-lutinit 26_00
CLBLM_L.SLICEL_X1.ALUT.INIT[55] origin:010-clb-lutinit 27_00
CLBLM_L.SLICEL_X1.ALUT.INIT[56] origin:010-clb-lutinit 29_03
CLBLM_L.SLICEL_X1.ALUT.INIT[57] origin:010-clb-lutinit 28_03
CLBLM_L.SLICEL_X1.ALUT.INIT[58] origin:010-clb-lutinit 29_02
CLBLM_L.SLICEL_X1.ALUT.INIT[59] origin:010-clb-lutinit 28_02
CLBLM_L.SLICEL_X1.ALUT.INIT[60] origin:010-clb-lutinit 29_01
CLBLM_L.SLICEL_X1.ALUT.INIT[61] origin:010-clb-lutinit 28_01
CLBLM_L.SLICEL_X1.ALUT.INIT[62] origin:010-clb-lutinit 29_00
CLBLM_L.SLICEL_X1.ALUT.INIT[63] origin:010-clb-lutinit 28_00
CLBLM_L.SLICEL_X1.AOUTMUX.A5Q origin:016-clb-noutmux !31_07 !31_09 !31_10 30_05
CLBLM_L.SLICEL_X1.AOUTMUX.CY origin:016-clb-noutmux !30_05 !31_09 31_07 31_10
CLBLM_L.SLICEL_X1.AOUTMUX.F7 origin:016-clb-noutmux !31_07 !31_09 30_05 31_10
CLBLM_L.SLICEL_X1.AOUTMUX.O5 origin:016-clb-noutmux !30_05 !31_07 31_09 31_10
CLBLM_L.SLICEL_X1.AOUTMUX.O6 origin:016-clb-noutmux !30_05 !31_07 !31_10 31_09
CLBLM_L.SLICEL_X1.AOUTMUX.XOR origin:016-clb-noutmux !30_05 !31_09 !31_10 31_07
CLBLM_L.SLICEL_X1.B5FF.ZINI origin:011-clb-ffconfig 31_23
CLBLM_L.SLICEL_X1.B5FF.ZRST origin:011-clb-ffconfig 00_16
CLBLM_L.SLICEL_X1.B5FFMUX.IN_A origin:012-clb-n5ffmux 31_19
CLBLM_L.SLICEL_X1.B5FFMUX.IN_B origin:012-clb-n5ffmux 31_18
CLBLM_L.SLICEL_X1.BFF.ZINI origin:011-clb-ffconfig 31_29
CLBLM_L.SLICEL_X1.BFF.ZRST origin:011-clb-ffconfig 31_30
CLBLM_L.SLICEL_X1.BFFMUX.BX origin:015-clb-nffmux !31_24 !31_25 !31_26 31_27
CLBLM_L.SLICEL_X1.BFFMUX.CY origin:015-clb-nffmux !31_24 !31_27 31_25 31_26
CLBLM_L.SLICEL_X1.BFFMUX.F8 origin:015-clb-nffmux !31_24 !31_26 31_25 31_27
CLBLM_L.SLICEL_X1.BFFMUX.O5 origin:015-clb-nffmux !31_26 !31_27 31_24 31_25
CLBLM_L.SLICEL_X1.BFFMUX.O6 origin:015-clb-nffmux !31_25 !31_26 !31_27 31_24
CLBLM_L.SLICEL_X1.BFFMUX.XOR origin:015-clb-nffmux !31_24 !31_25 !31_27 31_26
CLBLM_L.SLICEL_X1.BLUT.INIT[00] origin:010-clb-lutinit 26_31
CLBLM_L.SLICEL_X1.BLUT.INIT[01] origin:010-clb-lutinit 27_31
CLBLM_L.SLICEL_X1.BLUT.INIT[02] origin:010-clb-lutinit 26_30
CLBLM_L.SLICEL_X1.BLUT.INIT[03] origin:010-clb-lutinit 27_30
CLBLM_L.SLICEL_X1.BLUT.INIT[04] origin:010-clb-lutinit 26_29
CLBLM_L.SLICEL_X1.BLUT.INIT[05] origin:010-clb-lutinit 27_29
CLBLM_L.SLICEL_X1.BLUT.INIT[06] origin:010-clb-lutinit 26_28
CLBLM_L.SLICEL_X1.BLUT.INIT[07] origin:010-clb-lutinit 27_28
CLBLM_L.SLICEL_X1.BLUT.INIT[08] origin:010-clb-lutinit 29_31
CLBLM_L.SLICEL_X1.BLUT.INIT[09] origin:010-clb-lutinit 28_31
CLBLM_L.SLICEL_X1.BLUT.INIT[10] origin:010-clb-lutinit 29_30
CLBLM_L.SLICEL_X1.BLUT.INIT[11] origin:010-clb-lutinit 28_30
CLBLM_L.SLICEL_X1.BLUT.INIT[12] origin:010-clb-lutinit 29_29
CLBLM_L.SLICEL_X1.BLUT.INIT[13] origin:010-clb-lutinit 28_29
CLBLM_L.SLICEL_X1.BLUT.INIT[14] origin:010-clb-lutinit 29_28
CLBLM_L.SLICEL_X1.BLUT.INIT[15] origin:010-clb-lutinit 28_28
CLBLM_L.SLICEL_X1.BLUT.INIT[16] origin:010-clb-lutinit 26_27
CLBLM_L.SLICEL_X1.BLUT.INIT[17] origin:010-clb-lutinit 27_27
CLBLM_L.SLICEL_X1.BLUT.INIT[18] origin:010-clb-lutinit 26_26
CLBLM_L.SLICEL_X1.BLUT.INIT[19] origin:010-clb-lutinit 27_26
CLBLM_L.SLICEL_X1.BLUT.INIT[20] origin:010-clb-lutinit 26_25
CLBLM_L.SLICEL_X1.BLUT.INIT[21] origin:010-clb-lutinit 27_25
CLBLM_L.SLICEL_X1.BLUT.INIT[22] origin:010-clb-lutinit 26_24
CLBLM_L.SLICEL_X1.BLUT.INIT[23] origin:010-clb-lutinit 27_24
CLBLM_L.SLICEL_X1.BLUT.INIT[24] origin:010-clb-lutinit 29_27
CLBLM_L.SLICEL_X1.BLUT.INIT[25] origin:010-clb-lutinit 28_27
CLBLM_L.SLICEL_X1.BLUT.INIT[26] origin:010-clb-lutinit 29_26
CLBLM_L.SLICEL_X1.BLUT.INIT[27] origin:010-clb-lutinit 28_26
CLBLM_L.SLICEL_X1.BLUT.INIT[28] origin:010-clb-lutinit 29_25
CLBLM_L.SLICEL_X1.BLUT.INIT[29] origin:010-clb-lutinit 28_25
CLBLM_L.SLICEL_X1.BLUT.INIT[30] origin:010-clb-lutinit 29_24
CLBLM_L.SLICEL_X1.BLUT.INIT[31] origin:010-clb-lutinit 28_24
CLBLM_L.SLICEL_X1.BLUT.INIT[32] origin:010-clb-lutinit 26_23
CLBLM_L.SLICEL_X1.BLUT.INIT[33] origin:010-clb-lutinit 27_23
CLBLM_L.SLICEL_X1.BLUT.INIT[34] origin:010-clb-lutinit 26_22
CLBLM_L.SLICEL_X1.BLUT.INIT[35] origin:010-clb-lutinit 27_22
CLBLM_L.SLICEL_X1.BLUT.INIT[36] origin:010-clb-lutinit 26_21
CLBLM_L.SLICEL_X1.BLUT.INIT[37] origin:010-clb-lutinit 27_21
CLBLM_L.SLICEL_X1.BLUT.INIT[38] origin:010-clb-lutinit 26_20
CLBLM_L.SLICEL_X1.BLUT.INIT[39] origin:010-clb-lutinit 27_20
CLBLM_L.SLICEL_X1.BLUT.INIT[40] origin:010-clb-lutinit 29_23
CLBLM_L.SLICEL_X1.BLUT.INIT[41] origin:010-clb-lutinit 28_23
CLBLM_L.SLICEL_X1.BLUT.INIT[42] origin:010-clb-lutinit 29_22
CLBLM_L.SLICEL_X1.BLUT.INIT[43] origin:010-clb-lutinit 28_22
CLBLM_L.SLICEL_X1.BLUT.INIT[44] origin:010-clb-lutinit 29_21
CLBLM_L.SLICEL_X1.BLUT.INIT[45] origin:010-clb-lutinit 28_21
CLBLM_L.SLICEL_X1.BLUT.INIT[46] origin:010-clb-lutinit 29_20
CLBLM_L.SLICEL_X1.BLUT.INIT[47] origin:010-clb-lutinit 28_20
CLBLM_L.SLICEL_X1.BLUT.INIT[48] origin:010-clb-lutinit 26_19
CLBLM_L.SLICEL_X1.BLUT.INIT[49] origin:010-clb-lutinit 27_19
CLBLM_L.SLICEL_X1.BLUT.INIT[50] origin:010-clb-lutinit 26_18
CLBLM_L.SLICEL_X1.BLUT.INIT[51] origin:010-clb-lutinit 27_18
CLBLM_L.SLICEL_X1.BLUT.INIT[52] origin:010-clb-lutinit 26_17
CLBLM_L.SLICEL_X1.BLUT.INIT[53] origin:010-clb-lutinit 27_17
CLBLM_L.SLICEL_X1.BLUT.INIT[54] origin:010-clb-lutinit 26_16
CLBLM_L.SLICEL_X1.BLUT.INIT[55] origin:010-clb-lutinit 27_16
CLBLM_L.SLICEL_X1.BLUT.INIT[56] origin:010-clb-lutinit 29_19
CLBLM_L.SLICEL_X1.BLUT.INIT[57] origin:010-clb-lutinit 28_19
CLBLM_L.SLICEL_X1.BLUT.INIT[58] origin:010-clb-lutinit 29_18
CLBLM_L.SLICEL_X1.BLUT.INIT[59] origin:010-clb-lutinit 28_18
CLBLM_L.SLICEL_X1.BLUT.INIT[60] origin:010-clb-lutinit 29_17
CLBLM_L.SLICEL_X1.BLUT.INIT[61] origin:010-clb-lutinit 28_17
CLBLM_L.SLICEL_X1.BLUT.INIT[62] origin:010-clb-lutinit 29_16
CLBLM_L.SLICEL_X1.BLUT.INIT[63] origin:010-clb-lutinit 28_16
CLBLM_L.SLICEL_X1.BOUTMUX.B5Q origin:016-clb-noutmux !30_28 !31_20 !31_21 30_29
CLBLM_L.SLICEL_X1.BOUTMUX.CY origin:016-clb-noutmux !30_29 !31_20 30_28 31_21
CLBLM_L.SLICEL_X1.BOUTMUX.F8 origin:016-clb-noutmux !30_28 !31_20 30_29 31_21
CLBLM_L.SLICEL_X1.BOUTMUX.O5 origin:016-clb-noutmux !30_28 !30_29 31_20 31_21
CLBLM_L.SLICEL_X1.BOUTMUX.O6 origin:016-clb-noutmux !30_28 !30_29 !31_21 31_20
CLBLM_L.SLICEL_X1.BOUTMUX.XOR origin:016-clb-noutmux !30_29 !31_20 !31_21 30_28
CLBLM_L.SLICEL_X1.C5FF.ZINI origin:011-clb-ffconfig 31_42
CLBLM_L.SLICEL_X1.C5FF.ZRST origin:011-clb-ffconfig 00_44
CLBLM_L.SLICEL_X1.C5FFMUX.IN_A origin:012-clb-n5ffmux 31_44
CLBLM_L.SLICEL_X1.C5FFMUX.IN_B origin:012-clb-n5ffmux 31_39
CLBLM_L.SLICEL_X1.CARRY4.ACY0 origin:013-clb-ncy0 31_14
CLBLM_L.SLICEL_X1.CARRY4.BCY0 origin:013-clb-ncy0 00_08
CLBLM_L.SLICEL_X1.CARRY4.CCY0 origin:013-clb-ncy0 31_48
CLBLM_L.SLICEL_X1.CARRY4.DCY0 origin:013-clb-ncy0 31_49
CLBLM_L.SLICEL_X1.CEUSEDMUX origin:014-clb-ffsrcemux 00_36
CLBLM_L.SLICEL_X1.CFF.ZINI origin:011-clb-ffconfig 31_34
CLBLM_L.SLICEL_X1.CFF.ZRST origin:011-clb-ffconfig 30_34
CLBLM_L.SLICEL_X1.CFFMUX.CX origin:015-clb-nffmux !31_35 !31_36 !31_37 31_38
CLBLM_L.SLICEL_X1.CFFMUX.CY origin:015-clb-nffmux !31_36 !31_38 31_35 31_37
CLBLM_L.SLICEL_X1.CFFMUX.F7 origin:015-clb-nffmux !31_36 !31_37 31_35 31_38
CLBLM_L.SLICEL_X1.CFFMUX.O5 origin:015-clb-nffmux !31_37 !31_38 31_35 31_36
CLBLM_L.SLICEL_X1.CFFMUX.O6 origin:015-clb-nffmux !31_35 !31_37 !31_38 31_36
CLBLM_L.SLICEL_X1.CFFMUX.XOR origin:015-clb-nffmux !31_35 !31_36 !31_38 31_37
CLBLM_L.SLICEL_X1.CLKINV origin:011-clb-ffconfig 00_52
CLBLM_L.SLICEL_X1.CLUT.INIT[00] origin:010-clb-lutinit 26_47
CLBLM_L.SLICEL_X1.CLUT.INIT[01] origin:010-clb-lutinit 27_47
CLBLM_L.SLICEL_X1.CLUT.INIT[02] origin:010-clb-lutinit 26_46
CLBLM_L.SLICEL_X1.CLUT.INIT[03] origin:010-clb-lutinit 27_46
CLBLM_L.SLICEL_X1.CLUT.INIT[04] origin:010-clb-lutinit 26_45
CLBLM_L.SLICEL_X1.CLUT.INIT[05] origin:010-clb-lutinit 27_45
CLBLM_L.SLICEL_X1.CLUT.INIT[06] origin:010-clb-lutinit 26_44
CLBLM_L.SLICEL_X1.CLUT.INIT[07] origin:010-clb-lutinit 27_44
CLBLM_L.SLICEL_X1.CLUT.INIT[08] origin:010-clb-lutinit 29_47
CLBLM_L.SLICEL_X1.CLUT.INIT[09] origin:010-clb-lutinit 28_47
CLBLM_L.SLICEL_X1.CLUT.INIT[10] origin:010-clb-lutinit 29_46
CLBLM_L.SLICEL_X1.CLUT.INIT[11] origin:010-clb-lutinit 28_46
CLBLM_L.SLICEL_X1.CLUT.INIT[12] origin:010-clb-lutinit 29_45
CLBLM_L.SLICEL_X1.CLUT.INIT[13] origin:010-clb-lutinit 28_45
CLBLM_L.SLICEL_X1.CLUT.INIT[14] origin:010-clb-lutinit 29_44
CLBLM_L.SLICEL_X1.CLUT.INIT[15] origin:010-clb-lutinit 28_44
CLBLM_L.SLICEL_X1.CLUT.INIT[16] origin:010-clb-lutinit 26_43
CLBLM_L.SLICEL_X1.CLUT.INIT[17] origin:010-clb-lutinit 27_43
CLBLM_L.SLICEL_X1.CLUT.INIT[18] origin:010-clb-lutinit 26_42
CLBLM_L.SLICEL_X1.CLUT.INIT[19] origin:010-clb-lutinit 27_42
CLBLM_L.SLICEL_X1.CLUT.INIT[20] origin:010-clb-lutinit 26_41
CLBLM_L.SLICEL_X1.CLUT.INIT[21] origin:010-clb-lutinit 27_41
CLBLM_L.SLICEL_X1.CLUT.INIT[22] origin:010-clb-lutinit 26_40
CLBLM_L.SLICEL_X1.CLUT.INIT[23] origin:010-clb-lutinit 27_40
CLBLM_L.SLICEL_X1.CLUT.INIT[24] origin:010-clb-lutinit 29_43
CLBLM_L.SLICEL_X1.CLUT.INIT[25] origin:010-clb-lutinit 28_43
CLBLM_L.SLICEL_X1.CLUT.INIT[26] origin:010-clb-lutinit 29_42
CLBLM_L.SLICEL_X1.CLUT.INIT[27] origin:010-clb-lutinit 28_42
CLBLM_L.SLICEL_X1.CLUT.INIT[28] origin:010-clb-lutinit 29_41
CLBLM_L.SLICEL_X1.CLUT.INIT[29] origin:010-clb-lutinit 28_41
CLBLM_L.SLICEL_X1.CLUT.INIT[30] origin:010-clb-lutinit 29_40
CLBLM_L.SLICEL_X1.CLUT.INIT[31] origin:010-clb-lutinit 28_40
CLBLM_L.SLICEL_X1.CLUT.INIT[32] origin:010-clb-lutinit 26_39
CLBLM_L.SLICEL_X1.CLUT.INIT[33] origin:010-clb-lutinit 27_39
CLBLM_L.SLICEL_X1.CLUT.INIT[34] origin:010-clb-lutinit 26_38
CLBLM_L.SLICEL_X1.CLUT.INIT[35] origin:010-clb-lutinit 27_38
CLBLM_L.SLICEL_X1.CLUT.INIT[36] origin:010-clb-lutinit 26_37
CLBLM_L.SLICEL_X1.CLUT.INIT[37] origin:010-clb-lutinit 27_37
CLBLM_L.SLICEL_X1.CLUT.INIT[38] origin:010-clb-lutinit 26_36
CLBLM_L.SLICEL_X1.CLUT.INIT[39] origin:010-clb-lutinit 27_36
CLBLM_L.SLICEL_X1.CLUT.INIT[40] origin:010-clb-lutinit 29_39
CLBLM_L.SLICEL_X1.CLUT.INIT[41] origin:010-clb-lutinit 28_39
CLBLM_L.SLICEL_X1.CLUT.INIT[42] origin:010-clb-lutinit 29_38
CLBLM_L.SLICEL_X1.CLUT.INIT[43] origin:010-clb-lutinit 28_38
CLBLM_L.SLICEL_X1.CLUT.INIT[44] origin:010-clb-lutinit 29_37
CLBLM_L.SLICEL_X1.CLUT.INIT[45] origin:010-clb-lutinit 28_37
CLBLM_L.SLICEL_X1.CLUT.INIT[46] origin:010-clb-lutinit 29_36
CLBLM_L.SLICEL_X1.CLUT.INIT[47] origin:010-clb-lutinit 28_36
CLBLM_L.SLICEL_X1.CLUT.INIT[48] origin:010-clb-lutinit 26_35
CLBLM_L.SLICEL_X1.CLUT.INIT[49] origin:010-clb-lutinit 27_35
CLBLM_L.SLICEL_X1.CLUT.INIT[50] origin:010-clb-lutinit 26_34
CLBLM_L.SLICEL_X1.CLUT.INIT[51] origin:010-clb-lutinit 27_34
CLBLM_L.SLICEL_X1.CLUT.INIT[52] origin:010-clb-lutinit 26_33
CLBLM_L.SLICEL_X1.CLUT.INIT[53] origin:010-clb-lutinit 27_33
CLBLM_L.SLICEL_X1.CLUT.INIT[54] origin:010-clb-lutinit 26_32
CLBLM_L.SLICEL_X1.CLUT.INIT[55] origin:010-clb-lutinit 27_32
CLBLM_L.SLICEL_X1.CLUT.INIT[56] origin:010-clb-lutinit 29_35
CLBLM_L.SLICEL_X1.CLUT.INIT[57] origin:010-clb-lutinit 28_35
CLBLM_L.SLICEL_X1.CLUT.INIT[58] origin:010-clb-lutinit 29_34
CLBLM_L.SLICEL_X1.CLUT.INIT[59] origin:010-clb-lutinit 28_34
CLBLM_L.SLICEL_X1.CLUT.INIT[60] origin:010-clb-lutinit 29_33
CLBLM_L.SLICEL_X1.CLUT.INIT[61] origin:010-clb-lutinit 28_33
CLBLM_L.SLICEL_X1.CLUT.INIT[62] origin:010-clb-lutinit 29_32
CLBLM_L.SLICEL_X1.CLUT.INIT[63] origin:010-clb-lutinit 28_32
CLBLM_L.SLICEL_X1.COUTMUX.C5Q origin:016-clb-noutmux !30_42 !31_40 !31_43 30_41
CLBLM_L.SLICEL_X1.COUTMUX.CY origin:016-clb-noutmux !30_41 !31_43 30_42 31_40
CLBLM_L.SLICEL_X1.COUTMUX.F7 origin:016-clb-noutmux !30_42 !31_43 30_41 31_40
CLBLM_L.SLICEL_X1.COUTMUX.O5 origin:016-clb-noutmux !30_41 !30_42 31_40 31_43
CLBLM_L.SLICEL_X1.COUTMUX.O6 origin:016-clb-noutmux !30_41 !30_42 !31_40 31_43
CLBLM_L.SLICEL_X1.COUTMUX.XOR origin:016-clb-noutmux !30_41 !31_40 !31_43 30_42
CLBLM_L.SLICEL_X1.D5FF.ZINI origin:011-clb-ffconfig 31_52
CLBLM_L.SLICEL_X1.D5FF.ZRST origin:011-clb-ffconfig 00_56
CLBLM_L.SLICEL_X1.D5FFMUX.IN_A origin:012-clb-n5ffmux 31_55
CLBLM_L.SLICEL_X1.D5FFMUX.IN_B origin:012-clb-n5ffmux 31_54
CLBLM_L.SLICEL_X1.DFF.ZINI origin:011-clb-ffconfig 31_59
CLBLM_L.SLICEL_X1.DFF.ZRST origin:011-clb-ffconfig 31_50
CLBLM_L.SLICEL_X1.DFFMUX.CY origin:015-clb-nffmux !31_60 !31_61 30_58 31_62
CLBLM_L.SLICEL_X1.DFFMUX.DX origin:015-clb-nffmux !30_58 !31_60 !31_62 31_61
CLBLM_L.SLICEL_X1.DFFMUX.O5 origin:015-clb-nffmux !31_61 !31_62 30_58 31_60
CLBLM_L.SLICEL_X1.DFFMUX.O6 origin:015-clb-nffmux !30_58 !31_61 !31_62 31_60
CLBLM_L.SLICEL_X1.DFFMUX.XOR origin:015-clb-nffmux !30_58 !31_60 !31_61 31_62
CLBLM_L.SLICEL_X1.DLUT.INIT[00] origin:010-clb-lutinit 26_63
CLBLM_L.SLICEL_X1.DLUT.INIT[01] origin:010-clb-lutinit 27_63
CLBLM_L.SLICEL_X1.DLUT.INIT[02] origin:010-clb-lutinit 26_62
CLBLM_L.SLICEL_X1.DLUT.INIT[03] origin:010-clb-lutinit 27_62
CLBLM_L.SLICEL_X1.DLUT.INIT[04] origin:010-clb-lutinit 26_61
CLBLM_L.SLICEL_X1.DLUT.INIT[05] origin:010-clb-lutinit 27_61
CLBLM_L.SLICEL_X1.DLUT.INIT[06] origin:010-clb-lutinit 26_60
CLBLM_L.SLICEL_X1.DLUT.INIT[07] origin:010-clb-lutinit 27_60
CLBLM_L.SLICEL_X1.DLUT.INIT[08] origin:010-clb-lutinit 29_63
CLBLM_L.SLICEL_X1.DLUT.INIT[09] origin:010-clb-lutinit 28_63
CLBLM_L.SLICEL_X1.DLUT.INIT[10] origin:010-clb-lutinit 29_62
CLBLM_L.SLICEL_X1.DLUT.INIT[11] origin:010-clb-lutinit 28_62
CLBLM_L.SLICEL_X1.DLUT.INIT[12] origin:010-clb-lutinit 29_61
CLBLM_L.SLICEL_X1.DLUT.INIT[13] origin:010-clb-lutinit 28_61
CLBLM_L.SLICEL_X1.DLUT.INIT[14] origin:010-clb-lutinit 29_60
CLBLM_L.SLICEL_X1.DLUT.INIT[15] origin:010-clb-lutinit 28_60
CLBLM_L.SLICEL_X1.DLUT.INIT[16] origin:010-clb-lutinit 26_59
CLBLM_L.SLICEL_X1.DLUT.INIT[17] origin:010-clb-lutinit 27_59
CLBLM_L.SLICEL_X1.DLUT.INIT[18] origin:010-clb-lutinit 26_58
CLBLM_L.SLICEL_X1.DLUT.INIT[19] origin:010-clb-lutinit 27_58
CLBLM_L.SLICEL_X1.DLUT.INIT[20] origin:010-clb-lutinit 26_57
CLBLM_L.SLICEL_X1.DLUT.INIT[21] origin:010-clb-lutinit 27_57
CLBLM_L.SLICEL_X1.DLUT.INIT[22] origin:010-clb-lutinit 26_56
CLBLM_L.SLICEL_X1.DLUT.INIT[23] origin:010-clb-lutinit 27_56
CLBLM_L.SLICEL_X1.DLUT.INIT[24] origin:010-clb-lutinit 29_59
CLBLM_L.SLICEL_X1.DLUT.INIT[25] origin:010-clb-lutinit 28_59
CLBLM_L.SLICEL_X1.DLUT.INIT[26] origin:010-clb-lutinit 29_58
CLBLM_L.SLICEL_X1.DLUT.INIT[27] origin:010-clb-lutinit 28_58
CLBLM_L.SLICEL_X1.DLUT.INIT[28] origin:010-clb-lutinit 29_57
CLBLM_L.SLICEL_X1.DLUT.INIT[29] origin:010-clb-lutinit 28_57
CLBLM_L.SLICEL_X1.DLUT.INIT[30] origin:010-clb-lutinit 29_56
CLBLM_L.SLICEL_X1.DLUT.INIT[31] origin:010-clb-lutinit 28_56
CLBLM_L.SLICEL_X1.DLUT.INIT[32] origin:010-clb-lutinit 26_55
CLBLM_L.SLICEL_X1.DLUT.INIT[33] origin:010-clb-lutinit 27_55
CLBLM_L.SLICEL_X1.DLUT.INIT[34] origin:010-clb-lutinit 26_54
CLBLM_L.SLICEL_X1.DLUT.INIT[35] origin:010-clb-lutinit 27_54
CLBLM_L.SLICEL_X1.DLUT.INIT[36] origin:010-clb-lutinit 26_53
CLBLM_L.SLICEL_X1.DLUT.INIT[37] origin:010-clb-lutinit 27_53
CLBLM_L.SLICEL_X1.DLUT.INIT[38] origin:010-clb-lutinit 26_52
CLBLM_L.SLICEL_X1.DLUT.INIT[39] origin:010-clb-lutinit 27_52
CLBLM_L.SLICEL_X1.DLUT.INIT[40] origin:010-clb-lutinit 29_55
CLBLM_L.SLICEL_X1.DLUT.INIT[41] origin:010-clb-lutinit 28_55
CLBLM_L.SLICEL_X1.DLUT.INIT[42] origin:010-clb-lutinit 29_54
CLBLM_L.SLICEL_X1.DLUT.INIT[43] origin:010-clb-lutinit 28_54
CLBLM_L.SLICEL_X1.DLUT.INIT[44] origin:010-clb-lutinit 29_53
CLBLM_L.SLICEL_X1.DLUT.INIT[45] origin:010-clb-lutinit 28_53
CLBLM_L.SLICEL_X1.DLUT.INIT[46] origin:010-clb-lutinit 29_52
CLBLM_L.SLICEL_X1.DLUT.INIT[47] origin:010-clb-lutinit 28_52
CLBLM_L.SLICEL_X1.DLUT.INIT[48] origin:010-clb-lutinit 26_51
CLBLM_L.SLICEL_X1.DLUT.INIT[49] origin:010-clb-lutinit 27_51
CLBLM_L.SLICEL_X1.DLUT.INIT[50] origin:010-clb-lutinit 26_50
CLBLM_L.SLICEL_X1.DLUT.INIT[51] origin:010-clb-lutinit 27_50
CLBLM_L.SLICEL_X1.DLUT.INIT[52] origin:010-clb-lutinit 26_49
CLBLM_L.SLICEL_X1.DLUT.INIT[53] origin:010-clb-lutinit 27_49
CLBLM_L.SLICEL_X1.DLUT.INIT[54] origin:010-clb-lutinit 26_48
CLBLM_L.SLICEL_X1.DLUT.INIT[55] origin:010-clb-lutinit 27_48
CLBLM_L.SLICEL_X1.DLUT.INIT[56] origin:010-clb-lutinit 29_51
CLBLM_L.SLICEL_X1.DLUT.INIT[57] origin:010-clb-lutinit 28_51
CLBLM_L.SLICEL_X1.DLUT.INIT[58] origin:010-clb-lutinit 29_50
CLBLM_L.SLICEL_X1.DLUT.INIT[59] origin:010-clb-lutinit 28_50
CLBLM_L.SLICEL_X1.DLUT.INIT[60] origin:010-clb-lutinit 29_49
CLBLM_L.SLICEL_X1.DLUT.INIT[61] origin:010-clb-lutinit 28_49
CLBLM_L.SLICEL_X1.DLUT.INIT[62] origin:010-clb-lutinit 29_48
CLBLM_L.SLICEL_X1.DLUT.INIT[63] origin:010-clb-lutinit 28_48
CLBLM_L.SLICEL_X1.DOUTMUX.CY origin:016-clb-noutmux !31_53 !31_56 30_53 31_57
CLBLM_L.SLICEL_X1.DOUTMUX.D5Q origin:016-clb-noutmux !30_53 !31_56 !31_57 31_53
CLBLM_L.SLICEL_X1.DOUTMUX.O5 origin:016-clb-noutmux !30_53 !31_53 31_56 31_57
CLBLM_L.SLICEL_X1.DOUTMUX.O6 origin:016-clb-noutmux !30_53 !31_53 !31_57 31_56
CLBLM_L.SLICEL_X1.DOUTMUX.XOR origin:016-clb-noutmux !31_53 !31_56 !31_57 30_53
CLBLM_L.SLICEL_X1.FFSYNC origin:011-clb-ffconfig 01_31
CLBLM_L.SLICEL_X1.LATCH origin:011-clb-ffconfig 31_32
CLBLM_L.SLICEL_X1.PRECYINIT.AX origin:017-clb-precyinit !01_11 !31_12 31_13
CLBLM_L.SLICEL_X1.PRECYINIT.C0 origin:017-clb-precyinit !01_11 !31_12 !31_13
CLBLM_L.SLICEL_X1.PRECYINIT.C1 origin:017-clb-precyinit !31_12 !31_13 01_11
CLBLM_L.SLICEL_X1.PRECYINIT.CIN origin:017-clb-precyinit !01_11 !31_13 31_12
CLBLM_L.SLICEL_X1.SRUSEDMUX origin:014-clb-ffsrcemux 00_32
CLBLM_L.SLICEM_X0.A5FF.ZINI origin:011-clb-ffconfig 31_06
CLBLM_L.SLICEM_X0.A5FF.ZRST origin:011-clb-ffconfig 01_07
CLBLM_L.SLICEM_X0.A5FFMUX.IN_A origin:012-clb-n5ffmux 30_09
CLBLM_L.SLICEM_X0.A5FFMUX.IN_B origin:012-clb-n5ffmux 30_10
CLBLM_L.SLICEM_X0.AFF.ZINI origin:011-clb-ffconfig 31_03
CLBLM_L.SLICEM_X0.AFF.ZRST origin:011-clb-ffconfig 30_12
CLBLM_L.SLICEM_X0.AFFMUX.AX origin:015-clb-nffmux !30_00 !30_02 !30_03 30_01
CLBLM_L.SLICEM_X0.AFFMUX.CY origin:015-clb-nffmux !30_01 !30_03 30_00 30_02
CLBLM_L.SLICEM_X0.AFFMUX.F7 origin:015-clb-nffmux !30_02 !30_03 30_00 30_01
CLBLM_L.SLICEM_X0.AFFMUX.O5 origin:015-clb-nffmux !30_01 !30_02 30_00 30_03
CLBLM_L.SLICEM_X0.AFFMUX.O6 origin:015-clb-nffmux !30_00 !30_01 !30_02 30_03
CLBLM_L.SLICEM_X0.AFFMUX.XOR origin:015-clb-nffmux !30_00 !30_01 !30_03 30_02
CLBLM_L.SLICEM_X0.ALUT.DI1MUX.AI origin:019-clb-ndi1mux 00_00
CLBLM_L.SLICEM_X0.ALUT.INIT[00] origin:010-clb-lutinit 34_15
CLBLM_L.SLICEM_X0.ALUT.INIT[01] origin:010-clb-lutinit 35_15
CLBLM_L.SLICEM_X0.ALUT.INIT[02] origin:010-clb-lutinit 34_14
CLBLM_L.SLICEM_X0.ALUT.INIT[03] origin:010-clb-lutinit 35_14
CLBLM_L.SLICEM_X0.ALUT.INIT[04] origin:010-clb-lutinit 34_13
CLBLM_L.SLICEM_X0.ALUT.INIT[05] origin:010-clb-lutinit 35_13
CLBLM_L.SLICEM_X0.ALUT.INIT[06] origin:010-clb-lutinit 34_12
CLBLM_L.SLICEM_X0.ALUT.INIT[07] origin:010-clb-lutinit 35_12
CLBLM_L.SLICEM_X0.ALUT.INIT[08] origin:010-clb-lutinit 32_15
CLBLM_L.SLICEM_X0.ALUT.INIT[09] origin:010-clb-lutinit 33_15
CLBLM_L.SLICEM_X0.ALUT.INIT[10] origin:010-clb-lutinit 32_14
CLBLM_L.SLICEM_X0.ALUT.INIT[11] origin:010-clb-lutinit 33_14
CLBLM_L.SLICEM_X0.ALUT.INIT[12] origin:010-clb-lutinit 32_13
CLBLM_L.SLICEM_X0.ALUT.INIT[13] origin:010-clb-lutinit 33_13
CLBLM_L.SLICEM_X0.ALUT.INIT[14] origin:010-clb-lutinit 32_12
CLBLM_L.SLICEM_X0.ALUT.INIT[15] origin:010-clb-lutinit 33_12
CLBLM_L.SLICEM_X0.ALUT.INIT[16] origin:010-clb-lutinit 34_11
CLBLM_L.SLICEM_X0.ALUT.INIT[17] origin:010-clb-lutinit 35_11
CLBLM_L.SLICEM_X0.ALUT.INIT[18] origin:010-clb-lutinit 34_10
CLBLM_L.SLICEM_X0.ALUT.INIT[19] origin:010-clb-lutinit 35_10
CLBLM_L.SLICEM_X0.ALUT.INIT[20] origin:010-clb-lutinit 34_09
CLBLM_L.SLICEM_X0.ALUT.INIT[21] origin:010-clb-lutinit 35_09
CLBLM_L.SLICEM_X0.ALUT.INIT[22] origin:010-clb-lutinit 34_08
CLBLM_L.SLICEM_X0.ALUT.INIT[23] origin:010-clb-lutinit 35_08
CLBLM_L.SLICEM_X0.ALUT.INIT[24] origin:010-clb-lutinit 32_11
CLBLM_L.SLICEM_X0.ALUT.INIT[25] origin:010-clb-lutinit 33_11
CLBLM_L.SLICEM_X0.ALUT.INIT[26] origin:010-clb-lutinit 32_10
CLBLM_L.SLICEM_X0.ALUT.INIT[27] origin:010-clb-lutinit 33_10
CLBLM_L.SLICEM_X0.ALUT.INIT[28] origin:010-clb-lutinit 32_09
CLBLM_L.SLICEM_X0.ALUT.INIT[29] origin:010-clb-lutinit 33_09
CLBLM_L.SLICEM_X0.ALUT.INIT[30] origin:010-clb-lutinit 32_08
CLBLM_L.SLICEM_X0.ALUT.INIT[31] origin:010-clb-lutinit 33_08
CLBLM_L.SLICEM_X0.ALUT.INIT[32] origin:010-clb-lutinit 34_07
CLBLM_L.SLICEM_X0.ALUT.INIT[33] origin:010-clb-lutinit 35_07
CLBLM_L.SLICEM_X0.ALUT.INIT[34] origin:010-clb-lutinit 34_06
CLBLM_L.SLICEM_X0.ALUT.INIT[35] origin:010-clb-lutinit 35_06
CLBLM_L.SLICEM_X0.ALUT.INIT[36] origin:010-clb-lutinit 34_05
CLBLM_L.SLICEM_X0.ALUT.INIT[37] origin:010-clb-lutinit 35_05
CLBLM_L.SLICEM_X0.ALUT.INIT[38] origin:010-clb-lutinit 34_04
CLBLM_L.SLICEM_X0.ALUT.INIT[39] origin:010-clb-lutinit 35_04
CLBLM_L.SLICEM_X0.ALUT.INIT[40] origin:010-clb-lutinit 32_07
CLBLM_L.SLICEM_X0.ALUT.INIT[41] origin:010-clb-lutinit 33_07
CLBLM_L.SLICEM_X0.ALUT.INIT[42] origin:010-clb-lutinit 32_06
CLBLM_L.SLICEM_X0.ALUT.INIT[43] origin:010-clb-lutinit 33_06
CLBLM_L.SLICEM_X0.ALUT.INIT[44] origin:010-clb-lutinit 32_05
CLBLM_L.SLICEM_X0.ALUT.INIT[45] origin:010-clb-lutinit 33_05
CLBLM_L.SLICEM_X0.ALUT.INIT[46] origin:010-clb-lutinit 32_04
CLBLM_L.SLICEM_X0.ALUT.INIT[47] origin:010-clb-lutinit 33_04
CLBLM_L.SLICEM_X0.ALUT.INIT[48] origin:010-clb-lutinit 34_03
CLBLM_L.SLICEM_X0.ALUT.INIT[49] origin:010-clb-lutinit 35_03
CLBLM_L.SLICEM_X0.ALUT.INIT[50] origin:010-clb-lutinit 34_02
CLBLM_L.SLICEM_X0.ALUT.INIT[51] origin:010-clb-lutinit 35_02
CLBLM_L.SLICEM_X0.ALUT.INIT[52] origin:010-clb-lutinit 34_01
CLBLM_L.SLICEM_X0.ALUT.INIT[53] origin:010-clb-lutinit 35_01
CLBLM_L.SLICEM_X0.ALUT.INIT[54] origin:010-clb-lutinit 34_00
CLBLM_L.SLICEM_X0.ALUT.INIT[55] origin:010-clb-lutinit 35_00
CLBLM_L.SLICEM_X0.ALUT.INIT[56] origin:010-clb-lutinit 32_03
CLBLM_L.SLICEM_X0.ALUT.INIT[57] origin:010-clb-lutinit 33_03
CLBLM_L.SLICEM_X0.ALUT.INIT[58] origin:010-clb-lutinit 32_02
CLBLM_L.SLICEM_X0.ALUT.INIT[59] origin:010-clb-lutinit 33_02
CLBLM_L.SLICEM_X0.ALUT.INIT[60] origin:010-clb-lutinit 32_01
CLBLM_L.SLICEM_X0.ALUT.INIT[61] origin:010-clb-lutinit 33_01
CLBLM_L.SLICEM_X0.ALUT.INIT[62] origin:010-clb-lutinit 32_00
CLBLM_L.SLICEM_X0.ALUT.INIT[63] origin:010-clb-lutinit 33_00
CLBLM_L.SLICEM_X0.ALUT.RAM origin:018-clb-ram 31_16
CLBLM_L.SLICEM_X0.ALUT.SMALL origin:018-clb-ram 00_04
CLBLM_L.SLICEM_X0.ALUT.SRL origin:018-clb-ram 30_16
CLBLM_L.SLICEM_X0.AOUTMUX.A5Q origin:016-clb-noutmux !30_06 !30_08 !30_11 30_07
CLBLM_L.SLICEM_X0.AOUTMUX.CY origin:016-clb-noutmux !30_07 !30_11 30_06 30_08
CLBLM_L.SLICEM_X0.AOUTMUX.F7 origin:016-clb-noutmux !30_08 !30_11 30_06 30_07
CLBLM_L.SLICEM_X0.AOUTMUX.O5 origin:016-clb-noutmux !30_07 !30_08 30_06 30_11
CLBLM_L.SLICEM_X0.AOUTMUX.O6 origin:016-clb-noutmux !30_06 !30_07 !30_08 30_11
CLBLM_L.SLICEM_X0.AOUTMUX.XOR origin:016-clb-noutmux !30_06 !30_07 !30_11 30_08
CLBLM_L.SLICEM_X0.B5FF.ZINI origin:011-clb-ffconfig 31_22
CLBLM_L.SLICEM_X0.B5FF.ZRST origin:011-clb-ffconfig 01_19
CLBLM_L.SLICEM_X0.B5FFMUX.IN_A origin:012-clb-n5ffmux 30_19
CLBLM_L.SLICEM_X0.B5FFMUX.IN_B origin:012-clb-n5ffmux 30_18
CLBLM_L.SLICEM_X0.BFF.ZINI origin:011-clb-ffconfig 31_28
CLBLM_L.SLICEM_X0.BFF.ZRST origin:011-clb-ffconfig 30_30
CLBLM_L.SLICEM_X0.BFFMUX.BX origin:015-clb-nffmux !30_24 !30_25 !30_27 30_26
CLBLM_L.SLICEM_X0.BFFMUX.CY origin:015-clb-nffmux !30_24 !30_26 30_25 30_27
CLBLM_L.SLICEM_X0.BFFMUX.F8 origin:015-clb-nffmux !30_24 !30_25 30_26 30_27
CLBLM_L.SLICEM_X0.BFFMUX.O5 origin:015-clb-nffmux !30_25 !30_26 30_24 30_27
CLBLM_L.SLICEM_X0.BFFMUX.O6 origin:015-clb-nffmux !30_25 !30_26 !30_27 30_24
CLBLM_L.SLICEM_X0.BFFMUX.XOR origin:015-clb-nffmux !30_24 !30_26 !30_27 30_25
CLBLM_L.SLICEM_X0.BLUT.DI1MUX.BI origin:019-clb-ndi1mux 00_20
CLBLM_L.SLICEM_X0.BLUT.INIT[00] origin:010-clb-lutinit 34_31
CLBLM_L.SLICEM_X0.BLUT.INIT[01] origin:010-clb-lutinit 35_31
CLBLM_L.SLICEM_X0.BLUT.INIT[02] origin:010-clb-lutinit 34_30
CLBLM_L.SLICEM_X0.BLUT.INIT[03] origin:010-clb-lutinit 35_30
CLBLM_L.SLICEM_X0.BLUT.INIT[04] origin:010-clb-lutinit 34_29
CLBLM_L.SLICEM_X0.BLUT.INIT[05] origin:010-clb-lutinit 35_29
CLBLM_L.SLICEM_X0.BLUT.INIT[06] origin:010-clb-lutinit 34_28
CLBLM_L.SLICEM_X0.BLUT.INIT[07] origin:010-clb-lutinit 35_28
CLBLM_L.SLICEM_X0.BLUT.INIT[08] origin:010-clb-lutinit 32_31
CLBLM_L.SLICEM_X0.BLUT.INIT[09] origin:010-clb-lutinit 33_31
CLBLM_L.SLICEM_X0.BLUT.INIT[10] origin:010-clb-lutinit 32_30
CLBLM_L.SLICEM_X0.BLUT.INIT[11] origin:010-clb-lutinit 33_30
CLBLM_L.SLICEM_X0.BLUT.INIT[12] origin:010-clb-lutinit 32_29
CLBLM_L.SLICEM_X0.BLUT.INIT[13] origin:010-clb-lutinit 33_29
CLBLM_L.SLICEM_X0.BLUT.INIT[14] origin:010-clb-lutinit 32_28
CLBLM_L.SLICEM_X0.BLUT.INIT[15] origin:010-clb-lutinit 33_28
CLBLM_L.SLICEM_X0.BLUT.INIT[16] origin:010-clb-lutinit 34_27
CLBLM_L.SLICEM_X0.BLUT.INIT[17] origin:010-clb-lutinit 35_27
CLBLM_L.SLICEM_X0.BLUT.INIT[18] origin:010-clb-lutinit 34_26
CLBLM_L.SLICEM_X0.BLUT.INIT[19] origin:010-clb-lutinit 35_26
CLBLM_L.SLICEM_X0.BLUT.INIT[20] origin:010-clb-lutinit 34_25
CLBLM_L.SLICEM_X0.BLUT.INIT[21] origin:010-clb-lutinit 35_25
CLBLM_L.SLICEM_X0.BLUT.INIT[22] origin:010-clb-lutinit 34_24
CLBLM_L.SLICEM_X0.BLUT.INIT[23] origin:010-clb-lutinit 35_24
CLBLM_L.SLICEM_X0.BLUT.INIT[24] origin:010-clb-lutinit 32_27
CLBLM_L.SLICEM_X0.BLUT.INIT[25] origin:010-clb-lutinit 33_27
CLBLM_L.SLICEM_X0.BLUT.INIT[26] origin:010-clb-lutinit 32_26
CLBLM_L.SLICEM_X0.BLUT.INIT[27] origin:010-clb-lutinit 33_26
CLBLM_L.SLICEM_X0.BLUT.INIT[28] origin:010-clb-lutinit 32_25
CLBLM_L.SLICEM_X0.BLUT.INIT[29] origin:010-clb-lutinit 33_25
CLBLM_L.SLICEM_X0.BLUT.INIT[30] origin:010-clb-lutinit 32_24
CLBLM_L.SLICEM_X0.BLUT.INIT[31] origin:010-clb-lutinit 33_24
CLBLM_L.SLICEM_X0.BLUT.INIT[32] origin:010-clb-lutinit 34_23
CLBLM_L.SLICEM_X0.BLUT.INIT[33] origin:010-clb-lutinit 35_23
CLBLM_L.SLICEM_X0.BLUT.INIT[34] origin:010-clb-lutinit 34_22
CLBLM_L.SLICEM_X0.BLUT.INIT[35] origin:010-clb-lutinit 35_22
CLBLM_L.SLICEM_X0.BLUT.INIT[36] origin:010-clb-lutinit 34_21
CLBLM_L.SLICEM_X0.BLUT.INIT[37] origin:010-clb-lutinit 35_21
CLBLM_L.SLICEM_X0.BLUT.INIT[38] origin:010-clb-lutinit 34_20
CLBLM_L.SLICEM_X0.BLUT.INIT[39] origin:010-clb-lutinit 35_20
CLBLM_L.SLICEM_X0.BLUT.INIT[40] origin:010-clb-lutinit 32_23
CLBLM_L.SLICEM_X0.BLUT.INIT[41] origin:010-clb-lutinit 33_23
CLBLM_L.SLICEM_X0.BLUT.INIT[42] origin:010-clb-lutinit 32_22
CLBLM_L.SLICEM_X0.BLUT.INIT[43] origin:010-clb-lutinit 33_22
CLBLM_L.SLICEM_X0.BLUT.INIT[44] origin:010-clb-lutinit 32_21
CLBLM_L.SLICEM_X0.BLUT.INIT[45] origin:010-clb-lutinit 33_21
CLBLM_L.SLICEM_X0.BLUT.INIT[46] origin:010-clb-lutinit 32_20
CLBLM_L.SLICEM_X0.BLUT.INIT[47] origin:010-clb-lutinit 33_20
CLBLM_L.SLICEM_X0.BLUT.INIT[48] origin:010-clb-lutinit 34_19
CLBLM_L.SLICEM_X0.BLUT.INIT[49] origin:010-clb-lutinit 35_19
CLBLM_L.SLICEM_X0.BLUT.INIT[50] origin:010-clb-lutinit 34_18
CLBLM_L.SLICEM_X0.BLUT.INIT[51] origin:010-clb-lutinit 35_18
CLBLM_L.SLICEM_X0.BLUT.INIT[52] origin:010-clb-lutinit 34_17
CLBLM_L.SLICEM_X0.BLUT.INIT[53] origin:010-clb-lutinit 35_17
CLBLM_L.SLICEM_X0.BLUT.INIT[54] origin:010-clb-lutinit 34_16
CLBLM_L.SLICEM_X0.BLUT.INIT[55] origin:010-clb-lutinit 35_16
CLBLM_L.SLICEM_X0.BLUT.INIT[56] origin:010-clb-lutinit 32_19
CLBLM_L.SLICEM_X0.BLUT.INIT[57] origin:010-clb-lutinit 33_19
CLBLM_L.SLICEM_X0.BLUT.INIT[58] origin:010-clb-lutinit 32_18
CLBLM_L.SLICEM_X0.BLUT.INIT[59] origin:010-clb-lutinit 33_18
CLBLM_L.SLICEM_X0.BLUT.INIT[60] origin:010-clb-lutinit 32_17
CLBLM_L.SLICEM_X0.BLUT.INIT[61] origin:010-clb-lutinit 33_17
CLBLM_L.SLICEM_X0.BLUT.INIT[62] origin:010-clb-lutinit 32_16
CLBLM_L.SLICEM_X0.BLUT.INIT[63] origin:010-clb-lutinit 33_16
CLBLM_L.SLICEM_X0.BLUT.RAM origin:018-clb-ram 31_17
CLBLM_L.SLICEM_X0.BLUT.SMALL origin:018-clb-ram 00_24
CLBLM_L.SLICEM_X0.BLUT.SRL origin:018-clb-ram 30_17
CLBLM_L.SLICEM_X0.BOUTMUX.B5Q origin:016-clb-noutmux !30_20 !30_21 !30_22 30_23
CLBLM_L.SLICEM_X0.BOUTMUX.CY origin:016-clb-noutmux !30_20 !30_23 30_21 30_22
CLBLM_L.SLICEM_X0.BOUTMUX.F8 origin:016-clb-noutmux !30_20 !30_21 30_22 30_23
CLBLM_L.SLICEM_X0.BOUTMUX.O5 origin:016-clb-noutmux !30_21 !30_23 30_20 30_22
CLBLM_L.SLICEM_X0.BOUTMUX.O6 origin:016-clb-noutmux !30_21 !30_22 !30_23 30_20
CLBLM_L.SLICEM_X0.BOUTMUX.XOR origin:016-clb-noutmux !30_20 !30_22 !30_23 30_21
CLBLM_L.SLICEM_X0.C5FF.ZINI origin:011-clb-ffconfig 31_41
CLBLM_L.SLICEM_X0.C5FF.ZRST origin:011-clb-ffconfig 01_47
CLBLM_L.SLICEM_X0.C5FFMUX.IN_A origin:012-clb-n5ffmux 31_45
CLBLM_L.SLICEM_X0.C5FFMUX.IN_B origin:012-clb-n5ffmux 30_39
CLBLM_L.SLICEM_X0.CARRY4.ACY0 origin:013-clb-ncy0 30_15
CLBLM_L.SLICEM_X0.CARRY4.BCY0 origin:013-clb-ncy0 01_15
CLBLM_L.SLICEM_X0.CARRY4.CCY0 origin:013-clb-ncy0 30_48
CLBLM_L.SLICEM_X0.CARRY4.DCY0 origin:013-clb-ncy0 30_49
CLBLM_L.SLICEM_X0.CEUSEDMUX origin:014-clb-ffsrcemux 01_39
CLBLM_L.SLICEM_X0.CFF.ZINI origin:011-clb-ffconfig 31_33
CLBLM_L.SLICEM_X0.CFF.ZRST origin:011-clb-ffconfig 30_33
CLBLM_L.SLICEM_X0.CFFMUX.CX origin:015-clb-nffmux !30_35 !30_37 !30_38 30_36
CLBLM_L.SLICEM_X0.CFFMUX.CY origin:015-clb-nffmux !30_36 !30_38 30_35 30_37
CLBLM_L.SLICEM_X0.CFFMUX.F7 origin:015-clb-nffmux !30_37 !30_38 30_35 30_36
CLBLM_L.SLICEM_X0.CFFMUX.O5 origin:015-clb-nffmux !30_36 !30_37 30_35 30_38
CLBLM_L.SLICEM_X0.CFFMUX.O6 origin:015-clb-nffmux !30_35 !30_36 !30_37 30_38
CLBLM_L.SLICEM_X0.CFFMUX.XOR origin:015-clb-nffmux !30_35 !30_36 !30_38 30_37
CLBLM_L.SLICEM_X0.CLKINV origin:011-clb-ffconfig 01_51
CLBLM_L.SLICEM_X0.CLUT.DI1MUX.CI origin:019-clb-ndi1mux 01_43
CLBLM_L.SLICEM_X0.CLUT.INIT[00] origin:010-clb-lutinit 34_47
CLBLM_L.SLICEM_X0.CLUT.INIT[01] origin:010-clb-lutinit 35_47
CLBLM_L.SLICEM_X0.CLUT.INIT[02] origin:010-clb-lutinit 34_46
CLBLM_L.SLICEM_X0.CLUT.INIT[03] origin:010-clb-lutinit 35_46
CLBLM_L.SLICEM_X0.CLUT.INIT[04] origin:010-clb-lutinit 34_45
CLBLM_L.SLICEM_X0.CLUT.INIT[05] origin:010-clb-lutinit 35_45
CLBLM_L.SLICEM_X0.CLUT.INIT[06] origin:010-clb-lutinit 34_44
CLBLM_L.SLICEM_X0.CLUT.INIT[07] origin:010-clb-lutinit 35_44
CLBLM_L.SLICEM_X0.CLUT.INIT[08] origin:010-clb-lutinit 32_47
CLBLM_L.SLICEM_X0.CLUT.INIT[09] origin:010-clb-lutinit 33_47
CLBLM_L.SLICEM_X0.CLUT.INIT[10] origin:010-clb-lutinit 32_46
CLBLM_L.SLICEM_X0.CLUT.INIT[11] origin:010-clb-lutinit 33_46
CLBLM_L.SLICEM_X0.CLUT.INIT[12] origin:010-clb-lutinit 32_45
CLBLM_L.SLICEM_X0.CLUT.INIT[13] origin:010-clb-lutinit 33_45
CLBLM_L.SLICEM_X0.CLUT.INIT[14] origin:010-clb-lutinit 32_44
CLBLM_L.SLICEM_X0.CLUT.INIT[15] origin:010-clb-lutinit 33_44
CLBLM_L.SLICEM_X0.CLUT.INIT[16] origin:010-clb-lutinit 34_43
CLBLM_L.SLICEM_X0.CLUT.INIT[17] origin:010-clb-lutinit 35_43
CLBLM_L.SLICEM_X0.CLUT.INIT[18] origin:010-clb-lutinit 34_42
CLBLM_L.SLICEM_X0.CLUT.INIT[19] origin:010-clb-lutinit 35_42
CLBLM_L.SLICEM_X0.CLUT.INIT[20] origin:010-clb-lutinit 34_41
CLBLM_L.SLICEM_X0.CLUT.INIT[21] origin:010-clb-lutinit 35_41
CLBLM_L.SLICEM_X0.CLUT.INIT[22] origin:010-clb-lutinit 34_40
CLBLM_L.SLICEM_X0.CLUT.INIT[23] origin:010-clb-lutinit 35_40
CLBLM_L.SLICEM_X0.CLUT.INIT[24] origin:010-clb-lutinit 32_43
CLBLM_L.SLICEM_X0.CLUT.INIT[25] origin:010-clb-lutinit 33_43
CLBLM_L.SLICEM_X0.CLUT.INIT[26] origin:010-clb-lutinit 32_42
CLBLM_L.SLICEM_X0.CLUT.INIT[27] origin:010-clb-lutinit 33_42
CLBLM_L.SLICEM_X0.CLUT.INIT[28] origin:010-clb-lutinit 32_41
CLBLM_L.SLICEM_X0.CLUT.INIT[29] origin:010-clb-lutinit 33_41
CLBLM_L.SLICEM_X0.CLUT.INIT[30] origin:010-clb-lutinit 32_40
CLBLM_L.SLICEM_X0.CLUT.INIT[31] origin:010-clb-lutinit 33_40
CLBLM_L.SLICEM_X0.CLUT.INIT[32] origin:010-clb-lutinit 34_39
CLBLM_L.SLICEM_X0.CLUT.INIT[33] origin:010-clb-lutinit 35_39
CLBLM_L.SLICEM_X0.CLUT.INIT[34] origin:010-clb-lutinit 34_38
CLBLM_L.SLICEM_X0.CLUT.INIT[35] origin:010-clb-lutinit 35_38
CLBLM_L.SLICEM_X0.CLUT.INIT[36] origin:010-clb-lutinit 34_37
CLBLM_L.SLICEM_X0.CLUT.INIT[37] origin:010-clb-lutinit 35_37
CLBLM_L.SLICEM_X0.CLUT.INIT[38] origin:010-clb-lutinit 34_36
CLBLM_L.SLICEM_X0.CLUT.INIT[39] origin:010-clb-lutinit 35_36
CLBLM_L.SLICEM_X0.CLUT.INIT[40] origin:010-clb-lutinit 32_39
CLBLM_L.SLICEM_X0.CLUT.INIT[41] origin:010-clb-lutinit 33_39
CLBLM_L.SLICEM_X0.CLUT.INIT[42] origin:010-clb-lutinit 32_38
CLBLM_L.SLICEM_X0.CLUT.INIT[43] origin:010-clb-lutinit 33_38
CLBLM_L.SLICEM_X0.CLUT.INIT[44] origin:010-clb-lutinit 32_37
CLBLM_L.SLICEM_X0.CLUT.INIT[45] origin:010-clb-lutinit 33_37
CLBLM_L.SLICEM_X0.CLUT.INIT[46] origin:010-clb-lutinit 32_36
CLBLM_L.SLICEM_X0.CLUT.INIT[47] origin:010-clb-lutinit 33_36
CLBLM_L.SLICEM_X0.CLUT.INIT[48] origin:010-clb-lutinit 34_35
CLBLM_L.SLICEM_X0.CLUT.INIT[49] origin:010-clb-lutinit 35_35
CLBLM_L.SLICEM_X0.CLUT.INIT[50] origin:010-clb-lutinit 34_34
CLBLM_L.SLICEM_X0.CLUT.INIT[51] origin:010-clb-lutinit 35_34
CLBLM_L.SLICEM_X0.CLUT.INIT[52] origin:010-clb-lutinit 34_33
CLBLM_L.SLICEM_X0.CLUT.INIT[53] origin:010-clb-lutinit 35_33
CLBLM_L.SLICEM_X0.CLUT.INIT[54] origin:010-clb-lutinit 34_32
CLBLM_L.SLICEM_X0.CLUT.INIT[55] origin:010-clb-lutinit 35_32
CLBLM_L.SLICEM_X0.CLUT.INIT[56] origin:010-clb-lutinit 32_35
CLBLM_L.SLICEM_X0.CLUT.INIT[57] origin:010-clb-lutinit 33_35
CLBLM_L.SLICEM_X0.CLUT.INIT[58] origin:010-clb-lutinit 32_34
CLBLM_L.SLICEM_X0.CLUT.INIT[59] origin:010-clb-lutinit 33_34
CLBLM_L.SLICEM_X0.CLUT.INIT[60] origin:010-clb-lutinit 32_33
CLBLM_L.SLICEM_X0.CLUT.INIT[61] origin:010-clb-lutinit 33_33
CLBLM_L.SLICEM_X0.CLUT.INIT[62] origin:010-clb-lutinit 32_32
CLBLM_L.SLICEM_X0.CLUT.INIT[63] origin:010-clb-lutinit 33_32
CLBLM_L.SLICEM_X0.CLUT.RAM origin:018-clb-ram 31_46
CLBLM_L.SLICEM_X0.CLUT.SMALL origin:018-clb-ram 00_28
CLBLM_L.SLICEM_X0.CLUT.SRL origin:018-clb-ram 30_46
CLBLM_L.SLICEM_X0.COUTMUX.C5Q origin:016-clb-noutmux !30_40 !30_44 !30_45 30_43
CLBLM_L.SLICEM_X0.COUTMUX.CY origin:016-clb-noutmux !30_43 !30_45 30_40 30_44
CLBLM_L.SLICEM_X0.COUTMUX.F7 origin:016-clb-noutmux !30_44 !30_45 30_40 30_43
CLBLM_L.SLICEM_X0.COUTMUX.O5 origin:016-clb-noutmux !30_43 !30_44 30_40 30_45
CLBLM_L.SLICEM_X0.COUTMUX.O6 origin:016-clb-noutmux !30_40 !30_43 !30_44 30_45
CLBLM_L.SLICEM_X0.COUTMUX.XOR origin:016-clb-noutmux !30_40 !30_43 !30_45 30_44
CLBLM_L.SLICEM_X0.D5FF.ZINI origin:011-clb-ffconfig 31_51
CLBLM_L.SLICEM_X0.D5FF.ZRST origin:011-clb-ffconfig 01_55
CLBLM_L.SLICEM_X0.D5FFMUX.IN_A origin:012-clb-n5ffmux 30_55
CLBLM_L.SLICEM_X0.D5FFMUX.IN_B origin:012-clb-n5ffmux 30_54
CLBLM_L.SLICEM_X0.DFF.ZINI origin:011-clb-ffconfig 31_58
CLBLM_L.SLICEM_X0.DFF.ZRST origin:011-clb-ffconfig 30_50
CLBLM_L.SLICEM_X0.DFFMUX.CY origin:015-clb-nffmux !30_59 !30_61 30_60 30_62
CLBLM_L.SLICEM_X0.DFFMUX.DX origin:015-clb-nffmux !30_59 !30_60 !30_62 30_61
CLBLM_L.SLICEM_X0.DFFMUX.O5 origin:015-clb-nffmux !30_60 !30_61 30_59 30_62
CLBLM_L.SLICEM_X0.DFFMUX.O6 origin:015-clb-nffmux !30_60 !30_61 !30_62 30_59
CLBLM_L.SLICEM_X0.DFFMUX.XOR origin:015-clb-nffmux !30_59 !30_61 !30_62 30_60
CLBLM_L.SLICEM_X0.DLUT.INIT[00] origin:010-clb-lutinit 34_63
CLBLM_L.SLICEM_X0.DLUT.INIT[01] origin:010-clb-lutinit 35_63
CLBLM_L.SLICEM_X0.DLUT.INIT[02] origin:010-clb-lutinit 34_62
CLBLM_L.SLICEM_X0.DLUT.INIT[03] origin:010-clb-lutinit 35_62
CLBLM_L.SLICEM_X0.DLUT.INIT[04] origin:010-clb-lutinit 34_61
CLBLM_L.SLICEM_X0.DLUT.INIT[05] origin:010-clb-lutinit 35_61
CLBLM_L.SLICEM_X0.DLUT.INIT[06] origin:010-clb-lutinit 34_60
CLBLM_L.SLICEM_X0.DLUT.INIT[07] origin:010-clb-lutinit 35_60
CLBLM_L.SLICEM_X0.DLUT.INIT[08] origin:010-clb-lutinit 32_63
CLBLM_L.SLICEM_X0.DLUT.INIT[09] origin:010-clb-lutinit 33_63
CLBLM_L.SLICEM_X0.DLUT.INIT[10] origin:010-clb-lutinit 32_62
CLBLM_L.SLICEM_X0.DLUT.INIT[11] origin:010-clb-lutinit 33_62
CLBLM_L.SLICEM_X0.DLUT.INIT[12] origin:010-clb-lutinit 32_61
CLBLM_L.SLICEM_X0.DLUT.INIT[13] origin:010-clb-lutinit 33_61
CLBLM_L.SLICEM_X0.DLUT.INIT[14] origin:010-clb-lutinit 32_60
CLBLM_L.SLICEM_X0.DLUT.INIT[15] origin:010-clb-lutinit 33_60
CLBLM_L.SLICEM_X0.DLUT.INIT[16] origin:010-clb-lutinit 34_59
CLBLM_L.SLICEM_X0.DLUT.INIT[17] origin:010-clb-lutinit 35_59
CLBLM_L.SLICEM_X0.DLUT.INIT[18] origin:010-clb-lutinit 34_58
CLBLM_L.SLICEM_X0.DLUT.INIT[19] origin:010-clb-lutinit 35_58
CLBLM_L.SLICEM_X0.DLUT.INIT[20] origin:010-clb-lutinit 34_57
CLBLM_L.SLICEM_X0.DLUT.INIT[21] origin:010-clb-lutinit 35_57
CLBLM_L.SLICEM_X0.DLUT.INIT[22] origin:010-clb-lutinit 34_56
CLBLM_L.SLICEM_X0.DLUT.INIT[23] origin:010-clb-lutinit 35_56
CLBLM_L.SLICEM_X0.DLUT.INIT[24] origin:010-clb-lutinit 32_59
CLBLM_L.SLICEM_X0.DLUT.INIT[25] origin:010-clb-lutinit 33_59
CLBLM_L.SLICEM_X0.DLUT.INIT[26] origin:010-clb-lutinit 32_58
CLBLM_L.SLICEM_X0.DLUT.INIT[27] origin:010-clb-lutinit 33_58
CLBLM_L.SLICEM_X0.DLUT.INIT[28] origin:010-clb-lutinit 32_57
CLBLM_L.SLICEM_X0.DLUT.INIT[29] origin:010-clb-lutinit 33_57
CLBLM_L.SLICEM_X0.DLUT.INIT[30] origin:010-clb-lutinit 32_56
CLBLM_L.SLICEM_X0.DLUT.INIT[31] origin:010-clb-lutinit 33_56
CLBLM_L.SLICEM_X0.DLUT.INIT[32] origin:010-clb-lutinit 34_55
CLBLM_L.SLICEM_X0.DLUT.INIT[33] origin:010-clb-lutinit 35_55
CLBLM_L.SLICEM_X0.DLUT.INIT[34] origin:010-clb-lutinit 34_54
CLBLM_L.SLICEM_X0.DLUT.INIT[35] origin:010-clb-lutinit 35_54
CLBLM_L.SLICEM_X0.DLUT.INIT[36] origin:010-clb-lutinit 34_53
CLBLM_L.SLICEM_X0.DLUT.INIT[37] origin:010-clb-lutinit 35_53
CLBLM_L.SLICEM_X0.DLUT.INIT[38] origin:010-clb-lutinit 34_52
CLBLM_L.SLICEM_X0.DLUT.INIT[39] origin:010-clb-lutinit 35_52
CLBLM_L.SLICEM_X0.DLUT.INIT[40] origin:010-clb-lutinit 32_55
CLBLM_L.SLICEM_X0.DLUT.INIT[41] origin:010-clb-lutinit 33_55
CLBLM_L.SLICEM_X0.DLUT.INIT[42] origin:010-clb-lutinit 32_54
CLBLM_L.SLICEM_X0.DLUT.INIT[43] origin:010-clb-lutinit 33_54
CLBLM_L.SLICEM_X0.DLUT.INIT[44] origin:010-clb-lutinit 32_53
CLBLM_L.SLICEM_X0.DLUT.INIT[45] origin:010-clb-lutinit 33_53
CLBLM_L.SLICEM_X0.DLUT.INIT[46] origin:010-clb-lutinit 32_52
CLBLM_L.SLICEM_X0.DLUT.INIT[47] origin:010-clb-lutinit 33_52
CLBLM_L.SLICEM_X0.DLUT.INIT[48] origin:010-clb-lutinit 34_51
CLBLM_L.SLICEM_X0.DLUT.INIT[49] origin:010-clb-lutinit 35_51
CLBLM_L.SLICEM_X0.DLUT.INIT[50] origin:010-clb-lutinit 34_50
CLBLM_L.SLICEM_X0.DLUT.INIT[51] origin:010-clb-lutinit 35_50
CLBLM_L.SLICEM_X0.DLUT.INIT[52] origin:010-clb-lutinit 34_49
CLBLM_L.SLICEM_X0.DLUT.INIT[53] origin:010-clb-lutinit 35_49
CLBLM_L.SLICEM_X0.DLUT.INIT[54] origin:010-clb-lutinit 34_48
CLBLM_L.SLICEM_X0.DLUT.INIT[55] origin:010-clb-lutinit 35_48
CLBLM_L.SLICEM_X0.DLUT.INIT[56] origin:010-clb-lutinit 32_51
CLBLM_L.SLICEM_X0.DLUT.INIT[57] origin:010-clb-lutinit 33_51
CLBLM_L.SLICEM_X0.DLUT.INIT[58] origin:010-clb-lutinit 32_50
CLBLM_L.SLICEM_X0.DLUT.INIT[59] origin:010-clb-lutinit 33_50
CLBLM_L.SLICEM_X0.DLUT.INIT[60] origin:010-clb-lutinit 32_49
CLBLM_L.SLICEM_X0.DLUT.INIT[61] origin:010-clb-lutinit 33_49
CLBLM_L.SLICEM_X0.DLUT.INIT[62] origin:010-clb-lutinit 32_48
CLBLM_L.SLICEM_X0.DLUT.INIT[63] origin:010-clb-lutinit 33_48
CLBLM_L.SLICEM_X0.DLUT.RAM origin:018-clb-ram 31_47
CLBLM_L.SLICEM_X0.DLUT.SMALL origin:018-clb-ram 01_59
CLBLM_L.SLICEM_X0.DLUT.SRL origin:018-clb-ram 30_47
CLBLM_L.SLICEM_X0.DOUTMUX.CY origin:016-clb-noutmux !30_56 !30_57 30_51 30_52
CLBLM_L.SLICEM_X0.DOUTMUX.D5Q origin:016-clb-noutmux !30_51 !30_52 !30_56 30_57
CLBLM_L.SLICEM_X0.DOUTMUX.O5 origin:016-clb-noutmux !30_51 !30_57 30_52 30_56
CLBLM_L.SLICEM_X0.DOUTMUX.O6 origin:016-clb-noutmux !30_51 !30_52 !30_57 30_56
CLBLM_L.SLICEM_X0.DOUTMUX.XOR origin:016-clb-noutmux !30_52 !30_56 !30_57 30_51
CLBLM_L.SLICEM_X0.FFSYNC origin:011-clb-ffconfig 00_48
CLBLM_L.SLICEM_X0.LATCH origin:011-clb-ffconfig 30_32
CLBLM_L.SLICEM_X0.PRECYINIT.AX origin:017-clb-precyinit !00_12 !30_13 30_14
CLBLM_L.SLICEM_X0.PRECYINIT.C0 origin:017-clb-precyinit !00_12 !30_13 !30_14
CLBLM_L.SLICEM_X0.PRECYINIT.C1 origin:017-clb-precyinit !30_13 !30_14 00_12
CLBLM_L.SLICEM_X0.PRECYINIT.CIN origin:017-clb-precyinit !00_12 !30_14 30_13
CLBLM_L.SLICEM_X0.SRUSEDMUX origin:014-clb-ffsrcemux 01_35
CLBLM_L.SLICEM_X0.WA7USED origin:018-clb-ram 00_40
CLBLM_L.SLICEM_X0.WA8USED origin:018-clb-ram 01_27
CLBLM_L.SLICEM_X0.WEMUX.CE origin:018-clb-ram 01_23

696
zynq7/segbits_clblm_r.origin_info.db Normal file
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@ -0,0 +1,696 @@
CLBLM_R.SLICEL_X1.A5FF.ZINI origin:011-clb-ffconfig 31_05
CLBLM_R.SLICEL_X1.A5FF.ZRST origin:011-clb-ffconfig 01_03
CLBLM_R.SLICEL_X1.A5FFMUX.IN_A origin:012-clb-n5ffmux 31_08
CLBLM_R.SLICEL_X1.A5FFMUX.IN_B origin:012-clb-n5ffmux 31_11
CLBLM_R.SLICEL_X1.AFF.ZINI origin:011-clb-ffconfig 31_04
CLBLM_R.SLICEL_X1.AFF.ZRST origin:011-clb-ffconfig 31_15
CLBLM_R.SLICEL_X1.AFFMUX.AX origin:015-clb-nffmux !30_04 !31_00 !31_02 31_01
CLBLM_R.SLICEL_X1.AFFMUX.CY origin:015-clb-nffmux !30_04 !31_01 31_00 31_02
CLBLM_R.SLICEL_X1.AFFMUX.F7 origin:015-clb-nffmux !30_04 !31_02 31_00 31_01
CLBLM_R.SLICEL_X1.AFFMUX.O5 origin:015-clb-nffmux !31_01 !31_02 30_04 31_00
CLBLM_R.SLICEL_X1.AFFMUX.O6 origin:015-clb-nffmux !31_00 !31_01 !31_02 30_04
CLBLM_R.SLICEL_X1.AFFMUX.XOR origin:015-clb-nffmux !30_04 !31_00 !31_01 31_02
CLBLM_R.SLICEL_X1.ALUT.INIT[00] origin:010-clb-lutinit 26_15
CLBLM_R.SLICEL_X1.ALUT.INIT[01] origin:010-clb-lutinit 27_15
CLBLM_R.SLICEL_X1.ALUT.INIT[02] origin:010-clb-lutinit 26_14
CLBLM_R.SLICEL_X1.ALUT.INIT[03] origin:010-clb-lutinit 27_14
CLBLM_R.SLICEL_X1.ALUT.INIT[04] origin:010-clb-lutinit 26_13
CLBLM_R.SLICEL_X1.ALUT.INIT[05] origin:010-clb-lutinit 27_13
CLBLM_R.SLICEL_X1.ALUT.INIT[06] origin:010-clb-lutinit 26_12
CLBLM_R.SLICEL_X1.ALUT.INIT[07] origin:010-clb-lutinit 27_12
CLBLM_R.SLICEL_X1.ALUT.INIT[08] origin:010-clb-lutinit 29_15
CLBLM_R.SLICEL_X1.ALUT.INIT[09] origin:010-clb-lutinit 28_15
CLBLM_R.SLICEL_X1.ALUT.INIT[10] origin:010-clb-lutinit 29_14
CLBLM_R.SLICEL_X1.ALUT.INIT[11] origin:010-clb-lutinit 28_14
CLBLM_R.SLICEL_X1.ALUT.INIT[12] origin:010-clb-lutinit 29_13
CLBLM_R.SLICEL_X1.ALUT.INIT[13] origin:010-clb-lutinit 28_13
CLBLM_R.SLICEL_X1.ALUT.INIT[14] origin:010-clb-lutinit 29_12
CLBLM_R.SLICEL_X1.ALUT.INIT[15] origin:010-clb-lutinit 28_12
CLBLM_R.SLICEL_X1.ALUT.INIT[16] origin:010-clb-lutinit 26_11
CLBLM_R.SLICEL_X1.ALUT.INIT[17] origin:010-clb-lutinit 27_11
CLBLM_R.SLICEL_X1.ALUT.INIT[18] origin:010-clb-lutinit 26_10
CLBLM_R.SLICEL_X1.ALUT.INIT[19] origin:010-clb-lutinit 27_10
CLBLM_R.SLICEL_X1.ALUT.INIT[20] origin:010-clb-lutinit 26_09
CLBLM_R.SLICEL_X1.ALUT.INIT[21] origin:010-clb-lutinit 27_09
CLBLM_R.SLICEL_X1.ALUT.INIT[22] origin:010-clb-lutinit 26_08
CLBLM_R.SLICEL_X1.ALUT.INIT[23] origin:010-clb-lutinit 27_08
CLBLM_R.SLICEL_X1.ALUT.INIT[24] origin:010-clb-lutinit 29_11
CLBLM_R.SLICEL_X1.ALUT.INIT[25] origin:010-clb-lutinit 28_11
CLBLM_R.SLICEL_X1.ALUT.INIT[26] origin:010-clb-lutinit 29_10
CLBLM_R.SLICEL_X1.ALUT.INIT[27] origin:010-clb-lutinit 28_10
CLBLM_R.SLICEL_X1.ALUT.INIT[28] origin:010-clb-lutinit 29_09
CLBLM_R.SLICEL_X1.ALUT.INIT[29] origin:010-clb-lutinit 28_09
CLBLM_R.SLICEL_X1.ALUT.INIT[30] origin:010-clb-lutinit 29_08
CLBLM_R.SLICEL_X1.ALUT.INIT[31] origin:010-clb-lutinit 28_08
CLBLM_R.SLICEL_X1.ALUT.INIT[32] origin:010-clb-lutinit 26_07
CLBLM_R.SLICEL_X1.ALUT.INIT[33] origin:010-clb-lutinit 27_07
CLBLM_R.SLICEL_X1.ALUT.INIT[34] origin:010-clb-lutinit 26_06
CLBLM_R.SLICEL_X1.ALUT.INIT[35] origin:010-clb-lutinit 27_06
CLBLM_R.SLICEL_X1.ALUT.INIT[36] origin:010-clb-lutinit 26_05
CLBLM_R.SLICEL_X1.ALUT.INIT[37] origin:010-clb-lutinit 27_05
CLBLM_R.SLICEL_X1.ALUT.INIT[38] origin:010-clb-lutinit 26_04
CLBLM_R.SLICEL_X1.ALUT.INIT[39] origin:010-clb-lutinit 27_04
CLBLM_R.SLICEL_X1.ALUT.INIT[40] origin:010-clb-lutinit 29_07
CLBLM_R.SLICEL_X1.ALUT.INIT[41] origin:010-clb-lutinit 28_07
CLBLM_R.SLICEL_X1.ALUT.INIT[42] origin:010-clb-lutinit 29_06
CLBLM_R.SLICEL_X1.ALUT.INIT[43] origin:010-clb-lutinit 28_06
CLBLM_R.SLICEL_X1.ALUT.INIT[44] origin:010-clb-lutinit 29_05
CLBLM_R.SLICEL_X1.ALUT.INIT[45] origin:010-clb-lutinit 28_05
CLBLM_R.SLICEL_X1.ALUT.INIT[46] origin:010-clb-lutinit 29_04
CLBLM_R.SLICEL_X1.ALUT.INIT[47] origin:010-clb-lutinit 28_04
CLBLM_R.SLICEL_X1.ALUT.INIT[48] origin:010-clb-lutinit 26_03
CLBLM_R.SLICEL_X1.ALUT.INIT[49] origin:010-clb-lutinit 27_03
CLBLM_R.SLICEL_X1.ALUT.INIT[50] origin:010-clb-lutinit 26_02
CLBLM_R.SLICEL_X1.ALUT.INIT[51] origin:010-clb-lutinit 27_02
CLBLM_R.SLICEL_X1.ALUT.INIT[52] origin:010-clb-lutinit 26_01
CLBLM_R.SLICEL_X1.ALUT.INIT[53] origin:010-clb-lutinit 27_01
CLBLM_R.SLICEL_X1.ALUT.INIT[54] origin:010-clb-lutinit 26_00
CLBLM_R.SLICEL_X1.ALUT.INIT[55] origin:010-clb-lutinit 27_00
CLBLM_R.SLICEL_X1.ALUT.INIT[56] origin:010-clb-lutinit 29_03
CLBLM_R.SLICEL_X1.ALUT.INIT[57] origin:010-clb-lutinit 28_03
CLBLM_R.SLICEL_X1.ALUT.INIT[58] origin:010-clb-lutinit 29_02
CLBLM_R.SLICEL_X1.ALUT.INIT[59] origin:010-clb-lutinit 28_02
CLBLM_R.SLICEL_X1.ALUT.INIT[60] origin:010-clb-lutinit 29_01
CLBLM_R.SLICEL_X1.ALUT.INIT[61] origin:010-clb-lutinit 28_01
CLBLM_R.SLICEL_X1.ALUT.INIT[62] origin:010-clb-lutinit 29_00
CLBLM_R.SLICEL_X1.ALUT.INIT[63] origin:010-clb-lutinit 28_00
CLBLM_R.SLICEL_X1.AOUTMUX.A5Q origin:016-clb-noutmux !31_07 !31_09 !31_10 30_05
CLBLM_R.SLICEL_X1.AOUTMUX.CY origin:016-clb-noutmux !30_05 !31_09 31_07 31_10
CLBLM_R.SLICEL_X1.AOUTMUX.F7 origin:016-clb-noutmux !31_07 !31_09 30_05 31_10
CLBLM_R.SLICEL_X1.AOUTMUX.O5 origin:016-clb-noutmux !30_05 !31_07 31_09 31_10
CLBLM_R.SLICEL_X1.AOUTMUX.O6 origin:016-clb-noutmux !30_05 !31_07 !31_10 31_09
CLBLM_R.SLICEL_X1.AOUTMUX.XOR origin:016-clb-noutmux !30_05 !31_09 !31_10 31_07
CLBLM_R.SLICEL_X1.B5FF.ZINI origin:011-clb-ffconfig 31_23
CLBLM_R.SLICEL_X1.B5FF.ZRST origin:011-clb-ffconfig 00_16
CLBLM_R.SLICEL_X1.B5FFMUX.IN_A origin:012-clb-n5ffmux 31_19
CLBLM_R.SLICEL_X1.B5FFMUX.IN_B origin:012-clb-n5ffmux 31_18
CLBLM_R.SLICEL_X1.BFF.ZINI origin:011-clb-ffconfig 31_29
CLBLM_R.SLICEL_X1.BFF.ZRST origin:011-clb-ffconfig 31_30
CLBLM_R.SLICEL_X1.BFFMUX.BX origin:015-clb-nffmux !31_24 !31_25 !31_26 31_27
CLBLM_R.SLICEL_X1.BFFMUX.CY origin:015-clb-nffmux !31_24 !31_27 31_25 31_26
CLBLM_R.SLICEL_X1.BFFMUX.F8 origin:015-clb-nffmux !31_24 !31_26 31_25 31_27
CLBLM_R.SLICEL_X1.BFFMUX.O5 origin:015-clb-nffmux !31_26 !31_27 31_24 31_25
CLBLM_R.SLICEL_X1.BFFMUX.O6 origin:015-clb-nffmux !31_25 !31_26 !31_27 31_24
CLBLM_R.SLICEL_X1.BFFMUX.XOR origin:015-clb-nffmux !31_24 !31_25 !31_27 31_26
CLBLM_R.SLICEL_X1.BLUT.INIT[00] origin:010-clb-lutinit 26_31
CLBLM_R.SLICEL_X1.BLUT.INIT[01] origin:010-clb-lutinit 27_31
CLBLM_R.SLICEL_X1.BLUT.INIT[02] origin:010-clb-lutinit 26_30
CLBLM_R.SLICEL_X1.BLUT.INIT[03] origin:010-clb-lutinit 27_30
CLBLM_R.SLICEL_X1.BLUT.INIT[04] origin:010-clb-lutinit 26_29
CLBLM_R.SLICEL_X1.BLUT.INIT[05] origin:010-clb-lutinit 27_29
CLBLM_R.SLICEL_X1.BLUT.INIT[06] origin:010-clb-lutinit 26_28
CLBLM_R.SLICEL_X1.BLUT.INIT[07] origin:010-clb-lutinit 27_28
CLBLM_R.SLICEL_X1.BLUT.INIT[08] origin:010-clb-lutinit 29_31
CLBLM_R.SLICEL_X1.BLUT.INIT[09] origin:010-clb-lutinit 28_31
CLBLM_R.SLICEL_X1.BLUT.INIT[10] origin:010-clb-lutinit 29_30
CLBLM_R.SLICEL_X1.BLUT.INIT[11] origin:010-clb-lutinit 28_30
CLBLM_R.SLICEL_X1.BLUT.INIT[12] origin:010-clb-lutinit 29_29
CLBLM_R.SLICEL_X1.BLUT.INIT[13] origin:010-clb-lutinit 28_29
CLBLM_R.SLICEL_X1.BLUT.INIT[14] origin:010-clb-lutinit 29_28
CLBLM_R.SLICEL_X1.BLUT.INIT[15] origin:010-clb-lutinit 28_28
CLBLM_R.SLICEL_X1.BLUT.INIT[16] origin:010-clb-lutinit 26_27
CLBLM_R.SLICEL_X1.BLUT.INIT[17] origin:010-clb-lutinit 27_27
CLBLM_R.SLICEL_X1.BLUT.INIT[18] origin:010-clb-lutinit 26_26
CLBLM_R.SLICEL_X1.BLUT.INIT[19] origin:010-clb-lutinit 27_26
CLBLM_R.SLICEL_X1.BLUT.INIT[20] origin:010-clb-lutinit 26_25
CLBLM_R.SLICEL_X1.BLUT.INIT[21] origin:010-clb-lutinit 27_25
CLBLM_R.SLICEL_X1.BLUT.INIT[22] origin:010-clb-lutinit 26_24
CLBLM_R.SLICEL_X1.BLUT.INIT[23] origin:010-clb-lutinit 27_24
CLBLM_R.SLICEL_X1.BLUT.INIT[24] origin:010-clb-lutinit 29_27
CLBLM_R.SLICEL_X1.BLUT.INIT[25] origin:010-clb-lutinit 28_27
CLBLM_R.SLICEL_X1.BLUT.INIT[26] origin:010-clb-lutinit 29_26
CLBLM_R.SLICEL_X1.BLUT.INIT[27] origin:010-clb-lutinit 28_26
CLBLM_R.SLICEL_X1.BLUT.INIT[28] origin:010-clb-lutinit 29_25
CLBLM_R.SLICEL_X1.BLUT.INIT[29] origin:010-clb-lutinit 28_25
CLBLM_R.SLICEL_X1.BLUT.INIT[30] origin:010-clb-lutinit 29_24
CLBLM_R.SLICEL_X1.BLUT.INIT[31] origin:010-clb-lutinit 28_24
CLBLM_R.SLICEL_X1.BLUT.INIT[32] origin:010-clb-lutinit 26_23
CLBLM_R.SLICEL_X1.BLUT.INIT[33] origin:010-clb-lutinit 27_23
CLBLM_R.SLICEL_X1.BLUT.INIT[34] origin:010-clb-lutinit 26_22
CLBLM_R.SLICEL_X1.BLUT.INIT[35] origin:010-clb-lutinit 27_22
CLBLM_R.SLICEL_X1.BLUT.INIT[36] origin:010-clb-lutinit 26_21
CLBLM_R.SLICEL_X1.BLUT.INIT[37] origin:010-clb-lutinit 27_21
CLBLM_R.SLICEL_X1.BLUT.INIT[38] origin:010-clb-lutinit 26_20
CLBLM_R.SLICEL_X1.BLUT.INIT[39] origin:010-clb-lutinit 27_20
CLBLM_R.SLICEL_X1.BLUT.INIT[40] origin:010-clb-lutinit 29_23
CLBLM_R.SLICEL_X1.BLUT.INIT[41] origin:010-clb-lutinit 28_23
CLBLM_R.SLICEL_X1.BLUT.INIT[42] origin:010-clb-lutinit 29_22
CLBLM_R.SLICEL_X1.BLUT.INIT[43] origin:010-clb-lutinit 28_22
CLBLM_R.SLICEL_X1.BLUT.INIT[44] origin:010-clb-lutinit 29_21
CLBLM_R.SLICEL_X1.BLUT.INIT[45] origin:010-clb-lutinit 28_21
CLBLM_R.SLICEL_X1.BLUT.INIT[46] origin:010-clb-lutinit 29_20
CLBLM_R.SLICEL_X1.BLUT.INIT[47] origin:010-clb-lutinit 28_20
CLBLM_R.SLICEL_X1.BLUT.INIT[48] origin:010-clb-lutinit 26_19
CLBLM_R.SLICEL_X1.BLUT.INIT[49] origin:010-clb-lutinit 27_19
CLBLM_R.SLICEL_X1.BLUT.INIT[50] origin:010-clb-lutinit 26_18
CLBLM_R.SLICEL_X1.BLUT.INIT[51] origin:010-clb-lutinit 27_18
CLBLM_R.SLICEL_X1.BLUT.INIT[52] origin:010-clb-lutinit 26_17
CLBLM_R.SLICEL_X1.BLUT.INIT[53] origin:010-clb-lutinit 27_17
CLBLM_R.SLICEL_X1.BLUT.INIT[54] origin:010-clb-lutinit 26_16
CLBLM_R.SLICEL_X1.BLUT.INIT[55] origin:010-clb-lutinit 27_16
CLBLM_R.SLICEL_X1.BLUT.INIT[56] origin:010-clb-lutinit 29_19
CLBLM_R.SLICEL_X1.BLUT.INIT[57] origin:010-clb-lutinit 28_19
CLBLM_R.SLICEL_X1.BLUT.INIT[58] origin:010-clb-lutinit 29_18
CLBLM_R.SLICEL_X1.BLUT.INIT[59] origin:010-clb-lutinit 28_18
CLBLM_R.SLICEL_X1.BLUT.INIT[60] origin:010-clb-lutinit 29_17
CLBLM_R.SLICEL_X1.BLUT.INIT[61] origin:010-clb-lutinit 28_17
CLBLM_R.SLICEL_X1.BLUT.INIT[62] origin:010-clb-lutinit 29_16
CLBLM_R.SLICEL_X1.BLUT.INIT[63] origin:010-clb-lutinit 28_16
CLBLM_R.SLICEL_X1.BOUTMUX.B5Q origin:016-clb-noutmux !30_28 !31_20 !31_21 30_29
CLBLM_R.SLICEL_X1.BOUTMUX.CY origin:016-clb-noutmux !30_29 !31_20 30_28 31_21
CLBLM_R.SLICEL_X1.BOUTMUX.F8 origin:016-clb-noutmux !30_28 !31_20 30_29 31_21
CLBLM_R.SLICEL_X1.BOUTMUX.O5 origin:016-clb-noutmux !30_28 !30_29 31_20 31_21
CLBLM_R.SLICEL_X1.BOUTMUX.O6 origin:016-clb-noutmux !30_28 !30_29 !31_21 31_20
CLBLM_R.SLICEL_X1.BOUTMUX.XOR origin:016-clb-noutmux !30_29 !31_20 !31_21 30_28
CLBLM_R.SLICEL_X1.C5FF.ZINI origin:011-clb-ffconfig 31_42
CLBLM_R.SLICEL_X1.C5FF.ZRST origin:011-clb-ffconfig 00_44
CLBLM_R.SLICEL_X1.C5FFMUX.IN_A origin:012-clb-n5ffmux 31_44
CLBLM_R.SLICEL_X1.C5FFMUX.IN_B origin:012-clb-n5ffmux 31_39
CLBLM_R.SLICEL_X1.CARRY4.ACY0 origin:013-clb-ncy0 31_14
CLBLM_R.SLICEL_X1.CARRY4.BCY0 origin:013-clb-ncy0 00_08
CLBLM_R.SLICEL_X1.CARRY4.CCY0 origin:013-clb-ncy0 31_48
CLBLM_R.SLICEL_X1.CARRY4.DCY0 origin:013-clb-ncy0 31_49
CLBLM_R.SLICEL_X1.CEUSEDMUX origin:014-clb-ffsrcemux 00_36
CLBLM_R.SLICEL_X1.CFF.ZINI origin:011-clb-ffconfig 31_34
CLBLM_R.SLICEL_X1.CFF.ZRST origin:011-clb-ffconfig 30_34
CLBLM_R.SLICEL_X1.CFFMUX.CX origin:015-clb-nffmux !31_35 !31_36 !31_37 31_38
CLBLM_R.SLICEL_X1.CFFMUX.CY origin:015-clb-nffmux !31_36 !31_38 31_35 31_37
CLBLM_R.SLICEL_X1.CFFMUX.F7 origin:015-clb-nffmux !31_36 !31_37 31_35 31_38
CLBLM_R.SLICEL_X1.CFFMUX.O5 origin:015-clb-nffmux !31_37 !31_38 31_35 31_36
CLBLM_R.SLICEL_X1.CFFMUX.O6 origin:015-clb-nffmux !31_35 !31_37 !31_38 31_36
CLBLM_R.SLICEL_X1.CFFMUX.XOR origin:015-clb-nffmux !31_35 !31_36 !31_38 31_37
CLBLM_R.SLICEL_X1.CLKINV origin:011-clb-ffconfig 00_52
CLBLM_R.SLICEL_X1.CLUT.INIT[00] origin:010-clb-lutinit 26_47
CLBLM_R.SLICEL_X1.CLUT.INIT[01] origin:010-clb-lutinit 27_47
CLBLM_R.SLICEL_X1.CLUT.INIT[02] origin:010-clb-lutinit 26_46
CLBLM_R.SLICEL_X1.CLUT.INIT[03] origin:010-clb-lutinit 27_46
CLBLM_R.SLICEL_X1.CLUT.INIT[04] origin:010-clb-lutinit 26_45
CLBLM_R.SLICEL_X1.CLUT.INIT[05] origin:010-clb-lutinit 27_45
CLBLM_R.SLICEL_X1.CLUT.INIT[06] origin:010-clb-lutinit 26_44
CLBLM_R.SLICEL_X1.CLUT.INIT[07] origin:010-clb-lutinit 27_44
CLBLM_R.SLICEL_X1.CLUT.INIT[08] origin:010-clb-lutinit 29_47
CLBLM_R.SLICEL_X1.CLUT.INIT[09] origin:010-clb-lutinit 28_47
CLBLM_R.SLICEL_X1.CLUT.INIT[10] origin:010-clb-lutinit 29_46
CLBLM_R.SLICEL_X1.CLUT.INIT[11] origin:010-clb-lutinit 28_46
CLBLM_R.SLICEL_X1.CLUT.INIT[12] origin:010-clb-lutinit 29_45
CLBLM_R.SLICEL_X1.CLUT.INIT[13] origin:010-clb-lutinit 28_45
CLBLM_R.SLICEL_X1.CLUT.INIT[14] origin:010-clb-lutinit 29_44
CLBLM_R.SLICEL_X1.CLUT.INIT[15] origin:010-clb-lutinit 28_44
CLBLM_R.SLICEL_X1.CLUT.INIT[16] origin:010-clb-lutinit 26_43
CLBLM_R.SLICEL_X1.CLUT.INIT[17] origin:010-clb-lutinit 27_43
CLBLM_R.SLICEL_X1.CLUT.INIT[18] origin:010-clb-lutinit 26_42
CLBLM_R.SLICEL_X1.CLUT.INIT[19] origin:010-clb-lutinit 27_42
CLBLM_R.SLICEL_X1.CLUT.INIT[20] origin:010-clb-lutinit 26_41
CLBLM_R.SLICEL_X1.CLUT.INIT[21] origin:010-clb-lutinit 27_41
CLBLM_R.SLICEL_X1.CLUT.INIT[22] origin:010-clb-lutinit 26_40
CLBLM_R.SLICEL_X1.CLUT.INIT[23] origin:010-clb-lutinit 27_40
CLBLM_R.SLICEL_X1.CLUT.INIT[24] origin:010-clb-lutinit 29_43
CLBLM_R.SLICEL_X1.CLUT.INIT[25] origin:010-clb-lutinit 28_43
CLBLM_R.SLICEL_X1.CLUT.INIT[26] origin:010-clb-lutinit 29_42
CLBLM_R.SLICEL_X1.CLUT.INIT[27] origin:010-clb-lutinit 28_42
CLBLM_R.SLICEL_X1.CLUT.INIT[28] origin:010-clb-lutinit 29_41
CLBLM_R.SLICEL_X1.CLUT.INIT[29] origin:010-clb-lutinit 28_41
CLBLM_R.SLICEL_X1.CLUT.INIT[30] origin:010-clb-lutinit 29_40
CLBLM_R.SLICEL_X1.CLUT.INIT[31] origin:010-clb-lutinit 28_40
CLBLM_R.SLICEL_X1.CLUT.INIT[32] origin:010-clb-lutinit 26_39
CLBLM_R.SLICEL_X1.CLUT.INIT[33] origin:010-clb-lutinit 27_39
CLBLM_R.SLICEL_X1.CLUT.INIT[34] origin:010-clb-lutinit 26_38
CLBLM_R.SLICEL_X1.CLUT.INIT[35] origin:010-clb-lutinit 27_38
CLBLM_R.SLICEL_X1.CLUT.INIT[36] origin:010-clb-lutinit 26_37
CLBLM_R.SLICEL_X1.CLUT.INIT[37] origin:010-clb-lutinit 27_37
CLBLM_R.SLICEL_X1.CLUT.INIT[38] origin:010-clb-lutinit 26_36
CLBLM_R.SLICEL_X1.CLUT.INIT[39] origin:010-clb-lutinit 27_36
CLBLM_R.SLICEL_X1.CLUT.INIT[40] origin:010-clb-lutinit 29_39
CLBLM_R.SLICEL_X1.CLUT.INIT[41] origin:010-clb-lutinit 28_39
CLBLM_R.SLICEL_X1.CLUT.INIT[42] origin:010-clb-lutinit 29_38
CLBLM_R.SLICEL_X1.CLUT.INIT[43] origin:010-clb-lutinit 28_38
CLBLM_R.SLICEL_X1.CLUT.INIT[44] origin:010-clb-lutinit 29_37
CLBLM_R.SLICEL_X1.CLUT.INIT[45] origin:010-clb-lutinit 28_37
CLBLM_R.SLICEL_X1.CLUT.INIT[46] origin:010-clb-lutinit 29_36
CLBLM_R.SLICEL_X1.CLUT.INIT[47] origin:010-clb-lutinit 28_36
CLBLM_R.SLICEL_X1.CLUT.INIT[48] origin:010-clb-lutinit 26_35
CLBLM_R.SLICEL_X1.CLUT.INIT[49] origin:010-clb-lutinit 27_35
CLBLM_R.SLICEL_X1.CLUT.INIT[50] origin:010-clb-lutinit 26_34
CLBLM_R.SLICEL_X1.CLUT.INIT[51] origin:010-clb-lutinit 27_34
CLBLM_R.SLICEL_X1.CLUT.INIT[52] origin:010-clb-lutinit 26_33
CLBLM_R.SLICEL_X1.CLUT.INIT[53] origin:010-clb-lutinit 27_33
CLBLM_R.SLICEL_X1.CLUT.INIT[54] origin:010-clb-lutinit 26_32
CLBLM_R.SLICEL_X1.CLUT.INIT[55] origin:010-clb-lutinit 27_32
CLBLM_R.SLICEL_X1.CLUT.INIT[56] origin:010-clb-lutinit 29_35
CLBLM_R.SLICEL_X1.CLUT.INIT[57] origin:010-clb-lutinit 28_35
CLBLM_R.SLICEL_X1.CLUT.INIT[58] origin:010-clb-lutinit 29_34
CLBLM_R.SLICEL_X1.CLUT.INIT[59] origin:010-clb-lutinit 28_34
CLBLM_R.SLICEL_X1.CLUT.INIT[60] origin:010-clb-lutinit 29_33
CLBLM_R.SLICEL_X1.CLUT.INIT[61] origin:010-clb-lutinit 28_33
CLBLM_R.SLICEL_X1.CLUT.INIT[62] origin:010-clb-lutinit 29_32
CLBLM_R.SLICEL_X1.CLUT.INIT[63] origin:010-clb-lutinit 28_32
CLBLM_R.SLICEL_X1.COUTMUX.C5Q origin:016-clb-noutmux !30_42 !31_40 !31_43 30_41
CLBLM_R.SLICEL_X1.COUTMUX.CY origin:016-clb-noutmux !30_41 !31_43 30_42 31_40
CLBLM_R.SLICEL_X1.COUTMUX.F7 origin:016-clb-noutmux !30_42 !31_43 30_41 31_40
CLBLM_R.SLICEL_X1.COUTMUX.O5 origin:016-clb-noutmux !30_41 !30_42 31_40 31_43
CLBLM_R.SLICEL_X1.COUTMUX.O6 origin:016-clb-noutmux !30_41 !30_42 !31_40 31_43
CLBLM_R.SLICEL_X1.COUTMUX.XOR origin:016-clb-noutmux !30_41 !31_40 !31_43 30_42
CLBLM_R.SLICEL_X1.D5FF.ZINI origin:011-clb-ffconfig 31_52
CLBLM_R.SLICEL_X1.D5FF.ZRST origin:011-clb-ffconfig 00_56
CLBLM_R.SLICEL_X1.D5FFMUX.IN_A origin:012-clb-n5ffmux 31_55
CLBLM_R.SLICEL_X1.D5FFMUX.IN_B origin:012-clb-n5ffmux 31_54
CLBLM_R.SLICEL_X1.DFF.ZINI origin:011-clb-ffconfig 31_59
CLBLM_R.SLICEL_X1.DFF.ZRST origin:011-clb-ffconfig 31_50
CLBLM_R.SLICEL_X1.DFFMUX.CY origin:015-clb-nffmux !31_60 !31_61 30_58 31_62
CLBLM_R.SLICEL_X1.DFFMUX.DX origin:015-clb-nffmux !30_58 !31_60 !31_62 31_61
CLBLM_R.SLICEL_X1.DFFMUX.O5 origin:015-clb-nffmux !31_61 !31_62 30_58 31_60
CLBLM_R.SLICEL_X1.DFFMUX.O6 origin:015-clb-nffmux !30_58 !31_61 !31_62 31_60
CLBLM_R.SLICEL_X1.DFFMUX.XOR origin:015-clb-nffmux !30_58 !31_60 !31_61 31_62
CLBLM_R.SLICEL_X1.DLUT.INIT[00] origin:010-clb-lutinit 26_63
CLBLM_R.SLICEL_X1.DLUT.INIT[01] origin:010-clb-lutinit 27_63
CLBLM_R.SLICEL_X1.DLUT.INIT[02] origin:010-clb-lutinit 26_62
CLBLM_R.SLICEL_X1.DLUT.INIT[03] origin:010-clb-lutinit 27_62
CLBLM_R.SLICEL_X1.DLUT.INIT[04] origin:010-clb-lutinit 26_61
CLBLM_R.SLICEL_X1.DLUT.INIT[05] origin:010-clb-lutinit 27_61
CLBLM_R.SLICEL_X1.DLUT.INIT[06] origin:010-clb-lutinit 26_60
CLBLM_R.SLICEL_X1.DLUT.INIT[07] origin:010-clb-lutinit 27_60
CLBLM_R.SLICEL_X1.DLUT.INIT[08] origin:010-clb-lutinit 29_63
CLBLM_R.SLICEL_X1.DLUT.INIT[09] origin:010-clb-lutinit 28_63
CLBLM_R.SLICEL_X1.DLUT.INIT[10] origin:010-clb-lutinit 29_62
CLBLM_R.SLICEL_X1.DLUT.INIT[11] origin:010-clb-lutinit 28_62
CLBLM_R.SLICEL_X1.DLUT.INIT[12] origin:010-clb-lutinit 29_61
CLBLM_R.SLICEL_X1.DLUT.INIT[13] origin:010-clb-lutinit 28_61
CLBLM_R.SLICEL_X1.DLUT.INIT[14] origin:010-clb-lutinit 29_60
CLBLM_R.SLICEL_X1.DLUT.INIT[15] origin:010-clb-lutinit 28_60
CLBLM_R.SLICEL_X1.DLUT.INIT[16] origin:010-clb-lutinit 26_59
CLBLM_R.SLICEL_X1.DLUT.INIT[17] origin:010-clb-lutinit 27_59
CLBLM_R.SLICEL_X1.DLUT.INIT[18] origin:010-clb-lutinit 26_58
CLBLM_R.SLICEL_X1.DLUT.INIT[19] origin:010-clb-lutinit 27_58
CLBLM_R.SLICEL_X1.DLUT.INIT[20] origin:010-clb-lutinit 26_57
CLBLM_R.SLICEL_X1.DLUT.INIT[21] origin:010-clb-lutinit 27_57
CLBLM_R.SLICEL_X1.DLUT.INIT[22] origin:010-clb-lutinit 26_56
CLBLM_R.SLICEL_X1.DLUT.INIT[23] origin:010-clb-lutinit 27_56
CLBLM_R.SLICEL_X1.DLUT.INIT[24] origin:010-clb-lutinit 29_59
CLBLM_R.SLICEL_X1.DLUT.INIT[25] origin:010-clb-lutinit 28_59
CLBLM_R.SLICEL_X1.DLUT.INIT[26] origin:010-clb-lutinit 29_58
CLBLM_R.SLICEL_X1.DLUT.INIT[27] origin:010-clb-lutinit 28_58
CLBLM_R.SLICEL_X1.DLUT.INIT[28] origin:010-clb-lutinit 29_57
CLBLM_R.SLICEL_X1.DLUT.INIT[29] origin:010-clb-lutinit 28_57
CLBLM_R.SLICEL_X1.DLUT.INIT[30] origin:010-clb-lutinit 29_56
CLBLM_R.SLICEL_X1.DLUT.INIT[31] origin:010-clb-lutinit 28_56
CLBLM_R.SLICEL_X1.DLUT.INIT[32] origin:010-clb-lutinit 26_55
CLBLM_R.SLICEL_X1.DLUT.INIT[33] origin:010-clb-lutinit 27_55
CLBLM_R.SLICEL_X1.DLUT.INIT[34] origin:010-clb-lutinit 26_54
CLBLM_R.SLICEL_X1.DLUT.INIT[35] origin:010-clb-lutinit 27_54
CLBLM_R.SLICEL_X1.DLUT.INIT[36] origin:010-clb-lutinit 26_53
CLBLM_R.SLICEL_X1.DLUT.INIT[37] origin:010-clb-lutinit 27_53
CLBLM_R.SLICEL_X1.DLUT.INIT[38] origin:010-clb-lutinit 26_52
CLBLM_R.SLICEL_X1.DLUT.INIT[39] origin:010-clb-lutinit 27_52
CLBLM_R.SLICEL_X1.DLUT.INIT[40] origin:010-clb-lutinit 29_55
CLBLM_R.SLICEL_X1.DLUT.INIT[41] origin:010-clb-lutinit 28_55
CLBLM_R.SLICEL_X1.DLUT.INIT[42] origin:010-clb-lutinit 29_54
CLBLM_R.SLICEL_X1.DLUT.INIT[43] origin:010-clb-lutinit 28_54
CLBLM_R.SLICEL_X1.DLUT.INIT[44] origin:010-clb-lutinit 29_53
CLBLM_R.SLICEL_X1.DLUT.INIT[45] origin:010-clb-lutinit 28_53
CLBLM_R.SLICEL_X1.DLUT.INIT[46] origin:010-clb-lutinit 29_52
CLBLM_R.SLICEL_X1.DLUT.INIT[47] origin:010-clb-lutinit 28_52
CLBLM_R.SLICEL_X1.DLUT.INIT[48] origin:010-clb-lutinit 26_51
CLBLM_R.SLICEL_X1.DLUT.INIT[49] origin:010-clb-lutinit 27_51
CLBLM_R.SLICEL_X1.DLUT.INIT[50] origin:010-clb-lutinit 26_50
CLBLM_R.SLICEL_X1.DLUT.INIT[51] origin:010-clb-lutinit 27_50
CLBLM_R.SLICEL_X1.DLUT.INIT[52] origin:010-clb-lutinit 26_49
CLBLM_R.SLICEL_X1.DLUT.INIT[53] origin:010-clb-lutinit 27_49
CLBLM_R.SLICEL_X1.DLUT.INIT[54] origin:010-clb-lutinit 26_48
CLBLM_R.SLICEL_X1.DLUT.INIT[55] origin:010-clb-lutinit 27_48
CLBLM_R.SLICEL_X1.DLUT.INIT[56] origin:010-clb-lutinit 29_51
CLBLM_R.SLICEL_X1.DLUT.INIT[57] origin:010-clb-lutinit 28_51
CLBLM_R.SLICEL_X1.DLUT.INIT[58] origin:010-clb-lutinit 29_50
CLBLM_R.SLICEL_X1.DLUT.INIT[59] origin:010-clb-lutinit 28_50
CLBLM_R.SLICEL_X1.DLUT.INIT[60] origin:010-clb-lutinit 29_49
CLBLM_R.SLICEL_X1.DLUT.INIT[61] origin:010-clb-lutinit 28_49
CLBLM_R.SLICEL_X1.DLUT.INIT[62] origin:010-clb-lutinit 29_48
CLBLM_R.SLICEL_X1.DLUT.INIT[63] origin:010-clb-lutinit 28_48
CLBLM_R.SLICEL_X1.DOUTMUX.CY origin:016-clb-noutmux !31_53 !31_56 30_53 31_57
CLBLM_R.SLICEL_X1.DOUTMUX.D5Q origin:016-clb-noutmux !30_53 !31_56 !31_57 31_53
CLBLM_R.SLICEL_X1.DOUTMUX.O5 origin:016-clb-noutmux !30_53 !31_53 31_56 31_57
CLBLM_R.SLICEL_X1.DOUTMUX.O6 origin:016-clb-noutmux !30_53 !31_53 !31_57 31_56
CLBLM_R.SLICEL_X1.DOUTMUX.XOR origin:016-clb-noutmux !31_53 !31_56 !31_57 30_53
CLBLM_R.SLICEL_X1.FFSYNC origin:011-clb-ffconfig 01_31
CLBLM_R.SLICEL_X1.LATCH origin:011-clb-ffconfig 31_32
CLBLM_R.SLICEL_X1.PRECYINIT.AX origin:017-clb-precyinit !01_11 !31_12 31_13
CLBLM_R.SLICEL_X1.PRECYINIT.C0 origin:017-clb-precyinit !01_11 !31_12 !31_13
CLBLM_R.SLICEL_X1.PRECYINIT.C1 origin:017-clb-precyinit !31_12 !31_13 01_11
CLBLM_R.SLICEL_X1.PRECYINIT.CIN origin:017-clb-precyinit !01_11 !31_13 31_12
CLBLM_R.SLICEL_X1.SRUSEDMUX origin:014-clb-ffsrcemux 00_32
CLBLM_R.SLICEM_X0.A5FF.ZINI origin:011-clb-ffconfig 31_06
CLBLM_R.SLICEM_X0.A5FF.ZRST origin:011-clb-ffconfig 01_07
CLBLM_R.SLICEM_X0.A5FFMUX.IN_A origin:012-clb-n5ffmux 30_09
CLBLM_R.SLICEM_X0.A5FFMUX.IN_B origin:012-clb-n5ffmux 30_10
CLBLM_R.SLICEM_X0.AFF.ZINI origin:011-clb-ffconfig 31_03
CLBLM_R.SLICEM_X0.AFF.ZRST origin:011-clb-ffconfig 30_12
CLBLM_R.SLICEM_X0.AFFMUX.AX origin:015-clb-nffmux !30_00 !30_02 !30_03 30_01
CLBLM_R.SLICEM_X0.AFFMUX.CY origin:015-clb-nffmux !30_01 !30_03 30_00 30_02
CLBLM_R.SLICEM_X0.AFFMUX.F7 origin:015-clb-nffmux !30_02 !30_03 30_00 30_01
CLBLM_R.SLICEM_X0.AFFMUX.O5 origin:015-clb-nffmux !30_01 !30_02 30_00 30_03
CLBLM_R.SLICEM_X0.AFFMUX.O6 origin:015-clb-nffmux !30_00 !30_01 !30_02 30_03
CLBLM_R.SLICEM_X0.AFFMUX.XOR origin:015-clb-nffmux !30_00 !30_01 !30_03 30_02
CLBLM_R.SLICEM_X0.ALUT.DI1MUX.AI origin:019-clb-ndi1mux 00_00
CLBLM_R.SLICEM_X0.ALUT.INIT[00] origin:010-clb-lutinit 34_15
CLBLM_R.SLICEM_X0.ALUT.INIT[01] origin:010-clb-lutinit 35_15
CLBLM_R.SLICEM_X0.ALUT.INIT[02] origin:010-clb-lutinit 34_14
CLBLM_R.SLICEM_X0.ALUT.INIT[03] origin:010-clb-lutinit 35_14
CLBLM_R.SLICEM_X0.ALUT.INIT[04] origin:010-clb-lutinit 34_13
CLBLM_R.SLICEM_X0.ALUT.INIT[05] origin:010-clb-lutinit 35_13
CLBLM_R.SLICEM_X0.ALUT.INIT[06] origin:010-clb-lutinit 34_12
CLBLM_R.SLICEM_X0.ALUT.INIT[07] origin:010-clb-lutinit 35_12
CLBLM_R.SLICEM_X0.ALUT.INIT[08] origin:010-clb-lutinit 32_15
CLBLM_R.SLICEM_X0.ALUT.INIT[09] origin:010-clb-lutinit 33_15
CLBLM_R.SLICEM_X0.ALUT.INIT[10] origin:010-clb-lutinit 32_14
CLBLM_R.SLICEM_X0.ALUT.INIT[11] origin:010-clb-lutinit 33_14
CLBLM_R.SLICEM_X0.ALUT.INIT[12] origin:010-clb-lutinit 32_13
CLBLM_R.SLICEM_X0.ALUT.INIT[13] origin:010-clb-lutinit 33_13
CLBLM_R.SLICEM_X0.ALUT.INIT[14] origin:010-clb-lutinit 32_12
CLBLM_R.SLICEM_X0.ALUT.INIT[15] origin:010-clb-lutinit 33_12
CLBLM_R.SLICEM_X0.ALUT.INIT[16] origin:010-clb-lutinit 34_11
CLBLM_R.SLICEM_X0.ALUT.INIT[17] origin:010-clb-lutinit 35_11
CLBLM_R.SLICEM_X0.ALUT.INIT[18] origin:010-clb-lutinit 34_10
CLBLM_R.SLICEM_X0.ALUT.INIT[19] origin:010-clb-lutinit 35_10
CLBLM_R.SLICEM_X0.ALUT.INIT[20] origin:010-clb-lutinit 34_09
CLBLM_R.SLICEM_X0.ALUT.INIT[21] origin:010-clb-lutinit 35_09
CLBLM_R.SLICEM_X0.ALUT.INIT[22] origin:010-clb-lutinit 34_08
CLBLM_R.SLICEM_X0.ALUT.INIT[23] origin:010-clb-lutinit 35_08
CLBLM_R.SLICEM_X0.ALUT.INIT[24] origin:010-clb-lutinit 32_11
CLBLM_R.SLICEM_X0.ALUT.INIT[25] origin:010-clb-lutinit 33_11
CLBLM_R.SLICEM_X0.ALUT.INIT[26] origin:010-clb-lutinit 32_10
CLBLM_R.SLICEM_X0.ALUT.INIT[27] origin:010-clb-lutinit 33_10
CLBLM_R.SLICEM_X0.ALUT.INIT[28] origin:010-clb-lutinit 32_09
CLBLM_R.SLICEM_X0.ALUT.INIT[29] origin:010-clb-lutinit 33_09
CLBLM_R.SLICEM_X0.ALUT.INIT[30] origin:010-clb-lutinit 32_08
CLBLM_R.SLICEM_X0.ALUT.INIT[31] origin:010-clb-lutinit 33_08
CLBLM_R.SLICEM_X0.ALUT.INIT[32] origin:010-clb-lutinit 34_07
CLBLM_R.SLICEM_X0.ALUT.INIT[33] origin:010-clb-lutinit 35_07
CLBLM_R.SLICEM_X0.ALUT.INIT[34] origin:010-clb-lutinit 34_06
CLBLM_R.SLICEM_X0.ALUT.INIT[35] origin:010-clb-lutinit 35_06
CLBLM_R.SLICEM_X0.ALUT.INIT[36] origin:010-clb-lutinit 34_05
CLBLM_R.SLICEM_X0.ALUT.INIT[37] origin:010-clb-lutinit 35_05
CLBLM_R.SLICEM_X0.ALUT.INIT[38] origin:010-clb-lutinit 34_04
CLBLM_R.SLICEM_X0.ALUT.INIT[39] origin:010-clb-lutinit 35_04
CLBLM_R.SLICEM_X0.ALUT.INIT[40] origin:010-clb-lutinit 32_07
CLBLM_R.SLICEM_X0.ALUT.INIT[41] origin:010-clb-lutinit 33_07
CLBLM_R.SLICEM_X0.ALUT.INIT[42] origin:010-clb-lutinit 32_06
CLBLM_R.SLICEM_X0.ALUT.INIT[43] origin:010-clb-lutinit 33_06
CLBLM_R.SLICEM_X0.ALUT.INIT[44] origin:010-clb-lutinit 32_05
CLBLM_R.SLICEM_X0.ALUT.INIT[45] origin:010-clb-lutinit 33_05
CLBLM_R.SLICEM_X0.ALUT.INIT[46] origin:010-clb-lutinit 32_04
CLBLM_R.SLICEM_X0.ALUT.INIT[47] origin:010-clb-lutinit 33_04
CLBLM_R.SLICEM_X0.ALUT.INIT[48] origin:010-clb-lutinit 34_03
CLBLM_R.SLICEM_X0.ALUT.INIT[49] origin:010-clb-lutinit 35_03
CLBLM_R.SLICEM_X0.ALUT.INIT[50] origin:010-clb-lutinit 34_02
CLBLM_R.SLICEM_X0.ALUT.INIT[51] origin:010-clb-lutinit 35_02
CLBLM_R.SLICEM_X0.ALUT.INIT[52] origin:010-clb-lutinit 34_01
CLBLM_R.SLICEM_X0.ALUT.INIT[53] origin:010-clb-lutinit 35_01
CLBLM_R.SLICEM_X0.ALUT.INIT[54] origin:010-clb-lutinit 34_00
CLBLM_R.SLICEM_X0.ALUT.INIT[55] origin:010-clb-lutinit 35_00
CLBLM_R.SLICEM_X0.ALUT.INIT[56] origin:010-clb-lutinit 32_03
CLBLM_R.SLICEM_X0.ALUT.INIT[57] origin:010-clb-lutinit 33_03
CLBLM_R.SLICEM_X0.ALUT.INIT[58] origin:010-clb-lutinit 32_02
CLBLM_R.SLICEM_X0.ALUT.INIT[59] origin:010-clb-lutinit 33_02
CLBLM_R.SLICEM_X0.ALUT.INIT[60] origin:010-clb-lutinit 32_01
CLBLM_R.SLICEM_X0.ALUT.INIT[61] origin:010-clb-lutinit 33_01
CLBLM_R.SLICEM_X0.ALUT.INIT[62] origin:010-clb-lutinit 32_00
CLBLM_R.SLICEM_X0.ALUT.INIT[63] origin:010-clb-lutinit 33_00
CLBLM_R.SLICEM_X0.ALUT.RAM origin:018-clb-ram 31_16
CLBLM_R.SLICEM_X0.ALUT.SMALL origin:018-clb-ram 00_04
CLBLM_R.SLICEM_X0.ALUT.SRL origin:018-clb-ram 30_16
CLBLM_R.SLICEM_X0.AOUTMUX.A5Q origin:016-clb-noutmux !30_06 !30_08 !30_11 30_07
CLBLM_R.SLICEM_X0.AOUTMUX.CY origin:016-clb-noutmux !30_07 !30_11 30_06 30_08
CLBLM_R.SLICEM_X0.AOUTMUX.F7 origin:016-clb-noutmux !30_08 !30_11 30_06 30_07
CLBLM_R.SLICEM_X0.AOUTMUX.O5 origin:016-clb-noutmux !30_07 !30_08 30_06 30_11
CLBLM_R.SLICEM_X0.AOUTMUX.O6 origin:016-clb-noutmux !30_06 !30_07 !30_08 30_11
CLBLM_R.SLICEM_X0.AOUTMUX.XOR origin:016-clb-noutmux !30_06 !30_07 !30_11 30_08
CLBLM_R.SLICEM_X0.B5FF.ZINI origin:011-clb-ffconfig 31_22
CLBLM_R.SLICEM_X0.B5FF.ZRST origin:011-clb-ffconfig 01_19
CLBLM_R.SLICEM_X0.B5FFMUX.IN_A origin:012-clb-n5ffmux 30_19
CLBLM_R.SLICEM_X0.B5FFMUX.IN_B origin:012-clb-n5ffmux 30_18
CLBLM_R.SLICEM_X0.BFF.ZINI origin:011-clb-ffconfig 31_28
CLBLM_R.SLICEM_X0.BFF.ZRST origin:011-clb-ffconfig 30_30
CLBLM_R.SLICEM_X0.BFFMUX.BX origin:015-clb-nffmux !30_24 !30_25 !30_27 30_26
CLBLM_R.SLICEM_X0.BFFMUX.CY origin:015-clb-nffmux !30_24 !30_26 30_25 30_27
CLBLM_R.SLICEM_X0.BFFMUX.F8 origin:015-clb-nffmux !30_24 !30_25 30_26 30_27
CLBLM_R.SLICEM_X0.BFFMUX.O5 origin:015-clb-nffmux !30_25 !30_26 30_24 30_27
CLBLM_R.SLICEM_X0.BFFMUX.O6 origin:015-clb-nffmux !30_25 !30_26 !30_27 30_24
CLBLM_R.SLICEM_X0.BFFMUX.XOR origin:015-clb-nffmux !30_24 !30_26 !30_27 30_25
CLBLM_R.SLICEM_X0.BLUT.DI1MUX.BI origin:019-clb-ndi1mux 00_20
CLBLM_R.SLICEM_X0.BLUT.INIT[00] origin:010-clb-lutinit 34_31
CLBLM_R.SLICEM_X0.BLUT.INIT[01] origin:010-clb-lutinit 35_31
CLBLM_R.SLICEM_X0.BLUT.INIT[02] origin:010-clb-lutinit 34_30
CLBLM_R.SLICEM_X0.BLUT.INIT[03] origin:010-clb-lutinit 35_30
CLBLM_R.SLICEM_X0.BLUT.INIT[04] origin:010-clb-lutinit 34_29
CLBLM_R.SLICEM_X0.BLUT.INIT[05] origin:010-clb-lutinit 35_29
CLBLM_R.SLICEM_X0.BLUT.INIT[06] origin:010-clb-lutinit 34_28
CLBLM_R.SLICEM_X0.BLUT.INIT[07] origin:010-clb-lutinit 35_28
CLBLM_R.SLICEM_X0.BLUT.INIT[08] origin:010-clb-lutinit 32_31
CLBLM_R.SLICEM_X0.BLUT.INIT[09] origin:010-clb-lutinit 33_31
CLBLM_R.SLICEM_X0.BLUT.INIT[10] origin:010-clb-lutinit 32_30
CLBLM_R.SLICEM_X0.BLUT.INIT[11] origin:010-clb-lutinit 33_30
CLBLM_R.SLICEM_X0.BLUT.INIT[12] origin:010-clb-lutinit 32_29
CLBLM_R.SLICEM_X0.BLUT.INIT[13] origin:010-clb-lutinit 33_29
CLBLM_R.SLICEM_X0.BLUT.INIT[14] origin:010-clb-lutinit 32_28
CLBLM_R.SLICEM_X0.BLUT.INIT[15] origin:010-clb-lutinit 33_28
CLBLM_R.SLICEM_X0.BLUT.INIT[16] origin:010-clb-lutinit 34_27
CLBLM_R.SLICEM_X0.BLUT.INIT[17] origin:010-clb-lutinit 35_27
CLBLM_R.SLICEM_X0.BLUT.INIT[18] origin:010-clb-lutinit 34_26
CLBLM_R.SLICEM_X0.BLUT.INIT[19] origin:010-clb-lutinit 35_26
CLBLM_R.SLICEM_X0.BLUT.INIT[20] origin:010-clb-lutinit 34_25
CLBLM_R.SLICEM_X0.BLUT.INIT[21] origin:010-clb-lutinit 35_25
CLBLM_R.SLICEM_X0.BLUT.INIT[22] origin:010-clb-lutinit 34_24
CLBLM_R.SLICEM_X0.BLUT.INIT[23] origin:010-clb-lutinit 35_24
CLBLM_R.SLICEM_X0.BLUT.INIT[24] origin:010-clb-lutinit 32_27
CLBLM_R.SLICEM_X0.BLUT.INIT[25] origin:010-clb-lutinit 33_27
CLBLM_R.SLICEM_X0.BLUT.INIT[26] origin:010-clb-lutinit 32_26
CLBLM_R.SLICEM_X0.BLUT.INIT[27] origin:010-clb-lutinit 33_26
CLBLM_R.SLICEM_X0.BLUT.INIT[28] origin:010-clb-lutinit 32_25
CLBLM_R.SLICEM_X0.BLUT.INIT[29] origin:010-clb-lutinit 33_25
CLBLM_R.SLICEM_X0.BLUT.INIT[30] origin:010-clb-lutinit 32_24
CLBLM_R.SLICEM_X0.BLUT.INIT[31] origin:010-clb-lutinit 33_24
CLBLM_R.SLICEM_X0.BLUT.INIT[32] origin:010-clb-lutinit 34_23
CLBLM_R.SLICEM_X0.BLUT.INIT[33] origin:010-clb-lutinit 35_23
CLBLM_R.SLICEM_X0.BLUT.INIT[34] origin:010-clb-lutinit 34_22
CLBLM_R.SLICEM_X0.BLUT.INIT[35] origin:010-clb-lutinit 35_22
CLBLM_R.SLICEM_X0.BLUT.INIT[36] origin:010-clb-lutinit 34_21
CLBLM_R.SLICEM_X0.BLUT.INIT[37] origin:010-clb-lutinit 35_21
CLBLM_R.SLICEM_X0.BLUT.INIT[38] origin:010-clb-lutinit 34_20
CLBLM_R.SLICEM_X0.BLUT.INIT[39] origin:010-clb-lutinit 35_20
CLBLM_R.SLICEM_X0.BLUT.INIT[40] origin:010-clb-lutinit 32_23
CLBLM_R.SLICEM_X0.BLUT.INIT[41] origin:010-clb-lutinit 33_23
CLBLM_R.SLICEM_X0.BLUT.INIT[42] origin:010-clb-lutinit 32_22
CLBLM_R.SLICEM_X0.BLUT.INIT[43] origin:010-clb-lutinit 33_22
CLBLM_R.SLICEM_X0.BLUT.INIT[44] origin:010-clb-lutinit 32_21
CLBLM_R.SLICEM_X0.BLUT.INIT[45] origin:010-clb-lutinit 33_21
CLBLM_R.SLICEM_X0.BLUT.INIT[46] origin:010-clb-lutinit 32_20
CLBLM_R.SLICEM_X0.BLUT.INIT[47] origin:010-clb-lutinit 33_20
CLBLM_R.SLICEM_X0.BLUT.INIT[48] origin:010-clb-lutinit 34_19
CLBLM_R.SLICEM_X0.BLUT.INIT[49] origin:010-clb-lutinit 35_19
CLBLM_R.SLICEM_X0.BLUT.INIT[50] origin:010-clb-lutinit 34_18
CLBLM_R.SLICEM_X0.BLUT.INIT[51] origin:010-clb-lutinit 35_18
CLBLM_R.SLICEM_X0.BLUT.INIT[52] origin:010-clb-lutinit 34_17
CLBLM_R.SLICEM_X0.BLUT.INIT[53] origin:010-clb-lutinit 35_17
CLBLM_R.SLICEM_X0.BLUT.INIT[54] origin:010-clb-lutinit 34_16
CLBLM_R.SLICEM_X0.BLUT.INIT[55] origin:010-clb-lutinit 35_16
CLBLM_R.SLICEM_X0.BLUT.INIT[56] origin:010-clb-lutinit 32_19
CLBLM_R.SLICEM_X0.BLUT.INIT[57] origin:010-clb-lutinit 33_19
CLBLM_R.SLICEM_X0.BLUT.INIT[58] origin:010-clb-lutinit 32_18
CLBLM_R.SLICEM_X0.BLUT.INIT[59] origin:010-clb-lutinit 33_18
CLBLM_R.SLICEM_X0.BLUT.INIT[60] origin:010-clb-lutinit 32_17
CLBLM_R.SLICEM_X0.BLUT.INIT[61] origin:010-clb-lutinit 33_17
CLBLM_R.SLICEM_X0.BLUT.INIT[62] origin:010-clb-lutinit 32_16
CLBLM_R.SLICEM_X0.BLUT.INIT[63] origin:010-clb-lutinit 33_16
CLBLM_R.SLICEM_X0.BLUT.RAM origin:018-clb-ram 31_17
CLBLM_R.SLICEM_X0.BLUT.SMALL origin:018-clb-ram 00_24
CLBLM_R.SLICEM_X0.BLUT.SRL origin:018-clb-ram 30_17
CLBLM_R.SLICEM_X0.BOUTMUX.B5Q origin:016-clb-noutmux !30_20 !30_21 !30_22 30_23
CLBLM_R.SLICEM_X0.BOUTMUX.CY origin:016-clb-noutmux !30_20 !30_23 30_21 30_22
CLBLM_R.SLICEM_X0.BOUTMUX.F8 origin:016-clb-noutmux !30_20 !30_21 30_22 30_23
CLBLM_R.SLICEM_X0.BOUTMUX.O5 origin:016-clb-noutmux !30_21 !30_23 30_20 30_22
CLBLM_R.SLICEM_X0.BOUTMUX.O6 origin:016-clb-noutmux !30_21 !30_22 !30_23 30_20
CLBLM_R.SLICEM_X0.BOUTMUX.XOR origin:016-clb-noutmux !30_20 !30_22 !30_23 30_21
CLBLM_R.SLICEM_X0.C5FF.ZINI origin:011-clb-ffconfig 31_41
CLBLM_R.SLICEM_X0.C5FF.ZRST origin:011-clb-ffconfig 01_47
CLBLM_R.SLICEM_X0.C5FFMUX.IN_A origin:012-clb-n5ffmux 31_45
CLBLM_R.SLICEM_X0.C5FFMUX.IN_B origin:012-clb-n5ffmux 30_39
CLBLM_R.SLICEM_X0.CARRY4.ACY0 origin:013-clb-ncy0 30_15
CLBLM_R.SLICEM_X0.CARRY4.BCY0 origin:013-clb-ncy0 01_15
CLBLM_R.SLICEM_X0.CARRY4.CCY0 origin:013-clb-ncy0 30_48
CLBLM_R.SLICEM_X0.CARRY4.DCY0 origin:013-clb-ncy0 30_49
CLBLM_R.SLICEM_X0.CEUSEDMUX origin:014-clb-ffsrcemux 01_39
CLBLM_R.SLICEM_X0.CFF.ZINI origin:011-clb-ffconfig 31_33
CLBLM_R.SLICEM_X0.CFF.ZRST origin:011-clb-ffconfig 30_33
CLBLM_R.SLICEM_X0.CFFMUX.CX origin:015-clb-nffmux !30_35 !30_37 !30_38 30_36
CLBLM_R.SLICEM_X0.CFFMUX.CY origin:015-clb-nffmux !30_36 !30_38 30_35 30_37
CLBLM_R.SLICEM_X0.CFFMUX.F7 origin:015-clb-nffmux !30_37 !30_38 30_35 30_36
CLBLM_R.SLICEM_X0.CFFMUX.O5 origin:015-clb-nffmux !30_36 !30_37 30_35 30_38
CLBLM_R.SLICEM_X0.CFFMUX.O6 origin:015-clb-nffmux !30_35 !30_36 !30_37 30_38
CLBLM_R.SLICEM_X0.CFFMUX.XOR origin:015-clb-nffmux !30_35 !30_36 !30_38 30_37
CLBLM_R.SLICEM_X0.CLKINV origin:011-clb-ffconfig 01_51
CLBLM_R.SLICEM_X0.CLUT.DI1MUX.CI origin:019-clb-ndi1mux 01_43
CLBLM_R.SLICEM_X0.CLUT.INIT[00] origin:010-clb-lutinit 34_47
CLBLM_R.SLICEM_X0.CLUT.INIT[01] origin:010-clb-lutinit 35_47
CLBLM_R.SLICEM_X0.CLUT.INIT[02] origin:010-clb-lutinit 34_46
CLBLM_R.SLICEM_X0.CLUT.INIT[03] origin:010-clb-lutinit 35_46
CLBLM_R.SLICEM_X0.CLUT.INIT[04] origin:010-clb-lutinit 34_45
CLBLM_R.SLICEM_X0.CLUT.INIT[05] origin:010-clb-lutinit 35_45
CLBLM_R.SLICEM_X0.CLUT.INIT[06] origin:010-clb-lutinit 34_44
CLBLM_R.SLICEM_X0.CLUT.INIT[07] origin:010-clb-lutinit 35_44
CLBLM_R.SLICEM_X0.CLUT.INIT[08] origin:010-clb-lutinit 32_47
CLBLM_R.SLICEM_X0.CLUT.INIT[09] origin:010-clb-lutinit 33_47
CLBLM_R.SLICEM_X0.CLUT.INIT[10] origin:010-clb-lutinit 32_46
CLBLM_R.SLICEM_X0.CLUT.INIT[11] origin:010-clb-lutinit 33_46
CLBLM_R.SLICEM_X0.CLUT.INIT[12] origin:010-clb-lutinit 32_45
CLBLM_R.SLICEM_X0.CLUT.INIT[13] origin:010-clb-lutinit 33_45
CLBLM_R.SLICEM_X0.CLUT.INIT[14] origin:010-clb-lutinit 32_44
CLBLM_R.SLICEM_X0.CLUT.INIT[15] origin:010-clb-lutinit 33_44
CLBLM_R.SLICEM_X0.CLUT.INIT[16] origin:010-clb-lutinit 34_43
CLBLM_R.SLICEM_X0.CLUT.INIT[17] origin:010-clb-lutinit 35_43
CLBLM_R.SLICEM_X0.CLUT.INIT[18] origin:010-clb-lutinit 34_42
CLBLM_R.SLICEM_X0.CLUT.INIT[19] origin:010-clb-lutinit 35_42
CLBLM_R.SLICEM_X0.CLUT.INIT[20] origin:010-clb-lutinit 34_41
CLBLM_R.SLICEM_X0.CLUT.INIT[21] origin:010-clb-lutinit 35_41
CLBLM_R.SLICEM_X0.CLUT.INIT[22] origin:010-clb-lutinit 34_40
CLBLM_R.SLICEM_X0.CLUT.INIT[23] origin:010-clb-lutinit 35_40
CLBLM_R.SLICEM_X0.CLUT.INIT[24] origin:010-clb-lutinit 32_43
CLBLM_R.SLICEM_X0.CLUT.INIT[25] origin:010-clb-lutinit 33_43
CLBLM_R.SLICEM_X0.CLUT.INIT[26] origin:010-clb-lutinit 32_42
CLBLM_R.SLICEM_X0.CLUT.INIT[27] origin:010-clb-lutinit 33_42
CLBLM_R.SLICEM_X0.CLUT.INIT[28] origin:010-clb-lutinit 32_41
CLBLM_R.SLICEM_X0.CLUT.INIT[29] origin:010-clb-lutinit 33_41
CLBLM_R.SLICEM_X0.CLUT.INIT[30] origin:010-clb-lutinit 32_40
CLBLM_R.SLICEM_X0.CLUT.INIT[31] origin:010-clb-lutinit 33_40
CLBLM_R.SLICEM_X0.CLUT.INIT[32] origin:010-clb-lutinit 34_39
CLBLM_R.SLICEM_X0.CLUT.INIT[33] origin:010-clb-lutinit 35_39
CLBLM_R.SLICEM_X0.CLUT.INIT[34] origin:010-clb-lutinit 34_38
CLBLM_R.SLICEM_X0.CLUT.INIT[35] origin:010-clb-lutinit 35_38
CLBLM_R.SLICEM_X0.CLUT.INIT[36] origin:010-clb-lutinit 34_37
CLBLM_R.SLICEM_X0.CLUT.INIT[37] origin:010-clb-lutinit 35_37
CLBLM_R.SLICEM_X0.CLUT.INIT[38] origin:010-clb-lutinit 34_36
CLBLM_R.SLICEM_X0.CLUT.INIT[39] origin:010-clb-lutinit 35_36
CLBLM_R.SLICEM_X0.CLUT.INIT[40] origin:010-clb-lutinit 32_39
CLBLM_R.SLICEM_X0.CLUT.INIT[41] origin:010-clb-lutinit 33_39
CLBLM_R.SLICEM_X0.CLUT.INIT[42] origin:010-clb-lutinit 32_38
CLBLM_R.SLICEM_X0.CLUT.INIT[43] origin:010-clb-lutinit 33_38
CLBLM_R.SLICEM_X0.CLUT.INIT[44] origin:010-clb-lutinit 32_37
CLBLM_R.SLICEM_X0.CLUT.INIT[45] origin:010-clb-lutinit 33_37
CLBLM_R.SLICEM_X0.CLUT.INIT[46] origin:010-clb-lutinit 32_36
CLBLM_R.SLICEM_X0.CLUT.INIT[47] origin:010-clb-lutinit 33_36
CLBLM_R.SLICEM_X0.CLUT.INIT[48] origin:010-clb-lutinit 34_35
CLBLM_R.SLICEM_X0.CLUT.INIT[49] origin:010-clb-lutinit 35_35
CLBLM_R.SLICEM_X0.CLUT.INIT[50] origin:010-clb-lutinit 34_34
CLBLM_R.SLICEM_X0.CLUT.INIT[51] origin:010-clb-lutinit 35_34
CLBLM_R.SLICEM_X0.CLUT.INIT[52] origin:010-clb-lutinit 34_33
CLBLM_R.SLICEM_X0.CLUT.INIT[53] origin:010-clb-lutinit 35_33
CLBLM_R.SLICEM_X0.CLUT.INIT[54] origin:010-clb-lutinit 34_32
CLBLM_R.SLICEM_X0.CLUT.INIT[55] origin:010-clb-lutinit 35_32
CLBLM_R.SLICEM_X0.CLUT.INIT[56] origin:010-clb-lutinit 32_35
CLBLM_R.SLICEM_X0.CLUT.INIT[57] origin:010-clb-lutinit 33_35
CLBLM_R.SLICEM_X0.CLUT.INIT[58] origin:010-clb-lutinit 32_34
CLBLM_R.SLICEM_X0.CLUT.INIT[59] origin:010-clb-lutinit 33_34
CLBLM_R.SLICEM_X0.CLUT.INIT[60] origin:010-clb-lutinit 32_33
CLBLM_R.SLICEM_X0.CLUT.INIT[61] origin:010-clb-lutinit 33_33
CLBLM_R.SLICEM_X0.CLUT.INIT[62] origin:010-clb-lutinit 32_32
CLBLM_R.SLICEM_X0.CLUT.INIT[63] origin:010-clb-lutinit 33_32
CLBLM_R.SLICEM_X0.CLUT.RAM origin:018-clb-ram 31_46
CLBLM_R.SLICEM_X0.CLUT.SMALL origin:018-clb-ram 00_28
CLBLM_R.SLICEM_X0.CLUT.SRL origin:018-clb-ram 30_46
CLBLM_R.SLICEM_X0.COUTMUX.C5Q origin:016-clb-noutmux !30_40 !30_44 !30_45 30_43
CLBLM_R.SLICEM_X0.COUTMUX.CY origin:016-clb-noutmux !30_43 !30_45 30_40 30_44
CLBLM_R.SLICEM_X0.COUTMUX.F7 origin:016-clb-noutmux !30_44 !30_45 30_40 30_43
CLBLM_R.SLICEM_X0.COUTMUX.O5 origin:016-clb-noutmux !30_43 !30_44 30_40 30_45
CLBLM_R.SLICEM_X0.COUTMUX.O6 origin:016-clb-noutmux !30_40 !30_43 !30_44 30_45
CLBLM_R.SLICEM_X0.COUTMUX.XOR origin:016-clb-noutmux !30_40 !30_43 !30_45 30_44
CLBLM_R.SLICEM_X0.D5FF.ZINI origin:011-clb-ffconfig 31_51
CLBLM_R.SLICEM_X0.D5FF.ZRST origin:011-clb-ffconfig 01_55
CLBLM_R.SLICEM_X0.D5FFMUX.IN_A origin:012-clb-n5ffmux 30_55
CLBLM_R.SLICEM_X0.D5FFMUX.IN_B origin:012-clb-n5ffmux 30_54
CLBLM_R.SLICEM_X0.DFF.ZINI origin:011-clb-ffconfig 31_58
CLBLM_R.SLICEM_X0.DFF.ZRST origin:011-clb-ffconfig 30_50
CLBLM_R.SLICEM_X0.DFFMUX.CY origin:015-clb-nffmux !30_59 !30_61 30_60 30_62
CLBLM_R.SLICEM_X0.DFFMUX.DX origin:015-clb-nffmux !30_59 !30_60 !30_62 30_61
CLBLM_R.SLICEM_X0.DFFMUX.O5 origin:015-clb-nffmux !30_60 !30_61 30_59 30_62
CLBLM_R.SLICEM_X0.DFFMUX.O6 origin:015-clb-nffmux !30_60 !30_61 !30_62 30_59
CLBLM_R.SLICEM_X0.DFFMUX.XOR origin:015-clb-nffmux !30_59 !30_61 !30_62 30_60
CLBLM_R.SLICEM_X0.DLUT.INIT[00] origin:010-clb-lutinit 34_63
CLBLM_R.SLICEM_X0.DLUT.INIT[01] origin:010-clb-lutinit 35_63
CLBLM_R.SLICEM_X0.DLUT.INIT[02] origin:010-clb-lutinit 34_62
CLBLM_R.SLICEM_X0.DLUT.INIT[03] origin:010-clb-lutinit 35_62
CLBLM_R.SLICEM_X0.DLUT.INIT[04] origin:010-clb-lutinit 34_61
CLBLM_R.SLICEM_X0.DLUT.INIT[05] origin:010-clb-lutinit 35_61
CLBLM_R.SLICEM_X0.DLUT.INIT[06] origin:010-clb-lutinit 34_60
CLBLM_R.SLICEM_X0.DLUT.INIT[07] origin:010-clb-lutinit 35_60
CLBLM_R.SLICEM_X0.DLUT.INIT[08] origin:010-clb-lutinit 32_63
CLBLM_R.SLICEM_X0.DLUT.INIT[09] origin:010-clb-lutinit 33_63
CLBLM_R.SLICEM_X0.DLUT.INIT[10] origin:010-clb-lutinit 32_62
CLBLM_R.SLICEM_X0.DLUT.INIT[11] origin:010-clb-lutinit 33_62
CLBLM_R.SLICEM_X0.DLUT.INIT[12] origin:010-clb-lutinit 32_61
CLBLM_R.SLICEM_X0.DLUT.INIT[13] origin:010-clb-lutinit 33_61
CLBLM_R.SLICEM_X0.DLUT.INIT[14] origin:010-clb-lutinit 32_60
CLBLM_R.SLICEM_X0.DLUT.INIT[15] origin:010-clb-lutinit 33_60
CLBLM_R.SLICEM_X0.DLUT.INIT[16] origin:010-clb-lutinit 34_59
CLBLM_R.SLICEM_X0.DLUT.INIT[17] origin:010-clb-lutinit 35_59
CLBLM_R.SLICEM_X0.DLUT.INIT[18] origin:010-clb-lutinit 34_58
CLBLM_R.SLICEM_X0.DLUT.INIT[19] origin:010-clb-lutinit 35_58
CLBLM_R.SLICEM_X0.DLUT.INIT[20] origin:010-clb-lutinit 34_57
CLBLM_R.SLICEM_X0.DLUT.INIT[21] origin:010-clb-lutinit 35_57
CLBLM_R.SLICEM_X0.DLUT.INIT[22] origin:010-clb-lutinit 34_56
CLBLM_R.SLICEM_X0.DLUT.INIT[23] origin:010-clb-lutinit 35_56
CLBLM_R.SLICEM_X0.DLUT.INIT[24] origin:010-clb-lutinit 32_59
CLBLM_R.SLICEM_X0.DLUT.INIT[25] origin:010-clb-lutinit 33_59
CLBLM_R.SLICEM_X0.DLUT.INIT[26] origin:010-clb-lutinit 32_58
CLBLM_R.SLICEM_X0.DLUT.INIT[27] origin:010-clb-lutinit 33_58
CLBLM_R.SLICEM_X0.DLUT.INIT[28] origin:010-clb-lutinit 32_57
CLBLM_R.SLICEM_X0.DLUT.INIT[29] origin:010-clb-lutinit 33_57
CLBLM_R.SLICEM_X0.DLUT.INIT[30] origin:010-clb-lutinit 32_56
CLBLM_R.SLICEM_X0.DLUT.INIT[31] origin:010-clb-lutinit 33_56
CLBLM_R.SLICEM_X0.DLUT.INIT[32] origin:010-clb-lutinit 34_55
CLBLM_R.SLICEM_X0.DLUT.INIT[33] origin:010-clb-lutinit 35_55
CLBLM_R.SLICEM_X0.DLUT.INIT[34] origin:010-clb-lutinit 34_54
CLBLM_R.SLICEM_X0.DLUT.INIT[35] origin:010-clb-lutinit 35_54
CLBLM_R.SLICEM_X0.DLUT.INIT[36] origin:010-clb-lutinit 34_53
CLBLM_R.SLICEM_X0.DLUT.INIT[37] origin:010-clb-lutinit 35_53
CLBLM_R.SLICEM_X0.DLUT.INIT[38] origin:010-clb-lutinit 34_52
CLBLM_R.SLICEM_X0.DLUT.INIT[39] origin:010-clb-lutinit 35_52
CLBLM_R.SLICEM_X0.DLUT.INIT[40] origin:010-clb-lutinit 32_55
CLBLM_R.SLICEM_X0.DLUT.INIT[41] origin:010-clb-lutinit 33_55
CLBLM_R.SLICEM_X0.DLUT.INIT[42] origin:010-clb-lutinit 32_54
CLBLM_R.SLICEM_X0.DLUT.INIT[43] origin:010-clb-lutinit 33_54
CLBLM_R.SLICEM_X0.DLUT.INIT[44] origin:010-clb-lutinit 32_53
CLBLM_R.SLICEM_X0.DLUT.INIT[45] origin:010-clb-lutinit 33_53
CLBLM_R.SLICEM_X0.DLUT.INIT[46] origin:010-clb-lutinit 32_52
CLBLM_R.SLICEM_X0.DLUT.INIT[47] origin:010-clb-lutinit 33_52
CLBLM_R.SLICEM_X0.DLUT.INIT[48] origin:010-clb-lutinit 34_51
CLBLM_R.SLICEM_X0.DLUT.INIT[49] origin:010-clb-lutinit 35_51
CLBLM_R.SLICEM_X0.DLUT.INIT[50] origin:010-clb-lutinit 34_50
CLBLM_R.SLICEM_X0.DLUT.INIT[51] origin:010-clb-lutinit 35_50
CLBLM_R.SLICEM_X0.DLUT.INIT[52] origin:010-clb-lutinit 34_49
CLBLM_R.SLICEM_X0.DLUT.INIT[53] origin:010-clb-lutinit 35_49
CLBLM_R.SLICEM_X0.DLUT.INIT[54] origin:010-clb-lutinit 34_48
CLBLM_R.SLICEM_X0.DLUT.INIT[55] origin:010-clb-lutinit 35_48
CLBLM_R.SLICEM_X0.DLUT.INIT[56] origin:010-clb-lutinit 32_51
CLBLM_R.SLICEM_X0.DLUT.INIT[57] origin:010-clb-lutinit 33_51
CLBLM_R.SLICEM_X0.DLUT.INIT[58] origin:010-clb-lutinit 32_50
CLBLM_R.SLICEM_X0.DLUT.INIT[59] origin:010-clb-lutinit 33_50
CLBLM_R.SLICEM_X0.DLUT.INIT[60] origin:010-clb-lutinit 32_49
CLBLM_R.SLICEM_X0.DLUT.INIT[61] origin:010-clb-lutinit 33_49
CLBLM_R.SLICEM_X0.DLUT.INIT[62] origin:010-clb-lutinit 32_48
CLBLM_R.SLICEM_X0.DLUT.INIT[63] origin:010-clb-lutinit 33_48
CLBLM_R.SLICEM_X0.DLUT.RAM origin:018-clb-ram 31_47
CLBLM_R.SLICEM_X0.DLUT.SMALL origin:018-clb-ram 01_59
CLBLM_R.SLICEM_X0.DLUT.SRL origin:018-clb-ram 30_47
CLBLM_R.SLICEM_X0.DOUTMUX.CY origin:016-clb-noutmux !30_56 !30_57 30_51 30_52
CLBLM_R.SLICEM_X0.DOUTMUX.D5Q origin:016-clb-noutmux !30_51 !30_52 !30_56 30_57
CLBLM_R.SLICEM_X0.DOUTMUX.O5 origin:016-clb-noutmux !30_51 !30_57 30_52 30_56
CLBLM_R.SLICEM_X0.DOUTMUX.O6 origin:016-clb-noutmux !30_51 !30_52 !30_57 30_56
CLBLM_R.SLICEM_X0.DOUTMUX.XOR origin:016-clb-noutmux !30_52 !30_56 !30_57 30_51
CLBLM_R.SLICEM_X0.FFSYNC origin:011-clb-ffconfig 00_48
CLBLM_R.SLICEM_X0.LATCH origin:011-clb-ffconfig 30_32
CLBLM_R.SLICEM_X0.PRECYINIT.AX origin:017-clb-precyinit !00_12 !30_13 30_14
CLBLM_R.SLICEM_X0.PRECYINIT.C0 origin:017-clb-precyinit !00_12 !30_13 !30_14
CLBLM_R.SLICEM_X0.PRECYINIT.C1 origin:017-clb-precyinit !30_13 !30_14 00_12
CLBLM_R.SLICEM_X0.PRECYINIT.CIN origin:017-clb-precyinit !00_12 !30_14 30_13
CLBLM_R.SLICEM_X0.SRUSEDMUX origin:014-clb-ffsrcemux 01_35
CLBLM_R.SLICEM_X0.WA7USED origin:018-clb-ram 00_40
CLBLM_R.SLICEM_X0.WA8USED origin:018-clb-ram 01_27
CLBLM_R.SLICEM_X0.WEMUX.CE origin:018-clb-ram 01_23

336
zynq7/segbits_clk_bufg_bot_r.origin_info.db Normal file
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@ -0,0 +1,336 @@
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y0.INIT_OUT origin:042-clk-bufg-config 27_13
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y0.IN_USE origin:042-clk-bufg-config 27_00 27_15
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y0.IS_IGNORE0_INVERTED origin:042-clk-bufg-config 26_01
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y0.IS_IGNORE1_INVERTED origin:042-clk-bufg-config 27_12
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y0.PRESELECT_I1 origin:042-clk-bufg-config 26_12
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y0.ZINV_CE0 origin:042-clk-bufg-config 27_02
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y0.ZINV_CE1 origin:042-clk-bufg-config 27_11
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y0.ZINV_S0 origin:042-clk-bufg-config 27_03
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y0.ZINV_S1 origin:042-clk-bufg-config 26_11
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y0.ZPRESELECT_I0 origin:042-clk-bufg-config 26_02
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y1.INIT_OUT origin:042-clk-bufg-config 27_29
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y1.IN_USE origin:042-clk-bufg-config 27_16 27_31
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y1.IS_IGNORE0_INVERTED origin:042-clk-bufg-config 26_17
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y1.IS_IGNORE1_INVERTED origin:042-clk-bufg-config 27_28
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y1.PRESELECT_I1 origin:042-clk-bufg-config 26_28
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y1.ZINV_CE0 origin:042-clk-bufg-config 27_18
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y1.ZINV_CE1 origin:042-clk-bufg-config 27_27
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y1.ZINV_S0 origin:042-clk-bufg-config 27_19
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y1.ZINV_S1 origin:042-clk-bufg-config 26_27
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y1.ZPRESELECT_I0 origin:042-clk-bufg-config 26_18
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y10.INIT_OUT origin:042-clk-bufg-config 27_173
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y10.IN_USE origin:042-clk-bufg-config 27_160 27_175
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y10.IS_IGNORE0_INVERTED origin:042-clk-bufg-config 26_161
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y10.IS_IGNORE1_INVERTED origin:042-clk-bufg-config 27_172
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y10.PRESELECT_I1 origin:042-clk-bufg-config 26_172
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y10.ZINV_CE0 origin:042-clk-bufg-config 27_162
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y10.ZINV_CE1 origin:042-clk-bufg-config 27_171
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y10.ZINV_S0 origin:042-clk-bufg-config 27_163
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y10.ZINV_S1 origin:042-clk-bufg-config 26_171
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y10.ZPRESELECT_I0 origin:042-clk-bufg-config 26_162
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y11.INIT_OUT origin:042-clk-bufg-config 27_189
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y11.IN_USE origin:042-clk-bufg-config 27_176 27_191
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y11.IS_IGNORE0_INVERTED origin:042-clk-bufg-config 26_177
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y11.IS_IGNORE1_INVERTED origin:042-clk-bufg-config 27_188
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y11.PRESELECT_I1 origin:042-clk-bufg-config 26_188
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y11.ZINV_CE0 origin:042-clk-bufg-config 27_178
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y11.ZINV_CE1 origin:042-clk-bufg-config 27_187
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y11.ZINV_S0 origin:042-clk-bufg-config 27_179
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y11.ZINV_S1 origin:042-clk-bufg-config 26_187
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y11.ZPRESELECT_I0 origin:042-clk-bufg-config 26_178
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y12.INIT_OUT origin:042-clk-bufg-config 27_205
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y12.IN_USE origin:042-clk-bufg-config 27_192 27_207
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y12.IS_IGNORE0_INVERTED origin:042-clk-bufg-config 26_193
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y12.IS_IGNORE1_INVERTED origin:042-clk-bufg-config 27_204
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y12.PRESELECT_I1 origin:042-clk-bufg-config 26_204
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y12.ZINV_CE0 origin:042-clk-bufg-config 27_194
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y12.ZINV_CE1 origin:042-clk-bufg-config 27_203
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y12.ZINV_S0 origin:042-clk-bufg-config 27_195
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y12.ZINV_S1 origin:042-clk-bufg-config 26_203
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y12.ZPRESELECT_I0 origin:042-clk-bufg-config 26_194
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y13.INIT_OUT origin:042-clk-bufg-config 27_221
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y13.IN_USE origin:042-clk-bufg-config 27_208 27_223
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y13.IS_IGNORE0_INVERTED origin:042-clk-bufg-config 26_209
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y13.IS_IGNORE1_INVERTED origin:042-clk-bufg-config 27_220
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y13.PRESELECT_I1 origin:042-clk-bufg-config 26_220
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y13.ZINV_CE0 origin:042-clk-bufg-config 27_210
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y13.ZINV_CE1 origin:042-clk-bufg-config 27_219
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y13.ZINV_S0 origin:042-clk-bufg-config 27_211
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y13.ZINV_S1 origin:042-clk-bufg-config 26_219
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y13.ZPRESELECT_I0 origin:042-clk-bufg-config 26_210
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y14.INIT_OUT origin:042-clk-bufg-config 27_237
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y14.IN_USE origin:042-clk-bufg-config 27_224 27_239
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y14.IS_IGNORE0_INVERTED origin:042-clk-bufg-config 26_225
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y14.IS_IGNORE1_INVERTED origin:042-clk-bufg-config 27_236
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y14.PRESELECT_I1 origin:042-clk-bufg-config 26_236
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y14.ZINV_CE0 origin:042-clk-bufg-config 27_226
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y14.ZINV_CE1 origin:042-clk-bufg-config 27_235
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y14.ZINV_S0 origin:042-clk-bufg-config 27_227
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y14.ZINV_S1 origin:042-clk-bufg-config 26_235
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y14.ZPRESELECT_I0 origin:042-clk-bufg-config 26_226
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y15.INIT_OUT origin:042-clk-bufg-config 27_253
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y15.IN_USE origin:042-clk-bufg-config 27_240 27_255
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y15.IS_IGNORE0_INVERTED origin:042-clk-bufg-config 26_241
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y15.IS_IGNORE1_INVERTED origin:042-clk-bufg-config 27_252
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y15.PRESELECT_I1 origin:042-clk-bufg-config 26_252
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y15.ZINV_CE0 origin:042-clk-bufg-config 27_242
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y15.ZINV_CE1 origin:042-clk-bufg-config 27_251
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y15.ZINV_S0 origin:042-clk-bufg-config 27_243
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y15.ZINV_S1 origin:042-clk-bufg-config 26_251
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y15.ZPRESELECT_I0 origin:042-clk-bufg-config 26_242
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y2.INIT_OUT origin:042-clk-bufg-config 27_45
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y2.IN_USE origin:042-clk-bufg-config 27_32 27_47
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y2.IS_IGNORE0_INVERTED origin:042-clk-bufg-config 26_33
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y2.IS_IGNORE1_INVERTED origin:042-clk-bufg-config 27_44
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y2.PRESELECT_I1 origin:042-clk-bufg-config 26_44
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y2.ZINV_CE0 origin:042-clk-bufg-config 27_34
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y2.ZINV_CE1 origin:042-clk-bufg-config 27_43
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y2.ZINV_S0 origin:042-clk-bufg-config 27_35
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y2.ZINV_S1 origin:042-clk-bufg-config 26_43
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y2.ZPRESELECT_I0 origin:042-clk-bufg-config 26_34
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y3.INIT_OUT origin:042-clk-bufg-config 27_61
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y3.IN_USE origin:042-clk-bufg-config 27_48 27_63
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y3.IS_IGNORE0_INVERTED origin:042-clk-bufg-config 26_49
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y3.IS_IGNORE1_INVERTED origin:042-clk-bufg-config 27_60
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y3.PRESELECT_I1 origin:042-clk-bufg-config 26_60
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y3.ZINV_CE0 origin:042-clk-bufg-config 27_50
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y3.ZINV_CE1 origin:042-clk-bufg-config 27_59
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y3.ZINV_S0 origin:042-clk-bufg-config 27_51
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y3.ZINV_S1 origin:042-clk-bufg-config 26_59
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y3.ZPRESELECT_I0 origin:042-clk-bufg-config 26_50
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y4.INIT_OUT origin:042-clk-bufg-config 27_77
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y4.IN_USE origin:042-clk-bufg-config 27_64 27_79
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y4.IS_IGNORE0_INVERTED origin:042-clk-bufg-config 26_65
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y4.IS_IGNORE1_INVERTED origin:042-clk-bufg-config 27_76
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y4.PRESELECT_I1 origin:042-clk-bufg-config 26_76
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y4.ZINV_CE0 origin:042-clk-bufg-config 27_66
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y4.ZINV_CE1 origin:042-clk-bufg-config 27_75
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y4.ZINV_S0 origin:042-clk-bufg-config 27_67
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y4.ZINV_S1 origin:042-clk-bufg-config 26_75
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y4.ZPRESELECT_I0 origin:042-clk-bufg-config 26_66
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y5.INIT_OUT origin:042-clk-bufg-config 27_93
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y5.IN_USE origin:042-clk-bufg-config 27_80 27_95
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y5.IS_IGNORE0_INVERTED origin:042-clk-bufg-config 26_81
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y5.IS_IGNORE1_INVERTED origin:042-clk-bufg-config 27_92
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y5.PRESELECT_I1 origin:042-clk-bufg-config 26_92
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y5.ZINV_CE0 origin:042-clk-bufg-config 27_82
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y5.ZINV_CE1 origin:042-clk-bufg-config 27_91
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y5.ZINV_S0 origin:042-clk-bufg-config 27_83
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y5.ZINV_S1 origin:042-clk-bufg-config 26_91
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y5.ZPRESELECT_I0 origin:042-clk-bufg-config 26_82
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y6.INIT_OUT origin:042-clk-bufg-config 27_109
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y6.IN_USE origin:042-clk-bufg-config 27_111 27_96
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y6.IS_IGNORE0_INVERTED origin:042-clk-bufg-config 26_97
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y6.IS_IGNORE1_INVERTED origin:042-clk-bufg-config 27_108
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y6.PRESELECT_I1 origin:042-clk-bufg-config 26_108
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y6.ZINV_CE0 origin:042-clk-bufg-config 27_98
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y6.ZINV_CE1 origin:042-clk-bufg-config 27_107
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y6.ZINV_S0 origin:042-clk-bufg-config 27_99
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y6.ZINV_S1 origin:042-clk-bufg-config 26_107
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y6.ZPRESELECT_I0 origin:042-clk-bufg-config 26_98
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y7.INIT_OUT origin:042-clk-bufg-config 27_125
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y7.IN_USE origin:042-clk-bufg-config 27_112 27_127
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y7.IS_IGNORE0_INVERTED origin:042-clk-bufg-config 26_113
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y7.IS_IGNORE1_INVERTED origin:042-clk-bufg-config 27_124
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y7.PRESELECT_I1 origin:042-clk-bufg-config 26_124
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y7.ZINV_CE0 origin:042-clk-bufg-config 27_114
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y7.ZINV_CE1 origin:042-clk-bufg-config 27_123
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y7.ZINV_S0 origin:042-clk-bufg-config 27_115
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y7.ZINV_S1 origin:042-clk-bufg-config 26_123
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y7.ZPRESELECT_I0 origin:042-clk-bufg-config 26_114
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y8.INIT_OUT origin:042-clk-bufg-config 27_141
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y8.IN_USE origin:042-clk-bufg-config 27_128 27_143
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y8.IS_IGNORE0_INVERTED origin:042-clk-bufg-config 26_129
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y8.IS_IGNORE1_INVERTED origin:042-clk-bufg-config 27_140
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y8.PRESELECT_I1 origin:042-clk-bufg-config 26_140
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y8.ZINV_CE0 origin:042-clk-bufg-config 27_130
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y8.ZINV_CE1 origin:042-clk-bufg-config 27_139
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y8.ZINV_S0 origin:042-clk-bufg-config 27_131
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y8.ZINV_S1 origin:042-clk-bufg-config 26_139
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y8.ZPRESELECT_I0 origin:042-clk-bufg-config 26_130
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y9.INIT_OUT origin:042-clk-bufg-config 27_157
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y9.IN_USE origin:042-clk-bufg-config 27_144 27_159
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y9.IS_IGNORE0_INVERTED origin:042-clk-bufg-config 26_145
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y9.IS_IGNORE1_INVERTED origin:042-clk-bufg-config 27_156
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y9.PRESELECT_I1 origin:042-clk-bufg-config 26_156
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y9.ZINV_CE0 origin:042-clk-bufg-config 27_146
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y9.ZINV_CE1 origin:042-clk-bufg-config 27_155
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y9.ZINV_S0 origin:042-clk-bufg-config 27_147
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y9.ZINV_S1 origin:042-clk-bufg-config 26_155
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y9.ZPRESELECT_I0 origin:042-clk-bufg-config 26_146
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL0_I0.CLK_BUFG_BOT_R_CK_MUXED0 origin:044-clk-bufg-pips !26_07 !27_06 26_08
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL0_I0.CLK_BUFG_IMUX24_0 origin:044-clk-bufg-pips !26_07 !26_08 27_06
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL0_I0.CLK_BUFG_IMUX28_0 origin:044-clk-bufg-pips !26_07 !26_08 !27_06
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL0_I0.CLK_BUFG_R_FBG_OUT1 origin:044-clk-bufg-pips !26_08 26_07 27_06
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL0_I0.CLK_BUFG_R_FBG_OUT15 origin:044-clk-bufg-pips !26_08 !27_06 26_07
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL0_I1.CLK_BUFG_BOT_R_CK_MUXED1 origin:044-clk-bufg-pips !26_05 !27_05 26_04
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL0_I1.CLK_BUFG_IMUX24_0 origin:044-clk-bufg-pips !26_04 !27_05 26_05
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL0_I1.CLK_BUFG_IMUX28_0 origin:044-clk-bufg-pips !26_04 !26_05 !27_05
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL0_I1.CLK_BUFG_R_FBG_OUT1 origin:044-clk-bufg-pips !26_04 26_05 27_05
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL0_I1.CLK_BUFG_R_FBG_OUT15 origin:044-clk-bufg-pips !26_04 !26_05 27_05
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL10_I0.CLK_BUFG_BOT_R_CK_MUXED20 origin:044-clk-bufg-pips !26_167 !27_166 26_168
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL10_I0.CLK_BUFG_IMUX26_2 origin:044-clk-bufg-pips !26_167 !26_168 27_166
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL10_I0.CLK_BUFG_IMUX30_2 origin:044-clk-bufg-pips !26_167 !26_168 !27_166
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL10_I0.CLK_BUFG_R_FBG_OUT11 origin:044-clk-bufg-pips !26_168 26_167 27_166
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL10_I0.CLK_BUFG_R_FBG_OUT9 origin:044-clk-bufg-pips !26_168 !27_166 26_167
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL10_I1.CLK_BUFG_BOT_R_CK_MUXED21 origin:044-clk-bufg-pips !26_165 !27_165 26_164
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL10_I1.CLK_BUFG_IMUX26_2 origin:044-clk-bufg-pips !26_164 !27_165 26_165
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL10_I1.CLK_BUFG_IMUX30_2 origin:044-clk-bufg-pips !26_164 !26_165 !27_165
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL10_I1.CLK_BUFG_R_FBG_OUT11 origin:044-clk-bufg-pips !26_164 26_165 27_165
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL10_I1.CLK_BUFG_R_FBG_OUT9 origin:044-clk-bufg-pips !26_164 !26_165 27_165
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL11_I0.CLK_BUFG_BOT_R_CK_MUXED22 origin:044-clk-bufg-pips !26_183 !27_182 26_184
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL11_I0.CLK_BUFG_IMUX27_2 origin:044-clk-bufg-pips !26_183 !26_184 27_182
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL11_I0.CLK_BUFG_IMUX31_2 origin:044-clk-bufg-pips !26_183 !26_184 !27_182
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL11_I0.CLK_BUFG_R_FBG_OUT10 origin:044-clk-bufg-pips !26_184 !27_182 26_183
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL11_I0.CLK_BUFG_R_FBG_OUT12 origin:044-clk-bufg-pips !26_184 26_183 27_182
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL11_I1.CLK_BUFG_BOT_R_CK_MUXED23 origin:044-clk-bufg-pips !26_181 !27_181 26_180
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL11_I1.CLK_BUFG_IMUX27_2 origin:044-clk-bufg-pips !26_180 !27_181 26_181
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL11_I1.CLK_BUFG_IMUX31_2 origin:044-clk-bufg-pips !26_180 !26_181 !27_181
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL11_I1.CLK_BUFG_R_FBG_OUT10 origin:044-clk-bufg-pips !26_180 !26_181 27_181
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL11_I1.CLK_BUFG_R_FBG_OUT12 origin:044-clk-bufg-pips !26_180 26_181 27_181
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL12_I0.CLK_BUFG_BOT_R_CK_MUXED24 origin:044-clk-bufg-pips !26_199 !27_198 26_200
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL12_I0.CLK_BUFG_IMUX24_3 origin:044-clk-bufg-pips !26_199 !26_200 27_198
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL12_I0.CLK_BUFG_IMUX28_3 origin:044-clk-bufg-pips !26_199 !26_200 !27_198
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL12_I0.CLK_BUFG_R_FBG_OUT11 origin:044-clk-bufg-pips !26_200 !27_198 26_199
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL12_I0.CLK_BUFG_R_FBG_OUT13 origin:044-clk-bufg-pips !26_200 26_199 27_198
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL12_I1.CLK_BUFG_BOT_R_CK_MUXED25 origin:044-clk-bufg-pips !26_197 !27_197 26_196
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL12_I1.CLK_BUFG_IMUX24_3 origin:044-clk-bufg-pips !26_196 !27_197 26_197
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL12_I1.CLK_BUFG_IMUX28_3 origin:044-clk-bufg-pips !26_196 !26_197 !27_197
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL12_I1.CLK_BUFG_R_FBG_OUT11 origin:044-clk-bufg-pips !26_196 !26_197 27_197
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL12_I1.CLK_BUFG_R_FBG_OUT13 origin:044-clk-bufg-pips !26_196 26_197 27_197
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL13_I0.CLK_BUFG_BOT_R_CK_MUXED26 origin:044-clk-bufg-pips !26_215 !27_214 26_216
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL13_I0.CLK_BUFG_IMUX25_3 origin:044-clk-bufg-pips !26_215 !26_216 27_214
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL13_I0.CLK_BUFG_IMUX29_3 origin:044-clk-bufg-pips !26_215 !26_216 !27_214
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL13_I0.CLK_BUFG_R_FBG_OUT12 origin:044-clk-bufg-pips !26_216 !27_214 26_215
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL13_I0.CLK_BUFG_R_FBG_OUT14 origin:044-clk-bufg-pips !26_216 26_215 27_214
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL13_I1.CLK_BUFG_BOT_R_CK_MUXED27 origin:044-clk-bufg-pips !26_213 !27_213 26_212
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL13_I1.CLK_BUFG_IMUX25_3 origin:044-clk-bufg-pips !26_212 !27_213 26_213
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL13_I1.CLK_BUFG_IMUX29_3 origin:044-clk-bufg-pips !26_212 !26_213 !27_213
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL13_I1.CLK_BUFG_R_FBG_OUT12 origin:044-clk-bufg-pips !26_212 !26_213 27_213
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL13_I1.CLK_BUFG_R_FBG_OUT14 origin:044-clk-bufg-pips !26_212 26_213 27_213
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL14_I0.CLK_BUFG_BOT_R_CK_MUXED28 origin:044-clk-bufg-pips !26_231 !27_230 26_232
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL14_I0.CLK_BUFG_IMUX26_3 origin:044-clk-bufg-pips !26_231 !26_232 27_230
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL14_I0.CLK_BUFG_IMUX30_3 origin:044-clk-bufg-pips !26_231 !26_232 !27_230
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL14_I0.CLK_BUFG_R_FBG_OUT13 origin:044-clk-bufg-pips !26_232 !27_230 26_231
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL14_I0.CLK_BUFG_R_FBG_OUT15 origin:044-clk-bufg-pips !26_232 26_231 27_230
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL14_I1.CLK_BUFG_BOT_R_CK_MUXED29 origin:044-clk-bufg-pips !26_229 !27_229 26_228
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL14_I1.CLK_BUFG_IMUX26_3 origin:044-clk-bufg-pips !26_228 !27_229 26_229
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL14_I1.CLK_BUFG_IMUX30_3 origin:044-clk-bufg-pips !26_228 !26_229 !27_229
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL14_I1.CLK_BUFG_R_FBG_OUT13 origin:044-clk-bufg-pips !26_228 !26_229 27_229
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL14_I1.CLK_BUFG_R_FBG_OUT15 origin:044-clk-bufg-pips !26_228 26_229 27_229
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL15_I0.CLK_BUFG_BOT_R_CK_MUXED30 origin:044-clk-bufg-pips !26_247 !27_246 26_248
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL15_I0.CLK_BUFG_IMUX27_3 origin:044-clk-bufg-pips !26_247 !26_248 27_246
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL15_I0.CLK_BUFG_IMUX31_3 origin:044-clk-bufg-pips !26_247 !26_248 !27_246
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL15_I0.CLK_BUFG_R_FBG_OUT0 origin:044-clk-bufg-pips !26_248 26_247 27_246
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL15_I0.CLK_BUFG_R_FBG_OUT14 origin:044-clk-bufg-pips !26_248 !27_246 26_247
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL15_I1.CLK_BUFG_BOT_R_CK_MUXED31 origin:044-clk-bufg-pips !26_245 !27_245 26_244
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL15_I1.CLK_BUFG_IMUX27_3 origin:044-clk-bufg-pips !26_244 !27_245 26_245
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL15_I1.CLK_BUFG_IMUX31_3 origin:044-clk-bufg-pips !26_244 !26_245 !27_245
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL15_I1.CLK_BUFG_R_FBG_OUT0 origin:044-clk-bufg-pips !26_244 26_245 27_245
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL15_I1.CLK_BUFG_R_FBG_OUT14 origin:044-clk-bufg-pips !26_244 !26_245 27_245
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL1_I0.CLK_BUFG_BOT_R_CK_MUXED2 origin:044-clk-bufg-pips !26_23 !27_22 26_24
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL1_I0.CLK_BUFG_IMUX25_0 origin:044-clk-bufg-pips !26_23 !26_24 27_22
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL1_I0.CLK_BUFG_IMUX29_0 origin:044-clk-bufg-pips !26_23 !26_24 !27_22
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL1_I0.CLK_BUFG_R_FBG_OUT0 origin:044-clk-bufg-pips !26_24 !27_22 26_23
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL1_I0.CLK_BUFG_R_FBG_OUT2 origin:044-clk-bufg-pips !26_24 26_23 27_22
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL1_I1.CLK_BUFG_BOT_R_CK_MUXED3 origin:044-clk-bufg-pips !26_21 !27_21 26_20
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL1_I1.CLK_BUFG_IMUX25_0 origin:044-clk-bufg-pips !26_20 !27_21 26_21
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL1_I1.CLK_BUFG_IMUX29_0 origin:044-clk-bufg-pips !26_20 !26_21 !27_21
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL1_I1.CLK_BUFG_R_FBG_OUT0 origin:044-clk-bufg-pips !26_20 !26_21 27_21
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL1_I1.CLK_BUFG_R_FBG_OUT2 origin:044-clk-bufg-pips !26_20 26_21 27_21
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL2_I0.CLK_BUFG_BOT_R_CK_MUXED4 origin:044-clk-bufg-pips !26_39 !27_38 26_40
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL2_I0.CLK_BUFG_IMUX26_0 origin:044-clk-bufg-pips !26_39 !26_40 27_38
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL2_I0.CLK_BUFG_IMUX30_0 origin:044-clk-bufg-pips !26_39 !26_40 !27_38
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL2_I0.CLK_BUFG_R_FBG_OUT1 origin:044-clk-bufg-pips !26_40 !27_38 26_39
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL2_I0.CLK_BUFG_R_FBG_OUT3 origin:044-clk-bufg-pips !26_40 26_39 27_38
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL2_I1.CLK_BUFG_BOT_R_CK_MUXED5 origin:044-clk-bufg-pips !26_37 !27_37 26_36
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL2_I1.CLK_BUFG_IMUX26_0 origin:044-clk-bufg-pips !26_36 !27_37 26_37
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL2_I1.CLK_BUFG_IMUX30_0 origin:044-clk-bufg-pips !26_36 !26_37 !27_37
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL2_I1.CLK_BUFG_R_FBG_OUT1 origin:044-clk-bufg-pips !26_36 !26_37 27_37
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL2_I1.CLK_BUFG_R_FBG_OUT3 origin:044-clk-bufg-pips !26_36 26_37 27_37
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL3_I0.CLK_BUFG_BOT_R_CK_MUXED6 origin:044-clk-bufg-pips !26_55 !27_54 26_56
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL3_I0.CLK_BUFG_IMUX27_0 origin:044-clk-bufg-pips !26_55 !26_56 27_54
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL3_I0.CLK_BUFG_IMUX31_0 origin:044-clk-bufg-pips !26_55 !26_56 !27_54
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL3_I0.CLK_BUFG_R_FBG_OUT2 origin:044-clk-bufg-pips !26_56 !27_54 26_55
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL3_I0.CLK_BUFG_R_FBG_OUT4 origin:044-clk-bufg-pips !26_56 26_55 27_54
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL3_I1.CLK_BUFG_BOT_R_CK_MUXED7 origin:044-clk-bufg-pips !26_53 !27_53 26_52
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL3_I1.CLK_BUFG_IMUX27_0 origin:044-clk-bufg-pips !26_52 !27_53 26_53
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL3_I1.CLK_BUFG_IMUX31_0 origin:044-clk-bufg-pips !26_52 !26_53 !27_53
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL3_I1.CLK_BUFG_R_FBG_OUT2 origin:044-clk-bufg-pips !26_52 !26_53 27_53
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL3_I1.CLK_BUFG_R_FBG_OUT4 origin:044-clk-bufg-pips !26_52 26_53 27_53
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL4_I0.CLK_BUFG_BOT_R_CK_MUXED8 origin:044-clk-bufg-pips !26_71 !27_70 26_72
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL4_I0.CLK_BUFG_IMUX24_1 origin:044-clk-bufg-pips !26_71 !26_72 27_70
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL4_I0.CLK_BUFG_IMUX28_1 origin:044-clk-bufg-pips !26_71 !26_72 !27_70
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL4_I0.CLK_BUFG_R_FBG_OUT3 origin:044-clk-bufg-pips !26_72 !27_70 26_71
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL4_I0.CLK_BUFG_R_FBG_OUT5 origin:044-clk-bufg-pips !26_72 26_71 27_70
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL4_I1.CLK_BUFG_BOT_R_CK_MUXED9 origin:044-clk-bufg-pips !26_69 !27_69 26_68
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL4_I1.CLK_BUFG_IMUX24_1 origin:044-clk-bufg-pips !26_68 !27_69 26_69
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL4_I1.CLK_BUFG_IMUX28_1 origin:044-clk-bufg-pips !26_68 !26_69 !27_69
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL4_I1.CLK_BUFG_R_FBG_OUT3 origin:044-clk-bufg-pips !26_68 !26_69 27_69
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL4_I1.CLK_BUFG_R_FBG_OUT5 origin:044-clk-bufg-pips !26_68 26_69 27_69
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL5_I0.CLK_BUFG_BOT_R_CK_MUXED10 origin:044-clk-bufg-pips !26_87 !27_86 26_88
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL5_I0.CLK_BUFG_IMUX25_1 origin:044-clk-bufg-pips !26_87 !26_88 27_86
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL5_I0.CLK_BUFG_IMUX29_1 origin:044-clk-bufg-pips !26_87 !26_88 !27_86
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL5_I0.CLK_BUFG_R_FBG_OUT4 origin:044-clk-bufg-pips !26_88 !27_86 26_87
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL5_I0.CLK_BUFG_R_FBG_OUT6 origin:044-clk-bufg-pips !26_88 26_87 27_86
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL5_I1.CLK_BUFG_BOT_R_CK_MUXED11 origin:044-clk-bufg-pips !26_85 !27_85 26_84
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL5_I1.CLK_BUFG_IMUX25_1 origin:044-clk-bufg-pips !26_84 !27_85 26_85
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL5_I1.CLK_BUFG_IMUX29_1 origin:044-clk-bufg-pips !26_84 !26_85 !27_85
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL5_I1.CLK_BUFG_R_FBG_OUT4 origin:044-clk-bufg-pips !26_84 !26_85 27_85
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL5_I1.CLK_BUFG_R_FBG_OUT6 origin:044-clk-bufg-pips !26_84 26_85 27_85
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL6_I0.CLK_BUFG_BOT_R_CK_MUXED12 origin:044-clk-bufg-pips !26_103 !27_102 26_104
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL6_I0.CLK_BUFG_IMUX26_1 origin:044-clk-bufg-pips !26_103 !26_104 27_102
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL6_I0.CLK_BUFG_IMUX30_1 origin:044-clk-bufg-pips !26_103 !26_104 !27_102
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL6_I0.CLK_BUFG_R_FBG_OUT5 origin:044-clk-bufg-pips !26_104 !27_102 26_103
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL6_I0.CLK_BUFG_R_FBG_OUT7 origin:044-clk-bufg-pips !26_104 26_103 27_102
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL6_I1.CLK_BUFG_BOT_R_CK_MUXED13 origin:044-clk-bufg-pips !26_101 !27_101 26_100
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL6_I1.CLK_BUFG_IMUX26_1 origin:044-clk-bufg-pips !26_100 !27_101 26_101
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL6_I1.CLK_BUFG_IMUX30_1 origin:044-clk-bufg-pips !26_100 !26_101 !27_101
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL6_I1.CLK_BUFG_R_FBG_OUT5 origin:044-clk-bufg-pips !26_100 !26_101 27_101
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL6_I1.CLK_BUFG_R_FBG_OUT7 origin:044-clk-bufg-pips !26_100 26_101 27_101
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL7_I0.CLK_BUFG_BOT_R_CK_MUXED14 origin:044-clk-bufg-pips !26_119 !27_118 26_120
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL7_I0.CLK_BUFG_IMUX27_1 origin:044-clk-bufg-pips !26_119 !26_120 27_118
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL7_I0.CLK_BUFG_IMUX31_1 origin:044-clk-bufg-pips !26_119 !26_120 !27_118
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL7_I0.CLK_BUFG_R_FBG_OUT6 origin:044-clk-bufg-pips !26_120 !27_118 26_119
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL7_I0.CLK_BUFG_R_FBG_OUT8 origin:044-clk-bufg-pips !26_120 26_119 27_118
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL7_I1.CLK_BUFG_BOT_R_CK_MUXED15 origin:044-clk-bufg-pips !26_117 !27_117 26_116
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL7_I1.CLK_BUFG_IMUX27_1 origin:044-clk-bufg-pips !26_116 !27_117 26_117
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL7_I1.CLK_BUFG_IMUX31_1 origin:044-clk-bufg-pips !26_116 !26_117 !27_117
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL7_I1.CLK_BUFG_R_FBG_OUT6 origin:044-clk-bufg-pips !26_116 !26_117 27_117
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL7_I1.CLK_BUFG_R_FBG_OUT8 origin:044-clk-bufg-pips !26_116 26_117 27_117
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL8_I0.CLK_BUFG_BOT_R_CK_MUXED16 origin:044-clk-bufg-pips !26_135 !27_134 26_136
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL8_I0.CLK_BUFG_IMUX24_2 origin:044-clk-bufg-pips !26_135 !26_136 27_134
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL8_I0.CLK_BUFG_IMUX28_2 origin:044-clk-bufg-pips !26_135 !26_136 !27_134
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL8_I0.CLK_BUFG_R_FBG_OUT7 origin:044-clk-bufg-pips !26_136 !27_134 26_135
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL8_I0.CLK_BUFG_R_FBG_OUT9 origin:044-clk-bufg-pips !26_136 26_135 27_134
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL8_I1.CLK_BUFG_BOT_R_CK_MUXED17 origin:044-clk-bufg-pips !26_133 !27_133 26_132
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL8_I1.CLK_BUFG_IMUX24_2 origin:044-clk-bufg-pips !26_132 !27_133 26_133
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL8_I1.CLK_BUFG_IMUX28_2 origin:044-clk-bufg-pips !26_132 !26_133 !27_133
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL8_I1.CLK_BUFG_R_FBG_OUT7 origin:044-clk-bufg-pips !26_132 !26_133 27_133
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL8_I1.CLK_BUFG_R_FBG_OUT9 origin:044-clk-bufg-pips !26_132 26_133 27_133
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL9_I0.CLK_BUFG_BOT_R_CK_MUXED18 origin:044-clk-bufg-pips !26_151 !27_150 26_152
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL9_I0.CLK_BUFG_IMUX25_2 origin:044-clk-bufg-pips !26_151 !26_152 27_150
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL9_I0.CLK_BUFG_IMUX29_2 origin:044-clk-bufg-pips !26_151 !26_152 !27_150
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL9_I0.CLK_BUFG_R_FBG_OUT10 origin:044-clk-bufg-pips !26_152 26_151 27_150
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL9_I0.CLK_BUFG_R_FBG_OUT8 origin:044-clk-bufg-pips !26_152 !27_150 26_151
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL9_I1.CLK_BUFG_BOT_R_CK_MUXED19 origin:044-clk-bufg-pips !26_149 !27_149 26_148
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL9_I1.CLK_BUFG_IMUX25_2 origin:044-clk-bufg-pips !26_148 !27_149 26_149
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL9_I1.CLK_BUFG_IMUX29_2 origin:044-clk-bufg-pips !26_148 !26_149 !27_149
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL9_I1.CLK_BUFG_R_FBG_OUT10 origin:044-clk-bufg-pips !26_148 26_149 27_149
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL9_I1.CLK_BUFG_R_FBG_OUT8 origin:044-clk-bufg-pips !26_148 !26_149 27_149
CLK_BUFG_BOT_R.CLK_BUFG_CK_GCLK0.CLK_BUFG_BUFGCTRL0_O origin:044-clk-bufg-pips 27_14
CLK_BUFG_BOT_R.CLK_BUFG_CK_GCLK1.CLK_BUFG_BUFGCTRL1_O origin:044-clk-bufg-pips 27_30
CLK_BUFG_BOT_R.CLK_BUFG_CK_GCLK10.CLK_BUFG_BUFGCTRL10_O origin:044-clk-bufg-pips 27_174
CLK_BUFG_BOT_R.CLK_BUFG_CK_GCLK11.CLK_BUFG_BUFGCTRL11_O origin:044-clk-bufg-pips 27_190
CLK_BUFG_BOT_R.CLK_BUFG_CK_GCLK12.CLK_BUFG_BUFGCTRL12_O origin:044-clk-bufg-pips 27_206
CLK_BUFG_BOT_R.CLK_BUFG_CK_GCLK13.CLK_BUFG_BUFGCTRL13_O origin:044-clk-bufg-pips 27_222
CLK_BUFG_BOT_R.CLK_BUFG_CK_GCLK14.CLK_BUFG_BUFGCTRL14_O origin:044-clk-bufg-pips 27_238
CLK_BUFG_BOT_R.CLK_BUFG_CK_GCLK15.CLK_BUFG_BUFGCTRL15_O origin:044-clk-bufg-pips 27_254
CLK_BUFG_BOT_R.CLK_BUFG_CK_GCLK2.CLK_BUFG_BUFGCTRL2_O origin:044-clk-bufg-pips 27_46
CLK_BUFG_BOT_R.CLK_BUFG_CK_GCLK3.CLK_BUFG_BUFGCTRL3_O origin:044-clk-bufg-pips 27_62
CLK_BUFG_BOT_R.CLK_BUFG_CK_GCLK4.CLK_BUFG_BUFGCTRL4_O origin:044-clk-bufg-pips 27_78
CLK_BUFG_BOT_R.CLK_BUFG_CK_GCLK5.CLK_BUFG_BUFGCTRL5_O origin:044-clk-bufg-pips 27_94
CLK_BUFG_BOT_R.CLK_BUFG_CK_GCLK6.CLK_BUFG_BUFGCTRL6_O origin:044-clk-bufg-pips 27_110
CLK_BUFG_BOT_R.CLK_BUFG_CK_GCLK7.CLK_BUFG_BUFGCTRL7_O origin:044-clk-bufg-pips 27_126
CLK_BUFG_BOT_R.CLK_BUFG_CK_GCLK8.CLK_BUFG_BUFGCTRL8_O origin:044-clk-bufg-pips 27_142
CLK_BUFG_BOT_R.CLK_BUFG_CK_GCLK9.CLK_BUFG_BUFGCTRL9_O origin:044-clk-bufg-pips 27_158

128
zynq7/segbits_clk_bufg_rebuf.origin_info.db Normal file
View File

@ -0,0 +1,128 @@
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK0_BOT.CLK_BUFG_REBUF_R_CK_GCLK0_TOP origin:043-clk-rebuf-pips 27_15
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK0_TOP.CLK_BUFG_REBUF_R_CK_GCLK0_BOT origin:043-clk-rebuf-pips 27_13
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK10_BOT.CLK_BUFG_REBUF_R_CK_GCLK10_TOP origin:043-clk-rebuf-pips 26_47
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK10_TOP.CLK_BUFG_REBUF_R_CK_GCLK10_BOT origin:043-clk-rebuf-pips 26_45
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK11_BOT.CLK_BUFG_REBUF_R_CK_GCLK11_TOP origin:043-clk-rebuf-pips 26_63
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK11_TOP.CLK_BUFG_REBUF_R_CK_GCLK11_BOT origin:043-clk-rebuf-pips 26_61
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK12_BOT.CLK_BUFG_REBUF_R_CK_GCLK12_TOP origin:043-clk-rebuf-pips 26_79
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK12_TOP.CLK_BUFG_REBUF_R_CK_GCLK12_BOT origin:043-clk-rebuf-pips 26_77
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK13_BOT.CLK_BUFG_REBUF_R_CK_GCLK13_TOP origin:043-clk-rebuf-pips 26_95
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK13_TOP.CLK_BUFG_REBUF_R_CK_GCLK13_BOT origin:043-clk-rebuf-pips 26_93
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK14_BOT.CLK_BUFG_REBUF_R_CK_GCLK14_TOP origin:043-clk-rebuf-pips 26_111
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK14_TOP.CLK_BUFG_REBUF_R_CK_GCLK14_BOT origin:043-clk-rebuf-pips 26_109
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK15_BOT.CLK_BUFG_REBUF_R_CK_GCLK15_TOP origin:043-clk-rebuf-pips 26_127
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK15_TOP.CLK_BUFG_REBUF_R_CK_GCLK15_BOT origin:043-clk-rebuf-pips 26_125
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK16_BOT.CLK_BUFG_REBUF_R_CK_GCLK16_TOP origin:043-clk-rebuf-pips 27_14
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK16_TOP.CLK_BUFG_REBUF_R_CK_GCLK16_BOT origin:043-clk-rebuf-pips 27_12
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK17_BOT.CLK_BUFG_REBUF_R_CK_GCLK17_TOP origin:043-clk-rebuf-pips 27_30
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK17_TOP.CLK_BUFG_REBUF_R_CK_GCLK17_BOT origin:043-clk-rebuf-pips 27_28
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK18_BOT.CLK_BUFG_REBUF_R_CK_GCLK18_TOP origin:043-clk-rebuf-pips 27_46
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK18_TOP.CLK_BUFG_REBUF_R_CK_GCLK18_BOT origin:043-clk-rebuf-pips 27_44
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK19_BOT.CLK_BUFG_REBUF_R_CK_GCLK19_TOP origin:043-clk-rebuf-pips 27_62
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK19_TOP.CLK_BUFG_REBUF_R_CK_GCLK19_BOT origin:043-clk-rebuf-pips 27_60
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK1_BOT.CLK_BUFG_REBUF_R_CK_GCLK1_TOP origin:043-clk-rebuf-pips 27_31
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK1_TOP.CLK_BUFG_REBUF_R_CK_GCLK1_BOT origin:043-clk-rebuf-pips 27_29
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK20_BOT.CLK_BUFG_REBUF_R_CK_GCLK20_TOP origin:043-clk-rebuf-pips 27_78
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK20_TOP.CLK_BUFG_REBUF_R_CK_GCLK20_BOT origin:043-clk-rebuf-pips 27_76
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK21_BOT.CLK_BUFG_REBUF_R_CK_GCLK21_TOP origin:043-clk-rebuf-pips 27_94
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK21_TOP.CLK_BUFG_REBUF_R_CK_GCLK21_BOT origin:043-clk-rebuf-pips 27_92
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK22_BOT.CLK_BUFG_REBUF_R_CK_GCLK22_TOP origin:043-clk-rebuf-pips 27_110
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK22_TOP.CLK_BUFG_REBUF_R_CK_GCLK22_BOT origin:043-clk-rebuf-pips 27_108
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK23_BOT.CLK_BUFG_REBUF_R_CK_GCLK23_TOP origin:043-clk-rebuf-pips 27_126
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK23_TOP.CLK_BUFG_REBUF_R_CK_GCLK23_BOT origin:043-clk-rebuf-pips 27_124
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK24_BOT.CLK_BUFG_REBUF_R_CK_GCLK24_TOP origin:043-clk-rebuf-pips 26_14
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK24_TOP.CLK_BUFG_REBUF_R_CK_GCLK24_BOT origin:043-clk-rebuf-pips 26_12
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK25_BOT.CLK_BUFG_REBUF_R_CK_GCLK25_TOP origin:043-clk-rebuf-pips 26_30
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK25_TOP.CLK_BUFG_REBUF_R_CK_GCLK25_BOT origin:043-clk-rebuf-pips 26_28
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK26_BOT.CLK_BUFG_REBUF_R_CK_GCLK26_TOP origin:043-clk-rebuf-pips 26_46
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK26_TOP.CLK_BUFG_REBUF_R_CK_GCLK26_BOT origin:043-clk-rebuf-pips 26_44
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK27_BOT.CLK_BUFG_REBUF_R_CK_GCLK27_TOP origin:043-clk-rebuf-pips 26_62
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK27_TOP.CLK_BUFG_REBUF_R_CK_GCLK27_BOT origin:043-clk-rebuf-pips 26_60
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK28_BOT.CLK_BUFG_REBUF_R_CK_GCLK28_TOP origin:043-clk-rebuf-pips 26_78
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK28_TOP.CLK_BUFG_REBUF_R_CK_GCLK28_BOT origin:043-clk-rebuf-pips 26_76
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK29_BOT.CLK_BUFG_REBUF_R_CK_GCLK29_TOP origin:043-clk-rebuf-pips 26_94
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK29_TOP.CLK_BUFG_REBUF_R_CK_GCLK29_BOT origin:043-clk-rebuf-pips 26_92
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK2_BOT.CLK_BUFG_REBUF_R_CK_GCLK2_TOP origin:043-clk-rebuf-pips 27_47
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK2_TOP.CLK_BUFG_REBUF_R_CK_GCLK2_BOT origin:043-clk-rebuf-pips 27_45
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK30_BOT.CLK_BUFG_REBUF_R_CK_GCLK30_TOP origin:043-clk-rebuf-pips 26_110
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK30_TOP.CLK_BUFG_REBUF_R_CK_GCLK30_BOT origin:043-clk-rebuf-pips 26_108
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK31_BOT.CLK_BUFG_REBUF_R_CK_GCLK31_TOP origin:043-clk-rebuf-pips 26_126
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK31_TOP.CLK_BUFG_REBUF_R_CK_GCLK31_BOT origin:043-clk-rebuf-pips 26_124
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK3_BOT.CLK_BUFG_REBUF_R_CK_GCLK3_TOP origin:043-clk-rebuf-pips 27_63
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK3_TOP.CLK_BUFG_REBUF_R_CK_GCLK3_BOT origin:043-clk-rebuf-pips 27_61
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK4_BOT.CLK_BUFG_REBUF_R_CK_GCLK4_TOP origin:043-clk-rebuf-pips 27_79
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK4_TOP.CLK_BUFG_REBUF_R_CK_GCLK4_BOT origin:043-clk-rebuf-pips 27_77
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK5_BOT.CLK_BUFG_REBUF_R_CK_GCLK5_TOP origin:043-clk-rebuf-pips 27_95
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK5_TOP.CLK_BUFG_REBUF_R_CK_GCLK5_BOT origin:043-clk-rebuf-pips 27_93
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK6_BOT.CLK_BUFG_REBUF_R_CK_GCLK6_TOP origin:043-clk-rebuf-pips 27_111
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK6_TOP.CLK_BUFG_REBUF_R_CK_GCLK6_BOT origin:043-clk-rebuf-pips 27_109
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK7_BOT.CLK_BUFG_REBUF_R_CK_GCLK7_TOP origin:043-clk-rebuf-pips 27_127
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK7_TOP.CLK_BUFG_REBUF_R_CK_GCLK7_BOT origin:043-clk-rebuf-pips 27_125
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK8_BOT.CLK_BUFG_REBUF_R_CK_GCLK8_TOP origin:043-clk-rebuf-pips 26_15
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK8_TOP.CLK_BUFG_REBUF_R_CK_GCLK8_BOT origin:043-clk-rebuf-pips 26_13
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK9_BOT.CLK_BUFG_REBUF_R_CK_GCLK9_TOP origin:043-clk-rebuf-pips 26_31
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK9_TOP.CLK_BUFG_REBUF_R_CK_GCLK9_BOT origin:043-clk-rebuf-pips 26_29
CLK_BUFG_REBUF.GCLK0_ENABLE_ABOVE origin:043-clk-rebuf-pips 27_03
CLK_BUFG_REBUF.GCLK0_ENABLE_BELOW origin:043-clk-rebuf-pips 27_01
CLK_BUFG_REBUF.GCLK10_ENABLE_ABOVE origin:043-clk-rebuf-pips 26_35
CLK_BUFG_REBUF.GCLK10_ENABLE_BELOW origin:043-clk-rebuf-pips 26_33
CLK_BUFG_REBUF.GCLK11_ENABLE_ABOVE origin:043-clk-rebuf-pips 26_51
CLK_BUFG_REBUF.GCLK11_ENABLE_BELOW origin:043-clk-rebuf-pips 26_49
CLK_BUFG_REBUF.GCLK12_ENABLE_ABOVE origin:043-clk-rebuf-pips 26_67
CLK_BUFG_REBUF.GCLK12_ENABLE_BELOW origin:043-clk-rebuf-pips 26_65
CLK_BUFG_REBUF.GCLK13_ENABLE_ABOVE origin:043-clk-rebuf-pips 26_83
CLK_BUFG_REBUF.GCLK13_ENABLE_BELOW origin:043-clk-rebuf-pips 26_81
CLK_BUFG_REBUF.GCLK14_ENABLE_ABOVE origin:043-clk-rebuf-pips 26_99
CLK_BUFG_REBUF.GCLK14_ENABLE_BELOW origin:043-clk-rebuf-pips 26_97
CLK_BUFG_REBUF.GCLK15_ENABLE_ABOVE origin:043-clk-rebuf-pips 26_115
CLK_BUFG_REBUF.GCLK15_ENABLE_BELOW origin:043-clk-rebuf-pips 26_113
CLK_BUFG_REBUF.GCLK16_ENABLE_ABOVE origin:043-clk-rebuf-pips 27_02
CLK_BUFG_REBUF.GCLK16_ENABLE_BELOW origin:043-clk-rebuf-pips 27_00
CLK_BUFG_REBUF.GCLK17_ENABLE_ABOVE origin:043-clk-rebuf-pips 27_18
CLK_BUFG_REBUF.GCLK17_ENABLE_BELOW origin:043-clk-rebuf-pips 27_16
CLK_BUFG_REBUF.GCLK18_ENABLE_ABOVE origin:043-clk-rebuf-pips 27_34
CLK_BUFG_REBUF.GCLK18_ENABLE_BELOW origin:043-clk-rebuf-pips 27_32
CLK_BUFG_REBUF.GCLK19_ENABLE_ABOVE origin:043-clk-rebuf-pips 27_50
CLK_BUFG_REBUF.GCLK19_ENABLE_BELOW origin:043-clk-rebuf-pips 27_48
CLK_BUFG_REBUF.GCLK1_ENABLE_ABOVE origin:043-clk-rebuf-pips 27_19
CLK_BUFG_REBUF.GCLK1_ENABLE_BELOW origin:043-clk-rebuf-pips 27_17
CLK_BUFG_REBUF.GCLK20_ENABLE_ABOVE origin:043-clk-rebuf-pips 27_66
CLK_BUFG_REBUF.GCLK20_ENABLE_BELOW origin:043-clk-rebuf-pips 27_64
CLK_BUFG_REBUF.GCLK21_ENABLE_ABOVE origin:043-clk-rebuf-pips 27_82
CLK_BUFG_REBUF.GCLK21_ENABLE_BELOW origin:043-clk-rebuf-pips 27_80
CLK_BUFG_REBUF.GCLK22_ENABLE_ABOVE origin:043-clk-rebuf-pips 27_98
CLK_BUFG_REBUF.GCLK22_ENABLE_BELOW origin:043-clk-rebuf-pips 27_96
CLK_BUFG_REBUF.GCLK23_ENABLE_ABOVE origin:043-clk-rebuf-pips 27_114
CLK_BUFG_REBUF.GCLK23_ENABLE_BELOW origin:043-clk-rebuf-pips 27_112
CLK_BUFG_REBUF.GCLK24_ENABLE_ABOVE origin:043-clk-rebuf-pips 26_02
CLK_BUFG_REBUF.GCLK24_ENABLE_BELOW origin:043-clk-rebuf-pips 26_00
CLK_BUFG_REBUF.GCLK25_ENABLE_ABOVE origin:043-clk-rebuf-pips 26_18
CLK_BUFG_REBUF.GCLK25_ENABLE_BELOW origin:043-clk-rebuf-pips 26_16
CLK_BUFG_REBUF.GCLK26_ENABLE_ABOVE origin:043-clk-rebuf-pips 26_34
CLK_BUFG_REBUF.GCLK26_ENABLE_BELOW origin:043-clk-rebuf-pips 26_32
CLK_BUFG_REBUF.GCLK27_ENABLE_ABOVE origin:043-clk-rebuf-pips 26_50
CLK_BUFG_REBUF.GCLK27_ENABLE_BELOW origin:043-clk-rebuf-pips 26_48
CLK_BUFG_REBUF.GCLK28_ENABLE_ABOVE origin:043-clk-rebuf-pips 26_66
CLK_BUFG_REBUF.GCLK28_ENABLE_BELOW origin:043-clk-rebuf-pips 26_64
CLK_BUFG_REBUF.GCLK29_ENABLE_ABOVE origin:043-clk-rebuf-pips 26_82
CLK_BUFG_REBUF.GCLK29_ENABLE_BELOW origin:043-clk-rebuf-pips 26_80
CLK_BUFG_REBUF.GCLK2_ENABLE_ABOVE origin:043-clk-rebuf-pips 27_35
CLK_BUFG_REBUF.GCLK2_ENABLE_BELOW origin:043-clk-rebuf-pips 27_33
CLK_BUFG_REBUF.GCLK30_ENABLE_ABOVE origin:043-clk-rebuf-pips 26_98
CLK_BUFG_REBUF.GCLK30_ENABLE_BELOW origin:043-clk-rebuf-pips 26_96
CLK_BUFG_REBUF.GCLK31_ENABLE_ABOVE origin:043-clk-rebuf-pips 26_114
CLK_BUFG_REBUF.GCLK31_ENABLE_BELOW origin:043-clk-rebuf-pips 26_112
CLK_BUFG_REBUF.GCLK3_ENABLE_ABOVE origin:043-clk-rebuf-pips 27_51
CLK_BUFG_REBUF.GCLK3_ENABLE_BELOW origin:043-clk-rebuf-pips 27_49
CLK_BUFG_REBUF.GCLK4_ENABLE_ABOVE origin:043-clk-rebuf-pips 27_67
CLK_BUFG_REBUF.GCLK4_ENABLE_BELOW origin:043-clk-rebuf-pips 27_65
CLK_BUFG_REBUF.GCLK5_ENABLE_ABOVE origin:043-clk-rebuf-pips 27_83
CLK_BUFG_REBUF.GCLK5_ENABLE_BELOW origin:043-clk-rebuf-pips 27_81
CLK_BUFG_REBUF.GCLK6_ENABLE_ABOVE origin:043-clk-rebuf-pips 27_99
CLK_BUFG_REBUF.GCLK6_ENABLE_BELOW origin:043-clk-rebuf-pips 27_97
CLK_BUFG_REBUF.GCLK7_ENABLE_ABOVE origin:043-clk-rebuf-pips 27_115
CLK_BUFG_REBUF.GCLK7_ENABLE_BELOW origin:043-clk-rebuf-pips 27_113
CLK_BUFG_REBUF.GCLK8_ENABLE_ABOVE origin:043-clk-rebuf-pips 26_03
CLK_BUFG_REBUF.GCLK8_ENABLE_BELOW origin:043-clk-rebuf-pips 26_01
CLK_BUFG_REBUF.GCLK9_ENABLE_ABOVE origin:043-clk-rebuf-pips 26_19
CLK_BUFG_REBUF.GCLK9_ENABLE_BELOW origin:043-clk-rebuf-pips 26_17

336
zynq7/segbits_clk_bufg_top_r.origin_info.db Normal file
View File

@ -0,0 +1,336 @@
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y0.INIT_OUT origin:042-clk-bufg-config 27_13
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y0.IN_USE origin:042-clk-bufg-config 27_00 27_15
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y0.IS_IGNORE0_INVERTED origin:042-clk-bufg-config 26_01
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y0.IS_IGNORE1_INVERTED origin:042-clk-bufg-config 27_12
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y0.PRESELECT_I1 origin:042-clk-bufg-config 26_12
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y0.ZINV_CE0 origin:042-clk-bufg-config 27_02
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y0.ZINV_CE1 origin:042-clk-bufg-config 27_11
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y0.ZINV_S0 origin:042-clk-bufg-config 27_03
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y0.ZINV_S1 origin:042-clk-bufg-config 26_11
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y0.ZPRESELECT_I0 origin:042-clk-bufg-config 26_02
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y1.INIT_OUT origin:042-clk-bufg-config 27_29
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y1.IN_USE origin:042-clk-bufg-config 27_16 27_31
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y1.IS_IGNORE0_INVERTED origin:042-clk-bufg-config 26_17
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y1.IS_IGNORE1_INVERTED origin:042-clk-bufg-config 27_28
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y1.PRESELECT_I1 origin:042-clk-bufg-config 26_28
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y1.ZINV_CE0 origin:042-clk-bufg-config 27_18
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y1.ZINV_CE1 origin:042-clk-bufg-config 27_27
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y1.ZINV_S0 origin:042-clk-bufg-config 27_19
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y1.ZINV_S1 origin:042-clk-bufg-config 26_27
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y1.ZPRESELECT_I0 origin:042-clk-bufg-config 26_18
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y10.INIT_OUT origin:042-clk-bufg-config 27_173
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y10.IN_USE origin:042-clk-bufg-config 27_160 27_175
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y10.IS_IGNORE0_INVERTED origin:042-clk-bufg-config 26_161
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y10.IS_IGNORE1_INVERTED origin:042-clk-bufg-config 27_172
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y10.PRESELECT_I1 origin:042-clk-bufg-config 26_172
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y10.ZINV_CE0 origin:042-clk-bufg-config 27_162
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y10.ZINV_CE1 origin:042-clk-bufg-config 27_171
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y10.ZINV_S0 origin:042-clk-bufg-config 27_163
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y10.ZINV_S1 origin:042-clk-bufg-config 26_171
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y10.ZPRESELECT_I0 origin:042-clk-bufg-config 26_162
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y11.INIT_OUT origin:042-clk-bufg-config 27_189
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y11.IN_USE origin:042-clk-bufg-config 27_176 27_191
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y11.IS_IGNORE0_INVERTED origin:042-clk-bufg-config 26_177
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y11.IS_IGNORE1_INVERTED origin:042-clk-bufg-config 27_188
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y11.PRESELECT_I1 origin:042-clk-bufg-config 26_188
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y11.ZINV_CE0 origin:042-clk-bufg-config 27_178
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y11.ZINV_CE1 origin:042-clk-bufg-config 27_187
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y11.ZINV_S0 origin:042-clk-bufg-config 27_179
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y11.ZINV_S1 origin:042-clk-bufg-config 26_187
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y11.ZPRESELECT_I0 origin:042-clk-bufg-config 26_178
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y12.INIT_OUT origin:042-clk-bufg-config 27_205
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y12.IN_USE origin:042-clk-bufg-config 27_192 27_207
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y12.IS_IGNORE0_INVERTED origin:042-clk-bufg-config 26_193
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y12.IS_IGNORE1_INVERTED origin:042-clk-bufg-config 27_204
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y12.PRESELECT_I1 origin:042-clk-bufg-config 26_204
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y12.ZINV_CE0 origin:042-clk-bufg-config 27_194
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y12.ZINV_CE1 origin:042-clk-bufg-config 27_203
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y12.ZINV_S0 origin:042-clk-bufg-config 27_195
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y12.ZINV_S1 origin:042-clk-bufg-config 26_203
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y12.ZPRESELECT_I0 origin:042-clk-bufg-config 26_194
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y13.INIT_OUT origin:042-clk-bufg-config 27_221
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y13.IN_USE origin:042-clk-bufg-config 27_208 27_223
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y13.IS_IGNORE0_INVERTED origin:042-clk-bufg-config 26_209
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y13.IS_IGNORE1_INVERTED origin:042-clk-bufg-config 27_220
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y13.PRESELECT_I1 origin:042-clk-bufg-config 26_220
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y13.ZINV_CE0 origin:042-clk-bufg-config 27_210
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y13.ZINV_CE1 origin:042-clk-bufg-config 27_219
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y13.ZINV_S0 origin:042-clk-bufg-config 27_211
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y13.ZINV_S1 origin:042-clk-bufg-config 26_219
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y13.ZPRESELECT_I0 origin:042-clk-bufg-config 26_210
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y14.INIT_OUT origin:042-clk-bufg-config 27_237
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y14.IN_USE origin:042-clk-bufg-config 27_224 27_239
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y14.IS_IGNORE0_INVERTED origin:042-clk-bufg-config 26_225
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y14.IS_IGNORE1_INVERTED origin:042-clk-bufg-config 27_236
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y14.PRESELECT_I1 origin:042-clk-bufg-config 26_236
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y14.ZINV_CE0 origin:042-clk-bufg-config 27_226
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y14.ZINV_CE1 origin:042-clk-bufg-config 27_235
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y14.ZINV_S0 origin:042-clk-bufg-config 27_227
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y14.ZINV_S1 origin:042-clk-bufg-config 26_235
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y14.ZPRESELECT_I0 origin:042-clk-bufg-config 26_226
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y15.INIT_OUT origin:042-clk-bufg-config 27_253
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y15.IN_USE origin:042-clk-bufg-config 27_240 27_255
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y15.IS_IGNORE0_INVERTED origin:042-clk-bufg-config 26_241
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y15.IS_IGNORE1_INVERTED origin:042-clk-bufg-config 27_252
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y15.PRESELECT_I1 origin:042-clk-bufg-config 26_252
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y15.ZINV_CE0 origin:042-clk-bufg-config 27_242
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y15.ZINV_CE1 origin:042-clk-bufg-config 27_251
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y15.ZINV_S0 origin:042-clk-bufg-config 27_243
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y15.ZINV_S1 origin:042-clk-bufg-config 26_251
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y15.ZPRESELECT_I0 origin:042-clk-bufg-config 26_242
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y2.INIT_OUT origin:042-clk-bufg-config 27_45
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y2.IN_USE origin:042-clk-bufg-config 27_32 27_47
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y2.IS_IGNORE0_INVERTED origin:042-clk-bufg-config 26_33
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y2.IS_IGNORE1_INVERTED origin:042-clk-bufg-config 27_44
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y2.PRESELECT_I1 origin:042-clk-bufg-config 26_44
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y2.ZINV_CE0 origin:042-clk-bufg-config 27_34
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y2.ZINV_CE1 origin:042-clk-bufg-config 27_43
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y2.ZINV_S0 origin:042-clk-bufg-config 27_35
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y2.ZINV_S1 origin:042-clk-bufg-config 26_43
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y2.ZPRESELECT_I0 origin:042-clk-bufg-config 26_34
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y3.INIT_OUT origin:042-clk-bufg-config 27_61
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y3.IN_USE origin:042-clk-bufg-config 27_48 27_63
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y3.IS_IGNORE0_INVERTED origin:042-clk-bufg-config 26_49
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y3.IS_IGNORE1_INVERTED origin:042-clk-bufg-config 27_60
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y3.PRESELECT_I1 origin:042-clk-bufg-config 26_60
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y3.ZINV_CE0 origin:042-clk-bufg-config 27_50
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y3.ZINV_CE1 origin:042-clk-bufg-config 27_59
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y3.ZINV_S0 origin:042-clk-bufg-config 27_51
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y3.ZINV_S1 origin:042-clk-bufg-config 26_59
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y3.ZPRESELECT_I0 origin:042-clk-bufg-config 26_50
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y4.INIT_OUT origin:042-clk-bufg-config 27_77
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y4.IN_USE origin:042-clk-bufg-config 27_64 27_79
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y4.IS_IGNORE0_INVERTED origin:042-clk-bufg-config 26_65
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y4.IS_IGNORE1_INVERTED origin:042-clk-bufg-config 27_76
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y4.PRESELECT_I1 origin:042-clk-bufg-config 26_76
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y4.ZINV_CE0 origin:042-clk-bufg-config 27_66
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y4.ZINV_CE1 origin:042-clk-bufg-config 27_75
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y4.ZINV_S0 origin:042-clk-bufg-config 27_67
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y4.ZINV_S1 origin:042-clk-bufg-config 26_75
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y4.ZPRESELECT_I0 origin:042-clk-bufg-config 26_66
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y5.INIT_OUT origin:042-clk-bufg-config 27_93
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y5.IN_USE origin:042-clk-bufg-config 27_80 27_95
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y5.IS_IGNORE0_INVERTED origin:042-clk-bufg-config 26_81
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y5.IS_IGNORE1_INVERTED origin:042-clk-bufg-config 27_92
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y5.PRESELECT_I1 origin:042-clk-bufg-config 26_92
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y5.ZINV_CE0 origin:042-clk-bufg-config 27_82
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y5.ZINV_CE1 origin:042-clk-bufg-config 27_91
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y5.ZINV_S0 origin:042-clk-bufg-config 27_83
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y5.ZINV_S1 origin:042-clk-bufg-config 26_91
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y5.ZPRESELECT_I0 origin:042-clk-bufg-config 26_82
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y6.INIT_OUT origin:042-clk-bufg-config 27_109
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y6.IN_USE origin:042-clk-bufg-config 27_111 27_96
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y6.IS_IGNORE0_INVERTED origin:042-clk-bufg-config 26_97
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y6.IS_IGNORE1_INVERTED origin:042-clk-bufg-config 27_108
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y6.PRESELECT_I1 origin:042-clk-bufg-config 26_108
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y6.ZINV_CE0 origin:042-clk-bufg-config 27_98
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y6.ZINV_CE1 origin:042-clk-bufg-config 27_107
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y6.ZINV_S0 origin:042-clk-bufg-config 27_99
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y6.ZINV_S1 origin:042-clk-bufg-config 26_107
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y6.ZPRESELECT_I0 origin:042-clk-bufg-config 26_98
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y7.INIT_OUT origin:042-clk-bufg-config 27_125
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y7.IN_USE origin:042-clk-bufg-config 27_112 27_127
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y7.IS_IGNORE0_INVERTED origin:042-clk-bufg-config 26_113
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y7.IS_IGNORE1_INVERTED origin:042-clk-bufg-config 27_124
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y7.PRESELECT_I1 origin:042-clk-bufg-config 26_124
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y7.ZINV_CE0 origin:042-clk-bufg-config 27_114
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y7.ZINV_CE1 origin:042-clk-bufg-config 27_123
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y7.ZINV_S0 origin:042-clk-bufg-config 27_115
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y7.ZINV_S1 origin:042-clk-bufg-config 26_123
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y7.ZPRESELECT_I0 origin:042-clk-bufg-config 26_114
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y8.INIT_OUT origin:042-clk-bufg-config 27_141
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y8.IN_USE origin:042-clk-bufg-config 27_128 27_143
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y8.IS_IGNORE0_INVERTED origin:042-clk-bufg-config 26_129
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y8.IS_IGNORE1_INVERTED origin:042-clk-bufg-config 27_140
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y8.PRESELECT_I1 origin:042-clk-bufg-config 26_140
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y8.ZINV_CE0 origin:042-clk-bufg-config 27_130
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y8.ZINV_CE1 origin:042-clk-bufg-config 27_139
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y8.ZINV_S0 origin:042-clk-bufg-config 27_131
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y8.ZINV_S1 origin:042-clk-bufg-config 26_139
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y8.ZPRESELECT_I0 origin:042-clk-bufg-config 26_130
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y9.INIT_OUT origin:042-clk-bufg-config 27_157
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y9.IN_USE origin:042-clk-bufg-config 27_144 27_159
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y9.IS_IGNORE0_INVERTED origin:042-clk-bufg-config 26_145
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y9.IS_IGNORE1_INVERTED origin:042-clk-bufg-config 27_156
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y9.PRESELECT_I1 origin:042-clk-bufg-config 26_156
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y9.ZINV_CE0 origin:042-clk-bufg-config 27_146
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y9.ZINV_CE1 origin:042-clk-bufg-config 27_155
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y9.ZINV_S0 origin:042-clk-bufg-config 27_147
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y9.ZINV_S1 origin:042-clk-bufg-config 26_155
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y9.ZPRESELECT_I0 origin:042-clk-bufg-config 26_146
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL0_I0.CLK_BUFG_IMUX24_0 origin:044-clk-bufg-pips !26_07 !26_08 27_06
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL0_I0.CLK_BUFG_IMUX28_0 origin:044-clk-bufg-pips !26_07 !26_08 !27_06
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL0_I0.CLK_BUFG_R_FBG_OUT1 origin:044-clk-bufg-pips !26_08 26_07 27_06
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL0_I0.CLK_BUFG_R_FBG_OUT15 origin:044-clk-bufg-pips !26_08 !27_06 26_07
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL0_I0.CLK_BUFG_TOP_R_CK_MUXED0 origin:044-clk-bufg-pips !26_07 !27_06 26_08
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL0_I1.CLK_BUFG_IMUX24_0 origin:044-clk-bufg-pips !26_04 !27_05 26_05
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL0_I1.CLK_BUFG_IMUX28_0 origin:044-clk-bufg-pips !26_04 !26_05 !27_05
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL0_I1.CLK_BUFG_R_FBG_OUT1 origin:044-clk-bufg-pips !26_04 26_05 27_05
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL0_I1.CLK_BUFG_R_FBG_OUT15 origin:044-clk-bufg-pips !26_04 !26_05 27_05
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL0_I1.CLK_BUFG_TOP_R_CK_MUXED1 origin:044-clk-bufg-pips !26_05 !27_05 26_04
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL10_I0.CLK_BUFG_IMUX26_2 origin:044-clk-bufg-pips !26_167 !26_168 27_166
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL10_I0.CLK_BUFG_IMUX30_2 origin:044-clk-bufg-pips !26_167 !26_168 !27_166
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL10_I0.CLK_BUFG_R_FBG_OUT11 origin:044-clk-bufg-pips !26_168 26_167 27_166
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL10_I0.CLK_BUFG_R_FBG_OUT9 origin:044-clk-bufg-pips !26_168 !27_166 26_167
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL10_I0.CLK_BUFG_TOP_R_CK_MUXED20 origin:044-clk-bufg-pips !26_167 !27_166 26_168
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL10_I1.CLK_BUFG_IMUX26_2 origin:044-clk-bufg-pips !26_164 !27_165 26_165
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL10_I1.CLK_BUFG_IMUX30_2 origin:044-clk-bufg-pips !26_164 !26_165 !27_165
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL10_I1.CLK_BUFG_R_FBG_OUT11 origin:044-clk-bufg-pips !26_164 26_165 27_165
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL10_I1.CLK_BUFG_R_FBG_OUT9 origin:044-clk-bufg-pips !26_164 !26_165 27_165
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL10_I1.CLK_BUFG_TOP_R_CK_MUXED21 origin:044-clk-bufg-pips !26_165 !27_165 26_164
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL11_I0.CLK_BUFG_IMUX27_2 origin:044-clk-bufg-pips !26_183 !26_184 27_182
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL11_I0.CLK_BUFG_IMUX31_2 origin:044-clk-bufg-pips !26_183 !26_184 !27_182
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL11_I0.CLK_BUFG_R_FBG_OUT10 origin:044-clk-bufg-pips !26_184 !27_182 26_183
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL11_I0.CLK_BUFG_R_FBG_OUT12 origin:044-clk-bufg-pips !26_184 26_183 27_182
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL11_I0.CLK_BUFG_TOP_R_CK_MUXED22 origin:044-clk-bufg-pips !26_183 !27_182 26_184
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL11_I1.CLK_BUFG_IMUX27_2 origin:044-clk-bufg-pips !26_180 !27_181 26_181
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL11_I1.CLK_BUFG_IMUX31_2 origin:044-clk-bufg-pips !26_180 !26_181 !27_181
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL11_I1.CLK_BUFG_R_FBG_OUT10 origin:044-clk-bufg-pips !26_180 !26_181 27_181
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL11_I1.CLK_BUFG_R_FBG_OUT12 origin:044-clk-bufg-pips !26_180 26_181 27_181
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL11_I1.CLK_BUFG_TOP_R_CK_MUXED23 origin:044-clk-bufg-pips !26_181 !27_181 26_180
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL12_I0.CLK_BUFG_IMUX24_3 origin:044-clk-bufg-pips !26_199 !26_200 27_198
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL12_I0.CLK_BUFG_IMUX28_3 origin:044-clk-bufg-pips !26_199 !26_200 !27_198
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL12_I0.CLK_BUFG_R_FBG_OUT11 origin:044-clk-bufg-pips !26_200 !27_198 26_199
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL12_I0.CLK_BUFG_R_FBG_OUT13 origin:044-clk-bufg-pips !26_200 26_199 27_198
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL12_I0.CLK_BUFG_TOP_R_CK_MUXED24 origin:044-clk-bufg-pips !26_199 !27_198 26_200
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL12_I1.CLK_BUFG_IMUX24_3 origin:044-clk-bufg-pips !26_196 !27_197 26_197
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL12_I1.CLK_BUFG_IMUX28_3 origin:044-clk-bufg-pips !26_196 !26_197 !27_197
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL12_I1.CLK_BUFG_R_FBG_OUT11 origin:044-clk-bufg-pips !26_196 !26_197 27_197
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL12_I1.CLK_BUFG_R_FBG_OUT13 origin:044-clk-bufg-pips !26_196 26_197 27_197
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL12_I1.CLK_BUFG_TOP_R_CK_MUXED25 origin:044-clk-bufg-pips !26_197 !27_197 26_196
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL13_I0.CLK_BUFG_IMUX25_3 origin:044-clk-bufg-pips !26_215 !26_216 27_214
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL13_I0.CLK_BUFG_IMUX29_3 origin:044-clk-bufg-pips !26_215 !26_216 !27_214
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL13_I0.CLK_BUFG_R_FBG_OUT12 origin:044-clk-bufg-pips !26_216 !27_214 26_215
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL13_I0.CLK_BUFG_R_FBG_OUT14 origin:044-clk-bufg-pips !26_216 26_215 27_214
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL13_I0.CLK_BUFG_TOP_R_CK_MUXED26 origin:044-clk-bufg-pips !26_215 !27_214 26_216
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL13_I1.CLK_BUFG_IMUX25_3 origin:044-clk-bufg-pips !26_212 !27_213 26_213
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL13_I1.CLK_BUFG_IMUX29_3 origin:044-clk-bufg-pips !26_212 !26_213 !27_213
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL13_I1.CLK_BUFG_R_FBG_OUT12 origin:044-clk-bufg-pips !26_212 !26_213 27_213
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL13_I1.CLK_BUFG_R_FBG_OUT14 origin:044-clk-bufg-pips !26_212 26_213 27_213
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL13_I1.CLK_BUFG_TOP_R_CK_MUXED27 origin:044-clk-bufg-pips !26_213 !27_213 26_212
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL14_I0.CLK_BUFG_IMUX26_3 origin:044-clk-bufg-pips !26_231 !26_232 27_230
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL14_I0.CLK_BUFG_IMUX30_3 origin:044-clk-bufg-pips !26_231 !26_232 !27_230
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL14_I0.CLK_BUFG_R_FBG_OUT13 origin:044-clk-bufg-pips !26_232 !27_230 26_231
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL14_I0.CLK_BUFG_R_FBG_OUT15 origin:044-clk-bufg-pips !26_232 26_231 27_230
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL14_I0.CLK_BUFG_TOP_R_CK_MUXED28 origin:044-clk-bufg-pips !26_231 !27_230 26_232
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL14_I1.CLK_BUFG_IMUX26_3 origin:044-clk-bufg-pips !26_228 !27_229 26_229
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL14_I1.CLK_BUFG_IMUX30_3 origin:044-clk-bufg-pips !26_228 !26_229 !27_229
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL14_I1.CLK_BUFG_R_FBG_OUT13 origin:044-clk-bufg-pips !26_228 !26_229 27_229
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL14_I1.CLK_BUFG_R_FBG_OUT15 origin:044-clk-bufg-pips !26_228 26_229 27_229
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL14_I1.CLK_BUFG_TOP_R_CK_MUXED29 origin:044-clk-bufg-pips !26_229 !27_229 26_228
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL15_I0.CLK_BUFG_IMUX27_3 origin:044-clk-bufg-pips !26_247 !26_248 27_246
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL15_I0.CLK_BUFG_IMUX31_3 origin:044-clk-bufg-pips !26_247 !26_248 !27_246
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL15_I0.CLK_BUFG_R_FBG_OUT0 origin:044-clk-bufg-pips !26_248 26_247 27_246
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL15_I0.CLK_BUFG_R_FBG_OUT14 origin:044-clk-bufg-pips !26_248 !27_246 26_247
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL15_I0.CLK_BUFG_TOP_R_CK_MUXED30 origin:044-clk-bufg-pips !26_247 !27_246 26_248
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL15_I1.CLK_BUFG_IMUX27_3 origin:044-clk-bufg-pips !26_244 !27_245 26_245
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL15_I1.CLK_BUFG_IMUX31_3 origin:044-clk-bufg-pips !26_244 !26_245 !27_245
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL15_I1.CLK_BUFG_R_FBG_OUT0 origin:044-clk-bufg-pips !26_244 26_245 27_245
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL15_I1.CLK_BUFG_R_FBG_OUT14 origin:044-clk-bufg-pips !26_244 !26_245 27_245
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL15_I1.CLK_BUFG_TOP_R_CK_MUXED31 origin:044-clk-bufg-pips !26_245 !27_245 26_244
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL1_I0.CLK_BUFG_IMUX25_0 origin:044-clk-bufg-pips !26_23 !26_24 27_22
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL1_I0.CLK_BUFG_IMUX29_0 origin:044-clk-bufg-pips !26_23 !26_24 !27_22
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL1_I0.CLK_BUFG_R_FBG_OUT0 origin:044-clk-bufg-pips !26_24 !27_22 26_23
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL1_I0.CLK_BUFG_R_FBG_OUT2 origin:044-clk-bufg-pips !26_24 26_23 27_22
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL1_I0.CLK_BUFG_TOP_R_CK_MUXED2 origin:044-clk-bufg-pips !26_23 !27_22 26_24
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL1_I1.CLK_BUFG_IMUX25_0 origin:044-clk-bufg-pips !26_20 !27_21 26_21
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL1_I1.CLK_BUFG_IMUX29_0 origin:044-clk-bufg-pips !26_20 !26_21 !27_21
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL1_I1.CLK_BUFG_R_FBG_OUT0 origin:044-clk-bufg-pips !26_20 !26_21 27_21
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL1_I1.CLK_BUFG_R_FBG_OUT2 origin:044-clk-bufg-pips !26_20 26_21 27_21
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL1_I1.CLK_BUFG_TOP_R_CK_MUXED3 origin:044-clk-bufg-pips !26_21 !27_21 26_20
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL2_I0.CLK_BUFG_IMUX26_0 origin:044-clk-bufg-pips !26_39 !26_40 27_38
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL2_I0.CLK_BUFG_IMUX30_0 origin:044-clk-bufg-pips !26_39 !26_40 !27_38
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL2_I0.CLK_BUFG_R_FBG_OUT1 origin:044-clk-bufg-pips !26_40 !27_38 26_39
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL2_I0.CLK_BUFG_R_FBG_OUT3 origin:044-clk-bufg-pips !26_40 26_39 27_38
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL2_I0.CLK_BUFG_TOP_R_CK_MUXED4 origin:044-clk-bufg-pips !26_39 !27_38 26_40
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL2_I1.CLK_BUFG_IMUX26_0 origin:044-clk-bufg-pips !26_36 !27_37 26_37
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL2_I1.CLK_BUFG_IMUX30_0 origin:044-clk-bufg-pips !26_36 !26_37 !27_37
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL2_I1.CLK_BUFG_R_FBG_OUT1 origin:044-clk-bufg-pips !26_36 !26_37 27_37
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL2_I1.CLK_BUFG_R_FBG_OUT3 origin:044-clk-bufg-pips !26_36 26_37 27_37
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL2_I1.CLK_BUFG_TOP_R_CK_MUXED5 origin:044-clk-bufg-pips !26_37 !27_37 26_36
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL3_I0.CLK_BUFG_IMUX27_0 origin:044-clk-bufg-pips !26_55 !26_56 27_54
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL3_I0.CLK_BUFG_IMUX31_0 origin:044-clk-bufg-pips !26_55 !26_56 !27_54
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL3_I0.CLK_BUFG_R_FBG_OUT2 origin:044-clk-bufg-pips !26_56 !27_54 26_55
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL3_I0.CLK_BUFG_R_FBG_OUT4 origin:044-clk-bufg-pips !26_56 26_55 27_54
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL3_I0.CLK_BUFG_TOP_R_CK_MUXED6 origin:044-clk-bufg-pips !26_55 !27_54 26_56
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL3_I1.CLK_BUFG_IMUX27_0 origin:044-clk-bufg-pips !26_52 !27_53 26_53
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL3_I1.CLK_BUFG_IMUX31_0 origin:044-clk-bufg-pips !26_52 !26_53 !27_53
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL3_I1.CLK_BUFG_R_FBG_OUT2 origin:044-clk-bufg-pips !26_52 !26_53 27_53
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL3_I1.CLK_BUFG_R_FBG_OUT4 origin:044-clk-bufg-pips !26_52 26_53 27_53
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL3_I1.CLK_BUFG_TOP_R_CK_MUXED7 origin:044-clk-bufg-pips !26_53 !27_53 26_52
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL4_I0.CLK_BUFG_IMUX24_1 origin:044-clk-bufg-pips !26_71 !26_72 27_70
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL4_I0.CLK_BUFG_IMUX28_1 origin:044-clk-bufg-pips !26_71 !26_72 !27_70
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL4_I0.CLK_BUFG_R_FBG_OUT3 origin:044-clk-bufg-pips !26_72 !27_70 26_71
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL4_I0.CLK_BUFG_R_FBG_OUT5 origin:044-clk-bufg-pips !26_72 26_71 27_70
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL4_I0.CLK_BUFG_TOP_R_CK_MUXED8 origin:044-clk-bufg-pips !26_71 !27_70 26_72
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL4_I1.CLK_BUFG_IMUX24_1 origin:044-clk-bufg-pips !26_68 !27_69 26_69
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL4_I1.CLK_BUFG_IMUX28_1 origin:044-clk-bufg-pips !26_68 !26_69 !27_69
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL4_I1.CLK_BUFG_R_FBG_OUT3 origin:044-clk-bufg-pips !26_68 !26_69 27_69
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL4_I1.CLK_BUFG_R_FBG_OUT5 origin:044-clk-bufg-pips !26_68 26_69 27_69
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL4_I1.CLK_BUFG_TOP_R_CK_MUXED9 origin:044-clk-bufg-pips !26_69 !27_69 26_68
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL5_I0.CLK_BUFG_IMUX25_1 origin:044-clk-bufg-pips !26_87 !26_88 27_86
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL5_I0.CLK_BUFG_IMUX29_1 origin:044-clk-bufg-pips !26_87 !26_88 !27_86
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL5_I0.CLK_BUFG_R_FBG_OUT4 origin:044-clk-bufg-pips !26_88 !27_86 26_87
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL5_I0.CLK_BUFG_R_FBG_OUT6 origin:044-clk-bufg-pips !26_88 26_87 27_86
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL5_I0.CLK_BUFG_TOP_R_CK_MUXED10 origin:044-clk-bufg-pips !26_87 !27_86 26_88
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL5_I1.CLK_BUFG_IMUX25_1 origin:044-clk-bufg-pips !26_84 !27_85 26_85
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL5_I1.CLK_BUFG_IMUX29_1 origin:044-clk-bufg-pips !26_84 !26_85 !27_85
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL5_I1.CLK_BUFG_R_FBG_OUT4 origin:044-clk-bufg-pips !26_84 !26_85 27_85
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL5_I1.CLK_BUFG_R_FBG_OUT6 origin:044-clk-bufg-pips !26_84 26_85 27_85
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL5_I1.CLK_BUFG_TOP_R_CK_MUXED11 origin:044-clk-bufg-pips !26_85 !27_85 26_84
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL6_I0.CLK_BUFG_IMUX26_1 origin:044-clk-bufg-pips !26_103 !26_104 27_102
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL6_I0.CLK_BUFG_IMUX30_1 origin:044-clk-bufg-pips !26_103 !26_104 !27_102
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL6_I0.CLK_BUFG_R_FBG_OUT5 origin:044-clk-bufg-pips !26_104 !27_102 26_103
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL6_I0.CLK_BUFG_R_FBG_OUT7 origin:044-clk-bufg-pips !26_104 26_103 27_102
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL6_I0.CLK_BUFG_TOP_R_CK_MUXED12 origin:044-clk-bufg-pips !26_103 !27_102 26_104
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL6_I1.CLK_BUFG_IMUX26_1 origin:044-clk-bufg-pips !26_100 !27_101 26_101
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL6_I1.CLK_BUFG_IMUX30_1 origin:044-clk-bufg-pips !26_100 !26_101 !27_101
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL6_I1.CLK_BUFG_R_FBG_OUT5 origin:044-clk-bufg-pips !26_100 !26_101 27_101
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL6_I1.CLK_BUFG_R_FBG_OUT7 origin:044-clk-bufg-pips !26_100 26_101 27_101
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL6_I1.CLK_BUFG_TOP_R_CK_MUXED13 origin:044-clk-bufg-pips !26_101 !27_101 26_100
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL7_I0.CLK_BUFG_IMUX27_1 origin:044-clk-bufg-pips !26_119 !26_120 27_118
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL7_I0.CLK_BUFG_IMUX31_1 origin:044-clk-bufg-pips !26_119 !26_120 !27_118
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL7_I0.CLK_BUFG_R_FBG_OUT6 origin:044-clk-bufg-pips !26_120 !27_118 26_119
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL7_I0.CLK_BUFG_R_FBG_OUT8 origin:044-clk-bufg-pips !26_120 26_119 27_118
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL7_I0.CLK_BUFG_TOP_R_CK_MUXED14 origin:044-clk-bufg-pips !26_119 !27_118 26_120
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL7_I1.CLK_BUFG_IMUX27_1 origin:044-clk-bufg-pips !26_116 !27_117 26_117
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL7_I1.CLK_BUFG_IMUX31_1 origin:044-clk-bufg-pips !26_116 !26_117 !27_117
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL7_I1.CLK_BUFG_R_FBG_OUT6 origin:044-clk-bufg-pips !26_116 !26_117 27_117
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL7_I1.CLK_BUFG_R_FBG_OUT8 origin:044-clk-bufg-pips !26_116 26_117 27_117
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL7_I1.CLK_BUFG_TOP_R_CK_MUXED15 origin:044-clk-bufg-pips !26_117 !27_117 26_116
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL8_I0.CLK_BUFG_IMUX24_2 origin:044-clk-bufg-pips !26_135 !26_136 27_134
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL8_I0.CLK_BUFG_IMUX28_2 origin:044-clk-bufg-pips !26_135 !26_136 !27_134
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL8_I0.CLK_BUFG_R_FBG_OUT7 origin:044-clk-bufg-pips !26_136 !27_134 26_135
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL8_I0.CLK_BUFG_R_FBG_OUT9 origin:044-clk-bufg-pips !26_136 26_135 27_134
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL8_I0.CLK_BUFG_TOP_R_CK_MUXED16 origin:044-clk-bufg-pips !26_135 !27_134 26_136
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL8_I1.CLK_BUFG_IMUX24_2 origin:044-clk-bufg-pips !26_132 !27_133 26_133
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL8_I1.CLK_BUFG_IMUX28_2 origin:044-clk-bufg-pips !26_132 !26_133 !27_133
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL8_I1.CLK_BUFG_R_FBG_OUT7 origin:044-clk-bufg-pips !26_132 !26_133 27_133
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL8_I1.CLK_BUFG_R_FBG_OUT9 origin:044-clk-bufg-pips !26_132 26_133 27_133
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL8_I1.CLK_BUFG_TOP_R_CK_MUXED17 origin:044-clk-bufg-pips !26_133 !27_133 26_132
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL9_I0.CLK_BUFG_IMUX25_2 origin:044-clk-bufg-pips !26_151 !26_152 27_150
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL9_I0.CLK_BUFG_IMUX29_2 origin:044-clk-bufg-pips !26_151 !26_152 !27_150
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL9_I0.CLK_BUFG_R_FBG_OUT10 origin:044-clk-bufg-pips !26_152 26_151 27_150
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL9_I0.CLK_BUFG_R_FBG_OUT8 origin:044-clk-bufg-pips !26_152 !27_150 26_151
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL9_I0.CLK_BUFG_TOP_R_CK_MUXED18 origin:044-clk-bufg-pips !26_151 !27_150 26_152
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL9_I1.CLK_BUFG_IMUX25_2 origin:044-clk-bufg-pips !26_148 !27_149 26_149
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL9_I1.CLK_BUFG_IMUX29_2 origin:044-clk-bufg-pips !26_148 !26_149 !27_149
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL9_I1.CLK_BUFG_R_FBG_OUT10 origin:044-clk-bufg-pips !26_148 26_149 27_149
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL9_I1.CLK_BUFG_R_FBG_OUT8 origin:044-clk-bufg-pips !26_148 !26_149 27_149
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL9_I1.CLK_BUFG_TOP_R_CK_MUXED19 origin:044-clk-bufg-pips !26_149 !27_149 26_148
CLK_BUFG_TOP_R.CLK_BUFG_CK_GCLK16.CLK_BUFG_BUFGCTRL0_O origin:044-clk-bufg-pips 27_14
CLK_BUFG_TOP_R.CLK_BUFG_CK_GCLK17.CLK_BUFG_BUFGCTRL1_O origin:044-clk-bufg-pips 27_30
CLK_BUFG_TOP_R.CLK_BUFG_CK_GCLK18.CLK_BUFG_BUFGCTRL2_O origin:044-clk-bufg-pips 27_46
CLK_BUFG_TOP_R.CLK_BUFG_CK_GCLK19.CLK_BUFG_BUFGCTRL3_O origin:044-clk-bufg-pips 27_62
CLK_BUFG_TOP_R.CLK_BUFG_CK_GCLK20.CLK_BUFG_BUFGCTRL4_O origin:044-clk-bufg-pips 27_78
CLK_BUFG_TOP_R.CLK_BUFG_CK_GCLK21.CLK_BUFG_BUFGCTRL5_O origin:044-clk-bufg-pips 27_94
CLK_BUFG_TOP_R.CLK_BUFG_CK_GCLK22.CLK_BUFG_BUFGCTRL6_O origin:044-clk-bufg-pips 27_110
CLK_BUFG_TOP_R.CLK_BUFG_CK_GCLK23.CLK_BUFG_BUFGCTRL7_O origin:044-clk-bufg-pips 27_126
CLK_BUFG_TOP_R.CLK_BUFG_CK_GCLK24.CLK_BUFG_BUFGCTRL8_O origin:044-clk-bufg-pips 27_142
CLK_BUFG_TOP_R.CLK_BUFG_CK_GCLK25.CLK_BUFG_BUFGCTRL9_O origin:044-clk-bufg-pips 27_158
CLK_BUFG_TOP_R.CLK_BUFG_CK_GCLK26.CLK_BUFG_BUFGCTRL10_O origin:044-clk-bufg-pips 27_174
CLK_BUFG_TOP_R.CLK_BUFG_CK_GCLK27.CLK_BUFG_BUFGCTRL11_O origin:044-clk-bufg-pips 27_190
CLK_BUFG_TOP_R.CLK_BUFG_CK_GCLK28.CLK_BUFG_BUFGCTRL12_O origin:044-clk-bufg-pips 27_206
CLK_BUFG_TOP_R.CLK_BUFG_CK_GCLK29.CLK_BUFG_BUFGCTRL13_O origin:044-clk-bufg-pips 27_222
CLK_BUFG_TOP_R.CLK_BUFG_CK_GCLK30.CLK_BUFG_BUFGCTRL14_O origin:044-clk-bufg-pips 27_238
CLK_BUFG_TOP_R.CLK_BUFG_CK_GCLK31.CLK_BUFG_BUFGCTRL15_O origin:044-clk-bufg-pips 27_254

96
zynq7/segbits_clk_hrow_bot_r.origin_info.db Normal file
View File

@ -0,0 +1,96 @@
CLK_HROW_BOT_R.BUFHCE.BUFHCE_X0Y0.CE_TYPE.ASYNC origin:040-clk-hrow-config 27_214
CLK_HROW_BOT_R.BUFHCE.BUFHCE_X0Y0.INIT_OUT origin:040-clk-hrow-config 26_211
CLK_HROW_BOT_R.BUFHCE.BUFHCE_X0Y0.IN_USE origin:040-clk-hrow-config 27_215
CLK_HROW_BOT_R.BUFHCE.BUFHCE_X0Y0.ZINV_CE origin:040-clk-hrow-config 27_211
CLK_HROW_BOT_R.BUFHCE.BUFHCE_X0Y1.CE_TYPE.ASYNC origin:040-clk-hrow-config 29_214
CLK_HROW_BOT_R.BUFHCE.BUFHCE_X0Y1.INIT_OUT origin:040-clk-hrow-config 28_211
CLK_HROW_BOT_R.BUFHCE.BUFHCE_X0Y1.IN_USE origin:040-clk-hrow-config 29_215
CLK_HROW_BOT_R.BUFHCE.BUFHCE_X0Y1.ZINV_CE origin:040-clk-hrow-config 29_211
CLK_HROW_BOT_R.BUFHCE.BUFHCE_X0Y10.CE_TYPE.ASYNC origin:040-clk-hrow-config 27_326
CLK_HROW_BOT_R.BUFHCE.BUFHCE_X0Y10.INIT_OUT origin:040-clk-hrow-config 26_323
CLK_HROW_BOT_R.BUFHCE.BUFHCE_X0Y10.IN_USE origin:040-clk-hrow-config 27_327
CLK_HROW_BOT_R.BUFHCE.BUFHCE_X0Y10.ZINV_CE origin:040-clk-hrow-config 27_323
CLK_HROW_BOT_R.BUFHCE.BUFHCE_X0Y11.CE_TYPE.ASYNC origin:040-clk-hrow-config 29_326
CLK_HROW_BOT_R.BUFHCE.BUFHCE_X0Y11.INIT_OUT origin:040-clk-hrow-config 28_323
CLK_HROW_BOT_R.BUFHCE.BUFHCE_X0Y11.IN_USE origin:040-clk-hrow-config 29_327
CLK_HROW_BOT_R.BUFHCE.BUFHCE_X0Y11.ZINV_CE origin:040-clk-hrow-config 29_323
CLK_HROW_BOT_R.BUFHCE.BUFHCE_X0Y2.CE_TYPE.ASYNC origin:040-clk-hrow-config 27_230
CLK_HROW_BOT_R.BUFHCE.BUFHCE_X0Y2.INIT_OUT origin:040-clk-hrow-config 26_227
CLK_HROW_BOT_R.BUFHCE.BUFHCE_X0Y2.IN_USE origin:040-clk-hrow-config 27_231
CLK_HROW_BOT_R.BUFHCE.BUFHCE_X0Y2.ZINV_CE origin:040-clk-hrow-config 27_227
CLK_HROW_BOT_R.BUFHCE.BUFHCE_X0Y3.CE_TYPE.ASYNC origin:040-clk-hrow-config 29_230
CLK_HROW_BOT_R.BUFHCE.BUFHCE_X0Y3.INIT_OUT origin:040-clk-hrow-config 28_227
CLK_HROW_BOT_R.BUFHCE.BUFHCE_X0Y3.IN_USE origin:040-clk-hrow-config 29_231
CLK_HROW_BOT_R.BUFHCE.BUFHCE_X0Y3.ZINV_CE origin:040-clk-hrow-config 29_227
CLK_HROW_BOT_R.BUFHCE.BUFHCE_X0Y4.CE_TYPE.ASYNC origin:040-clk-hrow-config 27_246
CLK_HROW_BOT_R.BUFHCE.BUFHCE_X0Y4.INIT_OUT origin:040-clk-hrow-config 26_243
CLK_HROW_BOT_R.BUFHCE.BUFHCE_X0Y4.IN_USE origin:040-clk-hrow-config 27_247
CLK_HROW_BOT_R.BUFHCE.BUFHCE_X0Y4.ZINV_CE origin:040-clk-hrow-config 27_243
CLK_HROW_BOT_R.BUFHCE.BUFHCE_X0Y5.CE_TYPE.ASYNC origin:040-clk-hrow-config 29_246
CLK_HROW_BOT_R.BUFHCE.BUFHCE_X0Y5.INIT_OUT origin:040-clk-hrow-config 28_243
CLK_HROW_BOT_R.BUFHCE.BUFHCE_X0Y5.IN_USE origin:040-clk-hrow-config 29_247
CLK_HROW_BOT_R.BUFHCE.BUFHCE_X0Y5.ZINV_CE origin:040-clk-hrow-config 27_359 29_243
CLK_HROW_BOT_R.BUFHCE.BUFHCE_X0Y6.CE_TYPE.ASYNC origin:040-clk-hrow-config 27_294
CLK_HROW_BOT_R.BUFHCE.BUFHCE_X0Y6.INIT_OUT origin:040-clk-hrow-config 26_291
CLK_HROW_BOT_R.BUFHCE.BUFHCE_X0Y6.IN_USE origin:040-clk-hrow-config 27_295
CLK_HROW_BOT_R.BUFHCE.BUFHCE_X0Y6.ZINV_CE origin:040-clk-hrow-config 27_291
CLK_HROW_BOT_R.BUFHCE.BUFHCE_X0Y7.CE_TYPE.ASYNC origin:040-clk-hrow-config 29_294
CLK_HROW_BOT_R.BUFHCE.BUFHCE_X0Y7.INIT_OUT origin:040-clk-hrow-config 28_291
CLK_HROW_BOT_R.BUFHCE.BUFHCE_X0Y7.IN_USE origin:040-clk-hrow-config 29_295
CLK_HROW_BOT_R.BUFHCE.BUFHCE_X0Y7.ZINV_CE origin:040-clk-hrow-config 29_291
CLK_HROW_BOT_R.BUFHCE.BUFHCE_X0Y8.CE_TYPE.ASYNC origin:040-clk-hrow-config 27_310
CLK_HROW_BOT_R.BUFHCE.BUFHCE_X0Y8.INIT_OUT origin:040-clk-hrow-config 26_307
CLK_HROW_BOT_R.BUFHCE.BUFHCE_X0Y8.IN_USE origin:040-clk-hrow-config 27_311
CLK_HROW_BOT_R.BUFHCE.BUFHCE_X0Y8.ZINV_CE origin:040-clk-hrow-config 27_307
CLK_HROW_BOT_R.BUFHCE.BUFHCE_X0Y9.CE_TYPE.ASYNC origin:040-clk-hrow-config 29_310
CLK_HROW_BOT_R.BUFHCE.BUFHCE_X0Y9.INIT_OUT origin:040-clk-hrow-config 28_307
CLK_HROW_BOT_R.BUFHCE.BUFHCE_X0Y9.IN_USE origin:040-clk-hrow-config 29_311
CLK_HROW_BOT_R.BUFHCE.BUFHCE_X0Y9.ZINV_CE origin:040-clk-hrow-config 29_307
CLK_HROW_BOT_R.BUFHCE.BUFHCE_X1Y0.CE_TYPE.ASYNC origin:040-clk-hrow-config 27_166
CLK_HROW_BOT_R.BUFHCE.BUFHCE_X1Y0.INIT_OUT origin:040-clk-hrow-config 26_163
CLK_HROW_BOT_R.BUFHCE.BUFHCE_X1Y0.IN_USE origin:040-clk-hrow-config 27_167
CLK_HROW_BOT_R.BUFHCE.BUFHCE_X1Y0.ZINV_CE origin:040-clk-hrow-config 27_163
CLK_HROW_BOT_R.BUFHCE.BUFHCE_X1Y1.CE_TYPE.ASYNC origin:040-clk-hrow-config 29_166
CLK_HROW_BOT_R.BUFHCE.BUFHCE_X1Y1.INIT_OUT origin:040-clk-hrow-config 28_163
CLK_HROW_BOT_R.BUFHCE.BUFHCE_X1Y1.IN_USE origin:040-clk-hrow-config 29_167
CLK_HROW_BOT_R.BUFHCE.BUFHCE_X1Y1.ZINV_CE origin:040-clk-hrow-config 29_163
CLK_HROW_BOT_R.BUFHCE.BUFHCE_X1Y10.CE_TYPE.ASYNC origin:040-clk-hrow-config 27_374
CLK_HROW_BOT_R.BUFHCE.BUFHCE_X1Y10.INIT_OUT origin:040-clk-hrow-config 26_371
CLK_HROW_BOT_R.BUFHCE.BUFHCE_X1Y10.IN_USE origin:040-clk-hrow-config 27_375
CLK_HROW_BOT_R.BUFHCE.BUFHCE_X1Y10.ZINV_CE origin:040-clk-hrow-config 27_371
CLK_HROW_BOT_R.BUFHCE.BUFHCE_X1Y11.CE_TYPE.ASYNC origin:040-clk-hrow-config 29_374
CLK_HROW_BOT_R.BUFHCE.BUFHCE_X1Y11.INIT_OUT origin:040-clk-hrow-config 28_371
CLK_HROW_BOT_R.BUFHCE.BUFHCE_X1Y11.IN_USE origin:040-clk-hrow-config 29_375
CLK_HROW_BOT_R.BUFHCE.BUFHCE_X1Y11.ZINV_CE origin:040-clk-hrow-config 29_371
CLK_HROW_BOT_R.BUFHCE.BUFHCE_X1Y2.CE_TYPE.ASYNC origin:040-clk-hrow-config 27_182
CLK_HROW_BOT_R.BUFHCE.BUFHCE_X1Y2.INIT_OUT origin:040-clk-hrow-config 26_179
CLK_HROW_BOT_R.BUFHCE.BUFHCE_X1Y2.IN_USE origin:040-clk-hrow-config 27_183
CLK_HROW_BOT_R.BUFHCE.BUFHCE_X1Y2.ZINV_CE origin:040-clk-hrow-config 27_179
CLK_HROW_BOT_R.BUFHCE.BUFHCE_X1Y3.CE_TYPE.ASYNC origin:040-clk-hrow-config 29_182
CLK_HROW_BOT_R.BUFHCE.BUFHCE_X1Y3.INIT_OUT origin:040-clk-hrow-config 28_179
CLK_HROW_BOT_R.BUFHCE.BUFHCE_X1Y3.IN_USE origin:040-clk-hrow-config 29_183
CLK_HROW_BOT_R.BUFHCE.BUFHCE_X1Y3.ZINV_CE origin:040-clk-hrow-config 29_179
CLK_HROW_BOT_R.BUFHCE.BUFHCE_X1Y4.CE_TYPE.ASYNC origin:040-clk-hrow-config 27_198
CLK_HROW_BOT_R.BUFHCE.BUFHCE_X1Y4.INIT_OUT origin:040-clk-hrow-config 26_195
CLK_HROW_BOT_R.BUFHCE.BUFHCE_X1Y4.IN_USE origin:040-clk-hrow-config 27_199
CLK_HROW_BOT_R.BUFHCE.BUFHCE_X1Y4.ZINV_CE origin:040-clk-hrow-config 27_195
CLK_HROW_BOT_R.BUFHCE.BUFHCE_X1Y5.CE_TYPE.ASYNC origin:040-clk-hrow-config 29_198
CLK_HROW_BOT_R.BUFHCE.BUFHCE_X1Y5.INIT_OUT origin:040-clk-hrow-config 28_195
CLK_HROW_BOT_R.BUFHCE.BUFHCE_X1Y5.IN_USE origin:040-clk-hrow-config 29_199
CLK_HROW_BOT_R.BUFHCE.BUFHCE_X1Y5.ZINV_CE origin:040-clk-hrow-config 29_195
CLK_HROW_BOT_R.BUFHCE.BUFHCE_X1Y6.CE_TYPE.ASYNC origin:040-clk-hrow-config 27_342
CLK_HROW_BOT_R.BUFHCE.BUFHCE_X1Y6.INIT_OUT origin:040-clk-hrow-config 26_339
CLK_HROW_BOT_R.BUFHCE.BUFHCE_X1Y6.IN_USE origin:040-clk-hrow-config 27_343
CLK_HROW_BOT_R.BUFHCE.BUFHCE_X1Y6.ZINV_CE origin:040-clk-hrow-config 27_339
CLK_HROW_BOT_R.BUFHCE.BUFHCE_X1Y7.CE_TYPE.ASYNC origin:040-clk-hrow-config 29_342
CLK_HROW_BOT_R.BUFHCE.BUFHCE_X1Y7.INIT_OUT origin:040-clk-hrow-config 28_339
CLK_HROW_BOT_R.BUFHCE.BUFHCE_X1Y7.IN_USE origin:040-clk-hrow-config 29_343
CLK_HROW_BOT_R.BUFHCE.BUFHCE_X1Y7.ZINV_CE origin:040-clk-hrow-config 29_339
CLK_HROW_BOT_R.BUFHCE.BUFHCE_X1Y8.CE_TYPE.ASYNC origin:040-clk-hrow-config 27_358
CLK_HROW_BOT_R.BUFHCE.BUFHCE_X1Y8.INIT_OUT origin:040-clk-hrow-config 26_355
CLK_HROW_BOT_R.BUFHCE.BUFHCE_X1Y8.IN_USE origin:040-clk-hrow-config 27_359
CLK_HROW_BOT_R.BUFHCE.BUFHCE_X1Y8.ZINV_CE origin:040-clk-hrow-config 27_355
CLK_HROW_BOT_R.BUFHCE.BUFHCE_X1Y9.CE_TYPE.ASYNC origin:040-clk-hrow-config 29_358
CLK_HROW_BOT_R.BUFHCE.BUFHCE_X1Y9.INIT_OUT origin:040-clk-hrow-config 28_355
CLK_HROW_BOT_R.BUFHCE.BUFHCE_X1Y9.IN_USE origin:040-clk-hrow-config 29_359
CLK_HROW_BOT_R.BUFHCE.BUFHCE_X1Y9.ZINV_CE origin:040-clk-hrow-config 29_355

96
zynq7/segbits_clk_hrow_top_r.origin_info.db Normal file
View File

@ -0,0 +1,96 @@
CLK_HROW_TOP_R.BUFHCE.BUFHCE_X0Y0.CE_TYPE.ASYNC origin:040-clk-hrow-config 27_214
CLK_HROW_TOP_R.BUFHCE.BUFHCE_X0Y0.INIT_OUT origin:040-clk-hrow-config 26_211
CLK_HROW_TOP_R.BUFHCE.BUFHCE_X0Y0.IN_USE origin:040-clk-hrow-config 27_215
CLK_HROW_TOP_R.BUFHCE.BUFHCE_X0Y0.ZINV_CE origin:040-clk-hrow-config 27_211
CLK_HROW_TOP_R.BUFHCE.BUFHCE_X0Y1.CE_TYPE.ASYNC origin:040-clk-hrow-config 29_214
CLK_HROW_TOP_R.BUFHCE.BUFHCE_X0Y1.INIT_OUT origin:040-clk-hrow-config 28_211
CLK_HROW_TOP_R.BUFHCE.BUFHCE_X0Y1.IN_USE origin:040-clk-hrow-config 29_215
CLK_HROW_TOP_R.BUFHCE.BUFHCE_X0Y1.ZINV_CE origin:040-clk-hrow-config 29_211
CLK_HROW_TOP_R.BUFHCE.BUFHCE_X0Y10.CE_TYPE.ASYNC origin:040-clk-hrow-config 27_326
CLK_HROW_TOP_R.BUFHCE.BUFHCE_X0Y10.INIT_OUT origin:040-clk-hrow-config 26_323
CLK_HROW_TOP_R.BUFHCE.BUFHCE_X0Y10.IN_USE origin:040-clk-hrow-config 27_327
CLK_HROW_TOP_R.BUFHCE.BUFHCE_X0Y10.ZINV_CE origin:040-clk-hrow-config 27_323
CLK_HROW_TOP_R.BUFHCE.BUFHCE_X0Y11.CE_TYPE.ASYNC origin:040-clk-hrow-config 29_326
CLK_HROW_TOP_R.BUFHCE.BUFHCE_X0Y11.INIT_OUT origin:040-clk-hrow-config 28_323
CLK_HROW_TOP_R.BUFHCE.BUFHCE_X0Y11.IN_USE origin:040-clk-hrow-config 29_327
CLK_HROW_TOP_R.BUFHCE.BUFHCE_X0Y11.ZINV_CE origin:040-clk-hrow-config 29_323
CLK_HROW_TOP_R.BUFHCE.BUFHCE_X0Y2.CE_TYPE.ASYNC origin:040-clk-hrow-config 27_230
CLK_HROW_TOP_R.BUFHCE.BUFHCE_X0Y2.INIT_OUT origin:040-clk-hrow-config 26_227
CLK_HROW_TOP_R.BUFHCE.BUFHCE_X0Y2.IN_USE origin:040-clk-hrow-config 27_231
CLK_HROW_TOP_R.BUFHCE.BUFHCE_X0Y2.ZINV_CE origin:040-clk-hrow-config 27_227
CLK_HROW_TOP_R.BUFHCE.BUFHCE_X0Y3.CE_TYPE.ASYNC origin:040-clk-hrow-config 29_230
CLK_HROW_TOP_R.BUFHCE.BUFHCE_X0Y3.INIT_OUT origin:040-clk-hrow-config 28_227
CLK_HROW_TOP_R.BUFHCE.BUFHCE_X0Y3.IN_USE origin:040-clk-hrow-config 29_231
CLK_HROW_TOP_R.BUFHCE.BUFHCE_X0Y3.ZINV_CE origin:040-clk-hrow-config 29_227
CLK_HROW_TOP_R.BUFHCE.BUFHCE_X0Y4.CE_TYPE.ASYNC origin:040-clk-hrow-config 27_246
CLK_HROW_TOP_R.BUFHCE.BUFHCE_X0Y4.INIT_OUT origin:040-clk-hrow-config 26_243
CLK_HROW_TOP_R.BUFHCE.BUFHCE_X0Y4.IN_USE origin:040-clk-hrow-config 27_247
CLK_HROW_TOP_R.BUFHCE.BUFHCE_X0Y4.ZINV_CE origin:040-clk-hrow-config 27_243
CLK_HROW_TOP_R.BUFHCE.BUFHCE_X0Y5.CE_TYPE.ASYNC origin:040-clk-hrow-config 29_246
CLK_HROW_TOP_R.BUFHCE.BUFHCE_X0Y5.INIT_OUT origin:040-clk-hrow-config 28_243
CLK_HROW_TOP_R.BUFHCE.BUFHCE_X0Y5.IN_USE origin:040-clk-hrow-config 29_247
CLK_HROW_TOP_R.BUFHCE.BUFHCE_X0Y5.ZINV_CE origin:040-clk-hrow-config 27_359 29_243
CLK_HROW_TOP_R.BUFHCE.BUFHCE_X0Y6.CE_TYPE.ASYNC origin:040-clk-hrow-config 27_294
CLK_HROW_TOP_R.BUFHCE.BUFHCE_X0Y6.INIT_OUT origin:040-clk-hrow-config 26_291
CLK_HROW_TOP_R.BUFHCE.BUFHCE_X0Y6.IN_USE origin:040-clk-hrow-config 27_295
CLK_HROW_TOP_R.BUFHCE.BUFHCE_X0Y6.ZINV_CE origin:040-clk-hrow-config 27_291
CLK_HROW_TOP_R.BUFHCE.BUFHCE_X0Y7.CE_TYPE.ASYNC origin:040-clk-hrow-config 29_294
CLK_HROW_TOP_R.BUFHCE.BUFHCE_X0Y7.INIT_OUT origin:040-clk-hrow-config 28_291
CLK_HROW_TOP_R.BUFHCE.BUFHCE_X0Y7.IN_USE origin:040-clk-hrow-config 29_295
CLK_HROW_TOP_R.BUFHCE.BUFHCE_X0Y7.ZINV_CE origin:040-clk-hrow-config 29_291
CLK_HROW_TOP_R.BUFHCE.BUFHCE_X0Y8.CE_TYPE.ASYNC origin:040-clk-hrow-config 27_310
CLK_HROW_TOP_R.BUFHCE.BUFHCE_X0Y8.INIT_OUT origin:040-clk-hrow-config 26_307
CLK_HROW_TOP_R.BUFHCE.BUFHCE_X0Y8.IN_USE origin:040-clk-hrow-config 27_311
CLK_HROW_TOP_R.BUFHCE.BUFHCE_X0Y8.ZINV_CE origin:040-clk-hrow-config 27_307
CLK_HROW_TOP_R.BUFHCE.BUFHCE_X0Y9.CE_TYPE.ASYNC origin:040-clk-hrow-config 29_310
CLK_HROW_TOP_R.BUFHCE.BUFHCE_X0Y9.INIT_OUT origin:040-clk-hrow-config 28_307
CLK_HROW_TOP_R.BUFHCE.BUFHCE_X0Y9.IN_USE origin:040-clk-hrow-config 29_311
CLK_HROW_TOP_R.BUFHCE.BUFHCE_X0Y9.ZINV_CE origin:040-clk-hrow-config 29_307
CLK_HROW_TOP_R.BUFHCE.BUFHCE_X1Y0.CE_TYPE.ASYNC origin:040-clk-hrow-config 27_166
CLK_HROW_TOP_R.BUFHCE.BUFHCE_X1Y0.INIT_OUT origin:040-clk-hrow-config 26_163
CLK_HROW_TOP_R.BUFHCE.BUFHCE_X1Y0.IN_USE origin:040-clk-hrow-config 27_167
CLK_HROW_TOP_R.BUFHCE.BUFHCE_X1Y0.ZINV_CE origin:040-clk-hrow-config 27_163
CLK_HROW_TOP_R.BUFHCE.BUFHCE_X1Y1.CE_TYPE.ASYNC origin:040-clk-hrow-config 29_166
CLK_HROW_TOP_R.BUFHCE.BUFHCE_X1Y1.INIT_OUT origin:040-clk-hrow-config 28_163
CLK_HROW_TOP_R.BUFHCE.BUFHCE_X1Y1.IN_USE origin:040-clk-hrow-config 29_167
CLK_HROW_TOP_R.BUFHCE.BUFHCE_X1Y1.ZINV_CE origin:040-clk-hrow-config 29_163
CLK_HROW_TOP_R.BUFHCE.BUFHCE_X1Y10.CE_TYPE.ASYNC origin:040-clk-hrow-config 27_374
CLK_HROW_TOP_R.BUFHCE.BUFHCE_X1Y10.INIT_OUT origin:040-clk-hrow-config 26_371
CLK_HROW_TOP_R.BUFHCE.BUFHCE_X1Y10.IN_USE origin:040-clk-hrow-config 27_375
CLK_HROW_TOP_R.BUFHCE.BUFHCE_X1Y10.ZINV_CE origin:040-clk-hrow-config 27_371
CLK_HROW_TOP_R.BUFHCE.BUFHCE_X1Y11.CE_TYPE.ASYNC origin:040-clk-hrow-config 29_374
CLK_HROW_TOP_R.BUFHCE.BUFHCE_X1Y11.INIT_OUT origin:040-clk-hrow-config 28_371
CLK_HROW_TOP_R.BUFHCE.BUFHCE_X1Y11.IN_USE origin:040-clk-hrow-config 29_375
CLK_HROW_TOP_R.BUFHCE.BUFHCE_X1Y11.ZINV_CE origin:040-clk-hrow-config 29_371
CLK_HROW_TOP_R.BUFHCE.BUFHCE_X1Y2.CE_TYPE.ASYNC origin:040-clk-hrow-config 27_182
CLK_HROW_TOP_R.BUFHCE.BUFHCE_X1Y2.INIT_OUT origin:040-clk-hrow-config 26_179
CLK_HROW_TOP_R.BUFHCE.BUFHCE_X1Y2.IN_USE origin:040-clk-hrow-config 27_183
CLK_HROW_TOP_R.BUFHCE.BUFHCE_X1Y2.ZINV_CE origin:040-clk-hrow-config 27_179
CLK_HROW_TOP_R.BUFHCE.BUFHCE_X1Y3.CE_TYPE.ASYNC origin:040-clk-hrow-config 29_182
CLK_HROW_TOP_R.BUFHCE.BUFHCE_X1Y3.INIT_OUT origin:040-clk-hrow-config 28_179
CLK_HROW_TOP_R.BUFHCE.BUFHCE_X1Y3.IN_USE origin:040-clk-hrow-config 29_183
CLK_HROW_TOP_R.BUFHCE.BUFHCE_X1Y3.ZINV_CE origin:040-clk-hrow-config 29_179
CLK_HROW_TOP_R.BUFHCE.BUFHCE_X1Y4.CE_TYPE.ASYNC origin:040-clk-hrow-config 27_198
CLK_HROW_TOP_R.BUFHCE.BUFHCE_X1Y4.INIT_OUT origin:040-clk-hrow-config 26_195
CLK_HROW_TOP_R.BUFHCE.BUFHCE_X1Y4.IN_USE origin:040-clk-hrow-config 27_199
CLK_HROW_TOP_R.BUFHCE.BUFHCE_X1Y4.ZINV_CE origin:040-clk-hrow-config 27_195
CLK_HROW_TOP_R.BUFHCE.BUFHCE_X1Y5.CE_TYPE.ASYNC origin:040-clk-hrow-config 29_198
CLK_HROW_TOP_R.BUFHCE.BUFHCE_X1Y5.INIT_OUT origin:040-clk-hrow-config 28_195
CLK_HROW_TOP_R.BUFHCE.BUFHCE_X1Y5.IN_USE origin:040-clk-hrow-config 29_199
CLK_HROW_TOP_R.BUFHCE.BUFHCE_X1Y5.ZINV_CE origin:040-clk-hrow-config 29_195
CLK_HROW_TOP_R.BUFHCE.BUFHCE_X1Y6.CE_TYPE.ASYNC origin:040-clk-hrow-config 27_342
CLK_HROW_TOP_R.BUFHCE.BUFHCE_X1Y6.INIT_OUT origin:040-clk-hrow-config 26_339
CLK_HROW_TOP_R.BUFHCE.BUFHCE_X1Y6.IN_USE origin:040-clk-hrow-config 27_343
CLK_HROW_TOP_R.BUFHCE.BUFHCE_X1Y6.ZINV_CE origin:040-clk-hrow-config 27_339
CLK_HROW_TOP_R.BUFHCE.BUFHCE_X1Y7.CE_TYPE.ASYNC origin:040-clk-hrow-config 29_342
CLK_HROW_TOP_R.BUFHCE.BUFHCE_X1Y7.INIT_OUT origin:040-clk-hrow-config 28_339
CLK_HROW_TOP_R.BUFHCE.BUFHCE_X1Y7.IN_USE origin:040-clk-hrow-config 29_343
CLK_HROW_TOP_R.BUFHCE.BUFHCE_X1Y7.ZINV_CE origin:040-clk-hrow-config 29_339
CLK_HROW_TOP_R.BUFHCE.BUFHCE_X1Y8.CE_TYPE.ASYNC origin:040-clk-hrow-config 27_358
CLK_HROW_TOP_R.BUFHCE.BUFHCE_X1Y8.INIT_OUT origin:040-clk-hrow-config 26_355
CLK_HROW_TOP_R.BUFHCE.BUFHCE_X1Y8.IN_USE origin:040-clk-hrow-config 27_359
CLK_HROW_TOP_R.BUFHCE.BUFHCE_X1Y8.ZINV_CE origin:040-clk-hrow-config 27_355
CLK_HROW_TOP_R.BUFHCE.BUFHCE_X1Y9.CE_TYPE.ASYNC origin:040-clk-hrow-config 29_358
CLK_HROW_TOP_R.BUFHCE.BUFHCE_X1Y9.INIT_OUT origin:040-clk-hrow-config 28_355
CLK_HROW_TOP_R.BUFHCE.BUFHCE_X1Y9.IN_USE origin:040-clk-hrow-config 29_359
CLK_HROW_TOP_R.BUFHCE.BUFHCE_X1Y9.ZINV_CE origin:040-clk-hrow-config 29_355

192
zynq7/segbits_dsp_l.origin_info.db Normal file
View File

@ -0,0 +1,192 @@
DSP_L.DSP48.DSP_0.MASK[0] origin:100-dsp-mskpat 27_01
DSP_L.DSP48.DSP_0.MASK[10] origin:100-dsp-mskpat 27_26
DSP_L.DSP48.DSP_0.MASK[11] origin:100-dsp-mskpat 26_28
DSP_L.DSP48.DSP_0.MASK[12] origin:100-dsp-mskpat 26_41
DSP_L.DSP48.DSP_0.MASK[13] origin:100-dsp-mskpat 27_42
DSP_L.DSP48.DSP_0.MASK[14] origin:100-dsp-mskpat 26_45
DSP_L.DSP48.DSP_0.MASK[15] origin:100-dsp-mskpat 27_46
DSP_L.DSP48.DSP_0.MASK[16] origin:100-dsp-mskpat 26_49
DSP_L.DSP48.DSP_0.MASK[17] origin:100-dsp-mskpat 27_50
DSP_L.DSP48.DSP_0.MASK[18] origin:100-dsp-mskpat 27_57
DSP_L.DSP48.DSP_0.MASK[19] origin:100-dsp-mskpat 26_59
DSP_L.DSP48.DSP_0.MASK[1] origin:100-dsp-mskpat 26_03
DSP_L.DSP48.DSP_0.MASK[20] origin:100-dsp-mskpat 26_62
DSP_L.DSP48.DSP_0.MASK[21] origin:100-dsp-mskpat 27_63
DSP_L.DSP48.DSP_0.MASK[22] origin:100-dsp-mskpat 26_66
DSP_L.DSP48.DSP_0.MASK[23] origin:100-dsp-mskpat 27_67
DSP_L.DSP48.DSP_0.MASK[24] origin:100-dsp-mskpat 27_86
DSP_L.DSP48.DSP_0.MASK[25] origin:100-dsp-mskpat 26_88
DSP_L.DSP48.DSP_0.MASK[26] origin:100-dsp-mskpat 27_90
DSP_L.DSP48.DSP_0.MASK[27] origin:100-dsp-mskpat 26_92
DSP_L.DSP48.DSP_0.MASK[28] origin:100-dsp-mskpat 27_94
DSP_L.DSP48.DSP_0.MASK[29] origin:100-dsp-mskpat 26_96
DSP_L.DSP48.DSP_0.MASK[2] origin:100-dsp-mskpat 27_06
DSP_L.DSP48.DSP_0.MASK[30] origin:100-dsp-mskpat 27_102
DSP_L.DSP48.DSP_0.MASK[31] origin:100-dsp-mskpat 26_104
DSP_L.DSP48.DSP_0.MASK[32] origin:100-dsp-mskpat 27_106
DSP_L.DSP48.DSP_0.MASK[33] origin:100-dsp-mskpat 26_108
DSP_L.DSP48.DSP_0.MASK[34] origin:100-dsp-mskpat 27_110
DSP_L.DSP48.DSP_0.MASK[35] origin:100-dsp-mskpat 26_112
DSP_L.DSP48.DSP_0.MASK[36] origin:100-dsp-mskpat 27_127
DSP_L.DSP48.DSP_0.MASK[37] origin:100-dsp-mskpat 26_129
DSP_L.DSP48.DSP_0.MASK[38] origin:100-dsp-mskpat 26_132
DSP_L.DSP48.DSP_0.MASK[39] origin:100-dsp-mskpat 27_133
DSP_L.DSP48.DSP_0.MASK[3] origin:100-dsp-mskpat 26_07
DSP_L.DSP48.DSP_0.MASK[40] origin:100-dsp-mskpat 26_136
DSP_L.DSP48.DSP_0.MASK[41] origin:100-dsp-mskpat 27_137
DSP_L.DSP48.DSP_0.MASK[42] origin:100-dsp-mskpat 27_144
DSP_L.DSP48.DSP_0.MASK[43] origin:100-dsp-mskpat 26_146
DSP_L.DSP48.DSP_0.MASK[44] origin:100-dsp-mskpat 26_149
DSP_L.DSP48.DSP_0.MASK[45] origin:100-dsp-mskpat 27_150
DSP_L.DSP48.DSP_0.MASK[46] origin:100-dsp-mskpat 26_153
DSP_L.DSP48.DSP_0.MASK[47] origin:100-dsp-mskpat 26_154
DSP_L.DSP48.DSP_0.MASK[4] origin:100-dsp-mskpat 26_10
DSP_L.DSP48.DSP_0.MASK[5] origin:100-dsp-mskpat 27_11
DSP_L.DSP48.DSP_0.MASK[6] origin:100-dsp-mskpat 26_18
DSP_L.DSP48.DSP_0.MASK[7] origin:100-dsp-mskpat 27_19
DSP_L.DSP48.DSP_0.MASK[8] origin:100-dsp-mskpat 26_22
DSP_L.DSP48.DSP_0.MASK[9] origin:100-dsp-mskpat 27_23
DSP_L.DSP48.DSP_0.PATTERN[0] origin:100-dsp-mskpat 26_01
DSP_L.DSP48.DSP_0.PATTERN[10] origin:100-dsp-mskpat 26_26
DSP_L.DSP48.DSP_0.PATTERN[11] origin:100-dsp-mskpat 26_29
DSP_L.DSP48.DSP_0.PATTERN[12] origin:100-dsp-mskpat 27_40
DSP_L.DSP48.DSP_0.PATTERN[13] origin:100-dsp-mskpat 26_43
DSP_L.DSP48.DSP_0.PATTERN[14] origin:100-dsp-mskpat 27_44
DSP_L.DSP48.DSP_0.PATTERN[15] origin:100-dsp-mskpat 26_47
DSP_L.DSP48.DSP_0.PATTERN[16] origin:100-dsp-mskpat 27_48
DSP_L.DSP48.DSP_0.PATTERN[17] origin:100-dsp-mskpat 26_51
DSP_L.DSP48.DSP_0.PATTERN[18] origin:100-dsp-mskpat 26_57
DSP_L.DSP48.DSP_0.PATTERN[19] origin:100-dsp-mskpat 26_60
DSP_L.DSP48.DSP_0.PATTERN[1] origin:100-dsp-mskpat 26_04
DSP_L.DSP48.DSP_0.PATTERN[20] origin:100-dsp-mskpat 27_61
DSP_L.DSP48.DSP_0.PATTERN[21] origin:100-dsp-mskpat 26_64
DSP_L.DSP48.DSP_0.PATTERN[22] origin:100-dsp-mskpat 27_65
DSP_L.DSP48.DSP_0.PATTERN[23] origin:100-dsp-mskpat 26_68
DSP_L.DSP48.DSP_0.PATTERN[24] origin:100-dsp-mskpat 26_86
DSP_L.DSP48.DSP_0.PATTERN[25] origin:100-dsp-mskpat 27_88
DSP_L.DSP48.DSP_0.PATTERN[26] origin:100-dsp-mskpat 26_90
DSP_L.DSP48.DSP_0.PATTERN[27] origin:100-dsp-mskpat 27_92
DSP_L.DSP48.DSP_0.PATTERN[28] origin:100-dsp-mskpat 26_94
DSP_L.DSP48.DSP_0.PATTERN[29] origin:100-dsp-mskpat 26_97
DSP_L.DSP48.DSP_0.PATTERN[2] origin:100-dsp-mskpat 26_05
DSP_L.DSP48.DSP_0.PATTERN[30] origin:100-dsp-mskpat 27_101
DSP_L.DSP48.DSP_0.PATTERN[31] origin:100-dsp-mskpat 27_104
DSP_L.DSP48.DSP_0.PATTERN[32] origin:100-dsp-mskpat 26_106
DSP_L.DSP48.DSP_0.PATTERN[33] origin:100-dsp-mskpat 27_108
DSP_L.DSP48.DSP_0.PATTERN[34] origin:100-dsp-mskpat 26_110
DSP_L.DSP48.DSP_0.PATTERN[35] origin:100-dsp-mskpat 27_112
DSP_L.DSP48.DSP_0.PATTERN[36] origin:100-dsp-mskpat 26_127
DSP_L.DSP48.DSP_0.PATTERN[37] origin:100-dsp-mskpat 26_130
DSP_L.DSP48.DSP_0.PATTERN[38] origin:100-dsp-mskpat 27_131
DSP_L.DSP48.DSP_0.PATTERN[39] origin:100-dsp-mskpat 26_134
DSP_L.DSP48.DSP_0.PATTERN[3] origin:100-dsp-mskpat 27_08
DSP_L.DSP48.DSP_0.PATTERN[40] origin:100-dsp-mskpat 27_135
DSP_L.DSP48.DSP_0.PATTERN[41] origin:100-dsp-mskpat 26_138
DSP_L.DSP48.DSP_0.PATTERN[42] origin:100-dsp-mskpat 26_144
DSP_L.DSP48.DSP_0.PATTERN[43] origin:100-dsp-mskpat 27_146
DSP_L.DSP48.DSP_0.PATTERN[44] origin:100-dsp-mskpat 26_148
DSP_L.DSP48.DSP_0.PATTERN[45] origin:100-dsp-mskpat 26_151
DSP_L.DSP48.DSP_0.PATTERN[46] origin:100-dsp-mskpat 27_152
DSP_L.DSP48.DSP_0.PATTERN[47] origin:100-dsp-mskpat 26_155
DSP_L.DSP48.DSP_0.PATTERN[4] origin:100-dsp-mskpat 26_09
DSP_L.DSP48.DSP_0.PATTERN[5] origin:100-dsp-mskpat 26_12
DSP_L.DSP48.DSP_0.PATTERN[6] origin:100-dsp-mskpat 27_17
DSP_L.DSP48.DSP_0.PATTERN[7] origin:100-dsp-mskpat 26_20
DSP_L.DSP48.DSP_0.PATTERN[8] origin:100-dsp-mskpat 27_21
DSP_L.DSP48.DSP_0.PATTERN[9] origin:100-dsp-mskpat 27_24
DSP_L.DSP48.DSP_1.MASK[0] origin:100-dsp-mskpat 27_161
DSP_L.DSP48.DSP_1.MASK[10] origin:100-dsp-mskpat 27_186
DSP_L.DSP48.DSP_1.MASK[11] origin:100-dsp-mskpat 26_188
DSP_L.DSP48.DSP_1.MASK[12] origin:100-dsp-mskpat 26_201
DSP_L.DSP48.DSP_1.MASK[13] origin:100-dsp-mskpat 27_202
DSP_L.DSP48.DSP_1.MASK[14] origin:100-dsp-mskpat 26_205
DSP_L.DSP48.DSP_1.MASK[15] origin:100-dsp-mskpat 27_206
DSP_L.DSP48.DSP_1.MASK[16] origin:100-dsp-mskpat 26_209
DSP_L.DSP48.DSP_1.MASK[17] origin:100-dsp-mskpat 27_210
DSP_L.DSP48.DSP_1.MASK[18] origin:100-dsp-mskpat 27_217
DSP_L.DSP48.DSP_1.MASK[19] origin:100-dsp-mskpat 26_219
DSP_L.DSP48.DSP_1.MASK[1] origin:100-dsp-mskpat 26_163
DSP_L.DSP48.DSP_1.MASK[20] origin:100-dsp-mskpat 26_222
DSP_L.DSP48.DSP_1.MASK[21] origin:100-dsp-mskpat 27_223
DSP_L.DSP48.DSP_1.MASK[22] origin:100-dsp-mskpat 26_226
DSP_L.DSP48.DSP_1.MASK[23] origin:100-dsp-mskpat 27_227
DSP_L.DSP48.DSP_1.MASK[24] origin:100-dsp-mskpat 27_246
DSP_L.DSP48.DSP_1.MASK[25] origin:100-dsp-mskpat 26_248
DSP_L.DSP48.DSP_1.MASK[26] origin:100-dsp-mskpat 27_250
DSP_L.DSP48.DSP_1.MASK[27] origin:100-dsp-mskpat 26_252
DSP_L.DSP48.DSP_1.MASK[28] origin:100-dsp-mskpat 27_254
DSP_L.DSP48.DSP_1.MASK[29] origin:100-dsp-mskpat 26_256
DSP_L.DSP48.DSP_1.MASK[2] origin:100-dsp-mskpat 27_166
DSP_L.DSP48.DSP_1.MASK[30] origin:100-dsp-mskpat 27_262
DSP_L.DSP48.DSP_1.MASK[31] origin:100-dsp-mskpat 26_264
DSP_L.DSP48.DSP_1.MASK[32] origin:100-dsp-mskpat 27_266
DSP_L.DSP48.DSP_1.MASK[33] origin:100-dsp-mskpat 26_268
DSP_L.DSP48.DSP_1.MASK[34] origin:100-dsp-mskpat 27_270
DSP_L.DSP48.DSP_1.MASK[35] origin:100-dsp-mskpat 26_272
DSP_L.DSP48.DSP_1.MASK[36] origin:100-dsp-mskpat 27_287
DSP_L.DSP48.DSP_1.MASK[37] origin:100-dsp-mskpat 26_289
DSP_L.DSP48.DSP_1.MASK[38] origin:100-dsp-mskpat 26_292
DSP_L.DSP48.DSP_1.MASK[39] origin:100-dsp-mskpat 27_293
DSP_L.DSP48.DSP_1.MASK[3] origin:100-dsp-mskpat 26_167
DSP_L.DSP48.DSP_1.MASK[40] origin:100-dsp-mskpat 26_296
DSP_L.DSP48.DSP_1.MASK[41] origin:100-dsp-mskpat 27_297
DSP_L.DSP48.DSP_1.MASK[42] origin:100-dsp-mskpat 27_304
DSP_L.DSP48.DSP_1.MASK[43] origin:100-dsp-mskpat 26_306
DSP_L.DSP48.DSP_1.MASK[44] origin:100-dsp-mskpat 26_309
DSP_L.DSP48.DSP_1.MASK[45] origin:100-dsp-mskpat 27_310
DSP_L.DSP48.DSP_1.MASK[46] origin:100-dsp-mskpat 26_313
DSP_L.DSP48.DSP_1.MASK[47] origin:100-dsp-mskpat 26_314
DSP_L.DSP48.DSP_1.MASK[4] origin:100-dsp-mskpat 26_170
DSP_L.DSP48.DSP_1.MASK[5] origin:100-dsp-mskpat 27_171
DSP_L.DSP48.DSP_1.MASK[6] origin:100-dsp-mskpat 26_178
DSP_L.DSP48.DSP_1.MASK[7] origin:100-dsp-mskpat 27_179
DSP_L.DSP48.DSP_1.MASK[8] origin:100-dsp-mskpat 26_182
DSP_L.DSP48.DSP_1.MASK[9] origin:100-dsp-mskpat 27_183
DSP_L.DSP48.DSP_1.PATTERN[0] origin:100-dsp-mskpat 26_161
DSP_L.DSP48.DSP_1.PATTERN[10] origin:100-dsp-mskpat 26_186
DSP_L.DSP48.DSP_1.PATTERN[11] origin:100-dsp-mskpat 26_189
DSP_L.DSP48.DSP_1.PATTERN[12] origin:100-dsp-mskpat 27_200
DSP_L.DSP48.DSP_1.PATTERN[13] origin:100-dsp-mskpat 26_203
DSP_L.DSP48.DSP_1.PATTERN[14] origin:100-dsp-mskpat 27_204
DSP_L.DSP48.DSP_1.PATTERN[15] origin:100-dsp-mskpat 26_207
DSP_L.DSP48.DSP_1.PATTERN[16] origin:100-dsp-mskpat 27_208
DSP_L.DSP48.DSP_1.PATTERN[17] origin:100-dsp-mskpat 26_211
DSP_L.DSP48.DSP_1.PATTERN[18] origin:100-dsp-mskpat 26_217
DSP_L.DSP48.DSP_1.PATTERN[19] origin:100-dsp-mskpat 26_220
DSP_L.DSP48.DSP_1.PATTERN[1] origin:100-dsp-mskpat 26_164
DSP_L.DSP48.DSP_1.PATTERN[20] origin:100-dsp-mskpat 27_221
DSP_L.DSP48.DSP_1.PATTERN[21] origin:100-dsp-mskpat 26_224
DSP_L.DSP48.DSP_1.PATTERN[22] origin:100-dsp-mskpat 27_225
DSP_L.DSP48.DSP_1.PATTERN[23] origin:100-dsp-mskpat 26_228
DSP_L.DSP48.DSP_1.PATTERN[24] origin:100-dsp-mskpat 26_246
DSP_L.DSP48.DSP_1.PATTERN[25] origin:100-dsp-mskpat 27_248
DSP_L.DSP48.DSP_1.PATTERN[26] origin:100-dsp-mskpat 26_250
DSP_L.DSP48.DSP_1.PATTERN[27] origin:100-dsp-mskpat 27_252
DSP_L.DSP48.DSP_1.PATTERN[28] origin:100-dsp-mskpat 26_254
DSP_L.DSP48.DSP_1.PATTERN[29] origin:100-dsp-mskpat 26_257
DSP_L.DSP48.DSP_1.PATTERN[2] origin:100-dsp-mskpat 26_165
DSP_L.DSP48.DSP_1.PATTERN[30] origin:100-dsp-mskpat 27_261
DSP_L.DSP48.DSP_1.PATTERN[31] origin:100-dsp-mskpat 27_264
DSP_L.DSP48.DSP_1.PATTERN[32] origin:100-dsp-mskpat 26_266
DSP_L.DSP48.DSP_1.PATTERN[33] origin:100-dsp-mskpat 27_268
DSP_L.DSP48.DSP_1.PATTERN[34] origin:100-dsp-mskpat 26_270
DSP_L.DSP48.DSP_1.PATTERN[35] origin:100-dsp-mskpat 27_272
DSP_L.DSP48.DSP_1.PATTERN[36] origin:100-dsp-mskpat 26_287
DSP_L.DSP48.DSP_1.PATTERN[37] origin:100-dsp-mskpat 26_290
DSP_L.DSP48.DSP_1.PATTERN[38] origin:100-dsp-mskpat 27_291
DSP_L.DSP48.DSP_1.PATTERN[39] origin:100-dsp-mskpat 26_294
DSP_L.DSP48.DSP_1.PATTERN[3] origin:100-dsp-mskpat 27_168
DSP_L.DSP48.DSP_1.PATTERN[40] origin:100-dsp-mskpat 27_295
DSP_L.DSP48.DSP_1.PATTERN[41] origin:100-dsp-mskpat 26_298
DSP_L.DSP48.DSP_1.PATTERN[42] origin:100-dsp-mskpat 26_304
DSP_L.DSP48.DSP_1.PATTERN[43] origin:100-dsp-mskpat 27_306
DSP_L.DSP48.DSP_1.PATTERN[44] origin:100-dsp-mskpat 26_308
DSP_L.DSP48.DSP_1.PATTERN[45] origin:100-dsp-mskpat 26_311
DSP_L.DSP48.DSP_1.PATTERN[46] origin:100-dsp-mskpat 27_312
DSP_L.DSP48.DSP_1.PATTERN[47] origin:100-dsp-mskpat 26_315
DSP_L.DSP48.DSP_1.PATTERN[4] origin:100-dsp-mskpat 26_169
DSP_L.DSP48.DSP_1.PATTERN[5] origin:100-dsp-mskpat 26_172
DSP_L.DSP48.DSP_1.PATTERN[6] origin:100-dsp-mskpat 27_177
DSP_L.DSP48.DSP_1.PATTERN[7] origin:100-dsp-mskpat 26_180
DSP_L.DSP48.DSP_1.PATTERN[8] origin:100-dsp-mskpat 27_181
DSP_L.DSP48.DSP_1.PATTERN[9] origin:100-dsp-mskpat 27_184

192
zynq7/segbits_dsp_r.origin_info.db Normal file
View File

@ -0,0 +1,192 @@
DSP_R.DSP48.DSP_0.MASK[0] origin:100-dsp-mskpat 27_01
DSP_R.DSP48.DSP_0.MASK[10] origin:100-dsp-mskpat 27_26
DSP_R.DSP48.DSP_0.MASK[11] origin:100-dsp-mskpat 26_28
DSP_R.DSP48.DSP_0.MASK[12] origin:100-dsp-mskpat 26_41
DSP_R.DSP48.DSP_0.MASK[13] origin:100-dsp-mskpat 27_42
DSP_R.DSP48.DSP_0.MASK[14] origin:100-dsp-mskpat 26_45
DSP_R.DSP48.DSP_0.MASK[15] origin:100-dsp-mskpat 27_46
DSP_R.DSP48.DSP_0.MASK[16] origin:100-dsp-mskpat 26_49
DSP_R.DSP48.DSP_0.MASK[17] origin:100-dsp-mskpat 27_50
DSP_R.DSP48.DSP_0.MASK[18] origin:100-dsp-mskpat 27_57
DSP_R.DSP48.DSP_0.MASK[19] origin:100-dsp-mskpat 26_59
DSP_R.DSP48.DSP_0.MASK[1] origin:100-dsp-mskpat 26_03
DSP_R.DSP48.DSP_0.MASK[20] origin:100-dsp-mskpat 26_62
DSP_R.DSP48.DSP_0.MASK[21] origin:100-dsp-mskpat 27_63
DSP_R.DSP48.DSP_0.MASK[22] origin:100-dsp-mskpat 26_66
DSP_R.DSP48.DSP_0.MASK[23] origin:100-dsp-mskpat 27_67
DSP_R.DSP48.DSP_0.MASK[24] origin:100-dsp-mskpat 27_86
DSP_R.DSP48.DSP_0.MASK[25] origin:100-dsp-mskpat 26_88
DSP_R.DSP48.DSP_0.MASK[26] origin:100-dsp-mskpat 27_90
DSP_R.DSP48.DSP_0.MASK[27] origin:100-dsp-mskpat 26_92
DSP_R.DSP48.DSP_0.MASK[28] origin:100-dsp-mskpat 27_94
DSP_R.DSP48.DSP_0.MASK[29] origin:100-dsp-mskpat 26_96
DSP_R.DSP48.DSP_0.MASK[2] origin:100-dsp-mskpat 27_06
DSP_R.DSP48.DSP_0.MASK[30] origin:100-dsp-mskpat 27_102
DSP_R.DSP48.DSP_0.MASK[31] origin:100-dsp-mskpat 26_104
DSP_R.DSP48.DSP_0.MASK[32] origin:100-dsp-mskpat 27_106
DSP_R.DSP48.DSP_0.MASK[33] origin:100-dsp-mskpat 26_108
DSP_R.DSP48.DSP_0.MASK[34] origin:100-dsp-mskpat 27_110
DSP_R.DSP48.DSP_0.MASK[35] origin:100-dsp-mskpat 26_112
DSP_R.DSP48.DSP_0.MASK[36] origin:100-dsp-mskpat 27_127
DSP_R.DSP48.DSP_0.MASK[37] origin:100-dsp-mskpat 26_129
DSP_R.DSP48.DSP_0.MASK[38] origin:100-dsp-mskpat 26_132
DSP_R.DSP48.DSP_0.MASK[39] origin:100-dsp-mskpat 27_133
DSP_R.DSP48.DSP_0.MASK[3] origin:100-dsp-mskpat 26_07
DSP_R.DSP48.DSP_0.MASK[40] origin:100-dsp-mskpat 26_136
DSP_R.DSP48.DSP_0.MASK[41] origin:100-dsp-mskpat 27_137
DSP_R.DSP48.DSP_0.MASK[42] origin:100-dsp-mskpat 27_144
DSP_R.DSP48.DSP_0.MASK[43] origin:100-dsp-mskpat 26_146
DSP_R.DSP48.DSP_0.MASK[44] origin:100-dsp-mskpat 26_149
DSP_R.DSP48.DSP_0.MASK[45] origin:100-dsp-mskpat 27_150
DSP_R.DSP48.DSP_0.MASK[46] origin:100-dsp-mskpat 26_153
DSP_R.DSP48.DSP_0.MASK[47] origin:100-dsp-mskpat 26_154
DSP_R.DSP48.DSP_0.MASK[4] origin:100-dsp-mskpat 26_10
DSP_R.DSP48.DSP_0.MASK[5] origin:100-dsp-mskpat 27_11
DSP_R.DSP48.DSP_0.MASK[6] origin:100-dsp-mskpat 26_18
DSP_R.DSP48.DSP_0.MASK[7] origin:100-dsp-mskpat 27_19
DSP_R.DSP48.DSP_0.MASK[8] origin:100-dsp-mskpat 26_22
DSP_R.DSP48.DSP_0.MASK[9] origin:100-dsp-mskpat 27_23
DSP_R.DSP48.DSP_0.PATTERN[0] origin:100-dsp-mskpat 26_01
DSP_R.DSP48.DSP_0.PATTERN[10] origin:100-dsp-mskpat 26_26
DSP_R.DSP48.DSP_0.PATTERN[11] origin:100-dsp-mskpat 26_29
DSP_R.DSP48.DSP_0.PATTERN[12] origin:100-dsp-mskpat 27_40
DSP_R.DSP48.DSP_0.PATTERN[13] origin:100-dsp-mskpat 26_43
DSP_R.DSP48.DSP_0.PATTERN[14] origin:100-dsp-mskpat 27_44
DSP_R.DSP48.DSP_0.PATTERN[15] origin:100-dsp-mskpat 26_47
DSP_R.DSP48.DSP_0.PATTERN[16] origin:100-dsp-mskpat 27_48
DSP_R.DSP48.DSP_0.PATTERN[17] origin:100-dsp-mskpat 26_51
DSP_R.DSP48.DSP_0.PATTERN[18] origin:100-dsp-mskpat 26_57
DSP_R.DSP48.DSP_0.PATTERN[19] origin:100-dsp-mskpat 26_60
DSP_R.DSP48.DSP_0.PATTERN[1] origin:100-dsp-mskpat 26_04
DSP_R.DSP48.DSP_0.PATTERN[20] origin:100-dsp-mskpat 27_61
DSP_R.DSP48.DSP_0.PATTERN[21] origin:100-dsp-mskpat 26_64
DSP_R.DSP48.DSP_0.PATTERN[22] origin:100-dsp-mskpat 27_65
DSP_R.DSP48.DSP_0.PATTERN[23] origin:100-dsp-mskpat 26_68
DSP_R.DSP48.DSP_0.PATTERN[24] origin:100-dsp-mskpat 26_86
DSP_R.DSP48.DSP_0.PATTERN[25] origin:100-dsp-mskpat 27_88
DSP_R.DSP48.DSP_0.PATTERN[26] origin:100-dsp-mskpat 26_90
DSP_R.DSP48.DSP_0.PATTERN[27] origin:100-dsp-mskpat 27_92
DSP_R.DSP48.DSP_0.PATTERN[28] origin:100-dsp-mskpat 26_94
DSP_R.DSP48.DSP_0.PATTERN[29] origin:100-dsp-mskpat 26_97
DSP_R.DSP48.DSP_0.PATTERN[2] origin:100-dsp-mskpat 26_05
DSP_R.DSP48.DSP_0.PATTERN[30] origin:100-dsp-mskpat 27_101
DSP_R.DSP48.DSP_0.PATTERN[31] origin:100-dsp-mskpat 27_104
DSP_R.DSP48.DSP_0.PATTERN[32] origin:100-dsp-mskpat 26_106
DSP_R.DSP48.DSP_0.PATTERN[33] origin:100-dsp-mskpat 27_108
DSP_R.DSP48.DSP_0.PATTERN[34] origin:100-dsp-mskpat 26_110
DSP_R.DSP48.DSP_0.PATTERN[35] origin:100-dsp-mskpat 27_112
DSP_R.DSP48.DSP_0.PATTERN[36] origin:100-dsp-mskpat 26_127
DSP_R.DSP48.DSP_0.PATTERN[37] origin:100-dsp-mskpat 26_130
DSP_R.DSP48.DSP_0.PATTERN[38] origin:100-dsp-mskpat 27_131
DSP_R.DSP48.DSP_0.PATTERN[39] origin:100-dsp-mskpat 26_134
DSP_R.DSP48.DSP_0.PATTERN[3] origin:100-dsp-mskpat 27_08
DSP_R.DSP48.DSP_0.PATTERN[40] origin:100-dsp-mskpat 27_135
DSP_R.DSP48.DSP_0.PATTERN[41] origin:100-dsp-mskpat 26_138
DSP_R.DSP48.DSP_0.PATTERN[42] origin:100-dsp-mskpat 26_144
DSP_R.DSP48.DSP_0.PATTERN[43] origin:100-dsp-mskpat 27_146
DSP_R.DSP48.DSP_0.PATTERN[44] origin:100-dsp-mskpat 26_148
DSP_R.DSP48.DSP_0.PATTERN[45] origin:100-dsp-mskpat 26_151
DSP_R.DSP48.DSP_0.PATTERN[46] origin:100-dsp-mskpat 27_152
DSP_R.DSP48.DSP_0.PATTERN[47] origin:100-dsp-mskpat 26_155
DSP_R.DSP48.DSP_0.PATTERN[4] origin:100-dsp-mskpat 26_09
DSP_R.DSP48.DSP_0.PATTERN[5] origin:100-dsp-mskpat 26_12
DSP_R.DSP48.DSP_0.PATTERN[6] origin:100-dsp-mskpat 27_17
DSP_R.DSP48.DSP_0.PATTERN[7] origin:100-dsp-mskpat 26_20
DSP_R.DSP48.DSP_0.PATTERN[8] origin:100-dsp-mskpat 27_21
DSP_R.DSP48.DSP_0.PATTERN[9] origin:100-dsp-mskpat 27_24
DSP_R.DSP48.DSP_1.MASK[0] origin:100-dsp-mskpat 27_161
DSP_R.DSP48.DSP_1.MASK[10] origin:100-dsp-mskpat 27_186
DSP_R.DSP48.DSP_1.MASK[11] origin:100-dsp-mskpat 26_188
DSP_R.DSP48.DSP_1.MASK[12] origin:100-dsp-mskpat 26_201
DSP_R.DSP48.DSP_1.MASK[13] origin:100-dsp-mskpat 27_202
DSP_R.DSP48.DSP_1.MASK[14] origin:100-dsp-mskpat 26_205
DSP_R.DSP48.DSP_1.MASK[15] origin:100-dsp-mskpat 27_206
DSP_R.DSP48.DSP_1.MASK[16] origin:100-dsp-mskpat 26_209
DSP_R.DSP48.DSP_1.MASK[17] origin:100-dsp-mskpat 27_210
DSP_R.DSP48.DSP_1.MASK[18] origin:100-dsp-mskpat 27_217
DSP_R.DSP48.DSP_1.MASK[19] origin:100-dsp-mskpat 26_219
DSP_R.DSP48.DSP_1.MASK[1] origin:100-dsp-mskpat 26_163
DSP_R.DSP48.DSP_1.MASK[20] origin:100-dsp-mskpat 26_222
DSP_R.DSP48.DSP_1.MASK[21] origin:100-dsp-mskpat 27_223
DSP_R.DSP48.DSP_1.MASK[22] origin:100-dsp-mskpat 26_226
DSP_R.DSP48.DSP_1.MASK[23] origin:100-dsp-mskpat 27_227
DSP_R.DSP48.DSP_1.MASK[24] origin:100-dsp-mskpat 27_246
DSP_R.DSP48.DSP_1.MASK[25] origin:100-dsp-mskpat 26_248
DSP_R.DSP48.DSP_1.MASK[26] origin:100-dsp-mskpat 27_250
DSP_R.DSP48.DSP_1.MASK[27] origin:100-dsp-mskpat 26_252
DSP_R.DSP48.DSP_1.MASK[28] origin:100-dsp-mskpat 27_254
DSP_R.DSP48.DSP_1.MASK[29] origin:100-dsp-mskpat 26_256
DSP_R.DSP48.DSP_1.MASK[2] origin:100-dsp-mskpat 27_166
DSP_R.DSP48.DSP_1.MASK[30] origin:100-dsp-mskpat 27_262
DSP_R.DSP48.DSP_1.MASK[31] origin:100-dsp-mskpat 26_264
DSP_R.DSP48.DSP_1.MASK[32] origin:100-dsp-mskpat 27_266
DSP_R.DSP48.DSP_1.MASK[33] origin:100-dsp-mskpat 26_268
DSP_R.DSP48.DSP_1.MASK[34] origin:100-dsp-mskpat 27_270
DSP_R.DSP48.DSP_1.MASK[35] origin:100-dsp-mskpat 26_272
DSP_R.DSP48.DSP_1.MASK[36] origin:100-dsp-mskpat 27_287
DSP_R.DSP48.DSP_1.MASK[37] origin:100-dsp-mskpat 26_289
DSP_R.DSP48.DSP_1.MASK[38] origin:100-dsp-mskpat 26_292
DSP_R.DSP48.DSP_1.MASK[39] origin:100-dsp-mskpat 27_293
DSP_R.DSP48.DSP_1.MASK[3] origin:100-dsp-mskpat 26_167
DSP_R.DSP48.DSP_1.MASK[40] origin:100-dsp-mskpat 26_296
DSP_R.DSP48.DSP_1.MASK[41] origin:100-dsp-mskpat 27_297
DSP_R.DSP48.DSP_1.MASK[42] origin:100-dsp-mskpat 27_304
DSP_R.DSP48.DSP_1.MASK[43] origin:100-dsp-mskpat 26_306
DSP_R.DSP48.DSP_1.MASK[44] origin:100-dsp-mskpat 26_309
DSP_R.DSP48.DSP_1.MASK[45] origin:100-dsp-mskpat 27_310
DSP_R.DSP48.DSP_1.MASK[46] origin:100-dsp-mskpat 26_313
DSP_R.DSP48.DSP_1.MASK[47] origin:100-dsp-mskpat 26_314
DSP_R.DSP48.DSP_1.MASK[4] origin:100-dsp-mskpat 26_170
DSP_R.DSP48.DSP_1.MASK[5] origin:100-dsp-mskpat 27_171
DSP_R.DSP48.DSP_1.MASK[6] origin:100-dsp-mskpat 26_178
DSP_R.DSP48.DSP_1.MASK[7] origin:100-dsp-mskpat 27_179
DSP_R.DSP48.DSP_1.MASK[8] origin:100-dsp-mskpat 26_182
DSP_R.DSP48.DSP_1.MASK[9] origin:100-dsp-mskpat 27_183
DSP_R.DSP48.DSP_1.PATTERN[0] origin:100-dsp-mskpat 26_161
DSP_R.DSP48.DSP_1.PATTERN[10] origin:100-dsp-mskpat 26_186
DSP_R.DSP48.DSP_1.PATTERN[11] origin:100-dsp-mskpat 26_189
DSP_R.DSP48.DSP_1.PATTERN[12] origin:100-dsp-mskpat 27_200
DSP_R.DSP48.DSP_1.PATTERN[13] origin:100-dsp-mskpat 26_203
DSP_R.DSP48.DSP_1.PATTERN[14] origin:100-dsp-mskpat 27_204
DSP_R.DSP48.DSP_1.PATTERN[15] origin:100-dsp-mskpat 26_207
DSP_R.DSP48.DSP_1.PATTERN[16] origin:100-dsp-mskpat 27_208
DSP_R.DSP48.DSP_1.PATTERN[17] origin:100-dsp-mskpat 26_211
DSP_R.DSP48.DSP_1.PATTERN[18] origin:100-dsp-mskpat 26_217
DSP_R.DSP48.DSP_1.PATTERN[19] origin:100-dsp-mskpat 26_220
DSP_R.DSP48.DSP_1.PATTERN[1] origin:100-dsp-mskpat 26_164
DSP_R.DSP48.DSP_1.PATTERN[20] origin:100-dsp-mskpat 27_221
DSP_R.DSP48.DSP_1.PATTERN[21] origin:100-dsp-mskpat 26_224
DSP_R.DSP48.DSP_1.PATTERN[22] origin:100-dsp-mskpat 27_225
DSP_R.DSP48.DSP_1.PATTERN[23] origin:100-dsp-mskpat 26_228
DSP_R.DSP48.DSP_1.PATTERN[24] origin:100-dsp-mskpat 26_246
DSP_R.DSP48.DSP_1.PATTERN[25] origin:100-dsp-mskpat 27_248
DSP_R.DSP48.DSP_1.PATTERN[26] origin:100-dsp-mskpat 26_250
DSP_R.DSP48.DSP_1.PATTERN[27] origin:100-dsp-mskpat 27_252
DSP_R.DSP48.DSP_1.PATTERN[28] origin:100-dsp-mskpat 26_254
DSP_R.DSP48.DSP_1.PATTERN[29] origin:100-dsp-mskpat 26_257
DSP_R.DSP48.DSP_1.PATTERN[2] origin:100-dsp-mskpat 26_165
DSP_R.DSP48.DSP_1.PATTERN[30] origin:100-dsp-mskpat 27_261
DSP_R.DSP48.DSP_1.PATTERN[31] origin:100-dsp-mskpat 27_264
DSP_R.DSP48.DSP_1.PATTERN[32] origin:100-dsp-mskpat 26_266
DSP_R.DSP48.DSP_1.PATTERN[33] origin:100-dsp-mskpat 27_268
DSP_R.DSP48.DSP_1.PATTERN[34] origin:100-dsp-mskpat 26_270
DSP_R.DSP48.DSP_1.PATTERN[35] origin:100-dsp-mskpat 27_272
DSP_R.DSP48.DSP_1.PATTERN[36] origin:100-dsp-mskpat 26_287
DSP_R.DSP48.DSP_1.PATTERN[37] origin:100-dsp-mskpat 26_290
DSP_R.DSP48.DSP_1.PATTERN[38] origin:100-dsp-mskpat 27_291
DSP_R.DSP48.DSP_1.PATTERN[39] origin:100-dsp-mskpat 26_294
DSP_R.DSP48.DSP_1.PATTERN[3] origin:100-dsp-mskpat 27_168
DSP_R.DSP48.DSP_1.PATTERN[40] origin:100-dsp-mskpat 27_295
DSP_R.DSP48.DSP_1.PATTERN[41] origin:100-dsp-mskpat 26_298
DSP_R.DSP48.DSP_1.PATTERN[42] origin:100-dsp-mskpat 26_304
DSP_R.DSP48.DSP_1.PATTERN[43] origin:100-dsp-mskpat 27_306
DSP_R.DSP48.DSP_1.PATTERN[44] origin:100-dsp-mskpat 26_308
DSP_R.DSP48.DSP_1.PATTERN[45] origin:100-dsp-mskpat 26_311
DSP_R.DSP48.DSP_1.PATTERN[46] origin:100-dsp-mskpat 27_312
DSP_R.DSP48.DSP_1.PATTERN[47] origin:100-dsp-mskpat 26_315
DSP_R.DSP48.DSP_1.PATTERN[4] origin:100-dsp-mskpat 26_169
DSP_R.DSP48.DSP_1.PATTERN[5] origin:100-dsp-mskpat 26_172
DSP_R.DSP48.DSP_1.PATTERN[6] origin:100-dsp-mskpat 27_177
DSP_R.DSP48.DSP_1.PATTERN[7] origin:100-dsp-mskpat 26_180
DSP_R.DSP48.DSP_1.PATTERN[8] origin:100-dsp-mskpat 27_181
DSP_R.DSP48.DSP_1.PATTERN[9] origin:100-dsp-mskpat 27_184

644
zynq7/segbits_hclk_cmt_l.origin_info.db Normal file
View File

@ -0,0 +1,644 @@
HCLK_CMT_L.HCLK_CMT_CCIO0_ACTIVE origin:045-hclk-cmt-pips 27_157 27_159
HCLK_CMT_L.HCLK_CMT_CCIO1_ACTIVE origin:045-hclk-cmt-pips 26_156 26_159
HCLK_CMT_L.HCLK_CMT_CCIO2_ACTIVE origin:045-hclk-cmt-pips 27_158 28_217
HCLK_CMT_L.HCLK_CMT_CCIO3_ACTIVE origin:045-hclk-cmt-pips 26_158 29_218
HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK0_ACTIVE origin:045-hclk-cmt-pips 27_185
HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK10_ACTIVE origin:045-hclk-cmt-pips 28_186
HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK11_ACTIVE origin:045-hclk-cmt-pips 29_186
HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK1_ACTIVE origin:045-hclk-cmt-pips 26_185
HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK2_ACTIVE origin:045-hclk-cmt-pips 27_184
HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK3_ACTIVE origin:045-hclk-cmt-pips 26_184
HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK4_ACTIVE origin:045-hclk-cmt-pips 27_183
HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK5_ACTIVE origin:045-hclk-cmt-pips 26_183
HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK6_ACTIVE origin:045-hclk-cmt-pips 27_182
HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK7_ACTIVE origin:045-hclk-cmt-pips 26_182
HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK8_ACTIVE origin:045-hclk-cmt-pips 27_181
HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK9_ACTIVE origin:045-hclk-cmt-pips 26_181
HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK0_ACTIVE origin:045-hclk-cmt-pips 28_174
HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK1_ACTIVE origin:045-hclk-cmt-pips 29_174
HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK2_ACTIVE origin:045-hclk-cmt-pips 28_175
HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK3_ACTIVE origin:045-hclk-cmt-pips 29_175
HCLK_CMT_L.HCLK_CMT_CK_IN0.HCLK_CMT_CCIO0 origin:045-hclk-cmt-pips 27_151 27_153
HCLK_CMT_L.HCLK_CMT_CK_IN0.HCLK_CMT_CCIO1 origin:045-hclk-cmt-pips 26_153 27_151
HCLK_CMT_L.HCLK_CMT_CK_IN0.HCLK_CMT_CCIO2 origin:045-hclk-cmt-pips 26_152 27_153
HCLK_CMT_L.HCLK_CMT_CK_IN0.HCLK_CMT_CCIO3 origin:045-hclk-cmt-pips 26_152 26_153
HCLK_CMT_L.HCLK_CMT_CK_IN0.HCLK_CMT_CK_BUFHCLK0 origin:045-hclk-cmt-pips 27_150 27_155
HCLK_CMT_L.HCLK_CMT_CK_IN0.HCLK_CMT_CK_BUFHCLK1 origin:045-hclk-cmt-pips 26_155 27_150
HCLK_CMT_L.HCLK_CMT_CK_IN0.HCLK_CMT_CK_BUFHCLK10 origin:045-hclk-cmt-pips 26_151 27_153
HCLK_CMT_L.HCLK_CMT_CK_IN0.HCLK_CMT_CK_BUFHCLK11 origin:045-hclk-cmt-pips 26_151 26_153
HCLK_CMT_L.HCLK_CMT_CK_IN0.HCLK_CMT_CK_BUFHCLK2 origin:045-hclk-cmt-pips 27_150 27_154
HCLK_CMT_L.HCLK_CMT_CK_IN0.HCLK_CMT_CK_BUFHCLK3 origin:045-hclk-cmt-pips 26_154 27_150
HCLK_CMT_L.HCLK_CMT_CK_IN0.HCLK_CMT_CK_BUFHCLK4 origin:045-hclk-cmt-pips 27_150 27_153
HCLK_CMT_L.HCLK_CMT_CK_IN0.HCLK_CMT_CK_BUFHCLK5 origin:045-hclk-cmt-pips 26_153 27_150
HCLK_CMT_L.HCLK_CMT_CK_IN0.HCLK_CMT_CK_BUFHCLK6 origin:045-hclk-cmt-pips 26_151 27_155
HCLK_CMT_L.HCLK_CMT_CK_IN0.HCLK_CMT_CK_BUFHCLK7 origin:045-hclk-cmt-pips 26_151 26_155
HCLK_CMT_L.HCLK_CMT_CK_IN0.HCLK_CMT_CK_BUFHCLK8 origin:045-hclk-cmt-pips 26_151 27_154
HCLK_CMT_L.HCLK_CMT_CK_IN0.HCLK_CMT_CK_BUFHCLK9 origin:045-hclk-cmt-pips 26_151 26_154
HCLK_CMT_L.HCLK_CMT_CK_IN0.HCLK_CMT_MUX_CLK_MMCM0 origin:045-hclk-cmt-pips 27_149 27_154
HCLK_CMT_L.HCLK_CMT_CK_IN0.HCLK_CMT_MUX_CLK_MMCM1 origin:045-hclk-cmt-pips 26_154 27_149
HCLK_CMT_L.HCLK_CMT_CK_IN0.HCLK_CMT_MUX_CLK_MMCM10 origin:045-hclk-cmt-pips 27_151 27_155
HCLK_CMT_L.HCLK_CMT_CK_IN0.HCLK_CMT_MUX_CLK_MMCM11 origin:045-hclk-cmt-pips 26_155 27_151
HCLK_CMT_L.HCLK_CMT_CK_IN0.HCLK_CMT_MUX_CLK_MMCM12 origin:045-hclk-cmt-pips 27_151 27_154
HCLK_CMT_L.HCLK_CMT_CK_IN0.HCLK_CMT_MUX_CLK_MMCM2 origin:045-hclk-cmt-pips 27_149 27_153
HCLK_CMT_L.HCLK_CMT_CK_IN0.HCLK_CMT_MUX_CLK_MMCM3 origin:045-hclk-cmt-pips 26_153 27_149
HCLK_CMT_L.HCLK_CMT_CK_IN0.HCLK_CMT_MUX_CLK_MMCM4 origin:045-hclk-cmt-pips 26_150 27_155
HCLK_CMT_L.HCLK_CMT_CK_IN0.HCLK_CMT_MUX_CLK_MMCM5 origin:045-hclk-cmt-pips 26_150 26_155
HCLK_CMT_L.HCLK_CMT_CK_IN0.HCLK_CMT_MUX_CLK_MMCM6 origin:045-hclk-cmt-pips 26_150 27_154
HCLK_CMT_L.HCLK_CMT_CK_IN0.HCLK_CMT_MUX_CLK_MMCM7 origin:045-hclk-cmt-pips 26_150 26_154
HCLK_CMT_L.HCLK_CMT_CK_IN0.HCLK_CMT_MUX_CLK_MMCM8 origin:045-hclk-cmt-pips 26_150 27_153
HCLK_CMT_L.HCLK_CMT_CK_IN0.HCLK_CMT_MUX_CLK_MMCM9 origin:045-hclk-cmt-pips 26_150 26_153
HCLK_CMT_L.HCLK_CMT_CK_IN0.HCLK_CMT_MUX_CLK_PLL0 origin:045-hclk-cmt-pips 26_149 27_155
HCLK_CMT_L.HCLK_CMT_CK_IN0.HCLK_CMT_MUX_CLK_PLL1 origin:045-hclk-cmt-pips 26_149 26_155
HCLK_CMT_L.HCLK_CMT_CK_IN0.HCLK_CMT_MUX_CLK_PLL2 origin:045-hclk-cmt-pips 26_149 27_154
HCLK_CMT_L.HCLK_CMT_CK_IN0.HCLK_CMT_MUX_CLK_PLL3 origin:045-hclk-cmt-pips 26_149 26_154
HCLK_CMT_L.HCLK_CMT_CK_IN0.HCLK_CMT_MUX_CLK_PLL4 origin:045-hclk-cmt-pips 26_149 27_153
HCLK_CMT_L.HCLK_CMT_CK_IN0.HCLK_CMT_MUX_CLK_PLL5 origin:045-hclk-cmt-pips 26_149 26_153
HCLK_CMT_L.HCLK_CMT_CK_IN0.HCLK_CMT_MUX_CLK_PLL6 origin:045-hclk-cmt-pips 27_149 27_155
HCLK_CMT_L.HCLK_CMT_CK_IN1.HCLK_CMT_CCIO0 origin:045-hclk-cmt-pips 29_151 29_153
HCLK_CMT_L.HCLK_CMT_CK_IN1.HCLK_CMT_CCIO1 origin:045-hclk-cmt-pips 28_153 29_151
HCLK_CMT_L.HCLK_CMT_CK_IN1.HCLK_CMT_CCIO2 origin:045-hclk-cmt-pips 28_152 29_153
HCLK_CMT_L.HCLK_CMT_CK_IN1.HCLK_CMT_CCIO3 origin:045-hclk-cmt-pips 28_152 28_153
HCLK_CMT_L.HCLK_CMT_CK_IN1.HCLK_CMT_CK_BUFHCLK0 origin:045-hclk-cmt-pips 29_150 29_155
HCLK_CMT_L.HCLK_CMT_CK_IN1.HCLK_CMT_CK_BUFHCLK1 origin:045-hclk-cmt-pips 28_155 29_150
HCLK_CMT_L.HCLK_CMT_CK_IN1.HCLK_CMT_CK_BUFHCLK10 origin:045-hclk-cmt-pips 28_151 29_153
HCLK_CMT_L.HCLK_CMT_CK_IN1.HCLK_CMT_CK_BUFHCLK11 origin:045-hclk-cmt-pips 28_151 28_153
HCLK_CMT_L.HCLK_CMT_CK_IN1.HCLK_CMT_CK_BUFHCLK2 origin:045-hclk-cmt-pips 29_150 29_154
HCLK_CMT_L.HCLK_CMT_CK_IN1.HCLK_CMT_CK_BUFHCLK3 origin:045-hclk-cmt-pips 28_154 29_150
HCLK_CMT_L.HCLK_CMT_CK_IN1.HCLK_CMT_CK_BUFHCLK4 origin:045-hclk-cmt-pips 29_150 29_153
HCLK_CMT_L.HCLK_CMT_CK_IN1.HCLK_CMT_CK_BUFHCLK5 origin:045-hclk-cmt-pips 28_153 29_150
HCLK_CMT_L.HCLK_CMT_CK_IN1.HCLK_CMT_CK_BUFHCLK6 origin:045-hclk-cmt-pips 28_151 29_155
HCLK_CMT_L.HCLK_CMT_CK_IN1.HCLK_CMT_CK_BUFHCLK7 origin:045-hclk-cmt-pips 28_151 28_155
HCLK_CMT_L.HCLK_CMT_CK_IN1.HCLK_CMT_CK_BUFHCLK8 origin:045-hclk-cmt-pips 28_151 29_154
HCLK_CMT_L.HCLK_CMT_CK_IN1.HCLK_CMT_CK_BUFHCLK9 origin:045-hclk-cmt-pips 28_151 28_154
HCLK_CMT_L.HCLK_CMT_CK_IN1.HCLK_CMT_MUX_CLK_MMCM0 origin:045-hclk-cmt-pips 29_149 29_154
HCLK_CMT_L.HCLK_CMT_CK_IN1.HCLK_CMT_MUX_CLK_MMCM1 origin:045-hclk-cmt-pips 28_154 29_149
HCLK_CMT_L.HCLK_CMT_CK_IN1.HCLK_CMT_MUX_CLK_MMCM10 origin:045-hclk-cmt-pips 29_151 29_155
HCLK_CMT_L.HCLK_CMT_CK_IN1.HCLK_CMT_MUX_CLK_MMCM11 origin:045-hclk-cmt-pips 28_155 29_151
HCLK_CMT_L.HCLK_CMT_CK_IN1.HCLK_CMT_MUX_CLK_MMCM12 origin:045-hclk-cmt-pips 29_151 29_154
HCLK_CMT_L.HCLK_CMT_CK_IN1.HCLK_CMT_MUX_CLK_MMCM2 origin:045-hclk-cmt-pips 29_149 29_153
HCLK_CMT_L.HCLK_CMT_CK_IN1.HCLK_CMT_MUX_CLK_MMCM3 origin:045-hclk-cmt-pips 28_153 29_149
HCLK_CMT_L.HCLK_CMT_CK_IN1.HCLK_CMT_MUX_CLK_MMCM4 origin:045-hclk-cmt-pips 28_150 29_155
HCLK_CMT_L.HCLK_CMT_CK_IN1.HCLK_CMT_MUX_CLK_MMCM5 origin:045-hclk-cmt-pips 28_150 28_155
HCLK_CMT_L.HCLK_CMT_CK_IN1.HCLK_CMT_MUX_CLK_MMCM6 origin:045-hclk-cmt-pips 28_150 29_154
HCLK_CMT_L.HCLK_CMT_CK_IN1.HCLK_CMT_MUX_CLK_MMCM7 origin:045-hclk-cmt-pips 28_150 28_154
HCLK_CMT_L.HCLK_CMT_CK_IN1.HCLK_CMT_MUX_CLK_MMCM8 origin:045-hclk-cmt-pips 28_150 29_153
HCLK_CMT_L.HCLK_CMT_CK_IN1.HCLK_CMT_MUX_CLK_MMCM9 origin:045-hclk-cmt-pips 28_150 28_153
HCLK_CMT_L.HCLK_CMT_CK_IN1.HCLK_CMT_MUX_CLK_PLL0 origin:045-hclk-cmt-pips 28_149 29_155
HCLK_CMT_L.HCLK_CMT_CK_IN1.HCLK_CMT_MUX_CLK_PLL1 origin:045-hclk-cmt-pips 28_149 28_155
HCLK_CMT_L.HCLK_CMT_CK_IN1.HCLK_CMT_MUX_CLK_PLL2 origin:045-hclk-cmt-pips 28_149 29_154
HCLK_CMT_L.HCLK_CMT_CK_IN1.HCLK_CMT_MUX_CLK_PLL3 origin:045-hclk-cmt-pips 28_149 28_154
HCLK_CMT_L.HCLK_CMT_CK_IN1.HCLK_CMT_MUX_CLK_PLL4 origin:045-hclk-cmt-pips 28_149 29_153
HCLK_CMT_L.HCLK_CMT_CK_IN1.HCLK_CMT_MUX_CLK_PLL5 origin:045-hclk-cmt-pips 28_149 28_153
HCLK_CMT_L.HCLK_CMT_CK_IN1.HCLK_CMT_MUX_CLK_PLL6 origin:045-hclk-cmt-pips 29_149 29_155
HCLK_CMT_L.HCLK_CMT_CK_IN10.HCLK_CMT_CCIO0 origin:045-hclk-cmt-pips 28_205 28_207
HCLK_CMT_L.HCLK_CMT_CK_IN10.HCLK_CMT_CCIO1 origin:045-hclk-cmt-pips 28_207 29_205
HCLK_CMT_L.HCLK_CMT_CK_IN10.HCLK_CMT_CCIO2 origin:045-hclk-cmt-pips 28_205 29_206
HCLK_CMT_L.HCLK_CMT_CK_IN10.HCLK_CMT_CCIO3 origin:045-hclk-cmt-pips 29_205 29_206
HCLK_CMT_L.HCLK_CMT_CK_IN10.HCLK_CMT_CK_BUFHCLK0 origin:045-hclk-cmt-pips 28_203 28_208
HCLK_CMT_L.HCLK_CMT_CK_IN10.HCLK_CMT_CK_BUFHCLK1 origin:045-hclk-cmt-pips 28_208 29_203
HCLK_CMT_L.HCLK_CMT_CK_IN10.HCLK_CMT_CK_BUFHCLK10 origin:045-hclk-cmt-pips 28_205 29_207
HCLK_CMT_L.HCLK_CMT_CK_IN10.HCLK_CMT_CK_BUFHCLK11 origin:045-hclk-cmt-pips 29_205 29_207
HCLK_CMT_L.HCLK_CMT_CK_IN10.HCLK_CMT_CK_BUFHCLK2 origin:045-hclk-cmt-pips 28_204 28_208
HCLK_CMT_L.HCLK_CMT_CK_IN10.HCLK_CMT_CK_BUFHCLK3 origin:045-hclk-cmt-pips 28_208 29_204
HCLK_CMT_L.HCLK_CMT_CK_IN10.HCLK_CMT_CK_BUFHCLK4 origin:045-hclk-cmt-pips 28_205 28_208
HCLK_CMT_L.HCLK_CMT_CK_IN10.HCLK_CMT_CK_BUFHCLK5 origin:045-hclk-cmt-pips 28_208 29_205
HCLK_CMT_L.HCLK_CMT_CK_IN10.HCLK_CMT_CK_BUFHCLK6 origin:045-hclk-cmt-pips 28_203 29_207
HCLK_CMT_L.HCLK_CMT_CK_IN10.HCLK_CMT_CK_BUFHCLK7 origin:045-hclk-cmt-pips 29_203 29_207
HCLK_CMT_L.HCLK_CMT_CK_IN10.HCLK_CMT_CK_BUFHCLK8 origin:045-hclk-cmt-pips 28_204 29_207
HCLK_CMT_L.HCLK_CMT_CK_IN10.HCLK_CMT_CK_BUFHCLK9 origin:045-hclk-cmt-pips 29_204 29_207
HCLK_CMT_L.HCLK_CMT_CK_IN10.HCLK_CMT_MUX_CLK_MMCM0 origin:045-hclk-cmt-pips 28_204 28_209
HCLK_CMT_L.HCLK_CMT_CK_IN10.HCLK_CMT_MUX_CLK_MMCM1 origin:045-hclk-cmt-pips 28_209 29_204
HCLK_CMT_L.HCLK_CMT_CK_IN10.HCLK_CMT_MUX_CLK_MMCM10 origin:045-hclk-cmt-pips 28_203 28_207
HCLK_CMT_L.HCLK_CMT_CK_IN10.HCLK_CMT_MUX_CLK_MMCM11 origin:045-hclk-cmt-pips 28_207 29_203
HCLK_CMT_L.HCLK_CMT_CK_IN10.HCLK_CMT_MUX_CLK_MMCM12 origin:045-hclk-cmt-pips 28_204 28_207
HCLK_CMT_L.HCLK_CMT_CK_IN10.HCLK_CMT_MUX_CLK_MMCM2 origin:045-hclk-cmt-pips 28_205 28_209
HCLK_CMT_L.HCLK_CMT_CK_IN10.HCLK_CMT_MUX_CLK_MMCM3 origin:045-hclk-cmt-pips 28_209 29_205
HCLK_CMT_L.HCLK_CMT_CK_IN10.HCLK_CMT_MUX_CLK_MMCM4 origin:045-hclk-cmt-pips 28_203 29_208
HCLK_CMT_L.HCLK_CMT_CK_IN10.HCLK_CMT_MUX_CLK_MMCM5 origin:045-hclk-cmt-pips 29_203 29_208
HCLK_CMT_L.HCLK_CMT_CK_IN10.HCLK_CMT_MUX_CLK_MMCM6 origin:045-hclk-cmt-pips 28_204 29_208
HCLK_CMT_L.HCLK_CMT_CK_IN10.HCLK_CMT_MUX_CLK_MMCM7 origin:045-hclk-cmt-pips 29_204 29_208
HCLK_CMT_L.HCLK_CMT_CK_IN10.HCLK_CMT_MUX_CLK_MMCM8 origin:045-hclk-cmt-pips 28_205 29_208
HCLK_CMT_L.HCLK_CMT_CK_IN10.HCLK_CMT_MUX_CLK_MMCM9 origin:045-hclk-cmt-pips 29_205 29_208
HCLK_CMT_L.HCLK_CMT_CK_IN10.HCLK_CMT_MUX_CLK_PLL0 origin:045-hclk-cmt-pips 28_203 29_209
HCLK_CMT_L.HCLK_CMT_CK_IN10.HCLK_CMT_MUX_CLK_PLL1 origin:045-hclk-cmt-pips 29_203 29_209
HCLK_CMT_L.HCLK_CMT_CK_IN10.HCLK_CMT_MUX_CLK_PLL2 origin:045-hclk-cmt-pips 28_204 29_209
HCLK_CMT_L.HCLK_CMT_CK_IN10.HCLK_CMT_MUX_CLK_PLL3 origin:045-hclk-cmt-pips 29_204 29_209
HCLK_CMT_L.HCLK_CMT_CK_IN10.HCLK_CMT_MUX_CLK_PLL4 origin:045-hclk-cmt-pips 28_205 29_209
HCLK_CMT_L.HCLK_CMT_CK_IN10.HCLK_CMT_MUX_CLK_PLL5 origin:045-hclk-cmt-pips 29_205 29_209
HCLK_CMT_L.HCLK_CMT_CK_IN10.HCLK_CMT_MUX_CLK_PLL6 origin:045-hclk-cmt-pips 28_203 28_209
HCLK_CMT_L.HCLK_CMT_CK_IN11.HCLK_CMT_CCIO0 origin:045-hclk-cmt-pips 26_212 26_214
HCLK_CMT_L.HCLK_CMT_CK_IN11.HCLK_CMT_CCIO1 origin:045-hclk-cmt-pips 26_214 27_212
HCLK_CMT_L.HCLK_CMT_CK_IN11.HCLK_CMT_CCIO2 origin:045-hclk-cmt-pips 26_212 27_213
HCLK_CMT_L.HCLK_CMT_CK_IN11.HCLK_CMT_CCIO3 origin:045-hclk-cmt-pips 27_212 27_213
HCLK_CMT_L.HCLK_CMT_CK_IN11.HCLK_CMT_CK_BUFHCLK0 origin:045-hclk-cmt-pips 26_210 26_215
HCLK_CMT_L.HCLK_CMT_CK_IN11.HCLK_CMT_CK_BUFHCLK1 origin:045-hclk-cmt-pips 26_215 27_210
HCLK_CMT_L.HCLK_CMT_CK_IN11.HCLK_CMT_CK_BUFHCLK10 origin:045-hclk-cmt-pips 26_212 27_214
HCLK_CMT_L.HCLK_CMT_CK_IN11.HCLK_CMT_CK_BUFHCLK11 origin:045-hclk-cmt-pips 27_212 27_214
HCLK_CMT_L.HCLK_CMT_CK_IN11.HCLK_CMT_CK_BUFHCLK2 origin:045-hclk-cmt-pips 26_211 26_215
HCLK_CMT_L.HCLK_CMT_CK_IN11.HCLK_CMT_CK_BUFHCLK3 origin:045-hclk-cmt-pips 26_215 27_211
HCLK_CMT_L.HCLK_CMT_CK_IN11.HCLK_CMT_CK_BUFHCLK4 origin:045-hclk-cmt-pips 26_212 26_215
HCLK_CMT_L.HCLK_CMT_CK_IN11.HCLK_CMT_CK_BUFHCLK5 origin:045-hclk-cmt-pips 26_215 27_212
HCLK_CMT_L.HCLK_CMT_CK_IN11.HCLK_CMT_CK_BUFHCLK6 origin:045-hclk-cmt-pips 26_210 27_214
HCLK_CMT_L.HCLK_CMT_CK_IN11.HCLK_CMT_CK_BUFHCLK7 origin:045-hclk-cmt-pips 27_210 27_214
HCLK_CMT_L.HCLK_CMT_CK_IN11.HCLK_CMT_CK_BUFHCLK8 origin:045-hclk-cmt-pips 26_211 27_214
HCLK_CMT_L.HCLK_CMT_CK_IN11.HCLK_CMT_CK_BUFHCLK9 origin:045-hclk-cmt-pips 27_211 27_214
HCLK_CMT_L.HCLK_CMT_CK_IN11.HCLK_CMT_MUX_CLK_MMCM0 origin:045-hclk-cmt-pips 26_211 26_216
HCLK_CMT_L.HCLK_CMT_CK_IN11.HCLK_CMT_MUX_CLK_MMCM1 origin:045-hclk-cmt-pips 26_216 27_211
HCLK_CMT_L.HCLK_CMT_CK_IN11.HCLK_CMT_MUX_CLK_MMCM10 origin:045-hclk-cmt-pips 26_210 26_214
HCLK_CMT_L.HCLK_CMT_CK_IN11.HCLK_CMT_MUX_CLK_MMCM11 origin:045-hclk-cmt-pips 26_214 27_210
HCLK_CMT_L.HCLK_CMT_CK_IN11.HCLK_CMT_MUX_CLK_MMCM12 origin:045-hclk-cmt-pips 26_211 26_214
HCLK_CMT_L.HCLK_CMT_CK_IN11.HCLK_CMT_MUX_CLK_MMCM2 origin:045-hclk-cmt-pips 26_212 26_216
HCLK_CMT_L.HCLK_CMT_CK_IN11.HCLK_CMT_MUX_CLK_MMCM3 origin:045-hclk-cmt-pips 26_216 27_212
HCLK_CMT_L.HCLK_CMT_CK_IN11.HCLK_CMT_MUX_CLK_MMCM4 origin:045-hclk-cmt-pips 26_210 27_215
HCLK_CMT_L.HCLK_CMT_CK_IN11.HCLK_CMT_MUX_CLK_MMCM5 origin:045-hclk-cmt-pips 27_210 27_215
HCLK_CMT_L.HCLK_CMT_CK_IN11.HCLK_CMT_MUX_CLK_MMCM6 origin:045-hclk-cmt-pips 26_211 27_215
HCLK_CMT_L.HCLK_CMT_CK_IN11.HCLK_CMT_MUX_CLK_MMCM7 origin:045-hclk-cmt-pips 27_211 27_215
HCLK_CMT_L.HCLK_CMT_CK_IN11.HCLK_CMT_MUX_CLK_MMCM8 origin:045-hclk-cmt-pips 26_212 27_215
HCLK_CMT_L.HCLK_CMT_CK_IN11.HCLK_CMT_MUX_CLK_MMCM9 origin:045-hclk-cmt-pips 27_212 27_215
HCLK_CMT_L.HCLK_CMT_CK_IN11.HCLK_CMT_MUX_CLK_PLL0 origin:045-hclk-cmt-pips 26_210 27_216
HCLK_CMT_L.HCLK_CMT_CK_IN11.HCLK_CMT_MUX_CLK_PLL1 origin:045-hclk-cmt-pips 27_210 27_216
HCLK_CMT_L.HCLK_CMT_CK_IN11.HCLK_CMT_MUX_CLK_PLL2 origin:045-hclk-cmt-pips 26_211 27_216
HCLK_CMT_L.HCLK_CMT_CK_IN11.HCLK_CMT_MUX_CLK_PLL3 origin:045-hclk-cmt-pips 27_211 27_216
HCLK_CMT_L.HCLK_CMT_CK_IN11.HCLK_CMT_MUX_CLK_PLL4 origin:045-hclk-cmt-pips 26_212 27_216
HCLK_CMT_L.HCLK_CMT_CK_IN11.HCLK_CMT_MUX_CLK_PLL5 origin:045-hclk-cmt-pips 27_212 27_216
HCLK_CMT_L.HCLK_CMT_CK_IN11.HCLK_CMT_MUX_CLK_PLL6 origin:045-hclk-cmt-pips 26_210 26_216
HCLK_CMT_L.HCLK_CMT_CK_IN12.HCLK_CMT_CCIO0 origin:045-hclk-cmt-pips 28_212 28_214
HCLK_CMT_L.HCLK_CMT_CK_IN12.HCLK_CMT_CCIO1 origin:045-hclk-cmt-pips 28_214 29_212
HCLK_CMT_L.HCLK_CMT_CK_IN12.HCLK_CMT_CCIO2 origin:045-hclk-cmt-pips 28_212 29_213
HCLK_CMT_L.HCLK_CMT_CK_IN12.HCLK_CMT_CCIO3 origin:045-hclk-cmt-pips 29_212 29_213
HCLK_CMT_L.HCLK_CMT_CK_IN12.HCLK_CMT_CK_BUFHCLK0 origin:045-hclk-cmt-pips 28_210 28_215
HCLK_CMT_L.HCLK_CMT_CK_IN12.HCLK_CMT_CK_BUFHCLK1 origin:045-hclk-cmt-pips 28_215 29_210
HCLK_CMT_L.HCLK_CMT_CK_IN12.HCLK_CMT_CK_BUFHCLK10 origin:045-hclk-cmt-pips 28_212 29_214
HCLK_CMT_L.HCLK_CMT_CK_IN12.HCLK_CMT_CK_BUFHCLK11 origin:045-hclk-cmt-pips 29_212 29_214
HCLK_CMT_L.HCLK_CMT_CK_IN12.HCLK_CMT_CK_BUFHCLK2 origin:045-hclk-cmt-pips 28_211 28_215
HCLK_CMT_L.HCLK_CMT_CK_IN12.HCLK_CMT_CK_BUFHCLK3 origin:045-hclk-cmt-pips 28_215 29_211
HCLK_CMT_L.HCLK_CMT_CK_IN12.HCLK_CMT_CK_BUFHCLK4 origin:045-hclk-cmt-pips 28_212 28_215
HCLK_CMT_L.HCLK_CMT_CK_IN12.HCLK_CMT_CK_BUFHCLK5 origin:045-hclk-cmt-pips 28_215 29_212
HCLK_CMT_L.HCLK_CMT_CK_IN12.HCLK_CMT_CK_BUFHCLK6 origin:045-hclk-cmt-pips 28_210 29_214
HCLK_CMT_L.HCLK_CMT_CK_IN12.HCLK_CMT_CK_BUFHCLK7 origin:045-hclk-cmt-pips 29_210 29_214
HCLK_CMT_L.HCLK_CMT_CK_IN12.HCLK_CMT_CK_BUFHCLK8 origin:045-hclk-cmt-pips 28_211 29_214
HCLK_CMT_L.HCLK_CMT_CK_IN12.HCLK_CMT_CK_BUFHCLK9 origin:045-hclk-cmt-pips 29_211 29_214
HCLK_CMT_L.HCLK_CMT_CK_IN12.HCLK_CMT_MUX_CLK_MMCM0 origin:045-hclk-cmt-pips 28_211 28_216
HCLK_CMT_L.HCLK_CMT_CK_IN12.HCLK_CMT_MUX_CLK_MMCM1 origin:045-hclk-cmt-pips 28_216 29_211
HCLK_CMT_L.HCLK_CMT_CK_IN12.HCLK_CMT_MUX_CLK_MMCM10 origin:045-hclk-cmt-pips 28_210 28_214
HCLK_CMT_L.HCLK_CMT_CK_IN12.HCLK_CMT_MUX_CLK_MMCM11 origin:045-hclk-cmt-pips 28_214 29_210
HCLK_CMT_L.HCLK_CMT_CK_IN12.HCLK_CMT_MUX_CLK_MMCM12 origin:045-hclk-cmt-pips 28_211 28_214
HCLK_CMT_L.HCLK_CMT_CK_IN12.HCLK_CMT_MUX_CLK_MMCM2 origin:045-hclk-cmt-pips 28_212 28_216
HCLK_CMT_L.HCLK_CMT_CK_IN12.HCLK_CMT_MUX_CLK_MMCM3 origin:045-hclk-cmt-pips 28_216 29_212
HCLK_CMT_L.HCLK_CMT_CK_IN12.HCLK_CMT_MUX_CLK_MMCM4 origin:045-hclk-cmt-pips 28_210 29_215
HCLK_CMT_L.HCLK_CMT_CK_IN12.HCLK_CMT_MUX_CLK_MMCM5 origin:045-hclk-cmt-pips 29_210 29_215
HCLK_CMT_L.HCLK_CMT_CK_IN12.HCLK_CMT_MUX_CLK_MMCM6 origin:045-hclk-cmt-pips 28_211 29_215
HCLK_CMT_L.HCLK_CMT_CK_IN12.HCLK_CMT_MUX_CLK_MMCM7 origin:045-hclk-cmt-pips 29_211 29_215
HCLK_CMT_L.HCLK_CMT_CK_IN12.HCLK_CMT_MUX_CLK_MMCM8 origin:045-hclk-cmt-pips 28_212 29_215
HCLK_CMT_L.HCLK_CMT_CK_IN12.HCLK_CMT_MUX_CLK_MMCM9 origin:045-hclk-cmt-pips 29_212 29_215
HCLK_CMT_L.HCLK_CMT_CK_IN12.HCLK_CMT_MUX_CLK_PLL0 origin:045-hclk-cmt-pips 28_210 29_216
HCLK_CMT_L.HCLK_CMT_CK_IN12.HCLK_CMT_MUX_CLK_PLL1 origin:045-hclk-cmt-pips 29_210 29_216
HCLK_CMT_L.HCLK_CMT_CK_IN12.HCLK_CMT_MUX_CLK_PLL2 origin:045-hclk-cmt-pips 28_211 29_216
HCLK_CMT_L.HCLK_CMT_CK_IN12.HCLK_CMT_MUX_CLK_PLL3 origin:045-hclk-cmt-pips 29_211 29_216
HCLK_CMT_L.HCLK_CMT_CK_IN12.HCLK_CMT_MUX_CLK_PLL4 origin:045-hclk-cmt-pips 28_212 29_216
HCLK_CMT_L.HCLK_CMT_CK_IN12.HCLK_CMT_MUX_CLK_PLL5 origin:045-hclk-cmt-pips 29_212 29_216
HCLK_CMT_L.HCLK_CMT_CK_IN12.HCLK_CMT_MUX_CLK_PLL6 origin:045-hclk-cmt-pips 28_210 28_216
HCLK_CMT_L.HCLK_CMT_CK_IN13.HCLK_CMT_CCIO0 origin:045-hclk-cmt-pips 26_219 26_221
HCLK_CMT_L.HCLK_CMT_CK_IN13.HCLK_CMT_CCIO1 origin:045-hclk-cmt-pips 26_221 27_219
HCLK_CMT_L.HCLK_CMT_CK_IN13.HCLK_CMT_CCIO2 origin:045-hclk-cmt-pips 26_219 27_220
HCLK_CMT_L.HCLK_CMT_CK_IN13.HCLK_CMT_CCIO3 origin:045-hclk-cmt-pips 27_219 27_220
HCLK_CMT_L.HCLK_CMT_CK_IN13.HCLK_CMT_CK_BUFHCLK0 origin:045-hclk-cmt-pips 26_217 26_222
HCLK_CMT_L.HCLK_CMT_CK_IN13.HCLK_CMT_CK_BUFHCLK1 origin:045-hclk-cmt-pips 26_222 27_217
HCLK_CMT_L.HCLK_CMT_CK_IN13.HCLK_CMT_CK_BUFHCLK10 origin:045-hclk-cmt-pips 26_219 27_221
HCLK_CMT_L.HCLK_CMT_CK_IN13.HCLK_CMT_CK_BUFHCLK11 origin:045-hclk-cmt-pips 27_219 27_221
HCLK_CMT_L.HCLK_CMT_CK_IN13.HCLK_CMT_CK_BUFHCLK2 origin:045-hclk-cmt-pips 26_218 26_222
HCLK_CMT_L.HCLK_CMT_CK_IN13.HCLK_CMT_CK_BUFHCLK3 origin:045-hclk-cmt-pips 26_222 27_218
HCLK_CMT_L.HCLK_CMT_CK_IN13.HCLK_CMT_CK_BUFHCLK4 origin:045-hclk-cmt-pips 26_219 26_222
HCLK_CMT_L.HCLK_CMT_CK_IN13.HCLK_CMT_CK_BUFHCLK5 origin:045-hclk-cmt-pips 26_222 27_219
HCLK_CMT_L.HCLK_CMT_CK_IN13.HCLK_CMT_CK_BUFHCLK6 origin:045-hclk-cmt-pips 26_217 27_221
HCLK_CMT_L.HCLK_CMT_CK_IN13.HCLK_CMT_CK_BUFHCLK7 origin:045-hclk-cmt-pips 27_217 27_221
HCLK_CMT_L.HCLK_CMT_CK_IN13.HCLK_CMT_CK_BUFHCLK8 origin:045-hclk-cmt-pips 26_218 27_221
HCLK_CMT_L.HCLK_CMT_CK_IN13.HCLK_CMT_CK_BUFHCLK9 origin:045-hclk-cmt-pips 27_218 27_221
HCLK_CMT_L.HCLK_CMT_CK_IN13.HCLK_CMT_MUX_CLK_MMCM0 origin:045-hclk-cmt-pips 26_218 26_223
HCLK_CMT_L.HCLK_CMT_CK_IN13.HCLK_CMT_MUX_CLK_MMCM1 origin:045-hclk-cmt-pips 26_223 27_218
HCLK_CMT_L.HCLK_CMT_CK_IN13.HCLK_CMT_MUX_CLK_MMCM10 origin:045-hclk-cmt-pips 26_217 26_221
HCLK_CMT_L.HCLK_CMT_CK_IN13.HCLK_CMT_MUX_CLK_MMCM11 origin:045-hclk-cmt-pips 26_221 27_217
HCLK_CMT_L.HCLK_CMT_CK_IN13.HCLK_CMT_MUX_CLK_MMCM12 origin:045-hclk-cmt-pips 26_218 26_221
HCLK_CMT_L.HCLK_CMT_CK_IN13.HCLK_CMT_MUX_CLK_MMCM2 origin:045-hclk-cmt-pips 26_219 26_223
HCLK_CMT_L.HCLK_CMT_CK_IN13.HCLK_CMT_MUX_CLK_MMCM3 origin:045-hclk-cmt-pips 26_223 27_219
HCLK_CMT_L.HCLK_CMT_CK_IN13.HCLK_CMT_MUX_CLK_MMCM4 origin:045-hclk-cmt-pips 26_217 27_222
HCLK_CMT_L.HCLK_CMT_CK_IN13.HCLK_CMT_MUX_CLK_MMCM5 origin:045-hclk-cmt-pips 27_217 27_222
HCLK_CMT_L.HCLK_CMT_CK_IN13.HCLK_CMT_MUX_CLK_MMCM6 origin:045-hclk-cmt-pips 26_218 27_222
HCLK_CMT_L.HCLK_CMT_CK_IN13.HCLK_CMT_MUX_CLK_MMCM7 origin:045-hclk-cmt-pips 27_218 27_222
HCLK_CMT_L.HCLK_CMT_CK_IN13.HCLK_CMT_MUX_CLK_MMCM8 origin:045-hclk-cmt-pips 26_219 27_222
HCLK_CMT_L.HCLK_CMT_CK_IN13.HCLK_CMT_MUX_CLK_MMCM9 origin:045-hclk-cmt-pips 27_219 27_222
HCLK_CMT_L.HCLK_CMT_CK_IN13.HCLK_CMT_MUX_CLK_PLL0 origin:045-hclk-cmt-pips 26_217 27_223
HCLK_CMT_L.HCLK_CMT_CK_IN13.HCLK_CMT_MUX_CLK_PLL1 origin:045-hclk-cmt-pips 27_217 27_223
HCLK_CMT_L.HCLK_CMT_CK_IN13.HCLK_CMT_MUX_CLK_PLL2 origin:045-hclk-cmt-pips 26_218 27_223
HCLK_CMT_L.HCLK_CMT_CK_IN13.HCLK_CMT_MUX_CLK_PLL3 origin:045-hclk-cmt-pips 27_218 27_223
HCLK_CMT_L.HCLK_CMT_CK_IN13.HCLK_CMT_MUX_CLK_PLL4 origin:045-hclk-cmt-pips 26_219 27_223
HCLK_CMT_L.HCLK_CMT_CK_IN13.HCLK_CMT_MUX_CLK_PLL5 origin:045-hclk-cmt-pips 27_219 27_223
HCLK_CMT_L.HCLK_CMT_CK_IN13.HCLK_CMT_MUX_CLK_PLL6 origin:045-hclk-cmt-pips 26_217 26_223
HCLK_CMT_L.HCLK_CMT_CK_IN2.HCLK_CMT_CCIO0 origin:045-hclk-cmt-pips 27_144 27_146
HCLK_CMT_L.HCLK_CMT_CK_IN2.HCLK_CMT_CCIO1 origin:045-hclk-cmt-pips 26_146 27_144
HCLK_CMT_L.HCLK_CMT_CK_IN2.HCLK_CMT_CCIO2 origin:045-hclk-cmt-pips 26_145 27_146
HCLK_CMT_L.HCLK_CMT_CK_IN2.HCLK_CMT_CCIO3 origin:045-hclk-cmt-pips 26_145 26_146
HCLK_CMT_L.HCLK_CMT_CK_IN2.HCLK_CMT_CK_BUFHCLK0 origin:045-hclk-cmt-pips 27_143 27_148
HCLK_CMT_L.HCLK_CMT_CK_IN2.HCLK_CMT_CK_BUFHCLK1 origin:045-hclk-cmt-pips 26_148 27_143
HCLK_CMT_L.HCLK_CMT_CK_IN2.HCLK_CMT_CK_BUFHCLK10 origin:045-hclk-cmt-pips 26_144 27_146
HCLK_CMT_L.HCLK_CMT_CK_IN2.HCLK_CMT_CK_BUFHCLK11 origin:045-hclk-cmt-pips 26_144 26_146
HCLK_CMT_L.HCLK_CMT_CK_IN2.HCLK_CMT_CK_BUFHCLK2 origin:045-hclk-cmt-pips 27_143 27_147
HCLK_CMT_L.HCLK_CMT_CK_IN2.HCLK_CMT_CK_BUFHCLK3 origin:045-hclk-cmt-pips 26_147 27_143
HCLK_CMT_L.HCLK_CMT_CK_IN2.HCLK_CMT_CK_BUFHCLK4 origin:045-hclk-cmt-pips 27_143 27_146
HCLK_CMT_L.HCLK_CMT_CK_IN2.HCLK_CMT_CK_BUFHCLK5 origin:045-hclk-cmt-pips 26_146 27_143
HCLK_CMT_L.HCLK_CMT_CK_IN2.HCLK_CMT_CK_BUFHCLK6 origin:045-hclk-cmt-pips 26_144 27_148
HCLK_CMT_L.HCLK_CMT_CK_IN2.HCLK_CMT_CK_BUFHCLK7 origin:045-hclk-cmt-pips 26_144 26_148
HCLK_CMT_L.HCLK_CMT_CK_IN2.HCLK_CMT_CK_BUFHCLK8 origin:045-hclk-cmt-pips 26_144 27_147
HCLK_CMT_L.HCLK_CMT_CK_IN2.HCLK_CMT_CK_BUFHCLK9 origin:045-hclk-cmt-pips 26_144 26_147
HCLK_CMT_L.HCLK_CMT_CK_IN2.HCLK_CMT_MUX_CLK_MMCM0 origin:045-hclk-cmt-pips 27_142 27_147
HCLK_CMT_L.HCLK_CMT_CK_IN2.HCLK_CMT_MUX_CLK_MMCM1 origin:045-hclk-cmt-pips 26_147 27_142
HCLK_CMT_L.HCLK_CMT_CK_IN2.HCLK_CMT_MUX_CLK_MMCM10 origin:045-hclk-cmt-pips 27_144 27_148
HCLK_CMT_L.HCLK_CMT_CK_IN2.HCLK_CMT_MUX_CLK_MMCM11 origin:045-hclk-cmt-pips 26_148 27_144
HCLK_CMT_L.HCLK_CMT_CK_IN2.HCLK_CMT_MUX_CLK_MMCM12 origin:045-hclk-cmt-pips 27_144 27_147
HCLK_CMT_L.HCLK_CMT_CK_IN2.HCLK_CMT_MUX_CLK_MMCM2 origin:045-hclk-cmt-pips 27_142 27_146
HCLK_CMT_L.HCLK_CMT_CK_IN2.HCLK_CMT_MUX_CLK_MMCM3 origin:045-hclk-cmt-pips 26_146 27_142
HCLK_CMT_L.HCLK_CMT_CK_IN2.HCLK_CMT_MUX_CLK_MMCM4 origin:045-hclk-cmt-pips 26_143 27_148
HCLK_CMT_L.HCLK_CMT_CK_IN2.HCLK_CMT_MUX_CLK_MMCM5 origin:045-hclk-cmt-pips 26_143 26_148
HCLK_CMT_L.HCLK_CMT_CK_IN2.HCLK_CMT_MUX_CLK_MMCM6 origin:045-hclk-cmt-pips 26_143 27_147
HCLK_CMT_L.HCLK_CMT_CK_IN2.HCLK_CMT_MUX_CLK_MMCM7 origin:045-hclk-cmt-pips 26_143 26_147
HCLK_CMT_L.HCLK_CMT_CK_IN2.HCLK_CMT_MUX_CLK_MMCM8 origin:045-hclk-cmt-pips 26_143 27_146
HCLK_CMT_L.HCLK_CMT_CK_IN2.HCLK_CMT_MUX_CLK_MMCM9 origin:045-hclk-cmt-pips 26_143 26_146
HCLK_CMT_L.HCLK_CMT_CK_IN2.HCLK_CMT_MUX_CLK_PLL0 origin:045-hclk-cmt-pips 26_142 27_148
HCLK_CMT_L.HCLK_CMT_CK_IN2.HCLK_CMT_MUX_CLK_PLL1 origin:045-hclk-cmt-pips 26_142 26_148
HCLK_CMT_L.HCLK_CMT_CK_IN2.HCLK_CMT_MUX_CLK_PLL2 origin:045-hclk-cmt-pips 26_142 27_147
HCLK_CMT_L.HCLK_CMT_CK_IN2.HCLK_CMT_MUX_CLK_PLL3 origin:045-hclk-cmt-pips 26_142 26_147
HCLK_CMT_L.HCLK_CMT_CK_IN2.HCLK_CMT_MUX_CLK_PLL4 origin:045-hclk-cmt-pips 26_142 27_146
HCLK_CMT_L.HCLK_CMT_CK_IN2.HCLK_CMT_MUX_CLK_PLL5 origin:045-hclk-cmt-pips 26_142 26_146
HCLK_CMT_L.HCLK_CMT_CK_IN2.HCLK_CMT_MUX_CLK_PLL6 origin:045-hclk-cmt-pips 27_142 27_148
HCLK_CMT_L.HCLK_CMT_CK_IN3.HCLK_CMT_CCIO0 origin:045-hclk-cmt-pips 29_144 29_146
HCLK_CMT_L.HCLK_CMT_CK_IN3.HCLK_CMT_CCIO1 origin:045-hclk-cmt-pips 28_146 29_144
HCLK_CMT_L.HCLK_CMT_CK_IN3.HCLK_CMT_CCIO2 origin:045-hclk-cmt-pips 28_145 29_146
HCLK_CMT_L.HCLK_CMT_CK_IN3.HCLK_CMT_CCIO3 origin:045-hclk-cmt-pips 28_145 28_146
HCLK_CMT_L.HCLK_CMT_CK_IN3.HCLK_CMT_CK_BUFHCLK0 origin:045-hclk-cmt-pips 29_143 29_148
HCLK_CMT_L.HCLK_CMT_CK_IN3.HCLK_CMT_CK_BUFHCLK1 origin:045-hclk-cmt-pips 28_148 29_143
HCLK_CMT_L.HCLK_CMT_CK_IN3.HCLK_CMT_CK_BUFHCLK10 origin:045-hclk-cmt-pips 28_144 29_146
HCLK_CMT_L.HCLK_CMT_CK_IN3.HCLK_CMT_CK_BUFHCLK11 origin:045-hclk-cmt-pips 28_144 28_146
HCLK_CMT_L.HCLK_CMT_CK_IN3.HCLK_CMT_CK_BUFHCLK2 origin:045-hclk-cmt-pips 29_143 29_147
HCLK_CMT_L.HCLK_CMT_CK_IN3.HCLK_CMT_CK_BUFHCLK3 origin:045-hclk-cmt-pips 28_147 29_143
HCLK_CMT_L.HCLK_CMT_CK_IN3.HCLK_CMT_CK_BUFHCLK4 origin:045-hclk-cmt-pips 29_143 29_146
HCLK_CMT_L.HCLK_CMT_CK_IN3.HCLK_CMT_CK_BUFHCLK5 origin:045-hclk-cmt-pips 28_146 29_143
HCLK_CMT_L.HCLK_CMT_CK_IN3.HCLK_CMT_CK_BUFHCLK6 origin:045-hclk-cmt-pips 28_144 29_148
HCLK_CMT_L.HCLK_CMT_CK_IN3.HCLK_CMT_CK_BUFHCLK7 origin:045-hclk-cmt-pips 28_144 28_148
HCLK_CMT_L.HCLK_CMT_CK_IN3.HCLK_CMT_CK_BUFHCLK8 origin:045-hclk-cmt-pips 28_144 29_147
HCLK_CMT_L.HCLK_CMT_CK_IN3.HCLK_CMT_CK_BUFHCLK9 origin:045-hclk-cmt-pips 28_144 28_147
HCLK_CMT_L.HCLK_CMT_CK_IN3.HCLK_CMT_MUX_CLK_MMCM0 origin:045-hclk-cmt-pips 29_142 29_147
HCLK_CMT_L.HCLK_CMT_CK_IN3.HCLK_CMT_MUX_CLK_MMCM1 origin:045-hclk-cmt-pips 28_147 29_142
HCLK_CMT_L.HCLK_CMT_CK_IN3.HCLK_CMT_MUX_CLK_MMCM10 origin:045-hclk-cmt-pips 29_144 29_148
HCLK_CMT_L.HCLK_CMT_CK_IN3.HCLK_CMT_MUX_CLK_MMCM11 origin:045-hclk-cmt-pips 28_148 29_144
HCLK_CMT_L.HCLK_CMT_CK_IN3.HCLK_CMT_MUX_CLK_MMCM12 origin:045-hclk-cmt-pips 29_144 29_147
HCLK_CMT_L.HCLK_CMT_CK_IN3.HCLK_CMT_MUX_CLK_MMCM2 origin:045-hclk-cmt-pips 29_142 29_146
HCLK_CMT_L.HCLK_CMT_CK_IN3.HCLK_CMT_MUX_CLK_MMCM3 origin:045-hclk-cmt-pips 28_146 29_142
HCLK_CMT_L.HCLK_CMT_CK_IN3.HCLK_CMT_MUX_CLK_MMCM4 origin:045-hclk-cmt-pips 28_143 29_148
HCLK_CMT_L.HCLK_CMT_CK_IN3.HCLK_CMT_MUX_CLK_MMCM5 origin:045-hclk-cmt-pips 28_143 28_148
HCLK_CMT_L.HCLK_CMT_CK_IN3.HCLK_CMT_MUX_CLK_MMCM6 origin:045-hclk-cmt-pips 28_143 29_147
HCLK_CMT_L.HCLK_CMT_CK_IN3.HCLK_CMT_MUX_CLK_MMCM7 origin:045-hclk-cmt-pips 28_143 28_147
HCLK_CMT_L.HCLK_CMT_CK_IN3.HCLK_CMT_MUX_CLK_MMCM8 origin:045-hclk-cmt-pips 28_143 29_146
HCLK_CMT_L.HCLK_CMT_CK_IN3.HCLK_CMT_MUX_CLK_MMCM9 origin:045-hclk-cmt-pips 28_143 28_146
HCLK_CMT_L.HCLK_CMT_CK_IN3.HCLK_CMT_MUX_CLK_PLL0 origin:045-hclk-cmt-pips 28_142 29_148
HCLK_CMT_L.HCLK_CMT_CK_IN3.HCLK_CMT_MUX_CLK_PLL1 origin:045-hclk-cmt-pips 28_142 28_148
HCLK_CMT_L.HCLK_CMT_CK_IN3.HCLK_CMT_MUX_CLK_PLL2 origin:045-hclk-cmt-pips 28_142 29_147
HCLK_CMT_L.HCLK_CMT_CK_IN3.HCLK_CMT_MUX_CLK_PLL3 origin:045-hclk-cmt-pips 28_142 28_147
HCLK_CMT_L.HCLK_CMT_CK_IN3.HCLK_CMT_MUX_CLK_PLL4 origin:045-hclk-cmt-pips 28_142 29_146
HCLK_CMT_L.HCLK_CMT_CK_IN3.HCLK_CMT_MUX_CLK_PLL5 origin:045-hclk-cmt-pips 28_142 28_146
HCLK_CMT_L.HCLK_CMT_CK_IN3.HCLK_CMT_MUX_CLK_PLL6 origin:045-hclk-cmt-pips 29_142 29_148
HCLK_CMT_L.HCLK_CMT_CK_IN4.HCLK_CMT_CCIO0 origin:045-hclk-cmt-pips 27_137 27_139
HCLK_CMT_L.HCLK_CMT_CK_IN4.HCLK_CMT_CCIO1 origin:045-hclk-cmt-pips 26_139 27_137
HCLK_CMT_L.HCLK_CMT_CK_IN4.HCLK_CMT_CCIO2 origin:045-hclk-cmt-pips 26_138 27_139
HCLK_CMT_L.HCLK_CMT_CK_IN4.HCLK_CMT_CCIO3 origin:045-hclk-cmt-pips 26_138 26_139
HCLK_CMT_L.HCLK_CMT_CK_IN4.HCLK_CMT_CK_BUFHCLK0 origin:045-hclk-cmt-pips 27_136 27_141
HCLK_CMT_L.HCLK_CMT_CK_IN4.HCLK_CMT_CK_BUFHCLK1 origin:045-hclk-cmt-pips 26_141 27_136
HCLK_CMT_L.HCLK_CMT_CK_IN4.HCLK_CMT_CK_BUFHCLK10 origin:045-hclk-cmt-pips 26_137 27_139
HCLK_CMT_L.HCLK_CMT_CK_IN4.HCLK_CMT_CK_BUFHCLK11 origin:045-hclk-cmt-pips 26_137 26_139
HCLK_CMT_L.HCLK_CMT_CK_IN4.HCLK_CMT_CK_BUFHCLK2 origin:045-hclk-cmt-pips 27_136 27_140
HCLK_CMT_L.HCLK_CMT_CK_IN4.HCLK_CMT_CK_BUFHCLK3 origin:045-hclk-cmt-pips 26_140 27_136
HCLK_CMT_L.HCLK_CMT_CK_IN4.HCLK_CMT_CK_BUFHCLK4 origin:045-hclk-cmt-pips 27_136 27_139
HCLK_CMT_L.HCLK_CMT_CK_IN4.HCLK_CMT_CK_BUFHCLK5 origin:045-hclk-cmt-pips 26_139 27_136
HCLK_CMT_L.HCLK_CMT_CK_IN4.HCLK_CMT_CK_BUFHCLK6 origin:045-hclk-cmt-pips 26_137 27_141
HCLK_CMT_L.HCLK_CMT_CK_IN4.HCLK_CMT_CK_BUFHCLK7 origin:045-hclk-cmt-pips 26_137 26_141
HCLK_CMT_L.HCLK_CMT_CK_IN4.HCLK_CMT_CK_BUFHCLK8 origin:045-hclk-cmt-pips 26_137 27_140
HCLK_CMT_L.HCLK_CMT_CK_IN4.HCLK_CMT_CK_BUFHCLK9 origin:045-hclk-cmt-pips 26_137 26_140
HCLK_CMT_L.HCLK_CMT_CK_IN4.HCLK_CMT_MUX_CLK_MMCM0 origin:045-hclk-cmt-pips 27_135 27_140
HCLK_CMT_L.HCLK_CMT_CK_IN4.HCLK_CMT_MUX_CLK_MMCM1 origin:045-hclk-cmt-pips 26_140 27_135
HCLK_CMT_L.HCLK_CMT_CK_IN4.HCLK_CMT_MUX_CLK_MMCM10 origin:045-hclk-cmt-pips 27_137 27_141
HCLK_CMT_L.HCLK_CMT_CK_IN4.HCLK_CMT_MUX_CLK_MMCM11 origin:045-hclk-cmt-pips 26_141 27_137
HCLK_CMT_L.HCLK_CMT_CK_IN4.HCLK_CMT_MUX_CLK_MMCM12 origin:045-hclk-cmt-pips 27_137 27_140
HCLK_CMT_L.HCLK_CMT_CK_IN4.HCLK_CMT_MUX_CLK_MMCM2 origin:045-hclk-cmt-pips 27_135 27_139
HCLK_CMT_L.HCLK_CMT_CK_IN4.HCLK_CMT_MUX_CLK_MMCM3 origin:045-hclk-cmt-pips 26_139 27_135
HCLK_CMT_L.HCLK_CMT_CK_IN4.HCLK_CMT_MUX_CLK_MMCM4 origin:045-hclk-cmt-pips 26_136 27_141
HCLK_CMT_L.HCLK_CMT_CK_IN4.HCLK_CMT_MUX_CLK_MMCM5 origin:045-hclk-cmt-pips 26_136 26_141
HCLK_CMT_L.HCLK_CMT_CK_IN4.HCLK_CMT_MUX_CLK_MMCM6 origin:045-hclk-cmt-pips 26_136 27_140
HCLK_CMT_L.HCLK_CMT_CK_IN4.HCLK_CMT_MUX_CLK_MMCM7 origin:045-hclk-cmt-pips 26_136 26_140
HCLK_CMT_L.HCLK_CMT_CK_IN4.HCLK_CMT_MUX_CLK_MMCM8 origin:045-hclk-cmt-pips 26_136 27_139
HCLK_CMT_L.HCLK_CMT_CK_IN4.HCLK_CMT_MUX_CLK_MMCM9 origin:045-hclk-cmt-pips 26_136 26_139
HCLK_CMT_L.HCLK_CMT_CK_IN4.HCLK_CMT_MUX_CLK_PLL0 origin:045-hclk-cmt-pips 26_135 27_141
HCLK_CMT_L.HCLK_CMT_CK_IN4.HCLK_CMT_MUX_CLK_PLL1 origin:045-hclk-cmt-pips 26_135 26_141
HCLK_CMT_L.HCLK_CMT_CK_IN4.HCLK_CMT_MUX_CLK_PLL2 origin:045-hclk-cmt-pips 26_135 27_140
HCLK_CMT_L.HCLK_CMT_CK_IN4.HCLK_CMT_MUX_CLK_PLL3 origin:045-hclk-cmt-pips 26_135 26_140
HCLK_CMT_L.HCLK_CMT_CK_IN4.HCLK_CMT_MUX_CLK_PLL4 origin:045-hclk-cmt-pips 26_135 27_139
HCLK_CMT_L.HCLK_CMT_CK_IN4.HCLK_CMT_MUX_CLK_PLL5 origin:045-hclk-cmt-pips 26_135 26_139
HCLK_CMT_L.HCLK_CMT_CK_IN4.HCLK_CMT_MUX_CLK_PLL6 origin:045-hclk-cmt-pips 27_135 27_141
HCLK_CMT_L.HCLK_CMT_CK_IN5.HCLK_CMT_CCIO0 origin:045-hclk-cmt-pips 29_137 29_139
HCLK_CMT_L.HCLK_CMT_CK_IN5.HCLK_CMT_CCIO1 origin:045-hclk-cmt-pips 28_139 29_137
HCLK_CMT_L.HCLK_CMT_CK_IN5.HCLK_CMT_CCIO2 origin:045-hclk-cmt-pips 28_138 29_139
HCLK_CMT_L.HCLK_CMT_CK_IN5.HCLK_CMT_CCIO3 origin:045-hclk-cmt-pips 28_138 28_139
HCLK_CMT_L.HCLK_CMT_CK_IN5.HCLK_CMT_CK_BUFHCLK0 origin:045-hclk-cmt-pips 29_136 29_141
HCLK_CMT_L.HCLK_CMT_CK_IN5.HCLK_CMT_CK_BUFHCLK1 origin:045-hclk-cmt-pips 28_141 29_136
HCLK_CMT_L.HCLK_CMT_CK_IN5.HCLK_CMT_CK_BUFHCLK10 origin:045-hclk-cmt-pips 28_137 29_139
HCLK_CMT_L.HCLK_CMT_CK_IN5.HCLK_CMT_CK_BUFHCLK11 origin:045-hclk-cmt-pips 28_137 28_139
HCLK_CMT_L.HCLK_CMT_CK_IN5.HCLK_CMT_CK_BUFHCLK2 origin:045-hclk-cmt-pips 29_136 29_140
HCLK_CMT_L.HCLK_CMT_CK_IN5.HCLK_CMT_CK_BUFHCLK3 origin:045-hclk-cmt-pips 28_140 29_136
HCLK_CMT_L.HCLK_CMT_CK_IN5.HCLK_CMT_CK_BUFHCLK4 origin:045-hclk-cmt-pips 29_136 29_139
HCLK_CMT_L.HCLK_CMT_CK_IN5.HCLK_CMT_CK_BUFHCLK5 origin:045-hclk-cmt-pips 28_139 29_136
HCLK_CMT_L.HCLK_CMT_CK_IN5.HCLK_CMT_CK_BUFHCLK6 origin:045-hclk-cmt-pips 28_137 29_141
HCLK_CMT_L.HCLK_CMT_CK_IN5.HCLK_CMT_CK_BUFHCLK7 origin:045-hclk-cmt-pips 28_137 28_141
HCLK_CMT_L.HCLK_CMT_CK_IN5.HCLK_CMT_CK_BUFHCLK8 origin:045-hclk-cmt-pips 28_137 29_140
HCLK_CMT_L.HCLK_CMT_CK_IN5.HCLK_CMT_CK_BUFHCLK9 origin:045-hclk-cmt-pips 28_137 28_140
HCLK_CMT_L.HCLK_CMT_CK_IN5.HCLK_CMT_MUX_CLK_MMCM0 origin:045-hclk-cmt-pips 29_135 29_140
HCLK_CMT_L.HCLK_CMT_CK_IN5.HCLK_CMT_MUX_CLK_MMCM1 origin:045-hclk-cmt-pips 28_140 29_135
HCLK_CMT_L.HCLK_CMT_CK_IN5.HCLK_CMT_MUX_CLK_MMCM10 origin:045-hclk-cmt-pips 29_137 29_141
HCLK_CMT_L.HCLK_CMT_CK_IN5.HCLK_CMT_MUX_CLK_MMCM11 origin:045-hclk-cmt-pips 28_141 29_137
HCLK_CMT_L.HCLK_CMT_CK_IN5.HCLK_CMT_MUX_CLK_MMCM12 origin:045-hclk-cmt-pips 29_137 29_140
HCLK_CMT_L.HCLK_CMT_CK_IN5.HCLK_CMT_MUX_CLK_MMCM2 origin:045-hclk-cmt-pips 29_135 29_139
HCLK_CMT_L.HCLK_CMT_CK_IN5.HCLK_CMT_MUX_CLK_MMCM3 origin:045-hclk-cmt-pips 28_139 29_135
HCLK_CMT_L.HCLK_CMT_CK_IN5.HCLK_CMT_MUX_CLK_MMCM4 origin:045-hclk-cmt-pips 28_136 29_141
HCLK_CMT_L.HCLK_CMT_CK_IN5.HCLK_CMT_MUX_CLK_MMCM5 origin:045-hclk-cmt-pips 28_136 28_141
HCLK_CMT_L.HCLK_CMT_CK_IN5.HCLK_CMT_MUX_CLK_MMCM6 origin:045-hclk-cmt-pips 28_136 29_140
HCLK_CMT_L.HCLK_CMT_CK_IN5.HCLK_CMT_MUX_CLK_MMCM7 origin:045-hclk-cmt-pips 28_136 28_140
HCLK_CMT_L.HCLK_CMT_CK_IN5.HCLK_CMT_MUX_CLK_MMCM8 origin:045-hclk-cmt-pips 28_136 29_139
HCLK_CMT_L.HCLK_CMT_CK_IN5.HCLK_CMT_MUX_CLK_MMCM9 origin:045-hclk-cmt-pips 28_136 28_139
HCLK_CMT_L.HCLK_CMT_CK_IN5.HCLK_CMT_MUX_CLK_PLL0 origin:045-hclk-cmt-pips 28_135 29_141
HCLK_CMT_L.HCLK_CMT_CK_IN5.HCLK_CMT_MUX_CLK_PLL1 origin:045-hclk-cmt-pips 28_135 28_141
HCLK_CMT_L.HCLK_CMT_CK_IN5.HCLK_CMT_MUX_CLK_PLL2 origin:045-hclk-cmt-pips 28_135 29_140
HCLK_CMT_L.HCLK_CMT_CK_IN5.HCLK_CMT_MUX_CLK_PLL3 origin:045-hclk-cmt-pips 28_135 28_140
HCLK_CMT_L.HCLK_CMT_CK_IN5.HCLK_CMT_MUX_CLK_PLL4 origin:045-hclk-cmt-pips 28_135 29_139
HCLK_CMT_L.HCLK_CMT_CK_IN5.HCLK_CMT_MUX_CLK_PLL5 origin:045-hclk-cmt-pips 28_135 28_139
HCLK_CMT_L.HCLK_CMT_CK_IN5.HCLK_CMT_MUX_CLK_PLL6 origin:045-hclk-cmt-pips 29_135 29_141
HCLK_CMT_L.HCLK_CMT_CK_IN6.HCLK_CMT_CCIO0 origin:045-hclk-cmt-pips 27_130 27_132
HCLK_CMT_L.HCLK_CMT_CK_IN6.HCLK_CMT_CCIO1 origin:045-hclk-cmt-pips 26_132 27_130
HCLK_CMT_L.HCLK_CMT_CK_IN6.HCLK_CMT_CCIO2 origin:045-hclk-cmt-pips 26_131 27_132
HCLK_CMT_L.HCLK_CMT_CK_IN6.HCLK_CMT_CCIO3 origin:045-hclk-cmt-pips 26_131 26_132
HCLK_CMT_L.HCLK_CMT_CK_IN6.HCLK_CMT_CK_BUFHCLK0 origin:045-hclk-cmt-pips 27_129 27_134
HCLK_CMT_L.HCLK_CMT_CK_IN6.HCLK_CMT_CK_BUFHCLK1 origin:045-hclk-cmt-pips 26_134 27_129
HCLK_CMT_L.HCLK_CMT_CK_IN6.HCLK_CMT_CK_BUFHCLK10 origin:045-hclk-cmt-pips 26_130 27_132
HCLK_CMT_L.HCLK_CMT_CK_IN6.HCLK_CMT_CK_BUFHCLK11 origin:045-hclk-cmt-pips 26_130 26_132
HCLK_CMT_L.HCLK_CMT_CK_IN6.HCLK_CMT_CK_BUFHCLK2 origin:045-hclk-cmt-pips 27_129 27_133
HCLK_CMT_L.HCLK_CMT_CK_IN6.HCLK_CMT_CK_BUFHCLK3 origin:045-hclk-cmt-pips 26_133 27_129
HCLK_CMT_L.HCLK_CMT_CK_IN6.HCLK_CMT_CK_BUFHCLK4 origin:045-hclk-cmt-pips 27_129 27_132
HCLK_CMT_L.HCLK_CMT_CK_IN6.HCLK_CMT_CK_BUFHCLK5 origin:045-hclk-cmt-pips 26_132 27_129
HCLK_CMT_L.HCLK_CMT_CK_IN6.HCLK_CMT_CK_BUFHCLK6 origin:045-hclk-cmt-pips 26_130 27_134
HCLK_CMT_L.HCLK_CMT_CK_IN6.HCLK_CMT_CK_BUFHCLK7 origin:045-hclk-cmt-pips 26_130 26_134
HCLK_CMT_L.HCLK_CMT_CK_IN6.HCLK_CMT_CK_BUFHCLK8 origin:045-hclk-cmt-pips 26_130 27_133
HCLK_CMT_L.HCLK_CMT_CK_IN6.HCLK_CMT_CK_BUFHCLK9 origin:045-hclk-cmt-pips 26_130 26_133
HCLK_CMT_L.HCLK_CMT_CK_IN6.HCLK_CMT_MUX_CLK_MMCM0 origin:045-hclk-cmt-pips 27_128 27_133
HCLK_CMT_L.HCLK_CMT_CK_IN6.HCLK_CMT_MUX_CLK_MMCM1 origin:045-hclk-cmt-pips 26_133 27_128
HCLK_CMT_L.HCLK_CMT_CK_IN6.HCLK_CMT_MUX_CLK_MMCM10 origin:045-hclk-cmt-pips 27_130 27_134
HCLK_CMT_L.HCLK_CMT_CK_IN6.HCLK_CMT_MUX_CLK_MMCM11 origin:045-hclk-cmt-pips 26_134 27_130
HCLK_CMT_L.HCLK_CMT_CK_IN6.HCLK_CMT_MUX_CLK_MMCM12 origin:045-hclk-cmt-pips 27_130 27_133
HCLK_CMT_L.HCLK_CMT_CK_IN6.HCLK_CMT_MUX_CLK_MMCM2 origin:045-hclk-cmt-pips 27_128 27_132
HCLK_CMT_L.HCLK_CMT_CK_IN6.HCLK_CMT_MUX_CLK_MMCM3 origin:045-hclk-cmt-pips 26_132 27_128
HCLK_CMT_L.HCLK_CMT_CK_IN6.HCLK_CMT_MUX_CLK_MMCM4 origin:045-hclk-cmt-pips 26_129 27_134
HCLK_CMT_L.HCLK_CMT_CK_IN6.HCLK_CMT_MUX_CLK_MMCM5 origin:045-hclk-cmt-pips 26_129 26_134
HCLK_CMT_L.HCLK_CMT_CK_IN6.HCLK_CMT_MUX_CLK_MMCM6 origin:045-hclk-cmt-pips 26_129 27_133
HCLK_CMT_L.HCLK_CMT_CK_IN6.HCLK_CMT_MUX_CLK_MMCM7 origin:045-hclk-cmt-pips 26_129 26_133
HCLK_CMT_L.HCLK_CMT_CK_IN6.HCLK_CMT_MUX_CLK_MMCM8 origin:045-hclk-cmt-pips 26_129 27_132
HCLK_CMT_L.HCLK_CMT_CK_IN6.HCLK_CMT_MUX_CLK_MMCM9 origin:045-hclk-cmt-pips 26_129 26_132
HCLK_CMT_L.HCLK_CMT_CK_IN6.HCLK_CMT_MUX_CLK_PLL0 origin:045-hclk-cmt-pips 26_128 27_134
HCLK_CMT_L.HCLK_CMT_CK_IN6.HCLK_CMT_MUX_CLK_PLL1 origin:045-hclk-cmt-pips 26_128 26_134
HCLK_CMT_L.HCLK_CMT_CK_IN6.HCLK_CMT_MUX_CLK_PLL2 origin:045-hclk-cmt-pips 26_128 27_133
HCLK_CMT_L.HCLK_CMT_CK_IN6.HCLK_CMT_MUX_CLK_PLL3 origin:045-hclk-cmt-pips 26_128 26_133
HCLK_CMT_L.HCLK_CMT_CK_IN6.HCLK_CMT_MUX_CLK_PLL4 origin:045-hclk-cmt-pips 26_128 27_132
HCLK_CMT_L.HCLK_CMT_CK_IN6.HCLK_CMT_MUX_CLK_PLL5 origin:045-hclk-cmt-pips 26_128 26_132
HCLK_CMT_L.HCLK_CMT_CK_IN6.HCLK_CMT_MUX_CLK_PLL6 origin:045-hclk-cmt-pips 27_128 27_134
HCLK_CMT_L.HCLK_CMT_CK_IN7.HCLK_CMT_CCIO0 origin:045-hclk-cmt-pips 26_198 26_200
HCLK_CMT_L.HCLK_CMT_CK_IN7.HCLK_CMT_CCIO1 origin:045-hclk-cmt-pips 26_200 27_198
HCLK_CMT_L.HCLK_CMT_CK_IN7.HCLK_CMT_CCIO2 origin:045-hclk-cmt-pips 26_198 27_199
HCLK_CMT_L.HCLK_CMT_CK_IN7.HCLK_CMT_CCIO3 origin:045-hclk-cmt-pips 27_198 27_199
HCLK_CMT_L.HCLK_CMT_CK_IN7.HCLK_CMT_CK_BUFHCLK0 origin:045-hclk-cmt-pips 26_196 26_201
HCLK_CMT_L.HCLK_CMT_CK_IN7.HCLK_CMT_CK_BUFHCLK1 origin:045-hclk-cmt-pips 26_201 27_196
HCLK_CMT_L.HCLK_CMT_CK_IN7.HCLK_CMT_CK_BUFHCLK10 origin:045-hclk-cmt-pips 26_198 27_200
HCLK_CMT_L.HCLK_CMT_CK_IN7.HCLK_CMT_CK_BUFHCLK11 origin:045-hclk-cmt-pips 27_198 27_200
HCLK_CMT_L.HCLK_CMT_CK_IN7.HCLK_CMT_CK_BUFHCLK2 origin:045-hclk-cmt-pips 26_197 26_201
HCLK_CMT_L.HCLK_CMT_CK_IN7.HCLK_CMT_CK_BUFHCLK3 origin:045-hclk-cmt-pips 26_201 27_197
HCLK_CMT_L.HCLK_CMT_CK_IN7.HCLK_CMT_CK_BUFHCLK4 origin:045-hclk-cmt-pips 26_198 26_201
HCLK_CMT_L.HCLK_CMT_CK_IN7.HCLK_CMT_CK_BUFHCLK5 origin:045-hclk-cmt-pips 26_201 27_198
HCLK_CMT_L.HCLK_CMT_CK_IN7.HCLK_CMT_CK_BUFHCLK6 origin:045-hclk-cmt-pips 26_196 27_200
HCLK_CMT_L.HCLK_CMT_CK_IN7.HCLK_CMT_CK_BUFHCLK7 origin:045-hclk-cmt-pips 27_196 27_200
HCLK_CMT_L.HCLK_CMT_CK_IN7.HCLK_CMT_CK_BUFHCLK8 origin:045-hclk-cmt-pips 26_197 27_200
HCLK_CMT_L.HCLK_CMT_CK_IN7.HCLK_CMT_CK_BUFHCLK9 origin:045-hclk-cmt-pips 27_197 27_200
HCLK_CMT_L.HCLK_CMT_CK_IN7.HCLK_CMT_MUX_CLK_MMCM0 origin:045-hclk-cmt-pips 26_197 26_202
HCLK_CMT_L.HCLK_CMT_CK_IN7.HCLK_CMT_MUX_CLK_MMCM1 origin:045-hclk-cmt-pips 26_202 27_197
HCLK_CMT_L.HCLK_CMT_CK_IN7.HCLK_CMT_MUX_CLK_MMCM10 origin:045-hclk-cmt-pips 26_196 26_200
HCLK_CMT_L.HCLK_CMT_CK_IN7.HCLK_CMT_MUX_CLK_MMCM11 origin:045-hclk-cmt-pips 26_200 27_196
HCLK_CMT_L.HCLK_CMT_CK_IN7.HCLK_CMT_MUX_CLK_MMCM12 origin:045-hclk-cmt-pips 26_197 26_200
HCLK_CMT_L.HCLK_CMT_CK_IN7.HCLK_CMT_MUX_CLK_MMCM2 origin:045-hclk-cmt-pips 26_198 26_202
HCLK_CMT_L.HCLK_CMT_CK_IN7.HCLK_CMT_MUX_CLK_MMCM3 origin:045-hclk-cmt-pips 26_202 27_198
HCLK_CMT_L.HCLK_CMT_CK_IN7.HCLK_CMT_MUX_CLK_MMCM4 origin:045-hclk-cmt-pips 26_196 27_201
HCLK_CMT_L.HCLK_CMT_CK_IN7.HCLK_CMT_MUX_CLK_MMCM5 origin:045-hclk-cmt-pips 27_196 27_201
HCLK_CMT_L.HCLK_CMT_CK_IN7.HCLK_CMT_MUX_CLK_MMCM6 origin:045-hclk-cmt-pips 26_197 27_201
HCLK_CMT_L.HCLK_CMT_CK_IN7.HCLK_CMT_MUX_CLK_MMCM7 origin:045-hclk-cmt-pips 27_197 27_201
HCLK_CMT_L.HCLK_CMT_CK_IN7.HCLK_CMT_MUX_CLK_MMCM8 origin:045-hclk-cmt-pips 26_198 27_201
HCLK_CMT_L.HCLK_CMT_CK_IN7.HCLK_CMT_MUX_CLK_MMCM9 origin:045-hclk-cmt-pips 27_198 27_201
HCLK_CMT_L.HCLK_CMT_CK_IN7.HCLK_CMT_MUX_CLK_PLL0 origin:045-hclk-cmt-pips 26_196 27_202
HCLK_CMT_L.HCLK_CMT_CK_IN7.HCLK_CMT_MUX_CLK_PLL1 origin:045-hclk-cmt-pips 27_196 27_202
HCLK_CMT_L.HCLK_CMT_CK_IN7.HCLK_CMT_MUX_CLK_PLL2 origin:045-hclk-cmt-pips 26_197 27_202
HCLK_CMT_L.HCLK_CMT_CK_IN7.HCLK_CMT_MUX_CLK_PLL3 origin:045-hclk-cmt-pips 27_197 27_202
HCLK_CMT_L.HCLK_CMT_CK_IN7.HCLK_CMT_MUX_CLK_PLL4 origin:045-hclk-cmt-pips 26_198 27_202
HCLK_CMT_L.HCLK_CMT_CK_IN7.HCLK_CMT_MUX_CLK_PLL5 origin:045-hclk-cmt-pips 27_198 27_202
HCLK_CMT_L.HCLK_CMT_CK_IN7.HCLK_CMT_MUX_CLK_PLL6 origin:045-hclk-cmt-pips 26_196 26_202
HCLK_CMT_L.HCLK_CMT_CK_IN8.HCLK_CMT_CCIO0 origin:045-hclk-cmt-pips 28_198 28_200
HCLK_CMT_L.HCLK_CMT_CK_IN8.HCLK_CMT_CCIO1 origin:045-hclk-cmt-pips 28_200 29_198
HCLK_CMT_L.HCLK_CMT_CK_IN8.HCLK_CMT_CCIO2 origin:045-hclk-cmt-pips 28_198 29_199
HCLK_CMT_L.HCLK_CMT_CK_IN8.HCLK_CMT_CCIO3 origin:045-hclk-cmt-pips 29_198 29_199
HCLK_CMT_L.HCLK_CMT_CK_IN8.HCLK_CMT_CK_BUFHCLK0 origin:045-hclk-cmt-pips 28_196 28_201
HCLK_CMT_L.HCLK_CMT_CK_IN8.HCLK_CMT_CK_BUFHCLK1 origin:045-hclk-cmt-pips 28_201 29_196
HCLK_CMT_L.HCLK_CMT_CK_IN8.HCLK_CMT_CK_BUFHCLK10 origin:045-hclk-cmt-pips 28_198 29_200
HCLK_CMT_L.HCLK_CMT_CK_IN8.HCLK_CMT_CK_BUFHCLK11 origin:045-hclk-cmt-pips 29_198 29_200
HCLK_CMT_L.HCLK_CMT_CK_IN8.HCLK_CMT_CK_BUFHCLK2 origin:045-hclk-cmt-pips 28_197 28_201
HCLK_CMT_L.HCLK_CMT_CK_IN8.HCLK_CMT_CK_BUFHCLK3 origin:045-hclk-cmt-pips 28_201 29_197
HCLK_CMT_L.HCLK_CMT_CK_IN8.HCLK_CMT_CK_BUFHCLK4 origin:045-hclk-cmt-pips 28_198 28_201
HCLK_CMT_L.HCLK_CMT_CK_IN8.HCLK_CMT_CK_BUFHCLK5 origin:045-hclk-cmt-pips 28_201 29_198
HCLK_CMT_L.HCLK_CMT_CK_IN8.HCLK_CMT_CK_BUFHCLK6 origin:045-hclk-cmt-pips 28_196 29_200
HCLK_CMT_L.HCLK_CMT_CK_IN8.HCLK_CMT_CK_BUFHCLK7 origin:045-hclk-cmt-pips 29_196 29_200
HCLK_CMT_L.HCLK_CMT_CK_IN8.HCLK_CMT_CK_BUFHCLK8 origin:045-hclk-cmt-pips 28_197 29_200
HCLK_CMT_L.HCLK_CMT_CK_IN8.HCLK_CMT_CK_BUFHCLK9 origin:045-hclk-cmt-pips 29_197 29_200
HCLK_CMT_L.HCLK_CMT_CK_IN8.HCLK_CMT_MUX_CLK_MMCM0 origin:045-hclk-cmt-pips 28_197 28_202
HCLK_CMT_L.HCLK_CMT_CK_IN8.HCLK_CMT_MUX_CLK_MMCM1 origin:045-hclk-cmt-pips 28_202 29_197
HCLK_CMT_L.HCLK_CMT_CK_IN8.HCLK_CMT_MUX_CLK_MMCM10 origin:045-hclk-cmt-pips 28_196 28_200
HCLK_CMT_L.HCLK_CMT_CK_IN8.HCLK_CMT_MUX_CLK_MMCM11 origin:045-hclk-cmt-pips 28_200 29_196
HCLK_CMT_L.HCLK_CMT_CK_IN8.HCLK_CMT_MUX_CLK_MMCM12 origin:045-hclk-cmt-pips 28_197 28_200
HCLK_CMT_L.HCLK_CMT_CK_IN8.HCLK_CMT_MUX_CLK_MMCM2 origin:045-hclk-cmt-pips 28_198 28_202
HCLK_CMT_L.HCLK_CMT_CK_IN8.HCLK_CMT_MUX_CLK_MMCM3 origin:045-hclk-cmt-pips 28_202 29_198
HCLK_CMT_L.HCLK_CMT_CK_IN8.HCLK_CMT_MUX_CLK_MMCM4 origin:045-hclk-cmt-pips 28_196 29_201
HCLK_CMT_L.HCLK_CMT_CK_IN8.HCLK_CMT_MUX_CLK_MMCM5 origin:045-hclk-cmt-pips 29_196 29_201
HCLK_CMT_L.HCLK_CMT_CK_IN8.HCLK_CMT_MUX_CLK_MMCM6 origin:045-hclk-cmt-pips 28_197 29_201
HCLK_CMT_L.HCLK_CMT_CK_IN8.HCLK_CMT_MUX_CLK_MMCM7 origin:045-hclk-cmt-pips 29_197 29_201
HCLK_CMT_L.HCLK_CMT_CK_IN8.HCLK_CMT_MUX_CLK_MMCM8 origin:045-hclk-cmt-pips 28_198 29_201
HCLK_CMT_L.HCLK_CMT_CK_IN8.HCLK_CMT_MUX_CLK_MMCM9 origin:045-hclk-cmt-pips 29_198 29_201
HCLK_CMT_L.HCLK_CMT_CK_IN8.HCLK_CMT_MUX_CLK_PLL0 origin:045-hclk-cmt-pips 28_196 29_202
HCLK_CMT_L.HCLK_CMT_CK_IN8.HCLK_CMT_MUX_CLK_PLL1 origin:045-hclk-cmt-pips 29_196 29_202
HCLK_CMT_L.HCLK_CMT_CK_IN8.HCLK_CMT_MUX_CLK_PLL2 origin:045-hclk-cmt-pips 28_197 29_202
HCLK_CMT_L.HCLK_CMT_CK_IN8.HCLK_CMT_MUX_CLK_PLL3 origin:045-hclk-cmt-pips 29_197 29_202
HCLK_CMT_L.HCLK_CMT_CK_IN8.HCLK_CMT_MUX_CLK_PLL4 origin:045-hclk-cmt-pips 28_198 29_202
HCLK_CMT_L.HCLK_CMT_CK_IN8.HCLK_CMT_MUX_CLK_PLL5 origin:045-hclk-cmt-pips 29_198 29_202
HCLK_CMT_L.HCLK_CMT_CK_IN8.HCLK_CMT_MUX_CLK_PLL6 origin:045-hclk-cmt-pips 28_196 28_202
HCLK_CMT_L.HCLK_CMT_CK_IN9.HCLK_CMT_CCIO0 origin:045-hclk-cmt-pips 26_205 26_207
HCLK_CMT_L.HCLK_CMT_CK_IN9.HCLK_CMT_CCIO1 origin:045-hclk-cmt-pips 26_207 27_205
HCLK_CMT_L.HCLK_CMT_CK_IN9.HCLK_CMT_CCIO2 origin:045-hclk-cmt-pips 26_205 27_206
HCLK_CMT_L.HCLK_CMT_CK_IN9.HCLK_CMT_CCIO3 origin:045-hclk-cmt-pips 27_205 27_206
HCLK_CMT_L.HCLK_CMT_CK_IN9.HCLK_CMT_CK_BUFHCLK0 origin:045-hclk-cmt-pips 26_203 26_208
HCLK_CMT_L.HCLK_CMT_CK_IN9.HCLK_CMT_CK_BUFHCLK1 origin:045-hclk-cmt-pips 26_208 27_203
HCLK_CMT_L.HCLK_CMT_CK_IN9.HCLK_CMT_CK_BUFHCLK10 origin:045-hclk-cmt-pips 26_205 27_207
HCLK_CMT_L.HCLK_CMT_CK_IN9.HCLK_CMT_CK_BUFHCLK11 origin:045-hclk-cmt-pips 27_205 27_207
HCLK_CMT_L.HCLK_CMT_CK_IN9.HCLK_CMT_CK_BUFHCLK2 origin:045-hclk-cmt-pips 26_204 26_208
HCLK_CMT_L.HCLK_CMT_CK_IN9.HCLK_CMT_CK_BUFHCLK3 origin:045-hclk-cmt-pips 26_208 27_204
HCLK_CMT_L.HCLK_CMT_CK_IN9.HCLK_CMT_CK_BUFHCLK4 origin:045-hclk-cmt-pips 26_205 26_208
HCLK_CMT_L.HCLK_CMT_CK_IN9.HCLK_CMT_CK_BUFHCLK5 origin:045-hclk-cmt-pips 26_208 27_205
HCLK_CMT_L.HCLK_CMT_CK_IN9.HCLK_CMT_CK_BUFHCLK6 origin:045-hclk-cmt-pips 26_203 27_207
HCLK_CMT_L.HCLK_CMT_CK_IN9.HCLK_CMT_CK_BUFHCLK7 origin:045-hclk-cmt-pips 27_203 27_207
HCLK_CMT_L.HCLK_CMT_CK_IN9.HCLK_CMT_CK_BUFHCLK8 origin:045-hclk-cmt-pips 26_204 27_207
HCLK_CMT_L.HCLK_CMT_CK_IN9.HCLK_CMT_CK_BUFHCLK9 origin:045-hclk-cmt-pips 27_204 27_207
HCLK_CMT_L.HCLK_CMT_CK_IN9.HCLK_CMT_MUX_CLK_MMCM0 origin:045-hclk-cmt-pips 26_204 26_209
HCLK_CMT_L.HCLK_CMT_CK_IN9.HCLK_CMT_MUX_CLK_MMCM1 origin:045-hclk-cmt-pips 26_209 27_204
HCLK_CMT_L.HCLK_CMT_CK_IN9.HCLK_CMT_MUX_CLK_MMCM10 origin:045-hclk-cmt-pips 26_203 26_207
HCLK_CMT_L.HCLK_CMT_CK_IN9.HCLK_CMT_MUX_CLK_MMCM11 origin:045-hclk-cmt-pips 26_207 27_203
HCLK_CMT_L.HCLK_CMT_CK_IN9.HCLK_CMT_MUX_CLK_MMCM12 origin:045-hclk-cmt-pips 26_204 26_207
HCLK_CMT_L.HCLK_CMT_CK_IN9.HCLK_CMT_MUX_CLK_MMCM2 origin:045-hclk-cmt-pips 26_205 26_209
HCLK_CMT_L.HCLK_CMT_CK_IN9.HCLK_CMT_MUX_CLK_MMCM3 origin:045-hclk-cmt-pips 26_209 27_205
HCLK_CMT_L.HCLK_CMT_CK_IN9.HCLK_CMT_MUX_CLK_MMCM4 origin:045-hclk-cmt-pips 26_203 27_208
HCLK_CMT_L.HCLK_CMT_CK_IN9.HCLK_CMT_MUX_CLK_MMCM5 origin:045-hclk-cmt-pips 27_203 27_208
HCLK_CMT_L.HCLK_CMT_CK_IN9.HCLK_CMT_MUX_CLK_MMCM6 origin:045-hclk-cmt-pips 26_204 27_208
HCLK_CMT_L.HCLK_CMT_CK_IN9.HCLK_CMT_MUX_CLK_MMCM7 origin:045-hclk-cmt-pips 27_204 27_208
HCLK_CMT_L.HCLK_CMT_CK_IN9.HCLK_CMT_MUX_CLK_MMCM8 origin:045-hclk-cmt-pips 26_205 27_208
HCLK_CMT_L.HCLK_CMT_CK_IN9.HCLK_CMT_MUX_CLK_MMCM9 origin:045-hclk-cmt-pips 27_205 27_208
HCLK_CMT_L.HCLK_CMT_CK_IN9.HCLK_CMT_MUX_CLK_PLL0 origin:045-hclk-cmt-pips 26_203 27_209
HCLK_CMT_L.HCLK_CMT_CK_IN9.HCLK_CMT_MUX_CLK_PLL1 origin:045-hclk-cmt-pips 27_203 27_209
HCLK_CMT_L.HCLK_CMT_CK_IN9.HCLK_CMT_MUX_CLK_PLL2 origin:045-hclk-cmt-pips 26_204 27_209
HCLK_CMT_L.HCLK_CMT_CK_IN9.HCLK_CMT_MUX_CLK_PLL3 origin:045-hclk-cmt-pips 27_204 27_209
HCLK_CMT_L.HCLK_CMT_CK_IN9.HCLK_CMT_MUX_CLK_PLL4 origin:045-hclk-cmt-pips 26_205 27_209
HCLK_CMT_L.HCLK_CMT_CK_IN9.HCLK_CMT_MUX_CLK_PLL5 origin:045-hclk-cmt-pips 27_205 27_209
HCLK_CMT_L.HCLK_CMT_CK_IN9.HCLK_CMT_MUX_CLK_PLL6 origin:045-hclk-cmt-pips 26_203 26_209
HCLK_CMT_L.HCLK_CMT_MUX_MMCM_CLKFBIN.HCLK_CMT_CCIO0 origin:045-hclk-cmt-pips 27_123 27_125
HCLK_CMT_L.HCLK_CMT_MUX_MMCM_CLKFBIN.HCLK_CMT_CCIO1 origin:045-hclk-cmt-pips 26_125 27_123
HCLK_CMT_L.HCLK_CMT_MUX_MMCM_CLKFBIN.HCLK_CMT_CCIO2 origin:045-hclk-cmt-pips 26_124 27_125
HCLK_CMT_L.HCLK_CMT_MUX_MMCM_CLKFBIN.HCLK_CMT_CCIO3 origin:045-hclk-cmt-pips 26_124 26_125
HCLK_CMT_L.HCLK_CMT_MUX_MMCM_CLKFBIN.HCLK_CMT_CK_BUFHCLK0 origin:045-hclk-cmt-pips 27_122 27_127
HCLK_CMT_L.HCLK_CMT_MUX_MMCM_CLKFBIN.HCLK_CMT_CK_BUFHCLK1 origin:045-hclk-cmt-pips 26_127 27_122
HCLK_CMT_L.HCLK_CMT_MUX_MMCM_CLKFBIN.HCLK_CMT_CK_BUFHCLK10 origin:045-hclk-cmt-pips 26_123 27_125
HCLK_CMT_L.HCLK_CMT_MUX_MMCM_CLKFBIN.HCLK_CMT_CK_BUFHCLK11 origin:045-hclk-cmt-pips 26_123 26_125
HCLK_CMT_L.HCLK_CMT_MUX_MMCM_CLKFBIN.HCLK_CMT_CK_BUFHCLK2 origin:045-hclk-cmt-pips 27_122 27_126
HCLK_CMT_L.HCLK_CMT_MUX_MMCM_CLKFBIN.HCLK_CMT_CK_BUFHCLK3 origin:045-hclk-cmt-pips 26_126 27_122
HCLK_CMT_L.HCLK_CMT_MUX_MMCM_CLKFBIN.HCLK_CMT_CK_BUFHCLK4 origin:045-hclk-cmt-pips 27_122 27_125
HCLK_CMT_L.HCLK_CMT_MUX_MMCM_CLKFBIN.HCLK_CMT_CK_BUFHCLK5 origin:045-hclk-cmt-pips 26_125 27_122
HCLK_CMT_L.HCLK_CMT_MUX_MMCM_CLKFBIN.HCLK_CMT_CK_BUFHCLK6 origin:045-hclk-cmt-pips 26_123 27_127
HCLK_CMT_L.HCLK_CMT_MUX_MMCM_CLKFBIN.HCLK_CMT_CK_BUFHCLK7 origin:045-hclk-cmt-pips 26_123 26_127
HCLK_CMT_L.HCLK_CMT_MUX_MMCM_CLKFBIN.HCLK_CMT_CK_BUFHCLK8 origin:045-hclk-cmt-pips 26_123 27_126
HCLK_CMT_L.HCLK_CMT_MUX_MMCM_CLKFBIN.HCLK_CMT_CK_BUFHCLK9 origin:045-hclk-cmt-pips 26_123 26_126
HCLK_CMT_L.HCLK_CMT_MUX_MMCM_CLKFBIN.HCLK_CMT_CK_BUFRCLK0 origin:045-hclk-cmt-pips 27_123 27_127
HCLK_CMT_L.HCLK_CMT_MUX_MMCM_CLKFBIN.HCLK_CMT_CK_BUFRCLK1 origin:045-hclk-cmt-pips 26_127 27_123
HCLK_CMT_L.HCLK_CMT_MUX_MMCM_CLKFBIN.HCLK_CMT_CK_BUFRCLK2 origin:045-hclk-cmt-pips 27_123 27_126
HCLK_CMT_L.HCLK_CMT_MUX_MMCM_CLKFBIN.HCLK_CMT_CK_BUFRCLK3 origin:045-hclk-cmt-pips 26_126 27_123
HCLK_CMT_L.HCLK_CMT_MUX_MMCM_CLKIN1.HCLK_CMT_CCIO0 origin:045-hclk-cmt-pips 28_118 28_120
HCLK_CMT_L.HCLK_CMT_MUX_MMCM_CLKIN1.HCLK_CMT_CCIO1 origin:045-hclk-cmt-pips 28_118 29_119
HCLK_CMT_L.HCLK_CMT_MUX_MMCM_CLKIN1.HCLK_CMT_CCIO2 origin:045-hclk-cmt-pips 28_120 29_118
HCLK_CMT_L.HCLK_CMT_MUX_MMCM_CLKIN1.HCLK_CMT_CCIO3 origin:045-hclk-cmt-pips 29_118 29_119
HCLK_CMT_L.HCLK_CMT_MUX_MMCM_CLKIN1.HCLK_CMT_CK_BUFHCLK0 origin:045-hclk-cmt-pips 28_117 28_122
HCLK_CMT_L.HCLK_CMT_MUX_MMCM_CLKIN1.HCLK_CMT_CK_BUFHCLK1 origin:045-hclk-cmt-pips 28_117 29_121
HCLK_CMT_L.HCLK_CMT_MUX_MMCM_CLKIN1.HCLK_CMT_CK_BUFHCLK10 origin:045-hclk-cmt-pips 28_120 29_117
HCLK_CMT_L.HCLK_CMT_MUX_MMCM_CLKIN1.HCLK_CMT_CK_BUFHCLK11 origin:045-hclk-cmt-pips 29_117 29_119
HCLK_CMT_L.HCLK_CMT_MUX_MMCM_CLKIN1.HCLK_CMT_CK_BUFHCLK2 origin:045-hclk-cmt-pips 28_117 28_121
HCLK_CMT_L.HCLK_CMT_MUX_MMCM_CLKIN1.HCLK_CMT_CK_BUFHCLK3 origin:045-hclk-cmt-pips 28_117 29_120
HCLK_CMT_L.HCLK_CMT_MUX_MMCM_CLKIN1.HCLK_CMT_CK_BUFHCLK4 origin:045-hclk-cmt-pips 28_117 28_120
HCLK_CMT_L.HCLK_CMT_MUX_MMCM_CLKIN1.HCLK_CMT_CK_BUFHCLK5 origin:045-hclk-cmt-pips 28_117 29_119
HCLK_CMT_L.HCLK_CMT_MUX_MMCM_CLKIN1.HCLK_CMT_CK_BUFHCLK6 origin:045-hclk-cmt-pips 28_122 29_117
HCLK_CMT_L.HCLK_CMT_MUX_MMCM_CLKIN1.HCLK_CMT_CK_BUFHCLK7 origin:045-hclk-cmt-pips 29_117 29_121
HCLK_CMT_L.HCLK_CMT_MUX_MMCM_CLKIN1.HCLK_CMT_CK_BUFHCLK8 origin:045-hclk-cmt-pips 28_121 29_117
HCLK_CMT_L.HCLK_CMT_MUX_MMCM_CLKIN1.HCLK_CMT_CK_BUFHCLK9 origin:045-hclk-cmt-pips 29_117 29_120
HCLK_CMT_L.HCLK_CMT_MUX_MMCM_CLKIN1.HCLK_CMT_CK_BUFRCLK0 origin:045-hclk-cmt-pips 28_118 28_122
HCLK_CMT_L.HCLK_CMT_MUX_MMCM_CLKIN1.HCLK_CMT_CK_BUFRCLK1 origin:045-hclk-cmt-pips 28_118 29_121
HCLK_CMT_L.HCLK_CMT_MUX_MMCM_CLKIN1.HCLK_CMT_CK_BUFRCLK2 origin:045-hclk-cmt-pips 28_118 28_121
HCLK_CMT_L.HCLK_CMT_MUX_MMCM_CLKIN1.HCLK_CMT_CK_BUFRCLK3 origin:045-hclk-cmt-pips 28_118 29_120
HCLK_CMT_L.HCLK_CMT_MUX_MMCM_CLKIN2.HCLK_CMT_CCIO0 origin:045-hclk-cmt-pips 26_118 26_120
HCLK_CMT_L.HCLK_CMT_MUX_MMCM_CLKIN2.HCLK_CMT_CCIO1 origin:045-hclk-cmt-pips 26_118 27_119
HCLK_CMT_L.HCLK_CMT_MUX_MMCM_CLKIN2.HCLK_CMT_CCIO2 origin:045-hclk-cmt-pips 26_120 27_118
HCLK_CMT_L.HCLK_CMT_MUX_MMCM_CLKIN2.HCLK_CMT_CCIO3 origin:045-hclk-cmt-pips 27_118 27_119
HCLK_CMT_L.HCLK_CMT_MUX_MMCM_CLKIN2.HCLK_CMT_CK_BUFHCLK0 origin:045-hclk-cmt-pips 26_117 26_122
HCLK_CMT_L.HCLK_CMT_MUX_MMCM_CLKIN2.HCLK_CMT_CK_BUFHCLK1 origin:045-hclk-cmt-pips 26_117 27_121
HCLK_CMT_L.HCLK_CMT_MUX_MMCM_CLKIN2.HCLK_CMT_CK_BUFHCLK10 origin:045-hclk-cmt-pips 26_120 27_117
HCLK_CMT_L.HCLK_CMT_MUX_MMCM_CLKIN2.HCLK_CMT_CK_BUFHCLK11 origin:045-hclk-cmt-pips 27_117 27_119
HCLK_CMT_L.HCLK_CMT_MUX_MMCM_CLKIN2.HCLK_CMT_CK_BUFHCLK2 origin:045-hclk-cmt-pips 26_117 26_121
HCLK_CMT_L.HCLK_CMT_MUX_MMCM_CLKIN2.HCLK_CMT_CK_BUFHCLK3 origin:045-hclk-cmt-pips 26_117 27_120
HCLK_CMT_L.HCLK_CMT_MUX_MMCM_CLKIN2.HCLK_CMT_CK_BUFHCLK4 origin:045-hclk-cmt-pips 26_117 26_120
HCLK_CMT_L.HCLK_CMT_MUX_MMCM_CLKIN2.HCLK_CMT_CK_BUFHCLK5 origin:045-hclk-cmt-pips 26_117 27_119
HCLK_CMT_L.HCLK_CMT_MUX_MMCM_CLKIN2.HCLK_CMT_CK_BUFHCLK6 origin:045-hclk-cmt-pips 26_122 27_117
HCLK_CMT_L.HCLK_CMT_MUX_MMCM_CLKIN2.HCLK_CMT_CK_BUFHCLK7 origin:045-hclk-cmt-pips 27_117 27_121
HCLK_CMT_L.HCLK_CMT_MUX_MMCM_CLKIN2.HCLK_CMT_CK_BUFHCLK8 origin:045-hclk-cmt-pips 26_121 27_117
HCLK_CMT_L.HCLK_CMT_MUX_MMCM_CLKIN2.HCLK_CMT_CK_BUFHCLK9 origin:045-hclk-cmt-pips 27_117 27_120
HCLK_CMT_L.HCLK_CMT_MUX_MMCM_CLKIN2.HCLK_CMT_CK_BUFRCLK0 origin:045-hclk-cmt-pips 26_118 26_122
HCLK_CMT_L.HCLK_CMT_MUX_MMCM_CLKIN2.HCLK_CMT_CK_BUFRCLK1 origin:045-hclk-cmt-pips 26_118 27_121
HCLK_CMT_L.HCLK_CMT_MUX_MMCM_CLKIN2.HCLK_CMT_CK_BUFRCLK2 origin:045-hclk-cmt-pips 26_118 26_121
HCLK_CMT_L.HCLK_CMT_MUX_MMCM_CLKIN2.HCLK_CMT_CK_BUFRCLK3 origin:045-hclk-cmt-pips 26_118 27_120
HCLK_CMT_L.HCLK_CMT_MUX_PLLE2_CLKFBIN.HCLK_CMT_CCIO0 origin:045-hclk-cmt-pips 26_226 26_228
HCLK_CMT_L.HCLK_CMT_MUX_PLLE2_CLKFBIN.HCLK_CMT_CCIO1 origin:045-hclk-cmt-pips 26_228 27_226
HCLK_CMT_L.HCLK_CMT_MUX_PLLE2_CLKFBIN.HCLK_CMT_CCIO2 origin:045-hclk-cmt-pips 26_226 27_227
HCLK_CMT_L.HCLK_CMT_MUX_PLLE2_CLKFBIN.HCLK_CMT_CCIO3 origin:045-hclk-cmt-pips 27_226 27_227
HCLK_CMT_L.HCLK_CMT_MUX_PLLE2_CLKFBIN.HCLK_CMT_CK_BUFHCLK0 origin:045-hclk-cmt-pips 26_224 26_229
HCLK_CMT_L.HCLK_CMT_MUX_PLLE2_CLKFBIN.HCLK_CMT_CK_BUFHCLK1 origin:045-hclk-cmt-pips 26_229 27_224
HCLK_CMT_L.HCLK_CMT_MUX_PLLE2_CLKFBIN.HCLK_CMT_CK_BUFHCLK10 origin:045-hclk-cmt-pips 26_226 27_228
HCLK_CMT_L.HCLK_CMT_MUX_PLLE2_CLKFBIN.HCLK_CMT_CK_BUFHCLK11 origin:045-hclk-cmt-pips 27_226 27_228
HCLK_CMT_L.HCLK_CMT_MUX_PLLE2_CLKFBIN.HCLK_CMT_CK_BUFHCLK2 origin:045-hclk-cmt-pips 26_225 26_229
HCLK_CMT_L.HCLK_CMT_MUX_PLLE2_CLKFBIN.HCLK_CMT_CK_BUFHCLK3 origin:045-hclk-cmt-pips 26_229 27_225
HCLK_CMT_L.HCLK_CMT_MUX_PLLE2_CLKFBIN.HCLK_CMT_CK_BUFHCLK4 origin:045-hclk-cmt-pips 26_226 26_229
HCLK_CMT_L.HCLK_CMT_MUX_PLLE2_CLKFBIN.HCLK_CMT_CK_BUFHCLK5 origin:045-hclk-cmt-pips 26_229 27_226
HCLK_CMT_L.HCLK_CMT_MUX_PLLE2_CLKFBIN.HCLK_CMT_CK_BUFHCLK6 origin:045-hclk-cmt-pips 26_224 27_228
HCLK_CMT_L.HCLK_CMT_MUX_PLLE2_CLKFBIN.HCLK_CMT_CK_BUFHCLK7 origin:045-hclk-cmt-pips 27_224 27_228
HCLK_CMT_L.HCLK_CMT_MUX_PLLE2_CLKFBIN.HCLK_CMT_CK_BUFHCLK8 origin:045-hclk-cmt-pips 26_225 27_228
HCLK_CMT_L.HCLK_CMT_MUX_PLLE2_CLKFBIN.HCLK_CMT_CK_BUFHCLK9 origin:045-hclk-cmt-pips 27_225 27_228
HCLK_CMT_L.HCLK_CMT_MUX_PLLE2_CLKFBIN.HCLK_CMT_CK_BUFRCLK0 origin:045-hclk-cmt-pips 26_224 26_228
HCLK_CMT_L.HCLK_CMT_MUX_PLLE2_CLKFBIN.HCLK_CMT_CK_BUFRCLK1 origin:045-hclk-cmt-pips 26_228 27_224
HCLK_CMT_L.HCLK_CMT_MUX_PLLE2_CLKFBIN.HCLK_CMT_CK_BUFRCLK2 origin:045-hclk-cmt-pips 26_225 26_228
HCLK_CMT_L.HCLK_CMT_MUX_PLLE2_CLKFBIN.HCLK_CMT_CK_BUFRCLK3 origin:045-hclk-cmt-pips 26_228 27_225
HCLK_CMT_L.HCLK_CMT_MUX_PLLE2_CLKIN1.HCLK_CMT_CCIO0 origin:045-hclk-cmt-pips 29_231 29_233
HCLK_CMT_L.HCLK_CMT_MUX_PLLE2_CLKIN1.HCLK_CMT_CCIO1 origin:045-hclk-cmt-pips 28_232 29_233
HCLK_CMT_L.HCLK_CMT_MUX_PLLE2_CLKIN1.HCLK_CMT_CCIO2 origin:045-hclk-cmt-pips 28_233 29_231
HCLK_CMT_L.HCLK_CMT_MUX_PLLE2_CLKIN1.HCLK_CMT_CCIO3 origin:045-hclk-cmt-pips 28_232 28_233
HCLK_CMT_L.HCLK_CMT_MUX_PLLE2_CLKIN1.HCLK_CMT_CK_BUFHCLK0 origin:045-hclk-cmt-pips 29_229 29_234
HCLK_CMT_L.HCLK_CMT_MUX_PLLE2_CLKIN1.HCLK_CMT_CK_BUFHCLK1 origin:045-hclk-cmt-pips 28_230 29_234
HCLK_CMT_L.HCLK_CMT_MUX_PLLE2_CLKIN1.HCLK_CMT_CK_BUFHCLK10 origin:045-hclk-cmt-pips 28_234 29_231
HCLK_CMT_L.HCLK_CMT_MUX_PLLE2_CLKIN1.HCLK_CMT_CK_BUFHCLK11 origin:045-hclk-cmt-pips 28_232 28_234
HCLK_CMT_L.HCLK_CMT_MUX_PLLE2_CLKIN1.HCLK_CMT_CK_BUFHCLK2 origin:045-hclk-cmt-pips 29_230 29_234
HCLK_CMT_L.HCLK_CMT_MUX_PLLE2_CLKIN1.HCLK_CMT_CK_BUFHCLK3 origin:045-hclk-cmt-pips 28_231 29_234
HCLK_CMT_L.HCLK_CMT_MUX_PLLE2_CLKIN1.HCLK_CMT_CK_BUFHCLK4 origin:045-hclk-cmt-pips 29_231 29_234
HCLK_CMT_L.HCLK_CMT_MUX_PLLE2_CLKIN1.HCLK_CMT_CK_BUFHCLK5 origin:045-hclk-cmt-pips 28_232 29_234
HCLK_CMT_L.HCLK_CMT_MUX_PLLE2_CLKIN1.HCLK_CMT_CK_BUFHCLK6 origin:045-hclk-cmt-pips 28_234 29_229
HCLK_CMT_L.HCLK_CMT_MUX_PLLE2_CLKIN1.HCLK_CMT_CK_BUFHCLK7 origin:045-hclk-cmt-pips 28_230 28_234
HCLK_CMT_L.HCLK_CMT_MUX_PLLE2_CLKIN1.HCLK_CMT_CK_BUFHCLK8 origin:045-hclk-cmt-pips 28_234 29_230
HCLK_CMT_L.HCLK_CMT_MUX_PLLE2_CLKIN1.HCLK_CMT_CK_BUFHCLK9 origin:045-hclk-cmt-pips 28_231 28_234
HCLK_CMT_L.HCLK_CMT_MUX_PLLE2_CLKIN1.HCLK_CMT_CK_BUFRCLK0 origin:045-hclk-cmt-pips 29_229 29_233
HCLK_CMT_L.HCLK_CMT_MUX_PLLE2_CLKIN1.HCLK_CMT_CK_BUFRCLK1 origin:045-hclk-cmt-pips 28_230 29_233
HCLK_CMT_L.HCLK_CMT_MUX_PLLE2_CLKIN1.HCLK_CMT_CK_BUFRCLK2 origin:045-hclk-cmt-pips 29_230 29_233
HCLK_CMT_L.HCLK_CMT_MUX_PLLE2_CLKIN1.HCLK_CMT_CK_BUFRCLK3 origin:045-hclk-cmt-pips 28_231 29_233
HCLK_CMT_L.HCLK_CMT_MUX_PLLE2_CLKIN2.HCLK_CMT_CCIO0 origin:045-hclk-cmt-pips 27_231 27_233
HCLK_CMT_L.HCLK_CMT_MUX_PLLE2_CLKIN2.HCLK_CMT_CCIO1 origin:045-hclk-cmt-pips 26_232 27_233
HCLK_CMT_L.HCLK_CMT_MUX_PLLE2_CLKIN2.HCLK_CMT_CCIO2 origin:045-hclk-cmt-pips 26_233 27_231
HCLK_CMT_L.HCLK_CMT_MUX_PLLE2_CLKIN2.HCLK_CMT_CCIO3 origin:045-hclk-cmt-pips 26_232 26_233
HCLK_CMT_L.HCLK_CMT_MUX_PLLE2_CLKIN2.HCLK_CMT_CK_BUFHCLK0 origin:045-hclk-cmt-pips 27_229 27_234
HCLK_CMT_L.HCLK_CMT_MUX_PLLE2_CLKIN2.HCLK_CMT_CK_BUFHCLK1 origin:045-hclk-cmt-pips 26_230 27_234
HCLK_CMT_L.HCLK_CMT_MUX_PLLE2_CLKIN2.HCLK_CMT_CK_BUFHCLK10 origin:045-hclk-cmt-pips 26_234 27_231
HCLK_CMT_L.HCLK_CMT_MUX_PLLE2_CLKIN2.HCLK_CMT_CK_BUFHCLK11 origin:045-hclk-cmt-pips 26_232 26_234
HCLK_CMT_L.HCLK_CMT_MUX_PLLE2_CLKIN2.HCLK_CMT_CK_BUFHCLK2 origin:045-hclk-cmt-pips 27_230 27_234
HCLK_CMT_L.HCLK_CMT_MUX_PLLE2_CLKIN2.HCLK_CMT_CK_BUFHCLK3 origin:045-hclk-cmt-pips 26_231 27_234
HCLK_CMT_L.HCLK_CMT_MUX_PLLE2_CLKIN2.HCLK_CMT_CK_BUFHCLK4 origin:045-hclk-cmt-pips 27_231 27_234
HCLK_CMT_L.HCLK_CMT_MUX_PLLE2_CLKIN2.HCLK_CMT_CK_BUFHCLK5 origin:045-hclk-cmt-pips 26_232 27_234
HCLK_CMT_L.HCLK_CMT_MUX_PLLE2_CLKIN2.HCLK_CMT_CK_BUFHCLK6 origin:045-hclk-cmt-pips 26_234 27_229
HCLK_CMT_L.HCLK_CMT_MUX_PLLE2_CLKIN2.HCLK_CMT_CK_BUFHCLK7 origin:045-hclk-cmt-pips 26_230 26_234
HCLK_CMT_L.HCLK_CMT_MUX_PLLE2_CLKIN2.HCLK_CMT_CK_BUFHCLK8 origin:045-hclk-cmt-pips 26_234 27_230
HCLK_CMT_L.HCLK_CMT_MUX_PLLE2_CLKIN2.HCLK_CMT_CK_BUFHCLK9 origin:045-hclk-cmt-pips 26_231 26_234
HCLK_CMT_L.HCLK_CMT_MUX_PLLE2_CLKIN2.HCLK_CMT_CK_BUFRCLK0 origin:045-hclk-cmt-pips 27_229 27_233
HCLK_CMT_L.HCLK_CMT_MUX_PLLE2_CLKIN2.HCLK_CMT_CK_BUFRCLK1 origin:045-hclk-cmt-pips 26_230 27_233
HCLK_CMT_L.HCLK_CMT_MUX_PLLE2_CLKIN2.HCLK_CMT_CK_BUFRCLK2 origin:045-hclk-cmt-pips 27_230 27_233
HCLK_CMT_L.HCLK_CMT_MUX_PLLE2_CLKIN2.HCLK_CMT_CK_BUFRCLK3 origin:045-hclk-cmt-pips 26_231 27_233

196
zynq7/segbits_hclk_l.origin_info.db Normal file
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HCLK_L.ENABLE_BUFFER.HCLK_CK_BUFHCLK10 origin:058-pip-hclk 00_22
HCLK_L.ENABLE_BUFFER.HCLK_CK_BUFHCLK11 origin:058-pip-hclk 01_22
HCLK_L.ENABLE_BUFFER.HCLK_CK_BUFHCLK8 origin:058-pip-hclk 00_14
HCLK_L.ENABLE_BUFFER.HCLK_CK_BUFHCLK9 origin:058-pip-hclk 01_19
HCLK_L.HCLK_LEAF_CLK_B_BOTL0.HCLK_CK_BUFHCLK10 origin:058-pip-hclk 01_15 04_15
HCLK_L.HCLK_LEAF_CLK_B_BOTL0.HCLK_CK_BUFHCLK11 origin:058-pip-hclk 01_15 03_15
HCLK_L.HCLK_LEAF_CLK_B_BOTL0.HCLK_CK_BUFHCLK8 origin:058-pip-hclk 01_15 04_14
HCLK_L.HCLK_LEAF_CLK_B_BOTL0.HCLK_CK_BUFHCLK9 origin:058-pip-hclk 01_15 03_14
HCLK_L.HCLK_LEAF_CLK_B_BOTL0.HCLK_CK_BUFRCLK0 origin:058-pip-hclk 00_16 04_14
HCLK_L.HCLK_LEAF_CLK_B_BOTL0.HCLK_CK_BUFRCLK1 origin:058-pip-hclk 00_16 03_14
HCLK_L.HCLK_LEAF_CLK_B_BOTL0.HCLK_CK_BUFRCLK2 origin:058-pip-hclk 00_16 04_15
HCLK_L.HCLK_LEAF_CLK_B_BOTL0.HCLK_CK_BUFRCLK3 origin:058-pip-hclk 00_16 03_15
HCLK_L.HCLK_LEAF_CLK_B_BOTL0.HCLK_CK_OUTIN_L0 origin:058-pip-hclk 01_14 04_14
HCLK_L.HCLK_LEAF_CLK_B_BOTL0.HCLK_CK_OUTIN_L1 origin:058-pip-hclk 01_14 03_14
HCLK_L.HCLK_LEAF_CLK_B_BOTL0.HCLK_CK_OUTIN_L2 origin:058-pip-hclk 01_14 04_15
HCLK_L.HCLK_LEAF_CLK_B_BOTL0.HCLK_CK_OUTIN_L3 origin:058-pip-hclk 01_14 03_15
HCLK_L.HCLK_LEAF_CLK_B_BOTL0.HCLK_CK_OUTIN_L4 origin:058-pip-hclk 00_15 04_14
HCLK_L.HCLK_LEAF_CLK_B_BOTL0.HCLK_CK_OUTIN_L5 origin:058-pip-hclk 00_15 03_14
HCLK_L.HCLK_LEAF_CLK_B_BOTL0.HCLK_CK_OUTIN_L6 origin:058-pip-hclk 00_15 04_15
HCLK_L.HCLK_LEAF_CLK_B_BOTL0.HCLK_CK_OUTIN_L7 origin:058-pip-hclk 00_15 03_15
HCLK_L.HCLK_LEAF_CLK_B_BOTL1.HCLK_CK_BUFHCLK10 origin:058-pip-hclk 02_15 04_16
HCLK_L.HCLK_LEAF_CLK_B_BOTL1.HCLK_CK_BUFHCLK11 origin:058-pip-hclk 04_16 05_15
HCLK_L.HCLK_LEAF_CLK_B_BOTL1.HCLK_CK_BUFHCLK8 origin:058-pip-hclk 02_14 04_16
HCLK_L.HCLK_LEAF_CLK_B_BOTL1.HCLK_CK_BUFHCLK9 origin:058-pip-hclk 04_16 05_14
HCLK_L.HCLK_LEAF_CLK_B_BOTL1.HCLK_CK_BUFRCLK0 origin:058-pip-hclk 02_14 02_16
HCLK_L.HCLK_LEAF_CLK_B_BOTL1.HCLK_CK_BUFRCLK1 origin:058-pip-hclk 02_16 05_14
HCLK_L.HCLK_LEAF_CLK_B_BOTL1.HCLK_CK_BUFRCLK2 origin:058-pip-hclk 02_15 02_16
HCLK_L.HCLK_LEAF_CLK_B_BOTL1.HCLK_CK_BUFRCLK3 origin:058-pip-hclk 02_16 05_15
HCLK_L.HCLK_LEAF_CLK_B_BOTL1.HCLK_CK_OUTIN_L0 origin:058-pip-hclk 02_14 03_16
HCLK_L.HCLK_LEAF_CLK_B_BOTL1.HCLK_CK_OUTIN_L1 origin:058-pip-hclk 03_16 05_14
HCLK_L.HCLK_LEAF_CLK_B_BOTL1.HCLK_CK_OUTIN_L2 origin:058-pip-hclk 02_15 03_16
HCLK_L.HCLK_LEAF_CLK_B_BOTL1.HCLK_CK_OUTIN_L3 origin:058-pip-hclk 03_16 05_15
HCLK_L.HCLK_LEAF_CLK_B_BOTL1.HCLK_CK_OUTIN_L4 origin:058-pip-hclk 02_14 05_16
HCLK_L.HCLK_LEAF_CLK_B_BOTL1.HCLK_CK_OUTIN_L5 origin:058-pip-hclk 05_14 05_16
HCLK_L.HCLK_LEAF_CLK_B_BOTL1.HCLK_CK_OUTIN_L6 origin:058-pip-hclk 02_15 05_16
HCLK_L.HCLK_LEAF_CLK_B_BOTL1.HCLK_CK_OUTIN_L7 origin:058-pip-hclk 05_15 05_16
HCLK_L.HCLK_LEAF_CLK_B_BOTL2.HCLK_CK_BUFHCLK10 origin:058-pip-hclk 00_17 05_18
HCLK_L.HCLK_LEAF_CLK_B_BOTL2.HCLK_CK_BUFHCLK11 origin:058-pip-hclk 00_17 02_18
HCLK_L.HCLK_LEAF_CLK_B_BOTL2.HCLK_CK_BUFHCLK8 origin:058-pip-hclk 00_17 05_19
HCLK_L.HCLK_LEAF_CLK_B_BOTL2.HCLK_CK_BUFHCLK9 origin:058-pip-hclk 00_17 02_19
HCLK_L.HCLK_LEAF_CLK_B_BOTL2.HCLK_CK_BUFRCLK0 origin:058-pip-hclk 01_16 05_19
HCLK_L.HCLK_LEAF_CLK_B_BOTL2.HCLK_CK_BUFRCLK1 origin:058-pip-hclk 01_16 02_19
HCLK_L.HCLK_LEAF_CLK_B_BOTL2.HCLK_CK_BUFRCLK2 origin:058-pip-hclk 01_16 05_18
HCLK_L.HCLK_LEAF_CLK_B_BOTL2.HCLK_CK_BUFRCLK3 origin:058-pip-hclk 01_16 02_18
HCLK_L.HCLK_LEAF_CLK_B_BOTL2.HCLK_CK_OUTIN_L0 origin:058-pip-hclk 00_18 05_19
HCLK_L.HCLK_LEAF_CLK_B_BOTL2.HCLK_CK_OUTIN_L1 origin:058-pip-hclk 00_18 02_19
HCLK_L.HCLK_LEAF_CLK_B_BOTL2.HCLK_CK_OUTIN_L2 origin:058-pip-hclk 00_18 05_18
HCLK_L.HCLK_LEAF_CLK_B_BOTL2.HCLK_CK_OUTIN_L3 origin:058-pip-hclk 00_18 02_18
HCLK_L.HCLK_LEAF_CLK_B_BOTL2.HCLK_CK_OUTIN_L4 origin:058-pip-hclk 01_17 05_19
HCLK_L.HCLK_LEAF_CLK_B_BOTL2.HCLK_CK_OUTIN_L5 origin:058-pip-hclk 01_17 02_19
HCLK_L.HCLK_LEAF_CLK_B_BOTL2.HCLK_CK_OUTIN_L6 origin:058-pip-hclk 01_17 05_18
HCLK_L.HCLK_LEAF_CLK_B_BOTL2.HCLK_CK_OUTIN_L7 origin:058-pip-hclk 01_17 02_18
HCLK_L.HCLK_LEAF_CLK_B_BOTL3.HCLK_CK_BUFHCLK10 origin:058-pip-hclk 03_18 05_17
HCLK_L.HCLK_LEAF_CLK_B_BOTL3.HCLK_CK_BUFHCLK11 origin:058-pip-hclk 04_18 05_17
HCLK_L.HCLK_LEAF_CLK_B_BOTL3.HCLK_CK_BUFHCLK8 origin:058-pip-hclk 03_19 05_17
HCLK_L.HCLK_LEAF_CLK_B_BOTL3.HCLK_CK_BUFHCLK9 origin:058-pip-hclk 04_19 05_17
HCLK_L.HCLK_LEAF_CLK_B_BOTL3.HCLK_CK_BUFRCLK0 origin:058-pip-hclk 03_17 03_19
HCLK_L.HCLK_LEAF_CLK_B_BOTL3.HCLK_CK_BUFRCLK1 origin:058-pip-hclk 03_17 04_19
HCLK_L.HCLK_LEAF_CLK_B_BOTL3.HCLK_CK_BUFRCLK2 origin:058-pip-hclk 03_17 03_18
HCLK_L.HCLK_LEAF_CLK_B_BOTL3.HCLK_CK_BUFRCLK3 origin:058-pip-hclk 03_17 04_18
HCLK_L.HCLK_LEAF_CLK_B_BOTL3.HCLK_CK_OUTIN_L0 origin:058-pip-hclk 02_17 03_19
HCLK_L.HCLK_LEAF_CLK_B_BOTL3.HCLK_CK_OUTIN_L1 origin:058-pip-hclk 02_17 04_19
HCLK_L.HCLK_LEAF_CLK_B_BOTL3.HCLK_CK_OUTIN_L2 origin:058-pip-hclk 02_17 03_18
HCLK_L.HCLK_LEAF_CLK_B_BOTL3.HCLK_CK_OUTIN_L3 origin:058-pip-hclk 02_17 04_18
HCLK_L.HCLK_LEAF_CLK_B_BOTL3.HCLK_CK_OUTIN_L4 origin:058-pip-hclk 03_19 04_17
HCLK_L.HCLK_LEAF_CLK_B_BOTL3.HCLK_CK_OUTIN_L5 origin:058-pip-hclk 04_17 04_19
HCLK_L.HCLK_LEAF_CLK_B_BOTL3.HCLK_CK_OUTIN_L6 origin:058-pip-hclk 03_18 04_17
HCLK_L.HCLK_LEAF_CLK_B_BOTL3.HCLK_CK_OUTIN_L7 origin:058-pip-hclk 04_17 04_18
HCLK_L.HCLK_LEAF_CLK_B_BOTL4.HCLK_CK_BUFHCLK10 origin:058-pip-hclk 00_21 04_21
HCLK_L.HCLK_LEAF_CLK_B_BOTL4.HCLK_CK_BUFHCLK11 origin:058-pip-hclk 00_21 03_21
HCLK_L.HCLK_LEAF_CLK_B_BOTL4.HCLK_CK_BUFHCLK8 origin:058-pip-hclk 00_21 04_20
HCLK_L.HCLK_LEAF_CLK_B_BOTL4.HCLK_CK_BUFHCLK9 origin:058-pip-hclk 00_21 03_20
HCLK_L.HCLK_LEAF_CLK_B_BOTL4.HCLK_CK_BUFRCLK0 origin:058-pip-hclk 01_21 04_20
HCLK_L.HCLK_LEAF_CLK_B_BOTL4.HCLK_CK_BUFRCLK1 origin:058-pip-hclk 01_21 03_20
HCLK_L.HCLK_LEAF_CLK_B_BOTL4.HCLK_CK_BUFRCLK2 origin:058-pip-hclk 01_21 04_21
HCLK_L.HCLK_LEAF_CLK_B_BOTL4.HCLK_CK_BUFRCLK3 origin:058-pip-hclk 01_21 03_21
HCLK_L.HCLK_LEAF_CLK_B_BOTL4.HCLK_CK_OUTIN_L0 origin:058-pip-hclk 00_20 04_20
HCLK_L.HCLK_LEAF_CLK_B_BOTL4.HCLK_CK_OUTIN_L1 origin:058-pip-hclk 00_20 03_20
HCLK_L.HCLK_LEAF_CLK_B_BOTL4.HCLK_CK_OUTIN_L2 origin:058-pip-hclk 00_20 04_21
HCLK_L.HCLK_LEAF_CLK_B_BOTL4.HCLK_CK_OUTIN_L3 origin:058-pip-hclk 00_20 03_21
HCLK_L.HCLK_LEAF_CLK_B_BOTL4.HCLK_CK_OUTIN_L4 origin:058-pip-hclk 01_20 04_20
HCLK_L.HCLK_LEAF_CLK_B_BOTL4.HCLK_CK_OUTIN_L5 origin:058-pip-hclk 01_20 03_20
HCLK_L.HCLK_LEAF_CLK_B_BOTL4.HCLK_CK_OUTIN_L6 origin:058-pip-hclk 01_20 04_21
HCLK_L.HCLK_LEAF_CLK_B_BOTL4.HCLK_CK_OUTIN_L7 origin:058-pip-hclk 01_20 03_21
HCLK_L.HCLK_LEAF_CLK_B_BOTL5.HCLK_CK_BUFHCLK10 origin:058-pip-hclk 02_21 04_22
HCLK_L.HCLK_LEAF_CLK_B_BOTL5.HCLK_CK_BUFHCLK11 origin:058-pip-hclk 04_22 05_21
HCLK_L.HCLK_LEAF_CLK_B_BOTL5.HCLK_CK_BUFHCLK8 origin:058-pip-hclk 02_20 04_22
HCLK_L.HCLK_LEAF_CLK_B_BOTL5.HCLK_CK_BUFHCLK9 origin:058-pip-hclk 04_22 05_20
HCLK_L.HCLK_LEAF_CLK_B_BOTL5.HCLK_CK_BUFRCLK0 origin:058-pip-hclk 02_20 02_22
HCLK_L.HCLK_LEAF_CLK_B_BOTL5.HCLK_CK_BUFRCLK1 origin:058-pip-hclk 02_22 05_20
HCLK_L.HCLK_LEAF_CLK_B_BOTL5.HCLK_CK_BUFRCLK2 origin:058-pip-hclk 02_21 02_22
HCLK_L.HCLK_LEAF_CLK_B_BOTL5.HCLK_CK_BUFRCLK3 origin:058-pip-hclk 02_22 05_21
HCLK_L.HCLK_LEAF_CLK_B_BOTL5.HCLK_CK_OUTIN_L0 origin:058-pip-hclk 02_20 03_22
HCLK_L.HCLK_LEAF_CLK_B_BOTL5.HCLK_CK_OUTIN_L1 origin:058-pip-hclk 03_22 05_20
HCLK_L.HCLK_LEAF_CLK_B_BOTL5.HCLK_CK_OUTIN_L2 origin:058-pip-hclk 02_21 03_22
HCLK_L.HCLK_LEAF_CLK_B_BOTL5.HCLK_CK_OUTIN_L3 origin:058-pip-hclk 03_22 05_21
HCLK_L.HCLK_LEAF_CLK_B_BOTL5.HCLK_CK_OUTIN_L4 origin:058-pip-hclk 02_20 05_22
HCLK_L.HCLK_LEAF_CLK_B_BOTL5.HCLK_CK_OUTIN_L5 origin:058-pip-hclk 05_20 05_22
HCLK_L.HCLK_LEAF_CLK_B_BOTL5.HCLK_CK_OUTIN_L6 origin:058-pip-hclk 02_21 05_22
HCLK_L.HCLK_LEAF_CLK_B_BOTL5.HCLK_CK_OUTIN_L7 origin:058-pip-hclk 05_21 05_22
HCLK_L.HCLK_LEAF_CLK_B_TOPL0.HCLK_CK_BUFHCLK10 origin:058-pip-hclk 01_29 05_30
HCLK_L.HCLK_LEAF_CLK_B_TOPL0.HCLK_CK_BUFHCLK11 origin:058-pip-hclk 01_29 02_30
HCLK_L.HCLK_LEAF_CLK_B_TOPL0.HCLK_CK_BUFHCLK8 origin:058-pip-hclk 01_29 05_31
HCLK_L.HCLK_LEAF_CLK_B_TOPL0.HCLK_CK_BUFHCLK9 origin:058-pip-hclk 01_29 02_31
HCLK_L.HCLK_LEAF_CLK_B_TOPL0.HCLK_CK_BUFRCLK0 origin:058-pip-hclk 00_29 05_31
HCLK_L.HCLK_LEAF_CLK_B_TOPL0.HCLK_CK_BUFRCLK1 origin:058-pip-hclk 00_29 02_31
HCLK_L.HCLK_LEAF_CLK_B_TOPL0.HCLK_CK_BUFRCLK2 origin:058-pip-hclk 00_29 05_30
HCLK_L.HCLK_LEAF_CLK_B_TOPL0.HCLK_CK_BUFRCLK3 origin:058-pip-hclk 00_29 02_30
HCLK_L.HCLK_LEAF_CLK_B_TOPL0.HCLK_CK_OUTIN_L0 origin:058-pip-hclk 01_30 05_31
HCLK_L.HCLK_LEAF_CLK_B_TOPL0.HCLK_CK_OUTIN_L1 origin:058-pip-hclk 01_30 02_31
HCLK_L.HCLK_LEAF_CLK_B_TOPL0.HCLK_CK_OUTIN_L2 origin:058-pip-hclk 01_30 05_30
HCLK_L.HCLK_LEAF_CLK_B_TOPL0.HCLK_CK_OUTIN_L3 origin:058-pip-hclk 01_30 02_30
HCLK_L.HCLK_LEAF_CLK_B_TOPL0.HCLK_CK_OUTIN_L4 origin:058-pip-hclk 00_30 05_31
HCLK_L.HCLK_LEAF_CLK_B_TOPL0.HCLK_CK_OUTIN_L5 origin:058-pip-hclk 00_30 02_31
HCLK_L.HCLK_LEAF_CLK_B_TOPL0.HCLK_CK_OUTIN_L6 origin:058-pip-hclk 00_30 05_30
HCLK_L.HCLK_LEAF_CLK_B_TOPL0.HCLK_CK_OUTIN_L7 origin:058-pip-hclk 00_30 02_30
HCLK_L.HCLK_LEAF_CLK_B_TOPL1.HCLK_CK_BUFHCLK10 origin:058-pip-hclk 03_30 05_29
HCLK_L.HCLK_LEAF_CLK_B_TOPL1.HCLK_CK_BUFHCLK11 origin:058-pip-hclk 04_30 05_29
HCLK_L.HCLK_LEAF_CLK_B_TOPL1.HCLK_CK_BUFHCLK8 origin:058-pip-hclk 03_31 05_29
HCLK_L.HCLK_LEAF_CLK_B_TOPL1.HCLK_CK_BUFHCLK9 origin:058-pip-hclk 04_31 05_29
HCLK_L.HCLK_LEAF_CLK_B_TOPL1.HCLK_CK_BUFRCLK0 origin:058-pip-hclk 03_29 03_31
HCLK_L.HCLK_LEAF_CLK_B_TOPL1.HCLK_CK_BUFRCLK1 origin:058-pip-hclk 03_29 04_31
HCLK_L.HCLK_LEAF_CLK_B_TOPL1.HCLK_CK_BUFRCLK2 origin:058-pip-hclk 03_29 03_30
HCLK_L.HCLK_LEAF_CLK_B_TOPL1.HCLK_CK_BUFRCLK3 origin:058-pip-hclk 03_29 04_30
HCLK_L.HCLK_LEAF_CLK_B_TOPL1.HCLK_CK_OUTIN_L0 origin:058-pip-hclk 02_29 03_31
HCLK_L.HCLK_LEAF_CLK_B_TOPL1.HCLK_CK_OUTIN_L1 origin:058-pip-hclk 02_29 04_31
HCLK_L.HCLK_LEAF_CLK_B_TOPL1.HCLK_CK_OUTIN_L2 origin:058-pip-hclk 02_29 03_30
HCLK_L.HCLK_LEAF_CLK_B_TOPL1.HCLK_CK_OUTIN_L3 origin:058-pip-hclk 02_29 04_30
HCLK_L.HCLK_LEAF_CLK_B_TOPL1.HCLK_CK_OUTIN_L4 origin:058-pip-hclk 03_31 04_29
HCLK_L.HCLK_LEAF_CLK_B_TOPL1.HCLK_CK_OUTIN_L5 origin:058-pip-hclk 04_29 04_31
HCLK_L.HCLK_LEAF_CLK_B_TOPL1.HCLK_CK_OUTIN_L6 origin:058-pip-hclk 03_30 04_29
HCLK_L.HCLK_LEAF_CLK_B_TOPL1.HCLK_CK_OUTIN_L7 origin:058-pip-hclk 04_29 04_30
HCLK_L.HCLK_LEAF_CLK_B_TOPL2.HCLK_CK_BUFHCLK10 origin:058-pip-hclk 00_28 04_27
HCLK_L.HCLK_LEAF_CLK_B_TOPL2.HCLK_CK_BUFHCLK11 origin:058-pip-hclk 00_28 03_27
HCLK_L.HCLK_LEAF_CLK_B_TOPL2.HCLK_CK_BUFHCLK8 origin:058-pip-hclk 00_28 04_26
HCLK_L.HCLK_LEAF_CLK_B_TOPL2.HCLK_CK_BUFHCLK9 origin:058-pip-hclk 00_28 03_26
HCLK_L.HCLK_LEAF_CLK_B_TOPL2.HCLK_CK_BUFRCLK0 origin:058-pip-hclk 01_28 04_26
HCLK_L.HCLK_LEAF_CLK_B_TOPL2.HCLK_CK_BUFRCLK1 origin:058-pip-hclk 01_28 03_26
HCLK_L.HCLK_LEAF_CLK_B_TOPL2.HCLK_CK_BUFRCLK2 origin:058-pip-hclk 01_28 04_27
HCLK_L.HCLK_LEAF_CLK_B_TOPL2.HCLK_CK_BUFRCLK3 origin:058-pip-hclk 01_28 03_27
HCLK_L.HCLK_LEAF_CLK_B_TOPL2.HCLK_CK_OUTIN_L0 origin:058-pip-hclk 00_26 04_26
HCLK_L.HCLK_LEAF_CLK_B_TOPL2.HCLK_CK_OUTIN_L1 origin:058-pip-hclk 00_26 03_26
HCLK_L.HCLK_LEAF_CLK_B_TOPL2.HCLK_CK_OUTIN_L2 origin:058-pip-hclk 00_26 04_27
HCLK_L.HCLK_LEAF_CLK_B_TOPL2.HCLK_CK_OUTIN_L3 origin:058-pip-hclk 00_26 03_27
HCLK_L.HCLK_LEAF_CLK_B_TOPL2.HCLK_CK_OUTIN_L4 origin:058-pip-hclk 01_26 04_26
HCLK_L.HCLK_LEAF_CLK_B_TOPL2.HCLK_CK_OUTIN_L5 origin:058-pip-hclk 01_26 03_26
HCLK_L.HCLK_LEAF_CLK_B_TOPL2.HCLK_CK_OUTIN_L6 origin:058-pip-hclk 01_26 04_27
HCLK_L.HCLK_LEAF_CLK_B_TOPL2.HCLK_CK_OUTIN_L7 origin:058-pip-hclk 01_26 03_27
HCLK_L.HCLK_LEAF_CLK_B_TOPL3.HCLK_CK_BUFHCLK10 origin:058-pip-hclk 02_27 04_28
HCLK_L.HCLK_LEAF_CLK_B_TOPL3.HCLK_CK_BUFHCLK11 origin:058-pip-hclk 04_28 05_27
HCLK_L.HCLK_LEAF_CLK_B_TOPL3.HCLK_CK_BUFHCLK8 origin:058-pip-hclk 02_26 04_28
HCLK_L.HCLK_LEAF_CLK_B_TOPL3.HCLK_CK_BUFHCLK9 origin:058-pip-hclk 04_28 05_26
HCLK_L.HCLK_LEAF_CLK_B_TOPL3.HCLK_CK_BUFRCLK0 origin:058-pip-hclk 02_26 02_28
HCLK_L.HCLK_LEAF_CLK_B_TOPL3.HCLK_CK_BUFRCLK1 origin:058-pip-hclk 02_28 05_26
HCLK_L.HCLK_LEAF_CLK_B_TOPL3.HCLK_CK_BUFRCLK2 origin:058-pip-hclk 02_27 02_28
HCLK_L.HCLK_LEAF_CLK_B_TOPL3.HCLK_CK_BUFRCLK3 origin:058-pip-hclk 02_28 05_27
HCLK_L.HCLK_LEAF_CLK_B_TOPL3.HCLK_CK_OUTIN_L0 origin:058-pip-hclk 02_26 03_28
HCLK_L.HCLK_LEAF_CLK_B_TOPL3.HCLK_CK_OUTIN_L1 origin:058-pip-hclk 03_28 05_26
HCLK_L.HCLK_LEAF_CLK_B_TOPL3.HCLK_CK_OUTIN_L2 origin:058-pip-hclk 02_27 03_28
HCLK_L.HCLK_LEAF_CLK_B_TOPL3.HCLK_CK_OUTIN_L3 origin:058-pip-hclk 03_28 05_27
HCLK_L.HCLK_LEAF_CLK_B_TOPL3.HCLK_CK_OUTIN_L4 origin:058-pip-hclk 02_26 05_28
HCLK_L.HCLK_LEAF_CLK_B_TOPL3.HCLK_CK_OUTIN_L5 origin:058-pip-hclk 05_26 05_28
HCLK_L.HCLK_LEAF_CLK_B_TOPL3.HCLK_CK_OUTIN_L6 origin:058-pip-hclk 02_27 05_28
HCLK_L.HCLK_LEAF_CLK_B_TOPL3.HCLK_CK_OUTIN_L7 origin:058-pip-hclk 05_27 05_28
HCLK_L.HCLK_LEAF_CLK_B_TOPL4.HCLK_CK_BUFHCLK10 origin:058-pip-hclk 01_24 05_24
HCLK_L.HCLK_LEAF_CLK_B_TOPL4.HCLK_CK_BUFHCLK11 origin:058-pip-hclk 01_24 02_24
HCLK_L.HCLK_LEAF_CLK_B_TOPL4.HCLK_CK_BUFHCLK8 origin:058-pip-hclk 01_24 05_25
HCLK_L.HCLK_LEAF_CLK_B_TOPL4.HCLK_CK_BUFHCLK9 origin:058-pip-hclk 01_24 02_25
HCLK_L.HCLK_LEAF_CLK_B_TOPL4.HCLK_CK_BUFRCLK0 origin:058-pip-hclk 00_24 05_25
HCLK_L.HCLK_LEAF_CLK_B_TOPL4.HCLK_CK_BUFRCLK1 origin:058-pip-hclk 00_24 02_25
HCLK_L.HCLK_LEAF_CLK_B_TOPL4.HCLK_CK_BUFRCLK2 origin:058-pip-hclk 00_24 05_24
HCLK_L.HCLK_LEAF_CLK_B_TOPL4.HCLK_CK_BUFRCLK3 origin:058-pip-hclk 00_24 02_24
HCLK_L.HCLK_LEAF_CLK_B_TOPL4.HCLK_CK_OUTIN_L0 origin:058-pip-hclk 01_25 05_25
HCLK_L.HCLK_LEAF_CLK_B_TOPL4.HCLK_CK_OUTIN_L1 origin:058-pip-hclk 01_25 02_25
HCLK_L.HCLK_LEAF_CLK_B_TOPL4.HCLK_CK_OUTIN_L2 origin:058-pip-hclk 01_25 05_24
HCLK_L.HCLK_LEAF_CLK_B_TOPL4.HCLK_CK_OUTIN_L3 origin:058-pip-hclk 01_25 02_24
HCLK_L.HCLK_LEAF_CLK_B_TOPL4.HCLK_CK_OUTIN_L4 origin:058-pip-hclk 00_25 05_25
HCLK_L.HCLK_LEAF_CLK_B_TOPL4.HCLK_CK_OUTIN_L5 origin:058-pip-hclk 00_25 02_25
HCLK_L.HCLK_LEAF_CLK_B_TOPL4.HCLK_CK_OUTIN_L6 origin:058-pip-hclk 00_25 05_24
HCLK_L.HCLK_LEAF_CLK_B_TOPL4.HCLK_CK_OUTIN_L7 origin:058-pip-hclk 00_25 02_24
HCLK_L.HCLK_LEAF_CLK_B_TOPL5.HCLK_CK_BUFHCLK10 origin:058-pip-hclk 03_24 05_23
HCLK_L.HCLK_LEAF_CLK_B_TOPL5.HCLK_CK_BUFHCLK11 origin:058-pip-hclk 04_24 05_23
HCLK_L.HCLK_LEAF_CLK_B_TOPL5.HCLK_CK_BUFHCLK8 origin:058-pip-hclk 03_25 05_23
HCLK_L.HCLK_LEAF_CLK_B_TOPL5.HCLK_CK_BUFHCLK9 origin:058-pip-hclk 04_25 05_23
HCLK_L.HCLK_LEAF_CLK_B_TOPL5.HCLK_CK_BUFRCLK0 origin:058-pip-hclk 03_23 03_25
HCLK_L.HCLK_LEAF_CLK_B_TOPL5.HCLK_CK_BUFRCLK1 origin:058-pip-hclk 03_23 04_25
HCLK_L.HCLK_LEAF_CLK_B_TOPL5.HCLK_CK_BUFRCLK2 origin:058-pip-hclk 03_23 03_24
HCLK_L.HCLK_LEAF_CLK_B_TOPL5.HCLK_CK_BUFRCLK3 origin:058-pip-hclk 03_23 04_24
HCLK_L.HCLK_LEAF_CLK_B_TOPL5.HCLK_CK_OUTIN_L0 origin:058-pip-hclk 02_23 03_25
HCLK_L.HCLK_LEAF_CLK_B_TOPL5.HCLK_CK_OUTIN_L1 origin:058-pip-hclk 02_23 04_25
HCLK_L.HCLK_LEAF_CLK_B_TOPL5.HCLK_CK_OUTIN_L2 origin:058-pip-hclk 02_23 03_24
HCLK_L.HCLK_LEAF_CLK_B_TOPL5.HCLK_CK_OUTIN_L3 origin:058-pip-hclk 02_23 04_24
HCLK_L.HCLK_LEAF_CLK_B_TOPL5.HCLK_CK_OUTIN_L4 origin:058-pip-hclk 03_25 04_23
HCLK_L.HCLK_LEAF_CLK_B_TOPL5.HCLK_CK_OUTIN_L5 origin:058-pip-hclk 04_23 04_25
HCLK_L.HCLK_LEAF_CLK_B_TOPL5.HCLK_CK_OUTIN_L6 origin:058-pip-hclk 03_24 04_23
HCLK_L.HCLK_LEAF_CLK_B_TOPL5.HCLK_CK_OUTIN_L7 origin:058-pip-hclk 04_23 04_24

200
zynq7/segbits_hclk_r.origin_info.db Normal file
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@ -0,0 +1,200 @@
HCLK_R.ENABLE_BUFFER.HCLK_CK_BUFHCLK0 origin:058-pip-hclk 00_14
HCLK_R.ENABLE_BUFFER.HCLK_CK_BUFHCLK1 origin:058-pip-hclk 01_19
HCLK_R.ENABLE_BUFFER.HCLK_CK_BUFHCLK2 origin:058-pip-hclk 00_22
HCLK_R.ENABLE_BUFFER.HCLK_CK_BUFHCLK3 origin:058-pip-hclk 01_22
HCLK_R.ENABLE_BUFFER.HCLK_CK_BUFHCLK4 origin:058-pip-hclk 00_23
HCLK_R.ENABLE_BUFFER.HCLK_CK_BUFHCLK5 origin:058-pip-hclk 01_23
HCLK_R.ENABLE_BUFFER.HCLK_CK_BUFHCLK6 origin:058-pip-hclk 00_31
HCLK_R.ENABLE_BUFFER.HCLK_CK_BUFHCLK7 origin:058-pip-hclk 01_31
HCLK_R.HCLK_LEAF_CLK_B_BOT0.HCLK_CK_BUFHCLK0 origin:058-pip-hclk 01_14 04_14
HCLK_R.HCLK_LEAF_CLK_B_BOT0.HCLK_CK_BUFHCLK1 origin:058-pip-hclk 01_14 03_14
HCLK_R.HCLK_LEAF_CLK_B_BOT0.HCLK_CK_BUFHCLK2 origin:058-pip-hclk 01_14 04_15
HCLK_R.HCLK_LEAF_CLK_B_BOT0.HCLK_CK_BUFHCLK3 origin:058-pip-hclk 01_14 03_15
HCLK_R.HCLK_LEAF_CLK_B_BOT0.HCLK_CK_BUFHCLK4 origin:058-pip-hclk 00_15 04_14
HCLK_R.HCLK_LEAF_CLK_B_BOT0.HCLK_CK_BUFHCLK5 origin:058-pip-hclk 00_15 03_14
HCLK_R.HCLK_LEAF_CLK_B_BOT0.HCLK_CK_BUFHCLK6 origin:058-pip-hclk 00_15 04_15
HCLK_R.HCLK_LEAF_CLK_B_BOT0.HCLK_CK_BUFHCLK7 origin:058-pip-hclk 00_15 03_15
HCLK_R.HCLK_LEAF_CLK_B_BOT0.HCLK_CK_OUTIN_R0 origin:058-pip-hclk 00_16 04_14
HCLK_R.HCLK_LEAF_CLK_B_BOT0.HCLK_CK_OUTIN_R1 origin:058-pip-hclk 00_16 03_14
HCLK_R.HCLK_LEAF_CLK_B_BOT0.HCLK_CK_OUTIN_R2 origin:058-pip-hclk 00_16 04_15
HCLK_R.HCLK_LEAF_CLK_B_BOT0.HCLK_CK_OUTIN_R3 origin:058-pip-hclk 00_16 03_15
HCLK_R.HCLK_LEAF_CLK_B_BOT0.HCLK_CK_OUTIN_R4 origin:058-pip-hclk 01_15 04_14
HCLK_R.HCLK_LEAF_CLK_B_BOT0.HCLK_CK_OUTIN_R5 origin:058-pip-hclk 01_15 03_14
HCLK_R.HCLK_LEAF_CLK_B_BOT0.HCLK_CK_OUTIN_R6 origin:058-pip-hclk 01_15 04_15
HCLK_R.HCLK_LEAF_CLK_B_BOT0.HCLK_CK_OUTIN_R7 origin:058-pip-hclk 01_15 03_15
HCLK_R.HCLK_LEAF_CLK_B_BOT1.HCLK_CK_BUFHCLK0 origin:058-pip-hclk 02_14 03_16
HCLK_R.HCLK_LEAF_CLK_B_BOT1.HCLK_CK_BUFHCLK1 origin:058-pip-hclk 03_16 05_14
HCLK_R.HCLK_LEAF_CLK_B_BOT1.HCLK_CK_BUFHCLK2 origin:058-pip-hclk 02_15 03_16
HCLK_R.HCLK_LEAF_CLK_B_BOT1.HCLK_CK_BUFHCLK3 origin:058-pip-hclk 03_16 05_15
HCLK_R.HCLK_LEAF_CLK_B_BOT1.HCLK_CK_BUFHCLK4 origin:058-pip-hclk 02_14 05_16
HCLK_R.HCLK_LEAF_CLK_B_BOT1.HCLK_CK_BUFHCLK5 origin:058-pip-hclk 05_14 05_16
HCLK_R.HCLK_LEAF_CLK_B_BOT1.HCLK_CK_BUFHCLK6 origin:058-pip-hclk 02_15 05_16
HCLK_R.HCLK_LEAF_CLK_B_BOT1.HCLK_CK_BUFHCLK7 origin:058-pip-hclk 05_15 05_16
HCLK_R.HCLK_LEAF_CLK_B_BOT1.HCLK_CK_OUTIN_R0 origin:058-pip-hclk 02_14 02_16
HCLK_R.HCLK_LEAF_CLK_B_BOT1.HCLK_CK_OUTIN_R1 origin:058-pip-hclk 02_16 05_14
HCLK_R.HCLK_LEAF_CLK_B_BOT1.HCLK_CK_OUTIN_R2 origin:058-pip-hclk 02_15 02_16
HCLK_R.HCLK_LEAF_CLK_B_BOT1.HCLK_CK_OUTIN_R3 origin:058-pip-hclk 02_16 05_15
HCLK_R.HCLK_LEAF_CLK_B_BOT1.HCLK_CK_OUTIN_R4 origin:058-pip-hclk 02_14 04_16
HCLK_R.HCLK_LEAF_CLK_B_BOT1.HCLK_CK_OUTIN_R5 origin:058-pip-hclk 04_16 05_14
HCLK_R.HCLK_LEAF_CLK_B_BOT1.HCLK_CK_OUTIN_R6 origin:058-pip-hclk 02_15 04_16
HCLK_R.HCLK_LEAF_CLK_B_BOT1.HCLK_CK_OUTIN_R7 origin:058-pip-hclk 04_16 05_15
HCLK_R.HCLK_LEAF_CLK_B_BOT2.HCLK_CK_BUFHCLK0 origin:058-pip-hclk 00_18 05_19
HCLK_R.HCLK_LEAF_CLK_B_BOT2.HCLK_CK_BUFHCLK1 origin:058-pip-hclk 00_18 02_19
HCLK_R.HCLK_LEAF_CLK_B_BOT2.HCLK_CK_BUFHCLK2 origin:058-pip-hclk 00_18 05_18
HCLK_R.HCLK_LEAF_CLK_B_BOT2.HCLK_CK_BUFHCLK3 origin:058-pip-hclk 00_18 02_18
HCLK_R.HCLK_LEAF_CLK_B_BOT2.HCLK_CK_BUFHCLK4 origin:058-pip-hclk 01_17 05_19
HCLK_R.HCLK_LEAF_CLK_B_BOT2.HCLK_CK_BUFHCLK5 origin:058-pip-hclk 01_17 02_19
HCLK_R.HCLK_LEAF_CLK_B_BOT2.HCLK_CK_BUFHCLK6 origin:058-pip-hclk 01_17 05_18
HCLK_R.HCLK_LEAF_CLK_B_BOT2.HCLK_CK_BUFHCLK7 origin:058-pip-hclk 01_17 02_18
HCLK_R.HCLK_LEAF_CLK_B_BOT2.HCLK_CK_OUTIN_R0 origin:058-pip-hclk 01_16 05_19
HCLK_R.HCLK_LEAF_CLK_B_BOT2.HCLK_CK_OUTIN_R1 origin:058-pip-hclk 01_16 02_19
HCLK_R.HCLK_LEAF_CLK_B_BOT2.HCLK_CK_OUTIN_R2 origin:058-pip-hclk 01_16 05_18
HCLK_R.HCLK_LEAF_CLK_B_BOT2.HCLK_CK_OUTIN_R3 origin:058-pip-hclk 01_16 02_18
HCLK_R.HCLK_LEAF_CLK_B_BOT2.HCLK_CK_OUTIN_R4 origin:058-pip-hclk 00_17 05_19
HCLK_R.HCLK_LEAF_CLK_B_BOT2.HCLK_CK_OUTIN_R5 origin:058-pip-hclk 00_17 02_19
HCLK_R.HCLK_LEAF_CLK_B_BOT2.HCLK_CK_OUTIN_R6 origin:058-pip-hclk 00_17 05_18
HCLK_R.HCLK_LEAF_CLK_B_BOT2.HCLK_CK_OUTIN_R7 origin:058-pip-hclk 00_17 02_18
HCLK_R.HCLK_LEAF_CLK_B_BOT3.HCLK_CK_BUFHCLK0 origin:058-pip-hclk 02_17 03_19
HCLK_R.HCLK_LEAF_CLK_B_BOT3.HCLK_CK_BUFHCLK1 origin:058-pip-hclk 02_17 04_19
HCLK_R.HCLK_LEAF_CLK_B_BOT3.HCLK_CK_BUFHCLK2 origin:058-pip-hclk 02_17 03_18
HCLK_R.HCLK_LEAF_CLK_B_BOT3.HCLK_CK_BUFHCLK3 origin:058-pip-hclk 02_17 04_18
HCLK_R.HCLK_LEAF_CLK_B_BOT3.HCLK_CK_BUFHCLK4 origin:058-pip-hclk 03_19 04_17
HCLK_R.HCLK_LEAF_CLK_B_BOT3.HCLK_CK_BUFHCLK5 origin:058-pip-hclk 04_17 04_19
HCLK_R.HCLK_LEAF_CLK_B_BOT3.HCLK_CK_BUFHCLK6 origin:058-pip-hclk 03_18 04_17
HCLK_R.HCLK_LEAF_CLK_B_BOT3.HCLK_CK_BUFHCLK7 origin:058-pip-hclk 04_17 04_18
HCLK_R.HCLK_LEAF_CLK_B_BOT3.HCLK_CK_OUTIN_R0 origin:058-pip-hclk 03_17 03_19
HCLK_R.HCLK_LEAF_CLK_B_BOT3.HCLK_CK_OUTIN_R1 origin:058-pip-hclk 03_17 04_19
HCLK_R.HCLK_LEAF_CLK_B_BOT3.HCLK_CK_OUTIN_R2 origin:058-pip-hclk 03_17 03_18
HCLK_R.HCLK_LEAF_CLK_B_BOT3.HCLK_CK_OUTIN_R3 origin:058-pip-hclk 03_17 04_18
HCLK_R.HCLK_LEAF_CLK_B_BOT3.HCLK_CK_OUTIN_R4 origin:058-pip-hclk 03_19 05_17
HCLK_R.HCLK_LEAF_CLK_B_BOT3.HCLK_CK_OUTIN_R5 origin:058-pip-hclk 04_19 05_17
HCLK_R.HCLK_LEAF_CLK_B_BOT3.HCLK_CK_OUTIN_R6 origin:058-pip-hclk 03_18 05_17
HCLK_R.HCLK_LEAF_CLK_B_BOT3.HCLK_CK_OUTIN_R7 origin:058-pip-hclk 04_18 05_17
HCLK_R.HCLK_LEAF_CLK_B_BOT4.HCLK_CK_BUFHCLK0 origin:058-pip-hclk 00_20 04_20
HCLK_R.HCLK_LEAF_CLK_B_BOT4.HCLK_CK_BUFHCLK1 origin:058-pip-hclk 00_20 03_20
HCLK_R.HCLK_LEAF_CLK_B_BOT4.HCLK_CK_BUFHCLK2 origin:058-pip-hclk 00_20 04_21
HCLK_R.HCLK_LEAF_CLK_B_BOT4.HCLK_CK_BUFHCLK3 origin:058-pip-hclk 00_20 03_21
HCLK_R.HCLK_LEAF_CLK_B_BOT4.HCLK_CK_BUFHCLK4 origin:058-pip-hclk 01_20 04_20
HCLK_R.HCLK_LEAF_CLK_B_BOT4.HCLK_CK_BUFHCLK5 origin:058-pip-hclk 01_20 03_20
HCLK_R.HCLK_LEAF_CLK_B_BOT4.HCLK_CK_BUFHCLK6 origin:058-pip-hclk 01_20 04_21
HCLK_R.HCLK_LEAF_CLK_B_BOT4.HCLK_CK_BUFHCLK7 origin:058-pip-hclk 01_20 03_21
HCLK_R.HCLK_LEAF_CLK_B_BOT4.HCLK_CK_OUTIN_R0 origin:058-pip-hclk 01_21 04_20
HCLK_R.HCLK_LEAF_CLK_B_BOT4.HCLK_CK_OUTIN_R1 origin:058-pip-hclk 01_21 03_20
HCLK_R.HCLK_LEAF_CLK_B_BOT4.HCLK_CK_OUTIN_R2 origin:058-pip-hclk 01_21 04_21
HCLK_R.HCLK_LEAF_CLK_B_BOT4.HCLK_CK_OUTIN_R3 origin:058-pip-hclk 01_21 03_21
HCLK_R.HCLK_LEAF_CLK_B_BOT4.HCLK_CK_OUTIN_R4 origin:058-pip-hclk 00_21 04_20
HCLK_R.HCLK_LEAF_CLK_B_BOT4.HCLK_CK_OUTIN_R5 origin:058-pip-hclk 00_21 03_20
HCLK_R.HCLK_LEAF_CLK_B_BOT4.HCLK_CK_OUTIN_R6 origin:058-pip-hclk 00_21 04_21
HCLK_R.HCLK_LEAF_CLK_B_BOT4.HCLK_CK_OUTIN_R7 origin:058-pip-hclk 00_21 03_21
HCLK_R.HCLK_LEAF_CLK_B_BOT5.HCLK_CK_BUFHCLK0 origin:058-pip-hclk 02_20 03_22
HCLK_R.HCLK_LEAF_CLK_B_BOT5.HCLK_CK_BUFHCLK1 origin:058-pip-hclk 03_22 05_20
HCLK_R.HCLK_LEAF_CLK_B_BOT5.HCLK_CK_BUFHCLK2 origin:058-pip-hclk 02_21 03_22
HCLK_R.HCLK_LEAF_CLK_B_BOT5.HCLK_CK_BUFHCLK3 origin:058-pip-hclk 03_22 05_21
HCLK_R.HCLK_LEAF_CLK_B_BOT5.HCLK_CK_BUFHCLK4 origin:058-pip-hclk 02_20 05_22
HCLK_R.HCLK_LEAF_CLK_B_BOT5.HCLK_CK_BUFHCLK5 origin:058-pip-hclk 05_20 05_22
HCLK_R.HCLK_LEAF_CLK_B_BOT5.HCLK_CK_BUFHCLK6 origin:058-pip-hclk 02_21 05_22
HCLK_R.HCLK_LEAF_CLK_B_BOT5.HCLK_CK_BUFHCLK7 origin:058-pip-hclk 05_21 05_22
HCLK_R.HCLK_LEAF_CLK_B_BOT5.HCLK_CK_OUTIN_R0 origin:058-pip-hclk 02_20 02_22
HCLK_R.HCLK_LEAF_CLK_B_BOT5.HCLK_CK_OUTIN_R1 origin:058-pip-hclk 02_22 05_20
HCLK_R.HCLK_LEAF_CLK_B_BOT5.HCLK_CK_OUTIN_R2 origin:058-pip-hclk 02_21 02_22
HCLK_R.HCLK_LEAF_CLK_B_BOT5.HCLK_CK_OUTIN_R3 origin:058-pip-hclk 02_22 05_21
HCLK_R.HCLK_LEAF_CLK_B_BOT5.HCLK_CK_OUTIN_R4 origin:058-pip-hclk 02_20 04_22
HCLK_R.HCLK_LEAF_CLK_B_BOT5.HCLK_CK_OUTIN_R5 origin:058-pip-hclk 04_22 05_20
HCLK_R.HCLK_LEAF_CLK_B_BOT5.HCLK_CK_OUTIN_R6 origin:058-pip-hclk 02_21 04_22
HCLK_R.HCLK_LEAF_CLK_B_BOT5.HCLK_CK_OUTIN_R7 origin:058-pip-hclk 04_22 05_21
HCLK_R.HCLK_LEAF_CLK_B_TOP0.HCLK_CK_BUFHCLK0 origin:058-pip-hclk 01_30 05_31
HCLK_R.HCLK_LEAF_CLK_B_TOP0.HCLK_CK_BUFHCLK1 origin:058-pip-hclk 01_30 02_31
HCLK_R.HCLK_LEAF_CLK_B_TOP0.HCLK_CK_BUFHCLK2 origin:058-pip-hclk 01_30 05_30
HCLK_R.HCLK_LEAF_CLK_B_TOP0.HCLK_CK_BUFHCLK3 origin:058-pip-hclk 01_30 02_30
HCLK_R.HCLK_LEAF_CLK_B_TOP0.HCLK_CK_BUFHCLK4 origin:058-pip-hclk 00_30 05_31
HCLK_R.HCLK_LEAF_CLK_B_TOP0.HCLK_CK_BUFHCLK5 origin:058-pip-hclk 00_30 02_31
HCLK_R.HCLK_LEAF_CLK_B_TOP0.HCLK_CK_BUFHCLK6 origin:058-pip-hclk 00_30 05_30
HCLK_R.HCLK_LEAF_CLK_B_TOP0.HCLK_CK_BUFHCLK7 origin:058-pip-hclk 00_30 02_30
HCLK_R.HCLK_LEAF_CLK_B_TOP0.HCLK_CK_OUTIN_R0 origin:058-pip-hclk 00_29 05_31
HCLK_R.HCLK_LEAF_CLK_B_TOP0.HCLK_CK_OUTIN_R1 origin:058-pip-hclk 00_29 02_31
HCLK_R.HCLK_LEAF_CLK_B_TOP0.HCLK_CK_OUTIN_R2 origin:058-pip-hclk 00_29 05_30
HCLK_R.HCLK_LEAF_CLK_B_TOP0.HCLK_CK_OUTIN_R3 origin:058-pip-hclk 00_29 02_30
HCLK_R.HCLK_LEAF_CLK_B_TOP0.HCLK_CK_OUTIN_R4 origin:058-pip-hclk 01_29 05_31
HCLK_R.HCLK_LEAF_CLK_B_TOP0.HCLK_CK_OUTIN_R5 origin:058-pip-hclk 01_29 02_31
HCLK_R.HCLK_LEAF_CLK_B_TOP0.HCLK_CK_OUTIN_R6 origin:058-pip-hclk 01_29 05_30
HCLK_R.HCLK_LEAF_CLK_B_TOP0.HCLK_CK_OUTIN_R7 origin:058-pip-hclk 01_29 02_30
HCLK_R.HCLK_LEAF_CLK_B_TOP1.HCLK_CK_BUFHCLK0 origin:058-pip-hclk 02_29 03_31
HCLK_R.HCLK_LEAF_CLK_B_TOP1.HCLK_CK_BUFHCLK1 origin:058-pip-hclk 02_29 04_31
HCLK_R.HCLK_LEAF_CLK_B_TOP1.HCLK_CK_BUFHCLK2 origin:058-pip-hclk 02_29 03_30
HCLK_R.HCLK_LEAF_CLK_B_TOP1.HCLK_CK_BUFHCLK3 origin:058-pip-hclk 02_29 04_30
HCLK_R.HCLK_LEAF_CLK_B_TOP1.HCLK_CK_BUFHCLK4 origin:058-pip-hclk 03_31 04_29
HCLK_R.HCLK_LEAF_CLK_B_TOP1.HCLK_CK_BUFHCLK5 origin:058-pip-hclk 04_29 04_31
HCLK_R.HCLK_LEAF_CLK_B_TOP1.HCLK_CK_BUFHCLK6 origin:058-pip-hclk 03_30 04_29
HCLK_R.HCLK_LEAF_CLK_B_TOP1.HCLK_CK_BUFHCLK7 origin:058-pip-hclk 04_29 04_30
HCLK_R.HCLK_LEAF_CLK_B_TOP1.HCLK_CK_OUTIN_R0 origin:058-pip-hclk 03_29 03_31
HCLK_R.HCLK_LEAF_CLK_B_TOP1.HCLK_CK_OUTIN_R1 origin:058-pip-hclk 03_29 04_31
HCLK_R.HCLK_LEAF_CLK_B_TOP1.HCLK_CK_OUTIN_R2 origin:058-pip-hclk 03_29 03_30
HCLK_R.HCLK_LEAF_CLK_B_TOP1.HCLK_CK_OUTIN_R3 origin:058-pip-hclk 03_29 04_30
HCLK_R.HCLK_LEAF_CLK_B_TOP1.HCLK_CK_OUTIN_R4 origin:058-pip-hclk 03_31 05_29
HCLK_R.HCLK_LEAF_CLK_B_TOP1.HCLK_CK_OUTIN_R5 origin:058-pip-hclk 04_31 05_29
HCLK_R.HCLK_LEAF_CLK_B_TOP1.HCLK_CK_OUTIN_R6 origin:058-pip-hclk 03_30 05_29
HCLK_R.HCLK_LEAF_CLK_B_TOP1.HCLK_CK_OUTIN_R7 origin:058-pip-hclk 04_30 05_29
HCLK_R.HCLK_LEAF_CLK_B_TOP2.HCLK_CK_BUFHCLK0 origin:058-pip-hclk 00_26 04_26
HCLK_R.HCLK_LEAF_CLK_B_TOP2.HCLK_CK_BUFHCLK1 origin:058-pip-hclk 00_26 03_26
HCLK_R.HCLK_LEAF_CLK_B_TOP2.HCLK_CK_BUFHCLK2 origin:058-pip-hclk 00_26 04_27
HCLK_R.HCLK_LEAF_CLK_B_TOP2.HCLK_CK_BUFHCLK3 origin:058-pip-hclk 00_26 03_27
HCLK_R.HCLK_LEAF_CLK_B_TOP2.HCLK_CK_BUFHCLK4 origin:058-pip-hclk 01_26 04_26
HCLK_R.HCLK_LEAF_CLK_B_TOP2.HCLK_CK_BUFHCLK5 origin:058-pip-hclk 01_26 03_26
HCLK_R.HCLK_LEAF_CLK_B_TOP2.HCLK_CK_BUFHCLK6 origin:058-pip-hclk 01_26 04_27
HCLK_R.HCLK_LEAF_CLK_B_TOP2.HCLK_CK_BUFHCLK7 origin:058-pip-hclk 01_26 03_27
HCLK_R.HCLK_LEAF_CLK_B_TOP2.HCLK_CK_OUTIN_R0 origin:058-pip-hclk 01_28 04_26
HCLK_R.HCLK_LEAF_CLK_B_TOP2.HCLK_CK_OUTIN_R1 origin:058-pip-hclk 01_28 03_26
HCLK_R.HCLK_LEAF_CLK_B_TOP2.HCLK_CK_OUTIN_R2 origin:058-pip-hclk 01_28 04_27
HCLK_R.HCLK_LEAF_CLK_B_TOP2.HCLK_CK_OUTIN_R3 origin:058-pip-hclk 01_28 03_27
HCLK_R.HCLK_LEAF_CLK_B_TOP2.HCLK_CK_OUTIN_R4 origin:058-pip-hclk 00_28 04_26
HCLK_R.HCLK_LEAF_CLK_B_TOP2.HCLK_CK_OUTIN_R5 origin:058-pip-hclk 00_28 03_26
HCLK_R.HCLK_LEAF_CLK_B_TOP2.HCLK_CK_OUTIN_R6 origin:058-pip-hclk 00_28 04_27
HCLK_R.HCLK_LEAF_CLK_B_TOP2.HCLK_CK_OUTIN_R7 origin:058-pip-hclk 00_28 03_27
HCLK_R.HCLK_LEAF_CLK_B_TOP3.HCLK_CK_BUFHCLK0 origin:058-pip-hclk 02_26 03_28
HCLK_R.HCLK_LEAF_CLK_B_TOP3.HCLK_CK_BUFHCLK1 origin:058-pip-hclk 03_28 05_26
HCLK_R.HCLK_LEAF_CLK_B_TOP3.HCLK_CK_BUFHCLK2 origin:058-pip-hclk 02_27 03_28
HCLK_R.HCLK_LEAF_CLK_B_TOP3.HCLK_CK_BUFHCLK3 origin:058-pip-hclk 03_28 05_27
HCLK_R.HCLK_LEAF_CLK_B_TOP3.HCLK_CK_BUFHCLK4 origin:058-pip-hclk 02_26 05_28
HCLK_R.HCLK_LEAF_CLK_B_TOP3.HCLK_CK_BUFHCLK5 origin:058-pip-hclk 05_26 05_28
HCLK_R.HCLK_LEAF_CLK_B_TOP3.HCLK_CK_BUFHCLK6 origin:058-pip-hclk 02_27 05_28
HCLK_R.HCLK_LEAF_CLK_B_TOP3.HCLK_CK_BUFHCLK7 origin:058-pip-hclk 05_27 05_28
HCLK_R.HCLK_LEAF_CLK_B_TOP3.HCLK_CK_OUTIN_R0 origin:058-pip-hclk 02_26 02_28
HCLK_R.HCLK_LEAF_CLK_B_TOP3.HCLK_CK_OUTIN_R1 origin:058-pip-hclk 02_28 05_26
HCLK_R.HCLK_LEAF_CLK_B_TOP3.HCLK_CK_OUTIN_R2 origin:058-pip-hclk 02_27 02_28
HCLK_R.HCLK_LEAF_CLK_B_TOP3.HCLK_CK_OUTIN_R3 origin:058-pip-hclk 02_28 05_27
HCLK_R.HCLK_LEAF_CLK_B_TOP3.HCLK_CK_OUTIN_R4 origin:058-pip-hclk 02_26 04_28
HCLK_R.HCLK_LEAF_CLK_B_TOP3.HCLK_CK_OUTIN_R5 origin:058-pip-hclk 04_28 05_26
HCLK_R.HCLK_LEAF_CLK_B_TOP3.HCLK_CK_OUTIN_R6 origin:058-pip-hclk 02_27 04_28
HCLK_R.HCLK_LEAF_CLK_B_TOP3.HCLK_CK_OUTIN_R7 origin:058-pip-hclk 04_28 05_27
HCLK_R.HCLK_LEAF_CLK_B_TOP4.HCLK_CK_BUFHCLK0 origin:058-pip-hclk 01_25 05_25
HCLK_R.HCLK_LEAF_CLK_B_TOP4.HCLK_CK_BUFHCLK1 origin:058-pip-hclk 01_25 02_25
HCLK_R.HCLK_LEAF_CLK_B_TOP4.HCLK_CK_BUFHCLK2 origin:058-pip-hclk 01_25 05_24
HCLK_R.HCLK_LEAF_CLK_B_TOP4.HCLK_CK_BUFHCLK3 origin:058-pip-hclk 01_25 02_24
HCLK_R.HCLK_LEAF_CLK_B_TOP4.HCLK_CK_BUFHCLK4 origin:058-pip-hclk 00_25 05_25
HCLK_R.HCLK_LEAF_CLK_B_TOP4.HCLK_CK_BUFHCLK5 origin:058-pip-hclk 00_25 02_25
HCLK_R.HCLK_LEAF_CLK_B_TOP4.HCLK_CK_BUFHCLK6 origin:058-pip-hclk 00_25 05_24
HCLK_R.HCLK_LEAF_CLK_B_TOP4.HCLK_CK_BUFHCLK7 origin:058-pip-hclk 00_25 02_24
HCLK_R.HCLK_LEAF_CLK_B_TOP4.HCLK_CK_OUTIN_R0 origin:058-pip-hclk 00_24 05_25
HCLK_R.HCLK_LEAF_CLK_B_TOP4.HCLK_CK_OUTIN_R1 origin:058-pip-hclk 00_24 02_25
HCLK_R.HCLK_LEAF_CLK_B_TOP4.HCLK_CK_OUTIN_R2 origin:058-pip-hclk 00_24 05_24
HCLK_R.HCLK_LEAF_CLK_B_TOP4.HCLK_CK_OUTIN_R3 origin:058-pip-hclk 00_24 02_24
HCLK_R.HCLK_LEAF_CLK_B_TOP4.HCLK_CK_OUTIN_R4 origin:058-pip-hclk 01_24 05_25
HCLK_R.HCLK_LEAF_CLK_B_TOP4.HCLK_CK_OUTIN_R5 origin:058-pip-hclk 01_24 02_25
HCLK_R.HCLK_LEAF_CLK_B_TOP4.HCLK_CK_OUTIN_R6 origin:058-pip-hclk 01_24 05_24
HCLK_R.HCLK_LEAF_CLK_B_TOP4.HCLK_CK_OUTIN_R7 origin:058-pip-hclk 01_24 02_24
HCLK_R.HCLK_LEAF_CLK_B_TOP5.HCLK_CK_BUFHCLK0 origin:058-pip-hclk 02_23 03_25
HCLK_R.HCLK_LEAF_CLK_B_TOP5.HCLK_CK_BUFHCLK1 origin:058-pip-hclk 02_23 04_25
HCLK_R.HCLK_LEAF_CLK_B_TOP5.HCLK_CK_BUFHCLK2 origin:058-pip-hclk 02_23 03_24
HCLK_R.HCLK_LEAF_CLK_B_TOP5.HCLK_CK_BUFHCLK3 origin:058-pip-hclk 02_23 04_24
HCLK_R.HCLK_LEAF_CLK_B_TOP5.HCLK_CK_BUFHCLK4 origin:058-pip-hclk 03_25 04_23
HCLK_R.HCLK_LEAF_CLK_B_TOP5.HCLK_CK_BUFHCLK5 origin:058-pip-hclk 04_23 04_25
HCLK_R.HCLK_LEAF_CLK_B_TOP5.HCLK_CK_BUFHCLK6 origin:058-pip-hclk 03_24 04_23
HCLK_R.HCLK_LEAF_CLK_B_TOP5.HCLK_CK_BUFHCLK7 origin:058-pip-hclk 04_23 04_24
HCLK_R.HCLK_LEAF_CLK_B_TOP5.HCLK_CK_OUTIN_R0 origin:058-pip-hclk 03_23 03_25
HCLK_R.HCLK_LEAF_CLK_B_TOP5.HCLK_CK_OUTIN_R1 origin:058-pip-hclk 03_23 04_25
HCLK_R.HCLK_LEAF_CLK_B_TOP5.HCLK_CK_OUTIN_R2 origin:058-pip-hclk 03_23 03_24
HCLK_R.HCLK_LEAF_CLK_B_TOP5.HCLK_CK_OUTIN_R3 origin:058-pip-hclk 03_23 04_24
HCLK_R.HCLK_LEAF_CLK_B_TOP5.HCLK_CK_OUTIN_R4 origin:058-pip-hclk 03_25 05_23
HCLK_R.HCLK_LEAF_CLK_B_TOP5.HCLK_CK_OUTIN_R5 origin:058-pip-hclk 04_25 05_23
HCLK_R.HCLK_LEAF_CLK_B_TOP5.HCLK_CK_OUTIN_R6 origin:058-pip-hclk 03_24 05_23
HCLK_R.HCLK_LEAF_CLK_B_TOP5.HCLK_CK_OUTIN_R7 origin:058-pip-hclk 04_24 05_23

14
zynq7/segbits_int_l.db
View File

@ -1638,18 +1638,24 @@ INT_L.IMUX_L47.SS2END3 17_62 !22_62 !23_62 !24_62 25_62
INT_L.IMUX_L47.SW2END3 17_62 !22_62 !23_62 24_62 !25_62
INT_L.IMUX_L47.WL1END3 18_63 !22_62 23_62 24_62 25_62
INT_L.IMUX_L47.WW2END3 16_62 !22_62 !23_62 !24_62 25_62
INT_L.LV_L0.LV_L18 00_09 01_06
INT_L.LV_L0.SR1BEG_S0 00_05 01_05
INT_L.LV_L0.ER1END0 01_04 01_05
INT_L.LV_L0.LH0 00_02 01_06
INT_L.LV_L0.LH6 01_04 01_06
INT_L.LV_L0.LH12 00_05 01_06
INT_L.LV_L0.NN6END0 00_07 00_09
INT_L.LV_L0.NR1END0 00_02 01_05
INT_L.LV_L0.NW6END0 00_07 01_04
INT_L.LV_L0.SW6END0 00_09 01_05
INT_L.LV_L0.WR1END0 00_02 00_07
INT_L.LV_L0.WW4END0 00_05 00_07
INT_L.LV_L18.LV_L0 01_00 01_01
INT_L.LV_L18.SR1BEG_S0 00_03 01_08
INT_L.LV_L18.ER1END0 00_03 00_06
INT_L.LV_L18.LH0 00_01 01_02
INT_L.LV_L18.LH6 00_06 01_02
INT_L.LV_L18.LH12 01_02 01_08
INT_L.LV_L18.NN6END0 00_03 01_00
INT_L.LV_L18.NR1END0 00_01 00_03
INT_L.LV_L18.NW6END0 00_06 01_01
@ -1658,6 +1664,7 @@ INT_L.LV_L18.WR1END0 00_01 01_01
INT_L.LV_L18.WW4END0 01_01 01_08
INT_L.LVB_L0.LV_L0 00_47 01_52
INT_L.LVB_L0.LV_L18 01_42 01_52
INT_L.LVB_L0.LVB_L12 00_51 00_54
INT_L.LVB_L0.LH0 00_43 00_51
INT_L.LVB_L0.LH6 00_51 00_53
INT_L.LVB_L0.LH12 00_50 00_51
@ -1675,6 +1682,7 @@ INT_L.LVB_L0.WR1END3 01_42 01_50
INT_L.LVB_L0.WW4END3 00_53 01_50
INT_L.LVB_L12.LV_L0 00_45 01_44
INT_L.LVB_L12.LV_L18 00_45 01_48
INT_L.LVB_L12.LVB_L0 00_45 01_45
INT_L.LVB_L12.LH0 00_46 00_49
INT_L.LVB_L12.LH6 00_46 01_49
INT_L.LVB_L12.LH12 00_46 01_53
@ -2082,18 +2090,24 @@ INT_L.GFAN1.GCLK_L_B11_WEST !00_14 !00_18 !00_19 01_13 01_17
INT_L.GFAN1.GND_WIRE !00_14 00_17 !00_18 !00_19 01_13
INT_L.GFAN1.NR1END1 00_14 00_17 !00_18 00_19 01_13
INT_L.GFAN1.WW4END1 00_14 00_17 !00_18 !00_19 !01_13
INT_L.LH0.LV_L0 01_56 01_58
INT_L.LH0.LV_L9 00_59 01_56
INT_L.LH0.LV_L18 01_56 01_61
INT_L.LH0.EE4END3 00_58 01_61
INT_L.LH0.ER1END3 00_57 01_54
INT_L.LH0.LH12 01_54 01_56
INT_L.LH0.NE2END3 00_58 00_59
INT_L.LH0.NE6END3 00_58 01_58
INT_L.LH0.NW2END3 00_58 01_54
INT_L.LH0.SR1END3 00_57 00_59
INT_L.LH0.SS6END3 00_57 01_58
INT_L.LH0.SW6END3 00_57 01_61
INT_L.LH12.LV_L0 00_55 00_62
INT_L.LH12.LV_L9 00_62 01_57
INT_L.LH12.LV_L18 00_62 01_62
INT_L.LH12.EE4END3 01_60 01_62
INT_L.LH12.ER1END3 00_63 01_60
INT_L.LH12.LH0 00_61 00_63
INT_L.LH12.NE2END3 01_57 01_60
INT_L.LH12.NE6END3 00_55 01_60
INT_L.LH12.NW2END3 00_62 00_63

3636
zynq7/segbits_int_l.origin_info.db Normal file
View File

File diff suppressed because it is too large Load Diff

14
zynq7/segbits_int_r.db
View File

@ -2032,7 +2032,10 @@ INT_R.IMUX47.WL1END3 18_63 !22_62 23_62 24_62 25_62
INT_R.IMUX47.WW2END3 16_62 !22_62 !23_62 !24_62 25_62
INT_R.LH0.EE4END3 00_58 01_61
INT_R.LH0.ER1END3 00_57 01_54
INT_R.LH0.LH12 01_54 01_56
INT_R.LH0.LV0 01_56 01_58
INT_R.LH0.LV9 00_59 01_56
INT_R.LH0.LV18 01_56 01_61
INT_R.LH0.NE2END3 00_58 00_59
INT_R.LH0.NE6END3 00_58 01_58
INT_R.LH0.NW2END3 00_58 01_54
@ -2041,7 +2044,10 @@ INT_R.LH0.SS6END3 00_57 01_58
INT_R.LH0.SW6END3 00_57 01_61
INT_R.LH12.EE4END3 01_60 01_62
INT_R.LH12.ER1END3 00_63 01_60
INT_R.LH12.LH0 00_61 00_63
INT_R.LH12.LV0 00_55 00_62
INT_R.LH12.LV9 00_62 01_57
INT_R.LH12.LV18 00_62 01_62
INT_R.LH12.NE2END3 01_57 01_60
INT_R.LH12.NE6END3 00_55 01_60
INT_R.LH12.NW2END3 00_62 00_63
@ -2050,7 +2056,10 @@ INT_R.LH12.SS6END3 00_55 00_61
INT_R.LH12.SW6END3 00_61 01_62
INT_R.LV0.SR1BEG_S0 00_05 01_05
INT_R.LV0.ER1END0 01_04 01_05
INT_R.LV0.LH0 00_02 01_06
INT_R.LV0.LH6 01_04 01_06
INT_R.LV0.LH12 00_05 01_06
INT_R.LV0.LV18 00_09 01_06
INT_R.LV0.NN6END0 00_07 00_09
INT_R.LV0.NR1END0 00_02 01_05
INT_R.LV0.NW6END0 00_07 01_04
@ -2059,7 +2068,10 @@ INT_R.LV0.WR1END0 00_02 00_07
INT_R.LV0.WW4END0 00_05 00_07
INT_R.LV18.SR1BEG_S0 00_03 01_08
INT_R.LV18.ER1END0 00_03 00_06
INT_R.LV18.LH0 00_01 01_02
INT_R.LV18.LH6 00_06 01_02
INT_R.LV18.LH12 01_02 01_08
INT_R.LV18.LV0 01_00 01_01
INT_R.LV18.NN6END0 00_03 01_00
INT_R.LV18.NR1END0 00_01 00_03
INT_R.LV18.NW6END0 00_06 01_01
@ -2071,6 +2083,7 @@ INT_R.LVB0.LH6 00_51 00_53
INT_R.LVB0.LH12 00_50 00_51
INT_R.LVB0.LV0 00_47 01_52
INT_R.LVB0.LV18 01_42 01_52
INT_R.LVB0.LVB12 00_51 00_54
INT_R.LVB0.NE2END2 00_53 01_52
INT_R.LVB0.NN6END3 00_50 01_50
INT_R.LVB0.NR1END3 00_47 01_50
@ -2088,6 +2101,7 @@ INT_R.LVB12.LH6 00_46 01_49
INT_R.LVB12.LH12 00_46 01_53
INT_R.LVB12.LV0 00_45 01_44
INT_R.LVB12.LV18 00_45 01_48
INT_R.LVB12.LVB0 00_45 01_45
INT_R.LVB12.NE2END2 00_45 01_49
INT_R.LVB12.NN6END3 01_46 01_53
INT_R.LVB12.NR1END3 01_44 01_46

3636
zynq7/segbits_int_r.origin_info.db Normal file
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File diff suppressed because it is too large Load Diff

66
zynq7/segbits_liob33.origin_info.db Normal file
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@ -0,0 +1,66 @@
LIOB33.IOB_Y0.IDELMUXE3.0 origin:035-iob-ilogic 29_101
LIOB33.IOB_Y0.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE origin:035-iob-ilogic 27_98
LIOB33.IOB_Y0.IFF.DDR_CLK_EDGE.SAME_EDGE origin:035-iob-ilogic 26_99
LIOB33.IOB_Y0.IFF.SRTYPE.SYNC origin:035-iob-ilogic 29_67
LIOB33.IOB_Y0.IFF.ZINIT_Q1 origin:035-iob-ilogic 28_72
LIOB33.IOB_Y0.IFF.ZINIT_Q2 origin:035-iob-ilogic 28_76
LIOB33.IOB_Y0.IFF.ZINIT_Q3 origin:035-iob-ilogic 28_86
LIOB33.IOB_Y0.IFF.ZINIT_Q4 origin:035-iob-ilogic 28_94
LIOB33.IOB_Y0.IFF.ZINV_C origin:035-iob-ilogic 28_126 29_123 29_125
LIOB33.IOB_Y0.IFF.ZINV_OCLK origin:035-iob-ilogic 28_64
LIOB33.IOB_Y0.IFF.ZSRVAL_Q1 origin:035-iob-ilogic 29_71
LIOB33.IOB_Y0.IFF.ZSRVAL_Q2 origin:035-iob-ilogic 29_75
LIOB33.IOB_Y0.IFF.ZSRVAL_Q3 origin:035-iob-ilogic 29_85
LIOB33.IOB_Y0.IFF.ZSRVAL_Q4 origin:035-iob-ilogic 29_93
LIOB33.IOB_Y0.IFFDELMUXE3.0 origin:035-iob-ilogic 28_116
LIOB33.IOB_Y0.ISERDES.DATA_RATE.SDR origin:035-iob-ilogic 27_108
LIOB33.IOB_Y0.ISERDES.INTERFACE_TYPE.MEMORY_DDR3 origin:035-iob-ilogic 26_117
LIOB33.IOB_Y0.ISERDES.INTERFACE_TYPE.OVERSAMPLE origin:035-iob-ilogic 26_115
LIOB33.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE origin:036-iob-ologic !31_92
LIOB33.IOB_Y0.ODDR.DDR_CLK_EDGE.SAME_EDGE origin:036-iob-ologic 31_92
LIOB33.IOB_Y0.OFF.ZINIT_Q origin:036-iob-ologic 33_97
LIOB33.IOB_Y0.OSERDESE.DATA_RATE_TQ.BUF origin:036-iob-ologic 32_66
LIOB33.IOB_Y0.OSERDESE.DATA_RATE_TQ.DDR origin:036-iob-ologic 32_70
LIOB33.IOB_Y0.OSERDESE.DATA_RATE_TQ.SDR origin:036-iob-ologic 33_69
LIOB33.IOB_Y0.OSERDESE.DATA_WIDTH.2 origin:036-iob-ologic 30_127
LIOB33.IOB_Y0.OSERDESE.DATA_WIDTH.3 origin:036-iob-ologic 31_126
LIOB33.IOB_Y0.OSERDESE.DATA_WIDTH.4 origin:036-iob-ologic 31_124
LIOB33.IOB_Y0.OSERDESE.DATA_WIDTH.5 origin:036-iob-ologic 30_121
LIOB33.IOB_Y0.OSERDESE.DATA_WIDTH.6 origin:036-iob-ologic 31_120
LIOB33.IOB_Y0.OSERDESE.DATA_WIDTH.7 origin:036-iob-ologic 30_123
LIOB33.IOB_Y0.OSERDESE.DATA_WIDTH.8 origin:036-iob-ologic 31_116
LIOB33.IOB_Y0.TFF.ZINIT_Q origin:036-iob-ologic 30_75
LIOB33.IOB_Y0.ZINV_D origin:035-iob-ilogic 29_109
LIOB33.IOB_Y1.IDELMUXE3.0 origin:035-iob-ilogic 28_26
LIOB33.IOB_Y1.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE origin:035-iob-ilogic 26_29
LIOB33.IOB_Y1.IFF.DDR_CLK_EDGE.SAME_EDGE origin:035-iob-ilogic 27_28
LIOB33.IOB_Y1.IFF.SRTYPE.SYNC origin:035-iob-ilogic 28_60
LIOB33.IOB_Y1.IFF.ZINIT_Q1 origin:035-iob-ilogic 29_55
LIOB33.IOB_Y1.IFF.ZINIT_Q2 origin:035-iob-ilogic 29_51
LIOB33.IOB_Y1.IFF.ZINIT_Q3 origin:035-iob-ilogic 29_41
LIOB33.IOB_Y1.IFF.ZINIT_Q4 origin:035-iob-ilogic 29_33
LIOB33.IOB_Y1.IFF.ZINV_C origin:035-iob-ilogic 28_02 28_04 29_01
LIOB33.IOB_Y1.IFF.ZINV_OCLK origin:035-iob-ilogic 29_63
LIOB33.IOB_Y1.IFF.ZSRVAL_Q1 origin:035-iob-ilogic 28_56
LIOB33.IOB_Y1.IFF.ZSRVAL_Q2 origin:035-iob-ilogic 28_52
LIOB33.IOB_Y1.IFF.ZSRVAL_Q3 origin:035-iob-ilogic 28_42
LIOB33.IOB_Y1.IFF.ZSRVAL_Q4 origin:035-iob-ilogic 28_34
LIOB33.IOB_Y1.IFFDELMUXE3.0 origin:035-iob-ilogic 29_11
LIOB33.IOB_Y1.ISERDES.DATA_RATE.SDR origin:035-iob-ilogic 26_19
LIOB33.IOB_Y1.ISERDES.INTERFACE_TYPE.MEMORY_DDR3 origin:035-iob-ilogic 27_10
LIOB33.IOB_Y1.ISERDES.INTERFACE_TYPE.OVERSAMPLE origin:035-iob-ilogic 27_12
LIOB33.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE origin:036-iob-ologic !30_35
LIOB33.IOB_Y1.ODDR.DDR_CLK_EDGE.SAME_EDGE origin:036-iob-ologic 30_35
LIOB33.IOB_Y1.OFF.ZINIT_Q origin:036-iob-ologic 32_30
LIOB33.IOB_Y1.OSERDESE.DATA_RATE_TQ.BUF origin:036-iob-ologic 33_61
LIOB33.IOB_Y1.OSERDESE.DATA_RATE_TQ.DDR origin:036-iob-ologic 33_57
LIOB33.IOB_Y1.OSERDESE.DATA_RATE_TQ.SDR origin:036-iob-ologic 32_58
LIOB33.IOB_Y1.OSERDESE.DATA_WIDTH.2 origin:036-iob-ologic 31_00
LIOB33.IOB_Y1.OSERDESE.DATA_WIDTH.3 origin:036-iob-ologic 30_01
LIOB33.IOB_Y1.OSERDESE.DATA_WIDTH.4 origin:036-iob-ologic 30_03
LIOB33.IOB_Y1.OSERDESE.DATA_WIDTH.5 origin:036-iob-ologic 31_06
LIOB33.IOB_Y1.OSERDESE.DATA_WIDTH.6 origin:036-iob-ologic 30_07
LIOB33.IOB_Y1.OSERDESE.DATA_WIDTH.7 origin:036-iob-ologic 31_04
LIOB33.IOB_Y1.OSERDESE.DATA_WIDTH.8 origin:036-iob-ologic 30_11
LIOB33.IOB_Y1.TFF.ZINIT_Q origin:036-iob-ologic 31_52
LIOB33.IOB_Y1.ZINV_D origin:035-iob-ilogic 28_18

40
zynq7/segbits_riob33.db
View File

@ -76,13 +76,13 @@ RIOB33.IOB_Y1.IFF.ZSRVAL_Q1 28_56
RIOB33.IOB_Y1.IFF.ZSRVAL_Q2 28_52
RIOB33.IOB_Y1.IFF.ZSRVAL_Q3 28_42
RIOB33.IOB_Y1.IFF.ZSRVAL_Q4 28_34
RIOB33.IOB_Y1.IN_ONLY 38_02 38_08 39_09
RIOB33.IOB_Y1.IN_ONLY 38_02 38_08 38_14 38_40 38_42 39_09 39_41
RIOB33.IOB_Y1.INOUT 31_60
RIOB33.IOB_Y1.INTERMDISABLE.I 38_38
RIOB33.IOB_Y1.ISERDES.DATA_RATE.SDR 26_19
RIOB33.IOB_Y1.ISERDES.INTERFACE_TYPE.MEMORY_DDR3 27_10
RIOB33.IOB_Y1.ISERDES.INTERFACE_TYPE.OVERSAMPLE 27_12
RIOB33.IOB_Y1.LVTTL.DRIVE.I24 30_41 32_16 33_61 !38_00 !38_02 38_08 38_10 !38_14 !38_32 38_62 39_01 !39_09 !39_15 39_63
RIOB33.IOB_Y1.LVTTL.DRIVE.I24 30_41 32_16 33_61 !38_00 !38_02 38_08 38_10 !38_14 !38_32 !38_40 !38_42 38_62 39_01 !39_09 !39_15 !39_41 39_63
RIOB33.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE !30_35
RIOB33.IOB_Y1.ODDR.DDR_CLK_EDGE.SAME_EDGE 30_35
RIOB33.IOB_Y1.OFF.ZINIT_Q 32_30
@ -106,23 +106,23 @@ RIOB33.IOB_Y1.TFF.ZINIT_Q 31_52
RIOB33.IOB_Y1.ZINV_D 28_18
RIOB33.IOB_Y1.IDELMUXE3.0 28_26
RIOB33.IOB_Y1.IFFDELMUXE3.0 29_11
RIOB33.IOB_Y1.LVCMOS12.DRIVE.I4 30_41 32_16 33_61 !38_00 38_02 !38_08 !38_10 38_14 38_32 38_62 39_01 39_09 39_15 39_63
RIOB33.IOB_Y1.LVCMOS12.DRIVE.I8 30_41 32_16 33_61 !38_00 !38_02 38_08 !38_10 38_14 38_32 38_62 !39_01 !39_09 39_15 39_63
RIOB33.IOB_Y1.LVCMOS12.DRIVE.I12 30_41 32_16 33_61 38_00 !38_02 !38_08 !38_10 38_14 38_32 38_62 39_01 !39_09 39_15 39_63
RIOB33.IOB_Y1.LVCMOS12.DRIVE.I4 30_41 32_16 33_61 !38_00 38_02 !38_08 !38_10 38_14 38_32 !38_40 !38_42 38_62 39_01 39_09 39_15 !39_41 39_63
RIOB33.IOB_Y1.LVCMOS12.DRIVE.I8 30_41 32_16 33_61 !38_00 !38_02 38_08 !38_10 38_14 38_32 !38_40 !38_42 38_62 !39_01 !39_09 39_15 !39_41 39_63
RIOB33.IOB_Y1.LVCMOS12.DRIVE.I12 30_41 32_16 33_61 38_00 !38_02 !38_08 !38_10 38_14 38_32 !38_40 !38_42 38_62 39_01 !39_09 39_15 !39_41 39_63
RIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18.IN 38_14 !38_40 38_42 39_41
RIOB33.IOB_Y1.LVCMOS15.DRIVE.I8 30_41 32_16 33_61 38_00 38_02 38_08 !38_10 38_14 38_32 38_62 39_01 !39_09 39_15 39_63
RIOB33.IOB_Y1.LVCMOS15.DRIVE.I12 30_41 32_16 33_61 38_00 !38_02 !38_08 !38_10 38_14 38_32 38_62 !39_01 !39_09 39_15 39_63
RIOB33.IOB_Y1.LVCMOS15.DRIVE.I16 30_41 32_16 33_61 38_00 !38_02 !38_08 38_10 38_14 38_32 38_62 39_01 39_09 39_15 39_63
RIOB33.IOB_Y1.LVCMOS15_LVCMOS18.DRIVE.I4 30_41 32_16 33_61 38_00 38_02 !38_08 !38_10 38_14 38_32 38_62 !39_01 39_09 39_15 39_63
RIOB33.IOB_Y1.LVCMOS18.DRIVE.I12_I8 30_41 32_16 33_61 !38_00 38_02 38_08 !38_10 38_14 38_32 38_62 39_01 !39_09 39_15 39_63
RIOB33.IOB_Y1.LVCMOS18.DRIVE.I16 30_41 32_16 33_61 38_00 38_02 !38_08 !38_10 38_14 38_32 38_62 39_01 !39_09 39_15 39_63
RIOB33.IOB_Y1.LVCMOS18.DRIVE.I24 30_41 32_16 33_61 !38_00 !38_02 38_08 38_10 38_14 38_32 38_62 39_01 !39_09 39_15 39_63
RIOB33.IOB_Y1.LVCMOS25.DRIVE.I4 30_41 32_16 33_61 38_00 38_02 !38_08 !38_10 38_14 !38_32 38_62 !39_01 39_09 39_15 39_63
RIOB33.IOB_Y1.LVCMOS25.DRIVE.I8 30_41 32_16 33_61 !38_00 !38_02 38_08 !38_10 38_14 !38_32 38_62 !39_01 !39_09 39_15 39_63
RIOB33.IOB_Y1.LVCMOS25.DRIVE.I12 30_41 32_16 33_61 !38_00 !38_02 !38_08 !38_10 38_14 !38_32 38_62 !39_01 !39_09 39_15 39_63
RIOB33.IOB_Y1.LVCMOS25.DRIVE.I16 30_41 32_16 33_61 !38_00 !38_02 !38_08 38_10 38_14 !38_32 38_62 39_01 39_09 39_15 39_63
RIOB33.IOB_Y1.LVCMOS15.DRIVE.I8 30_41 32_16 33_61 38_00 38_02 38_08 !38_10 38_14 38_32 !38_40 !38_42 38_62 39_01 !39_09 39_15 !39_41 39_63
RIOB33.IOB_Y1.LVCMOS15.DRIVE.I12 30_41 32_16 33_61 38_00 !38_02 !38_08 !38_10 38_14 38_32 !38_40 !38_42 38_62 !39_01 !39_09 39_15 !39_41 39_63
RIOB33.IOB_Y1.LVCMOS15.DRIVE.I16 30_41 32_16 33_61 38_00 !38_02 !38_08 38_10 38_14 38_32 !38_40 !38_42 38_62 39_01 39_09 39_15 !39_41 39_63
RIOB33.IOB_Y1.LVCMOS15_LVCMOS18.DRIVE.I4 30_41 32_16 33_61 38_00 38_02 !38_08 !38_10 38_14 38_32 !38_40 !38_42 38_62 !39_01 39_09 39_15 !39_41 39_63
RIOB33.IOB_Y1.LVCMOS18.DRIVE.I12_I8 30_41 32_16 33_61 !38_00 38_02 38_08 !38_10 38_14 38_32 !38_40 !38_42 38_62 39_01 !39_09 39_15 !39_41 39_63
RIOB33.IOB_Y1.LVCMOS18.DRIVE.I16 30_41 32_16 33_61 38_00 38_02 !38_08 !38_10 38_14 38_32 !38_40 !38_42 38_62 39_01 !39_09 39_15 !39_41 39_63
RIOB33.IOB_Y1.LVCMOS18.DRIVE.I24 30_41 32_16 33_61 !38_00 !38_02 38_08 38_10 38_14 38_32 !38_40 !38_42 38_62 39_01 !39_09 39_15 !39_41 39_63
RIOB33.IOB_Y1.LVCMOS25.DRIVE.I4 30_41 32_16 33_61 38_00 38_02 !38_08 !38_10 38_14 !38_32 !38_40 !38_42 38_62 !39_01 39_09 39_15 !39_41 39_63
RIOB33.IOB_Y1.LVCMOS25.DRIVE.I8 30_41 32_16 33_61 !38_00 !38_02 38_08 !38_10 38_14 !38_32 !38_40 !38_42 38_62 !39_01 !39_09 39_15 !39_41 39_63
RIOB33.IOB_Y1.LVCMOS25.DRIVE.I12 30_41 32_16 33_61 !38_00 !38_02 !38_08 !38_10 38_14 !38_32 !38_40 !38_42 38_62 !39_01 !39_09 39_15 !39_41 39_63
RIOB33.IOB_Y1.LVCMOS25.DRIVE.I16 30_41 32_16 33_61 !38_00 !38_02 !38_08 38_10 38_14 !38_32 !38_40 !38_42 38_62 39_01 39_09 39_15 !39_41 39_63
RIOB33.IOB_Y1.LVCMOS25_LVCMOS33_LVTTL.IN 38_14 38_40 38_42 39_41
RIOB33.IOB_Y1.LVCMOS33.DRIVE.I16 30_41 32_16 33_61 38_00 !38_02 !38_08 38_10 !38_14 !38_32 38_62 !39_01 39_09 !39_15 39_63
RIOB33.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I4 30_41 32_16 33_61 38_00 38_02 !38_08 !38_10 !38_14 !38_32 38_62 !39_01 39_09 !39_15 39_63
RIOB33.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I8 30_41 32_16 33_61 !38_00 38_02 38_08 !38_10 !38_14 !38_32 38_62 39_01 !39_09 !39_15 39_63
RIOB33.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I16 30_41 32_16 33_61 38_00 38_02 !38_08 !38_10 !38_14 !38_32 38_62 39_01 !39_09 !39_15 39_63
RIOB33.IOB_Y1.LVCMOS33.DRIVE.I16 30_41 32_16 33_61 38_00 !38_02 !38_08 38_10 !38_14 !38_32 !38_40 !38_42 38_62 !39_01 39_09 !39_15 !39_41 39_63
RIOB33.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I4 30_41 32_16 33_61 38_00 38_02 !38_08 !38_10 !38_14 !38_32 !38_40 !38_42 38_62 !39_01 39_09 !39_15 !39_41 39_63
RIOB33.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I8 30_41 32_16 33_61 !38_00 38_02 38_08 !38_10 !38_14 !38_32 !38_40 !38_42 38_62 39_01 !39_09 !39_15 !39_41 39_63
RIOB33.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I16 30_41 32_16 33_61 38_00 38_02 !38_08 !38_10 !38_14 !38_32 !38_40 !38_42 38_62 39_01 !39_09 !39_15 !39_41 39_63

128
zynq7/segbits_riob33.origin_info.db Normal file
View File

@ -0,0 +1,128 @@
RIOB33.IOB_Y0.IBUFDISABLE.I origin:030-iob 38_82
RIOB33.IOB_Y0.IDELMUXE3.0 origin:035-iob-ilogic 29_101
RIOB33.IOB_Y0.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE origin:035-iob-ilogic 27_98
RIOB33.IOB_Y0.IFF.DDR_CLK_EDGE.SAME_EDGE origin:035-iob-ilogic 26_99
RIOB33.IOB_Y0.IFF.SRTYPE.SYNC origin:035-iob-ilogic 29_67
RIOB33.IOB_Y0.IFF.ZINIT_Q1 origin:035-iob-ilogic 28_72
RIOB33.IOB_Y0.IFF.ZINIT_Q2 origin:035-iob-ilogic 28_76
RIOB33.IOB_Y0.IFF.ZINIT_Q3 origin:035-iob-ilogic 28_86
RIOB33.IOB_Y0.IFF.ZINIT_Q4 origin:035-iob-ilogic 28_94
RIOB33.IOB_Y0.IFF.ZINV_C origin:035-iob-ilogic 28_126 29_123 29_125
RIOB33.IOB_Y0.IFF.ZINV_OCLK origin:035-iob-ilogic 28_64
RIOB33.IOB_Y0.IFF.ZSRVAL_Q1 origin:035-iob-ilogic 29_71
RIOB33.IOB_Y0.IFF.ZSRVAL_Q2 origin:035-iob-ilogic 29_75
RIOB33.IOB_Y0.IFF.ZSRVAL_Q3 origin:035-iob-ilogic 29_85
RIOB33.IOB_Y0.IFF.ZSRVAL_Q4 origin:035-iob-ilogic 29_93
RIOB33.IOB_Y0.IFFDELMUXE3.0 origin:035-iob-ilogic 28_116
RIOB33.IOB_Y0.INOUT origin:030-iob 30_67
RIOB33.IOB_Y0.INTERMDISABLE.I origin:030-iob 39_89
RIOB33.IOB_Y0.IN_ONLY origin:030-iob 38_118 39_119 39_125
RIOB33.IOB_Y0.ISERDES.DATA_RATE.SDR origin:035-iob-ilogic 27_108
RIOB33.IOB_Y0.ISERDES.INTERFACE_TYPE.MEMORY_DDR3 origin:035-iob-ilogic 26_117
RIOB33.IOB_Y0.ISERDES.INTERFACE_TYPE.OVERSAMPLE origin:035-iob-ilogic 26_115
RIOB33.IOB_Y0.LVCMOS12.DRIVE.I12 origin:030-iob !38_118 !39_117 !39_119 !39_125 31_86 32_66 33_111 38_112 38_126 38_64 39_113 39_127 39_65 39_95
RIOB33.IOB_Y0.LVCMOS12.DRIVE.I4 origin:030-iob !39_117 !39_119 !39_127 31_86 32_66 33_111 38_112 38_118 38_126 38_64 39_113 39_125 39_65 39_95
RIOB33.IOB_Y0.LVCMOS12.DRIVE.I8 origin:030-iob !38_118 !38_126 !39_117 !39_125 !39_127 31_86 32_66 33_111 38_112 38_64 39_113 39_119 39_65 39_95
RIOB33.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18.IN origin:030-iob !39_87 38_86 39_113 39_85
RIOB33.IOB_Y0.LVCMOS15.DRIVE.I12 origin:030-iob !38_118 !38_126 !39_117 !39_119 !39_125 31_86 32_66 33_111 38_112 38_64 39_113 39_127 39_65 39_95
RIOB33.IOB_Y0.LVCMOS15.DRIVE.I16 origin:030-iob !39_119 !39_125 31_86 32_66 33_111 38_112 38_118 38_126 38_64 39_113 39_117 39_127 39_65 39_95
RIOB33.IOB_Y0.LVCMOS15.DRIVE.I8 origin:030-iob !38_118 !39_117 31_86 32_66 33_111 38_112 38_126 38_64 39_113 39_119 39_125 39_127 39_65 39_95
RIOB33.IOB_Y0.LVCMOS15_LVCMOS18.DRIVE.I4 origin:030-iob !38_126 !39_117 !39_119 31_86 32_66 33_111 38_112 38_118 38_64 39_113 39_125 39_127 39_65 39_95
RIOB33.IOB_Y0.LVCMOS18.DRIVE.I12_I8 origin:030-iob !38_118 !39_117 !39_127 31_86 32_66 33_111 38_112 38_126 38_64 39_113 39_119 39_125 39_65 39_95
RIOB33.IOB_Y0.LVCMOS18.DRIVE.I16 origin:030-iob !38_118 !39_117 !39_119 31_86 32_66 33_111 38_112 38_126 38_64 39_113 39_125 39_127 39_65 39_95
RIOB33.IOB_Y0.LVCMOS18.DRIVE.I24 origin:030-iob !38_118 !39_125 !39_127 31_86 32_66 33_111 38_112 38_126 38_64 39_113 39_117 39_119 39_65 39_95
RIOB33.IOB_Y0.LVCMOS25.DRIVE.I12 origin:030-iob !38_118 !38_126 !39_117 !39_119 !39_125 !39_127 !39_95 31_86 32_66 33_111 38_112 38_64 39_113 39_65
RIOB33.IOB_Y0.LVCMOS25.DRIVE.I16 origin:030-iob !39_119 !39_125 !39_127 !39_95 31_86 32_66 33_111 38_112 38_118 38_126 38_64 39_113 39_117 39_65
RIOB33.IOB_Y0.LVCMOS25.DRIVE.I4 origin:030-iob !38_126 !39_117 !39_119 !39_95 31_86 32_66 33_111 38_112 38_118 38_64 39_113 39_125 39_127 39_65
RIOB33.IOB_Y0.LVCMOS25.DRIVE.I8 origin:030-iob !38_118 !38_126 !39_117 !39_125 !39_127 !39_95 31_86 32_66 33_111 38_112 38_64 39_113 39_119 39_65
RIOB33.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN origin:030-iob 38_86 39_113 39_85 39_87
RIOB33.IOB_Y0.LVCMOS33.DRIVE.I16 origin:030-iob !38_112 !38_126 !39_113 !39_119 !39_125 !39_95 31_86 32_66 33_111 38_118 38_64 39_117 39_127 39_65
RIOB33.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I12_I16 origin:030-iob !38_112 !38_118 !39_113 !39_117 !39_119 !39_95 31_86 32_66 33_111 38_126 38_64 39_125 39_127 39_65
RIOB33.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I12_I8 origin:030-iob !38_112 !38_118 !39_113 !39_117 !39_127 !39_95 31_86 32_66 33_111 38_126 38_64 39_119 39_125 39_65
RIOB33.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I4 origin:030-iob !38_112 !38_126 !39_113 !39_117 !39_119 !39_95 31_86 32_66 33_111 38_118 38_64 39_125 39_127 39_65
RIOB33.IOB_Y0.LVTTL.DRIVE.I24 origin:030-iob !38_112 !38_118 !39_113 !39_125 !39_127 !39_95 31_86 32_66 33_111 38_126 38_64 39_117 39_119 39_65
RIOB33.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE origin:036-iob-ologic !31_92
RIOB33.IOB_Y0.ODDR.DDR_CLK_EDGE.SAME_EDGE origin:036-iob-ologic 31_92
RIOB33.IOB_Y0.OFF.ZINIT_Q origin:036-iob-ologic 33_97
RIOB33.IOB_Y0.OSERDESE.DATA_RATE_TQ.BUF origin:036-iob-ologic 32_66
RIOB33.IOB_Y0.OSERDESE.DATA_RATE_TQ.DDR origin:036-iob-ologic 32_70
RIOB33.IOB_Y0.OSERDESE.DATA_RATE_TQ.SDR origin:036-iob-ologic 33_69
RIOB33.IOB_Y0.OSERDESE.DATA_WIDTH.2 origin:036-iob-ologic 30_127
RIOB33.IOB_Y0.OSERDESE.DATA_WIDTH.3 origin:036-iob-ologic 31_126
RIOB33.IOB_Y0.OSERDESE.DATA_WIDTH.4 origin:036-iob-ologic 31_124
RIOB33.IOB_Y0.OSERDESE.DATA_WIDTH.5 origin:036-iob-ologic 30_121
RIOB33.IOB_Y0.OSERDESE.DATA_WIDTH.6 origin:036-iob-ologic 31_120
RIOB33.IOB_Y0.OSERDESE.DATA_WIDTH.7 origin:036-iob-ologic 30_123
RIOB33.IOB_Y0.OSERDESE.DATA_WIDTH.8 origin:036-iob-ologic 31_116
RIOB33.IOB_Y0.PULLTYPE.KEEPER origin:030-iob !39_93 38_92 38_94
RIOB33.IOB_Y0.PULLTYPE.NONE origin:030-iob !38_92 !39_93 38_94
RIOB33.IOB_Y0.PULLTYPE.PULLDOWN origin:030-iob !38_92 !38_94 !39_93
RIOB33.IOB_Y0.PULLTYPE.PULLUP origin:030-iob !38_92 38_94 39_93
RIOB33.IOB_Y0.SLEW.FAST origin:030-iob !38_106 !38_110 !39_105 !39_109
RIOB33.IOB_Y0.SLEW.SLOW origin:030-iob 38_106 38_110 39_105 39_109
RIOB33.IOB_Y0.TFF.ZINIT_Q origin:036-iob-ologic 30_75
RIOB33.IOB_Y0.ZINV_D origin:035-iob-ilogic 29_109
RIOB33.IOB_Y1.IBUFDISABLE.I origin:030-iob 39_45
RIOB33.IOB_Y1.IDELMUXE3.0 origin:035-iob-ilogic 28_26
RIOB33.IOB_Y1.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE origin:035-iob-ilogic 26_29
RIOB33.IOB_Y1.IFF.DDR_CLK_EDGE.SAME_EDGE origin:035-iob-ilogic 27_28
RIOB33.IOB_Y1.IFF.SRTYPE.SYNC origin:035-iob-ilogic 28_60
RIOB33.IOB_Y1.IFF.ZINIT_Q1 origin:035-iob-ilogic 29_55
RIOB33.IOB_Y1.IFF.ZINIT_Q2 origin:035-iob-ilogic 29_51
RIOB33.IOB_Y1.IFF.ZINIT_Q3 origin:035-iob-ilogic 29_41
RIOB33.IOB_Y1.IFF.ZINIT_Q4 origin:035-iob-ilogic 29_33
RIOB33.IOB_Y1.IFF.ZINV_C origin:035-iob-ilogic 28_02 28_04 29_01
RIOB33.IOB_Y1.IFF.ZINV_OCLK origin:035-iob-ilogic 29_63
RIOB33.IOB_Y1.IFF.ZSRVAL_Q1 origin:035-iob-ilogic 28_56
RIOB33.IOB_Y1.IFF.ZSRVAL_Q2 origin:035-iob-ilogic 28_52
RIOB33.IOB_Y1.IFF.ZSRVAL_Q3 origin:035-iob-ilogic 28_42
RIOB33.IOB_Y1.IFF.ZSRVAL_Q4 origin:035-iob-ilogic 28_34
RIOB33.IOB_Y1.IFFDELMUXE3.0 origin:035-iob-ilogic 29_11
RIOB33.IOB_Y1.INOUT origin:030-iob 31_60
RIOB33.IOB_Y1.INTERMDISABLE.I origin:030-iob 38_38
RIOB33.IOB_Y1.IN_ONLY origin:030-iob 38_02 38_08 38_14 38_40 38_42 39_09 39_41
RIOB33.IOB_Y1.ISERDES.DATA_RATE.SDR origin:035-iob-ilogic 26_19
RIOB33.IOB_Y1.ISERDES.INTERFACE_TYPE.MEMORY_DDR3 origin:035-iob-ilogic 27_10
RIOB33.IOB_Y1.ISERDES.INTERFACE_TYPE.OVERSAMPLE origin:035-iob-ilogic 27_12
RIOB33.IOB_Y1.LVCMOS12.DRIVE.I12 origin:030-iob !38_02 !38_08 !38_10 !38_40 !38_42 !39_09 !39_41 30_41 32_16 33_61 38_00 38_14 38_32 38_62 39_01 39_15 39_63
RIOB33.IOB_Y1.LVCMOS12.DRIVE.I4 origin:030-iob !38_00 !38_08 !38_10 !38_40 !38_42 !39_41 30_41 32_16 33_61 38_02 38_14 38_32 38_62 39_01 39_09 39_15 39_63
RIOB33.IOB_Y1.LVCMOS12.DRIVE.I8 origin:030-iob !38_00 !38_02 !38_10 !38_40 !38_42 !39_01 !39_09 !39_41 30_41 32_16 33_61 38_08 38_14 38_32 38_62 39_15 39_63
RIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18.IN origin:030-iob !38_40 38_14 38_42 39_41
RIOB33.IOB_Y1.LVCMOS15.DRIVE.I12 origin:030-iob !38_02 !38_08 !38_10 !38_40 !38_42 !39_01 !39_09 !39_41 30_41 32_16 33_61 38_00 38_14 38_32 38_62 39_15 39_63
RIOB33.IOB_Y1.LVCMOS15.DRIVE.I16 origin:030-iob !38_02 !38_08 !38_40 !38_42 !39_41 30_41 32_16 33_61 38_00 38_10 38_14 38_32 38_62 39_01 39_09 39_15 39_63
RIOB33.IOB_Y1.LVCMOS15.DRIVE.I8 origin:030-iob !38_10 !38_40 !38_42 !39_09 !39_41 30_41 32_16 33_61 38_00 38_02 38_08 38_14 38_32 38_62 39_01 39_15 39_63
RIOB33.IOB_Y1.LVCMOS15_LVCMOS18.DRIVE.I4 origin:030-iob !38_08 !38_10 !38_40 !38_42 !39_01 !39_41 30_41 32_16 33_61 38_00 38_02 38_14 38_32 38_62 39_09 39_15 39_63
RIOB33.IOB_Y1.LVCMOS18.DRIVE.I12_I8 origin:030-iob !38_00 !38_10 !38_40 !38_42 !39_09 !39_41 30_41 32_16 33_61 38_02 38_08 38_14 38_32 38_62 39_01 39_15 39_63
RIOB33.IOB_Y1.LVCMOS18.DRIVE.I16 origin:030-iob !38_08 !38_10 !38_40 !38_42 !39_09 !39_41 30_41 32_16 33_61 38_00 38_02 38_14 38_32 38_62 39_01 39_15 39_63
RIOB33.IOB_Y1.LVCMOS18.DRIVE.I24 origin:030-iob !38_00 !38_02 !38_40 !38_42 !39_09 !39_41 30_41 32_16 33_61 38_08 38_10 38_14 38_32 38_62 39_01 39_15 39_63
RIOB33.IOB_Y1.LVCMOS25.DRIVE.I12 origin:030-iob !38_00 !38_02 !38_08 !38_10 !38_32 !38_40 !38_42 !39_01 !39_09 !39_41 30_41 32_16 33_61 38_14 38_62 39_15 39_63
RIOB33.IOB_Y1.LVCMOS25.DRIVE.I16 origin:030-iob !38_00 !38_02 !38_08 !38_32 !38_40 !38_42 !39_41 30_41 32_16 33_61 38_10 38_14 38_62 39_01 39_09 39_15 39_63
RIOB33.IOB_Y1.LVCMOS25.DRIVE.I4 origin:030-iob !38_08 !38_10 !38_32 !38_40 !38_42 !39_01 !39_41 30_41 32_16 33_61 38_00 38_02 38_14 38_62 39_09 39_15 39_63
RIOB33.IOB_Y1.LVCMOS25.DRIVE.I8 origin:030-iob !38_00 !38_02 !38_10 !38_32 !38_40 !38_42 !39_01 !39_09 !39_41 30_41 32_16 33_61 38_08 38_14 38_62 39_15 39_63
RIOB33.IOB_Y1.LVCMOS25_LVCMOS33_LVTTL.IN origin:030-iob 38_14 38_40 38_42 39_41
RIOB33.IOB_Y1.LVCMOS33.DRIVE.I16 origin:030-iob !38_02 !38_08 !38_14 !38_32 !38_40 !38_42 !39_01 !39_15 !39_41 30_41 32_16 33_61 38_00 38_10 38_62 39_09 39_63
RIOB33.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I16 origin:030-iob !38_08 !38_10 !38_14 !38_32 !38_40 !38_42 !39_09 !39_15 !39_41 30_41 32_16 33_61 38_00 38_02 38_62 39_01 39_63
RIOB33.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I8 origin:030-iob !38_00 !38_10 !38_14 !38_32 !38_40 !38_42 !39_09 !39_15 !39_41 30_41 32_16 33_61 38_02 38_08 38_62 39_01 39_63
RIOB33.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I4 origin:030-iob !38_08 !38_10 !38_14 !38_32 !38_40 !38_42 !39_01 !39_15 !39_41 30_41 32_16 33_61 38_00 38_02 38_62 39_09 39_63
RIOB33.IOB_Y1.LVTTL.DRIVE.I24 origin:030-iob !38_00 !38_02 !38_14 !38_32 !38_40 !38_42 !39_09 !39_15 !39_41 30_41 32_16 33_61 38_08 38_10 38_62 39_01 39_63
RIOB33.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE origin:036-iob-ologic !30_35
RIOB33.IOB_Y1.ODDR.DDR_CLK_EDGE.SAME_EDGE origin:036-iob-ologic 30_35
RIOB33.IOB_Y1.OFF.ZINIT_Q origin:036-iob-ologic 32_30
RIOB33.IOB_Y1.OSERDESE.DATA_RATE_TQ.BUF origin:036-iob-ologic 33_61
RIOB33.IOB_Y1.OSERDESE.DATA_RATE_TQ.DDR origin:036-iob-ologic 33_57
RIOB33.IOB_Y1.OSERDESE.DATA_RATE_TQ.SDR origin:036-iob-ologic 32_58
RIOB33.IOB_Y1.OSERDESE.DATA_WIDTH.2 origin:036-iob-ologic 31_00
RIOB33.IOB_Y1.OSERDESE.DATA_WIDTH.3 origin:036-iob-ologic 30_01
RIOB33.IOB_Y1.OSERDESE.DATA_WIDTH.4 origin:036-iob-ologic 30_03
RIOB33.IOB_Y1.OSERDESE.DATA_WIDTH.5 origin:036-iob-ologic 31_06
RIOB33.IOB_Y1.OSERDESE.DATA_WIDTH.6 origin:036-iob-ologic 30_07
RIOB33.IOB_Y1.OSERDESE.DATA_WIDTH.7 origin:036-iob-ologic 31_04
RIOB33.IOB_Y1.OSERDESE.DATA_WIDTH.8 origin:036-iob-ologic 30_11
RIOB33.IOB_Y1.PULLTYPE.KEEPER origin:030-iob !38_34 39_33 39_35
RIOB33.IOB_Y1.PULLTYPE.NONE origin:030-iob !38_34 !39_35 39_33
RIOB33.IOB_Y1.PULLTYPE.PULLDOWN origin:030-iob !38_34 !39_33 !39_35
RIOB33.IOB_Y1.PULLTYPE.PULLUP origin:030-iob !39_35 38_34 39_33
RIOB33.IOB_Y1.SLEW.FAST origin:030-iob !38_18 !38_22 !39_17 !39_21
RIOB33.IOB_Y1.SLEW.SLOW origin:030-iob 38_18 38_22 39_17 39_21
RIOB33.IOB_Y1.TFF.ZINIT_Q origin:036-iob-ologic 31_52
RIOB33.IOB_Y1.ZINV_D origin:035-iob-ilogic 28_18

1108
zynq7/tile_type_BRAM_INT_INTERFACE_L.json
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1108
zynq7/tile_type_BRAM_INT_INTERFACE_R.json
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28728
zynq7/tile_type_BRAM_L.json
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28728
zynq7/tile_type_BRAM_R.json
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132
zynq7/tile_type_BRKH_BRAM.json
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@ -2,70 +2,70 @@
"pips": {},
"sites": [],
"tile_type": "BRKH_BRAM",
"wires": [
"BRKH_BRAM_CASCADEA_L",
"BRKH_BRAM_CASCADEA_R",
"BRKH_BRAM_CASCADEB_L",
"BRKH_BRAM_CASCADEB_R",
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU0",
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU1",
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU10",
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU11",
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU12",
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU13",
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU14",
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU2",
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU3",
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU4",
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU5",
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU6",
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU7",
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU8",
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU9",
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU0",
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU1",
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU10",
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU11",
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU12",
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU13",
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU14",
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU2",
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU3",
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU4",
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU5",
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU6",
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU7",
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU8",
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU9",
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU0",
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU1",
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU10",
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU11",
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU12",
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU13",
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU14",
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU2",
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU3",
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU4",
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU5",
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU6",
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU7",
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU8",
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU9",
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU0",
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU1",
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU10",
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU11",
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU12",
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU13",
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU14",
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU2",
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU3",
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU4",
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU5",
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU6",
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU7",
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU8",
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU9"
]
"wires": {
"BRKH_BRAM_CASCADEA_L": null,
"BRKH_BRAM_CASCADEA_R": null,
"BRKH_BRAM_CASCADEB_L": null,
"BRKH_BRAM_CASCADEB_R": null,
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU0": null,
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU1": null,
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU10": null,
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU11": null,
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU12": null,
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU13": null,
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU14": null,
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU2": null,
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU3": null,
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU4": null,
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU5": null,
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU6": null,
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU7": null,
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU8": null,
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU9": null,
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU0": null,
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU1": null,
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU10": null,
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU11": null,
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU12": null,
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU13": null,
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU14": null,
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU2": null,
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU3": null,
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU4": null,
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU5": null,
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU6": null,
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU7": null,
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU8": null,
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU9": null,
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU0": null,
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU1": null,
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU10": null,
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU11": null,
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU12": null,
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU13": null,
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU14": null,
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU2": null,
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU3": null,
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU4": null,
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU5": null,
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU6": null,
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU7": null,
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU8": null,
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU9": null,
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU0": null,
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU1": null,
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU10": null,
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU11": null,
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU12": null,
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU13": null,
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU14": null,
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU2": null,
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU3": null,
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU4": null,
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU5": null,
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU6": null,
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU7": null,
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU8": null,
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU9": null
}
}

24
zynq7/tile_type_BRKH_CLB.json
View File

@ -2,10 +2,22 @@
"pips": {},
"sites": [],
"tile_type": "BRKH_CLB",
"wires": [
"BRKH_CLB_COUT0_L",
"BRKH_CLB_COUT0_R",
"BRKH_CLB_COUT1_L",
"BRKH_CLB_COUT1_R"
]
"wires": {
"BRKH_CLB_COUT0_L": {
"cap": "1.000",
"res": "0.000"
},
"BRKH_CLB_COUT0_R": {
"cap": "1.000",
"res": "0.000"
},
"BRKH_CLB_COUT1_L": {
"cap": "1.000",
"res": "0.000"
},
"BRKH_CLB_COUT1_R": {
"cap": "1.000",
"res": "0.000"
}
}
}

260
zynq7/tile_type_BRKH_CLK.json
View File

@ -2,134 +2,134 @@
"pips": {},
"sites": [],
"tile_type": "BRKH_CLK",
"wires": [
"BRKH_CLK_CK_BUFG_CASC0",
"BRKH_CLK_CK_BUFG_CASC1",
"BRKH_CLK_CK_BUFG_CASC10",
"BRKH_CLK_CK_BUFG_CASC11",
"BRKH_CLK_CK_BUFG_CASC12",
"BRKH_CLK_CK_BUFG_CASC13",
"BRKH_CLK_CK_BUFG_CASC14",
"BRKH_CLK_CK_BUFG_CASC15",
"BRKH_CLK_CK_BUFG_CASC16",
"BRKH_CLK_CK_BUFG_CASC17",
"BRKH_CLK_CK_BUFG_CASC18",
"BRKH_CLK_CK_BUFG_CASC19",
"BRKH_CLK_CK_BUFG_CASC2",
"BRKH_CLK_CK_BUFG_CASC20",
"BRKH_CLK_CK_BUFG_CASC21",
"BRKH_CLK_CK_BUFG_CASC22",
"BRKH_CLK_CK_BUFG_CASC23",
"BRKH_CLK_CK_BUFG_CASC24",
"BRKH_CLK_CK_BUFG_CASC25",
"BRKH_CLK_CK_BUFG_CASC26",
"BRKH_CLK_CK_BUFG_CASC27",
"BRKH_CLK_CK_BUFG_CASC28",
"BRKH_CLK_CK_BUFG_CASC29",
"BRKH_CLK_CK_BUFG_CASC3",
"BRKH_CLK_CK_BUFG_CASC30",
"BRKH_CLK_CK_BUFG_CASC31",
"BRKH_CLK_CK_BUFG_CASC4",
"BRKH_CLK_CK_BUFG_CASC5",
"BRKH_CLK_CK_BUFG_CASC6",
"BRKH_CLK_CK_BUFG_CASC7",
"BRKH_CLK_CK_BUFG_CASC8",
"BRKH_CLK_CK_BUFG_CASC9",
"BRKH_CLK_CK_GCLK0",
"BRKH_CLK_CK_GCLK1",
"BRKH_CLK_CK_GCLK10",
"BRKH_CLK_CK_GCLK11",
"BRKH_CLK_CK_GCLK12",
"BRKH_CLK_CK_GCLK13",
"BRKH_CLK_CK_GCLK14",
"BRKH_CLK_CK_GCLK15",
"BRKH_CLK_CK_GCLK16",
"BRKH_CLK_CK_GCLK17",
"BRKH_CLK_CK_GCLK18",
"BRKH_CLK_CK_GCLK19",
"BRKH_CLK_CK_GCLK2",
"BRKH_CLK_CK_GCLK20",
"BRKH_CLK_CK_GCLK21",
"BRKH_CLK_CK_GCLK22",
"BRKH_CLK_CK_GCLK23",
"BRKH_CLK_CK_GCLK24",
"BRKH_CLK_CK_GCLK25",
"BRKH_CLK_CK_GCLK26",
"BRKH_CLK_CK_GCLK27",
"BRKH_CLK_CK_GCLK28",
"BRKH_CLK_CK_GCLK29",
"BRKH_CLK_CK_GCLK3",
"BRKH_CLK_CK_GCLK30",
"BRKH_CLK_CK_GCLK31",
"BRKH_CLK_CK_GCLK4",
"BRKH_CLK_CK_GCLK5",
"BRKH_CLK_CK_GCLK6",
"BRKH_CLK_CK_GCLK7",
"BRKH_CLK_CK_GCLK8",
"BRKH_CLK_CK_GCLK9",
"BRKH_CLK_R_CK_BUFG_CASC0",
"BRKH_CLK_R_CK_BUFG_CASC1",
"BRKH_CLK_R_CK_BUFG_CASC10",
"BRKH_CLK_R_CK_BUFG_CASC11",
"BRKH_CLK_R_CK_BUFG_CASC12",
"BRKH_CLK_R_CK_BUFG_CASC13",
"BRKH_CLK_R_CK_BUFG_CASC14",
"BRKH_CLK_R_CK_BUFG_CASC15",
"BRKH_CLK_R_CK_BUFG_CASC16",
"BRKH_CLK_R_CK_BUFG_CASC17",
"BRKH_CLK_R_CK_BUFG_CASC18",
"BRKH_CLK_R_CK_BUFG_CASC19",
"BRKH_CLK_R_CK_BUFG_CASC2",
"BRKH_CLK_R_CK_BUFG_CASC20",
"BRKH_CLK_R_CK_BUFG_CASC21",
"BRKH_CLK_R_CK_BUFG_CASC22",
"BRKH_CLK_R_CK_BUFG_CASC23",
"BRKH_CLK_R_CK_BUFG_CASC24",
"BRKH_CLK_R_CK_BUFG_CASC25",
"BRKH_CLK_R_CK_BUFG_CASC26",
"BRKH_CLK_R_CK_BUFG_CASC27",
"BRKH_CLK_R_CK_BUFG_CASC28",
"BRKH_CLK_R_CK_BUFG_CASC29",
"BRKH_CLK_R_CK_BUFG_CASC3",
"BRKH_CLK_R_CK_BUFG_CASC30",
"BRKH_CLK_R_CK_BUFG_CASC31",
"BRKH_CLK_R_CK_BUFG_CASC4",
"BRKH_CLK_R_CK_BUFG_CASC5",
"BRKH_CLK_R_CK_BUFG_CASC6",
"BRKH_CLK_R_CK_BUFG_CASC7",
"BRKH_CLK_R_CK_BUFG_CASC8",
"BRKH_CLK_R_CK_BUFG_CASC9",
"BRKH_CLK_R_CK_GCLK0",
"BRKH_CLK_R_CK_GCLK1",
"BRKH_CLK_R_CK_GCLK10",
"BRKH_CLK_R_CK_GCLK11",
"BRKH_CLK_R_CK_GCLK12",
"BRKH_CLK_R_CK_GCLK13",
"BRKH_CLK_R_CK_GCLK14",
"BRKH_CLK_R_CK_GCLK15",
"BRKH_CLK_R_CK_GCLK16",
"BRKH_CLK_R_CK_GCLK17",
"BRKH_CLK_R_CK_GCLK18",
"BRKH_CLK_R_CK_GCLK19",
"BRKH_CLK_R_CK_GCLK2",
"BRKH_CLK_R_CK_GCLK20",
"BRKH_CLK_R_CK_GCLK21",
"BRKH_CLK_R_CK_GCLK22",
"BRKH_CLK_R_CK_GCLK23",
"BRKH_CLK_R_CK_GCLK24",
"BRKH_CLK_R_CK_GCLK25",
"BRKH_CLK_R_CK_GCLK26",
"BRKH_CLK_R_CK_GCLK27",
"BRKH_CLK_R_CK_GCLK28",
"BRKH_CLK_R_CK_GCLK29",
"BRKH_CLK_R_CK_GCLK3",
"BRKH_CLK_R_CK_GCLK30",
"BRKH_CLK_R_CK_GCLK31",
"BRKH_CLK_R_CK_GCLK4",
"BRKH_CLK_R_CK_GCLK5",
"BRKH_CLK_R_CK_GCLK6",
"BRKH_CLK_R_CK_GCLK7",
"BRKH_CLK_R_CK_GCLK8",
"BRKH_CLK_R_CK_GCLK9"
]
"wires": {
"BRKH_CLK_CK_BUFG_CASC0": null,
"BRKH_CLK_CK_BUFG_CASC1": null,
"BRKH_CLK_CK_BUFG_CASC10": null,
"BRKH_CLK_CK_BUFG_CASC11": null,
"BRKH_CLK_CK_BUFG_CASC12": null,
"BRKH_CLK_CK_BUFG_CASC13": null,
"BRKH_CLK_CK_BUFG_CASC14": null,
"BRKH_CLK_CK_BUFG_CASC15": null,
"BRKH_CLK_CK_BUFG_CASC16": null,
"BRKH_CLK_CK_BUFG_CASC17": null,
"BRKH_CLK_CK_BUFG_CASC18": null,
"BRKH_CLK_CK_BUFG_CASC19": null,
"BRKH_CLK_CK_BUFG_CASC2": null,
"BRKH_CLK_CK_BUFG_CASC20": null,
"BRKH_CLK_CK_BUFG_CASC21": null,
"BRKH_CLK_CK_BUFG_CASC22": null,
"BRKH_CLK_CK_BUFG_CASC23": null,
"BRKH_CLK_CK_BUFG_CASC24": null,
"BRKH_CLK_CK_BUFG_CASC25": null,
"BRKH_CLK_CK_BUFG_CASC26": null,
"BRKH_CLK_CK_BUFG_CASC27": null,
"BRKH_CLK_CK_BUFG_CASC28": null,
"BRKH_CLK_CK_BUFG_CASC29": null,
"BRKH_CLK_CK_BUFG_CASC3": null,
"BRKH_CLK_CK_BUFG_CASC30": null,
"BRKH_CLK_CK_BUFG_CASC31": null,
"BRKH_CLK_CK_BUFG_CASC4": null,
"BRKH_CLK_CK_BUFG_CASC5": null,
"BRKH_CLK_CK_BUFG_CASC6": null,
"BRKH_CLK_CK_BUFG_CASC7": null,
"BRKH_CLK_CK_BUFG_CASC8": null,
"BRKH_CLK_CK_BUFG_CASC9": null,
"BRKH_CLK_CK_GCLK0": null,
"BRKH_CLK_CK_GCLK1": null,
"BRKH_CLK_CK_GCLK10": null,
"BRKH_CLK_CK_GCLK11": null,
"BRKH_CLK_CK_GCLK12": null,
"BRKH_CLK_CK_GCLK13": null,
"BRKH_CLK_CK_GCLK14": null,
"BRKH_CLK_CK_GCLK15": null,
"BRKH_CLK_CK_GCLK16": null,
"BRKH_CLK_CK_GCLK17": null,
"BRKH_CLK_CK_GCLK18": null,
"BRKH_CLK_CK_GCLK19": null,
"BRKH_CLK_CK_GCLK2": null,
"BRKH_CLK_CK_GCLK20": null,
"BRKH_CLK_CK_GCLK21": null,
"BRKH_CLK_CK_GCLK22": null,
"BRKH_CLK_CK_GCLK23": null,
"BRKH_CLK_CK_GCLK24": null,
"BRKH_CLK_CK_GCLK25": null,
"BRKH_CLK_CK_GCLK26": null,
"BRKH_CLK_CK_GCLK27": null,
"BRKH_CLK_CK_GCLK28": null,
"BRKH_CLK_CK_GCLK29": null,
"BRKH_CLK_CK_GCLK3": null,
"BRKH_CLK_CK_GCLK30": null,
"BRKH_CLK_CK_GCLK31": null,
"BRKH_CLK_CK_GCLK4": null,
"BRKH_CLK_CK_GCLK5": null,
"BRKH_CLK_CK_GCLK6": null,
"BRKH_CLK_CK_GCLK7": null,
"BRKH_CLK_CK_GCLK8": null,
"BRKH_CLK_CK_GCLK9": null,
"BRKH_CLK_R_CK_BUFG_CASC0": null,
"BRKH_CLK_R_CK_BUFG_CASC1": null,
"BRKH_CLK_R_CK_BUFG_CASC10": null,
"BRKH_CLK_R_CK_BUFG_CASC11": null,
"BRKH_CLK_R_CK_BUFG_CASC12": null,
"BRKH_CLK_R_CK_BUFG_CASC13": null,
"BRKH_CLK_R_CK_BUFG_CASC14": null,
"BRKH_CLK_R_CK_BUFG_CASC15": null,
"BRKH_CLK_R_CK_BUFG_CASC16": null,
"BRKH_CLK_R_CK_BUFG_CASC17": null,
"BRKH_CLK_R_CK_BUFG_CASC18": null,
"BRKH_CLK_R_CK_BUFG_CASC19": null,
"BRKH_CLK_R_CK_BUFG_CASC2": null,
"BRKH_CLK_R_CK_BUFG_CASC20": null,
"BRKH_CLK_R_CK_BUFG_CASC21": null,
"BRKH_CLK_R_CK_BUFG_CASC22": null,
"BRKH_CLK_R_CK_BUFG_CASC23": null,
"BRKH_CLK_R_CK_BUFG_CASC24": null,
"BRKH_CLK_R_CK_BUFG_CASC25": null,
"BRKH_CLK_R_CK_BUFG_CASC26": null,
"BRKH_CLK_R_CK_BUFG_CASC27": null,
"BRKH_CLK_R_CK_BUFG_CASC28": null,
"BRKH_CLK_R_CK_BUFG_CASC29": null,
"BRKH_CLK_R_CK_BUFG_CASC3": null,
"BRKH_CLK_R_CK_BUFG_CASC30": null,
"BRKH_CLK_R_CK_BUFG_CASC31": null,
"BRKH_CLK_R_CK_BUFG_CASC4": null,
"BRKH_CLK_R_CK_BUFG_CASC5": null,
"BRKH_CLK_R_CK_BUFG_CASC6": null,
"BRKH_CLK_R_CK_BUFG_CASC7": null,
"BRKH_CLK_R_CK_BUFG_CASC8": null,
"BRKH_CLK_R_CK_BUFG_CASC9": null,
"BRKH_CLK_R_CK_GCLK0": null,
"BRKH_CLK_R_CK_GCLK1": null,
"BRKH_CLK_R_CK_GCLK10": null,
"BRKH_CLK_R_CK_GCLK11": null,
"BRKH_CLK_R_CK_GCLK12": null,
"BRKH_CLK_R_CK_GCLK13": null,
"BRKH_CLK_R_CK_GCLK14": null,
"BRKH_CLK_R_CK_GCLK15": null,
"BRKH_CLK_R_CK_GCLK16": null,
"BRKH_CLK_R_CK_GCLK17": null,
"BRKH_CLK_R_CK_GCLK18": null,
"BRKH_CLK_R_CK_GCLK19": null,
"BRKH_CLK_R_CK_GCLK2": null,
"BRKH_CLK_R_CK_GCLK20": null,
"BRKH_CLK_R_CK_GCLK21": null,
"BRKH_CLK_R_CK_GCLK22": null,
"BRKH_CLK_R_CK_GCLK23": null,
"BRKH_CLK_R_CK_GCLK24": null,
"BRKH_CLK_R_CK_GCLK25": null,
"BRKH_CLK_R_CK_GCLK26": null,
"BRKH_CLK_R_CK_GCLK27": null,
"BRKH_CLK_R_CK_GCLK28": null,
"BRKH_CLK_R_CK_GCLK29": null,
"BRKH_CLK_R_CK_GCLK3": null,
"BRKH_CLK_R_CK_GCLK30": null,
"BRKH_CLK_R_CK_GCLK31": null,
"BRKH_CLK_R_CK_GCLK4": null,
"BRKH_CLK_R_CK_GCLK5": null,
"BRKH_CLK_R_CK_GCLK6": null,
"BRKH_CLK_R_CK_GCLK7": null,
"BRKH_CLK_R_CK_GCLK8": null,
"BRKH_CLK_R_CK_GCLK9": null
}
}

22
zynq7/tile_type_BRKH_CMT.json
View File

@ -2,15 +2,15 @@
"pips": {},
"sites": [],
"tile_type": "BRKH_CMT",
"wires": [
"BRKH_CMT_FREQ_REF_NS0",
"BRKH_CMT_FREQ_REF_NS1",
"BRKH_CMT_FREQ_REF_NS2",
"BRKH_CMT_FREQ_REF_NS3",
"BRKH_CMT_PHASEREF0",
"BRKH_CMT_PHASEREF1",
"BRKH_CMT_PHASEREF_BELOW0",
"BRKH_CMT_PHASEREF_BELOW1",
"BRKH_CMT_PHYCTRL_SYNC_BB"
]
"wires": {
"BRKH_CMT_FREQ_REF_NS0": null,
"BRKH_CMT_FREQ_REF_NS1": null,
"BRKH_CMT_FREQ_REF_NS2": null,
"BRKH_CMT_FREQ_REF_NS3": null,
"BRKH_CMT_PHASEREF0": null,
"BRKH_CMT_PHASEREF1": null,
"BRKH_CMT_PHASEREF_BELOW0": null,
"BRKH_CMT_PHASEREF_BELOW1": null,
"BRKH_CMT_PHYCTRL_SYNC_BB": null
}
}

200
zynq7/tile_type_BRKH_DSP_L.json
View File

@ -2,104 +2,104 @@
"pips": {},
"sites": [],
"tile_type": "BRKH_DSP_L",
"wires": [
"BRKH_DSP_ACIN0",
"BRKH_DSP_ACIN1",
"BRKH_DSP_ACIN10",
"BRKH_DSP_ACIN11",
"BRKH_DSP_ACIN12",
"BRKH_DSP_ACIN13",
"BRKH_DSP_ACIN14",
"BRKH_DSP_ACIN15",
"BRKH_DSP_ACIN16",
"BRKH_DSP_ACIN17",
"BRKH_DSP_ACIN18",
"BRKH_DSP_ACIN19",
"BRKH_DSP_ACIN2",
"BRKH_DSP_ACIN20",
"BRKH_DSP_ACIN21",
"BRKH_DSP_ACIN22",
"BRKH_DSP_ACIN23",
"BRKH_DSP_ACIN24",
"BRKH_DSP_ACIN25",
"BRKH_DSP_ACIN26",
"BRKH_DSP_ACIN27",
"BRKH_DSP_ACIN28",
"BRKH_DSP_ACIN29",
"BRKH_DSP_ACIN3",
"BRKH_DSP_ACIN4",
"BRKH_DSP_ACIN5",
"BRKH_DSP_ACIN6",
"BRKH_DSP_ACIN7",
"BRKH_DSP_ACIN8",
"BRKH_DSP_ACIN9",
"BRKH_DSP_BCIN0",
"BRKH_DSP_BCIN1",
"BRKH_DSP_BCIN10",
"BRKH_DSP_BCIN11",
"BRKH_DSP_BCIN12",
"BRKH_DSP_BCIN13",
"BRKH_DSP_BCIN14",
"BRKH_DSP_BCIN15",
"BRKH_DSP_BCIN16",
"BRKH_DSP_BCIN17",
"BRKH_DSP_BCIN2",
"BRKH_DSP_BCIN3",
"BRKH_DSP_BCIN4",
"BRKH_DSP_BCIN5",
"BRKH_DSP_BCIN6",
"BRKH_DSP_BCIN7",
"BRKH_DSP_BCIN8",
"BRKH_DSP_BCIN9",
"BRKH_DSP_CARRYCASCIN",
"BRKH_DSP_MULTSIGNIN",
"BRKH_DSP_PCIN0",
"BRKH_DSP_PCIN1",
"BRKH_DSP_PCIN10",
"BRKH_DSP_PCIN11",
"BRKH_DSP_PCIN12",
"BRKH_DSP_PCIN13",
"BRKH_DSP_PCIN14",
"BRKH_DSP_PCIN15",
"BRKH_DSP_PCIN16",
"BRKH_DSP_PCIN17",
"BRKH_DSP_PCIN18",
"BRKH_DSP_PCIN19",
"BRKH_DSP_PCIN2",
"BRKH_DSP_PCIN20",
"BRKH_DSP_PCIN21",
"BRKH_DSP_PCIN22",
"BRKH_DSP_PCIN23",
"BRKH_DSP_PCIN24",
"BRKH_DSP_PCIN25",
"BRKH_DSP_PCIN26",
"BRKH_DSP_PCIN27",
"BRKH_DSP_PCIN28",
"BRKH_DSP_PCIN29",
"BRKH_DSP_PCIN3",
"BRKH_DSP_PCIN30",
"BRKH_DSP_PCIN31",
"BRKH_DSP_PCIN32",
"BRKH_DSP_PCIN33",
"BRKH_DSP_PCIN34",
"BRKH_DSP_PCIN35",
"BRKH_DSP_PCIN36",
"BRKH_DSP_PCIN37",
"BRKH_DSP_PCIN38",
"BRKH_DSP_PCIN39",
"BRKH_DSP_PCIN4",
"BRKH_DSP_PCIN40",
"BRKH_DSP_PCIN41",
"BRKH_DSP_PCIN42",
"BRKH_DSP_PCIN43",
"BRKH_DSP_PCIN44",
"BRKH_DSP_PCIN45",
"BRKH_DSP_PCIN46",
"BRKH_DSP_PCIN47",
"BRKH_DSP_PCIN5",
"BRKH_DSP_PCIN6",
"BRKH_DSP_PCIN7",
"BRKH_DSP_PCIN8",
"BRKH_DSP_PCIN9"
]
"wires": {
"BRKH_DSP_ACIN0": null,
"BRKH_DSP_ACIN1": null,
"BRKH_DSP_ACIN10": null,
"BRKH_DSP_ACIN11": null,
"BRKH_DSP_ACIN12": null,
"BRKH_DSP_ACIN13": null,
"BRKH_DSP_ACIN14": null,
"BRKH_DSP_ACIN15": null,
"BRKH_DSP_ACIN16": null,
"BRKH_DSP_ACIN17": null,
"BRKH_DSP_ACIN18": null,
"BRKH_DSP_ACIN19": null,
"BRKH_DSP_ACIN2": null,
"BRKH_DSP_ACIN20": null,
"BRKH_DSP_ACIN21": null,
"BRKH_DSP_ACIN22": null,
"BRKH_DSP_ACIN23": null,
"BRKH_DSP_ACIN24": null,
"BRKH_DSP_ACIN25": null,
"BRKH_DSP_ACIN26": null,
"BRKH_DSP_ACIN27": null,
"BRKH_DSP_ACIN28": null,
"BRKH_DSP_ACIN29": null,
"BRKH_DSP_ACIN3": null,
"BRKH_DSP_ACIN4": null,
"BRKH_DSP_ACIN5": null,
"BRKH_DSP_ACIN6": null,
"BRKH_DSP_ACIN7": null,
"BRKH_DSP_ACIN8": null,
"BRKH_DSP_ACIN9": null,
"BRKH_DSP_BCIN0": null,
"BRKH_DSP_BCIN1": null,
"BRKH_DSP_BCIN10": null,
"BRKH_DSP_BCIN11": null,
"BRKH_DSP_BCIN12": null,
"BRKH_DSP_BCIN13": null,
"BRKH_DSP_BCIN14": null,
"BRKH_DSP_BCIN15": null,
"BRKH_DSP_BCIN16": null,
"BRKH_DSP_BCIN17": null,
"BRKH_DSP_BCIN2": null,
"BRKH_DSP_BCIN3": null,
"BRKH_DSP_BCIN4": null,
"BRKH_DSP_BCIN5": null,
"BRKH_DSP_BCIN6": null,
"BRKH_DSP_BCIN7": null,
"BRKH_DSP_BCIN8": null,
"BRKH_DSP_BCIN9": null,
"BRKH_DSP_CARRYCASCIN": null,
"BRKH_DSP_MULTSIGNIN": null,
"BRKH_DSP_PCIN0": null,
"BRKH_DSP_PCIN1": null,
"BRKH_DSP_PCIN10": null,
"BRKH_DSP_PCIN11": null,
"BRKH_DSP_PCIN12": null,
"BRKH_DSP_PCIN13": null,
"BRKH_DSP_PCIN14": null,
"BRKH_DSP_PCIN15": null,
"BRKH_DSP_PCIN16": null,
"BRKH_DSP_PCIN17": null,
"BRKH_DSP_PCIN18": null,
"BRKH_DSP_PCIN19": null,
"BRKH_DSP_PCIN2": null,
"BRKH_DSP_PCIN20": null,
"BRKH_DSP_PCIN21": null,
"BRKH_DSP_PCIN22": null,
"BRKH_DSP_PCIN23": null,
"BRKH_DSP_PCIN24": null,
"BRKH_DSP_PCIN25": null,
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}
}

200
zynq7/tile_type_BRKH_DSP_R.json
View File

@ -2,104 +2,104 @@
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1513
zynq7/tile_type_BRKH_INT.json
View File

File diff suppressed because it is too large Load Diff

330
zynq7/tile_type_B_TERM_INT.json
View File

@ -2,124 +2,214 @@
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"B_TERM_UTURN_INT_SS6E3": null,
"B_TERM_UTURN_INT_SW2BEG0": null,
"B_TERM_UTURN_INT_SW2BEG1": null,
"B_TERM_UTURN_INT_SW2BEG2": null,
"B_TERM_UTURN_INT_SW2BEG3": null,
"B_TERM_UTURN_INT_SW6A0": null,
"B_TERM_UTURN_INT_SW6A1": null,
"B_TERM_UTURN_INT_SW6A2": null,
"B_TERM_UTURN_INT_SW6A3": null,
"B_TERM_UTURN_INT_SW6B0": null,
"B_TERM_UTURN_INT_SW6B1": null,
"B_TERM_UTURN_INT_SW6B2": null,
"B_TERM_UTURN_INT_SW6B3": null,
"B_TERM_UTURN_INT_SW6C0": null,
"B_TERM_UTURN_INT_SW6C1": null,
"B_TERM_UTURN_INT_SW6C2": null,
"B_TERM_UTURN_INT_SW6C3": null,
"B_TERM_UTURN_INT_SW6D0": null,
"B_TERM_UTURN_INT_SW6D1": null,
"B_TERM_UTURN_INT_SW6D2": null,
"B_TERM_UTURN_INT_SW6D3": null,
"B_TERM_UTURN_INT_SW6END_N0_3": null,
"B_TERM_UTURN_INT_WR1BEG0": null,
"B_TERM_UTURN_INT_WR1END0": null
}
}

6
zynq7/tile_type_B_TERM_INT_PSS.json
View File

@ -2,7 +2,7 @@
"pips": {},
"sites": [],
"tile_type": "B_TERM_INT_PSS",
"wires": [
"DUMMYFOO"
]
"wires": {
"DUMMYFOO": null
}
}

6
zynq7/tile_type_B_TERM_VBRK.json
View File

@ -2,7 +2,7 @@
"pips": {},
"sites": [],
"tile_type": "B_TERM_VBRK",
"wires": [
"DUMMYFOO"
]
"wires": {
"DUMMYFOO": null
}
}

21215
zynq7/tile_type_CFG_CENTER_BOT.json
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28367
zynq7/tile_type_CFG_CENTER_MID.json
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11481
zynq7/tile_type_CFG_CENTER_TOP.json
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2676
zynq7/tile_type_CFG_SECURITY_BOT_PELE1.json
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2654
zynq7/tile_type_CFG_SECURITY_MID_PELE1.json
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1350
zynq7/tile_type_CFG_SECURITY_TOP_PELE1.json
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3974
zynq7/tile_type_CLBLL_L.json
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3974
zynq7/tile_type_CLBLL_R.json
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4016
zynq7/tile_type_CLBLM_L.json
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4016
zynq7/tile_type_CLBLM_R.json
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10860
zynq7/tile_type_CLK_BUFG_BOT_R.json
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3036
zynq7/tile_type_CLK_BUFG_REBUF.json
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10860
zynq7/tile_type_CLK_BUFG_TOP_R.json
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512
zynq7/tile_type_CLK_FEED.json
View File

@ -2,260 +2,260 @@
"pips": {},
"sites": [],
"tile_type": "CLK_FEED",
"wires": [
"CLK_FEED_CK_BUFG_CASC0",
"CLK_FEED_CK_BUFG_CASC1",
"CLK_FEED_CK_BUFG_CASC10",
"CLK_FEED_CK_BUFG_CASC11",
"CLK_FEED_CK_BUFG_CASC12",
"CLK_FEED_CK_BUFG_CASC13",
"CLK_FEED_CK_BUFG_CASC14",
"CLK_FEED_CK_BUFG_CASC15",
"CLK_FEED_CK_BUFG_CASC16",
"CLK_FEED_CK_BUFG_CASC17",
"CLK_FEED_CK_BUFG_CASC18",
"CLK_FEED_CK_BUFG_CASC19",
"CLK_FEED_CK_BUFG_CASC2",
"CLK_FEED_CK_BUFG_CASC20",
"CLK_FEED_CK_BUFG_CASC21",
"CLK_FEED_CK_BUFG_CASC22",
"CLK_FEED_CK_BUFG_CASC23",
"CLK_FEED_CK_BUFG_CASC24",
"CLK_FEED_CK_BUFG_CASC25",
"CLK_FEED_CK_BUFG_CASC26",
"CLK_FEED_CK_BUFG_CASC27",
"CLK_FEED_CK_BUFG_CASC28",
"CLK_FEED_CK_BUFG_CASC29",
"CLK_FEED_CK_BUFG_CASC3",
"CLK_FEED_CK_BUFG_CASC30",
"CLK_FEED_CK_BUFG_CASC31",
"CLK_FEED_CK_BUFG_CASC4",
"CLK_FEED_CK_BUFG_CASC5",
"CLK_FEED_CK_BUFG_CASC6",
"CLK_FEED_CK_BUFG_CASC7",
"CLK_FEED_CK_BUFG_CASC8",
"CLK_FEED_CK_BUFG_CASC9",
"CLK_FEED_CK_GCLK0",
"CLK_FEED_CK_GCLK1",
"CLK_FEED_CK_GCLK10",
"CLK_FEED_CK_GCLK11",
"CLK_FEED_CK_GCLK12",
"CLK_FEED_CK_GCLK13",
"CLK_FEED_CK_GCLK14",
"CLK_FEED_CK_GCLK15",
"CLK_FEED_CK_GCLK16",
"CLK_FEED_CK_GCLK17",
"CLK_FEED_CK_GCLK18",
"CLK_FEED_CK_GCLK19",
"CLK_FEED_CK_GCLK2",
"CLK_FEED_CK_GCLK20",
"CLK_FEED_CK_GCLK21",
"CLK_FEED_CK_GCLK22",
"CLK_FEED_CK_GCLK23",
"CLK_FEED_CK_GCLK24",
"CLK_FEED_CK_GCLK25",
"CLK_FEED_CK_GCLK26",
"CLK_FEED_CK_GCLK27",
"CLK_FEED_CK_GCLK28",
"CLK_FEED_CK_GCLK29",
"CLK_FEED_CK_GCLK3",
"CLK_FEED_CK_GCLK30",
"CLK_FEED_CK_GCLK31",
"CLK_FEED_CK_GCLK4",
"CLK_FEED_CK_GCLK5",
"CLK_FEED_CK_GCLK6",
"CLK_FEED_CK_GCLK7",
"CLK_FEED_CK_GCLK8",
"CLK_FEED_CK_GCLK9",
"CLK_FEED_EE2A0",
"CLK_FEED_EE2A1",
"CLK_FEED_EE2A2",
"CLK_FEED_EE2A3",
"CLK_FEED_EE2BEG0",
"CLK_FEED_EE2BEG1",
"CLK_FEED_EE2BEG2",
"CLK_FEED_EE2BEG3",
"CLK_FEED_EE4A0",
"CLK_FEED_EE4A1",
"CLK_FEED_EE4A2",
"CLK_FEED_EE4A3",
"CLK_FEED_EE4B0",
"CLK_FEED_EE4B1",
"CLK_FEED_EE4B2",
"CLK_FEED_EE4B3",
"CLK_FEED_EE4BEG0",
"CLK_FEED_EE4BEG1",
"CLK_FEED_EE4BEG2",
"CLK_FEED_EE4BEG3",
"CLK_FEED_EE4C0",
"CLK_FEED_EE4C1",
"CLK_FEED_EE4C2",
"CLK_FEED_EE4C3",
"CLK_FEED_EL1BEG0",
"CLK_FEED_EL1BEG1",
"CLK_FEED_EL1BEG2",
"CLK_FEED_EL1BEG3",
"CLK_FEED_ER1BEG0",
"CLK_FEED_ER1BEG1",
"CLK_FEED_ER1BEG2",
"CLK_FEED_ER1BEG3",
"CLK_FEED_LH1",
"CLK_FEED_LH10",
"CLK_FEED_LH11",
"CLK_FEED_LH12",
"CLK_FEED_LH2",
"CLK_FEED_LH3",
"CLK_FEED_LH4",
"CLK_FEED_LH5",
"CLK_FEED_LH6",
"CLK_FEED_LH7",
"CLK_FEED_LH8",
"CLK_FEED_LH9",
"CLK_FEED_MONITOR_N",
"CLK_FEED_MONITOR_P",
"CLK_FEED_NE2A0",
"CLK_FEED_NE2A1",
"CLK_FEED_NE2A2",
"CLK_FEED_NE2A3",
"CLK_FEED_NE4BEG0",
"CLK_FEED_NE4BEG1",
"CLK_FEED_NE4BEG2",
"CLK_FEED_NE4BEG3",
"CLK_FEED_NE4C0",
"CLK_FEED_NE4C1",
"CLK_FEED_NE4C2",
"CLK_FEED_NE4C3",
"CLK_FEED_NW2A0",
"CLK_FEED_NW2A1",
"CLK_FEED_NW2A2",
"CLK_FEED_NW2A3",
"CLK_FEED_NW4A0",
"CLK_FEED_NW4A1",
"CLK_FEED_NW4A2",
"CLK_FEED_NW4A3",
"CLK_FEED_NW4END0",
"CLK_FEED_NW4END1",
"CLK_FEED_NW4END2",
"CLK_FEED_NW4END3",
"CLK_FEED_R_CK_BUFG_CASC0",
"CLK_FEED_R_CK_BUFG_CASC1",
"CLK_FEED_R_CK_BUFG_CASC10",
"CLK_FEED_R_CK_BUFG_CASC11",
"CLK_FEED_R_CK_BUFG_CASC12",
"CLK_FEED_R_CK_BUFG_CASC13",
"CLK_FEED_R_CK_BUFG_CASC14",
"CLK_FEED_R_CK_BUFG_CASC15",
"CLK_FEED_R_CK_BUFG_CASC16",
"CLK_FEED_R_CK_BUFG_CASC17",
"CLK_FEED_R_CK_BUFG_CASC18",
"CLK_FEED_R_CK_BUFG_CASC19",
"CLK_FEED_R_CK_BUFG_CASC2",
"CLK_FEED_R_CK_BUFG_CASC20",
"CLK_FEED_R_CK_BUFG_CASC21",
"CLK_FEED_R_CK_BUFG_CASC22",
"CLK_FEED_R_CK_BUFG_CASC23",
"CLK_FEED_R_CK_BUFG_CASC24",
"CLK_FEED_R_CK_BUFG_CASC25",
"CLK_FEED_R_CK_BUFG_CASC26",
"CLK_FEED_R_CK_BUFG_CASC27",
"CLK_FEED_R_CK_BUFG_CASC28",
"CLK_FEED_R_CK_BUFG_CASC29",
"CLK_FEED_R_CK_BUFG_CASC3",
"CLK_FEED_R_CK_BUFG_CASC30",
"CLK_FEED_R_CK_BUFG_CASC31",
"CLK_FEED_R_CK_BUFG_CASC4",
"CLK_FEED_R_CK_BUFG_CASC5",
"CLK_FEED_R_CK_BUFG_CASC6",
"CLK_FEED_R_CK_BUFG_CASC7",
"CLK_FEED_R_CK_BUFG_CASC8",
"CLK_FEED_R_CK_BUFG_CASC9",
"CLK_FEED_R_CK_GCLK0",
"CLK_FEED_R_CK_GCLK1",
"CLK_FEED_R_CK_GCLK10",
"CLK_FEED_R_CK_GCLK11",
"CLK_FEED_R_CK_GCLK12",
"CLK_FEED_R_CK_GCLK13",
"CLK_FEED_R_CK_GCLK14",
"CLK_FEED_R_CK_GCLK15",
"CLK_FEED_R_CK_GCLK16",
"CLK_FEED_R_CK_GCLK17",
"CLK_FEED_R_CK_GCLK18",
"CLK_FEED_R_CK_GCLK19",
"CLK_FEED_R_CK_GCLK2",
"CLK_FEED_R_CK_GCLK20",
"CLK_FEED_R_CK_GCLK21",
"CLK_FEED_R_CK_GCLK22",
"CLK_FEED_R_CK_GCLK23",
"CLK_FEED_R_CK_GCLK24",
"CLK_FEED_R_CK_GCLK25",
"CLK_FEED_R_CK_GCLK26",
"CLK_FEED_R_CK_GCLK27",
"CLK_FEED_R_CK_GCLK28",
"CLK_FEED_R_CK_GCLK29",
"CLK_FEED_R_CK_GCLK3",
"CLK_FEED_R_CK_GCLK30",
"CLK_FEED_R_CK_GCLK31",
"CLK_FEED_R_CK_GCLK4",
"CLK_FEED_R_CK_GCLK5",
"CLK_FEED_R_CK_GCLK6",
"CLK_FEED_R_CK_GCLK7",
"CLK_FEED_R_CK_GCLK8",
"CLK_FEED_R_CK_GCLK9",
"CLK_FEED_SE2A0",
"CLK_FEED_SE2A1",
"CLK_FEED_SE2A2",
"CLK_FEED_SE2A3",
"CLK_FEED_SE4BEG0",
"CLK_FEED_SE4BEG1",
"CLK_FEED_SE4BEG2",
"CLK_FEED_SE4BEG3",
"CLK_FEED_SE4C0",
"CLK_FEED_SE4C1",
"CLK_FEED_SE4C2",
"CLK_FEED_SE4C3",
"CLK_FEED_SW2A0",
"CLK_FEED_SW2A1",
"CLK_FEED_SW2A2",
"CLK_FEED_SW2A3",
"CLK_FEED_SW4A0",
"CLK_FEED_SW4A1",
"CLK_FEED_SW4A2",
"CLK_FEED_SW4A3",
"CLK_FEED_SW4END0",
"CLK_FEED_SW4END1",
"CLK_FEED_SW4END2",
"CLK_FEED_SW4END3",
"CLK_FEED_WL1END0",
"CLK_FEED_WL1END1",
"CLK_FEED_WL1END2",
"CLK_FEED_WL1END3",
"CLK_FEED_WR1END0",
"CLK_FEED_WR1END1",
"CLK_FEED_WR1END2",
"CLK_FEED_WR1END3",
"CLK_FEED_WW2A0",
"CLK_FEED_WW2A1",
"CLK_FEED_WW2A2",
"CLK_FEED_WW2A3",
"CLK_FEED_WW2END0",
"CLK_FEED_WW2END1",
"CLK_FEED_WW2END2",
"CLK_FEED_WW2END3",
"CLK_FEED_WW4A0",
"CLK_FEED_WW4A1",
"CLK_FEED_WW4A2",
"CLK_FEED_WW4A3",
"CLK_FEED_WW4B0",
"CLK_FEED_WW4B1",
"CLK_FEED_WW4B2",
"CLK_FEED_WW4B3",
"CLK_FEED_WW4C0",
"CLK_FEED_WW4C1",
"CLK_FEED_WW4C2",
"CLK_FEED_WW4C3",
"CLK_FEED_WW4END0",
"CLK_FEED_WW4END1",
"CLK_FEED_WW4END2",
"CLK_FEED_WW4END3"
]
"wires": {
"CLK_FEED_CK_BUFG_CASC0": null,
"CLK_FEED_CK_BUFG_CASC1": null,
"CLK_FEED_CK_BUFG_CASC10": null,
"CLK_FEED_CK_BUFG_CASC11": null,
"CLK_FEED_CK_BUFG_CASC12": null,
"CLK_FEED_CK_BUFG_CASC13": null,
"CLK_FEED_CK_BUFG_CASC14": null,
"CLK_FEED_CK_BUFG_CASC15": null,
"CLK_FEED_CK_BUFG_CASC16": null,
"CLK_FEED_CK_BUFG_CASC17": null,
"CLK_FEED_CK_BUFG_CASC18": null,
"CLK_FEED_CK_BUFG_CASC19": null,
"CLK_FEED_CK_BUFG_CASC2": null,
"CLK_FEED_CK_BUFG_CASC20": null,
"CLK_FEED_CK_BUFG_CASC21": null,
"CLK_FEED_CK_BUFG_CASC22": null,
"CLK_FEED_CK_BUFG_CASC23": null,
"CLK_FEED_CK_BUFG_CASC24": null,
"CLK_FEED_CK_BUFG_CASC25": null,
"CLK_FEED_CK_BUFG_CASC26": null,
"CLK_FEED_CK_BUFG_CASC27": null,
"CLK_FEED_CK_BUFG_CASC28": null,
"CLK_FEED_CK_BUFG_CASC29": null,
"CLK_FEED_CK_BUFG_CASC3": null,
"CLK_FEED_CK_BUFG_CASC30": null,
"CLK_FEED_CK_BUFG_CASC31": null,
"CLK_FEED_CK_BUFG_CASC4": null,
"CLK_FEED_CK_BUFG_CASC5": null,
"CLK_FEED_CK_BUFG_CASC6": null,
"CLK_FEED_CK_BUFG_CASC7": null,
"CLK_FEED_CK_BUFG_CASC8": null,
"CLK_FEED_CK_BUFG_CASC9": null,
"CLK_FEED_CK_GCLK0": null,
"CLK_FEED_CK_GCLK1": null,
"CLK_FEED_CK_GCLK10": null,
"CLK_FEED_CK_GCLK11": null,
"CLK_FEED_CK_GCLK12": null,
"CLK_FEED_CK_GCLK13": null,
"CLK_FEED_CK_GCLK14": null,
"CLK_FEED_CK_GCLK15": null,
"CLK_FEED_CK_GCLK16": null,
"CLK_FEED_CK_GCLK17": null,
"CLK_FEED_CK_GCLK18": null,
"CLK_FEED_CK_GCLK19": null,
"CLK_FEED_CK_GCLK2": null,
"CLK_FEED_CK_GCLK20": null,
"CLK_FEED_CK_GCLK21": null,
"CLK_FEED_CK_GCLK22": null,
"CLK_FEED_CK_GCLK23": null,
"CLK_FEED_CK_GCLK24": null,
"CLK_FEED_CK_GCLK25": null,
"CLK_FEED_CK_GCLK26": null,
"CLK_FEED_CK_GCLK27": null,
"CLK_FEED_CK_GCLK28": null,
"CLK_FEED_CK_GCLK29": null,
"CLK_FEED_CK_GCLK3": null,
"CLK_FEED_CK_GCLK30": null,
"CLK_FEED_CK_GCLK31": null,
"CLK_FEED_CK_GCLK4": null,
"CLK_FEED_CK_GCLK5": null,
"CLK_FEED_CK_GCLK6": null,
"CLK_FEED_CK_GCLK7": null,
"CLK_FEED_CK_GCLK8": null,
"CLK_FEED_CK_GCLK9": null,
"CLK_FEED_EE2A0": null,
"CLK_FEED_EE2A1": null,
"CLK_FEED_EE2A2": null,
"CLK_FEED_EE2A3": null,
"CLK_FEED_EE2BEG0": null,
"CLK_FEED_EE2BEG1": null,
"CLK_FEED_EE2BEG2": null,
"CLK_FEED_EE2BEG3": null,
"CLK_FEED_EE4A0": null,
"CLK_FEED_EE4A1": null,
"CLK_FEED_EE4A2": null,
"CLK_FEED_EE4A3": null,
"CLK_FEED_EE4B0": null,
"CLK_FEED_EE4B1": null,
"CLK_FEED_EE4B2": null,
"CLK_FEED_EE4B3": null,
"CLK_FEED_EE4BEG0": null,
"CLK_FEED_EE4BEG1": null,
"CLK_FEED_EE4BEG2": null,
"CLK_FEED_EE4BEG3": null,
"CLK_FEED_EE4C0": null,
"CLK_FEED_EE4C1": null,
"CLK_FEED_EE4C2": null,
"CLK_FEED_EE4C3": null,
"CLK_FEED_EL1BEG0": null,
"CLK_FEED_EL1BEG1": null,
"CLK_FEED_EL1BEG2": null,
"CLK_FEED_EL1BEG3": null,
"CLK_FEED_ER1BEG0": null,
"CLK_FEED_ER1BEG1": null,
"CLK_FEED_ER1BEG2": null,
"CLK_FEED_ER1BEG3": null,
"CLK_FEED_LH1": null,
"CLK_FEED_LH10": null,
"CLK_FEED_LH11": null,
"CLK_FEED_LH12": null,
"CLK_FEED_LH2": null,
"CLK_FEED_LH3": null,
"CLK_FEED_LH4": null,
"CLK_FEED_LH5": null,
"CLK_FEED_LH6": null,
"CLK_FEED_LH7": null,
"CLK_FEED_LH8": null,
"CLK_FEED_LH9": null,
"CLK_FEED_MONITOR_N": null,
"CLK_FEED_MONITOR_P": null,
"CLK_FEED_NE2A0": null,
"CLK_FEED_NE2A1": null,
"CLK_FEED_NE2A2": null,
"CLK_FEED_NE2A3": null,
"CLK_FEED_NE4BEG0": null,
"CLK_FEED_NE4BEG1": null,
"CLK_FEED_NE4BEG2": null,
"CLK_FEED_NE4BEG3": null,
"CLK_FEED_NE4C0": null,
"CLK_FEED_NE4C1": null,
"CLK_FEED_NE4C2": null,
"CLK_FEED_NE4C3": null,
"CLK_FEED_NW2A0": null,
"CLK_FEED_NW2A1": null,
"CLK_FEED_NW2A2": null,
"CLK_FEED_NW2A3": null,
"CLK_FEED_NW4A0": null,
"CLK_FEED_NW4A1": null,
"CLK_FEED_NW4A2": null,
"CLK_FEED_NW4A3": null,
"CLK_FEED_NW4END0": null,
"CLK_FEED_NW4END1": null,
"CLK_FEED_NW4END2": null,
"CLK_FEED_NW4END3": null,
"CLK_FEED_R_CK_BUFG_CASC0": null,
"CLK_FEED_R_CK_BUFG_CASC1": null,
"CLK_FEED_R_CK_BUFG_CASC10": null,
"CLK_FEED_R_CK_BUFG_CASC11": null,
"CLK_FEED_R_CK_BUFG_CASC12": null,
"CLK_FEED_R_CK_BUFG_CASC13": null,
"CLK_FEED_R_CK_BUFG_CASC14": null,
"CLK_FEED_R_CK_BUFG_CASC15": null,
"CLK_FEED_R_CK_BUFG_CASC16": null,
"CLK_FEED_R_CK_BUFG_CASC17": null,
"CLK_FEED_R_CK_BUFG_CASC18": null,
"CLK_FEED_R_CK_BUFG_CASC19": null,
"CLK_FEED_R_CK_BUFG_CASC2": null,
"CLK_FEED_R_CK_BUFG_CASC20": null,
"CLK_FEED_R_CK_BUFG_CASC21": null,
"CLK_FEED_R_CK_BUFG_CASC22": null,
"CLK_FEED_R_CK_BUFG_CASC23": null,
"CLK_FEED_R_CK_BUFG_CASC24": null,
"CLK_FEED_R_CK_BUFG_CASC25": null,
"CLK_FEED_R_CK_BUFG_CASC26": null,
"CLK_FEED_R_CK_BUFG_CASC27": null,
"CLK_FEED_R_CK_BUFG_CASC28": null,
"CLK_FEED_R_CK_BUFG_CASC29": null,
"CLK_FEED_R_CK_BUFG_CASC3": null,
"CLK_FEED_R_CK_BUFG_CASC30": null,
"CLK_FEED_R_CK_BUFG_CASC31": null,
"CLK_FEED_R_CK_BUFG_CASC4": null,
"CLK_FEED_R_CK_BUFG_CASC5": null,
"CLK_FEED_R_CK_BUFG_CASC6": null,
"CLK_FEED_R_CK_BUFG_CASC7": null,
"CLK_FEED_R_CK_BUFG_CASC8": null,
"CLK_FEED_R_CK_BUFG_CASC9": null,
"CLK_FEED_R_CK_GCLK0": null,
"CLK_FEED_R_CK_GCLK1": null,
"CLK_FEED_R_CK_GCLK10": null,
"CLK_FEED_R_CK_GCLK11": null,
"CLK_FEED_R_CK_GCLK12": null,
"CLK_FEED_R_CK_GCLK13": null,
"CLK_FEED_R_CK_GCLK14": null,
"CLK_FEED_R_CK_GCLK15": null,
"CLK_FEED_R_CK_GCLK16": null,
"CLK_FEED_R_CK_GCLK17": null,
"CLK_FEED_R_CK_GCLK18": null,
"CLK_FEED_R_CK_GCLK19": null,
"CLK_FEED_R_CK_GCLK2": null,
"CLK_FEED_R_CK_GCLK20": null,
"CLK_FEED_R_CK_GCLK21": null,
"CLK_FEED_R_CK_GCLK22": null,
"CLK_FEED_R_CK_GCLK23": null,
"CLK_FEED_R_CK_GCLK24": null,
"CLK_FEED_R_CK_GCLK25": null,
"CLK_FEED_R_CK_GCLK26": null,
"CLK_FEED_R_CK_GCLK27": null,
"CLK_FEED_R_CK_GCLK28": null,
"CLK_FEED_R_CK_GCLK29": null,
"CLK_FEED_R_CK_GCLK3": null,
"CLK_FEED_R_CK_GCLK30": null,
"CLK_FEED_R_CK_GCLK31": null,
"CLK_FEED_R_CK_GCLK4": null,
"CLK_FEED_R_CK_GCLK5": null,
"CLK_FEED_R_CK_GCLK6": null,
"CLK_FEED_R_CK_GCLK7": null,
"CLK_FEED_R_CK_GCLK8": null,
"CLK_FEED_R_CK_GCLK9": null,
"CLK_FEED_SE2A0": null,
"CLK_FEED_SE2A1": null,
"CLK_FEED_SE2A2": null,
"CLK_FEED_SE2A3": null,
"CLK_FEED_SE4BEG0": null,
"CLK_FEED_SE4BEG1": null,
"CLK_FEED_SE4BEG2": null,
"CLK_FEED_SE4BEG3": null,
"CLK_FEED_SE4C0": null,
"CLK_FEED_SE4C1": null,
"CLK_FEED_SE4C2": null,
"CLK_FEED_SE4C3": null,
"CLK_FEED_SW2A0": null,
"CLK_FEED_SW2A1": null,
"CLK_FEED_SW2A2": null,
"CLK_FEED_SW2A3": null,
"CLK_FEED_SW4A0": null,
"CLK_FEED_SW4A1": null,
"CLK_FEED_SW4A2": null,
"CLK_FEED_SW4A3": null,
"CLK_FEED_SW4END0": null,
"CLK_FEED_SW4END1": null,
"CLK_FEED_SW4END2": null,
"CLK_FEED_SW4END3": null,
"CLK_FEED_WL1END0": null,
"CLK_FEED_WL1END1": null,
"CLK_FEED_WL1END2": null,
"CLK_FEED_WL1END3": null,
"CLK_FEED_WR1END0": null,
"CLK_FEED_WR1END1": null,
"CLK_FEED_WR1END2": null,
"CLK_FEED_WR1END3": null,
"CLK_FEED_WW2A0": null,
"CLK_FEED_WW2A1": null,
"CLK_FEED_WW2A2": null,
"CLK_FEED_WW2A3": null,
"CLK_FEED_WW2END0": null,
"CLK_FEED_WW2END1": null,
"CLK_FEED_WW2END2": null,
"CLK_FEED_WW2END3": null,
"CLK_FEED_WW4A0": null,
"CLK_FEED_WW4A1": null,
"CLK_FEED_WW4A2": null,
"CLK_FEED_WW4A3": null,
"CLK_FEED_WW4B0": null,
"CLK_FEED_WW4B1": null,
"CLK_FEED_WW4B2": null,
"CLK_FEED_WW4B3": null,
"CLK_FEED_WW4C0": null,
"CLK_FEED_WW4C1": null,
"CLK_FEED_WW4C2": null,
"CLK_FEED_WW4C3": null,
"CLK_FEED_WW4END0": null,
"CLK_FEED_WW4END1": null,
"CLK_FEED_WW4END2": null,
"CLK_FEED_WW4END3": null
}
}

65084
zynq7/tile_type_CLK_HROW_BOT_R.json
View File

File diff suppressed because it is too large Load Diff

65084
zynq7/tile_type_CLK_HROW_TOP_R.json
View File

File diff suppressed because it is too large Load Diff

720
zynq7/tile_type_CLK_MTBF2.json
View File

@ -2,364 +2,364 @@
"pips": {},
"sites": [],
"tile_type": "CLK_MTBF2",
"wires": [
"CLK_FEED_CK_BUFG_CASC0",
"CLK_FEED_CK_BUFG_CASC1",
"CLK_FEED_CK_BUFG_CASC10",
"CLK_FEED_CK_BUFG_CASC11",
"CLK_FEED_CK_BUFG_CASC12",
"CLK_FEED_CK_BUFG_CASC13",
"CLK_FEED_CK_BUFG_CASC14",
"CLK_FEED_CK_BUFG_CASC15",
"CLK_FEED_CK_BUFG_CASC16",
"CLK_FEED_CK_BUFG_CASC17",
"CLK_FEED_CK_BUFG_CASC18",
"CLK_FEED_CK_BUFG_CASC19",
"CLK_FEED_CK_BUFG_CASC2",
"CLK_FEED_CK_BUFG_CASC20",
"CLK_FEED_CK_BUFG_CASC21",
"CLK_FEED_CK_BUFG_CASC22",
"CLK_FEED_CK_BUFG_CASC23",
"CLK_FEED_CK_BUFG_CASC24",
"CLK_FEED_CK_BUFG_CASC25",
"CLK_FEED_CK_BUFG_CASC26",
"CLK_FEED_CK_BUFG_CASC27",
"CLK_FEED_CK_BUFG_CASC28",
"CLK_FEED_CK_BUFG_CASC29",
"CLK_FEED_CK_BUFG_CASC3",
"CLK_FEED_CK_BUFG_CASC30",
"CLK_FEED_CK_BUFG_CASC31",
"CLK_FEED_CK_BUFG_CASC4",
"CLK_FEED_CK_BUFG_CASC5",
"CLK_FEED_CK_BUFG_CASC6",
"CLK_FEED_CK_BUFG_CASC7",
"CLK_FEED_CK_BUFG_CASC8",
"CLK_FEED_CK_BUFG_CASC9",
"CLK_FEED_CK_GCLK0",
"CLK_FEED_CK_GCLK1",
"CLK_FEED_CK_GCLK10",
"CLK_FEED_CK_GCLK11",
"CLK_FEED_CK_GCLK12",
"CLK_FEED_CK_GCLK13",
"CLK_FEED_CK_GCLK14",
"CLK_FEED_CK_GCLK15",
"CLK_FEED_CK_GCLK16",
"CLK_FEED_CK_GCLK17",
"CLK_FEED_CK_GCLK18",
"CLK_FEED_CK_GCLK19",
"CLK_FEED_CK_GCLK2",
"CLK_FEED_CK_GCLK20",
"CLK_FEED_CK_GCLK21",
"CLK_FEED_CK_GCLK22",
"CLK_FEED_CK_GCLK23",
"CLK_FEED_CK_GCLK24",
"CLK_FEED_CK_GCLK25",
"CLK_FEED_CK_GCLK26",
"CLK_FEED_CK_GCLK27",
"CLK_FEED_CK_GCLK28",
"CLK_FEED_CK_GCLK29",
"CLK_FEED_CK_GCLK3",
"CLK_FEED_CK_GCLK30",
"CLK_FEED_CK_GCLK31",
"CLK_FEED_CK_GCLK4",
"CLK_FEED_CK_GCLK5",
"CLK_FEED_CK_GCLK6",
"CLK_FEED_CK_GCLK7",
"CLK_FEED_CK_GCLK8",
"CLK_FEED_CK_GCLK9",
"CLK_FEED_EE2A0",
"CLK_FEED_EE2A1",
"CLK_FEED_EE2A2",
"CLK_FEED_EE2A3",
"CLK_FEED_EE2BEG0",
"CLK_FEED_EE2BEG1",
"CLK_FEED_EE2BEG2",
"CLK_FEED_EE2BEG3",
"CLK_FEED_EE4A0",
"CLK_FEED_EE4A1",
"CLK_FEED_EE4A2",
"CLK_FEED_EE4A3",
"CLK_FEED_EE4B0",
"CLK_FEED_EE4B1",
"CLK_FEED_EE4B2",
"CLK_FEED_EE4B3",
"CLK_FEED_EE4BEG0",
"CLK_FEED_EE4BEG1",
"CLK_FEED_EE4BEG2",
"CLK_FEED_EE4BEG3",
"CLK_FEED_EE4C0",
"CLK_FEED_EE4C1",
"CLK_FEED_EE4C2",
"CLK_FEED_EE4C3",
"CLK_FEED_EL1BEG0",
"CLK_FEED_EL1BEG1",
"CLK_FEED_EL1BEG2",
"CLK_FEED_EL1BEG3",
"CLK_FEED_ER1BEG0",
"CLK_FEED_ER1BEG1",
"CLK_FEED_ER1BEG2",
"CLK_FEED_ER1BEG3",
"CLK_FEED_LH1",
"CLK_FEED_LH10",
"CLK_FEED_LH11",
"CLK_FEED_LH12",
"CLK_FEED_LH2",
"CLK_FEED_LH3",
"CLK_FEED_LH4",
"CLK_FEED_LH5",
"CLK_FEED_LH6",
"CLK_FEED_LH7",
"CLK_FEED_LH8",
"CLK_FEED_LH9",
"CLK_FEED_MONITOR_N",
"CLK_FEED_MONITOR_P",
"CLK_FEED_NE2A0",
"CLK_FEED_NE2A1",
"CLK_FEED_NE2A2",
"CLK_FEED_NE2A3",
"CLK_FEED_NE4BEG0",
"CLK_FEED_NE4BEG1",
"CLK_FEED_NE4BEG2",
"CLK_FEED_NE4BEG3",
"CLK_FEED_NE4C0",
"CLK_FEED_NE4C1",
"CLK_FEED_NE4C2",
"CLK_FEED_NE4C3",
"CLK_FEED_NW2A0",
"CLK_FEED_NW2A1",
"CLK_FEED_NW2A2",
"CLK_FEED_NW2A3",
"CLK_FEED_NW4A0",
"CLK_FEED_NW4A1",
"CLK_FEED_NW4A2",
"CLK_FEED_NW4A3",
"CLK_FEED_NW4END0",
"CLK_FEED_NW4END1",
"CLK_FEED_NW4END2",
"CLK_FEED_NW4END3",
"CLK_FEED_R_CK_BUFG_CASC0",
"CLK_FEED_R_CK_BUFG_CASC1",
"CLK_FEED_R_CK_BUFG_CASC10",
"CLK_FEED_R_CK_BUFG_CASC11",
"CLK_FEED_R_CK_BUFG_CASC12",
"CLK_FEED_R_CK_BUFG_CASC13",
"CLK_FEED_R_CK_BUFG_CASC14",
"CLK_FEED_R_CK_BUFG_CASC15",
"CLK_FEED_R_CK_BUFG_CASC16",
"CLK_FEED_R_CK_BUFG_CASC17",
"CLK_FEED_R_CK_BUFG_CASC18",
"CLK_FEED_R_CK_BUFG_CASC19",
"CLK_FEED_R_CK_BUFG_CASC2",
"CLK_FEED_R_CK_BUFG_CASC20",
"CLK_FEED_R_CK_BUFG_CASC21",
"CLK_FEED_R_CK_BUFG_CASC22",
"CLK_FEED_R_CK_BUFG_CASC23",
"CLK_FEED_R_CK_BUFG_CASC24",
"CLK_FEED_R_CK_BUFG_CASC25",
"CLK_FEED_R_CK_BUFG_CASC26",
"CLK_FEED_R_CK_BUFG_CASC27",
"CLK_FEED_R_CK_BUFG_CASC28",
"CLK_FEED_R_CK_BUFG_CASC29",
"CLK_FEED_R_CK_BUFG_CASC3",
"CLK_FEED_R_CK_BUFG_CASC30",
"CLK_FEED_R_CK_BUFG_CASC31",
"CLK_FEED_R_CK_BUFG_CASC4",
"CLK_FEED_R_CK_BUFG_CASC5",
"CLK_FEED_R_CK_BUFG_CASC6",
"CLK_FEED_R_CK_BUFG_CASC7",
"CLK_FEED_R_CK_BUFG_CASC8",
"CLK_FEED_R_CK_BUFG_CASC9",
"CLK_FEED_R_CK_GCLK0",
"CLK_FEED_R_CK_GCLK1",
"CLK_FEED_R_CK_GCLK10",
"CLK_FEED_R_CK_GCLK11",
"CLK_FEED_R_CK_GCLK12",
"CLK_FEED_R_CK_GCLK13",
"CLK_FEED_R_CK_GCLK14",
"CLK_FEED_R_CK_GCLK15",
"CLK_FEED_R_CK_GCLK16",
"CLK_FEED_R_CK_GCLK17",
"CLK_FEED_R_CK_GCLK18",
"CLK_FEED_R_CK_GCLK19",
"CLK_FEED_R_CK_GCLK2",
"CLK_FEED_R_CK_GCLK20",
"CLK_FEED_R_CK_GCLK21",
"CLK_FEED_R_CK_GCLK22",
"CLK_FEED_R_CK_GCLK23",
"CLK_FEED_R_CK_GCLK24",
"CLK_FEED_R_CK_GCLK25",
"CLK_FEED_R_CK_GCLK26",
"CLK_FEED_R_CK_GCLK27",
"CLK_FEED_R_CK_GCLK28",
"CLK_FEED_R_CK_GCLK29",
"CLK_FEED_R_CK_GCLK3",
"CLK_FEED_R_CK_GCLK30",
"CLK_FEED_R_CK_GCLK31",
"CLK_FEED_R_CK_GCLK4",
"CLK_FEED_R_CK_GCLK5",
"CLK_FEED_R_CK_GCLK6",
"CLK_FEED_R_CK_GCLK7",
"CLK_FEED_R_CK_GCLK8",
"CLK_FEED_R_CK_GCLK9",
"CLK_FEED_SE2A0",
"CLK_FEED_SE2A1",
"CLK_FEED_SE2A2",
"CLK_FEED_SE2A3",
"CLK_FEED_SE4BEG0",
"CLK_FEED_SE4BEG1",
"CLK_FEED_SE4BEG2",
"CLK_FEED_SE4BEG3",
"CLK_FEED_SE4C0",
"CLK_FEED_SE4C1",
"CLK_FEED_SE4C2",
"CLK_FEED_SE4C3",
"CLK_FEED_SW2A0",
"CLK_FEED_SW2A1",
"CLK_FEED_SW2A2",
"CLK_FEED_SW2A3",
"CLK_FEED_SW4A0",
"CLK_FEED_SW4A1",
"CLK_FEED_SW4A2",
"CLK_FEED_SW4A3",
"CLK_FEED_SW4END0",
"CLK_FEED_SW4END1",
"CLK_FEED_SW4END2",
"CLK_FEED_SW4END3",
"CLK_FEED_WL1END0",
"CLK_FEED_WL1END1",
"CLK_FEED_WL1END2",
"CLK_FEED_WL1END3",
"CLK_FEED_WR1END0",
"CLK_FEED_WR1END1",
"CLK_FEED_WR1END2",
"CLK_FEED_WR1END3",
"CLK_FEED_WW2A0",
"CLK_FEED_WW2A1",
"CLK_FEED_WW2A2",
"CLK_FEED_WW2A3",
"CLK_FEED_WW2END0",
"CLK_FEED_WW2END1",
"CLK_FEED_WW2END2",
"CLK_FEED_WW2END3",
"CLK_FEED_WW4A0",
"CLK_FEED_WW4A1",
"CLK_FEED_WW4A2",
"CLK_FEED_WW4A3",
"CLK_FEED_WW4B0",
"CLK_FEED_WW4B1",
"CLK_FEED_WW4B2",
"CLK_FEED_WW4B3",
"CLK_FEED_WW4C0",
"CLK_FEED_WW4C1",
"CLK_FEED_WW4C2",
"CLK_FEED_WW4C3",
"CLK_FEED_WW4END0",
"CLK_FEED_WW4END1",
"CLK_FEED_WW4END2",
"CLK_FEED_WW4END3",
"CLK_MTBF2_CLK",
"CLK_MTBF2_DIN",
"CLK_MTBF2_EN",
"CLK_MTBF2_Q0B",
"CLK_MTBF2_Q1B",
"CLK_MTBF2_Q2B",
"CLK_MTBF2_Q3B",
"CLK_MTBF2_Q4B",
"CLK_MTBF2_Q5B",
"CLK_MTBF2_Q6B",
"CLK_MTBF2_Q7B",
"CLK_MTBF2_RESET",
"CLK_PMV_BYP0_0",
"CLK_PMV_BYP1_0",
"CLK_PMV_BYP2_0",
"CLK_PMV_BYP3_0",
"CLK_PMV_BYP4_0",
"CLK_PMV_BYP5_0",
"CLK_PMV_BYP6_0",
"CLK_PMV_BYP7_0",
"CLK_PMV_CLK0_0",
"CLK_PMV_CLK1_0",
"CLK_PMV_CTRL0_0",
"CLK_PMV_CTRL1_0",
"CLK_PMV_FAN0_0",
"CLK_PMV_FAN1_0",
"CLK_PMV_FAN2_0",
"CLK_PMV_FAN3_0",
"CLK_PMV_FAN4_0",
"CLK_PMV_FAN5_0",
"CLK_PMV_FAN6_0",
"CLK_PMV_FAN7_0",
"CLK_PMV_IMUX0_0",
"CLK_PMV_IMUX10_0",
"CLK_PMV_IMUX11_0",
"CLK_PMV_IMUX12_0",
"CLK_PMV_IMUX13_0",
"CLK_PMV_IMUX14_0",
"CLK_PMV_IMUX15_0",
"CLK_PMV_IMUX16_0",
"CLK_PMV_IMUX17_0",
"CLK_PMV_IMUX18_0",
"CLK_PMV_IMUX19_0",
"CLK_PMV_IMUX1_0",
"CLK_PMV_IMUX20_0",
"CLK_PMV_IMUX21_0",
"CLK_PMV_IMUX22_0",
"CLK_PMV_IMUX23_0",
"CLK_PMV_IMUX24_0",
"CLK_PMV_IMUX25_0",
"CLK_PMV_IMUX26_0",
"CLK_PMV_IMUX27_0",
"CLK_PMV_IMUX28_0",
"CLK_PMV_IMUX29_0",
"CLK_PMV_IMUX2_0",
"CLK_PMV_IMUX30_0",
"CLK_PMV_IMUX31_0",
"CLK_PMV_IMUX32_0",
"CLK_PMV_IMUX33_0",
"CLK_PMV_IMUX34_0",
"CLK_PMV_IMUX35_0",
"CLK_PMV_IMUX36_0",
"CLK_PMV_IMUX37_0",
"CLK_PMV_IMUX38_0",
"CLK_PMV_IMUX39_0",
"CLK_PMV_IMUX3_0",
"CLK_PMV_IMUX40_0",
"CLK_PMV_IMUX41_0",
"CLK_PMV_IMUX42_0",
"CLK_PMV_IMUX43_0",
"CLK_PMV_IMUX44_0",
"CLK_PMV_IMUX45_0",
"CLK_PMV_IMUX46_0",
"CLK_PMV_IMUX47_0",
"CLK_PMV_IMUX4_0",
"CLK_PMV_IMUX5_0",
"CLK_PMV_IMUX6_0",
"CLK_PMV_IMUX7_0",
"CLK_PMV_IMUX8_0",
"CLK_PMV_IMUX9_0",
"CLK_PMV_LOGIC_OUTS0_0",
"CLK_PMV_LOGIC_OUTS10_0",
"CLK_PMV_LOGIC_OUTS11_0",
"CLK_PMV_LOGIC_OUTS12_0",
"CLK_PMV_LOGIC_OUTS13_0",
"CLK_PMV_LOGIC_OUTS14_0",
"CLK_PMV_LOGIC_OUTS15_0",
"CLK_PMV_LOGIC_OUTS16_0",
"CLK_PMV_LOGIC_OUTS17_0",
"CLK_PMV_LOGIC_OUTS18_0",
"CLK_PMV_LOGIC_OUTS19_0",
"CLK_PMV_LOGIC_OUTS1_0",
"CLK_PMV_LOGIC_OUTS20_0",
"CLK_PMV_LOGIC_OUTS21_0",
"CLK_PMV_LOGIC_OUTS22_0",
"CLK_PMV_LOGIC_OUTS23_0",
"CLK_PMV_LOGIC_OUTS2_0",
"CLK_PMV_LOGIC_OUTS3_0",
"CLK_PMV_LOGIC_OUTS4_0",
"CLK_PMV_LOGIC_OUTS5_0",
"CLK_PMV_LOGIC_OUTS6_0",
"CLK_PMV_LOGIC_OUTS7_0",
"CLK_PMV_LOGIC_OUTS8_0",
"CLK_PMV_LOGIC_OUTS9_0"
]
"wires": {
"CLK_FEED_CK_BUFG_CASC0": null,
"CLK_FEED_CK_BUFG_CASC1": null,
"CLK_FEED_CK_BUFG_CASC10": null,
"CLK_FEED_CK_BUFG_CASC11": null,
"CLK_FEED_CK_BUFG_CASC12": null,
"CLK_FEED_CK_BUFG_CASC13": null,
"CLK_FEED_CK_BUFG_CASC14": null,
"CLK_FEED_CK_BUFG_CASC15": null,
"CLK_FEED_CK_BUFG_CASC16": null,
"CLK_FEED_CK_BUFG_CASC17": null,
"CLK_FEED_CK_BUFG_CASC18": null,
"CLK_FEED_CK_BUFG_CASC19": null,
"CLK_FEED_CK_BUFG_CASC2": null,
"CLK_FEED_CK_BUFG_CASC20": null,
"CLK_FEED_CK_BUFG_CASC21": null,
"CLK_FEED_CK_BUFG_CASC22": null,
"CLK_FEED_CK_BUFG_CASC23": null,
"CLK_FEED_CK_BUFG_CASC24": null,
"CLK_FEED_CK_BUFG_CASC25": null,
"CLK_FEED_CK_BUFG_CASC26": null,
"CLK_FEED_CK_BUFG_CASC27": null,
"CLK_FEED_CK_BUFG_CASC28": null,
"CLK_FEED_CK_BUFG_CASC29": null,
"CLK_FEED_CK_BUFG_CASC3": null,
"CLK_FEED_CK_BUFG_CASC30": null,
"CLK_FEED_CK_BUFG_CASC31": null,
"CLK_FEED_CK_BUFG_CASC4": null,
"CLK_FEED_CK_BUFG_CASC5": null,
"CLK_FEED_CK_BUFG_CASC6": null,
"CLK_FEED_CK_BUFG_CASC7": null,
"CLK_FEED_CK_BUFG_CASC8": null,
"CLK_FEED_CK_BUFG_CASC9": null,
"CLK_FEED_CK_GCLK0": null,
"CLK_FEED_CK_GCLK1": null,
"CLK_FEED_CK_GCLK10": null,
"CLK_FEED_CK_GCLK11": null,
"CLK_FEED_CK_GCLK12": null,
"CLK_FEED_CK_GCLK13": null,
"CLK_FEED_CK_GCLK14": null,
"CLK_FEED_CK_GCLK15": null,
"CLK_FEED_CK_GCLK16": null,
"CLK_FEED_CK_GCLK17": null,
"CLK_FEED_CK_GCLK18": null,
"CLK_FEED_CK_GCLK19": null,
"CLK_FEED_CK_GCLK2": null,
"CLK_FEED_CK_GCLK20": null,
"CLK_FEED_CK_GCLK21": null,
"CLK_FEED_CK_GCLK22": null,
"CLK_FEED_CK_GCLK23": null,
"CLK_FEED_CK_GCLK24": null,
"CLK_FEED_CK_GCLK25": null,
"CLK_FEED_CK_GCLK26": null,
"CLK_FEED_CK_GCLK27": null,
"CLK_FEED_CK_GCLK28": null,
"CLK_FEED_CK_GCLK29": null,
"CLK_FEED_CK_GCLK3": null,
"CLK_FEED_CK_GCLK30": null,
"CLK_FEED_CK_GCLK31": null,
"CLK_FEED_CK_GCLK4": null,
"CLK_FEED_CK_GCLK5": null,
"CLK_FEED_CK_GCLK6": null,
"CLK_FEED_CK_GCLK7": null,
"CLK_FEED_CK_GCLK8": null,
"CLK_FEED_CK_GCLK9": null,
"CLK_FEED_EE2A0": null,
"CLK_FEED_EE2A1": null,
"CLK_FEED_EE2A2": null,
"CLK_FEED_EE2A3": null,
"CLK_FEED_EE2BEG0": null,
"CLK_FEED_EE2BEG1": null,
"CLK_FEED_EE2BEG2": null,
"CLK_FEED_EE2BEG3": null,
"CLK_FEED_EE4A0": null,
"CLK_FEED_EE4A1": null,
"CLK_FEED_EE4A2": null,
"CLK_FEED_EE4A3": null,
"CLK_FEED_EE4B0": null,
"CLK_FEED_EE4B1": null,
"CLK_FEED_EE4B2": null,
"CLK_FEED_EE4B3": null,
"CLK_FEED_EE4BEG0": null,
"CLK_FEED_EE4BEG1": null,
"CLK_FEED_EE4BEG2": null,
"CLK_FEED_EE4BEG3": null,
"CLK_FEED_EE4C0": null,
"CLK_FEED_EE4C1": null,
"CLK_FEED_EE4C2": null,
"CLK_FEED_EE4C3": null,
"CLK_FEED_EL1BEG0": null,
"CLK_FEED_EL1BEG1": null,
"CLK_FEED_EL1BEG2": null,
"CLK_FEED_EL1BEG3": null,
"CLK_FEED_ER1BEG0": null,
"CLK_FEED_ER1BEG1": null,
"CLK_FEED_ER1BEG2": null,
"CLK_FEED_ER1BEG3": null,
"CLK_FEED_LH1": null,
"CLK_FEED_LH10": null,
"CLK_FEED_LH11": null,
"CLK_FEED_LH12": null,
"CLK_FEED_LH2": null,
"CLK_FEED_LH3": null,
"CLK_FEED_LH4": null,
"CLK_FEED_LH5": null,
"CLK_FEED_LH6": null,
"CLK_FEED_LH7": null,
"CLK_FEED_LH8": null,
"CLK_FEED_LH9": null,
"CLK_FEED_MONITOR_N": null,
"CLK_FEED_MONITOR_P": null,
"CLK_FEED_NE2A0": null,
"CLK_FEED_NE2A1": null,
"CLK_FEED_NE2A2": null,
"CLK_FEED_NE2A3": null,
"CLK_FEED_NE4BEG0": null,
"CLK_FEED_NE4BEG1": null,
"CLK_FEED_NE4BEG2": null,
"CLK_FEED_NE4BEG3": null,
"CLK_FEED_NE4C0": null,
"CLK_FEED_NE4C1": null,
"CLK_FEED_NE4C2": null,
"CLK_FEED_NE4C3": null,
"CLK_FEED_NW2A0": null,
"CLK_FEED_NW2A1": null,
"CLK_FEED_NW2A2": null,
"CLK_FEED_NW2A3": null,
"CLK_FEED_NW4A0": null,
"CLK_FEED_NW4A1": null,
"CLK_FEED_NW4A2": null,
"CLK_FEED_NW4A3": null,
"CLK_FEED_NW4END0": null,
"CLK_FEED_NW4END1": null,
"CLK_FEED_NW4END2": null,
"CLK_FEED_NW4END3": null,
"CLK_FEED_R_CK_BUFG_CASC0": null,
"CLK_FEED_R_CK_BUFG_CASC1": null,
"CLK_FEED_R_CK_BUFG_CASC10": null,
"CLK_FEED_R_CK_BUFG_CASC11": null,
"CLK_FEED_R_CK_BUFG_CASC12": null,
"CLK_FEED_R_CK_BUFG_CASC13": null,
"CLK_FEED_R_CK_BUFG_CASC14": null,
"CLK_FEED_R_CK_BUFG_CASC15": null,
"CLK_FEED_R_CK_BUFG_CASC16": null,
"CLK_FEED_R_CK_BUFG_CASC17": null,
"CLK_FEED_R_CK_BUFG_CASC18": null,
"CLK_FEED_R_CK_BUFG_CASC19": null,
"CLK_FEED_R_CK_BUFG_CASC2": null,
"CLK_FEED_R_CK_BUFG_CASC20": null,
"CLK_FEED_R_CK_BUFG_CASC21": null,
"CLK_FEED_R_CK_BUFG_CASC22": null,
"CLK_FEED_R_CK_BUFG_CASC23": null,
"CLK_FEED_R_CK_BUFG_CASC24": null,
"CLK_FEED_R_CK_BUFG_CASC25": null,
"CLK_FEED_R_CK_BUFG_CASC26": null,
"CLK_FEED_R_CK_BUFG_CASC27": null,
"CLK_FEED_R_CK_BUFG_CASC28": null,
"CLK_FEED_R_CK_BUFG_CASC29": null,
"CLK_FEED_R_CK_BUFG_CASC3": null,
"CLK_FEED_R_CK_BUFG_CASC30": null,
"CLK_FEED_R_CK_BUFG_CASC31": null,
"CLK_FEED_R_CK_BUFG_CASC4": null,
"CLK_FEED_R_CK_BUFG_CASC5": null,
"CLK_FEED_R_CK_BUFG_CASC6": null,
"CLK_FEED_R_CK_BUFG_CASC7": null,
"CLK_FEED_R_CK_BUFG_CASC8": null,
"CLK_FEED_R_CK_BUFG_CASC9": null,
"CLK_FEED_R_CK_GCLK0": null,
"CLK_FEED_R_CK_GCLK1": null,
"CLK_FEED_R_CK_GCLK10": null,
"CLK_FEED_R_CK_GCLK11": null,
"CLK_FEED_R_CK_GCLK12": null,
"CLK_FEED_R_CK_GCLK13": null,
"CLK_FEED_R_CK_GCLK14": null,
"CLK_FEED_R_CK_GCLK15": null,
"CLK_FEED_R_CK_GCLK16": null,
"CLK_FEED_R_CK_GCLK17": null,
"CLK_FEED_R_CK_GCLK18": null,
"CLK_FEED_R_CK_GCLK19": null,
"CLK_FEED_R_CK_GCLK2": null,
"CLK_FEED_R_CK_GCLK20": null,
"CLK_FEED_R_CK_GCLK21": null,
"CLK_FEED_R_CK_GCLK22": null,
"CLK_FEED_R_CK_GCLK23": null,
"CLK_FEED_R_CK_GCLK24": null,
"CLK_FEED_R_CK_GCLK25": null,
"CLK_FEED_R_CK_GCLK26": null,
"CLK_FEED_R_CK_GCLK27": null,
"CLK_FEED_R_CK_GCLK28": null,
"CLK_FEED_R_CK_GCLK29": null,
"CLK_FEED_R_CK_GCLK3": null,
"CLK_FEED_R_CK_GCLK30": null,
"CLK_FEED_R_CK_GCLK31": null,
"CLK_FEED_R_CK_GCLK4": null,
"CLK_FEED_R_CK_GCLK5": null,
"CLK_FEED_R_CK_GCLK6": null,
"CLK_FEED_R_CK_GCLK7": null,
"CLK_FEED_R_CK_GCLK8": null,
"CLK_FEED_R_CK_GCLK9": null,
"CLK_FEED_SE2A0": null,
"CLK_FEED_SE2A1": null,
"CLK_FEED_SE2A2": null,
"CLK_FEED_SE2A3": null,
"CLK_FEED_SE4BEG0": null,
"CLK_FEED_SE4BEG1": null,
"CLK_FEED_SE4BEG2": null,
"CLK_FEED_SE4BEG3": null,
"CLK_FEED_SE4C0": null,
"CLK_FEED_SE4C1": null,
"CLK_FEED_SE4C2": null,
"CLK_FEED_SE4C3": null,
"CLK_FEED_SW2A0": null,
"CLK_FEED_SW2A1": null,
"CLK_FEED_SW2A2": null,
"CLK_FEED_SW2A3": null,
"CLK_FEED_SW4A0": null,
"CLK_FEED_SW4A1": null,
"CLK_FEED_SW4A2": null,
"CLK_FEED_SW4A3": null,
"CLK_FEED_SW4END0": null,
"CLK_FEED_SW4END1": null,
"CLK_FEED_SW4END2": null,
"CLK_FEED_SW4END3": null,
"CLK_FEED_WL1END0": null,
"CLK_FEED_WL1END1": null,
"CLK_FEED_WL1END2": null,
"CLK_FEED_WL1END3": null,
"CLK_FEED_WR1END0": null,
"CLK_FEED_WR1END1": null,
"CLK_FEED_WR1END2": null,
"CLK_FEED_WR1END3": null,
"CLK_FEED_WW2A0": null,
"CLK_FEED_WW2A1": null,
"CLK_FEED_WW2A2": null,
"CLK_FEED_WW2A3": null,
"CLK_FEED_WW2END0": null,
"CLK_FEED_WW2END1": null,
"CLK_FEED_WW2END2": null,
"CLK_FEED_WW2END3": null,
"CLK_FEED_WW4A0": null,
"CLK_FEED_WW4A1": null,
"CLK_FEED_WW4A2": null,
"CLK_FEED_WW4A3": null,
"CLK_FEED_WW4B0": null,
"CLK_FEED_WW4B1": null,
"CLK_FEED_WW4B2": null,
"CLK_FEED_WW4B3": null,
"CLK_FEED_WW4C0": null,
"CLK_FEED_WW4C1": null,
"CLK_FEED_WW4C2": null,
"CLK_FEED_WW4C3": null,
"CLK_FEED_WW4END0": null,
"CLK_FEED_WW4END1": null,
"CLK_FEED_WW4END2": null,
"CLK_FEED_WW4END3": null,
"CLK_MTBF2_CLK": null,
"CLK_MTBF2_DIN": null,
"CLK_MTBF2_EN": null,
"CLK_MTBF2_Q0B": null,
"CLK_MTBF2_Q1B": null,
"CLK_MTBF2_Q2B": null,
"CLK_MTBF2_Q3B": null,
"CLK_MTBF2_Q4B": null,
"CLK_MTBF2_Q5B": null,
"CLK_MTBF2_Q6B": null,
"CLK_MTBF2_Q7B": null,
"CLK_MTBF2_RESET": null,
"CLK_PMV_BYP0_0": null,
"CLK_PMV_BYP1_0": null,
"CLK_PMV_BYP2_0": null,
"CLK_PMV_BYP3_0": null,
"CLK_PMV_BYP4_0": null,
"CLK_PMV_BYP5_0": null,
"CLK_PMV_BYP6_0": null,
"CLK_PMV_BYP7_0": null,
"CLK_PMV_CLK0_0": null,
"CLK_PMV_CLK1_0": null,
"CLK_PMV_CTRL0_0": null,
"CLK_PMV_CTRL1_0": null,
"CLK_PMV_FAN0_0": null,
"CLK_PMV_FAN1_0": null,
"CLK_PMV_FAN2_0": null,
"CLK_PMV_FAN3_0": null,
"CLK_PMV_FAN4_0": null,
"CLK_PMV_FAN5_0": null,
"CLK_PMV_FAN6_0": null,
"CLK_PMV_FAN7_0": null,
"CLK_PMV_IMUX0_0": null,
"CLK_PMV_IMUX10_0": null,
"CLK_PMV_IMUX11_0": null,
"CLK_PMV_IMUX12_0": null,
"CLK_PMV_IMUX13_0": null,
"CLK_PMV_IMUX14_0": null,
"CLK_PMV_IMUX15_0": null,
"CLK_PMV_IMUX16_0": null,
"CLK_PMV_IMUX17_0": null,
"CLK_PMV_IMUX18_0": null,
"CLK_PMV_IMUX19_0": null,
"CLK_PMV_IMUX1_0": null,
"CLK_PMV_IMUX20_0": null,
"CLK_PMV_IMUX21_0": null,
"CLK_PMV_IMUX22_0": null,
"CLK_PMV_IMUX23_0": null,
"CLK_PMV_IMUX24_0": null,
"CLK_PMV_IMUX25_0": null,
"CLK_PMV_IMUX26_0": null,
"CLK_PMV_IMUX27_0": null,
"CLK_PMV_IMUX28_0": null,
"CLK_PMV_IMUX29_0": null,
"CLK_PMV_IMUX2_0": null,
"CLK_PMV_IMUX30_0": null,
"CLK_PMV_IMUX31_0": null,
"CLK_PMV_IMUX32_0": null,
"CLK_PMV_IMUX33_0": null,
"CLK_PMV_IMUX34_0": null,
"CLK_PMV_IMUX35_0": null,
"CLK_PMV_IMUX36_0": null,
"CLK_PMV_IMUX37_0": null,
"CLK_PMV_IMUX38_0": null,
"CLK_PMV_IMUX39_0": null,
"CLK_PMV_IMUX3_0": null,
"CLK_PMV_IMUX40_0": null,
"CLK_PMV_IMUX41_0": null,
"CLK_PMV_IMUX42_0": null,
"CLK_PMV_IMUX43_0": null,
"CLK_PMV_IMUX44_0": null,
"CLK_PMV_IMUX45_0": null,
"CLK_PMV_IMUX46_0": null,
"CLK_PMV_IMUX47_0": null,
"CLK_PMV_IMUX4_0": null,
"CLK_PMV_IMUX5_0": null,
"CLK_PMV_IMUX6_0": null,
"CLK_PMV_IMUX7_0": null,
"CLK_PMV_IMUX8_0": null,
"CLK_PMV_IMUX9_0": null,
"CLK_PMV_LOGIC_OUTS0_0": null,
"CLK_PMV_LOGIC_OUTS10_0": null,
"CLK_PMV_LOGIC_OUTS11_0": null,
"CLK_PMV_LOGIC_OUTS12_0": null,
"CLK_PMV_LOGIC_OUTS13_0": null,
"CLK_PMV_LOGIC_OUTS14_0": null,
"CLK_PMV_LOGIC_OUTS15_0": null,
"CLK_PMV_LOGIC_OUTS16_0": null,
"CLK_PMV_LOGIC_OUTS17_0": null,
"CLK_PMV_LOGIC_OUTS18_0": null,
"CLK_PMV_LOGIC_OUTS19_0": null,
"CLK_PMV_LOGIC_OUTS1_0": null,
"CLK_PMV_LOGIC_OUTS20_0": null,
"CLK_PMV_LOGIC_OUTS21_0": null,
"CLK_PMV_LOGIC_OUTS22_0": null,
"CLK_PMV_LOGIC_OUTS23_0": null,
"CLK_PMV_LOGIC_OUTS2_0": null,
"CLK_PMV_LOGIC_OUTS3_0": null,
"CLK_PMV_LOGIC_OUTS4_0": null,
"CLK_PMV_LOGIC_OUTS5_0": null,
"CLK_PMV_LOGIC_OUTS6_0": null,
"CLK_PMV_LOGIC_OUTS7_0": null,
"CLK_PMV_LOGIC_OUTS8_0": null,
"CLK_PMV_LOGIC_OUTS9_0": null
}
}

3332
zynq7/tile_type_CLK_PMV.json
View File

File diff suppressed because it is too large Load Diff

787
zynq7/tile_type_CLK_PMV2.json
View File

@ -5,13 +5,76 @@
"name": "X0Y0",
"prefix": "PMV",
"site_pins": {
"A0": "CLK_PMV2_A0",
"A1": "CLK_PMV2_A1",
"A2": "CLK_PMV2_A2",
"EN": "CLK_PMV2_EN",
"O": "CLK_PMV2_O",
"ODIV2": "CLK_PMV2_ODIV2",
"ODIV4": "CLK_PMV2_ODIV4"
"A0": {
"cap": "0.000",
"delay": [
"0.000",
"0.000",
"0.000",
"0.000"
],
"wire": "CLK_PMV2_A0"
},
"A1": {
"cap": "0.000",
"delay": [
"0.000",
"0.000",
"0.000",
"0.000"
],
"wire": "CLK_PMV2_A1"
},
"A2": {
"cap": "0.000",
"delay": [
"0.000",
"0.000",
"0.000",
"0.000"
],
"wire": "CLK_PMV2_A2"
},
"EN": {
"cap": "0.000",
"delay": [
"0.000",
"0.000",
"0.000",
"0.000"
],
"wire": "CLK_PMV2_EN"
},
"O": {
"delay": [
"0.000",
"0.000",
"0.000",
"0.000"
],
"res": "0.0",
"wire": "CLK_PMV2_O"
},
"ODIV2": {
"delay": [
"0.000",
"0.000",
"0.000",
"0.000"
],
"res": "0.0",
"wire": "CLK_PMV2_ODIV2"
},
"ODIV4": {
"delay": [
"0.000",
"0.000",
"0.000",
"0.000"
],
"res": "0.0",
"wire": "CLK_PMV2_ODIV4"
}
},
"type": "PMV2",
"x_coord": 0,
@ -19,359 +82,359 @@
}
],
"tile_type": "CLK_PMV2",
"wires": [
"CLK_FEED_CK_BUFG_CASC0",
"CLK_FEED_CK_BUFG_CASC1",
"CLK_FEED_CK_BUFG_CASC10",
"CLK_FEED_CK_BUFG_CASC11",
"CLK_FEED_CK_BUFG_CASC12",
"CLK_FEED_CK_BUFG_CASC13",
"CLK_FEED_CK_BUFG_CASC14",
"CLK_FEED_CK_BUFG_CASC15",
"CLK_FEED_CK_BUFG_CASC16",
"CLK_FEED_CK_BUFG_CASC17",
"CLK_FEED_CK_BUFG_CASC18",
"CLK_FEED_CK_BUFG_CASC19",
"CLK_FEED_CK_BUFG_CASC2",
"CLK_FEED_CK_BUFG_CASC20",
"CLK_FEED_CK_BUFG_CASC21",
"CLK_FEED_CK_BUFG_CASC22",
"CLK_FEED_CK_BUFG_CASC23",
"CLK_FEED_CK_BUFG_CASC24",
"CLK_FEED_CK_BUFG_CASC25",
"CLK_FEED_CK_BUFG_CASC26",
"CLK_FEED_CK_BUFG_CASC27",
"CLK_FEED_CK_BUFG_CASC28",
"CLK_FEED_CK_BUFG_CASC29",
"CLK_FEED_CK_BUFG_CASC3",
"CLK_FEED_CK_BUFG_CASC30",
"CLK_FEED_CK_BUFG_CASC31",
"CLK_FEED_CK_BUFG_CASC4",
"CLK_FEED_CK_BUFG_CASC5",
"CLK_FEED_CK_BUFG_CASC6",
"CLK_FEED_CK_BUFG_CASC7",
"CLK_FEED_CK_BUFG_CASC8",
"CLK_FEED_CK_BUFG_CASC9",
"CLK_FEED_CK_GCLK0",
"CLK_FEED_CK_GCLK1",
"CLK_FEED_CK_GCLK10",
"CLK_FEED_CK_GCLK11",
"CLK_FEED_CK_GCLK12",
"CLK_FEED_CK_GCLK13",
"CLK_FEED_CK_GCLK14",
"CLK_FEED_CK_GCLK15",
"CLK_FEED_CK_GCLK16",
"CLK_FEED_CK_GCLK17",
"CLK_FEED_CK_GCLK18",
"CLK_FEED_CK_GCLK19",
"CLK_FEED_CK_GCLK2",
"CLK_FEED_CK_GCLK20",
"CLK_FEED_CK_GCLK21",
"CLK_FEED_CK_GCLK22",
"CLK_FEED_CK_GCLK23",
"CLK_FEED_CK_GCLK24",
"CLK_FEED_CK_GCLK25",
"CLK_FEED_CK_GCLK26",
"CLK_FEED_CK_GCLK27",
"CLK_FEED_CK_GCLK28",
"CLK_FEED_CK_GCLK29",
"CLK_FEED_CK_GCLK3",
"CLK_FEED_CK_GCLK30",
"CLK_FEED_CK_GCLK31",
"CLK_FEED_CK_GCLK4",
"CLK_FEED_CK_GCLK5",
"CLK_FEED_CK_GCLK6",
"CLK_FEED_CK_GCLK7",
"CLK_FEED_CK_GCLK8",
"CLK_FEED_CK_GCLK9",
"CLK_FEED_EE2A0",
"CLK_FEED_EE2A1",
"CLK_FEED_EE2A2",
"CLK_FEED_EE2A3",
"CLK_FEED_EE2BEG0",
"CLK_FEED_EE2BEG1",
"CLK_FEED_EE2BEG2",
"CLK_FEED_EE2BEG3",
"CLK_FEED_EE4A0",
"CLK_FEED_EE4A1",
"CLK_FEED_EE4A2",
"CLK_FEED_EE4A3",
"CLK_FEED_EE4B0",
"CLK_FEED_EE4B1",
"CLK_FEED_EE4B2",
"CLK_FEED_EE4B3",
"CLK_FEED_EE4BEG0",
"CLK_FEED_EE4BEG1",
"CLK_FEED_EE4BEG2",
"CLK_FEED_EE4BEG3",
"CLK_FEED_EE4C0",
"CLK_FEED_EE4C1",
"CLK_FEED_EE4C2",
"CLK_FEED_EE4C3",
"CLK_FEED_EL1BEG0",
"CLK_FEED_EL1BEG1",
"CLK_FEED_EL1BEG2",
"CLK_FEED_EL1BEG3",
"CLK_FEED_ER1BEG0",
"CLK_FEED_ER1BEG1",
"CLK_FEED_ER1BEG2",
"CLK_FEED_ER1BEG3",
"CLK_FEED_LH1",
"CLK_FEED_LH10",
"CLK_FEED_LH11",
"CLK_FEED_LH12",
"CLK_FEED_LH2",
"CLK_FEED_LH3",
"CLK_FEED_LH4",
"CLK_FEED_LH5",
"CLK_FEED_LH6",
"CLK_FEED_LH7",
"CLK_FEED_LH8",
"CLK_FEED_LH9",
"CLK_FEED_MONITOR_N",
"CLK_FEED_MONITOR_P",
"CLK_FEED_NE2A0",
"CLK_FEED_NE2A1",
"CLK_FEED_NE2A2",
"CLK_FEED_NE2A3",
"CLK_FEED_NE4BEG0",
"CLK_FEED_NE4BEG1",
"CLK_FEED_NE4BEG2",
"CLK_FEED_NE4BEG3",
"CLK_FEED_NE4C0",
"CLK_FEED_NE4C1",
"CLK_FEED_NE4C2",
"CLK_FEED_NE4C3",
"CLK_FEED_NW2A0",
"CLK_FEED_NW2A1",
"CLK_FEED_NW2A2",
"CLK_FEED_NW2A3",
"CLK_FEED_NW4A0",
"CLK_FEED_NW4A1",
"CLK_FEED_NW4A2",
"CLK_FEED_NW4A3",
"CLK_FEED_NW4END0",
"CLK_FEED_NW4END1",
"CLK_FEED_NW4END2",
"CLK_FEED_NW4END3",
"CLK_FEED_R_CK_BUFG_CASC0",
"CLK_FEED_R_CK_BUFG_CASC1",
"CLK_FEED_R_CK_BUFG_CASC10",
"CLK_FEED_R_CK_BUFG_CASC11",
"CLK_FEED_R_CK_BUFG_CASC12",
"CLK_FEED_R_CK_BUFG_CASC13",
"CLK_FEED_R_CK_BUFG_CASC14",
"CLK_FEED_R_CK_BUFG_CASC15",
"CLK_FEED_R_CK_BUFG_CASC16",
"CLK_FEED_R_CK_BUFG_CASC17",
"CLK_FEED_R_CK_BUFG_CASC18",
"CLK_FEED_R_CK_BUFG_CASC19",
"CLK_FEED_R_CK_BUFG_CASC2",
"CLK_FEED_R_CK_BUFG_CASC20",
"CLK_FEED_R_CK_BUFG_CASC21",
"CLK_FEED_R_CK_BUFG_CASC22",
"CLK_FEED_R_CK_BUFG_CASC23",
"CLK_FEED_R_CK_BUFG_CASC24",
"CLK_FEED_R_CK_BUFG_CASC25",
"CLK_FEED_R_CK_BUFG_CASC26",
"CLK_FEED_R_CK_BUFG_CASC27",
"CLK_FEED_R_CK_BUFG_CASC28",
"CLK_FEED_R_CK_BUFG_CASC29",
"CLK_FEED_R_CK_BUFG_CASC3",
"CLK_FEED_R_CK_BUFG_CASC30",
"CLK_FEED_R_CK_BUFG_CASC31",
"CLK_FEED_R_CK_BUFG_CASC4",
"CLK_FEED_R_CK_BUFG_CASC5",
"CLK_FEED_R_CK_BUFG_CASC6",
"CLK_FEED_R_CK_BUFG_CASC7",
"CLK_FEED_R_CK_BUFG_CASC8",
"CLK_FEED_R_CK_BUFG_CASC9",
"CLK_FEED_R_CK_GCLK0",
"CLK_FEED_R_CK_GCLK1",
"CLK_FEED_R_CK_GCLK10",
"CLK_FEED_R_CK_GCLK11",
"CLK_FEED_R_CK_GCLK12",
"CLK_FEED_R_CK_GCLK13",
"CLK_FEED_R_CK_GCLK14",
"CLK_FEED_R_CK_GCLK15",
"CLK_FEED_R_CK_GCLK16",
"CLK_FEED_R_CK_GCLK17",
"CLK_FEED_R_CK_GCLK18",
"CLK_FEED_R_CK_GCLK19",
"CLK_FEED_R_CK_GCLK2",
"CLK_FEED_R_CK_GCLK20",
"CLK_FEED_R_CK_GCLK21",
"CLK_FEED_R_CK_GCLK22",
"CLK_FEED_R_CK_GCLK23",
"CLK_FEED_R_CK_GCLK24",
"CLK_FEED_R_CK_GCLK25",
"CLK_FEED_R_CK_GCLK26",
"CLK_FEED_R_CK_GCLK27",
"CLK_FEED_R_CK_GCLK28",
"CLK_FEED_R_CK_GCLK29",
"CLK_FEED_R_CK_GCLK3",
"CLK_FEED_R_CK_GCLK30",
"CLK_FEED_R_CK_GCLK31",
"CLK_FEED_R_CK_GCLK4",
"CLK_FEED_R_CK_GCLK5",
"CLK_FEED_R_CK_GCLK6",
"CLK_FEED_R_CK_GCLK7",
"CLK_FEED_R_CK_GCLK8",
"CLK_FEED_R_CK_GCLK9",
"CLK_FEED_SE2A0",
"CLK_FEED_SE2A1",
"CLK_FEED_SE2A2",
"CLK_FEED_SE2A3",
"CLK_FEED_SE4BEG0",
"CLK_FEED_SE4BEG1",
"CLK_FEED_SE4BEG2",
"CLK_FEED_SE4BEG3",
"CLK_FEED_SE4C0",
"CLK_FEED_SE4C1",
"CLK_FEED_SE4C2",
"CLK_FEED_SE4C3",
"CLK_FEED_SW2A0",
"CLK_FEED_SW2A1",
"CLK_FEED_SW2A2",
"CLK_FEED_SW2A3",
"CLK_FEED_SW4A0",
"CLK_FEED_SW4A1",
"CLK_FEED_SW4A2",
"CLK_FEED_SW4A3",
"CLK_FEED_SW4END0",
"CLK_FEED_SW4END1",
"CLK_FEED_SW4END2",
"CLK_FEED_SW4END3",
"CLK_FEED_WL1END0",
"CLK_FEED_WL1END1",
"CLK_FEED_WL1END2",
"CLK_FEED_WL1END3",
"CLK_FEED_WR1END0",
"CLK_FEED_WR1END1",
"CLK_FEED_WR1END2",
"CLK_FEED_WR1END3",
"CLK_FEED_WW2A0",
"CLK_FEED_WW2A1",
"CLK_FEED_WW2A2",
"CLK_FEED_WW2A3",
"CLK_FEED_WW2END0",
"CLK_FEED_WW2END1",
"CLK_FEED_WW2END2",
"CLK_FEED_WW2END3",
"CLK_FEED_WW4A0",
"CLK_FEED_WW4A1",
"CLK_FEED_WW4A2",
"CLK_FEED_WW4A3",
"CLK_FEED_WW4B0",
"CLK_FEED_WW4B1",
"CLK_FEED_WW4B2",
"CLK_FEED_WW4B3",
"CLK_FEED_WW4C0",
"CLK_FEED_WW4C1",
"CLK_FEED_WW4C2",
"CLK_FEED_WW4C3",
"CLK_FEED_WW4END0",
"CLK_FEED_WW4END1",
"CLK_FEED_WW4END2",
"CLK_FEED_WW4END3",
"CLK_PMV2_A0",
"CLK_PMV2_A1",
"CLK_PMV2_A2",
"CLK_PMV2_EN",
"CLK_PMV2_O",
"CLK_PMV2_ODIV2",
"CLK_PMV2_ODIV4",
"CLK_PMV_BYP0_0",
"CLK_PMV_BYP1_0",
"CLK_PMV_BYP2_0",
"CLK_PMV_BYP3_0",
"CLK_PMV_BYP4_0",
"CLK_PMV_BYP5_0",
"CLK_PMV_BYP6_0",
"CLK_PMV_BYP7_0",
"CLK_PMV_CLK0_0",
"CLK_PMV_CLK1_0",
"CLK_PMV_CTRL0_0",
"CLK_PMV_CTRL1_0",
"CLK_PMV_FAN0_0",
"CLK_PMV_FAN1_0",
"CLK_PMV_FAN2_0",
"CLK_PMV_FAN3_0",
"CLK_PMV_FAN4_0",
"CLK_PMV_FAN5_0",
"CLK_PMV_FAN6_0",
"CLK_PMV_FAN7_0",
"CLK_PMV_IMUX0_0",
"CLK_PMV_IMUX10_0",
"CLK_PMV_IMUX11_0",
"CLK_PMV_IMUX12_0",
"CLK_PMV_IMUX13_0",
"CLK_PMV_IMUX14_0",
"CLK_PMV_IMUX15_0",
"CLK_PMV_IMUX16_0",
"CLK_PMV_IMUX17_0",
"CLK_PMV_IMUX18_0",
"CLK_PMV_IMUX19_0",
"CLK_PMV_IMUX1_0",
"CLK_PMV_IMUX20_0",
"CLK_PMV_IMUX21_0",
"CLK_PMV_IMUX22_0",
"CLK_PMV_IMUX23_0",
"CLK_PMV_IMUX24_0",
"CLK_PMV_IMUX25_0",
"CLK_PMV_IMUX26_0",
"CLK_PMV_IMUX27_0",
"CLK_PMV_IMUX28_0",
"CLK_PMV_IMUX29_0",
"CLK_PMV_IMUX2_0",
"CLK_PMV_IMUX30_0",
"CLK_PMV_IMUX31_0",
"CLK_PMV_IMUX32_0",
"CLK_PMV_IMUX33_0",
"CLK_PMV_IMUX34_0",
"CLK_PMV_IMUX35_0",
"CLK_PMV_IMUX36_0",
"CLK_PMV_IMUX37_0",
"CLK_PMV_IMUX38_0",
"CLK_PMV_IMUX39_0",
"CLK_PMV_IMUX3_0",
"CLK_PMV_IMUX40_0",
"CLK_PMV_IMUX41_0",
"CLK_PMV_IMUX42_0",
"CLK_PMV_IMUX43_0",
"CLK_PMV_IMUX44_0",
"CLK_PMV_IMUX45_0",
"CLK_PMV_IMUX46_0",
"CLK_PMV_IMUX47_0",
"CLK_PMV_IMUX4_0",
"CLK_PMV_IMUX5_0",
"CLK_PMV_IMUX6_0",
"CLK_PMV_IMUX7_0",
"CLK_PMV_IMUX8_0",
"CLK_PMV_IMUX9_0",
"CLK_PMV_LOGIC_OUTS0_0",
"CLK_PMV_LOGIC_OUTS10_0",
"CLK_PMV_LOGIC_OUTS11_0",
"CLK_PMV_LOGIC_OUTS12_0",
"CLK_PMV_LOGIC_OUTS13_0",
"CLK_PMV_LOGIC_OUTS14_0",
"CLK_PMV_LOGIC_OUTS15_0",
"CLK_PMV_LOGIC_OUTS16_0",
"CLK_PMV_LOGIC_OUTS17_0",
"CLK_PMV_LOGIC_OUTS18_0",
"CLK_PMV_LOGIC_OUTS19_0",
"CLK_PMV_LOGIC_OUTS1_0",
"CLK_PMV_LOGIC_OUTS20_0",
"CLK_PMV_LOGIC_OUTS21_0",
"CLK_PMV_LOGIC_OUTS22_0",
"CLK_PMV_LOGIC_OUTS23_0",
"CLK_PMV_LOGIC_OUTS2_0",
"CLK_PMV_LOGIC_OUTS3_0",
"CLK_PMV_LOGIC_OUTS4_0",
"CLK_PMV_LOGIC_OUTS5_0",
"CLK_PMV_LOGIC_OUTS6_0",
"CLK_PMV_LOGIC_OUTS7_0",
"CLK_PMV_LOGIC_OUTS8_0",
"CLK_PMV_LOGIC_OUTS9_0"
]
"wires": {
"CLK_FEED_CK_BUFG_CASC0": null,
"CLK_FEED_CK_BUFG_CASC1": null,
"CLK_FEED_CK_BUFG_CASC10": null,
"CLK_FEED_CK_BUFG_CASC11": null,
"CLK_FEED_CK_BUFG_CASC12": null,
"CLK_FEED_CK_BUFG_CASC13": null,
"CLK_FEED_CK_BUFG_CASC14": null,
"CLK_FEED_CK_BUFG_CASC15": null,
"CLK_FEED_CK_BUFG_CASC16": null,
"CLK_FEED_CK_BUFG_CASC17": null,
"CLK_FEED_CK_BUFG_CASC18": null,
"CLK_FEED_CK_BUFG_CASC19": null,
"CLK_FEED_CK_BUFG_CASC2": null,
"CLK_FEED_CK_BUFG_CASC20": null,
"CLK_FEED_CK_BUFG_CASC21": null,
"CLK_FEED_CK_BUFG_CASC22": null,
"CLK_FEED_CK_BUFG_CASC23": null,
"CLK_FEED_CK_BUFG_CASC24": null,
"CLK_FEED_CK_BUFG_CASC25": null,
"CLK_FEED_CK_BUFG_CASC26": null,
"CLK_FEED_CK_BUFG_CASC27": null,
"CLK_FEED_CK_BUFG_CASC28": null,
"CLK_FEED_CK_BUFG_CASC29": null,
"CLK_FEED_CK_BUFG_CASC3": null,
"CLK_FEED_CK_BUFG_CASC30": null,
"CLK_FEED_CK_BUFG_CASC31": null,
"CLK_FEED_CK_BUFG_CASC4": null,
"CLK_FEED_CK_BUFG_CASC5": null,
"CLK_FEED_CK_BUFG_CASC6": null,
"CLK_FEED_CK_BUFG_CASC7": null,
"CLK_FEED_CK_BUFG_CASC8": null,
"CLK_FEED_CK_BUFG_CASC9": null,
"CLK_FEED_CK_GCLK0": null,
"CLK_FEED_CK_GCLK1": null,
"CLK_FEED_CK_GCLK10": null,
"CLK_FEED_CK_GCLK11": null,
"CLK_FEED_CK_GCLK12": null,
"CLK_FEED_CK_GCLK13": null,
"CLK_FEED_CK_GCLK14": null,
"CLK_FEED_CK_GCLK15": null,
"CLK_FEED_CK_GCLK16": null,
"CLK_FEED_CK_GCLK17": null,
"CLK_FEED_CK_GCLK18": null,
"CLK_FEED_CK_GCLK19": null,
"CLK_FEED_CK_GCLK2": null,
"CLK_FEED_CK_GCLK20": null,
"CLK_FEED_CK_GCLK21": null,
"CLK_FEED_CK_GCLK22": null,
"CLK_FEED_CK_GCLK23": null,
"CLK_FEED_CK_GCLK24": null,
"CLK_FEED_CK_GCLK25": null,
"CLK_FEED_CK_GCLK26": null,
"CLK_FEED_CK_GCLK27": null,
"CLK_FEED_CK_GCLK28": null,
"CLK_FEED_CK_GCLK29": null,
"CLK_FEED_CK_GCLK3": null,
"CLK_FEED_CK_GCLK30": null,
"CLK_FEED_CK_GCLK31": null,
"CLK_FEED_CK_GCLK4": null,
"CLK_FEED_CK_GCLK5": null,
"CLK_FEED_CK_GCLK6": null,
"CLK_FEED_CK_GCLK7": null,
"CLK_FEED_CK_GCLK8": null,
"CLK_FEED_CK_GCLK9": null,
"CLK_FEED_EE2A0": null,
"CLK_FEED_EE2A1": null,
"CLK_FEED_EE2A2": null,
"CLK_FEED_EE2A3": null,
"CLK_FEED_EE2BEG0": null,
"CLK_FEED_EE2BEG1": null,
"CLK_FEED_EE2BEG2": null,
"CLK_FEED_EE2BEG3": null,
"CLK_FEED_EE4A0": null,
"CLK_FEED_EE4A1": null,
"CLK_FEED_EE4A2": null,
"CLK_FEED_EE4A3": null,
"CLK_FEED_EE4B0": null,
"CLK_FEED_EE4B1": null,
"CLK_FEED_EE4B2": null,
"CLK_FEED_EE4B3": null,
"CLK_FEED_EE4BEG0": null,
"CLK_FEED_EE4BEG1": null,
"CLK_FEED_EE4BEG2": null,
"CLK_FEED_EE4BEG3": null,
"CLK_FEED_EE4C0": null,
"CLK_FEED_EE4C1": null,
"CLK_FEED_EE4C2": null,
"CLK_FEED_EE4C3": null,
"CLK_FEED_EL1BEG0": null,
"CLK_FEED_EL1BEG1": null,
"CLK_FEED_EL1BEG2": null,
"CLK_FEED_EL1BEG3": null,
"CLK_FEED_ER1BEG0": null,
"CLK_FEED_ER1BEG1": null,
"CLK_FEED_ER1BEG2": null,
"CLK_FEED_ER1BEG3": null,
"CLK_FEED_LH1": null,
"CLK_FEED_LH10": null,
"CLK_FEED_LH11": null,
"CLK_FEED_LH12": null,
"CLK_FEED_LH2": null,
"CLK_FEED_LH3": null,
"CLK_FEED_LH4": null,
"CLK_FEED_LH5": null,
"CLK_FEED_LH6": null,
"CLK_FEED_LH7": null,
"CLK_FEED_LH8": null,
"CLK_FEED_LH9": null,
"CLK_FEED_MONITOR_N": null,
"CLK_FEED_MONITOR_P": null,
"CLK_FEED_NE2A0": null,
"CLK_FEED_NE2A1": null,
"CLK_FEED_NE2A2": null,
"CLK_FEED_NE2A3": null,
"CLK_FEED_NE4BEG0": null,
"CLK_FEED_NE4BEG1": null,
"CLK_FEED_NE4BEG2": null,
"CLK_FEED_NE4BEG3": null,
"CLK_FEED_NE4C0": null,
"CLK_FEED_NE4C1": null,
"CLK_FEED_NE4C2": null,
"CLK_FEED_NE4C3": null,
"CLK_FEED_NW2A0": null,
"CLK_FEED_NW2A1": null,
"CLK_FEED_NW2A2": null,
"CLK_FEED_NW2A3": null,
"CLK_FEED_NW4A0": null,
"CLK_FEED_NW4A1": null,
"CLK_FEED_NW4A2": null,
"CLK_FEED_NW4A3": null,
"CLK_FEED_NW4END0": null,
"CLK_FEED_NW4END1": null,
"CLK_FEED_NW4END2": null,
"CLK_FEED_NW4END3": null,
"CLK_FEED_R_CK_BUFG_CASC0": null,
"CLK_FEED_R_CK_BUFG_CASC1": null,
"CLK_FEED_R_CK_BUFG_CASC10": null,
"CLK_FEED_R_CK_BUFG_CASC11": null,
"CLK_FEED_R_CK_BUFG_CASC12": null,
"CLK_FEED_R_CK_BUFG_CASC13": null,
"CLK_FEED_R_CK_BUFG_CASC14": null,
"CLK_FEED_R_CK_BUFG_CASC15": null,
"CLK_FEED_R_CK_BUFG_CASC16": null,
"CLK_FEED_R_CK_BUFG_CASC17": null,
"CLK_FEED_R_CK_BUFG_CASC18": null,
"CLK_FEED_R_CK_BUFG_CASC19": null,
"CLK_FEED_R_CK_BUFG_CASC2": null,
"CLK_FEED_R_CK_BUFG_CASC20": null,
"CLK_FEED_R_CK_BUFG_CASC21": null,
"CLK_FEED_R_CK_BUFG_CASC22": null,
"CLK_FEED_R_CK_BUFG_CASC23": null,
"CLK_FEED_R_CK_BUFG_CASC24": null,
"CLK_FEED_R_CK_BUFG_CASC25": null,
"CLK_FEED_R_CK_BUFG_CASC26": null,
"CLK_FEED_R_CK_BUFG_CASC27": null,
"CLK_FEED_R_CK_BUFG_CASC28": null,
"CLK_FEED_R_CK_BUFG_CASC29": null,
"CLK_FEED_R_CK_BUFG_CASC3": null,
"CLK_FEED_R_CK_BUFG_CASC30": null,
"CLK_FEED_R_CK_BUFG_CASC31": null,
"CLK_FEED_R_CK_BUFG_CASC4": null,
"CLK_FEED_R_CK_BUFG_CASC5": null,
"CLK_FEED_R_CK_BUFG_CASC6": null,
"CLK_FEED_R_CK_BUFG_CASC7": null,
"CLK_FEED_R_CK_BUFG_CASC8": null,
"CLK_FEED_R_CK_BUFG_CASC9": null,
"CLK_FEED_R_CK_GCLK0": null,
"CLK_FEED_R_CK_GCLK1": null,
"CLK_FEED_R_CK_GCLK10": null,
"CLK_FEED_R_CK_GCLK11": null,
"CLK_FEED_R_CK_GCLK12": null,
"CLK_FEED_R_CK_GCLK13": null,
"CLK_FEED_R_CK_GCLK14": null,
"CLK_FEED_R_CK_GCLK15": null,
"CLK_FEED_R_CK_GCLK16": null,
"CLK_FEED_R_CK_GCLK17": null,
"CLK_FEED_R_CK_GCLK18": null,
"CLK_FEED_R_CK_GCLK19": null,
"CLK_FEED_R_CK_GCLK2": null,
"CLK_FEED_R_CK_GCLK20": null,
"CLK_FEED_R_CK_GCLK21": null,
"CLK_FEED_R_CK_GCLK22": null,
"CLK_FEED_R_CK_GCLK23": null,
"CLK_FEED_R_CK_GCLK24": null,
"CLK_FEED_R_CK_GCLK25": null,
"CLK_FEED_R_CK_GCLK26": null,
"CLK_FEED_R_CK_GCLK27": null,
"CLK_FEED_R_CK_GCLK28": null,
"CLK_FEED_R_CK_GCLK29": null,
"CLK_FEED_R_CK_GCLK3": null,
"CLK_FEED_R_CK_GCLK30": null,
"CLK_FEED_R_CK_GCLK31": null,
"CLK_FEED_R_CK_GCLK4": null,
"CLK_FEED_R_CK_GCLK5": null,
"CLK_FEED_R_CK_GCLK6": null,
"CLK_FEED_R_CK_GCLK7": null,
"CLK_FEED_R_CK_GCLK8": null,
"CLK_FEED_R_CK_GCLK9": null,
"CLK_FEED_SE2A0": null,
"CLK_FEED_SE2A1": null,
"CLK_FEED_SE2A2": null,
"CLK_FEED_SE2A3": null,
"CLK_FEED_SE4BEG0": null,
"CLK_FEED_SE4BEG1": null,
"CLK_FEED_SE4BEG2": null,
"CLK_FEED_SE4BEG3": null,
"CLK_FEED_SE4C0": null,
"CLK_FEED_SE4C1": null,
"CLK_FEED_SE4C2": null,
"CLK_FEED_SE4C3": null,
"CLK_FEED_SW2A0": null,
"CLK_FEED_SW2A1": null,
"CLK_FEED_SW2A2": null,
"CLK_FEED_SW2A3": null,
"CLK_FEED_SW4A0": null,
"CLK_FEED_SW4A1": null,
"CLK_FEED_SW4A2": null,
"CLK_FEED_SW4A3": null,
"CLK_FEED_SW4END0": null,
"CLK_FEED_SW4END1": null,
"CLK_FEED_SW4END2": null,
"CLK_FEED_SW4END3": null,
"CLK_FEED_WL1END0": null,
"CLK_FEED_WL1END1": null,
"CLK_FEED_WL1END2": null,
"CLK_FEED_WL1END3": null,
"CLK_FEED_WR1END0": null,
"CLK_FEED_WR1END1": null,
"CLK_FEED_WR1END2": null,
"CLK_FEED_WR1END3": null,
"CLK_FEED_WW2A0": null,
"CLK_FEED_WW2A1": null,
"CLK_FEED_WW2A2": null,
"CLK_FEED_WW2A3": null,
"CLK_FEED_WW2END0": null,
"CLK_FEED_WW2END1": null,
"CLK_FEED_WW2END2": null,
"CLK_FEED_WW2END3": null,
"CLK_FEED_WW4A0": null,
"CLK_FEED_WW4A1": null,
"CLK_FEED_WW4A2": null,
"CLK_FEED_WW4A3": null,
"CLK_FEED_WW4B0": null,
"CLK_FEED_WW4B1": null,
"CLK_FEED_WW4B2": null,
"CLK_FEED_WW4B3": null,
"CLK_FEED_WW4C0": null,
"CLK_FEED_WW4C1": null,
"CLK_FEED_WW4C2": null,
"CLK_FEED_WW4C3": null,
"CLK_FEED_WW4END0": null,
"CLK_FEED_WW4END1": null,
"CLK_FEED_WW4END2": null,
"CLK_FEED_WW4END3": null,
"CLK_PMV2_A0": null,
"CLK_PMV2_A1": null,
"CLK_PMV2_A2": null,
"CLK_PMV2_EN": null,
"CLK_PMV2_O": null,
"CLK_PMV2_ODIV2": null,
"CLK_PMV2_ODIV4": null,
"CLK_PMV_BYP0_0": null,
"CLK_PMV_BYP1_0": null,
"CLK_PMV_BYP2_0": null,
"CLK_PMV_BYP3_0": null,
"CLK_PMV_BYP4_0": null,
"CLK_PMV_BYP5_0": null,
"CLK_PMV_BYP6_0": null,
"CLK_PMV_BYP7_0": null,
"CLK_PMV_CLK0_0": null,
"CLK_PMV_CLK1_0": null,
"CLK_PMV_CTRL0_0": null,
"CLK_PMV_CTRL1_0": null,
"CLK_PMV_FAN0_0": null,
"CLK_PMV_FAN1_0": null,
"CLK_PMV_FAN2_0": null,
"CLK_PMV_FAN3_0": null,
"CLK_PMV_FAN4_0": null,
"CLK_PMV_FAN5_0": null,
"CLK_PMV_FAN6_0": null,
"CLK_PMV_FAN7_0": null,
"CLK_PMV_IMUX0_0": null,
"CLK_PMV_IMUX10_0": null,
"CLK_PMV_IMUX11_0": null,
"CLK_PMV_IMUX12_0": null,
"CLK_PMV_IMUX13_0": null,
"CLK_PMV_IMUX14_0": null,
"CLK_PMV_IMUX15_0": null,
"CLK_PMV_IMUX16_0": null,
"CLK_PMV_IMUX17_0": null,
"CLK_PMV_IMUX18_0": null,
"CLK_PMV_IMUX19_0": null,
"CLK_PMV_IMUX1_0": null,
"CLK_PMV_IMUX20_0": null,
"CLK_PMV_IMUX21_0": null,
"CLK_PMV_IMUX22_0": null,
"CLK_PMV_IMUX23_0": null,
"CLK_PMV_IMUX24_0": null,
"CLK_PMV_IMUX25_0": null,
"CLK_PMV_IMUX26_0": null,
"CLK_PMV_IMUX27_0": null,
"CLK_PMV_IMUX28_0": null,
"CLK_PMV_IMUX29_0": null,
"CLK_PMV_IMUX2_0": null,
"CLK_PMV_IMUX30_0": null,
"CLK_PMV_IMUX31_0": null,
"CLK_PMV_IMUX32_0": null,
"CLK_PMV_IMUX33_0": null,
"CLK_PMV_IMUX34_0": null,
"CLK_PMV_IMUX35_0": null,
"CLK_PMV_IMUX36_0": null,
"CLK_PMV_IMUX37_0": null,
"CLK_PMV_IMUX38_0": null,
"CLK_PMV_IMUX39_0": null,
"CLK_PMV_IMUX3_0": null,
"CLK_PMV_IMUX40_0": null,
"CLK_PMV_IMUX41_0": null,
"CLK_PMV_IMUX42_0": null,
"CLK_PMV_IMUX43_0": null,
"CLK_PMV_IMUX44_0": null,
"CLK_PMV_IMUX45_0": null,
"CLK_PMV_IMUX46_0": null,
"CLK_PMV_IMUX47_0": null,
"CLK_PMV_IMUX4_0": null,
"CLK_PMV_IMUX5_0": null,
"CLK_PMV_IMUX6_0": null,
"CLK_PMV_IMUX7_0": null,
"CLK_PMV_IMUX8_0": null,
"CLK_PMV_IMUX9_0": null,
"CLK_PMV_LOGIC_OUTS0_0": null,
"CLK_PMV_LOGIC_OUTS10_0": null,
"CLK_PMV_LOGIC_OUTS11_0": null,
"CLK_PMV_LOGIC_OUTS12_0": null,
"CLK_PMV_LOGIC_OUTS13_0": null,
"CLK_PMV_LOGIC_OUTS14_0": null,
"CLK_PMV_LOGIC_OUTS15_0": null,
"CLK_PMV_LOGIC_OUTS16_0": null,
"CLK_PMV_LOGIC_OUTS17_0": null,
"CLK_PMV_LOGIC_OUTS18_0": null,
"CLK_PMV_LOGIC_OUTS19_0": null,
"CLK_PMV_LOGIC_OUTS1_0": null,
"CLK_PMV_LOGIC_OUTS20_0": null,
"CLK_PMV_LOGIC_OUTS21_0": null,
"CLK_PMV_LOGIC_OUTS22_0": null,
"CLK_PMV_LOGIC_OUTS23_0": null,
"CLK_PMV_LOGIC_OUTS2_0": null,
"CLK_PMV_LOGIC_OUTS3_0": null,
"CLK_PMV_LOGIC_OUTS4_0": null,
"CLK_PMV_LOGIC_OUTS5_0": null,
"CLK_PMV_LOGIC_OUTS6_0": null,
"CLK_PMV_LOGIC_OUTS7_0": null,
"CLK_PMV_LOGIC_OUTS8_0": null,
"CLK_PMV_LOGIC_OUTS9_0": null
}
}

710
zynq7/tile_type_CLK_PMV2_SVT.json
View File

@ -2,359 +2,359 @@
"pips": {},
"sites": [],
"tile_type": "CLK_PMV2_SVT",
"wires": [
"CLK_FEED_CK_BUFG_CASC0",
"CLK_FEED_CK_BUFG_CASC1",
"CLK_FEED_CK_BUFG_CASC10",
"CLK_FEED_CK_BUFG_CASC11",
"CLK_FEED_CK_BUFG_CASC12",
"CLK_FEED_CK_BUFG_CASC13",
"CLK_FEED_CK_BUFG_CASC14",
"CLK_FEED_CK_BUFG_CASC15",
"CLK_FEED_CK_BUFG_CASC16",
"CLK_FEED_CK_BUFG_CASC17",
"CLK_FEED_CK_BUFG_CASC18",
"CLK_FEED_CK_BUFG_CASC19",
"CLK_FEED_CK_BUFG_CASC2",
"CLK_FEED_CK_BUFG_CASC20",
"CLK_FEED_CK_BUFG_CASC21",
"CLK_FEED_CK_BUFG_CASC22",
"CLK_FEED_CK_BUFG_CASC23",
"CLK_FEED_CK_BUFG_CASC24",
"CLK_FEED_CK_BUFG_CASC25",
"CLK_FEED_CK_BUFG_CASC26",
"CLK_FEED_CK_BUFG_CASC27",
"CLK_FEED_CK_BUFG_CASC28",
"CLK_FEED_CK_BUFG_CASC29",
"CLK_FEED_CK_BUFG_CASC3",
"CLK_FEED_CK_BUFG_CASC30",
"CLK_FEED_CK_BUFG_CASC31",
"CLK_FEED_CK_BUFG_CASC4",
"CLK_FEED_CK_BUFG_CASC5",
"CLK_FEED_CK_BUFG_CASC6",
"CLK_FEED_CK_BUFG_CASC7",
"CLK_FEED_CK_BUFG_CASC8",
"CLK_FEED_CK_BUFG_CASC9",
"CLK_FEED_CK_GCLK0",
"CLK_FEED_CK_GCLK1",
"CLK_FEED_CK_GCLK10",
"CLK_FEED_CK_GCLK11",
"CLK_FEED_CK_GCLK12",
"CLK_FEED_CK_GCLK13",
"CLK_FEED_CK_GCLK14",
"CLK_FEED_CK_GCLK15",
"CLK_FEED_CK_GCLK16",
"CLK_FEED_CK_GCLK17",
"CLK_FEED_CK_GCLK18",
"CLK_FEED_CK_GCLK19",
"CLK_FEED_CK_GCLK2",
"CLK_FEED_CK_GCLK20",
"CLK_FEED_CK_GCLK21",
"CLK_FEED_CK_GCLK22",
"CLK_FEED_CK_GCLK23",
"CLK_FEED_CK_GCLK24",
"CLK_FEED_CK_GCLK25",
"CLK_FEED_CK_GCLK26",
"CLK_FEED_CK_GCLK27",
"CLK_FEED_CK_GCLK28",
"CLK_FEED_CK_GCLK29",
"CLK_FEED_CK_GCLK3",
"CLK_FEED_CK_GCLK30",
"CLK_FEED_CK_GCLK31",
"CLK_FEED_CK_GCLK4",
"CLK_FEED_CK_GCLK5",
"CLK_FEED_CK_GCLK6",
"CLK_FEED_CK_GCLK7",
"CLK_FEED_CK_GCLK8",
"CLK_FEED_CK_GCLK9",
"CLK_FEED_EE2A0",
"CLK_FEED_EE2A1",
"CLK_FEED_EE2A2",
"CLK_FEED_EE2A3",
"CLK_FEED_EE2BEG0",
"CLK_FEED_EE2BEG1",
"CLK_FEED_EE2BEG2",
"CLK_FEED_EE2BEG3",
"CLK_FEED_EE4A0",
"CLK_FEED_EE4A1",
"CLK_FEED_EE4A2",
"CLK_FEED_EE4A3",
"CLK_FEED_EE4B0",
"CLK_FEED_EE4B1",
"CLK_FEED_EE4B2",
"CLK_FEED_EE4B3",
"CLK_FEED_EE4BEG0",
"CLK_FEED_EE4BEG1",
"CLK_FEED_EE4BEG2",
"CLK_FEED_EE4BEG3",
"CLK_FEED_EE4C0",
"CLK_FEED_EE4C1",
"CLK_FEED_EE4C2",
"CLK_FEED_EE4C3",
"CLK_FEED_EL1BEG0",
"CLK_FEED_EL1BEG1",
"CLK_FEED_EL1BEG2",
"CLK_FEED_EL1BEG3",
"CLK_FEED_ER1BEG0",
"CLK_FEED_ER1BEG1",
"CLK_FEED_ER1BEG2",
"CLK_FEED_ER1BEG3",
"CLK_FEED_LH1",
"CLK_FEED_LH10",
"CLK_FEED_LH11",
"CLK_FEED_LH12",
"CLK_FEED_LH2",
"CLK_FEED_LH3",
"CLK_FEED_LH4",
"CLK_FEED_LH5",
"CLK_FEED_LH6",
"CLK_FEED_LH7",
"CLK_FEED_LH8",
"CLK_FEED_LH9",
"CLK_FEED_MONITOR_N",
"CLK_FEED_MONITOR_P",
"CLK_FEED_NE2A0",
"CLK_FEED_NE2A1",
"CLK_FEED_NE2A2",
"CLK_FEED_NE2A3",
"CLK_FEED_NE4BEG0",
"CLK_FEED_NE4BEG1",
"CLK_FEED_NE4BEG2",
"CLK_FEED_NE4BEG3",
"CLK_FEED_NE4C0",
"CLK_FEED_NE4C1",
"CLK_FEED_NE4C2",
"CLK_FEED_NE4C3",
"CLK_FEED_NW2A0",
"CLK_FEED_NW2A1",
"CLK_FEED_NW2A2",
"CLK_FEED_NW2A3",
"CLK_FEED_NW4A0",
"CLK_FEED_NW4A1",
"CLK_FEED_NW4A2",
"CLK_FEED_NW4A3",
"CLK_FEED_NW4END0",
"CLK_FEED_NW4END1",
"CLK_FEED_NW4END2",
"CLK_FEED_NW4END3",
"CLK_FEED_R_CK_BUFG_CASC0",
"CLK_FEED_R_CK_BUFG_CASC1",
"CLK_FEED_R_CK_BUFG_CASC10",
"CLK_FEED_R_CK_BUFG_CASC11",
"CLK_FEED_R_CK_BUFG_CASC12",
"CLK_FEED_R_CK_BUFG_CASC13",
"CLK_FEED_R_CK_BUFG_CASC14",
"CLK_FEED_R_CK_BUFG_CASC15",
"CLK_FEED_R_CK_BUFG_CASC16",
"CLK_FEED_R_CK_BUFG_CASC17",
"CLK_FEED_R_CK_BUFG_CASC18",
"CLK_FEED_R_CK_BUFG_CASC19",
"CLK_FEED_R_CK_BUFG_CASC2",
"CLK_FEED_R_CK_BUFG_CASC20",
"CLK_FEED_R_CK_BUFG_CASC21",
"CLK_FEED_R_CK_BUFG_CASC22",
"CLK_FEED_R_CK_BUFG_CASC23",
"CLK_FEED_R_CK_BUFG_CASC24",
"CLK_FEED_R_CK_BUFG_CASC25",
"CLK_FEED_R_CK_BUFG_CASC26",
"CLK_FEED_R_CK_BUFG_CASC27",
"CLK_FEED_R_CK_BUFG_CASC28",
"CLK_FEED_R_CK_BUFG_CASC29",
"CLK_FEED_R_CK_BUFG_CASC3",
"CLK_FEED_R_CK_BUFG_CASC30",
"CLK_FEED_R_CK_BUFG_CASC31",
"CLK_FEED_R_CK_BUFG_CASC4",
"CLK_FEED_R_CK_BUFG_CASC5",
"CLK_FEED_R_CK_BUFG_CASC6",
"CLK_FEED_R_CK_BUFG_CASC7",
"CLK_FEED_R_CK_BUFG_CASC8",
"CLK_FEED_R_CK_BUFG_CASC9",
"CLK_FEED_R_CK_GCLK0",
"CLK_FEED_R_CK_GCLK1",
"CLK_FEED_R_CK_GCLK10",
"CLK_FEED_R_CK_GCLK11",
"CLK_FEED_R_CK_GCLK12",
"CLK_FEED_R_CK_GCLK13",
"CLK_FEED_R_CK_GCLK14",
"CLK_FEED_R_CK_GCLK15",
"CLK_FEED_R_CK_GCLK16",
"CLK_FEED_R_CK_GCLK17",
"CLK_FEED_R_CK_GCLK18",
"CLK_FEED_R_CK_GCLK19",
"CLK_FEED_R_CK_GCLK2",
"CLK_FEED_R_CK_GCLK20",
"CLK_FEED_R_CK_GCLK21",
"CLK_FEED_R_CK_GCLK22",
"CLK_FEED_R_CK_GCLK23",
"CLK_FEED_R_CK_GCLK24",
"CLK_FEED_R_CK_GCLK25",
"CLK_FEED_R_CK_GCLK26",
"CLK_FEED_R_CK_GCLK27",
"CLK_FEED_R_CK_GCLK28",
"CLK_FEED_R_CK_GCLK29",
"CLK_FEED_R_CK_GCLK3",
"CLK_FEED_R_CK_GCLK30",
"CLK_FEED_R_CK_GCLK31",
"CLK_FEED_R_CK_GCLK4",
"CLK_FEED_R_CK_GCLK5",
"CLK_FEED_R_CK_GCLK6",
"CLK_FEED_R_CK_GCLK7",
"CLK_FEED_R_CK_GCLK8",
"CLK_FEED_R_CK_GCLK9",
"CLK_FEED_SE2A0",
"CLK_FEED_SE2A1",
"CLK_FEED_SE2A2",
"CLK_FEED_SE2A3",
"CLK_FEED_SE4BEG0",
"CLK_FEED_SE4BEG1",
"CLK_FEED_SE4BEG2",
"CLK_FEED_SE4BEG3",
"CLK_FEED_SE4C0",
"CLK_FEED_SE4C1",
"CLK_FEED_SE4C2",
"CLK_FEED_SE4C3",
"CLK_FEED_SW2A0",
"CLK_FEED_SW2A1",
"CLK_FEED_SW2A2",
"CLK_FEED_SW2A3",
"CLK_FEED_SW4A0",
"CLK_FEED_SW4A1",
"CLK_FEED_SW4A2",
"CLK_FEED_SW4A3",
"CLK_FEED_SW4END0",
"CLK_FEED_SW4END1",
"CLK_FEED_SW4END2",
"CLK_FEED_SW4END3",
"CLK_FEED_WL1END0",
"CLK_FEED_WL1END1",
"CLK_FEED_WL1END2",
"CLK_FEED_WL1END3",
"CLK_FEED_WR1END0",
"CLK_FEED_WR1END1",
"CLK_FEED_WR1END2",
"CLK_FEED_WR1END3",
"CLK_FEED_WW2A0",
"CLK_FEED_WW2A1",
"CLK_FEED_WW2A2",
"CLK_FEED_WW2A3",
"CLK_FEED_WW2END0",
"CLK_FEED_WW2END1",
"CLK_FEED_WW2END2",
"CLK_FEED_WW2END3",
"CLK_FEED_WW4A0",
"CLK_FEED_WW4A1",
"CLK_FEED_WW4A2",
"CLK_FEED_WW4A3",
"CLK_FEED_WW4B0",
"CLK_FEED_WW4B1",
"CLK_FEED_WW4B2",
"CLK_FEED_WW4B3",
"CLK_FEED_WW4C0",
"CLK_FEED_WW4C1",
"CLK_FEED_WW4C2",
"CLK_FEED_WW4C3",
"CLK_FEED_WW4END0",
"CLK_FEED_WW4END1",
"CLK_FEED_WW4END2",
"CLK_FEED_WW4END3",
"CLK_PMV2_A0",
"CLK_PMV2_A1",
"CLK_PMV2_A2",
"CLK_PMV2_EN",
"CLK_PMV2_O",
"CLK_PMV2_ODIV2",
"CLK_PMV2_ODIV4",
"CLK_PMV_BYP0_0",
"CLK_PMV_BYP1_0",
"CLK_PMV_BYP2_0",
"CLK_PMV_BYP3_0",
"CLK_PMV_BYP4_0",
"CLK_PMV_BYP5_0",
"CLK_PMV_BYP6_0",
"CLK_PMV_BYP7_0",
"CLK_PMV_CLK0_0",
"CLK_PMV_CLK1_0",
"CLK_PMV_CTRL0_0",
"CLK_PMV_CTRL1_0",
"CLK_PMV_FAN0_0",
"CLK_PMV_FAN1_0",
"CLK_PMV_FAN2_0",
"CLK_PMV_FAN3_0",
"CLK_PMV_FAN4_0",
"CLK_PMV_FAN5_0",
"CLK_PMV_FAN6_0",
"CLK_PMV_FAN7_0",
"CLK_PMV_IMUX0_0",
"CLK_PMV_IMUX10_0",
"CLK_PMV_IMUX11_0",
"CLK_PMV_IMUX12_0",
"CLK_PMV_IMUX13_0",
"CLK_PMV_IMUX14_0",
"CLK_PMV_IMUX15_0",
"CLK_PMV_IMUX16_0",
"CLK_PMV_IMUX17_0",
"CLK_PMV_IMUX18_0",
"CLK_PMV_IMUX19_0",
"CLK_PMV_IMUX1_0",
"CLK_PMV_IMUX20_0",
"CLK_PMV_IMUX21_0",
"CLK_PMV_IMUX22_0",
"CLK_PMV_IMUX23_0",
"CLK_PMV_IMUX24_0",
"CLK_PMV_IMUX25_0",
"CLK_PMV_IMUX26_0",
"CLK_PMV_IMUX27_0",
"CLK_PMV_IMUX28_0",
"CLK_PMV_IMUX29_0",
"CLK_PMV_IMUX2_0",
"CLK_PMV_IMUX30_0",
"CLK_PMV_IMUX31_0",
"CLK_PMV_IMUX32_0",
"CLK_PMV_IMUX33_0",
"CLK_PMV_IMUX34_0",
"CLK_PMV_IMUX35_0",
"CLK_PMV_IMUX36_0",
"CLK_PMV_IMUX37_0",
"CLK_PMV_IMUX38_0",
"CLK_PMV_IMUX39_0",
"CLK_PMV_IMUX3_0",
"CLK_PMV_IMUX40_0",
"CLK_PMV_IMUX41_0",
"CLK_PMV_IMUX42_0",
"CLK_PMV_IMUX43_0",
"CLK_PMV_IMUX44_0",
"CLK_PMV_IMUX45_0",
"CLK_PMV_IMUX46_0",
"CLK_PMV_IMUX47_0",
"CLK_PMV_IMUX4_0",
"CLK_PMV_IMUX5_0",
"CLK_PMV_IMUX6_0",
"CLK_PMV_IMUX7_0",
"CLK_PMV_IMUX8_0",
"CLK_PMV_IMUX9_0",
"CLK_PMV_LOGIC_OUTS0_0",
"CLK_PMV_LOGIC_OUTS10_0",
"CLK_PMV_LOGIC_OUTS11_0",
"CLK_PMV_LOGIC_OUTS12_0",
"CLK_PMV_LOGIC_OUTS13_0",
"CLK_PMV_LOGIC_OUTS14_0",
"CLK_PMV_LOGIC_OUTS15_0",
"CLK_PMV_LOGIC_OUTS16_0",
"CLK_PMV_LOGIC_OUTS17_0",
"CLK_PMV_LOGIC_OUTS18_0",
"CLK_PMV_LOGIC_OUTS19_0",
"CLK_PMV_LOGIC_OUTS1_0",
"CLK_PMV_LOGIC_OUTS20_0",
"CLK_PMV_LOGIC_OUTS21_0",
"CLK_PMV_LOGIC_OUTS22_0",
"CLK_PMV_LOGIC_OUTS23_0",
"CLK_PMV_LOGIC_OUTS2_0",
"CLK_PMV_LOGIC_OUTS3_0",
"CLK_PMV_LOGIC_OUTS4_0",
"CLK_PMV_LOGIC_OUTS5_0",
"CLK_PMV_LOGIC_OUTS6_0",
"CLK_PMV_LOGIC_OUTS7_0",
"CLK_PMV_LOGIC_OUTS8_0",
"CLK_PMV_LOGIC_OUTS9_0"
]
"wires": {
"CLK_FEED_CK_BUFG_CASC0": null,
"CLK_FEED_CK_BUFG_CASC1": null,
"CLK_FEED_CK_BUFG_CASC10": null,
"CLK_FEED_CK_BUFG_CASC11": null,
"CLK_FEED_CK_BUFG_CASC12": null,
"CLK_FEED_CK_BUFG_CASC13": null,
"CLK_FEED_CK_BUFG_CASC14": null,
"CLK_FEED_CK_BUFG_CASC15": null,
"CLK_FEED_CK_BUFG_CASC16": null,
"CLK_FEED_CK_BUFG_CASC17": null,
"CLK_FEED_CK_BUFG_CASC18": null,
"CLK_FEED_CK_BUFG_CASC19": null,
"CLK_FEED_CK_BUFG_CASC2": null,
"CLK_FEED_CK_BUFG_CASC20": null,
"CLK_FEED_CK_BUFG_CASC21": null,
"CLK_FEED_CK_BUFG_CASC22": null,
"CLK_FEED_CK_BUFG_CASC23": null,
"CLK_FEED_CK_BUFG_CASC24": null,
"CLK_FEED_CK_BUFG_CASC25": null,
"CLK_FEED_CK_BUFG_CASC26": null,
"CLK_FEED_CK_BUFG_CASC27": null,
"CLK_FEED_CK_BUFG_CASC28": null,
"CLK_FEED_CK_BUFG_CASC29": null,
"CLK_FEED_CK_BUFG_CASC3": null,
"CLK_FEED_CK_BUFG_CASC30": null,
"CLK_FEED_CK_BUFG_CASC31": null,
"CLK_FEED_CK_BUFG_CASC4": null,
"CLK_FEED_CK_BUFG_CASC5": null,
"CLK_FEED_CK_BUFG_CASC6": null,
"CLK_FEED_CK_BUFG_CASC7": null,
"CLK_FEED_CK_BUFG_CASC8": null,
"CLK_FEED_CK_BUFG_CASC9": null,
"CLK_FEED_CK_GCLK0": null,
"CLK_FEED_CK_GCLK1": null,
"CLK_FEED_CK_GCLK10": null,
"CLK_FEED_CK_GCLK11": null,
"CLK_FEED_CK_GCLK12": null,
"CLK_FEED_CK_GCLK13": null,
"CLK_FEED_CK_GCLK14": null,
"CLK_FEED_CK_GCLK15": null,
"CLK_FEED_CK_GCLK16": null,
"CLK_FEED_CK_GCLK17": null,
"CLK_FEED_CK_GCLK18": null,
"CLK_FEED_CK_GCLK19": null,
"CLK_FEED_CK_GCLK2": null,
"CLK_FEED_CK_GCLK20": null,
"CLK_FEED_CK_GCLK21": null,
"CLK_FEED_CK_GCLK22": null,
"CLK_FEED_CK_GCLK23": null,
"CLK_FEED_CK_GCLK24": null,
"CLK_FEED_CK_GCLK25": null,
"CLK_FEED_CK_GCLK26": null,
"CLK_FEED_CK_GCLK27": null,
"CLK_FEED_CK_GCLK28": null,
"CLK_FEED_CK_GCLK29": null,
"CLK_FEED_CK_GCLK3": null,
"CLK_FEED_CK_GCLK30": null,
"CLK_FEED_CK_GCLK31": null,
"CLK_FEED_CK_GCLK4": null,
"CLK_FEED_CK_GCLK5": null,
"CLK_FEED_CK_GCLK6": null,
"CLK_FEED_CK_GCLK7": null,
"CLK_FEED_CK_GCLK8": null,
"CLK_FEED_CK_GCLK9": null,
"CLK_FEED_EE2A0": null,
"CLK_FEED_EE2A1": null,
"CLK_FEED_EE2A2": null,
"CLK_FEED_EE2A3": null,
"CLK_FEED_EE2BEG0": null,
"CLK_FEED_EE2BEG1": null,
"CLK_FEED_EE2BEG2": null,
"CLK_FEED_EE2BEG3": null,
"CLK_FEED_EE4A0": null,
"CLK_FEED_EE4A1": null,
"CLK_FEED_EE4A2": null,
"CLK_FEED_EE4A3": null,
"CLK_FEED_EE4B0": null,
"CLK_FEED_EE4B1": null,
"CLK_FEED_EE4B2": null,
"CLK_FEED_EE4B3": null,
"CLK_FEED_EE4BEG0": null,
"CLK_FEED_EE4BEG1": null,
"CLK_FEED_EE4BEG2": null,
"CLK_FEED_EE4BEG3": null,
"CLK_FEED_EE4C0": null,
"CLK_FEED_EE4C1": null,
"CLK_FEED_EE4C2": null,
"CLK_FEED_EE4C3": null,
"CLK_FEED_EL1BEG0": null,
"CLK_FEED_EL1BEG1": null,
"CLK_FEED_EL1BEG2": null,
"CLK_FEED_EL1BEG3": null,
"CLK_FEED_ER1BEG0": null,
"CLK_FEED_ER1BEG1": null,
"CLK_FEED_ER1BEG2": null,
"CLK_FEED_ER1BEG3": null,
"CLK_FEED_LH1": null,
"CLK_FEED_LH10": null,
"CLK_FEED_LH11": null,
"CLK_FEED_LH12": null,
"CLK_FEED_LH2": null,
"CLK_FEED_LH3": null,
"CLK_FEED_LH4": null,
"CLK_FEED_LH5": null,
"CLK_FEED_LH6": null,
"CLK_FEED_LH7": null,
"CLK_FEED_LH8": null,
"CLK_FEED_LH9": null,
"CLK_FEED_MONITOR_N": null,
"CLK_FEED_MONITOR_P": null,
"CLK_FEED_NE2A0": null,
"CLK_FEED_NE2A1": null,
"CLK_FEED_NE2A2": null,
"CLK_FEED_NE2A3": null,
"CLK_FEED_NE4BEG0": null,
"CLK_FEED_NE4BEG1": null,
"CLK_FEED_NE4BEG2": null,
"CLK_FEED_NE4BEG3": null,
"CLK_FEED_NE4C0": null,
"CLK_FEED_NE4C1": null,
"CLK_FEED_NE4C2": null,
"CLK_FEED_NE4C3": null,
"CLK_FEED_NW2A0": null,
"CLK_FEED_NW2A1": null,
"CLK_FEED_NW2A2": null,
"CLK_FEED_NW2A3": null,
"CLK_FEED_NW4A0": null,
"CLK_FEED_NW4A1": null,
"CLK_FEED_NW4A2": null,
"CLK_FEED_NW4A3": null,
"CLK_FEED_NW4END0": null,
"CLK_FEED_NW4END1": null,
"CLK_FEED_NW4END2": null,
"CLK_FEED_NW4END3": null,
"CLK_FEED_R_CK_BUFG_CASC0": null,
"CLK_FEED_R_CK_BUFG_CASC1": null,
"CLK_FEED_R_CK_BUFG_CASC10": null,
"CLK_FEED_R_CK_BUFG_CASC11": null,
"CLK_FEED_R_CK_BUFG_CASC12": null,
"CLK_FEED_R_CK_BUFG_CASC13": null,
"CLK_FEED_R_CK_BUFG_CASC14": null,
"CLK_FEED_R_CK_BUFG_CASC15": null,
"CLK_FEED_R_CK_BUFG_CASC16": null,
"CLK_FEED_R_CK_BUFG_CASC17": null,
"CLK_FEED_R_CK_BUFG_CASC18": null,
"CLK_FEED_R_CK_BUFG_CASC19": null,
"CLK_FEED_R_CK_BUFG_CASC2": null,
"CLK_FEED_R_CK_BUFG_CASC20": null,
"CLK_FEED_R_CK_BUFG_CASC21": null,
"CLK_FEED_R_CK_BUFG_CASC22": null,
"CLK_FEED_R_CK_BUFG_CASC23": null,
"CLK_FEED_R_CK_BUFG_CASC24": null,
"CLK_FEED_R_CK_BUFG_CASC25": null,
"CLK_FEED_R_CK_BUFG_CASC26": null,
"CLK_FEED_R_CK_BUFG_CASC27": null,
"CLK_FEED_R_CK_BUFG_CASC28": null,
"CLK_FEED_R_CK_BUFG_CASC29": null,
"CLK_FEED_R_CK_BUFG_CASC3": null,
"CLK_FEED_R_CK_BUFG_CASC30": null,
"CLK_FEED_R_CK_BUFG_CASC31": null,
"CLK_FEED_R_CK_BUFG_CASC4": null,
"CLK_FEED_R_CK_BUFG_CASC5": null,
"CLK_FEED_R_CK_BUFG_CASC6": null,
"CLK_FEED_R_CK_BUFG_CASC7": null,
"CLK_FEED_R_CK_BUFG_CASC8": null,
"CLK_FEED_R_CK_BUFG_CASC9": null,
"CLK_FEED_R_CK_GCLK0": null,
"CLK_FEED_R_CK_GCLK1": null,
"CLK_FEED_R_CK_GCLK10": null,
"CLK_FEED_R_CK_GCLK11": null,
"CLK_FEED_R_CK_GCLK12": null,
"CLK_FEED_R_CK_GCLK13": null,
"CLK_FEED_R_CK_GCLK14": null,
"CLK_FEED_R_CK_GCLK15": null,
"CLK_FEED_R_CK_GCLK16": null,
"CLK_FEED_R_CK_GCLK17": null,
"CLK_FEED_R_CK_GCLK18": null,
"CLK_FEED_R_CK_GCLK19": null,
"CLK_FEED_R_CK_GCLK2": null,
"CLK_FEED_R_CK_GCLK20": null,
"CLK_FEED_R_CK_GCLK21": null,
"CLK_FEED_R_CK_GCLK22": null,
"CLK_FEED_R_CK_GCLK23": null,
"CLK_FEED_R_CK_GCLK24": null,
"CLK_FEED_R_CK_GCLK25": null,
"CLK_FEED_R_CK_GCLK26": null,
"CLK_FEED_R_CK_GCLK27": null,
"CLK_FEED_R_CK_GCLK28": null,
"CLK_FEED_R_CK_GCLK29": null,
"CLK_FEED_R_CK_GCLK3": null,
"CLK_FEED_R_CK_GCLK30": null,
"CLK_FEED_R_CK_GCLK31": null,
"CLK_FEED_R_CK_GCLK4": null,
"CLK_FEED_R_CK_GCLK5": null,
"CLK_FEED_R_CK_GCLK6": null,
"CLK_FEED_R_CK_GCLK7": null,
"CLK_FEED_R_CK_GCLK8": null,
"CLK_FEED_R_CK_GCLK9": null,
"CLK_FEED_SE2A0": null,
"CLK_FEED_SE2A1": null,
"CLK_FEED_SE2A2": null,
"CLK_FEED_SE2A3": null,
"CLK_FEED_SE4BEG0": null,
"CLK_FEED_SE4BEG1": null,
"CLK_FEED_SE4BEG2": null,
"CLK_FEED_SE4BEG3": null,
"CLK_FEED_SE4C0": null,
"CLK_FEED_SE4C1": null,
"CLK_FEED_SE4C2": null,
"CLK_FEED_SE4C3": null,
"CLK_FEED_SW2A0": null,
"CLK_FEED_SW2A1": null,
"CLK_FEED_SW2A2": null,
"CLK_FEED_SW2A3": null,
"CLK_FEED_SW4A0": null,
"CLK_FEED_SW4A1": null,
"CLK_FEED_SW4A2": null,
"CLK_FEED_SW4A3": null,
"CLK_FEED_SW4END0": null,
"CLK_FEED_SW4END1": null,
"CLK_FEED_SW4END2": null,
"CLK_FEED_SW4END3": null,
"CLK_FEED_WL1END0": null,
"CLK_FEED_WL1END1": null,
"CLK_FEED_WL1END2": null,
"CLK_FEED_WL1END3": null,
"CLK_FEED_WR1END0": null,
"CLK_FEED_WR1END1": null,
"CLK_FEED_WR1END2": null,
"CLK_FEED_WR1END3": null,
"CLK_FEED_WW2A0": null,
"CLK_FEED_WW2A1": null,
"CLK_FEED_WW2A2": null,
"CLK_FEED_WW2A3": null,
"CLK_FEED_WW2END0": null,
"CLK_FEED_WW2END1": null,
"CLK_FEED_WW2END2": null,
"CLK_FEED_WW2END3": null,
"CLK_FEED_WW4A0": null,
"CLK_FEED_WW4A1": null,
"CLK_FEED_WW4A2": null,
"CLK_FEED_WW4A3": null,
"CLK_FEED_WW4B0": null,
"CLK_FEED_WW4B1": null,
"CLK_FEED_WW4B2": null,
"CLK_FEED_WW4B3": null,
"CLK_FEED_WW4C0": null,
"CLK_FEED_WW4C1": null,
"CLK_FEED_WW4C2": null,
"CLK_FEED_WW4C3": null,
"CLK_FEED_WW4END0": null,
"CLK_FEED_WW4END1": null,
"CLK_FEED_WW4END2": null,
"CLK_FEED_WW4END3": null,
"CLK_PMV2_A0": null,
"CLK_PMV2_A1": null,
"CLK_PMV2_A2": null,
"CLK_PMV2_EN": null,
"CLK_PMV2_O": null,
"CLK_PMV2_ODIV2": null,
"CLK_PMV2_ODIV4": null,
"CLK_PMV_BYP0_0": null,
"CLK_PMV_BYP1_0": null,
"CLK_PMV_BYP2_0": null,
"CLK_PMV_BYP3_0": null,
"CLK_PMV_BYP4_0": null,
"CLK_PMV_BYP5_0": null,
"CLK_PMV_BYP6_0": null,
"CLK_PMV_BYP7_0": null,
"CLK_PMV_CLK0_0": null,
"CLK_PMV_CLK1_0": null,
"CLK_PMV_CTRL0_0": null,
"CLK_PMV_CTRL1_0": null,
"CLK_PMV_FAN0_0": null,
"CLK_PMV_FAN1_0": null,
"CLK_PMV_FAN2_0": null,
"CLK_PMV_FAN3_0": null,
"CLK_PMV_FAN4_0": null,
"CLK_PMV_FAN5_0": null,
"CLK_PMV_FAN6_0": null,
"CLK_PMV_FAN7_0": null,
"CLK_PMV_IMUX0_0": null,
"CLK_PMV_IMUX10_0": null,
"CLK_PMV_IMUX11_0": null,
"CLK_PMV_IMUX12_0": null,
"CLK_PMV_IMUX13_0": null,
"CLK_PMV_IMUX14_0": null,
"CLK_PMV_IMUX15_0": null,
"CLK_PMV_IMUX16_0": null,
"CLK_PMV_IMUX17_0": null,
"CLK_PMV_IMUX18_0": null,
"CLK_PMV_IMUX19_0": null,
"CLK_PMV_IMUX1_0": null,
"CLK_PMV_IMUX20_0": null,
"CLK_PMV_IMUX21_0": null,
"CLK_PMV_IMUX22_0": null,
"CLK_PMV_IMUX23_0": null,
"CLK_PMV_IMUX24_0": null,
"CLK_PMV_IMUX25_0": null,
"CLK_PMV_IMUX26_0": null,
"CLK_PMV_IMUX27_0": null,
"CLK_PMV_IMUX28_0": null,
"CLK_PMV_IMUX29_0": null,
"CLK_PMV_IMUX2_0": null,
"CLK_PMV_IMUX30_0": null,
"CLK_PMV_IMUX31_0": null,
"CLK_PMV_IMUX32_0": null,
"CLK_PMV_IMUX33_0": null,
"CLK_PMV_IMUX34_0": null,
"CLK_PMV_IMUX35_0": null,
"CLK_PMV_IMUX36_0": null,
"CLK_PMV_IMUX37_0": null,
"CLK_PMV_IMUX38_0": null,
"CLK_PMV_IMUX39_0": null,
"CLK_PMV_IMUX3_0": null,
"CLK_PMV_IMUX40_0": null,
"CLK_PMV_IMUX41_0": null,
"CLK_PMV_IMUX42_0": null,
"CLK_PMV_IMUX43_0": null,
"CLK_PMV_IMUX44_0": null,
"CLK_PMV_IMUX45_0": null,
"CLK_PMV_IMUX46_0": null,
"CLK_PMV_IMUX47_0": null,
"CLK_PMV_IMUX4_0": null,
"CLK_PMV_IMUX5_0": null,
"CLK_PMV_IMUX6_0": null,
"CLK_PMV_IMUX7_0": null,
"CLK_PMV_IMUX8_0": null,
"CLK_PMV_IMUX9_0": null,
"CLK_PMV_LOGIC_OUTS0_0": null,
"CLK_PMV_LOGIC_OUTS10_0": null,
"CLK_PMV_LOGIC_OUTS11_0": null,
"CLK_PMV_LOGIC_OUTS12_0": null,
"CLK_PMV_LOGIC_OUTS13_0": null,
"CLK_PMV_LOGIC_OUTS14_0": null,
"CLK_PMV_LOGIC_OUTS15_0": null,
"CLK_PMV_LOGIC_OUTS16_0": null,
"CLK_PMV_LOGIC_OUTS17_0": null,
"CLK_PMV_LOGIC_OUTS18_0": null,
"CLK_PMV_LOGIC_OUTS19_0": null,
"CLK_PMV_LOGIC_OUTS1_0": null,
"CLK_PMV_LOGIC_OUTS20_0": null,
"CLK_PMV_LOGIC_OUTS21_0": null,
"CLK_PMV_LOGIC_OUTS22_0": null,
"CLK_PMV_LOGIC_OUTS23_0": null,
"CLK_PMV_LOGIC_OUTS2_0": null,
"CLK_PMV_LOGIC_OUTS3_0": null,
"CLK_PMV_LOGIC_OUTS4_0": null,
"CLK_PMV_LOGIC_OUTS5_0": null,
"CLK_PMV_LOGIC_OUTS6_0": null,
"CLK_PMV_LOGIC_OUTS7_0": null,
"CLK_PMV_LOGIC_OUTS8_0": null,
"CLK_PMV_LOGIC_OUTS9_0": null
}
}

708
zynq7/tile_type_CLK_PMVIOB.json
View File

@ -2,358 +2,358 @@
"pips": {},
"sites": [],
"tile_type": "CLK_PMVIOB",
"wires": [
"CLK_FEED_CK_BUFG_CASC0",
"CLK_FEED_CK_BUFG_CASC1",
"CLK_FEED_CK_BUFG_CASC10",
"CLK_FEED_CK_BUFG_CASC11",
"CLK_FEED_CK_BUFG_CASC12",
"CLK_FEED_CK_BUFG_CASC13",
"CLK_FEED_CK_BUFG_CASC14",
"CLK_FEED_CK_BUFG_CASC15",
"CLK_FEED_CK_BUFG_CASC16",
"CLK_FEED_CK_BUFG_CASC17",
"CLK_FEED_CK_BUFG_CASC18",
"CLK_FEED_CK_BUFG_CASC19",
"CLK_FEED_CK_BUFG_CASC2",
"CLK_FEED_CK_BUFG_CASC20",
"CLK_FEED_CK_BUFG_CASC21",
"CLK_FEED_CK_BUFG_CASC22",
"CLK_FEED_CK_BUFG_CASC23",
"CLK_FEED_CK_BUFG_CASC24",
"CLK_FEED_CK_BUFG_CASC25",
"CLK_FEED_CK_BUFG_CASC26",
"CLK_FEED_CK_BUFG_CASC27",
"CLK_FEED_CK_BUFG_CASC28",
"CLK_FEED_CK_BUFG_CASC29",
"CLK_FEED_CK_BUFG_CASC3",
"CLK_FEED_CK_BUFG_CASC30",
"CLK_FEED_CK_BUFG_CASC31",
"CLK_FEED_CK_BUFG_CASC4",
"CLK_FEED_CK_BUFG_CASC5",
"CLK_FEED_CK_BUFG_CASC6",
"CLK_FEED_CK_BUFG_CASC7",
"CLK_FEED_CK_BUFG_CASC8",
"CLK_FEED_CK_BUFG_CASC9",
"CLK_FEED_CK_GCLK0",
"CLK_FEED_CK_GCLK1",
"CLK_FEED_CK_GCLK10",
"CLK_FEED_CK_GCLK11",
"CLK_FEED_CK_GCLK12",
"CLK_FEED_CK_GCLK13",
"CLK_FEED_CK_GCLK14",
"CLK_FEED_CK_GCLK15",
"CLK_FEED_CK_GCLK16",
"CLK_FEED_CK_GCLK17",
"CLK_FEED_CK_GCLK18",
"CLK_FEED_CK_GCLK19",
"CLK_FEED_CK_GCLK2",
"CLK_FEED_CK_GCLK20",
"CLK_FEED_CK_GCLK21",
"CLK_FEED_CK_GCLK22",
"CLK_FEED_CK_GCLK23",
"CLK_FEED_CK_GCLK24",
"CLK_FEED_CK_GCLK25",
"CLK_FEED_CK_GCLK26",
"CLK_FEED_CK_GCLK27",
"CLK_FEED_CK_GCLK28",
"CLK_FEED_CK_GCLK29",
"CLK_FEED_CK_GCLK3",
"CLK_FEED_CK_GCLK30",
"CLK_FEED_CK_GCLK31",
"CLK_FEED_CK_GCLK4",
"CLK_FEED_CK_GCLK5",
"CLK_FEED_CK_GCLK6",
"CLK_FEED_CK_GCLK7",
"CLK_FEED_CK_GCLK8",
"CLK_FEED_CK_GCLK9",
"CLK_FEED_EE2A0",
"CLK_FEED_EE2A1",
"CLK_FEED_EE2A2",
"CLK_FEED_EE2A3",
"CLK_FEED_EE2BEG0",
"CLK_FEED_EE2BEG1",
"CLK_FEED_EE2BEG2",
"CLK_FEED_EE2BEG3",
"CLK_FEED_EE4A0",
"CLK_FEED_EE4A1",
"CLK_FEED_EE4A2",
"CLK_FEED_EE4A3",
"CLK_FEED_EE4B0",
"CLK_FEED_EE4B1",
"CLK_FEED_EE4B2",
"CLK_FEED_EE4B3",
"CLK_FEED_EE4BEG0",
"CLK_FEED_EE4BEG1",
"CLK_FEED_EE4BEG2",
"CLK_FEED_EE4BEG3",
"CLK_FEED_EE4C0",
"CLK_FEED_EE4C1",
"CLK_FEED_EE4C2",
"CLK_FEED_EE4C3",
"CLK_FEED_EL1BEG0",
"CLK_FEED_EL1BEG1",
"CLK_FEED_EL1BEG2",
"CLK_FEED_EL1BEG3",
"CLK_FEED_ER1BEG0",
"CLK_FEED_ER1BEG1",
"CLK_FEED_ER1BEG2",
"CLK_FEED_ER1BEG3",
"CLK_FEED_LH1",
"CLK_FEED_LH10",
"CLK_FEED_LH11",
"CLK_FEED_LH12",
"CLK_FEED_LH2",
"CLK_FEED_LH3",
"CLK_FEED_LH4",
"CLK_FEED_LH5",
"CLK_FEED_LH6",
"CLK_FEED_LH7",
"CLK_FEED_LH8",
"CLK_FEED_LH9",
"CLK_FEED_MONITOR_N",
"CLK_FEED_MONITOR_P",
"CLK_FEED_NE2A0",
"CLK_FEED_NE2A1",
"CLK_FEED_NE2A2",
"CLK_FEED_NE2A3",
"CLK_FEED_NE4BEG0",
"CLK_FEED_NE4BEG1",
"CLK_FEED_NE4BEG2",
"CLK_FEED_NE4BEG3",
"CLK_FEED_NE4C0",
"CLK_FEED_NE4C1",
"CLK_FEED_NE4C2",
"CLK_FEED_NE4C3",
"CLK_FEED_NW2A0",
"CLK_FEED_NW2A1",
"CLK_FEED_NW2A2",
"CLK_FEED_NW2A3",
"CLK_FEED_NW4A0",
"CLK_FEED_NW4A1",
"CLK_FEED_NW4A2",
"CLK_FEED_NW4A3",
"CLK_FEED_NW4END0",
"CLK_FEED_NW4END1",
"CLK_FEED_NW4END2",
"CLK_FEED_NW4END3",
"CLK_FEED_R_CK_BUFG_CASC0",
"CLK_FEED_R_CK_BUFG_CASC1",
"CLK_FEED_R_CK_BUFG_CASC10",
"CLK_FEED_R_CK_BUFG_CASC11",
"CLK_FEED_R_CK_BUFG_CASC12",
"CLK_FEED_R_CK_BUFG_CASC13",
"CLK_FEED_R_CK_BUFG_CASC14",
"CLK_FEED_R_CK_BUFG_CASC15",
"CLK_FEED_R_CK_BUFG_CASC16",
"CLK_FEED_R_CK_BUFG_CASC17",
"CLK_FEED_R_CK_BUFG_CASC18",
"CLK_FEED_R_CK_BUFG_CASC19",
"CLK_FEED_R_CK_BUFG_CASC2",
"CLK_FEED_R_CK_BUFG_CASC20",
"CLK_FEED_R_CK_BUFG_CASC21",
"CLK_FEED_R_CK_BUFG_CASC22",
"CLK_FEED_R_CK_BUFG_CASC23",
"CLK_FEED_R_CK_BUFG_CASC24",
"CLK_FEED_R_CK_BUFG_CASC25",
"CLK_FEED_R_CK_BUFG_CASC26",
"CLK_FEED_R_CK_BUFG_CASC27",
"CLK_FEED_R_CK_BUFG_CASC28",
"CLK_FEED_R_CK_BUFG_CASC29",
"CLK_FEED_R_CK_BUFG_CASC3",
"CLK_FEED_R_CK_BUFG_CASC30",
"CLK_FEED_R_CK_BUFG_CASC31",
"CLK_FEED_R_CK_BUFG_CASC4",
"CLK_FEED_R_CK_BUFG_CASC5",
"CLK_FEED_R_CK_BUFG_CASC6",
"CLK_FEED_R_CK_BUFG_CASC7",
"CLK_FEED_R_CK_BUFG_CASC8",
"CLK_FEED_R_CK_BUFG_CASC9",
"CLK_FEED_R_CK_GCLK0",
"CLK_FEED_R_CK_GCLK1",
"CLK_FEED_R_CK_GCLK10",
"CLK_FEED_R_CK_GCLK11",
"CLK_FEED_R_CK_GCLK12",
"CLK_FEED_R_CK_GCLK13",
"CLK_FEED_R_CK_GCLK14",
"CLK_FEED_R_CK_GCLK15",
"CLK_FEED_R_CK_GCLK16",
"CLK_FEED_R_CK_GCLK17",
"CLK_FEED_R_CK_GCLK18",
"CLK_FEED_R_CK_GCLK19",
"CLK_FEED_R_CK_GCLK2",
"CLK_FEED_R_CK_GCLK20",
"CLK_FEED_R_CK_GCLK21",
"CLK_FEED_R_CK_GCLK22",
"CLK_FEED_R_CK_GCLK23",
"CLK_FEED_R_CK_GCLK24",
"CLK_FEED_R_CK_GCLK25",
"CLK_FEED_R_CK_GCLK26",
"CLK_FEED_R_CK_GCLK27",
"CLK_FEED_R_CK_GCLK28",
"CLK_FEED_R_CK_GCLK29",
"CLK_FEED_R_CK_GCLK3",
"CLK_FEED_R_CK_GCLK30",
"CLK_FEED_R_CK_GCLK31",
"CLK_FEED_R_CK_GCLK4",
"CLK_FEED_R_CK_GCLK5",
"CLK_FEED_R_CK_GCLK6",
"CLK_FEED_R_CK_GCLK7",
"CLK_FEED_R_CK_GCLK8",
"CLK_FEED_R_CK_GCLK9",
"CLK_FEED_SE2A0",
"CLK_FEED_SE2A1",
"CLK_FEED_SE2A2",
"CLK_FEED_SE2A3",
"CLK_FEED_SE4BEG0",
"CLK_FEED_SE4BEG1",
"CLK_FEED_SE4BEG2",
"CLK_FEED_SE4BEG3",
"CLK_FEED_SE4C0",
"CLK_FEED_SE4C1",
"CLK_FEED_SE4C2",
"CLK_FEED_SE4C3",
"CLK_FEED_SW2A0",
"CLK_FEED_SW2A1",
"CLK_FEED_SW2A2",
"CLK_FEED_SW2A3",
"CLK_FEED_SW4A0",
"CLK_FEED_SW4A1",
"CLK_FEED_SW4A2",
"CLK_FEED_SW4A3",
"CLK_FEED_SW4END0",
"CLK_FEED_SW4END1",
"CLK_FEED_SW4END2",
"CLK_FEED_SW4END3",
"CLK_FEED_WL1END0",
"CLK_FEED_WL1END1",
"CLK_FEED_WL1END2",
"CLK_FEED_WL1END3",
"CLK_FEED_WR1END0",
"CLK_FEED_WR1END1",
"CLK_FEED_WR1END2",
"CLK_FEED_WR1END3",
"CLK_FEED_WW2A0",
"CLK_FEED_WW2A1",
"CLK_FEED_WW2A2",
"CLK_FEED_WW2A3",
"CLK_FEED_WW2END0",
"CLK_FEED_WW2END1",
"CLK_FEED_WW2END2",
"CLK_FEED_WW2END3",
"CLK_FEED_WW4A0",
"CLK_FEED_WW4A1",
"CLK_FEED_WW4A2",
"CLK_FEED_WW4A3",
"CLK_FEED_WW4B0",
"CLK_FEED_WW4B1",
"CLK_FEED_WW4B2",
"CLK_FEED_WW4B3",
"CLK_FEED_WW4C0",
"CLK_FEED_WW4C1",
"CLK_FEED_WW4C2",
"CLK_FEED_WW4C3",
"CLK_FEED_WW4END0",
"CLK_FEED_WW4END1",
"CLK_FEED_WW4END2",
"CLK_FEED_WW4END3",
"CLK_PMVIOB_A0",
"CLK_PMVIOB_A1",
"CLK_PMVIOB_EN",
"CLK_PMVIOB_O",
"CLK_PMVIOB_ODIV2",
"CLK_PMVIOB_ODIV4",
"CLK_PMV_BYP0_0",
"CLK_PMV_BYP1_0",
"CLK_PMV_BYP2_0",
"CLK_PMV_BYP3_0",
"CLK_PMV_BYP4_0",
"CLK_PMV_BYP5_0",
"CLK_PMV_BYP6_0",
"CLK_PMV_BYP7_0",
"CLK_PMV_CLK0_0",
"CLK_PMV_CLK1_0",
"CLK_PMV_CTRL0_0",
"CLK_PMV_CTRL1_0",
"CLK_PMV_FAN0_0",
"CLK_PMV_FAN1_0",
"CLK_PMV_FAN2_0",
"CLK_PMV_FAN3_0",
"CLK_PMV_FAN4_0",
"CLK_PMV_FAN5_0",
"CLK_PMV_FAN6_0",
"CLK_PMV_FAN7_0",
"CLK_PMV_IMUX0_0",
"CLK_PMV_IMUX10_0",
"CLK_PMV_IMUX11_0",
"CLK_PMV_IMUX12_0",
"CLK_PMV_IMUX13_0",
"CLK_PMV_IMUX14_0",
"CLK_PMV_IMUX15_0",
"CLK_PMV_IMUX16_0",
"CLK_PMV_IMUX17_0",
"CLK_PMV_IMUX18_0",
"CLK_PMV_IMUX19_0",
"CLK_PMV_IMUX1_0",
"CLK_PMV_IMUX20_0",
"CLK_PMV_IMUX21_0",
"CLK_PMV_IMUX22_0",
"CLK_PMV_IMUX23_0",
"CLK_PMV_IMUX24_0",
"CLK_PMV_IMUX25_0",
"CLK_PMV_IMUX26_0",
"CLK_PMV_IMUX27_0",
"CLK_PMV_IMUX28_0",
"CLK_PMV_IMUX29_0",
"CLK_PMV_IMUX2_0",
"CLK_PMV_IMUX30_0",
"CLK_PMV_IMUX31_0",
"CLK_PMV_IMUX32_0",
"CLK_PMV_IMUX33_0",
"CLK_PMV_IMUX34_0",
"CLK_PMV_IMUX35_0",
"CLK_PMV_IMUX36_0",
"CLK_PMV_IMUX37_0",
"CLK_PMV_IMUX38_0",
"CLK_PMV_IMUX39_0",
"CLK_PMV_IMUX3_0",
"CLK_PMV_IMUX40_0",
"CLK_PMV_IMUX41_0",
"CLK_PMV_IMUX42_0",
"CLK_PMV_IMUX43_0",
"CLK_PMV_IMUX44_0",
"CLK_PMV_IMUX45_0",
"CLK_PMV_IMUX46_0",
"CLK_PMV_IMUX47_0",
"CLK_PMV_IMUX4_0",
"CLK_PMV_IMUX5_0",
"CLK_PMV_IMUX6_0",
"CLK_PMV_IMUX7_0",
"CLK_PMV_IMUX8_0",
"CLK_PMV_IMUX9_0",
"CLK_PMV_LOGIC_OUTS0_0",
"CLK_PMV_LOGIC_OUTS10_0",
"CLK_PMV_LOGIC_OUTS11_0",
"CLK_PMV_LOGIC_OUTS12_0",
"CLK_PMV_LOGIC_OUTS13_0",
"CLK_PMV_LOGIC_OUTS14_0",
"CLK_PMV_LOGIC_OUTS15_0",
"CLK_PMV_LOGIC_OUTS16_0",
"CLK_PMV_LOGIC_OUTS17_0",
"CLK_PMV_LOGIC_OUTS18_0",
"CLK_PMV_LOGIC_OUTS19_0",
"CLK_PMV_LOGIC_OUTS1_0",
"CLK_PMV_LOGIC_OUTS20_0",
"CLK_PMV_LOGIC_OUTS21_0",
"CLK_PMV_LOGIC_OUTS22_0",
"CLK_PMV_LOGIC_OUTS23_0",
"CLK_PMV_LOGIC_OUTS2_0",
"CLK_PMV_LOGIC_OUTS3_0",
"CLK_PMV_LOGIC_OUTS4_0",
"CLK_PMV_LOGIC_OUTS5_0",
"CLK_PMV_LOGIC_OUTS6_0",
"CLK_PMV_LOGIC_OUTS7_0",
"CLK_PMV_LOGIC_OUTS8_0",
"CLK_PMV_LOGIC_OUTS9_0"
]
"wires": {
"CLK_FEED_CK_BUFG_CASC0": null,
"CLK_FEED_CK_BUFG_CASC1": null,
"CLK_FEED_CK_BUFG_CASC10": null,
"CLK_FEED_CK_BUFG_CASC11": null,
"CLK_FEED_CK_BUFG_CASC12": null,
"CLK_FEED_CK_BUFG_CASC13": null,
"CLK_FEED_CK_BUFG_CASC14": null,
"CLK_FEED_CK_BUFG_CASC15": null,
"CLK_FEED_CK_BUFG_CASC16": null,
"CLK_FEED_CK_BUFG_CASC17": null,
"CLK_FEED_CK_BUFG_CASC18": null,
"CLK_FEED_CK_BUFG_CASC19": null,
"CLK_FEED_CK_BUFG_CASC2": null,
"CLK_FEED_CK_BUFG_CASC20": null,
"CLK_FEED_CK_BUFG_CASC21": null,
"CLK_FEED_CK_BUFG_CASC22": null,
"CLK_FEED_CK_BUFG_CASC23": null,
"CLK_FEED_CK_BUFG_CASC24": null,
"CLK_FEED_CK_BUFG_CASC25": null,
"CLK_FEED_CK_BUFG_CASC26": null,
"CLK_FEED_CK_BUFG_CASC27": null,
"CLK_FEED_CK_BUFG_CASC28": null,
"CLK_FEED_CK_BUFG_CASC29": null,
"CLK_FEED_CK_BUFG_CASC3": null,
"CLK_FEED_CK_BUFG_CASC30": null,
"CLK_FEED_CK_BUFG_CASC31": null,
"CLK_FEED_CK_BUFG_CASC4": null,
"CLK_FEED_CK_BUFG_CASC5": null,
"CLK_FEED_CK_BUFG_CASC6": null,
"CLK_FEED_CK_BUFG_CASC7": null,
"CLK_FEED_CK_BUFG_CASC8": null,
"CLK_FEED_CK_BUFG_CASC9": null,
"CLK_FEED_CK_GCLK0": null,
"CLK_FEED_CK_GCLK1": null,
"CLK_FEED_CK_GCLK10": null,
"CLK_FEED_CK_GCLK11": null,
"CLK_FEED_CK_GCLK12": null,
"CLK_FEED_CK_GCLK13": null,
"CLK_FEED_CK_GCLK14": null,
"CLK_FEED_CK_GCLK15": null,
"CLK_FEED_CK_GCLK16": null,
"CLK_FEED_CK_GCLK17": null,
"CLK_FEED_CK_GCLK18": null,
"CLK_FEED_CK_GCLK19": null,
"CLK_FEED_CK_GCLK2": null,
"CLK_FEED_CK_GCLK20": null,
"CLK_FEED_CK_GCLK21": null,
"CLK_FEED_CK_GCLK22": null,
"CLK_FEED_CK_GCLK23": null,
"CLK_FEED_CK_GCLK24": null,
"CLK_FEED_CK_GCLK25": null,
"CLK_FEED_CK_GCLK26": null,
"CLK_FEED_CK_GCLK27": null,
"CLK_FEED_CK_GCLK28": null,
"CLK_FEED_CK_GCLK29": null,
"CLK_FEED_CK_GCLK3": null,
"CLK_FEED_CK_GCLK30": null,
"CLK_FEED_CK_GCLK31": null,
"CLK_FEED_CK_GCLK4": null,
"CLK_FEED_CK_GCLK5": null,
"CLK_FEED_CK_GCLK6": null,
"CLK_FEED_CK_GCLK7": null,
"CLK_FEED_CK_GCLK8": null,
"CLK_FEED_CK_GCLK9": null,
"CLK_FEED_EE2A0": null,
"CLK_FEED_EE2A1": null,
"CLK_FEED_EE2A2": null,
"CLK_FEED_EE2A3": null,
"CLK_FEED_EE2BEG0": null,
"CLK_FEED_EE2BEG1": null,
"CLK_FEED_EE2BEG2": null,
"CLK_FEED_EE2BEG3": null,
"CLK_FEED_EE4A0": null,
"CLK_FEED_EE4A1": null,
"CLK_FEED_EE4A2": null,
"CLK_FEED_EE4A3": null,
"CLK_FEED_EE4B0": null,
"CLK_FEED_EE4B1": null,
"CLK_FEED_EE4B2": null,
"CLK_FEED_EE4B3": null,
"CLK_FEED_EE4BEG0": null,
"CLK_FEED_EE4BEG1": null,
"CLK_FEED_EE4BEG2": null,
"CLK_FEED_EE4BEG3": null,
"CLK_FEED_EE4C0": null,
"CLK_FEED_EE4C1": null,
"CLK_FEED_EE4C2": null,
"CLK_FEED_EE4C3": null,
"CLK_FEED_EL1BEG0": null,
"CLK_FEED_EL1BEG1": null,
"CLK_FEED_EL1BEG2": null,
"CLK_FEED_EL1BEG3": null,
"CLK_FEED_ER1BEG0": null,
"CLK_FEED_ER1BEG1": null,
"CLK_FEED_ER1BEG2": null,
"CLK_FEED_ER1BEG3": null,
"CLK_FEED_LH1": null,
"CLK_FEED_LH10": null,
"CLK_FEED_LH11": null,
"CLK_FEED_LH12": null,
"CLK_FEED_LH2": null,
"CLK_FEED_LH3": null,
"CLK_FEED_LH4": null,
"CLK_FEED_LH5": null,
"CLK_FEED_LH6": null,
"CLK_FEED_LH7": null,
"CLK_FEED_LH8": null,
"CLK_FEED_LH9": null,
"CLK_FEED_MONITOR_N": null,
"CLK_FEED_MONITOR_P": null,
"CLK_FEED_NE2A0": null,
"CLK_FEED_NE2A1": null,
"CLK_FEED_NE2A2": null,
"CLK_FEED_NE2A3": null,
"CLK_FEED_NE4BEG0": null,
"CLK_FEED_NE4BEG1": null,
"CLK_FEED_NE4BEG2": null,
"CLK_FEED_NE4BEG3": null,
"CLK_FEED_NE4C0": null,
"CLK_FEED_NE4C1": null,
"CLK_FEED_NE4C2": null,
"CLK_FEED_NE4C3": null,
"CLK_FEED_NW2A0": null,
"CLK_FEED_NW2A1": null,
"CLK_FEED_NW2A2": null,
"CLK_FEED_NW2A3": null,
"CLK_FEED_NW4A0": null,
"CLK_FEED_NW4A1": null,
"CLK_FEED_NW4A2": null,
"CLK_FEED_NW4A3": null,
"CLK_FEED_NW4END0": null,
"CLK_FEED_NW4END1": null,
"CLK_FEED_NW4END2": null,
"CLK_FEED_NW4END3": null,
"CLK_FEED_R_CK_BUFG_CASC0": null,
"CLK_FEED_R_CK_BUFG_CASC1": null,
"CLK_FEED_R_CK_BUFG_CASC10": null,
"CLK_FEED_R_CK_BUFG_CASC11": null,
"CLK_FEED_R_CK_BUFG_CASC12": null,
"CLK_FEED_R_CK_BUFG_CASC13": null,
"CLK_FEED_R_CK_BUFG_CASC14": null,
"CLK_FEED_R_CK_BUFG_CASC15": null,
"CLK_FEED_R_CK_BUFG_CASC16": null,
"CLK_FEED_R_CK_BUFG_CASC17": null,
"CLK_FEED_R_CK_BUFG_CASC18": null,
"CLK_FEED_R_CK_BUFG_CASC19": null,
"CLK_FEED_R_CK_BUFG_CASC2": null,
"CLK_FEED_R_CK_BUFG_CASC20": null,
"CLK_FEED_R_CK_BUFG_CASC21": null,
"CLK_FEED_R_CK_BUFG_CASC22": null,
"CLK_FEED_R_CK_BUFG_CASC23": null,
"CLK_FEED_R_CK_BUFG_CASC24": null,
"CLK_FEED_R_CK_BUFG_CASC25": null,
"CLK_FEED_R_CK_BUFG_CASC26": null,
"CLK_FEED_R_CK_BUFG_CASC27": null,
"CLK_FEED_R_CK_BUFG_CASC28": null,
"CLK_FEED_R_CK_BUFG_CASC29": null,
"CLK_FEED_R_CK_BUFG_CASC3": null,
"CLK_FEED_R_CK_BUFG_CASC30": null,
"CLK_FEED_R_CK_BUFG_CASC31": null,
"CLK_FEED_R_CK_BUFG_CASC4": null,
"CLK_FEED_R_CK_BUFG_CASC5": null,
"CLK_FEED_R_CK_BUFG_CASC6": null,
"CLK_FEED_R_CK_BUFG_CASC7": null,
"CLK_FEED_R_CK_BUFG_CASC8": null,
"CLK_FEED_R_CK_BUFG_CASC9": null,
"CLK_FEED_R_CK_GCLK0": null,
"CLK_FEED_R_CK_GCLK1": null,
"CLK_FEED_R_CK_GCLK10": null,
"CLK_FEED_R_CK_GCLK11": null,
"CLK_FEED_R_CK_GCLK12": null,
"CLK_FEED_R_CK_GCLK13": null,
"CLK_FEED_R_CK_GCLK14": null,
"CLK_FEED_R_CK_GCLK15": null,
"CLK_FEED_R_CK_GCLK16": null,
"CLK_FEED_R_CK_GCLK17": null,
"CLK_FEED_R_CK_GCLK18": null,
"CLK_FEED_R_CK_GCLK19": null,
"CLK_FEED_R_CK_GCLK2": null,
"CLK_FEED_R_CK_GCLK20": null,
"CLK_FEED_R_CK_GCLK21": null,
"CLK_FEED_R_CK_GCLK22": null,
"CLK_FEED_R_CK_GCLK23": null,
"CLK_FEED_R_CK_GCLK24": null,
"CLK_FEED_R_CK_GCLK25": null,
"CLK_FEED_R_CK_GCLK26": null,
"CLK_FEED_R_CK_GCLK27": null,
"CLK_FEED_R_CK_GCLK28": null,
"CLK_FEED_R_CK_GCLK29": null,
"CLK_FEED_R_CK_GCLK3": null,
"CLK_FEED_R_CK_GCLK30": null,
"CLK_FEED_R_CK_GCLK31": null,
"CLK_FEED_R_CK_GCLK4": null,
"CLK_FEED_R_CK_GCLK5": null,
"CLK_FEED_R_CK_GCLK6": null,
"CLK_FEED_R_CK_GCLK7": null,
"CLK_FEED_R_CK_GCLK8": null,
"CLK_FEED_R_CK_GCLK9": null,
"CLK_FEED_SE2A0": null,
"CLK_FEED_SE2A1": null,
"CLK_FEED_SE2A2": null,
"CLK_FEED_SE2A3": null,
"CLK_FEED_SE4BEG0": null,
"CLK_FEED_SE4BEG1": null,
"CLK_FEED_SE4BEG2": null,
"CLK_FEED_SE4BEG3": null,
"CLK_FEED_SE4C0": null,
"CLK_FEED_SE4C1": null,
"CLK_FEED_SE4C2": null,
"CLK_FEED_SE4C3": null,
"CLK_FEED_SW2A0": null,
"CLK_FEED_SW2A1": null,
"CLK_FEED_SW2A2": null,
"CLK_FEED_SW2A3": null,
"CLK_FEED_SW4A0": null,
"CLK_FEED_SW4A1": null,
"CLK_FEED_SW4A2": null,
"CLK_FEED_SW4A3": null,
"CLK_FEED_SW4END0": null,
"CLK_FEED_SW4END1": null,
"CLK_FEED_SW4END2": null,
"CLK_FEED_SW4END3": null,
"CLK_FEED_WL1END0": null,
"CLK_FEED_WL1END1": null,
"CLK_FEED_WL1END2": null,
"CLK_FEED_WL1END3": null,
"CLK_FEED_WR1END0": null,
"CLK_FEED_WR1END1": null,
"CLK_FEED_WR1END2": null,
"CLK_FEED_WR1END3": null,
"CLK_FEED_WW2A0": null,
"CLK_FEED_WW2A1": null,
"CLK_FEED_WW2A2": null,
"CLK_FEED_WW2A3": null,
"CLK_FEED_WW2END0": null,
"CLK_FEED_WW2END1": null,
"CLK_FEED_WW2END2": null,
"CLK_FEED_WW2END3": null,
"CLK_FEED_WW4A0": null,
"CLK_FEED_WW4A1": null,
"CLK_FEED_WW4A2": null,
"CLK_FEED_WW4A3": null,
"CLK_FEED_WW4B0": null,
"CLK_FEED_WW4B1": null,
"CLK_FEED_WW4B2": null,
"CLK_FEED_WW4B3": null,
"CLK_FEED_WW4C0": null,
"CLK_FEED_WW4C1": null,
"CLK_FEED_WW4C2": null,
"CLK_FEED_WW4C3": null,
"CLK_FEED_WW4END0": null,
"CLK_FEED_WW4END1": null,
"CLK_FEED_WW4END2": null,
"CLK_FEED_WW4END3": null,
"CLK_PMVIOB_A0": null,
"CLK_PMVIOB_A1": null,
"CLK_PMVIOB_EN": null,
"CLK_PMVIOB_O": null,
"CLK_PMVIOB_ODIV2": null,
"CLK_PMVIOB_ODIV4": null,
"CLK_PMV_BYP0_0": null,
"CLK_PMV_BYP1_0": null,
"CLK_PMV_BYP2_0": null,
"CLK_PMV_BYP3_0": null,
"CLK_PMV_BYP4_0": null,
"CLK_PMV_BYP5_0": null,
"CLK_PMV_BYP6_0": null,
"CLK_PMV_BYP7_0": null,
"CLK_PMV_CLK0_0": null,
"CLK_PMV_CLK1_0": null,
"CLK_PMV_CTRL0_0": null,
"CLK_PMV_CTRL1_0": null,
"CLK_PMV_FAN0_0": null,
"CLK_PMV_FAN1_0": null,
"CLK_PMV_FAN2_0": null,
"CLK_PMV_FAN3_0": null,
"CLK_PMV_FAN4_0": null,
"CLK_PMV_FAN5_0": null,
"CLK_PMV_FAN6_0": null,
"CLK_PMV_FAN7_0": null,
"CLK_PMV_IMUX0_0": null,
"CLK_PMV_IMUX10_0": null,
"CLK_PMV_IMUX11_0": null,
"CLK_PMV_IMUX12_0": null,
"CLK_PMV_IMUX13_0": null,
"CLK_PMV_IMUX14_0": null,
"CLK_PMV_IMUX15_0": null,
"CLK_PMV_IMUX16_0": null,
"CLK_PMV_IMUX17_0": null,
"CLK_PMV_IMUX18_0": null,
"CLK_PMV_IMUX19_0": null,
"CLK_PMV_IMUX1_0": null,
"CLK_PMV_IMUX20_0": null,
"CLK_PMV_IMUX21_0": null,
"CLK_PMV_IMUX22_0": null,
"CLK_PMV_IMUX23_0": null,
"CLK_PMV_IMUX24_0": null,
"CLK_PMV_IMUX25_0": null,
"CLK_PMV_IMUX26_0": null,
"CLK_PMV_IMUX27_0": null,
"CLK_PMV_IMUX28_0": null,
"CLK_PMV_IMUX29_0": null,
"CLK_PMV_IMUX2_0": null,
"CLK_PMV_IMUX30_0": null,
"CLK_PMV_IMUX31_0": null,
"CLK_PMV_IMUX32_0": null,
"CLK_PMV_IMUX33_0": null,
"CLK_PMV_IMUX34_0": null,
"CLK_PMV_IMUX35_0": null,
"CLK_PMV_IMUX36_0": null,
"CLK_PMV_IMUX37_0": null,
"CLK_PMV_IMUX38_0": null,
"CLK_PMV_IMUX39_0": null,
"CLK_PMV_IMUX3_0": null,
"CLK_PMV_IMUX40_0": null,
"CLK_PMV_IMUX41_0": null,
"CLK_PMV_IMUX42_0": null,
"CLK_PMV_IMUX43_0": null,
"CLK_PMV_IMUX44_0": null,
"CLK_PMV_IMUX45_0": null,
"CLK_PMV_IMUX46_0": null,
"CLK_PMV_IMUX47_0": null,
"CLK_PMV_IMUX4_0": null,
"CLK_PMV_IMUX5_0": null,
"CLK_PMV_IMUX6_0": null,
"CLK_PMV_IMUX7_0": null,
"CLK_PMV_IMUX8_0": null,
"CLK_PMV_IMUX9_0": null,
"CLK_PMV_LOGIC_OUTS0_0": null,
"CLK_PMV_LOGIC_OUTS10_0": null,
"CLK_PMV_LOGIC_OUTS11_0": null,
"CLK_PMV_LOGIC_OUTS12_0": null,
"CLK_PMV_LOGIC_OUTS13_0": null,
"CLK_PMV_LOGIC_OUTS14_0": null,
"CLK_PMV_LOGIC_OUTS15_0": null,
"CLK_PMV_LOGIC_OUTS16_0": null,
"CLK_PMV_LOGIC_OUTS17_0": null,
"CLK_PMV_LOGIC_OUTS18_0": null,
"CLK_PMV_LOGIC_OUTS19_0": null,
"CLK_PMV_LOGIC_OUTS1_0": null,
"CLK_PMV_LOGIC_OUTS20_0": null,
"CLK_PMV_LOGIC_OUTS21_0": null,
"CLK_PMV_LOGIC_OUTS22_0": null,
"CLK_PMV_LOGIC_OUTS23_0": null,
"CLK_PMV_LOGIC_OUTS2_0": null,
"CLK_PMV_LOGIC_OUTS3_0": null,
"CLK_PMV_LOGIC_OUTS4_0": null,
"CLK_PMV_LOGIC_OUTS5_0": null,
"CLK_PMV_LOGIC_OUTS6_0": null,
"CLK_PMV_LOGIC_OUTS7_0": null,
"CLK_PMV_LOGIC_OUTS8_0": null,
"CLK_PMV_LOGIC_OUTS9_0": null
}
}

132
zynq7/tile_type_CLK_TERM.json
View File

@ -2,70 +2,70 @@
"pips": {},
"sites": [],
"tile_type": "CLK_TERM",
"wires": [
"CLK_TERM_GCLK0",
"CLK_TERM_GCLK1",
"CLK_TERM_GCLK10",
"CLK_TERM_GCLK11",
"CLK_TERM_GCLK12",
"CLK_TERM_GCLK13",
"CLK_TERM_GCLK14",
"CLK_TERM_GCLK15",
"CLK_TERM_GCLK16",
"CLK_TERM_GCLK17",
"CLK_TERM_GCLK18",
"CLK_TERM_GCLK19",
"CLK_TERM_GCLK2",
"CLK_TERM_GCLK20",
"CLK_TERM_GCLK21",
"CLK_TERM_GCLK22",
"CLK_TERM_GCLK23",
"CLK_TERM_GCLK24",
"CLK_TERM_GCLK25",
"CLK_TERM_GCLK26",
"CLK_TERM_GCLK27",
"CLK_TERM_GCLK28",
"CLK_TERM_GCLK29",
"CLK_TERM_GCLK3",
"CLK_TERM_GCLK30",
"CLK_TERM_GCLK31",
"CLK_TERM_GCLK4",
"CLK_TERM_GCLK5",
"CLK_TERM_GCLK6",
"CLK_TERM_GCLK7",
"CLK_TERM_GCLK8",
"CLK_TERM_GCLK9",
"CLK_TERM_R_GCLK0",
"CLK_TERM_R_GCLK1",
"CLK_TERM_R_GCLK10",
"CLK_TERM_R_GCLK11",
"CLK_TERM_R_GCLK12",
"CLK_TERM_R_GCLK13",
"CLK_TERM_R_GCLK14",
"CLK_TERM_R_GCLK15",
"CLK_TERM_R_GCLK16",
"CLK_TERM_R_GCLK17",
"CLK_TERM_R_GCLK18",
"CLK_TERM_R_GCLK19",
"CLK_TERM_R_GCLK2",
"CLK_TERM_R_GCLK20",
"CLK_TERM_R_GCLK21",
"CLK_TERM_R_GCLK22",
"CLK_TERM_R_GCLK23",
"CLK_TERM_R_GCLK24",
"CLK_TERM_R_GCLK25",
"CLK_TERM_R_GCLK26",
"CLK_TERM_R_GCLK27",
"CLK_TERM_R_GCLK28",
"CLK_TERM_R_GCLK29",
"CLK_TERM_R_GCLK3",
"CLK_TERM_R_GCLK30",
"CLK_TERM_R_GCLK31",
"CLK_TERM_R_GCLK4",
"CLK_TERM_R_GCLK5",
"CLK_TERM_R_GCLK6",
"CLK_TERM_R_GCLK7",
"CLK_TERM_R_GCLK8",
"CLK_TERM_R_GCLK9"
]
"wires": {
"CLK_TERM_GCLK0": null,
"CLK_TERM_GCLK1": null,
"CLK_TERM_GCLK10": null,
"CLK_TERM_GCLK11": null,
"CLK_TERM_GCLK12": null,
"CLK_TERM_GCLK13": null,
"CLK_TERM_GCLK14": null,
"CLK_TERM_GCLK15": null,
"CLK_TERM_GCLK16": null,
"CLK_TERM_GCLK17": null,
"CLK_TERM_GCLK18": null,
"CLK_TERM_GCLK19": null,
"CLK_TERM_GCLK2": null,
"CLK_TERM_GCLK20": null,
"CLK_TERM_GCLK21": null,
"CLK_TERM_GCLK22": null,
"CLK_TERM_GCLK23": null,
"CLK_TERM_GCLK24": null,
"CLK_TERM_GCLK25": null,
"CLK_TERM_GCLK26": null,
"CLK_TERM_GCLK27": null,
"CLK_TERM_GCLK28": null,
"CLK_TERM_GCLK29": null,
"CLK_TERM_GCLK3": null,
"CLK_TERM_GCLK30": null,
"CLK_TERM_GCLK31": null,
"CLK_TERM_GCLK4": null,
"CLK_TERM_GCLK5": null,
"CLK_TERM_GCLK6": null,
"CLK_TERM_GCLK7": null,
"CLK_TERM_GCLK8": null,
"CLK_TERM_GCLK9": null,
"CLK_TERM_R_GCLK0": null,
"CLK_TERM_R_GCLK1": null,
"CLK_TERM_R_GCLK10": null,
"CLK_TERM_R_GCLK11": null,
"CLK_TERM_R_GCLK12": null,
"CLK_TERM_R_GCLK13": null,
"CLK_TERM_R_GCLK14": null,
"CLK_TERM_R_GCLK15": null,
"CLK_TERM_R_GCLK16": null,
"CLK_TERM_R_GCLK17": null,
"CLK_TERM_R_GCLK18": null,
"CLK_TERM_R_GCLK19": null,
"CLK_TERM_R_GCLK2": null,
"CLK_TERM_R_GCLK20": null,
"CLK_TERM_R_GCLK21": null,
"CLK_TERM_R_GCLK22": null,
"CLK_TERM_R_GCLK23": null,
"CLK_TERM_R_GCLK24": null,
"CLK_TERM_R_GCLK25": null,
"CLK_TERM_R_GCLK26": null,
"CLK_TERM_R_GCLK27": null,
"CLK_TERM_R_GCLK28": null,
"CLK_TERM_R_GCLK29": null,
"CLK_TERM_R_GCLK3": null,
"CLK_TERM_R_GCLK30": null,
"CLK_TERM_R_GCLK31": null,
"CLK_TERM_R_GCLK4": null,
"CLK_TERM_R_GCLK5": null,
"CLK_TERM_R_GCLK6": null,
"CLK_TERM_R_GCLK7": null,
"CLK_TERM_R_GCLK8": null,
"CLK_TERM_R_GCLK9": null
}
}

17678
zynq7/tile_type_CMT_FIFO_L.json
View File

File diff suppressed because it is too large Load Diff

822
zynq7/tile_type_CMT_PMV_L.json
View File

@ -2,229 +2,601 @@
"pips": {},
"sites": [],
"tile_type": "CMT_PMV_L",
"wires": [
"CMT_PMV_BYP0",
"CMT_PMV_BYP1",
"CMT_PMV_BYP2",
"CMT_PMV_BYP3",
"CMT_PMV_BYP4",
"CMT_PMV_BYP5",
"CMT_PMV_BYP6",
"CMT_PMV_BYP7",
"CMT_PMV_CLK0",
"CMT_PMV_CLK1",
"CMT_PMV_CTRL0",
"CMT_PMV_CTRL1",
"CMT_PMV_EE2A0",
"CMT_PMV_EE2A1",
"CMT_PMV_EE2A2",
"CMT_PMV_EE2A3",
"CMT_PMV_EE2BEG0",
"CMT_PMV_EE2BEG1",
"CMT_PMV_EE2BEG2",
"CMT_PMV_EE2BEG3",
"CMT_PMV_EE4A0",
"CMT_PMV_EE4A1",
"CMT_PMV_EE4A2",
"CMT_PMV_EE4A3",
"CMT_PMV_EE4B0",
"CMT_PMV_EE4B1",
"CMT_PMV_EE4B2",
"CMT_PMV_EE4B3",
"CMT_PMV_EE4BEG0",
"CMT_PMV_EE4BEG1",
"CMT_PMV_EE4BEG2",
"CMT_PMV_EE4BEG3",
"CMT_PMV_EE4C0",
"CMT_PMV_EE4C1",
"CMT_PMV_EE4C2",
"CMT_PMV_EE4C3",
"CMT_PMV_EL1BEG0",
"CMT_PMV_EL1BEG1",
"CMT_PMV_EL1BEG2",
"CMT_PMV_EL1BEG3",
"CMT_PMV_ER1BEG0",
"CMT_PMV_ER1BEG1",
"CMT_PMV_ER1BEG2",
"CMT_PMV_ER1BEG3",
"CMT_PMV_FAN0",
"CMT_PMV_FAN1",
"CMT_PMV_FAN2",
"CMT_PMV_FAN3",
"CMT_PMV_FAN4",
"CMT_PMV_FAN5",
"CMT_PMV_FAN6",
"CMT_PMV_FAN7",
"CMT_PMV_IMUX0",
"CMT_PMV_IMUX1",
"CMT_PMV_IMUX10",
"CMT_PMV_IMUX11",
"CMT_PMV_IMUX12",
"CMT_PMV_IMUX13",
"CMT_PMV_IMUX14",
"CMT_PMV_IMUX15",
"CMT_PMV_IMUX16",
"CMT_PMV_IMUX17",
"CMT_PMV_IMUX18",
"CMT_PMV_IMUX19",
"CMT_PMV_IMUX2",
"CMT_PMV_IMUX20",
"CMT_PMV_IMUX21",
"CMT_PMV_IMUX22",
"CMT_PMV_IMUX23",
"CMT_PMV_IMUX24",
"CMT_PMV_IMUX25",
"CMT_PMV_IMUX26",
"CMT_PMV_IMUX27",
"CMT_PMV_IMUX28",
"CMT_PMV_IMUX29",
"CMT_PMV_IMUX3",
"CMT_PMV_IMUX30",
"CMT_PMV_IMUX31",
"CMT_PMV_IMUX32",
"CMT_PMV_IMUX33",
"CMT_PMV_IMUX34",
"CMT_PMV_IMUX35",
"CMT_PMV_IMUX36",
"CMT_PMV_IMUX37",
"CMT_PMV_IMUX38",
"CMT_PMV_IMUX39",
"CMT_PMV_IMUX4",
"CMT_PMV_IMUX40",
"CMT_PMV_IMUX41",
"CMT_PMV_IMUX42",
"CMT_PMV_IMUX43",
"CMT_PMV_IMUX44",
"CMT_PMV_IMUX45",
"CMT_PMV_IMUX46",
"CMT_PMV_IMUX47",
"CMT_PMV_IMUX5",
"CMT_PMV_IMUX6",
"CMT_PMV_IMUX7",
"CMT_PMV_IMUX8",
"CMT_PMV_IMUX9",
"CMT_PMV_LH1",
"CMT_PMV_LH10",
"CMT_PMV_LH11",
"CMT_PMV_LH12",
"CMT_PMV_LH2",
"CMT_PMV_LH3",
"CMT_PMV_LH4",
"CMT_PMV_LH5",
"CMT_PMV_LH6",
"CMT_PMV_LH7",
"CMT_PMV_LH8",
"CMT_PMV_LH9",
"CMT_PMV_LOGIC_OUTS0",
"CMT_PMV_LOGIC_OUTS1",
"CMT_PMV_LOGIC_OUTS10",
"CMT_PMV_LOGIC_OUTS11",
"CMT_PMV_LOGIC_OUTS12",
"CMT_PMV_LOGIC_OUTS13",
"CMT_PMV_LOGIC_OUTS14",
"CMT_PMV_LOGIC_OUTS15",
"CMT_PMV_LOGIC_OUTS16",
"CMT_PMV_LOGIC_OUTS17",
"CMT_PMV_LOGIC_OUTS18",
"CMT_PMV_LOGIC_OUTS19",
"CMT_PMV_LOGIC_OUTS2",
"CMT_PMV_LOGIC_OUTS20",
"CMT_PMV_LOGIC_OUTS21",
"CMT_PMV_LOGIC_OUTS22",
"CMT_PMV_LOGIC_OUTS23",
"CMT_PMV_LOGIC_OUTS3",
"CMT_PMV_LOGIC_OUTS4",
"CMT_PMV_LOGIC_OUTS5",
"CMT_PMV_LOGIC_OUTS6",
"CMT_PMV_LOGIC_OUTS7",
"CMT_PMV_LOGIC_OUTS8",
"CMT_PMV_LOGIC_OUTS9",
"CMT_PMV_MONITOR_N",
"CMT_PMV_MONITOR_P",
"CMT_PMV_NE2A0",
"CMT_PMV_NE2A1",
"CMT_PMV_NE2A2",
"CMT_PMV_NE2A3",
"CMT_PMV_NE4BEG0",
"CMT_PMV_NE4BEG1",
"CMT_PMV_NE4BEG2",
"CMT_PMV_NE4BEG3",
"CMT_PMV_NE4C0",
"CMT_PMV_NE4C1",
"CMT_PMV_NE4C2",
"CMT_PMV_NE4C3",
"CMT_PMV_NW2A0",
"CMT_PMV_NW2A1",
"CMT_PMV_NW2A2",
"CMT_PMV_NW2A3",
"CMT_PMV_NW4A0",
"CMT_PMV_NW4A1",
"CMT_PMV_NW4A2",
"CMT_PMV_NW4A3",
"CMT_PMV_NW4END0",
"CMT_PMV_NW4END1",
"CMT_PMV_NW4END2",
"CMT_PMV_NW4END3",
"CMT_PMV_SE2A0",
"CMT_PMV_SE2A1",
"CMT_PMV_SE2A2",
"CMT_PMV_SE2A3",
"CMT_PMV_SE4BEG0",
"CMT_PMV_SE4BEG1",
"CMT_PMV_SE4BEG2",
"CMT_PMV_SE4BEG3",
"CMT_PMV_SE4C0",
"CMT_PMV_SE4C1",
"CMT_PMV_SE4C2",
"CMT_PMV_SE4C3",
"CMT_PMV_SW2A0",
"CMT_PMV_SW2A1",
"CMT_PMV_SW2A2",
"CMT_PMV_SW2A3",
"CMT_PMV_SW4A0",
"CMT_PMV_SW4A1",
"CMT_PMV_SW4A2",
"CMT_PMV_SW4A3",
"CMT_PMV_SW4END0",
"CMT_PMV_SW4END1",
"CMT_PMV_SW4END2",
"CMT_PMV_SW4END3",
"CMT_PMV_WL1END0",
"CMT_PMV_WL1END1",
"CMT_PMV_WL1END2",
"CMT_PMV_WL1END3",
"CMT_PMV_WR1END0",
"CMT_PMV_WR1END1",
"CMT_PMV_WR1END2",
"CMT_PMV_WR1END3",
"CMT_PMV_WW2A0",
"CMT_PMV_WW2A1",
"CMT_PMV_WW2A2",
"CMT_PMV_WW2A3",
"CMT_PMV_WW2END0",
"CMT_PMV_WW2END1",
"CMT_PMV_WW2END2",
"CMT_PMV_WW2END3",
"CMT_PMV_WW4A0",
"CMT_PMV_WW4A1",
"CMT_PMV_WW4A2",
"CMT_PMV_WW4A3",
"CMT_PMV_WW4B0",
"CMT_PMV_WW4B1",
"CMT_PMV_WW4B2",
"CMT_PMV_WW4B3",
"CMT_PMV_WW4C0",
"CMT_PMV_WW4C1",
"CMT_PMV_WW4C2",
"CMT_PMV_WW4C3",
"CMT_PMV_WW4END0",
"CMT_PMV_WW4END1",
"CMT_PMV_WW4END2",
"CMT_PMV_WW4END3",
"L_TERM_INT_PHASER_TO_IO_ICLK",
"L_TERM_INT_PHASER_TO_IO_ICLKDIV",
"L_TERM_INT_PHASER_TO_IO_OCLK",
"L_TERM_INT_PHASER_TO_IO_OCLK1X_90",
"L_TERM_INT_PHASER_TO_IO_OCLKDIV"
]
"wires": {
"CMT_PMV_BYP0": null,
"CMT_PMV_BYP1": null,
"CMT_PMV_BYP2": null,
"CMT_PMV_BYP3": null,
"CMT_PMV_BYP4": null,
"CMT_PMV_BYP5": null,
"CMT_PMV_BYP6": null,
"CMT_PMV_BYP7": null,
"CMT_PMV_CLK0": null,
"CMT_PMV_CLK1": null,
"CMT_PMV_CTRL0": null,
"CMT_PMV_CTRL1": null,
"CMT_PMV_EE2A0": {
"cap": "22.067",
"res": "317.510"
},
"CMT_PMV_EE2A1": {
"cap": "22.067",
"res": "317.510"
},
"CMT_PMV_EE2A2": {
"cap": "22.067",
"res": "317.510"
},
"CMT_PMV_EE2A3": {
"cap": "22.067",
"res": "317.510"
},
"CMT_PMV_EE2BEG0": {
"cap": "22.067",
"res": "317.510"
},
"CMT_PMV_EE2BEG1": {
"cap": "22.067",
"res": "317.510"
},
"CMT_PMV_EE2BEG2": {
"cap": "22.067",
"res": "317.510"
},
"CMT_PMV_EE2BEG3": {
"cap": "22.067",
"res": "317.510"
},
"CMT_PMV_EE4A0": {
"cap": "18.000",
"res": "317.510"
},
"CMT_PMV_EE4A1": {
"cap": "18.000",
"res": "317.510"
},
"CMT_PMV_EE4A2": {
"cap": "18.000",
"res": "317.510"
},
"CMT_PMV_EE4A3": {
"cap": "18.000",
"res": "317.510"
},
"CMT_PMV_EE4B0": {
"cap": "18.000",
"res": "317.510"
},
"CMT_PMV_EE4B1": {
"cap": "18.000",
"res": "317.510"
},
"CMT_PMV_EE4B2": {
"cap": "18.000",
"res": "317.510"
},
"CMT_PMV_EE4B3": {
"cap": "18.000",
"res": "317.510"
},
"CMT_PMV_EE4BEG0": {
"cap": "18.000",
"res": "317.510"
},
"CMT_PMV_EE4BEG1": {
"cap": "18.000",
"res": "317.510"
},
"CMT_PMV_EE4BEG2": {
"cap": "18.000",
"res": "317.510"
},
"CMT_PMV_EE4BEG3": {
"cap": "18.000",
"res": "317.510"
},
"CMT_PMV_EE4C0": {
"cap": "18.000",
"res": "317.510"
},
"CMT_PMV_EE4C1": {
"cap": "18.000",
"res": "317.510"
},
"CMT_PMV_EE4C2": {
"cap": "18.000",
"res": "317.510"
},
"CMT_PMV_EE4C3": {
"cap": "18.000",
"res": "317.510"
},
"CMT_PMV_EL1BEG0": {
"cap": "25.000",
"res": "317.510"
},
"CMT_PMV_EL1BEG1": {
"cap": "25.000",
"res": "317.510"
},
"CMT_PMV_EL1BEG2": {
"cap": "25.000",
"res": "317.510"
},
"CMT_PMV_EL1BEG3": {
"cap": "25.000",
"res": "317.510"
},
"CMT_PMV_ER1BEG0": {
"cap": "25.000",
"res": "317.510"
},
"CMT_PMV_ER1BEG1": {
"cap": "25.000",
"res": "317.510"
},
"CMT_PMV_ER1BEG2": {
"cap": "25.000",
"res": "317.510"
},
"CMT_PMV_ER1BEG3": {
"cap": "25.000",
"res": "317.510"
},
"CMT_PMV_FAN0": null,
"CMT_PMV_FAN1": null,
"CMT_PMV_FAN2": null,
"CMT_PMV_FAN3": null,
"CMT_PMV_FAN4": null,
"CMT_PMV_FAN5": null,
"CMT_PMV_FAN6": null,
"CMT_PMV_FAN7": null,
"CMT_PMV_IMUX0": null,
"CMT_PMV_IMUX1": null,
"CMT_PMV_IMUX10": null,
"CMT_PMV_IMUX11": null,
"CMT_PMV_IMUX12": null,
"CMT_PMV_IMUX13": null,
"CMT_PMV_IMUX14": null,
"CMT_PMV_IMUX15": null,
"CMT_PMV_IMUX16": null,
"CMT_PMV_IMUX17": null,
"CMT_PMV_IMUX18": null,
"CMT_PMV_IMUX19": null,
"CMT_PMV_IMUX2": null,
"CMT_PMV_IMUX20": null,
"CMT_PMV_IMUX21": null,
"CMT_PMV_IMUX22": null,
"CMT_PMV_IMUX23": null,
"CMT_PMV_IMUX24": null,
"CMT_PMV_IMUX25": null,
"CMT_PMV_IMUX26": null,
"CMT_PMV_IMUX27": null,
"CMT_PMV_IMUX28": null,
"CMT_PMV_IMUX29": null,
"CMT_PMV_IMUX3": null,
"CMT_PMV_IMUX30": null,
"CMT_PMV_IMUX31": null,
"CMT_PMV_IMUX32": null,
"CMT_PMV_IMUX33": null,
"CMT_PMV_IMUX34": null,
"CMT_PMV_IMUX35": null,
"CMT_PMV_IMUX36": null,
"CMT_PMV_IMUX37": null,
"CMT_PMV_IMUX38": null,
"CMT_PMV_IMUX39": null,
"CMT_PMV_IMUX4": null,
"CMT_PMV_IMUX40": null,
"CMT_PMV_IMUX41": null,
"CMT_PMV_IMUX42": null,
"CMT_PMV_IMUX43": null,
"CMT_PMV_IMUX44": null,
"CMT_PMV_IMUX45": null,
"CMT_PMV_IMUX46": null,
"CMT_PMV_IMUX47": null,
"CMT_PMV_IMUX5": null,
"CMT_PMV_IMUX6": null,
"CMT_PMV_IMUX7": null,
"CMT_PMV_IMUX8": null,
"CMT_PMV_IMUX9": null,
"CMT_PMV_LH1": {
"cap": "60.260",
"res": "15.190"
},
"CMT_PMV_LH10": {
"cap": "60.260",
"res": "15.190"
},
"CMT_PMV_LH11": {
"cap": "60.260",
"res": "15.190"
},
"CMT_PMV_LH12": {
"cap": "60.260",
"res": "15.190"
},
"CMT_PMV_LH2": {
"cap": "60.260",
"res": "15.190"
},
"CMT_PMV_LH3": {
"cap": "60.260",
"res": "15.190"
},
"CMT_PMV_LH4": {
"cap": "60.260",
"res": "15.190"
},
"CMT_PMV_LH5": {
"cap": "60.260",
"res": "15.190"
},
"CMT_PMV_LH6": {
"cap": "60.260",
"res": "15.190"
},
"CMT_PMV_LH7": {
"cap": "60.260",
"res": "15.190"
},
"CMT_PMV_LH8": {
"cap": "60.260",
"res": "15.190"
},
"CMT_PMV_LH9": {
"cap": "60.260",
"res": "15.190"
},
"CMT_PMV_LOGIC_OUTS0": null,
"CMT_PMV_LOGIC_OUTS1": null,
"CMT_PMV_LOGIC_OUTS10": null,
"CMT_PMV_LOGIC_OUTS11": null,
"CMT_PMV_LOGIC_OUTS12": null,
"CMT_PMV_LOGIC_OUTS13": null,
"CMT_PMV_LOGIC_OUTS14": null,
"CMT_PMV_LOGIC_OUTS15": null,
"CMT_PMV_LOGIC_OUTS16": null,
"CMT_PMV_LOGIC_OUTS17": null,
"CMT_PMV_LOGIC_OUTS18": null,
"CMT_PMV_LOGIC_OUTS19": null,
"CMT_PMV_LOGIC_OUTS2": null,
"CMT_PMV_LOGIC_OUTS20": null,
"CMT_PMV_LOGIC_OUTS21": null,
"CMT_PMV_LOGIC_OUTS22": null,
"CMT_PMV_LOGIC_OUTS23": null,
"CMT_PMV_LOGIC_OUTS3": null,
"CMT_PMV_LOGIC_OUTS4": null,
"CMT_PMV_LOGIC_OUTS5": null,
"CMT_PMV_LOGIC_OUTS6": null,
"CMT_PMV_LOGIC_OUTS7": null,
"CMT_PMV_LOGIC_OUTS8": null,
"CMT_PMV_LOGIC_OUTS9": null,
"CMT_PMV_MONITOR_N": null,
"CMT_PMV_MONITOR_P": null,
"CMT_PMV_NE2A0": {
"cap": "22.067",
"res": "317.510"
},
"CMT_PMV_NE2A1": {
"cap": "22.067",
"res": "317.510"
},
"CMT_PMV_NE2A2": {
"cap": "22.067",
"res": "317.510"
},
"CMT_PMV_NE2A3": {
"cap": "22.067",
"res": "317.510"
},
"CMT_PMV_NE4BEG0": {
"cap": "18.000",
"res": "317.510"
},
"CMT_PMV_NE4BEG1": {
"cap": "18.000",
"res": "317.510"
},
"CMT_PMV_NE4BEG2": {
"cap": "18.000",
"res": "317.510"
},
"CMT_PMV_NE4BEG3": {
"cap": "18.000",
"res": "317.510"
},
"CMT_PMV_NE4C0": {
"cap": "18.000",
"res": "317.510"
},
"CMT_PMV_NE4C1": {
"cap": "18.000",
"res": "317.510"
},
"CMT_PMV_NE4C2": {
"cap": "18.000",
"res": "317.510"
},
"CMT_PMV_NE4C3": {
"cap": "18.000",
"res": "317.510"
},
"CMT_PMV_NW2A0": {
"cap": "22.067",
"res": "317.510"
},
"CMT_PMV_NW2A1": {
"cap": "22.067",
"res": "317.510"
},
"CMT_PMV_NW2A2": {
"cap": "22.067",
"res": "317.510"
},
"CMT_PMV_NW2A3": {
"cap": "22.067",
"res": "317.510"
},
"CMT_PMV_NW4A0": {
"cap": "18.000",
"res": "317.510"
},
"CMT_PMV_NW4A1": {
"cap": "18.000",
"res": "317.510"
},
"CMT_PMV_NW4A2": {
"cap": "18.000",
"res": "317.510"
},
"CMT_PMV_NW4A3": {
"cap": "18.000",
"res": "317.510"
},
"CMT_PMV_NW4END0": {
"cap": "18.000",
"res": "317.510"
},
"CMT_PMV_NW4END1": {
"cap": "18.000",
"res": "317.510"
},
"CMT_PMV_NW4END2": {
"cap": "18.000",
"res": "317.510"
},
"CMT_PMV_NW4END3": {
"cap": "18.000",
"res": "317.510"
},
"CMT_PMV_SE2A0": {
"cap": "22.067",
"res": "317.510"
},
"CMT_PMV_SE2A1": {
"cap": "22.067",
"res": "317.510"
},
"CMT_PMV_SE2A2": {
"cap": "22.067",
"res": "317.510"
},
"CMT_PMV_SE2A3": {
"cap": "22.067",
"res": "317.510"
},
"CMT_PMV_SE4BEG0": {
"cap": "18.000",
"res": "317.510"
},
"CMT_PMV_SE4BEG1": {
"cap": "18.000",
"res": "317.510"
},
"CMT_PMV_SE4BEG2": {
"cap": "18.000",
"res": "317.510"
},
"CMT_PMV_SE4BEG3": {
"cap": "18.000",
"res": "317.510"
},
"CMT_PMV_SE4C0": {
"cap": "18.000",
"res": "317.510"
},
"CMT_PMV_SE4C1": {
"cap": "18.000",
"res": "317.510"
},
"CMT_PMV_SE4C2": {
"cap": "18.000",
"res": "317.510"
},
"CMT_PMV_SE4C3": {
"cap": "18.000",
"res": "317.510"
},
"CMT_PMV_SW2A0": {
"cap": "22.067",
"res": "317.510"
},
"CMT_PMV_SW2A1": {
"cap": "22.067",
"res": "317.510"
},
"CMT_PMV_SW2A2": {
"cap": "22.067",
"res": "317.510"
},
"CMT_PMV_SW2A3": {
"cap": "22.067",
"res": "317.510"
},
"CMT_PMV_SW4A0": {
"cap": "18.000",
"res": "317.510"
},
"CMT_PMV_SW4A1": {
"cap": "18.000",
"res": "317.510"
},
"CMT_PMV_SW4A2": {
"cap": "18.000",
"res": "317.510"
},
"CMT_PMV_SW4A3": {
"cap": "18.000",
"res": "317.510"
},
"CMT_PMV_SW4END0": {
"cap": "18.000",
"res": "317.510"
},
"CMT_PMV_SW4END1": {
"cap": "18.000",
"res": "317.510"
},
"CMT_PMV_SW4END2": {
"cap": "18.000",
"res": "317.510"
},
"CMT_PMV_SW4END3": {
"cap": "18.000",
"res": "317.510"
},
"CMT_PMV_WL1END0": {
"cap": "25.000",
"res": "317.510"
},
"CMT_PMV_WL1END1": {
"cap": "25.000",
"res": "317.510"
},
"CMT_PMV_WL1END2": {
"cap": "25.000",
"res": "317.510"
},
"CMT_PMV_WL1END3": {
"cap": "25.000",
"res": "317.510"
},
"CMT_PMV_WR1END0": {
"cap": "25.000",
"res": "317.510"
},
"CMT_PMV_WR1END1": {
"cap": "25.000",
"res": "317.510"
},
"CMT_PMV_WR1END2": {
"cap": "25.000",
"res": "317.510"
},
"CMT_PMV_WR1END3": {
"cap": "25.000",
"res": "317.510"
},
"CMT_PMV_WW2A0": {
"cap": "22.067",
"res": "317.510"
},
"CMT_PMV_WW2A1": {
"cap": "22.067",
"res": "317.510"
},
"CMT_PMV_WW2A2": {
"cap": "22.067",
"res": "317.510"
},
"CMT_PMV_WW2A3": {
"cap": "22.067",
"res": "317.510"
},
"CMT_PMV_WW2END0": {
"cap": "22.067",
"res": "317.510"
},
"CMT_PMV_WW2END1": {
"cap": "22.067",
"res": "317.510"
},
"CMT_PMV_WW2END2": {
"cap": "22.067",
"res": "317.510"
},
"CMT_PMV_WW2END3": {
"cap": "22.067",
"res": "317.510"
},
"CMT_PMV_WW4A0": {
"cap": "18.000",
"res": "317.510"
},
"CMT_PMV_WW4A1": {
"cap": "18.000",
"res": "317.510"
},
"CMT_PMV_WW4A2": {
"cap": "18.000",
"res": "317.510"
},
"CMT_PMV_WW4A3": {
"cap": "18.000",
"res": "317.510"
},
"CMT_PMV_WW4B0": {
"cap": "18.000",
"res": "317.510"
},
"CMT_PMV_WW4B1": {
"cap": "18.000",
"res": "317.510"
},
"CMT_PMV_WW4B2": {
"cap": "18.000",
"res": "317.510"
},
"CMT_PMV_WW4B3": {
"cap": "18.000",
"res": "317.510"
},
"CMT_PMV_WW4C0": {
"cap": "18.000",
"res": "317.510"
},
"CMT_PMV_WW4C1": {
"cap": "18.000",
"res": "317.510"
},
"CMT_PMV_WW4C2": {
"cap": "18.000",
"res": "317.510"
},
"CMT_PMV_WW4C3": {
"cap": "18.000",
"res": "317.510"
},
"CMT_PMV_WW4END0": {
"cap": "18.000",
"res": "317.510"
},
"CMT_PMV_WW4END1": {
"cap": "18.000",
"res": "317.510"
},
"CMT_PMV_WW4END2": {
"cap": "18.000",
"res": "317.510"
},
"CMT_PMV_WW4END3": {
"cap": "18.000",
"res": "317.510"
},
"L_TERM_INT_PHASER_TO_IO_ICLK": null,
"L_TERM_INT_PHASER_TO_IO_ICLKDIV": null,
"L_TERM_INT_PHASER_TO_IO_OCLK": null,
"L_TERM_INT_PHASER_TO_IO_OCLK1X_90": null,
"L_TERM_INT_PHASER_TO_IO_OCLKDIV": null
}
}

21951
zynq7/tile_type_CMT_TOP_L_LOWER_B.json
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17446
zynq7/tile_type_CMT_TOP_L_LOWER_T.json
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23839
zynq7/tile_type_CMT_TOP_L_UPPER_B.json
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17911
zynq7/tile_type_CMT_TOP_L_UPPER_T.json
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24806
zynq7/tile_type_DSP_L.json
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24806
zynq7/tile_type_DSP_R.json
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206
zynq7/tile_type_HCLK_BRAM.json
View File

@ -2,107 +2,107 @@
"pips": {},
"sites": [],
"tile_type": "HCLK_BRAM",
"wires": [
"HCLK_BRAM_CASCADEA_L",
"HCLK_BRAM_CASCADEA_R",
"HCLK_BRAM_CASCADEB_L",
"HCLK_BRAM_CASCADEB_R",
"HCLK_BRAM_CASCIN_L_ADDRARDADDRU0",
"HCLK_BRAM_CASCIN_L_ADDRARDADDRU1",
"HCLK_BRAM_CASCIN_L_ADDRARDADDRU10",
"HCLK_BRAM_CASCIN_L_ADDRARDADDRU11",
"HCLK_BRAM_CASCIN_L_ADDRARDADDRU12",
"HCLK_BRAM_CASCIN_L_ADDRARDADDRU13",
"HCLK_BRAM_CASCIN_L_ADDRARDADDRU14",
"HCLK_BRAM_CASCIN_L_ADDRARDADDRU2",
"HCLK_BRAM_CASCIN_L_ADDRARDADDRU3",
"HCLK_BRAM_CASCIN_L_ADDRARDADDRU4",
"HCLK_BRAM_CASCIN_L_ADDRARDADDRU5",
"HCLK_BRAM_CASCIN_L_ADDRARDADDRU6",
"HCLK_BRAM_CASCIN_L_ADDRARDADDRU7",
"HCLK_BRAM_CASCIN_L_ADDRARDADDRU8",
"HCLK_BRAM_CASCIN_L_ADDRARDADDRU9",
"HCLK_BRAM_CASCIN_L_ADDRBWRADDRU0",
"HCLK_BRAM_CASCIN_L_ADDRBWRADDRU1",
"HCLK_BRAM_CASCIN_L_ADDRBWRADDRU10",
"HCLK_BRAM_CASCIN_L_ADDRBWRADDRU11",
"HCLK_BRAM_CASCIN_L_ADDRBWRADDRU12",
"HCLK_BRAM_CASCIN_L_ADDRBWRADDRU13",
"HCLK_BRAM_CASCIN_L_ADDRBWRADDRU14",
"HCLK_BRAM_CASCIN_L_ADDRBWRADDRU2",
"HCLK_BRAM_CASCIN_L_ADDRBWRADDRU3",
"HCLK_BRAM_CASCIN_L_ADDRBWRADDRU4",
"HCLK_BRAM_CASCIN_L_ADDRBWRADDRU5",
"HCLK_BRAM_CASCIN_L_ADDRBWRADDRU6",
"HCLK_BRAM_CASCIN_L_ADDRBWRADDRU7",
"HCLK_BRAM_CASCIN_L_ADDRBWRADDRU8",
"HCLK_BRAM_CASCIN_L_ADDRBWRADDRU9",
"HCLK_BRAM_CASCOUT_L_ADDRARDADDRU0",
"HCLK_BRAM_CASCOUT_L_ADDRARDADDRU1",
"HCLK_BRAM_CASCOUT_L_ADDRARDADDRU10",
"HCLK_BRAM_CASCOUT_L_ADDRARDADDRU11",
"HCLK_BRAM_CASCOUT_L_ADDRARDADDRU12",
"HCLK_BRAM_CASCOUT_L_ADDRARDADDRU13",
"HCLK_BRAM_CASCOUT_L_ADDRARDADDRU14",
"HCLK_BRAM_CASCOUT_L_ADDRARDADDRU2",
"HCLK_BRAM_CASCOUT_L_ADDRARDADDRU3",
"HCLK_BRAM_CASCOUT_L_ADDRARDADDRU4",
"HCLK_BRAM_CASCOUT_L_ADDRARDADDRU5",
"HCLK_BRAM_CASCOUT_L_ADDRARDADDRU6",
"HCLK_BRAM_CASCOUT_L_ADDRARDADDRU7",
"HCLK_BRAM_CASCOUT_L_ADDRARDADDRU8",
"HCLK_BRAM_CASCOUT_L_ADDRARDADDRU9",
"HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU0",
"HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU1",
"HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU10",
"HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU11",
"HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU12",
"HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU13",
"HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU14",
"HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU2",
"HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU3",
"HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU4",
"HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU5",
"HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU6",
"HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU7",
"HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU8",
"HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU9",
"HCLK_BRAM_CK_BUFHCLK0",
"HCLK_BRAM_CK_BUFHCLK1",
"HCLK_BRAM_CK_BUFHCLK10",
"HCLK_BRAM_CK_BUFHCLK11",
"HCLK_BRAM_CK_BUFHCLK2",
"HCLK_BRAM_CK_BUFHCLK3",
"HCLK_BRAM_CK_BUFHCLK4",
"HCLK_BRAM_CK_BUFHCLK5",
"HCLK_BRAM_CK_BUFHCLK6",
"HCLK_BRAM_CK_BUFHCLK7",
"HCLK_BRAM_CK_BUFHCLK8",
"HCLK_BRAM_CK_BUFHCLK9",
"HCLK_BRAM_CK_BUFRCLK0",
"HCLK_BRAM_CK_BUFRCLK1",
"HCLK_BRAM_CK_BUFRCLK2",
"HCLK_BRAM_CK_BUFRCLK3",
"HCLK_BRAM_CK_IN0",
"HCLK_BRAM_CK_IN1",
"HCLK_BRAM_CK_IN10",
"HCLK_BRAM_CK_IN11",
"HCLK_BRAM_CK_IN12",
"HCLK_BRAM_CK_IN13",
"HCLK_BRAM_CK_IN2",
"HCLK_BRAM_CK_IN3",
"HCLK_BRAM_CK_IN4",
"HCLK_BRAM_CK_IN5",
"HCLK_BRAM_CK_IN6",
"HCLK_BRAM_CK_IN7",
"HCLK_BRAM_CK_IN8",
"HCLK_BRAM_CK_IN9",
"HCLK_BRAM_PMVBRAM_O",
"HCLK_BRAM_PMVBRAM_ODIV2",
"HCLK_BRAM_PMVBRAM_ODIV4",
"HCLK_BRAM_PMVBRAM_SELECT1",
"HCLK_BRAM_PMVBRAM_SELECT2",
"HCLK_BRAM_PMVBRAM_SELECT3",
"HCLK_BRAM_PMVBRAM_SELECT4"
]
"wires": {
"HCLK_BRAM_CASCADEA_L": null,
"HCLK_BRAM_CASCADEA_R": null,
"HCLK_BRAM_CASCADEB_L": null,
"HCLK_BRAM_CASCADEB_R": null,
"HCLK_BRAM_CASCIN_L_ADDRARDADDRU0": null,
"HCLK_BRAM_CASCIN_L_ADDRARDADDRU1": null,
"HCLK_BRAM_CASCIN_L_ADDRARDADDRU10": null,
"HCLK_BRAM_CASCIN_L_ADDRARDADDRU11": null,
"HCLK_BRAM_CASCIN_L_ADDRARDADDRU12": null,
"HCLK_BRAM_CASCIN_L_ADDRARDADDRU13": null,
"HCLK_BRAM_CASCIN_L_ADDRARDADDRU14": null,
"HCLK_BRAM_CASCIN_L_ADDRARDADDRU2": null,
"HCLK_BRAM_CASCIN_L_ADDRARDADDRU3": null,
"HCLK_BRAM_CASCIN_L_ADDRARDADDRU4": null,
"HCLK_BRAM_CASCIN_L_ADDRARDADDRU5": null,
"HCLK_BRAM_CASCIN_L_ADDRARDADDRU6": null,
"HCLK_BRAM_CASCIN_L_ADDRARDADDRU7": null,
"HCLK_BRAM_CASCIN_L_ADDRARDADDRU8": null,
"HCLK_BRAM_CASCIN_L_ADDRARDADDRU9": null,
"HCLK_BRAM_CASCIN_L_ADDRBWRADDRU0": null,
"HCLK_BRAM_CASCIN_L_ADDRBWRADDRU1": null,
"HCLK_BRAM_CASCIN_L_ADDRBWRADDRU10": null,
"HCLK_BRAM_CASCIN_L_ADDRBWRADDRU11": null,
"HCLK_BRAM_CASCIN_L_ADDRBWRADDRU12": null,
"HCLK_BRAM_CASCIN_L_ADDRBWRADDRU13": null,
"HCLK_BRAM_CASCIN_L_ADDRBWRADDRU14": null,
"HCLK_BRAM_CASCIN_L_ADDRBWRADDRU2": null,
"HCLK_BRAM_CASCIN_L_ADDRBWRADDRU3": null,
"HCLK_BRAM_CASCIN_L_ADDRBWRADDRU4": null,
"HCLK_BRAM_CASCIN_L_ADDRBWRADDRU5": null,
"HCLK_BRAM_CASCIN_L_ADDRBWRADDRU6": null,
"HCLK_BRAM_CASCIN_L_ADDRBWRADDRU7": null,
"HCLK_BRAM_CASCIN_L_ADDRBWRADDRU8": null,
"HCLK_BRAM_CASCIN_L_ADDRBWRADDRU9": null,
"HCLK_BRAM_CASCOUT_L_ADDRARDADDRU0": null,
"HCLK_BRAM_CASCOUT_L_ADDRARDADDRU1": null,
"HCLK_BRAM_CASCOUT_L_ADDRARDADDRU10": null,
"HCLK_BRAM_CASCOUT_L_ADDRARDADDRU11": null,
"HCLK_BRAM_CASCOUT_L_ADDRARDADDRU12": null,
"HCLK_BRAM_CASCOUT_L_ADDRARDADDRU13": null,
"HCLK_BRAM_CASCOUT_L_ADDRARDADDRU14": null,
"HCLK_BRAM_CASCOUT_L_ADDRARDADDRU2": null,
"HCLK_BRAM_CASCOUT_L_ADDRARDADDRU3": null,
"HCLK_BRAM_CASCOUT_L_ADDRARDADDRU4": null,
"HCLK_BRAM_CASCOUT_L_ADDRARDADDRU5": null,
"HCLK_BRAM_CASCOUT_L_ADDRARDADDRU6": null,
"HCLK_BRAM_CASCOUT_L_ADDRARDADDRU7": null,
"HCLK_BRAM_CASCOUT_L_ADDRARDADDRU8": null,
"HCLK_BRAM_CASCOUT_L_ADDRARDADDRU9": null,
"HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU0": null,
"HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU1": null,
"HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU10": null,
"HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU11": null,
"HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU12": null,
"HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU13": null,
"HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU14": null,
"HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU2": null,
"HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU3": null,
"HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU4": null,
"HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU5": null,
"HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU6": null,
"HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU7": null,
"HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU8": null,
"HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU9": null,
"HCLK_BRAM_CK_BUFHCLK0": null,
"HCLK_BRAM_CK_BUFHCLK1": null,
"HCLK_BRAM_CK_BUFHCLK10": null,
"HCLK_BRAM_CK_BUFHCLK11": null,
"HCLK_BRAM_CK_BUFHCLK2": null,
"HCLK_BRAM_CK_BUFHCLK3": null,
"HCLK_BRAM_CK_BUFHCLK4": null,
"HCLK_BRAM_CK_BUFHCLK5": null,
"HCLK_BRAM_CK_BUFHCLK6": null,
"HCLK_BRAM_CK_BUFHCLK7": null,
"HCLK_BRAM_CK_BUFHCLK8": null,
"HCLK_BRAM_CK_BUFHCLK9": null,
"HCLK_BRAM_CK_BUFRCLK0": null,
"HCLK_BRAM_CK_BUFRCLK1": null,
"HCLK_BRAM_CK_BUFRCLK2": null,
"HCLK_BRAM_CK_BUFRCLK3": null,
"HCLK_BRAM_CK_IN0": null,
"HCLK_BRAM_CK_IN1": null,
"HCLK_BRAM_CK_IN10": null,
"HCLK_BRAM_CK_IN11": null,
"HCLK_BRAM_CK_IN12": null,
"HCLK_BRAM_CK_IN13": null,
"HCLK_BRAM_CK_IN2": null,
"HCLK_BRAM_CK_IN3": null,
"HCLK_BRAM_CK_IN4": null,
"HCLK_BRAM_CK_IN5": null,
"HCLK_BRAM_CK_IN6": null,
"HCLK_BRAM_CK_IN7": null,
"HCLK_BRAM_CK_IN8": null,
"HCLK_BRAM_CK_IN9": null,
"HCLK_BRAM_PMVBRAM_O": null,
"HCLK_BRAM_PMVBRAM_ODIV2": null,
"HCLK_BRAM_PMVBRAM_ODIV4": null,
"HCLK_BRAM_PMVBRAM_SELECT1": null,
"HCLK_BRAM_PMVBRAM_SELECT2": null,
"HCLK_BRAM_PMVBRAM_SELECT3": null,
"HCLK_BRAM_PMVBRAM_SELECT4": null
}
}

100
zynq7/tile_type_HCLK_CLB.json
View File

@ -2,48 +2,60 @@
"pips": {},
"sites": [],
"tile_type": "HCLK_CLB",
"wires": [
"HCLK_CLB_CK_BUFHCLK0",
"HCLK_CLB_CK_BUFHCLK1",
"HCLK_CLB_CK_BUFHCLK10",
"HCLK_CLB_CK_BUFHCLK11",
"HCLK_CLB_CK_BUFHCLK2",
"HCLK_CLB_CK_BUFHCLK3",
"HCLK_CLB_CK_BUFHCLK4",
"HCLK_CLB_CK_BUFHCLK5",
"HCLK_CLB_CK_BUFHCLK6",
"HCLK_CLB_CK_BUFHCLK7",
"HCLK_CLB_CK_BUFHCLK8",
"HCLK_CLB_CK_BUFHCLK9",
"HCLK_CLB_CK_BUFRCLK0",
"HCLK_CLB_CK_BUFRCLK1",
"HCLK_CLB_CK_BUFRCLK2",
"HCLK_CLB_CK_BUFRCLK3",
"HCLK_CLB_CK_IN0",
"HCLK_CLB_CK_IN1",
"HCLK_CLB_CK_IN10",
"HCLK_CLB_CK_IN11",
"HCLK_CLB_CK_IN12",
"HCLK_CLB_CK_IN13",
"HCLK_CLB_CK_IN2",
"HCLK_CLB_CK_IN3",
"HCLK_CLB_CK_IN4",
"HCLK_CLB_CK_IN5",
"HCLK_CLB_CK_IN6",
"HCLK_CLB_CK_IN7",
"HCLK_CLB_CK_IN8",
"HCLK_CLB_CK_IN9",
"HCLK_CLB_COUT0_L",
"HCLK_CLB_COUT0_R",
"HCLK_CLB_COUT1_L",
"HCLK_CLB_COUT1_R",
"HCLK_CLB_PERFCLK0",
"HCLK_CLB_PERFCLK1",
"HCLK_CLB_PERFCLK2",
"HCLK_CLB_PERFCLK3",
"HCLK_CLB_REFCK_EASTCLK0",
"HCLK_CLB_REFCK_EASTCLK1",
"HCLK_CLB_REFCK_WESTCLK0",
"HCLK_CLB_REFCK_WESTCLK1"
]
"wires": {
"HCLK_CLB_CK_BUFHCLK0": null,
"HCLK_CLB_CK_BUFHCLK1": null,
"HCLK_CLB_CK_BUFHCLK10": null,
"HCLK_CLB_CK_BUFHCLK11": null,
"HCLK_CLB_CK_BUFHCLK2": null,
"HCLK_CLB_CK_BUFHCLK3": null,
"HCLK_CLB_CK_BUFHCLK4": null,
"HCLK_CLB_CK_BUFHCLK5": null,
"HCLK_CLB_CK_BUFHCLK6": null,
"HCLK_CLB_CK_BUFHCLK7": null,
"HCLK_CLB_CK_BUFHCLK8": null,
"HCLK_CLB_CK_BUFHCLK9": null,
"HCLK_CLB_CK_BUFRCLK0": null,
"HCLK_CLB_CK_BUFRCLK1": null,
"HCLK_CLB_CK_BUFRCLK2": null,
"HCLK_CLB_CK_BUFRCLK3": null,
"HCLK_CLB_CK_IN0": null,
"HCLK_CLB_CK_IN1": null,
"HCLK_CLB_CK_IN10": null,
"HCLK_CLB_CK_IN11": null,
"HCLK_CLB_CK_IN12": null,
"HCLK_CLB_CK_IN13": null,
"HCLK_CLB_CK_IN2": null,
"HCLK_CLB_CK_IN3": null,
"HCLK_CLB_CK_IN4": null,
"HCLK_CLB_CK_IN5": null,
"HCLK_CLB_CK_IN6": null,
"HCLK_CLB_CK_IN7": null,
"HCLK_CLB_CK_IN8": null,
"HCLK_CLB_CK_IN9": null,
"HCLK_CLB_COUT0_L": {
"cap": "13.000",
"res": "0.000"
},
"HCLK_CLB_COUT0_R": {
"cap": "13.000",
"res": "0.000"
},
"HCLK_CLB_COUT1_L": {
"cap": "13.000",
"res": "0.000"
},
"HCLK_CLB_COUT1_R": {
"cap": "13.000",
"res": "0.000"
},
"HCLK_CLB_PERFCLK0": null,
"HCLK_CLB_PERFCLK1": null,
"HCLK_CLB_PERFCLK2": null,
"HCLK_CLB_PERFCLK3": null,
"HCLK_CLB_REFCK_EASTCLK0": null,
"HCLK_CLB_REFCK_EASTCLK1": null,
"HCLK_CLB_REFCK_WESTCLK0": null,
"HCLK_CLB_REFCK_WESTCLK1": null
}
}

20952
zynq7/tile_type_HCLK_CMT_L.json
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554
zynq7/tile_type_HCLK_DSP_L.json
View File

@ -2,134 +2,428 @@
"pips": {},
"sites": [],
"tile_type": "HCLK_DSP_L",
"wires": [
"HCLK_DSP_ACIN0",
"HCLK_DSP_ACIN1",
"HCLK_DSP_ACIN10",
"HCLK_DSP_ACIN11",
"HCLK_DSP_ACIN12",
"HCLK_DSP_ACIN13",
"HCLK_DSP_ACIN14",
"HCLK_DSP_ACIN15",
"HCLK_DSP_ACIN16",
"HCLK_DSP_ACIN17",
"HCLK_DSP_ACIN18",
"HCLK_DSP_ACIN19",
"HCLK_DSP_ACIN2",
"HCLK_DSP_ACIN20",
"HCLK_DSP_ACIN21",
"HCLK_DSP_ACIN22",
"HCLK_DSP_ACIN23",
"HCLK_DSP_ACIN24",
"HCLK_DSP_ACIN25",
"HCLK_DSP_ACIN26",
"HCLK_DSP_ACIN27",
"HCLK_DSP_ACIN28",
"HCLK_DSP_ACIN29",
"HCLK_DSP_ACIN3",
"HCLK_DSP_ACIN4",
"HCLK_DSP_ACIN5",
"HCLK_DSP_ACIN6",
"HCLK_DSP_ACIN7",
"HCLK_DSP_ACIN8",
"HCLK_DSP_ACIN9",
"HCLK_DSP_BCIN0",
"HCLK_DSP_BCIN1",
"HCLK_DSP_BCIN10",
"HCLK_DSP_BCIN11",
"HCLK_DSP_BCIN12",
"HCLK_DSP_BCIN13",
"HCLK_DSP_BCIN14",
"HCLK_DSP_BCIN15",
"HCLK_DSP_BCIN16",
"HCLK_DSP_BCIN17",
"HCLK_DSP_BCIN2",
"HCLK_DSP_BCIN3",
"HCLK_DSP_BCIN4",
"HCLK_DSP_BCIN5",
"HCLK_DSP_BCIN6",
"HCLK_DSP_BCIN7",
"HCLK_DSP_BCIN8",
"HCLK_DSP_BCIN9",
"HCLK_DSP_CARRYCASCIN",
"HCLK_DSP_CK_BUFHCLK0",
"HCLK_DSP_CK_BUFHCLK1",
"HCLK_DSP_CK_BUFHCLK10",
"HCLK_DSP_CK_BUFHCLK11",
"HCLK_DSP_CK_BUFHCLK2",
"HCLK_DSP_CK_BUFHCLK3",
"HCLK_DSP_CK_BUFHCLK4",
"HCLK_DSP_CK_BUFHCLK5",
"HCLK_DSP_CK_BUFHCLK6",
"HCLK_DSP_CK_BUFHCLK7",
"HCLK_DSP_CK_BUFHCLK8",
"HCLK_DSP_CK_BUFHCLK9",
"HCLK_DSP_CK_BUFRCLK0",
"HCLK_DSP_CK_BUFRCLK1",
"HCLK_DSP_CK_BUFRCLK2",
"HCLK_DSP_CK_BUFRCLK3",
"HCLK_DSP_CK_IN0",
"HCLK_DSP_CK_IN1",
"HCLK_DSP_CK_IN10",
"HCLK_DSP_CK_IN11",
"HCLK_DSP_CK_IN12",
"HCLK_DSP_CK_IN13",
"HCLK_DSP_CK_IN2",
"HCLK_DSP_CK_IN3",
"HCLK_DSP_CK_IN4",
"HCLK_DSP_CK_IN5",
"HCLK_DSP_CK_IN6",
"HCLK_DSP_CK_IN7",
"HCLK_DSP_CK_IN8",
"HCLK_DSP_CK_IN9",
"HCLK_DSP_MULTSIGNIN",
"HCLK_DSP_PCIN0",
"HCLK_DSP_PCIN1",
"HCLK_DSP_PCIN10",
"HCLK_DSP_PCIN11",
"HCLK_DSP_PCIN12",
"HCLK_DSP_PCIN13",
"HCLK_DSP_PCIN14",
"HCLK_DSP_PCIN15",
"HCLK_DSP_PCIN16",
"HCLK_DSP_PCIN17",
"HCLK_DSP_PCIN18",
"HCLK_DSP_PCIN19",
"HCLK_DSP_PCIN2",
"HCLK_DSP_PCIN20",
"HCLK_DSP_PCIN21",
"HCLK_DSP_PCIN22",
"HCLK_DSP_PCIN23",
"HCLK_DSP_PCIN24",
"HCLK_DSP_PCIN25",
"HCLK_DSP_PCIN26",
"HCLK_DSP_PCIN27",
"HCLK_DSP_PCIN28",
"HCLK_DSP_PCIN29",
"HCLK_DSP_PCIN3",
"HCLK_DSP_PCIN30",
"HCLK_DSP_PCIN31",
"HCLK_DSP_PCIN32",
"HCLK_DSP_PCIN33",
"HCLK_DSP_PCIN34",
"HCLK_DSP_PCIN35",
"HCLK_DSP_PCIN36",
"HCLK_DSP_PCIN37",
"HCLK_DSP_PCIN38",
"HCLK_DSP_PCIN39",
"HCLK_DSP_PCIN4",
"HCLK_DSP_PCIN40",
"HCLK_DSP_PCIN41",
"HCLK_DSP_PCIN42",
"HCLK_DSP_PCIN43",
"HCLK_DSP_PCIN44",
"HCLK_DSP_PCIN45",
"HCLK_DSP_PCIN46",
"HCLK_DSP_PCIN47",
"HCLK_DSP_PCIN5",
"HCLK_DSP_PCIN6",
"HCLK_DSP_PCIN7",
"HCLK_DSP_PCIN8",
"HCLK_DSP_PCIN9"
]
"wires": {
"HCLK_DSP_ACIN0": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_ACIN1": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_ACIN10": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_ACIN11": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_ACIN12": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_ACIN13": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_ACIN14": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_ACIN15": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_ACIN16": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_ACIN17": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_ACIN18": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_ACIN19": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_ACIN2": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_ACIN20": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_ACIN21": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_ACIN22": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_ACIN23": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_ACIN24": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_ACIN25": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_ACIN26": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_ACIN27": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_ACIN28": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_ACIN29": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_ACIN3": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_ACIN4": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_ACIN5": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_ACIN6": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_ACIN7": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_ACIN8": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_ACIN9": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_BCIN0": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_BCIN1": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_BCIN10": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_BCIN11": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_BCIN12": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_BCIN13": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_BCIN14": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_BCIN15": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_BCIN16": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_BCIN17": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_BCIN2": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_BCIN3": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_BCIN4": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_BCIN5": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_BCIN6": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_BCIN7": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_BCIN8": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_BCIN9": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_CARRYCASCIN": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_CK_BUFHCLK0": null,
"HCLK_DSP_CK_BUFHCLK1": null,
"HCLK_DSP_CK_BUFHCLK10": null,
"HCLK_DSP_CK_BUFHCLK11": null,
"HCLK_DSP_CK_BUFHCLK2": null,
"HCLK_DSP_CK_BUFHCLK3": null,
"HCLK_DSP_CK_BUFHCLK4": null,
"HCLK_DSP_CK_BUFHCLK5": null,
"HCLK_DSP_CK_BUFHCLK6": null,
"HCLK_DSP_CK_BUFHCLK7": null,
"HCLK_DSP_CK_BUFHCLK8": null,
"HCLK_DSP_CK_BUFHCLK9": null,
"HCLK_DSP_CK_BUFRCLK0": null,
"HCLK_DSP_CK_BUFRCLK1": null,
"HCLK_DSP_CK_BUFRCLK2": null,
"HCLK_DSP_CK_BUFRCLK3": null,
"HCLK_DSP_CK_IN0": null,
"HCLK_DSP_CK_IN1": null,
"HCLK_DSP_CK_IN10": null,
"HCLK_DSP_CK_IN11": null,
"HCLK_DSP_CK_IN12": null,
"HCLK_DSP_CK_IN13": null,
"HCLK_DSP_CK_IN2": null,
"HCLK_DSP_CK_IN3": null,
"HCLK_DSP_CK_IN4": null,
"HCLK_DSP_CK_IN5": null,
"HCLK_DSP_CK_IN6": null,
"HCLK_DSP_CK_IN7": null,
"HCLK_DSP_CK_IN8": null,
"HCLK_DSP_CK_IN9": null,
"HCLK_DSP_MULTSIGNIN": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_PCIN0": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_PCIN1": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_PCIN10": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_PCIN11": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_PCIN12": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_PCIN13": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_PCIN14": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_PCIN15": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_PCIN16": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_PCIN17": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_PCIN18": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_PCIN19": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_PCIN2": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_PCIN20": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_PCIN21": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_PCIN22": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_PCIN23": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_PCIN24": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_PCIN25": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_PCIN26": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_PCIN27": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_PCIN28": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_PCIN29": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_PCIN3": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_PCIN30": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_PCIN31": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_PCIN32": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_PCIN33": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_PCIN34": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_PCIN35": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_PCIN36": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_PCIN37": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_PCIN38": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_PCIN39": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_PCIN4": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_PCIN40": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_PCIN41": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_PCIN42": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_PCIN43": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_PCIN44": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_PCIN45": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_PCIN46": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_PCIN47": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_PCIN5": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_PCIN6": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_PCIN7": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_PCIN8": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_PCIN9": {
"cap": "31.166",
"res": "0.000"
}
}
}

554
zynq7/tile_type_HCLK_DSP_R.json
View File

@ -2,134 +2,428 @@
"pips": {},
"sites": [],
"tile_type": "HCLK_DSP_R",
"wires": [
"HCLK_DSP_ACIN0",
"HCLK_DSP_ACIN1",
"HCLK_DSP_ACIN10",
"HCLK_DSP_ACIN11",
"HCLK_DSP_ACIN12",
"HCLK_DSP_ACIN13",
"HCLK_DSP_ACIN14",
"HCLK_DSP_ACIN15",
"HCLK_DSP_ACIN16",
"HCLK_DSP_ACIN17",
"HCLK_DSP_ACIN18",
"HCLK_DSP_ACIN19",
"HCLK_DSP_ACIN2",
"HCLK_DSP_ACIN20",
"HCLK_DSP_ACIN21",
"HCLK_DSP_ACIN22",
"HCLK_DSP_ACIN23",
"HCLK_DSP_ACIN24",
"HCLK_DSP_ACIN25",
"HCLK_DSP_ACIN26",
"HCLK_DSP_ACIN27",
"HCLK_DSP_ACIN28",
"HCLK_DSP_ACIN29",
"HCLK_DSP_ACIN3",
"HCLK_DSP_ACIN4",
"HCLK_DSP_ACIN5",
"HCLK_DSP_ACIN6",
"HCLK_DSP_ACIN7",
"HCLK_DSP_ACIN8",
"HCLK_DSP_ACIN9",
"HCLK_DSP_BCIN0",
"HCLK_DSP_BCIN1",
"HCLK_DSP_BCIN10",
"HCLK_DSP_BCIN11",
"HCLK_DSP_BCIN12",
"HCLK_DSP_BCIN13",
"HCLK_DSP_BCIN14",
"HCLK_DSP_BCIN15",
"HCLK_DSP_BCIN16",
"HCLK_DSP_BCIN17",
"HCLK_DSP_BCIN2",
"HCLK_DSP_BCIN3",
"HCLK_DSP_BCIN4",
"HCLK_DSP_BCIN5",
"HCLK_DSP_BCIN6",
"HCLK_DSP_BCIN7",
"HCLK_DSP_BCIN8",
"HCLK_DSP_BCIN9",
"HCLK_DSP_CARRYCASCIN",
"HCLK_DSP_CK_BUFHCLK0",
"HCLK_DSP_CK_BUFHCLK1",
"HCLK_DSP_CK_BUFHCLK10",
"HCLK_DSP_CK_BUFHCLK11",
"HCLK_DSP_CK_BUFHCLK2",
"HCLK_DSP_CK_BUFHCLK3",
"HCLK_DSP_CK_BUFHCLK4",
"HCLK_DSP_CK_BUFHCLK5",
"HCLK_DSP_CK_BUFHCLK6",
"HCLK_DSP_CK_BUFHCLK7",
"HCLK_DSP_CK_BUFHCLK8",
"HCLK_DSP_CK_BUFHCLK9",
"HCLK_DSP_CK_BUFRCLK0",
"HCLK_DSP_CK_BUFRCLK1",
"HCLK_DSP_CK_BUFRCLK2",
"HCLK_DSP_CK_BUFRCLK3",
"HCLK_DSP_CK_IN0",
"HCLK_DSP_CK_IN1",
"HCLK_DSP_CK_IN10",
"HCLK_DSP_CK_IN11",
"HCLK_DSP_CK_IN12",
"HCLK_DSP_CK_IN13",
"HCLK_DSP_CK_IN2",
"HCLK_DSP_CK_IN3",
"HCLK_DSP_CK_IN4",
"HCLK_DSP_CK_IN5",
"HCLK_DSP_CK_IN6",
"HCLK_DSP_CK_IN7",
"HCLK_DSP_CK_IN8",
"HCLK_DSP_CK_IN9",
"HCLK_DSP_MULTSIGNIN",
"HCLK_DSP_PCIN0",
"HCLK_DSP_PCIN1",
"HCLK_DSP_PCIN10",
"HCLK_DSP_PCIN11",
"HCLK_DSP_PCIN12",
"HCLK_DSP_PCIN13",
"HCLK_DSP_PCIN14",
"HCLK_DSP_PCIN15",
"HCLK_DSP_PCIN16",
"HCLK_DSP_PCIN17",
"HCLK_DSP_PCIN18",
"HCLK_DSP_PCIN19",
"HCLK_DSP_PCIN2",
"HCLK_DSP_PCIN20",
"HCLK_DSP_PCIN21",
"HCLK_DSP_PCIN22",
"HCLK_DSP_PCIN23",
"HCLK_DSP_PCIN24",
"HCLK_DSP_PCIN25",
"HCLK_DSP_PCIN26",
"HCLK_DSP_PCIN27",
"HCLK_DSP_PCIN28",
"HCLK_DSP_PCIN29",
"HCLK_DSP_PCIN3",
"HCLK_DSP_PCIN30",
"HCLK_DSP_PCIN31",
"HCLK_DSP_PCIN32",
"HCLK_DSP_PCIN33",
"HCLK_DSP_PCIN34",
"HCLK_DSP_PCIN35",
"HCLK_DSP_PCIN36",
"HCLK_DSP_PCIN37",
"HCLK_DSP_PCIN38",
"HCLK_DSP_PCIN39",
"HCLK_DSP_PCIN4",
"HCLK_DSP_PCIN40",
"HCLK_DSP_PCIN41",
"HCLK_DSP_PCIN42",
"HCLK_DSP_PCIN43",
"HCLK_DSP_PCIN44",
"HCLK_DSP_PCIN45",
"HCLK_DSP_PCIN46",
"HCLK_DSP_PCIN47",
"HCLK_DSP_PCIN5",
"HCLK_DSP_PCIN6",
"HCLK_DSP_PCIN7",
"HCLK_DSP_PCIN8",
"HCLK_DSP_PCIN9"
]
"wires": {
"HCLK_DSP_ACIN0": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_ACIN1": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_ACIN10": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_ACIN11": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_ACIN12": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_ACIN13": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_ACIN14": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_ACIN15": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_ACIN16": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_ACIN17": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_ACIN18": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_ACIN19": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_ACIN2": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_ACIN20": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_ACIN21": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_ACIN22": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_ACIN23": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_ACIN24": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_ACIN25": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_ACIN26": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_ACIN27": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_ACIN28": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_ACIN29": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_ACIN3": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_ACIN4": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_ACIN5": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_ACIN6": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_ACIN7": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_ACIN8": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_ACIN9": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_BCIN0": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_BCIN1": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_BCIN10": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_BCIN11": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_BCIN12": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_BCIN13": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_BCIN14": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_BCIN15": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_BCIN16": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_BCIN17": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_BCIN2": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_BCIN3": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_BCIN4": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_BCIN5": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_BCIN6": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_BCIN7": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_BCIN8": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_BCIN9": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_CARRYCASCIN": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_CK_BUFHCLK0": null,
"HCLK_DSP_CK_BUFHCLK1": null,
"HCLK_DSP_CK_BUFHCLK10": null,
"HCLK_DSP_CK_BUFHCLK11": null,
"HCLK_DSP_CK_BUFHCLK2": null,
"HCLK_DSP_CK_BUFHCLK3": null,
"HCLK_DSP_CK_BUFHCLK4": null,
"HCLK_DSP_CK_BUFHCLK5": null,
"HCLK_DSP_CK_BUFHCLK6": null,
"HCLK_DSP_CK_BUFHCLK7": null,
"HCLK_DSP_CK_BUFHCLK8": null,
"HCLK_DSP_CK_BUFHCLK9": null,
"HCLK_DSP_CK_BUFRCLK0": null,
"HCLK_DSP_CK_BUFRCLK1": null,
"HCLK_DSP_CK_BUFRCLK2": null,
"HCLK_DSP_CK_BUFRCLK3": null,
"HCLK_DSP_CK_IN0": null,
"HCLK_DSP_CK_IN1": null,
"HCLK_DSP_CK_IN10": null,
"HCLK_DSP_CK_IN11": null,
"HCLK_DSP_CK_IN12": null,
"HCLK_DSP_CK_IN13": null,
"HCLK_DSP_CK_IN2": null,
"HCLK_DSP_CK_IN3": null,
"HCLK_DSP_CK_IN4": null,
"HCLK_DSP_CK_IN5": null,
"HCLK_DSP_CK_IN6": null,
"HCLK_DSP_CK_IN7": null,
"HCLK_DSP_CK_IN8": null,
"HCLK_DSP_CK_IN9": null,
"HCLK_DSP_MULTSIGNIN": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_PCIN0": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_PCIN1": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_PCIN10": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_PCIN11": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_PCIN12": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_PCIN13": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_PCIN14": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_PCIN15": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_PCIN16": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_PCIN17": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_PCIN18": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_PCIN19": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_PCIN2": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_PCIN20": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_PCIN21": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_PCIN22": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_PCIN23": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_PCIN24": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_PCIN25": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_PCIN26": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_PCIN27": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_PCIN28": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_PCIN29": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_PCIN3": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_PCIN30": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_PCIN31": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_PCIN32": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_PCIN33": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_PCIN34": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_PCIN35": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_PCIN36": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_PCIN37": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_PCIN38": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_PCIN39": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_PCIN4": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_PCIN40": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_PCIN41": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_PCIN42": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_PCIN43": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_PCIN44": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_PCIN45": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_PCIN46": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_PCIN47": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_PCIN5": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_PCIN6": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_PCIN7": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_PCIN8": {
"cap": "31.166",
"res": "0.000"
},
"HCLK_DSP_PCIN9": {
"cap": "31.166",
"res": "0.000"
}
}
}

64
zynq7/tile_type_HCLK_FEEDTHRU_1.json
View File

@ -2,36 +2,36 @@
"pips": {},
"sites": [],
"tile_type": "HCLK_FEEDTHRU_1",
"wires": [
"HCLK_FEEDTHRU_1_CK_BUFHCLK0",
"HCLK_FEEDTHRU_1_CK_BUFHCLK1",
"HCLK_FEEDTHRU_1_CK_BUFHCLK10",
"HCLK_FEEDTHRU_1_CK_BUFHCLK11",
"HCLK_FEEDTHRU_1_CK_BUFHCLK2",
"HCLK_FEEDTHRU_1_CK_BUFHCLK3",
"HCLK_FEEDTHRU_1_CK_BUFHCLK4",
"HCLK_FEEDTHRU_1_CK_BUFHCLK5",
"HCLK_FEEDTHRU_1_CK_BUFHCLK6",
"HCLK_FEEDTHRU_1_CK_BUFHCLK7",
"HCLK_FEEDTHRU_1_CK_BUFHCLK8",
"HCLK_FEEDTHRU_1_CK_BUFHCLK9",
"HCLK_FEEDTHRU_1_CK_BUFRCLK0",
"HCLK_FEEDTHRU_1_CK_BUFRCLK1",
"HCLK_FEEDTHRU_1_CK_BUFRCLK2",
"HCLK_FEEDTHRU_1_CK_BUFRCLK3",
"HCLK_FEEDTHRU_1_CK_IN0",
"HCLK_FEEDTHRU_1_CK_IN1",
"HCLK_FEEDTHRU_1_CK_IN10",
"HCLK_FEEDTHRU_1_CK_IN11",
"HCLK_FEEDTHRU_1_CK_IN12",
"HCLK_FEEDTHRU_1_CK_IN13",
"HCLK_FEEDTHRU_1_CK_IN2",
"HCLK_FEEDTHRU_1_CK_IN3",
"HCLK_FEEDTHRU_1_CK_IN4",
"HCLK_FEEDTHRU_1_CK_IN5",
"HCLK_FEEDTHRU_1_CK_IN6",
"HCLK_FEEDTHRU_1_CK_IN7",
"HCLK_FEEDTHRU_1_CK_IN8",
"HCLK_FEEDTHRU_1_CK_IN9"
]
"wires": {
"HCLK_FEEDTHRU_1_CK_BUFHCLK0": null,
"HCLK_FEEDTHRU_1_CK_BUFHCLK1": null,
"HCLK_FEEDTHRU_1_CK_BUFHCLK10": null,
"HCLK_FEEDTHRU_1_CK_BUFHCLK11": null,
"HCLK_FEEDTHRU_1_CK_BUFHCLK2": null,
"HCLK_FEEDTHRU_1_CK_BUFHCLK3": null,
"HCLK_FEEDTHRU_1_CK_BUFHCLK4": null,
"HCLK_FEEDTHRU_1_CK_BUFHCLK5": null,
"HCLK_FEEDTHRU_1_CK_BUFHCLK6": null,
"HCLK_FEEDTHRU_1_CK_BUFHCLK7": null,
"HCLK_FEEDTHRU_1_CK_BUFHCLK8": null,
"HCLK_FEEDTHRU_1_CK_BUFHCLK9": null,
"HCLK_FEEDTHRU_1_CK_BUFRCLK0": null,
"HCLK_FEEDTHRU_1_CK_BUFRCLK1": null,
"HCLK_FEEDTHRU_1_CK_BUFRCLK2": null,
"HCLK_FEEDTHRU_1_CK_BUFRCLK3": null,
"HCLK_FEEDTHRU_1_CK_IN0": null,
"HCLK_FEEDTHRU_1_CK_IN1": null,
"HCLK_FEEDTHRU_1_CK_IN10": null,
"HCLK_FEEDTHRU_1_CK_IN11": null,
"HCLK_FEEDTHRU_1_CK_IN12": null,
"HCLK_FEEDTHRU_1_CK_IN13": null,
"HCLK_FEEDTHRU_1_CK_IN2": null,
"HCLK_FEEDTHRU_1_CK_IN3": null,
"HCLK_FEEDTHRU_1_CK_IN4": null,
"HCLK_FEEDTHRU_1_CK_IN5": null,
"HCLK_FEEDTHRU_1_CK_IN6": null,
"HCLK_FEEDTHRU_1_CK_IN7": null,
"HCLK_FEEDTHRU_1_CK_IN8": null,
"HCLK_FEEDTHRU_1_CK_IN9": null
}
}

128
zynq7/tile_type_HCLK_FEEDTHRU_1_PELE.json
View File

@ -2,68 +2,68 @@
"pips": {},
"sites": [],
"tile_type": "HCLK_FEEDTHRU_1_PELE",
"wires": [
"HCLK_FEEDTHRU_1_CK_BUFHCLK0",
"HCLK_FEEDTHRU_1_CK_BUFHCLK1",
"HCLK_FEEDTHRU_1_CK_BUFHCLK10",
"HCLK_FEEDTHRU_1_CK_BUFHCLK11",
"HCLK_FEEDTHRU_1_CK_BUFHCLK2",
"HCLK_FEEDTHRU_1_CK_BUFHCLK3",
"HCLK_FEEDTHRU_1_CK_BUFHCLK4",
"HCLK_FEEDTHRU_1_CK_BUFHCLK5",
"HCLK_FEEDTHRU_1_CK_BUFHCLK6",
"HCLK_FEEDTHRU_1_CK_BUFHCLK7",
"HCLK_FEEDTHRU_1_CK_BUFHCLK8",
"HCLK_FEEDTHRU_1_CK_BUFHCLK9",
"HCLK_FEEDTHRU_1_CK_BUFRCLK0",
"HCLK_FEEDTHRU_1_CK_BUFRCLK1",
"HCLK_FEEDTHRU_1_CK_BUFRCLK2",
"HCLK_FEEDTHRU_1_CK_BUFRCLK3",
"HCLK_FEEDTHRU_1_CK_IN0",
"HCLK_FEEDTHRU_1_CK_IN1",
"HCLK_FEEDTHRU_1_CK_IN10",
"HCLK_FEEDTHRU_1_CK_IN11",
"HCLK_FEEDTHRU_1_CK_IN12",
"HCLK_FEEDTHRU_1_CK_IN13",
"HCLK_FEEDTHRU_1_CK_IN2",
"HCLK_FEEDTHRU_1_CK_IN3",
"HCLK_FEEDTHRU_1_CK_IN4",
"HCLK_FEEDTHRU_1_CK_IN5",
"HCLK_FEEDTHRU_1_CK_IN6",
"HCLK_FEEDTHRU_1_CK_IN7",
"HCLK_FEEDTHRU_1_CK_IN8",
"HCLK_FEEDTHRU_1_CK_IN9",
"MONITOR_VERT_HCLK_VAUXN0",
"MONITOR_VERT_HCLK_VAUXN1",
"MONITOR_VERT_HCLK_VAUXN10",
"MONITOR_VERT_HCLK_VAUXN11",
"MONITOR_VERT_HCLK_VAUXN12",
"MONITOR_VERT_HCLK_VAUXN13",
"MONITOR_VERT_HCLK_VAUXN14",
"MONITOR_VERT_HCLK_VAUXN15",
"MONITOR_VERT_HCLK_VAUXN2",
"MONITOR_VERT_HCLK_VAUXN3",
"MONITOR_VERT_HCLK_VAUXN4",
"MONITOR_VERT_HCLK_VAUXN5",
"MONITOR_VERT_HCLK_VAUXN6",
"MONITOR_VERT_HCLK_VAUXN7",
"MONITOR_VERT_HCLK_VAUXN8",
"MONITOR_VERT_HCLK_VAUXN9",
"MONITOR_VERT_HCLK_VAUXP0",
"MONITOR_VERT_HCLK_VAUXP1",
"MONITOR_VERT_HCLK_VAUXP10",
"MONITOR_VERT_HCLK_VAUXP11",
"MONITOR_VERT_HCLK_VAUXP12",
"MONITOR_VERT_HCLK_VAUXP13",
"MONITOR_VERT_HCLK_VAUXP14",
"MONITOR_VERT_HCLK_VAUXP15",
"MONITOR_VERT_HCLK_VAUXP2",
"MONITOR_VERT_HCLK_VAUXP3",
"MONITOR_VERT_HCLK_VAUXP4",
"MONITOR_VERT_HCLK_VAUXP5",
"MONITOR_VERT_HCLK_VAUXP6",
"MONITOR_VERT_HCLK_VAUXP7",
"MONITOR_VERT_HCLK_VAUXP8",
"MONITOR_VERT_HCLK_VAUXP9"
]
"wires": {
"HCLK_FEEDTHRU_1_CK_BUFHCLK0": null,
"HCLK_FEEDTHRU_1_CK_BUFHCLK1": null,
"HCLK_FEEDTHRU_1_CK_BUFHCLK10": null,
"HCLK_FEEDTHRU_1_CK_BUFHCLK11": null,
"HCLK_FEEDTHRU_1_CK_BUFHCLK2": null,
"HCLK_FEEDTHRU_1_CK_BUFHCLK3": null,
"HCLK_FEEDTHRU_1_CK_BUFHCLK4": null,
"HCLK_FEEDTHRU_1_CK_BUFHCLK5": null,
"HCLK_FEEDTHRU_1_CK_BUFHCLK6": null,
"HCLK_FEEDTHRU_1_CK_BUFHCLK7": null,
"HCLK_FEEDTHRU_1_CK_BUFHCLK8": null,
"HCLK_FEEDTHRU_1_CK_BUFHCLK9": null,
"HCLK_FEEDTHRU_1_CK_BUFRCLK0": null,
"HCLK_FEEDTHRU_1_CK_BUFRCLK1": null,
"HCLK_FEEDTHRU_1_CK_BUFRCLK2": null,
"HCLK_FEEDTHRU_1_CK_BUFRCLK3": null,
"HCLK_FEEDTHRU_1_CK_IN0": null,
"HCLK_FEEDTHRU_1_CK_IN1": null,
"HCLK_FEEDTHRU_1_CK_IN10": null,
"HCLK_FEEDTHRU_1_CK_IN11": null,
"HCLK_FEEDTHRU_1_CK_IN12": null,
"HCLK_FEEDTHRU_1_CK_IN13": null,
"HCLK_FEEDTHRU_1_CK_IN2": null,
"HCLK_FEEDTHRU_1_CK_IN3": null,
"HCLK_FEEDTHRU_1_CK_IN4": null,
"HCLK_FEEDTHRU_1_CK_IN5": null,
"HCLK_FEEDTHRU_1_CK_IN6": null,
"HCLK_FEEDTHRU_1_CK_IN7": null,
"HCLK_FEEDTHRU_1_CK_IN8": null,
"HCLK_FEEDTHRU_1_CK_IN9": null,
"MONITOR_VERT_HCLK_VAUXN0": null,
"MONITOR_VERT_HCLK_VAUXN1": null,
"MONITOR_VERT_HCLK_VAUXN10": null,
"MONITOR_VERT_HCLK_VAUXN11": null,
"MONITOR_VERT_HCLK_VAUXN12": null,
"MONITOR_VERT_HCLK_VAUXN13": null,
"MONITOR_VERT_HCLK_VAUXN14": null,
"MONITOR_VERT_HCLK_VAUXN15": null,
"MONITOR_VERT_HCLK_VAUXN2": null,
"MONITOR_VERT_HCLK_VAUXN3": null,
"MONITOR_VERT_HCLK_VAUXN4": null,
"MONITOR_VERT_HCLK_VAUXN5": null,
"MONITOR_VERT_HCLK_VAUXN6": null,
"MONITOR_VERT_HCLK_VAUXN7": null,
"MONITOR_VERT_HCLK_VAUXN8": null,
"MONITOR_VERT_HCLK_VAUXN9": null,
"MONITOR_VERT_HCLK_VAUXP0": null,
"MONITOR_VERT_HCLK_VAUXP1": null,
"MONITOR_VERT_HCLK_VAUXP10": null,
"MONITOR_VERT_HCLK_VAUXP11": null,
"MONITOR_VERT_HCLK_VAUXP12": null,
"MONITOR_VERT_HCLK_VAUXP13": null,
"MONITOR_VERT_HCLK_VAUXP14": null,
"MONITOR_VERT_HCLK_VAUXP15": null,
"MONITOR_VERT_HCLK_VAUXP2": null,
"MONITOR_VERT_HCLK_VAUXP3": null,
"MONITOR_VERT_HCLK_VAUXP4": null,
"MONITOR_VERT_HCLK_VAUXP5": null,
"MONITOR_VERT_HCLK_VAUXP6": null,
"MONITOR_VERT_HCLK_VAUXP7": null,
"MONITOR_VERT_HCLK_VAUXP8": null,
"MONITOR_VERT_HCLK_VAUXP9": null
}
}

64
zynq7/tile_type_HCLK_FEEDTHRU_2.json
View File

@ -2,36 +2,36 @@
"pips": {},
"sites": [],
"tile_type": "HCLK_FEEDTHRU_2",
"wires": [
"HCLK_FEEDTHRU_2_CK_BUFHCLK0",
"HCLK_FEEDTHRU_2_CK_BUFHCLK1",
"HCLK_FEEDTHRU_2_CK_BUFHCLK10",
"HCLK_FEEDTHRU_2_CK_BUFHCLK11",
"HCLK_FEEDTHRU_2_CK_BUFHCLK2",
"HCLK_FEEDTHRU_2_CK_BUFHCLK3",
"HCLK_FEEDTHRU_2_CK_BUFHCLK4",
"HCLK_FEEDTHRU_2_CK_BUFHCLK5",
"HCLK_FEEDTHRU_2_CK_BUFHCLK6",
"HCLK_FEEDTHRU_2_CK_BUFHCLK7",
"HCLK_FEEDTHRU_2_CK_BUFHCLK8",
"HCLK_FEEDTHRU_2_CK_BUFHCLK9",
"HCLK_FEEDTHRU_2_CK_BUFRCLK0",
"HCLK_FEEDTHRU_2_CK_BUFRCLK1",
"HCLK_FEEDTHRU_2_CK_BUFRCLK2",
"HCLK_FEEDTHRU_2_CK_BUFRCLK3",
"HCLK_FEEDTHRU_2_CK_IN0",
"HCLK_FEEDTHRU_2_CK_IN1",
"HCLK_FEEDTHRU_2_CK_IN10",
"HCLK_FEEDTHRU_2_CK_IN11",
"HCLK_FEEDTHRU_2_CK_IN12",
"HCLK_FEEDTHRU_2_CK_IN13",
"HCLK_FEEDTHRU_2_CK_IN2",
"HCLK_FEEDTHRU_2_CK_IN3",
"HCLK_FEEDTHRU_2_CK_IN4",
"HCLK_FEEDTHRU_2_CK_IN5",
"HCLK_FEEDTHRU_2_CK_IN6",
"HCLK_FEEDTHRU_2_CK_IN7",
"HCLK_FEEDTHRU_2_CK_IN8",
"HCLK_FEEDTHRU_2_CK_IN9"
]
"wires": {
"HCLK_FEEDTHRU_2_CK_BUFHCLK0": null,
"HCLK_FEEDTHRU_2_CK_BUFHCLK1": null,
"HCLK_FEEDTHRU_2_CK_BUFHCLK10": null,
"HCLK_FEEDTHRU_2_CK_BUFHCLK11": null,
"HCLK_FEEDTHRU_2_CK_BUFHCLK2": null,
"HCLK_FEEDTHRU_2_CK_BUFHCLK3": null,
"HCLK_FEEDTHRU_2_CK_BUFHCLK4": null,
"HCLK_FEEDTHRU_2_CK_BUFHCLK5": null,
"HCLK_FEEDTHRU_2_CK_BUFHCLK6": null,
"HCLK_FEEDTHRU_2_CK_BUFHCLK7": null,
"HCLK_FEEDTHRU_2_CK_BUFHCLK8": null,
"HCLK_FEEDTHRU_2_CK_BUFHCLK9": null,
"HCLK_FEEDTHRU_2_CK_BUFRCLK0": null,
"HCLK_FEEDTHRU_2_CK_BUFRCLK1": null,
"HCLK_FEEDTHRU_2_CK_BUFRCLK2": null,
"HCLK_FEEDTHRU_2_CK_BUFRCLK3": null,
"HCLK_FEEDTHRU_2_CK_IN0": null,
"HCLK_FEEDTHRU_2_CK_IN1": null,
"HCLK_FEEDTHRU_2_CK_IN10": null,
"HCLK_FEEDTHRU_2_CK_IN11": null,
"HCLK_FEEDTHRU_2_CK_IN12": null,
"HCLK_FEEDTHRU_2_CK_IN13": null,
"HCLK_FEEDTHRU_2_CK_IN2": null,
"HCLK_FEEDTHRU_2_CK_IN3": null,
"HCLK_FEEDTHRU_2_CK_IN4": null,
"HCLK_FEEDTHRU_2_CK_IN5": null,
"HCLK_FEEDTHRU_2_CK_IN6": null,
"HCLK_FEEDTHRU_2_CK_IN7": null,
"HCLK_FEEDTHRU_2_CK_IN8": null,
"HCLK_FEEDTHRU_2_CK_IN9": null
}
}

80
zynq7/tile_type_HCLK_FIFO_L.json
View File

@ -2,44 +2,44 @@
"pips": {},
"sites": [],
"tile_type": "HCLK_FIFO_L",
"wires": [
"HCLK_FIFO_CCIO0",
"HCLK_FIFO_CCIO1",
"HCLK_FIFO_CCIO2",
"HCLK_FIFO_CCIO3",
"HCLK_FIFO_CK_BUFHCLK0",
"HCLK_FIFO_CK_BUFHCLK1",
"HCLK_FIFO_CK_BUFHCLK10",
"HCLK_FIFO_CK_BUFHCLK11",
"HCLK_FIFO_CK_BUFHCLK2",
"HCLK_FIFO_CK_BUFHCLK3",
"HCLK_FIFO_CK_BUFHCLK4",
"HCLK_FIFO_CK_BUFHCLK5",
"HCLK_FIFO_CK_BUFHCLK6",
"HCLK_FIFO_CK_BUFHCLK7",
"HCLK_FIFO_CK_BUFHCLK8",
"HCLK_FIFO_CK_BUFHCLK9",
"HCLK_FIFO_CK_BUFRCLK0",
"HCLK_FIFO_CK_BUFRCLK1",
"HCLK_FIFO_CK_BUFRCLK2",
"HCLK_FIFO_CK_BUFRCLK3",
"HCLK_FIFO_CK_IN0",
"HCLK_FIFO_CK_IN1",
"HCLK_FIFO_CK_IN10",
"HCLK_FIFO_CK_IN11",
"HCLK_FIFO_CK_IN12",
"HCLK_FIFO_CK_IN13",
"HCLK_FIFO_CK_IN2",
"HCLK_FIFO_CK_IN3",
"HCLK_FIFO_CK_IN4",
"HCLK_FIFO_CK_IN5",
"HCLK_FIFO_CK_IN6",
"HCLK_FIFO_CK_IN7",
"HCLK_FIFO_CK_IN8",
"HCLK_FIFO_CK_IN9",
"HCLK_FIFO_PERFCLK0",
"HCLK_FIFO_PERFCLK1",
"HCLK_FIFO_PERFCLK2",
"HCLK_FIFO_PERFCLK3"
]
"wires": {
"HCLK_FIFO_CCIO0": null,
"HCLK_FIFO_CCIO1": null,
"HCLK_FIFO_CCIO2": null,
"HCLK_FIFO_CCIO3": null,
"HCLK_FIFO_CK_BUFHCLK0": null,
"HCLK_FIFO_CK_BUFHCLK1": null,
"HCLK_FIFO_CK_BUFHCLK10": null,
"HCLK_FIFO_CK_BUFHCLK11": null,
"HCLK_FIFO_CK_BUFHCLK2": null,
"HCLK_FIFO_CK_BUFHCLK3": null,
"HCLK_FIFO_CK_BUFHCLK4": null,
"HCLK_FIFO_CK_BUFHCLK5": null,
"HCLK_FIFO_CK_BUFHCLK6": null,
"HCLK_FIFO_CK_BUFHCLK7": null,
"HCLK_FIFO_CK_BUFHCLK8": null,
"HCLK_FIFO_CK_BUFHCLK9": null,
"HCLK_FIFO_CK_BUFRCLK0": null,
"HCLK_FIFO_CK_BUFRCLK1": null,
"HCLK_FIFO_CK_BUFRCLK2": null,
"HCLK_FIFO_CK_BUFRCLK3": null,
"HCLK_FIFO_CK_IN0": null,
"HCLK_FIFO_CK_IN1": null,
"HCLK_FIFO_CK_IN10": null,
"HCLK_FIFO_CK_IN11": null,
"HCLK_FIFO_CK_IN12": null,
"HCLK_FIFO_CK_IN13": null,
"HCLK_FIFO_CK_IN2": null,
"HCLK_FIFO_CK_IN3": null,
"HCLK_FIFO_CK_IN4": null,
"HCLK_FIFO_CK_IN5": null,
"HCLK_FIFO_CK_IN6": null,
"HCLK_FIFO_CK_IN7": null,
"HCLK_FIFO_CK_IN8": null,
"HCLK_FIFO_CK_IN9": null,
"HCLK_FIFO_PERFCLK0": null,
"HCLK_FIFO_PERFCLK1": null,
"HCLK_FIFO_PERFCLK2": null,
"HCLK_FIFO_PERFCLK3": null
}
}

88
zynq7/tile_type_HCLK_INT_INTERFACE.json
View File

@ -2,48 +2,48 @@
"pips": {},
"sites": [],
"tile_type": "HCLK_INT_INTERFACE",
"wires": [
"HCLK_INT_INTERFACE_CCIO0",
"HCLK_INT_INTERFACE_CCIO1",
"HCLK_INT_INTERFACE_CCIO2",
"HCLK_INT_INTERFACE_CCIO3",
"HCLK_INT_INTERFACE_CK_BUFHCLK0",
"HCLK_INT_INTERFACE_CK_BUFHCLK1",
"HCLK_INT_INTERFACE_CK_BUFHCLK10",
"HCLK_INT_INTERFACE_CK_BUFHCLK11",
"HCLK_INT_INTERFACE_CK_BUFHCLK2",
"HCLK_INT_INTERFACE_CK_BUFHCLK3",
"HCLK_INT_INTERFACE_CK_BUFHCLK4",
"HCLK_INT_INTERFACE_CK_BUFHCLK5",
"HCLK_INT_INTERFACE_CK_BUFHCLK6",
"HCLK_INT_INTERFACE_CK_BUFHCLK7",
"HCLK_INT_INTERFACE_CK_BUFHCLK8",
"HCLK_INT_INTERFACE_CK_BUFHCLK9",
"HCLK_INT_INTERFACE_CK_BUFRCLK0",
"HCLK_INT_INTERFACE_CK_BUFRCLK1",
"HCLK_INT_INTERFACE_CK_BUFRCLK2",
"HCLK_INT_INTERFACE_CK_BUFRCLK3",
"HCLK_INT_INTERFACE_CK_IN0",
"HCLK_INT_INTERFACE_CK_IN1",
"HCLK_INT_INTERFACE_CK_IN10",
"HCLK_INT_INTERFACE_CK_IN11",
"HCLK_INT_INTERFACE_CK_IN12",
"HCLK_INT_INTERFACE_CK_IN13",
"HCLK_INT_INTERFACE_CK_IN2",
"HCLK_INT_INTERFACE_CK_IN3",
"HCLK_INT_INTERFACE_CK_IN4",
"HCLK_INT_INTERFACE_CK_IN5",
"HCLK_INT_INTERFACE_CK_IN6",
"HCLK_INT_INTERFACE_CK_IN7",
"HCLK_INT_INTERFACE_CK_IN8",
"HCLK_INT_INTERFACE_CK_IN9",
"HCLK_INT_INTERFACE_PERFCLK0",
"HCLK_INT_INTERFACE_PERFCLK1",
"HCLK_INT_INTERFACE_PERFCLK2",
"HCLK_INT_INTERFACE_PERFCLK3",
"HCLK_INT_INTERFACE_REFCK_EASTCLK0",
"HCLK_INT_INTERFACE_REFCK_EASTCLK1",
"HCLK_INT_INTERFACE_REFCK_WESTCLK0",
"HCLK_INT_INTERFACE_REFCK_WESTCLK1"
]
"wires": {
"HCLK_INT_INTERFACE_CCIO0": null,
"HCLK_INT_INTERFACE_CCIO1": null,
"HCLK_INT_INTERFACE_CCIO2": null,
"HCLK_INT_INTERFACE_CCIO3": null,
"HCLK_INT_INTERFACE_CK_BUFHCLK0": null,
"HCLK_INT_INTERFACE_CK_BUFHCLK1": null,
"HCLK_INT_INTERFACE_CK_BUFHCLK10": null,
"HCLK_INT_INTERFACE_CK_BUFHCLK11": null,
"HCLK_INT_INTERFACE_CK_BUFHCLK2": null,
"HCLK_INT_INTERFACE_CK_BUFHCLK3": null,
"HCLK_INT_INTERFACE_CK_BUFHCLK4": null,
"HCLK_INT_INTERFACE_CK_BUFHCLK5": null,
"HCLK_INT_INTERFACE_CK_BUFHCLK6": null,
"HCLK_INT_INTERFACE_CK_BUFHCLK7": null,
"HCLK_INT_INTERFACE_CK_BUFHCLK8": null,
"HCLK_INT_INTERFACE_CK_BUFHCLK9": null,
"HCLK_INT_INTERFACE_CK_BUFRCLK0": null,
"HCLK_INT_INTERFACE_CK_BUFRCLK1": null,
"HCLK_INT_INTERFACE_CK_BUFRCLK2": null,
"HCLK_INT_INTERFACE_CK_BUFRCLK3": null,
"HCLK_INT_INTERFACE_CK_IN0": null,
"HCLK_INT_INTERFACE_CK_IN1": null,
"HCLK_INT_INTERFACE_CK_IN10": null,
"HCLK_INT_INTERFACE_CK_IN11": null,
"HCLK_INT_INTERFACE_CK_IN12": null,
"HCLK_INT_INTERFACE_CK_IN13": null,
"HCLK_INT_INTERFACE_CK_IN2": null,
"HCLK_INT_INTERFACE_CK_IN3": null,
"HCLK_INT_INTERFACE_CK_IN4": null,
"HCLK_INT_INTERFACE_CK_IN5": null,
"HCLK_INT_INTERFACE_CK_IN6": null,
"HCLK_INT_INTERFACE_CK_IN7": null,
"HCLK_INT_INTERFACE_CK_IN8": null,
"HCLK_INT_INTERFACE_CK_IN9": null,
"HCLK_INT_INTERFACE_PERFCLK0": null,
"HCLK_INT_INTERFACE_PERFCLK1": null,
"HCLK_INT_INTERFACE_PERFCLK2": null,
"HCLK_INT_INTERFACE_PERFCLK3": null,
"HCLK_INT_INTERFACE_REFCK_EASTCLK0": null,
"HCLK_INT_INTERFACE_REFCK_EASTCLK1": null,
"HCLK_INT_INTERFACE_REFCK_WESTCLK0": null,
"HCLK_INT_INTERFACE_REFCK_WESTCLK1": null
}
}

114
zynq7/tile_type_HCLK_IOB.json
View File

@ -2,40 +2,82 @@
"pips": {},
"sites": [],
"tile_type": "HCLK_IOB",
"wires": [
"HCLK_IOB_CK_BUFHCLK0",
"HCLK_IOB_CK_BUFHCLK1",
"HCLK_IOB_CK_BUFHCLK10",
"HCLK_IOB_CK_BUFHCLK11",
"HCLK_IOB_CK_BUFHCLK2",
"HCLK_IOB_CK_BUFHCLK3",
"HCLK_IOB_CK_BUFHCLK4",
"HCLK_IOB_CK_BUFHCLK5",
"HCLK_IOB_CK_BUFHCLK6",
"HCLK_IOB_CK_BUFHCLK7",
"HCLK_IOB_CK_BUFHCLK8",
"HCLK_IOB_CK_BUFHCLK9",
"HCLK_IOB_CK_BUFRCLK0",
"HCLK_IOB_CK_BUFRCLK1",
"HCLK_IOB_CK_BUFRCLK2",
"HCLK_IOB_CK_BUFRCLK3",
"HCLK_IOB_CK_IN0",
"HCLK_IOB_CK_IN1",
"HCLK_IOB_CK_IN10",
"HCLK_IOB_CK_IN11",
"HCLK_IOB_CK_IN12",
"HCLK_IOB_CK_IN13",
"HCLK_IOB_CK_IN2",
"HCLK_IOB_CK_IN3",
"HCLK_IOB_CK_IN4",
"HCLK_IOB_CK_IN5",
"HCLK_IOB_CK_IN6",
"HCLK_IOB_CK_IN7",
"HCLK_IOB_CK_IN8",
"HCLK_IOB_CK_IN9",
"HCLK_IOB_PERFCLK0",
"HCLK_IOB_PERFCLK1",
"HCLK_IOB_PERFCLK2",
"HCLK_IOB_PERFCLK3"
]
"wires": {
"HCLK_IOB_CK_BUFHCLK0": null,
"HCLK_IOB_CK_BUFHCLK1": null,
"HCLK_IOB_CK_BUFHCLK10": null,
"HCLK_IOB_CK_BUFHCLK11": null,
"HCLK_IOB_CK_BUFHCLK2": null,
"HCLK_IOB_CK_BUFHCLK3": null,
"HCLK_IOB_CK_BUFHCLK4": null,
"HCLK_IOB_CK_BUFHCLK5": null,
"HCLK_IOB_CK_BUFHCLK6": null,
"HCLK_IOB_CK_BUFHCLK7": null,
"HCLK_IOB_CK_BUFHCLK8": null,
"HCLK_IOB_CK_BUFHCLK9": null,
"HCLK_IOB_CK_BUFRCLK0": null,
"HCLK_IOB_CK_BUFRCLK1": null,
"HCLK_IOB_CK_BUFRCLK2": null,
"HCLK_IOB_CK_BUFRCLK3": null,
"HCLK_IOB_CK_IN0": {
"cap": "0.001",
"res": "0.001"
},
"HCLK_IOB_CK_IN1": {
"cap": "0.001",
"res": "0.001"
},
"HCLK_IOB_CK_IN10": {
"cap": "0.001",
"res": "0.001"
},
"HCLK_IOB_CK_IN11": {
"cap": "0.001",
"res": "0.001"
},
"HCLK_IOB_CK_IN12": {
"cap": "0.001",
"res": "0.001"
},
"HCLK_IOB_CK_IN13": {
"cap": "0.001",
"res": "0.001"
},
"HCLK_IOB_CK_IN2": {
"cap": "0.001",
"res": "0.001"
},
"HCLK_IOB_CK_IN3": {
"cap": "0.001",
"res": "0.001"
},
"HCLK_IOB_CK_IN4": {
"cap": "0.001",
"res": "0.001"
},
"HCLK_IOB_CK_IN5": {
"cap": "0.001",
"res": "0.001"
},
"HCLK_IOB_CK_IN6": {
"cap": "0.001",
"res": "0.001"
},
"HCLK_IOB_CK_IN7": {
"cap": "0.001",
"res": "0.001"
},
"HCLK_IOB_CK_IN8": {
"cap": "0.001",
"res": "0.001"
},
"HCLK_IOB_CK_IN9": {
"cap": "0.001",
"res": "0.001"
},
"HCLK_IOB_PERFCLK0": null,
"HCLK_IOB_PERFCLK1": null,
"HCLK_IOB_PERFCLK2": null,
"HCLK_IOB_PERFCLK3": null
}
}

5639
zynq7/tile_type_HCLK_IOI3.json
View File

File diff suppressed because it is too large Load Diff

5429
zynq7/tile_type_HCLK_L.json
View File

File diff suppressed because it is too large Load Diff

5429
zynq7/tile_type_HCLK_R.json
View File

File diff suppressed because it is too large Load Diff

80
zynq7/tile_type_HCLK_TERM.json
View File

@ -2,44 +2,44 @@
"pips": {},
"sites": [],
"tile_type": "HCLK_TERM",
"wires": [
"HCLK_TERM_CCIO0",
"HCLK_TERM_CCIO1",
"HCLK_TERM_CCIO2",
"HCLK_TERM_CCIO3",
"HCLK_TERM_CK_BUFHCLK0",
"HCLK_TERM_CK_BUFHCLK1",
"HCLK_TERM_CK_BUFHCLK10",
"HCLK_TERM_CK_BUFHCLK11",
"HCLK_TERM_CK_BUFHCLK2",
"HCLK_TERM_CK_BUFHCLK3",
"HCLK_TERM_CK_BUFHCLK4",
"HCLK_TERM_CK_BUFHCLK5",
"HCLK_TERM_CK_BUFHCLK6",
"HCLK_TERM_CK_BUFHCLK7",
"HCLK_TERM_CK_BUFHCLK8",
"HCLK_TERM_CK_BUFHCLK9",
"HCLK_TERM_CK_BUFRCLK0",
"HCLK_TERM_CK_BUFRCLK1",
"HCLK_TERM_CK_BUFRCLK2",
"HCLK_TERM_CK_BUFRCLK3",
"HCLK_TERM_CK_IN0",
"HCLK_TERM_CK_IN1",
"HCLK_TERM_CK_IN10",
"HCLK_TERM_CK_IN11",
"HCLK_TERM_CK_IN12",
"HCLK_TERM_CK_IN13",
"HCLK_TERM_CK_IN2",
"HCLK_TERM_CK_IN3",
"HCLK_TERM_CK_IN4",
"HCLK_TERM_CK_IN5",
"HCLK_TERM_CK_IN6",
"HCLK_TERM_CK_IN7",
"HCLK_TERM_CK_IN8",
"HCLK_TERM_CK_IN9",
"HCLK_TERM_PERFCLK0",
"HCLK_TERM_PERFCLK1",
"HCLK_TERM_PERFCLK2",
"HCLK_TERM_PERFCLK3"
]
"wires": {
"HCLK_TERM_CCIO0": null,
"HCLK_TERM_CCIO1": null,
"HCLK_TERM_CCIO2": null,
"HCLK_TERM_CCIO3": null,
"HCLK_TERM_CK_BUFHCLK0": null,
"HCLK_TERM_CK_BUFHCLK1": null,
"HCLK_TERM_CK_BUFHCLK10": null,
"HCLK_TERM_CK_BUFHCLK11": null,
"HCLK_TERM_CK_BUFHCLK2": null,
"HCLK_TERM_CK_BUFHCLK3": null,
"HCLK_TERM_CK_BUFHCLK4": null,
"HCLK_TERM_CK_BUFHCLK5": null,
"HCLK_TERM_CK_BUFHCLK6": null,
"HCLK_TERM_CK_BUFHCLK7": null,
"HCLK_TERM_CK_BUFHCLK8": null,
"HCLK_TERM_CK_BUFHCLK9": null,
"HCLK_TERM_CK_BUFRCLK0": null,
"HCLK_TERM_CK_BUFRCLK1": null,
"HCLK_TERM_CK_BUFRCLK2": null,
"HCLK_TERM_CK_BUFRCLK3": null,
"HCLK_TERM_CK_IN0": null,
"HCLK_TERM_CK_IN1": null,
"HCLK_TERM_CK_IN10": null,
"HCLK_TERM_CK_IN11": null,
"HCLK_TERM_CK_IN12": null,
"HCLK_TERM_CK_IN13": null,
"HCLK_TERM_CK_IN2": null,
"HCLK_TERM_CK_IN3": null,
"HCLK_TERM_CK_IN4": null,
"HCLK_TERM_CK_IN5": null,
"HCLK_TERM_CK_IN6": null,
"HCLK_TERM_CK_IN7": null,
"HCLK_TERM_CK_IN8": null,
"HCLK_TERM_CK_IN9": null,
"HCLK_TERM_PERFCLK0": null,
"HCLK_TERM_PERFCLK1": null,
"HCLK_TERM_PERFCLK2": null,
"HCLK_TERM_PERFCLK3": null
}
}

80
zynq7/tile_type_HCLK_VBRK.json
View File

@ -2,44 +2,44 @@
"pips": {},
"sites": [],
"tile_type": "HCLK_VBRK",
"wires": [
"HCLK_VBRK_CK_BUFHCLK0",
"HCLK_VBRK_CK_BUFHCLK1",
"HCLK_VBRK_CK_BUFHCLK10",
"HCLK_VBRK_CK_BUFHCLK11",
"HCLK_VBRK_CK_BUFHCLK2",
"HCLK_VBRK_CK_BUFHCLK3",
"HCLK_VBRK_CK_BUFHCLK4",
"HCLK_VBRK_CK_BUFHCLK5",
"HCLK_VBRK_CK_BUFHCLK6",
"HCLK_VBRK_CK_BUFHCLK7",
"HCLK_VBRK_CK_BUFHCLK8",
"HCLK_VBRK_CK_BUFHCLK9",
"HCLK_VBRK_CK_BUFRCLK0",
"HCLK_VBRK_CK_BUFRCLK1",
"HCLK_VBRK_CK_BUFRCLK2",
"HCLK_VBRK_CK_BUFRCLK3",
"HCLK_VBRK_MUX_CLK0",
"HCLK_VBRK_MUX_CLK1",
"HCLK_VBRK_MUX_CLK10",
"HCLK_VBRK_MUX_CLK11",
"HCLK_VBRK_MUX_CLK12",
"HCLK_VBRK_MUX_CLK13",
"HCLK_VBRK_MUX_CLK2",
"HCLK_VBRK_MUX_CLK3",
"HCLK_VBRK_MUX_CLK4",
"HCLK_VBRK_MUX_CLK5",
"HCLK_VBRK_MUX_CLK6",
"HCLK_VBRK_MUX_CLK7",
"HCLK_VBRK_MUX_CLK8",
"HCLK_VBRK_MUX_CLK9",
"HCLK_VBRK_PHSR_PERFCLK0",
"HCLK_VBRK_PHSR_PERFCLK1",
"HCLK_VBRK_PHSR_PERFCLK2",
"HCLK_VBRK_PHSR_PERFCLK3",
"HCLK_VBRK_REFCK_EASTCLK0",
"HCLK_VBRK_REFCK_EASTCLK1",
"HCLK_VBRK_REFCK_WESTCLK0",
"HCLK_VBRK_REFCK_WESTCLK1"
]
"wires": {
"HCLK_VBRK_CK_BUFHCLK0": null,
"HCLK_VBRK_CK_BUFHCLK1": null,
"HCLK_VBRK_CK_BUFHCLK10": null,
"HCLK_VBRK_CK_BUFHCLK11": null,
"HCLK_VBRK_CK_BUFHCLK2": null,
"HCLK_VBRK_CK_BUFHCLK3": null,
"HCLK_VBRK_CK_BUFHCLK4": null,
"HCLK_VBRK_CK_BUFHCLK5": null,
"HCLK_VBRK_CK_BUFHCLK6": null,
"HCLK_VBRK_CK_BUFHCLK7": null,
"HCLK_VBRK_CK_BUFHCLK8": null,
"HCLK_VBRK_CK_BUFHCLK9": null,
"HCLK_VBRK_CK_BUFRCLK0": null,
"HCLK_VBRK_CK_BUFRCLK1": null,
"HCLK_VBRK_CK_BUFRCLK2": null,
"HCLK_VBRK_CK_BUFRCLK3": null,
"HCLK_VBRK_MUX_CLK0": null,
"HCLK_VBRK_MUX_CLK1": null,
"HCLK_VBRK_MUX_CLK10": null,
"HCLK_VBRK_MUX_CLK11": null,
"HCLK_VBRK_MUX_CLK12": null,
"HCLK_VBRK_MUX_CLK13": null,
"HCLK_VBRK_MUX_CLK2": null,
"HCLK_VBRK_MUX_CLK3": null,
"HCLK_VBRK_MUX_CLK4": null,
"HCLK_VBRK_MUX_CLK5": null,
"HCLK_VBRK_MUX_CLK6": null,
"HCLK_VBRK_MUX_CLK7": null,
"HCLK_VBRK_MUX_CLK8": null,
"HCLK_VBRK_MUX_CLK9": null,
"HCLK_VBRK_PHSR_PERFCLK0": null,
"HCLK_VBRK_PHSR_PERFCLK1": null,
"HCLK_VBRK_PHSR_PERFCLK2": null,
"HCLK_VBRK_PHSR_PERFCLK3": null,
"HCLK_VBRK_REFCK_EASTCLK0": null,
"HCLK_VBRK_REFCK_EASTCLK1": null,
"HCLK_VBRK_REFCK_WESTCLK0": null,
"HCLK_VBRK_REFCK_WESTCLK1": null
}
}

64
zynq7/tile_type_HCLK_VFRAME.json
View File

@ -2,36 +2,36 @@
"pips": {},
"sites": [],
"tile_type": "HCLK_VFRAME",
"wires": [
"HCLK_VFRAME_CK_BUFHCLK0",
"HCLK_VFRAME_CK_BUFHCLK1",
"HCLK_VFRAME_CK_BUFHCLK10",
"HCLK_VFRAME_CK_BUFHCLK11",
"HCLK_VFRAME_CK_BUFHCLK2",
"HCLK_VFRAME_CK_BUFHCLK3",
"HCLK_VFRAME_CK_BUFHCLK4",
"HCLK_VFRAME_CK_BUFHCLK5",
"HCLK_VFRAME_CK_BUFHCLK6",
"HCLK_VFRAME_CK_BUFHCLK7",
"HCLK_VFRAME_CK_BUFHCLK8",
"HCLK_VFRAME_CK_BUFHCLK9",
"HCLK_VFRAME_CK_BUFRCLK0",
"HCLK_VFRAME_CK_BUFRCLK1",
"HCLK_VFRAME_CK_BUFRCLK2",
"HCLK_VFRAME_CK_BUFRCLK3",
"HCLK_VFRAME_CK_IN0",
"HCLK_VFRAME_CK_IN1",
"HCLK_VFRAME_CK_IN10",
"HCLK_VFRAME_CK_IN11",
"HCLK_VFRAME_CK_IN12",
"HCLK_VFRAME_CK_IN13",
"HCLK_VFRAME_CK_IN2",
"HCLK_VFRAME_CK_IN3",
"HCLK_VFRAME_CK_IN4",
"HCLK_VFRAME_CK_IN5",
"HCLK_VFRAME_CK_IN6",
"HCLK_VFRAME_CK_IN7",
"HCLK_VFRAME_CK_IN8",
"HCLK_VFRAME_CK_IN9"
]
"wires": {
"HCLK_VFRAME_CK_BUFHCLK0": null,
"HCLK_VFRAME_CK_BUFHCLK1": null,
"HCLK_VFRAME_CK_BUFHCLK10": null,
"HCLK_VFRAME_CK_BUFHCLK11": null,
"HCLK_VFRAME_CK_BUFHCLK2": null,
"HCLK_VFRAME_CK_BUFHCLK3": null,
"HCLK_VFRAME_CK_BUFHCLK4": null,
"HCLK_VFRAME_CK_BUFHCLK5": null,
"HCLK_VFRAME_CK_BUFHCLK6": null,
"HCLK_VFRAME_CK_BUFHCLK7": null,
"HCLK_VFRAME_CK_BUFHCLK8": null,
"HCLK_VFRAME_CK_BUFHCLK9": null,
"HCLK_VFRAME_CK_BUFRCLK0": null,
"HCLK_VFRAME_CK_BUFRCLK1": null,
"HCLK_VFRAME_CK_BUFRCLK2": null,
"HCLK_VFRAME_CK_BUFRCLK3": null,
"HCLK_VFRAME_CK_IN0": null,
"HCLK_VFRAME_CK_IN1": null,
"HCLK_VFRAME_CK_IN10": null,
"HCLK_VFRAME_CK_IN11": null,
"HCLK_VFRAME_CK_IN12": null,
"HCLK_VFRAME_CK_IN13": null,
"HCLK_VFRAME_CK_IN2": null,
"HCLK_VFRAME_CK_IN3": null,
"HCLK_VFRAME_CK_IN4": null,
"HCLK_VFRAME_CK_IN5": null,
"HCLK_VFRAME_CK_IN6": null,
"HCLK_VFRAME_CK_IN7": null,
"HCLK_VFRAME_CK_IN8": null,
"HCLK_VFRAME_CK_IN9": null
}
}

256
zynq7/tile_type_INT_FEEDTHRU_1.json
View File

@ -2,132 +2,132 @@
"pips": {},
"sites": [],
"tile_type": "INT_FEEDTHRU_1",
"wires": [
"INT_FEEDTHRU_1_EE2A0",
"INT_FEEDTHRU_1_EE2A1",
"INT_FEEDTHRU_1_EE2A2",
"INT_FEEDTHRU_1_EE2A3",
"INT_FEEDTHRU_1_EE2BEG0",
"INT_FEEDTHRU_1_EE2BEG1",
"INT_FEEDTHRU_1_EE2BEG2",
"INT_FEEDTHRU_1_EE2BEG3",
"INT_FEEDTHRU_1_EE4A0",
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}

256
zynq7/tile_type_INT_FEEDTHRU_2.json
View File

@ -2,132 +2,132 @@
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}
}

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