Updating DB based on "Merge pull request #229 from mcmasterg/k7_bits".
See [Info File](Info.md) for details. Signed-off-by: Tim 'mithro' Ansell <me@mith.ro>
This commit is contained in:
Tim 'mithro' Ansell
parent
6f02e2fa4b
commit
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Info.md
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Info.md
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@ -37,37 +37,39 @@ These files are released under the very permissive [CC0 1.0 Universal](COPYING).
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# Details
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Last updated on Thu Oct 25 23:18:25 UTC 2018 (2018-10-25T23:18:25+00:00).
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Last updated on Mon Nov 12 02:58:43 UTC 2018 (2018-11-12T02:58:43+00:00).
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Created using [Project X-Ray](https://github.com/SymbiFlow/prjxray) version [v0.0-903-ga0cfca8](https://github.com/SymbiFlow/prjxray/commit/a0cfca860872a99ac81b223ee1e5e9ae567b9590).
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Created using [Project X-Ray](https://github.com/SymbiFlow/prjxray) version [v0.0-984-gb43bf35](https://github.com/SymbiFlow/prjxray/commit/b43bf3539f51ed8a755ae245682cd660ca23d813).
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Latest commit was;
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```
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commit a0cfca860872a99ac81b223ee1e5e9ae567b9590
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Merge: d33fdb7 3247963
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commit b43bf3539f51ed8a755ae245682cd660ca23d813
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Merge: b5d691c e2e236e
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Author: Tim Ansell <me@mith.ro>
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Date: Wed Oct 24 17:00:19 2018 -0700
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Date: Tue Nov 6 15:11:29 2018 -0800
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Merge pull request #191 from mithro/master
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Merge pull request #229 from mcmasterg/k7_bits
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minitests/roi_harness: Add XRAY_PIN values valid for Arty.
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k7: use all bitstream bits, format settings.sh alike
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```
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## Database for [artix7](artix7/)
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### Settings
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Created using following [settings.sh (sha256: cb777c1e854d877556482ff2067eff348386ce627caa0ef5617a6e5dea01dc6a)](https://github.com/SymbiFlow/prjxray/blob/a0cfca860872a99ac81b223ee1e5e9ae567b9590/database/artix7/settings.sh)
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Created using following [settings.sh (sha256: d77b40f729b66962f0197a5e31b43860326401b6116ac36e727411319adac0f2)](https://github.com/SymbiFlow/prjxray/blob/b43bf3539f51ed8a755ae245682cd660ca23d813/database/artix7/settings.sh)
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```shell
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export XRAY_DATABASE="artix7"
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export XRAY_PART="xc7a50tfgg484-1"
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export XRAY_ROI="SLICE_X12Y100:SLICE_X27Y149"
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export XRAY_ROI_FRAMES="0x00000000:0xffffffff"
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# Leave some CLBs to the left to allow easy ROI entering
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export XRAY_ROI="SLICE_X8Y100:SLICE_X27Y149 RAMB18_X0Y40:RAMB18_X0Y59 RAMB36_X0Y20:RAMB36_X0Y29 DSP48_X0Y40:DSP48_X0Y59"
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export XRAY_ROI_GRID_X1="18"
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export XRAY_ROI_GRID_X2="47"
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# All CLB's in part, all BRAM's in part, all DSP's in part.
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export XRAY_ROI="SLICE_X0Y0:SLICE_X65Y99 SLICE_X0Y100:SLICE_X57Y149 RAMB18_X0Y0:RAMB18_X1Y59 RAMB36_X0Y0:RAMB36_X1Y29 RAMB18_X2Y0:RAMB18_X2Y39 RAMB36_X2Y0:RAMB36_X2Y19 DSP48_X0Y0:DSP48_X1Y59"
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# Most of CMT X0Y2.
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export XRAY_ROI_GRID_X1="9"
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export XRAY_ROI_GRID_X2="58"
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# Include VBRK / VTERM
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export XRAY_ROI_GRID_Y1="0"
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export XRAY_ROI_GRID_Y2="52"
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@ -90,24 +92,24 @@ Results have checksums;
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* [`6864d8edcef442cb129f83b9c5cd27be85d1b4bded8007bbeadcfc70717f8c48 ./artix7/gridinfo/grid-xc7a50tfgg484-1-db.txt`](./artix7/gridinfo/grid-xc7a50tfgg484-1-db.txt)
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* [`8416e8eef29e5defebbd3e45f60baa15cbcc22d66647a8da62ec7c42eff8b521 ./artix7/harness/arty-a7/pmod/design.bit`](./artix7/harness/arty-a7/pmod/design.bit)
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* [`c98eefb677a5cd469b75223d6ceb0e95f5d331de00291193caed008f33ee746c ./artix7/harness/arty-a7/pmod/design.dcp`](./artix7/harness/arty-a7/pmod/design.dcp)
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* [`856f9f5845a6eea5b7df26a110ed6fefa37a8cf4a8653ef9876c76e233005e03 ./artix7/harness/arty-a7/pmod/design.json`](./artix7/harness/arty-a7/pmod/design.json)
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* [`64173d4eabd1ed0d33f8513d5247a384635c8352ea3b0c86bdb30b1229e8b713 ./artix7/harness/arty-a7/pmod/design.json`](./artix7/harness/arty-a7/pmod/design.json)
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* [`0c0db34e2b1a0f38b05799ad7e042874d43443d79426e9f32f0b63c71a8c9d3d ./artix7/harness/arty-a7/pmod/design.txt`](./artix7/harness/arty-a7/pmod/design.txt)
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* [`0df8a22d29a4425ee1da4363b8cdb56c82c1ab71913fbe36b4470b3ebc082c60 ./artix7/harness/arty-a7/swbut/design.bit`](./artix7/harness/arty-a7/swbut/design.bit)
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* [`578bbe948ecc1af59c3e9cda0aacd53841d31534a6ec156af9d2779aee8770f4 ./artix7/harness/arty-a7/swbut/design.dcp`](./artix7/harness/arty-a7/swbut/design.dcp)
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* [`e291554cf40e009b4ca1981c514bf3fb54eccd411d8133d3ef743d9efeaea783 ./artix7/harness/arty-a7/swbut/design.json`](./artix7/harness/arty-a7/swbut/design.json)
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* [`44fbfe293c32ae7729c10ae7df08a7f85703feb2129949be30af6c5b1202c14d ./artix7/harness/arty-a7/swbut/design.json`](./artix7/harness/arty-a7/swbut/design.json)
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* [`d8c1255df5bc352fbff05b9688b86becfc7d28ee82663256332e0a7b8ac4b338 ./artix7/harness/arty-a7/swbut/design.txt`](./artix7/harness/arty-a7/swbut/design.txt)
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* [`c805c150d4a58e392a1c41046261fec0b2c76fe1cce5812253902fc95715ba54 ./artix7/harness/basys3/swbut/design.bit`](./artix7/harness/basys3/swbut/design.bit)
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* [`29981e44415eaeff674c940dcd5b5be4fc5b04efa1c10f6a43eb054101e0c966 ./artix7/harness/basys3/swbut/design.dcp`](./artix7/harness/basys3/swbut/design.dcp)
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* [`b80709f701e7d3611aa9c8d9c70640374f2eb2c15cd7e64fa74d6b4211a9b197 ./artix7/harness/basys3/swbut/design.json`](./artix7/harness/basys3/swbut/design.json)
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* [`e2d3754c0e87be5e1c511b9564843644d7bc787229267d7f43a432f93a99ffd5 ./artix7/harness/basys3/swbut/design.json`](./artix7/harness/basys3/swbut/design.json)
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* [`cd4000b96378f736d31686b381ebd4349898b3b8bd09606223c7ca48cb1a5aba ./artix7/harness/basys3/swbut/design.txt`](./artix7/harness/basys3/swbut/design.txt)
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* [`4c0a815ab8943181331f7aa9ac77655a0a640d9a409a602e4f24f8feb5f905e9 ./artix7/harness/README.md`](./artix7/harness/README.md)
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* [`69f298082e6c8e537d8348b9d4c01f582d0d86fdeddf1e6606b90e800994bcdd ./artix7/mask_bram_l.db`](./artix7/mask_bram_l.db)
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* [`169a5dc2a069653f17dad854fff1895e3981bcd703109304f719d7f1b3a02ab1 ./artix7/mask_bram_r.db`](./artix7/mask_bram_r.db)
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* [`1c863520307fac805e9dec67ed91eabf663e7cf873b3da16e581cefa771ed9c4 ./artix7/mask_bram_l.db`](./artix7/mask_bram_l.db)
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* [`9b0ecfed6b65de55c9975d59c92512f3f67ed5cc07106d027eb63edaffe53fca ./artix7/mask_bram_r.db`](./artix7/mask_bram_r.db)
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* [`5c274320294201935a3edccb43eca8e347ca1f0acded71ec388c794877d4b55b ./artix7/mask_clbll_l.db`](./artix7/mask_clbll_l.db)
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* [`5c274320294201935a3edccb43eca8e347ca1f0acded71ec388c794877d4b55b ./artix7/mask_clbll_r.db`](./artix7/mask_clbll_r.db)
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* [`5c274320294201935a3edccb43eca8e347ca1f0acded71ec388c794877d4b55b ./artix7/mask_clblm_l.db`](./artix7/mask_clblm_l.db)
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* [`5c274320294201935a3edccb43eca8e347ca1f0acded71ec388c794877d4b55b ./artix7/mask_clblm_r.db`](./artix7/mask_clblm_r.db)
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* [`69f298082e6c8e537d8348b9d4c01f582d0d86fdeddf1e6606b90e800994bcdd ./artix7/mask_dsp_l.db`](./artix7/mask_dsp_l.db)
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* [`ad8008e2e4dfd461e421b15f236cd1862e501e5679ad292ede421122373e224f ./artix7/mask_dsp_l.db`](./artix7/mask_dsp_l.db)
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* [`169a5dc2a069653f17dad854fff1895e3981bcd703109304f719d7f1b3a02ab1 ./artix7/mask_dsp_r.db`](./artix7/mask_dsp_r.db)
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* [`76d1e0bd4b7ad492cf3fe8698b2b5f46f7dcc5fe446984e5dccae373c63edafd ./artix7/mask_hclk_l.db`](./artix7/mask_hclk_l.db)
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* [`76d1e0bd4b7ad492cf3fe8698b2b5f46f7dcc5fe446984e5dccae373c63edafd ./artix7/mask_hclk_r.db`](./artix7/mask_hclk_r.db)
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@ -119,173 +121,177 @@ Results have checksums;
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* [`81e0696179a33bdf8d2279a53b406911a403d50224355e9ad29eccee01a70305 ./artix7/ppips_hclk_r.db`](./artix7/ppips_hclk_r.db)
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* [`be617c15d1ec311b6249791414bbd69380fe90b476353cbb2fc2a7cb06f5029d ./artix7/ppips_int_l.db`](./artix7/ppips_int_l.db)
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* [`a1423859c97a82dcfb114644f50b991db4ca7e0996e6d1ae4d2c97bfdfcb723d ./artix7/ppips_int_r.db`](./artix7/ppips_int_r.db)
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* [`3b359f4fa09bb224b88ce7c3060b890a611bf1d68319b3dabeed5157d3f42bb8 ./artix7/segbits_clbll_l.db`](./artix7/segbits_clbll_l.db)
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* [`d21b75b8912c30de5e1ab0256bdb7dbb0590d205c36fcfca11ce522d84854eef ./artix7/segbits_clbll_r.db`](./artix7/segbits_clbll_r.db)
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* [`816ae2c85b352788bcccf62bdfff1935a9d4871eb975196b0cc2d07f25ef0068 ./artix7/segbits_clblm_l.db`](./artix7/segbits_clblm_l.db)
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* [`4108286bcffee65beea5574e8f068a74c0321bab27349eb312376ed71cfc3010 ./artix7/segbits_clblm_r.db`](./artix7/segbits_clblm_r.db)
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* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./artix7/segbits_bram_l.block_ram.db`](./artix7/segbits_bram_l.block_ram.db)
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* [`b3011b6a49b05f1f0a40b499537d0f3eb208a51b87d6d97811911df50d4ad2d2 ./artix7/segbits_bram_l.db`](./artix7/segbits_bram_l.db)
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* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./artix7/segbits_bram_r.block_ram.db`](./artix7/segbits_bram_r.block_ram.db)
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* [`ac4e1c029ed8e623985ca2665e7aa1fae57aa2b33defb5f8cfa17d34d160e4b1 ./artix7/segbits_bram_r.db`](./artix7/segbits_bram_r.db)
|
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* [`280eb9f102fe5fb64a657088b277d08bb0600c90507a17567bf44b544b6cf2ac ./artix7/segbits_clbll_l.db`](./artix7/segbits_clbll_l.db)
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* [`28a4160e4ce09f2a3d015b913d4f0a320ff8e47088fdada9622fcdf8c4b523e6 ./artix7/segbits_clbll_r.db`](./artix7/segbits_clbll_r.db)
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* [`de134d4d2a9e1e2aed74bffaea198d886d12e7e906152d58cc777db65d58e2d2 ./artix7/segbits_clblm_l.db`](./artix7/segbits_clblm_l.db)
|
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* [`b1e17491351b2f402df2415ef0908d8ff4e84fa645180c2c9931843c479d8e45 ./artix7/segbits_clblm_r.db`](./artix7/segbits_clblm_r.db)
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* [`20f7bf469951b04a56e5e140b6327470750b08960643353384b35baf85eb9117 ./artix7/segbits_hclk_l.db`](./artix7/segbits_hclk_l.db)
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* [`5e22f758a04eab3185b2453c9994aa2fa48f50ca8a6b49bf82e8fc4351f23a5c ./artix7/segbits_hclk_r.db`](./artix7/segbits_hclk_r.db)
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* [`08dee581e565abbd09db559f9226139ba5a253f8aec4f3492152d8df8a87bbab ./artix7/segbits_int_l.db`](./artix7/segbits_int_l.db)
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* [`90d9243f3210a3ac7feb0d5c4434d62bd74ebf5edc75b95a9eae22540d462d3f ./artix7/segbits_int_l.db`](./artix7/segbits_int_l.db)
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* [`13bc58bf4a42029adf4f9b06ffd7c9436e2294bf4fdc16cdaa70505c28a2a7b7 ./artix7/segbits_int_r.db`](./artix7/segbits_int_r.db)
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* [`cb777c1e854d877556482ff2067eff348386ce627caa0ef5617a6e5dea01dc6a ./artix7/settings.sh`](./artix7/settings.sh)
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* [`3f6ab41214df9776a9cd8ea63cca60adab925abf08a3204549fa956ef87270de ./artix7/site_type_BSCAN.json`](./artix7/site_type_BSCAN.json)
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* [`b1e326e9c93fa1d239423b681aa22a1f999994280a6ef94626eafeb855d93571 ./artix7/site_type_BUFGCTRL.json`](./artix7/site_type_BUFGCTRL.json)
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* [`04a2cffb41ec815914fc361cb527df69cb36e4db74f25de6792c59f6ce97f6d3 ./artix7/site_type_BUFHCE.json`](./artix7/site_type_BUFHCE.json)
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* [`b8fba943d1daba4bf68b60662ecd54d15d2e420844b3c365fccbbf540397e04f ./artix7/site_type_BUFIO.json`](./artix7/site_type_BUFIO.json)
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* [`6eee616ddd66d86ed27d23bf3fbe6d964ae0dcc7ee4b9acdc08a0b5fbe192716 ./artix7/site_type_BUFMRCE.json`](./artix7/site_type_BUFMRCE.json)
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* [`61463380a7c97068b62bc8d8ca6f3da2952fe53e03adc047b932fb4478ee10e5 ./artix7/site_type_BUFR.json`](./artix7/site_type_BUFR.json)
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* [`4d9bff782e23eec21c5297ef886b3091ae374cdcb38f946eb87f015945982c0a ./artix7/site_type_CAPTURE.json`](./artix7/site_type_CAPTURE.json)
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* [`74c501f8de850d82eb3f3c9b1e50dfb0c29ead2449b03d85378bef0483219e0f ./artix7/site_type_DCIRESET.json`](./artix7/site_type_DCIRESET.json)
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* [`a3abad475dd74f0440940410ac9f2f42f0c451f0735150eb6ca4b9db677bafc2 ./artix7/site_type_DNA_PORT.json`](./artix7/site_type_DNA_PORT.json)
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* [`40e35d71c2a160ef3d118f978f6223eb71c32c51f26c610e9e70bf3429f14b98 ./artix7/site_type_DSP48E1.json`](./artix7/site_type_DSP48E1.json)
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* [`4c2c513fd2f431c471cac55f9a1f5a806ce7215b9ff95fdb4e74b9011b53a396 ./artix7/site_type_EFUSE_USR.json`](./artix7/site_type_EFUSE_USR.json)
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* [`bdf8fe24883948cdcbefb1f9b2b0dd1f2533d994b688b0704a24f921cfa4d99f ./artix7/site_type_FIFO18E1.json`](./artix7/site_type_FIFO18E1.json)
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* [`284bc518c0512f70f2603760167bac98fb906c96ce6c251cc1d56e4e87e378cd ./artix7/site_type_FRAME_ECC.json`](./artix7/site_type_FRAME_ECC.json)
|
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* [`d4b2ff801a0f3ab6d8c38aa62de389b8ff3952b1867539cda26e08172731de29 ./artix7/site_type_GTPE2_CHANNEL.json`](./artix7/site_type_GTPE2_CHANNEL.json)
|
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* [`27c8cefd0ffd675d7c24c68e4662fc406673c25875701b8296d59a68908b41d0 ./artix7/site_type_GTPE2_COMMON.json`](./artix7/site_type_GTPE2_COMMON.json)
|
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* [`e85ae0c6b4a240b9783b013ff5917fabb06dea964fe877c1fc7c20f3b33ba8ed ./artix7/site_type_IBUFDS_GTE2.json`](./artix7/site_type_IBUFDS_GTE2.json)
|
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* [`d706003a200bc4309f7ef341015682f7dd54fba6b141477c23861bb9cd0d4486 ./artix7/site_type_ICAP.json`](./artix7/site_type_ICAP.json)
|
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* [`6a80e0e7d8d3204a85cf2e936ddaf4b23d6c00f62fbce8c9db417d18f06a0c3e ./artix7/site_type_IDELAYCTRL.json`](./artix7/site_type_IDELAYCTRL.json)
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* [`6028d3d30bba5d7b358fb6fbc59748093acbb7da70aec150f8802f77d8f87b07 ./artix7/site_type_IDELAYE2.json`](./artix7/site_type_IDELAYE2.json)
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* [`438f89ca18cdaed11e9de8ef6795544baa1ac4615ff700af7ed74e9d8a20fd1b ./artix7/site_type_ILOGICE3.json`](./artix7/site_type_ILOGICE3.json)
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* [`3c1b001db1ac05cbc830802c26619aaeb523b098c9b399a58bf8881d2a02c64d ./artix7/site_type_IN_FIFO.json`](./artix7/site_type_IN_FIFO.json)
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* [`9f5a74baa3d1fa9c741960474e5d877a9bb154471441625a0316f93a7ee5e143 ./artix7/site_type_IOB33.json`](./artix7/site_type_IOB33.json)
|
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* [`3b9f691b31151a937c853167a76a5fc7cfd4b953911b8094a699f43d7a7f3817 ./artix7/site_type_IOB33M.json`](./artix7/site_type_IOB33M.json)
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||||
* [`96c85a161b70018c34afa42e4702c41b7830b74277cbecce591fb0e18db615fa ./artix7/site_type_IOB33S.json`](./artix7/site_type_IOB33S.json)
|
||||
* [`6922af5e94c020bf330e088a74c09ad7be09b4264756154dea5769d5631e22bf ./artix7/site_type_IPAD.json`](./artix7/site_type_IPAD.json)
|
||||
* [`0a7bc04c8bd544fc3aad7049e3964ffbc7c518940910c7c6a4b89861b1aa7f45 ./artix7/site_type_MMCME2_ADV.json`](./artix7/site_type_MMCME2_ADV.json)
|
||||
* [`ef28166f73ad270ee5fc64968012ae41107076e623cb64eb9b35e49bf9859f65 ./artix7/site_type_OLOGICE3.json`](./artix7/site_type_OLOGICE3.json)
|
||||
* [`26a864898c5fccc0713e6c50cc1d979b85c7f80ef283ad7f4bebc390b272a0a0 ./artix7/site_type_OPAD.json`](./artix7/site_type_OPAD.json)
|
||||
* [`ff4222fff87a32b2d60f9d369351d5a6562d45cbb81bb57932e7a300b841f7aa ./artix7/site_type_OUT_FIFO.json`](./artix7/site_type_OUT_FIFO.json)
|
||||
* [`a5645197aa379ff9fc84a44db88a9f1607e0997340dafc15b9a841f44f7aecdb ./artix7/site_type_PCIE_2_1.json`](./artix7/site_type_PCIE_2_1.json)
|
||||
* [`dc92ad839e19b851026f0d51aef5c3eca10b515a8d62531dc80c27dfc5091662 ./artix7/site_type_PHASER_IN_PHY.json`](./artix7/site_type_PHASER_IN_PHY.json)
|
||||
* [`cda392eabd755443dff137a722d7b0d4025cc227e1f5e145aadd98cbbd0da0f4 ./artix7/site_type_PHASER_OUT_PHY.json`](./artix7/site_type_PHASER_OUT_PHY.json)
|
||||
* [`72d4e83a5804df49866853b801d85c54b394dcafc63ac3ea6e34d491706d11c8 ./artix7/site_type_PHASER_REF.json`](./artix7/site_type_PHASER_REF.json)
|
||||
* [`6e792b1cedee55c39ab8cf647fc995566881e69829dfcfffa57abd356b49758b ./artix7/site_type_PHY_CONTROL.json`](./artix7/site_type_PHY_CONTROL.json)
|
||||
* [`dc0d72419c95f0889bb7456f9a0918dff2682e22e98b9dccde3ff7601daafdfd ./artix7/site_type_PLLE2_ADV.json`](./artix7/site_type_PLLE2_ADV.json)
|
||||
* [`2495d3a037afd68198f70e586e8c74bce54e8eabcb32b10b785d188436280bb7 ./artix7/site_type_PMV2.json`](./artix7/site_type_PMV2.json)
|
||||
* [`88d6ebac0ebdd0e2ef8a944dcacfcfd78420f72727d258aba070d8e6eb609f69 ./artix7/site_type_RAMB18E1.json`](./artix7/site_type_RAMB18E1.json)
|
||||
* [`320778636593bbbd2f8bd8097941b7b379ea5dbfc61a206bcee5dab64c504b7e ./artix7/site_type_RAMBFIFO36E1.json`](./artix7/site_type_RAMBFIFO36E1.json)
|
||||
* [`e57b372cbe08c97dc7678bb132058c0cd7f41e8d120b38ee117ad6cc25ebe00a ./artix7/site_type_SLICEL.json`](./artix7/site_type_SLICEL.json)
|
||||
* [`c9a6b2741f6d77ecf39d7bf5d2f1145a1a1ee5ef06619830a23d3fe6b63043d1 ./artix7/site_type_SLICEM.json`](./artix7/site_type_SLICEM.json)
|
||||
* [`2edebd3fb074b965e1cc2ed3d31528e2037321cbdd883142c00403681b91751a ./artix7/site_type_STARTUP.json`](./artix7/site_type_STARTUP.json)
|
||||
* [`7329766c3d005888d7c26e2971eede01b5868561ebf3a2fd79418ede9b8eea7e ./artix7/site_type_TIEOFF.json`](./artix7/site_type_TIEOFF.json)
|
||||
* [`6746bf25b93062155c468035227aa8ef912c147eb0d97e3724d1ab2c3acb9065 ./artix7/site_type_USR_ACCESS.json`](./artix7/site_type_USR_ACCESS.json)
|
||||
* [`4152c0be5caf2fe2810dac83454e30ad41506031c16786e984bfb50bc9fd82d8 ./artix7/site_type_XADC.json`](./artix7/site_type_XADC.json)
|
||||
* [`d0d86823154a508161b8a1a8b6206236b627741516418d4dd5b5f01b6a88992d ./artix7/tileconn.json`](./artix7/tileconn.json)
|
||||
* [`e4714777a45ecef568f8915a7fef0bd7487e209d9e3c513b0d9d7e5a5d64f227 ./artix7/tilegrid.json`](./artix7/tilegrid.json)
|
||||
* [`96bd9762fcbef56313fee998f9d71e86434a0bf5b1bd49d8cb39f7f4043cdd8f ./artix7/tile_type_BRAM_INT_INTERFACE_L.json`](./artix7/tile_type_BRAM_INT_INTERFACE_L.json)
|
||||
* [`cc34b1d6319fe191bdba0a4317fb8f36060015aa96a7c822fd0b9bbee744d39b ./artix7/tile_type_BRAM_INT_INTERFACE_R.json`](./artix7/tile_type_BRAM_INT_INTERFACE_R.json)
|
||||
* [`509db2857c61a69275743dbd86eb129366412ce17df62300fdee9b980703330e ./artix7/tile_type_BRAM_L.json`](./artix7/tile_type_BRAM_L.json)
|
||||
* [`a5cc5eb48161440a48585304d2364067d2807bd618b7f31309b3e40a78b85f0d ./artix7/tile_type_BRAM_R.json`](./artix7/tile_type_BRAM_R.json)
|
||||
* [`1dba05eeed981c1e0fa2179918bb692cb21a7d7fa5122f10bf5479706e1e616b ./artix7/tile_type_BRKH_BRAM.json`](./artix7/tile_type_BRKH_BRAM.json)
|
||||
* [`3e9da0953579409e59428e455e17bda198a29d54390e5f57ee436775f66a9138 ./artix7/tile_type_BRKH_B_TERM_INT.json`](./artix7/tile_type_BRKH_B_TERM_INT.json)
|
||||
* [`434771e6f6ed7b0ca283edf42befd2fefd8e5de26c933d346df676662d33b6c5 ./artix7/tile_type_BRKH_CLB.json`](./artix7/tile_type_BRKH_CLB.json)
|
||||
* [`329e0d77958e01e1a9c27cbbe15f86de2f5c4acbad122181dbfc0560e3df106a ./artix7/tile_type_BRKH_CLK.json`](./artix7/tile_type_BRKH_CLK.json)
|
||||
* [`49ae3a8c79dad931c7a79c746f36d963567fd757f36b74d6b0b088461ee0f59e ./artix7/tile_type_BRKH_CMT.json`](./artix7/tile_type_BRKH_CMT.json)
|
||||
* [`c1a3651e57b00d01134cff1314c25b16bcc965ee0569ac6d03bb4a3eddf1388a ./artix7/tile_type_BRKH_DSP_L.json`](./artix7/tile_type_BRKH_DSP_L.json)
|
||||
* [`952e7c1c4d9f2f9f368df0be54be09c79b3924a4e539e5e6ab4a9aec1661f268 ./artix7/tile_type_BRKH_DSP_R.json`](./artix7/tile_type_BRKH_DSP_R.json)
|
||||
* [`d2eabfc7818d23215ea38b3e68cfdadb91ca30bb39839bf47af4ceae9e4eed10 ./artix7/tile_type_BRKH_GTX.json`](./artix7/tile_type_BRKH_GTX.json)
|
||||
* [`88686877ac897b2f5c5bbcb02e14e8f60a424e560f8cf003a5e940c83f5ddf46 ./artix7/tile_type_BRKH_INT.json`](./artix7/tile_type_BRKH_INT.json)
|
||||
* [`fd2249a437197885384c08ce702307f26cc8d126edbacd52c54e8e1434fefa0e ./artix7/tile_type_BRKH_TERM_INT.json`](./artix7/tile_type_BRKH_TERM_INT.json)
|
||||
* [`a8d81a873cb0688754abd313da95879cfa380cae3f8da7976f9c059e9aac4d09 ./artix7/tile_type_B_TERM_INT.json`](./artix7/tile_type_B_TERM_INT.json)
|
||||
* [`c1238348a056b5dae21a1a44c5123fdce85755d98fa49c740d8a383f9f7d7e13 ./artix7/tile_type_CFG_CENTER_BOT.json`](./artix7/tile_type_CFG_CENTER_BOT.json)
|
||||
* [`60dc54d12e3f3d6ecdcf01f45ad75a99e6bb7d22b5842eec521fdcea986b7b77 ./artix7/tile_type_CFG_CENTER_MID.json`](./artix7/tile_type_CFG_CENTER_MID.json)
|
||||
* [`1a9b9d718034c8f7d6a9bb04847cf2d3b0d8f74e6e581a35aaaa8235f79d3af8 ./artix7/tile_type_CFG_CENTER_TOP.json`](./artix7/tile_type_CFG_CENTER_TOP.json)
|
||||
* [`c22e7f31794cc3fc1070cb546e7584102ca62a7f86ad1823313961699a072bc4 ./artix7/tile_type_CLBLL_L.json`](./artix7/tile_type_CLBLL_L.json)
|
||||
* [`f1c43a89f4c5427d235867ffcc5cbf908252f1bf510f71c4aabcb7ab34d805e8 ./artix7/tile_type_CLBLL_R.json`](./artix7/tile_type_CLBLL_R.json)
|
||||
* [`daad6e76b986e23fb88c0b93a739f419eb924f91cedc5bc87285db889f0eee68 ./artix7/tile_type_CLBLM_L.json`](./artix7/tile_type_CLBLM_L.json)
|
||||
* [`6e803df11513a9caad8d7de723cdba867cd8c630d8e48163a941bb75945d5426 ./artix7/tile_type_CLBLM_R.json`](./artix7/tile_type_CLBLM_R.json)
|
||||
* [`07f5eaa242ee26bfaf46751f1c85b8735f27e547d6ba6c1efc97d5ff629f77a5 ./artix7/tile_type_CLK_BUFG_BOT_R.json`](./artix7/tile_type_CLK_BUFG_BOT_R.json)
|
||||
* [`64bfc2aef95d3c080bc0eb89ad2fe78946dd08f3b18d02bdac8a6edcc5e8a874 ./artix7/tile_type_CLK_BUFG_REBUF.json`](./artix7/tile_type_CLK_BUFG_REBUF.json)
|
||||
* [`26b5499eaf4c78ebbcfbedbd353c75a739b0e74cc3b56d18ed1a9216d67d3977 ./artix7/tile_type_CLK_BUFG_TOP_R.json`](./artix7/tile_type_CLK_BUFG_TOP_R.json)
|
||||
* [`b56c24f19f8a4629c7f110d31fac19c362d90c72ab7a5c824a087a23179b5d51 ./artix7/tile_type_CLK_FEED.json`](./artix7/tile_type_CLK_FEED.json)
|
||||
* [`1d31b4dbec6587875144c362e15871a51747da31d83da93dcfa0b0323a12f3c9 ./artix7/tile_type_CLK_HROW_BOT_R.json`](./artix7/tile_type_CLK_HROW_BOT_R.json)
|
||||
* [`b31aff49780d075be6bb5805465206d9de7b3fb9b58dfd0cc6f47f73bd16448f ./artix7/tile_type_CLK_HROW_TOP_R.json`](./artix7/tile_type_CLK_HROW_TOP_R.json)
|
||||
* [`57c35d6ffa8ef48238dc8ce9ae2410dea367f9d3ad913f5e79dd460b44530130 ./artix7/tile_type_CLK_MTBF2.json`](./artix7/tile_type_CLK_MTBF2.json)
|
||||
* [`640ec690886110946ba82e5285c8e49f0a05d08ff734a5c29350d8e29b712d61 ./artix7/tile_type_CLK_PMV2.json`](./artix7/tile_type_CLK_PMV2.json)
|
||||
* [`3594df245c20773ddcb284051106e849965f4ff2805ad860b4e30e81ec7394b8 ./artix7/tile_type_CLK_PMV2_SVT.json`](./artix7/tile_type_CLK_PMV2_SVT.json)
|
||||
* [`4224e30e6cd0ef19a2e6e8c4d6f6a79f5c2ec32d3611a9828643e166310f5ba9 ./artix7/tile_type_CLK_PMVIOB.json`](./artix7/tile_type_CLK_PMVIOB.json)
|
||||
* [`07127da65c6d3f4626f9f9998bff4c765d2915105c9ed7e221ce15e55d48b931 ./artix7/tile_type_CLK_PMV.json`](./artix7/tile_type_CLK_PMV.json)
|
||||
* [`d68d9a3d3deda97961c6b0f4291cd5d4abaa43f857a58ce54c5382f27f50d87b ./artix7/tile_type_CLK_TERM.json`](./artix7/tile_type_CLK_TERM.json)
|
||||
* [`75a6fb608f520f0426d80248dfd494c8e12a18e61eb9987c1db899b7095924e1 ./artix7/tile_type_CMT_FIFO_L.json`](./artix7/tile_type_CMT_FIFO_L.json)
|
||||
* [`31d4070f65a35538fdad0bd8a83323b2dbc639c0045b29ade3aacf3a42ea75d3 ./artix7/tile_type_CMT_FIFO_R.json`](./artix7/tile_type_CMT_FIFO_R.json)
|
||||
* [`459f15606ca5b02f0f111b61ac5d5a77343b4ad0526d8071b3ae75b93620b856 ./artix7/tile_type_CMT_PMV.json`](./artix7/tile_type_CMT_PMV.json)
|
||||
* [`73e78465cea1179ed85ed7e4af40586d74b5f865443c1fe5421157bea5373dae ./artix7/tile_type_CMT_PMV_L.json`](./artix7/tile_type_CMT_PMV_L.json)
|
||||
* [`22225c63385fe168ebb71620d5f3dcde16390493d69a94e2bb980f52240de032 ./artix7/tile_type_CMT_TOP_L_LOWER_B.json`](./artix7/tile_type_CMT_TOP_L_LOWER_B.json)
|
||||
* [`b525c403635abbd7d25758783ead521a7f48ce74aa82d187b4c40aac11ccff63 ./artix7/tile_type_CMT_TOP_L_LOWER_T.json`](./artix7/tile_type_CMT_TOP_L_LOWER_T.json)
|
||||
* [`423c600a061a44d2c5992a74489e043156f0ce51bddea0179ad3839118d97300 ./artix7/tile_type_CMT_TOP_L_UPPER_B.json`](./artix7/tile_type_CMT_TOP_L_UPPER_B.json)
|
||||
* [`cd031c507deb41780832b200a1ad529875cb6e6e37fe9d297de6da09bca9a862 ./artix7/tile_type_CMT_TOP_L_UPPER_T.json`](./artix7/tile_type_CMT_TOP_L_UPPER_T.json)
|
||||
* [`5abf0285d3445d56cf14f84e5c35f9f08b38d5536d0450da2dbcb2ee402843af ./artix7/tile_type_CMT_TOP_R_LOWER_B.json`](./artix7/tile_type_CMT_TOP_R_LOWER_B.json)
|
||||
* [`b5c0c6a388c2daef9f015ed902eafcb39e188fd6f703d26278567c23d563d05a ./artix7/tile_type_CMT_TOP_R_LOWER_T.json`](./artix7/tile_type_CMT_TOP_R_LOWER_T.json)
|
||||
* [`e8b16871b40ad1723c81b947273f3076e3822ee481618ac9225a171880e874e8 ./artix7/tile_type_CMT_TOP_R_UPPER_B.json`](./artix7/tile_type_CMT_TOP_R_UPPER_B.json)
|
||||
* [`2b1da4927adbd17c1bbbc8065660fba5b86cc0bf1744fd5a29093b15ca7fd4a3 ./artix7/tile_type_CMT_TOP_R_UPPER_T.json`](./artix7/tile_type_CMT_TOP_R_UPPER_T.json)
|
||||
* [`66ad652bb45bbac2e97037a3abf6e4ce84f156991f957dba26b45a7e16fe3ff0 ./artix7/tile_type_DSP_L.json`](./artix7/tile_type_DSP_L.json)
|
||||
* [`acaf6cef3d56adae402461ae65436adecbfe917b51130815d70a7687decc9349 ./artix7/tile_type_DSP_R.json`](./artix7/tile_type_DSP_R.json)
|
||||
* [`32f16cf599af10eb001ffde848d2d2ca7639e9a0a0a1ad71e4ad00839e779f15 ./artix7/tile_type_GTP_CHANNEL_0.json`](./artix7/tile_type_GTP_CHANNEL_0.json)
|
||||
* [`93f44305d6c81e5d79086bf1a4788f0f330289b6488d6b39a6223a929deb3bb3 ./artix7/tile_type_GTP_CHANNEL_1.json`](./artix7/tile_type_GTP_CHANNEL_1.json)
|
||||
* [`8f6f73d74921ef0b581535cf6e772bd36da38e065c1d40c3e273b4bb8a03c0fa ./artix7/tile_type_GTP_CHANNEL_2.json`](./artix7/tile_type_GTP_CHANNEL_2.json)
|
||||
* [`c7b191abe2299171aedfcbff19d8119dadc07e8374eb25cf03ba66464aa36d63 ./artix7/tile_type_GTP_CHANNEL_3.json`](./artix7/tile_type_GTP_CHANNEL_3.json)
|
||||
* [`ac6166d744ff39b887886012f52cf0f9ccb658a187b438e83d43e1fcba331580 ./artix7/tile_type_GTP_COMMON.json`](./artix7/tile_type_GTP_COMMON.json)
|
||||
* [`99b8469c4d666836daeaab3b6417375242bcae0754109102f85b5c7eea62e545 ./artix7/tile_type_GTP_INT_INTERFACE.json`](./artix7/tile_type_GTP_INT_INTERFACE.json)
|
||||
* [`d2b19757fd7c73d130ddafbed0faf72d4e4436eead7f4675ae1181d6d8a68d50 ./artix7/tile_type_HCLK_BRAM.json`](./artix7/tile_type_HCLK_BRAM.json)
|
||||
* [`7602524759035e96bb966ed5ac3c42734376ea9774588918e323796ccf9f6f3a ./artix7/tile_type_HCLK_CLB.json`](./artix7/tile_type_HCLK_CLB.json)
|
||||
* [`3bac2f61dcbf39fea3066fd3c5f0162b0f9b9928c630046c5081a1a00562c682 ./artix7/tile_type_HCLK_CMT.json`](./artix7/tile_type_HCLK_CMT.json)
|
||||
* [`75624a70cf598442283771416ffe99c961d7ad655235e955631e2e3a3c76eb9e ./artix7/tile_type_HCLK_CMT_L.json`](./artix7/tile_type_HCLK_CMT_L.json)
|
||||
* [`a696906513f868f89c4429f00e6c0451336544ad23b9033df6d3f75370b87183 ./artix7/tile_type_HCLK_DSP_L.json`](./artix7/tile_type_HCLK_DSP_L.json)
|
||||
* [`c2bb2ba94a8d789c22856014cb5257b9bd7f1c93b9d9c4bf2865188d5a5891b1 ./artix7/tile_type_HCLK_DSP_R.json`](./artix7/tile_type_HCLK_DSP_R.json)
|
||||
* [`836677a427eb6530e5808d8bdf26b03b7a27ac786615a8c2ca6f84941dff3d74 ./artix7/tile_type_HCLK_FEEDTHRU_1.json`](./artix7/tile_type_HCLK_FEEDTHRU_1.json)
|
||||
* [`7c9c6a027ebd89f54b57ba9a135d9eb1843a80a1e707ef37c64d3fead885c17e ./artix7/tile_type_HCLK_FEEDTHRU_2.json`](./artix7/tile_type_HCLK_FEEDTHRU_2.json)
|
||||
* [`881869baa9874c48fa3d11b78cd8fac446202a3bff4ebf30c9413640ba26ac39 ./artix7/tile_type_HCLK_FIFO_L.json`](./artix7/tile_type_HCLK_FIFO_L.json)
|
||||
* [`6954fd8e515e8beed9ce26f65abf3269b119fdb86b7247a0082c1618fc0d5e4d ./artix7/tile_type_HCLK_GTX.json`](./artix7/tile_type_HCLK_GTX.json)
|
||||
* [`d3e5b322b3847e5ca61436500fbffec6f9eee2ba813e3b4e997ebb501318ab38 ./artix7/tile_type_HCLK_INT_INTERFACE.json`](./artix7/tile_type_HCLK_INT_INTERFACE.json)
|
||||
* [`6b4850191cb040d640a4e99e4727c47b305cc9bee828143c0ddf02fc73ade8f8 ./artix7/tile_type_HCLK_IOB.json`](./artix7/tile_type_HCLK_IOB.json)
|
||||
* [`02b7b54a7ec81534bef46ab8c57c7eb232ddde7b7434f14705857ba4dfef6cab ./artix7/tile_type_HCLK_IOI3.json`](./artix7/tile_type_HCLK_IOI3.json)
|
||||
* [`86d4dc44b7ada38f320144986f77dadd48ab1441868f982e75f9f6b8f8f6e694 ./artix7/tile_type_HCLK_L_BOT_UTURN.json`](./artix7/tile_type_HCLK_L_BOT_UTURN.json)
|
||||
* [`226a6787452e47288a68f7458e367ec0a39ed7925b6404ac789b32dc2fe006ed ./artix7/tile_type_HCLK_L.json`](./artix7/tile_type_HCLK_L.json)
|
||||
* [`e4f0a9a1594a425ff5a99f84a2f34515b61ba1323a815b08dd57bd947eb7b545 ./artix7/tile_type_HCLK_R_BOT_UTURN.json`](./artix7/tile_type_HCLK_R_BOT_UTURN.json)
|
||||
* [`d87c6ac4b94c69d5bab4c12996d95d4389ab0a2a615e7397e1dd96c75c7a40d4 ./artix7/tile_type_HCLK_R.json`](./artix7/tile_type_HCLK_R.json)
|
||||
* [`33ea81f2555030771b7bd44c6619ca0e5583433da0e01ee0e2930e5a1f33d60e ./artix7/tile_type_HCLK_TERM_GTX.json`](./artix7/tile_type_HCLK_TERM_GTX.json)
|
||||
* [`81875ea3bce1aa1cdb2cc73b48d39911807bc2948b81a062f7d587c8dc43e13b ./artix7/tile_type_HCLK_TERM.json`](./artix7/tile_type_HCLK_TERM.json)
|
||||
* [`30cc3e3002a88010d7031cf128a37149c9ba05fb862ed4f2761543f7c0e76117 ./artix7/tile_type_HCLK_VBRK.json`](./artix7/tile_type_HCLK_VBRK.json)
|
||||
* [`4ff9d85171843ed8854c4991e5f425b4f83d6125fad1d523547ff49e1327c093 ./artix7/tile_type_HCLK_VFRAME.json`](./artix7/tile_type_HCLK_VFRAME.json)
|
||||
* [`5fb8b135a485853e88853d5d88044eaa8a2cbcdd4cd8c2192276e4dbbc79c2dc ./artix7/tile_type_INT_FEEDTHRU_1.json`](./artix7/tile_type_INT_FEEDTHRU_1.json)
|
||||
* [`69046907543c5d2821690b8217a2f6c4d94ada5cbbc446c1c3f3121bb8bf5a63 ./artix7/tile_type_INT_FEEDTHRU_2.json`](./artix7/tile_type_INT_FEEDTHRU_2.json)
|
||||
* [`e2a128688fa2cb0dcf0d9a2865d1be99e709ca79f032c5012ef0d0a456f8672e ./artix7/tile_type_INT_INTERFACE_L.json`](./artix7/tile_type_INT_INTERFACE_L.json)
|
||||
* [`14354fb555d1a48ba80df13a75fc3a6d10bbcaf164ee4bba4ad168d5b0b30a66 ./artix7/tile_type_INT_INTERFACE_R.json`](./artix7/tile_type_INT_INTERFACE_R.json)
|
||||
* [`ddc6f7153fc2c363a568f744fbf934971f978a02bc16d797d8e364cfd75526ca ./artix7/tile_type_INT_L.json`](./artix7/tile_type_INT_L.json)
|
||||
* [`92f8d11bfac53f072a60176dd88db65eafc72836b94ef32fbbdf62566dbc58d1 ./artix7/tile_type_INT_R.json`](./artix7/tile_type_INT_R.json)
|
||||
* [`77b19fbc668f84f06bf5eb97fd57c5384736e2bd421066a5f1153f3c4a0c5218 ./artix7/tile_type_IO_INT_INTERFACE_L.json`](./artix7/tile_type_IO_INT_INTERFACE_L.json)
|
||||
* [`db8165acebe5ab2f999947e47671aa2ecc2c4c55fca01477e972feedf8743a95 ./artix7/tile_type_IO_INT_INTERFACE_R.json`](./artix7/tile_type_IO_INT_INTERFACE_R.json)
|
||||
* [`a74a5d13a115b33869f44a586df07fdbbe220cf7b4b5127631465908dd2b0704 ./artix7/tile_type_LIOB33.json`](./artix7/tile_type_LIOB33.json)
|
||||
* [`0aa3ef5d5cfa96f983d34caa2622d717b5246d6527b8d99bc1e696085d2489e5 ./artix7/tile_type_LIOB33_SING.json`](./artix7/tile_type_LIOB33_SING.json)
|
||||
* [`298c949bf1d572fb1d887107e938a53f57d8d9df2c3cec6f5e83120379ccee37 ./artix7/tile_type_LIOI3.json`](./artix7/tile_type_LIOI3.json)
|
||||
* [`57f8b4bd7596ba9205151f1590bb31951224f5725a2064d8157b5e90014aef2d ./artix7/tile_type_LIOI3_SING.json`](./artix7/tile_type_LIOI3_SING.json)
|
||||
* [`b39aed9f4ee86472202ee8e986e378e6a517d9985927c3dbf1efdf6138887f6b ./artix7/tile_type_LIOI3_TBYTESRC.json`](./artix7/tile_type_LIOI3_TBYTESRC.json)
|
||||
* [`6dfa1fd318de1a04abc2601c53ce5a8d62f518c7116475eb9057bc121860d70a ./artix7/tile_type_LIOI3_TBYTETERM.json`](./artix7/tile_type_LIOI3_TBYTETERM.json)
|
||||
* [`0d9afa21f52f65fb0d541dba5a530e8ccbec906c5b58683648896f3092a52310 ./artix7/tile_type_L_TERM_INT.json`](./artix7/tile_type_L_TERM_INT.json)
|
||||
* [`7f1088bfbf484521a6316c918b75c9e84dd32e7846e6a32499d3fb6c842732f1 ./artix7/tile_type_MONITOR_BOT.json`](./artix7/tile_type_MONITOR_BOT.json)
|
||||
* [`333f69423f69afee987546623ab07298f166fb958fccafd51cf57a22eea04cdd ./artix7/tile_type_MONITOR_MID.json`](./artix7/tile_type_MONITOR_MID.json)
|
||||
* [`c86dc3f82a8c0d2dd19c41c993f2ee3ebe18c19a7ae63c0cab2bfc8f4fd48f66 ./artix7/tile_type_MONITOR_TOP.json`](./artix7/tile_type_MONITOR_TOP.json)
|
||||
* [`6b16e9202757be322b72cdcd73f45a1e61252444ef4ee6557272fc8361d87557 ./artix7/tile_type_NULL.json`](./artix7/tile_type_NULL.json)
|
||||
* [`f5f3dcd3a4cb9ccb9e2a5774372eeba4f07dfe58ff3b6c38729c6b2c801ddfc8 ./artix7/tile_type_PCIE_BOT.json`](./artix7/tile_type_PCIE_BOT.json)
|
||||
* [`9e07f51515ad2162c9921af8837a5d75923721395832cd0e83e3ac16b37b135d ./artix7/tile_type_PCIE_INT_INTERFACE_L.json`](./artix7/tile_type_PCIE_INT_INTERFACE_L.json)
|
||||
* [`9c62f669675e111af20f6b42602a36ed961ca7eb8dcbc1e5a849772a2a040063 ./artix7/tile_type_PCIE_INT_INTERFACE_R.json`](./artix7/tile_type_PCIE_INT_INTERFACE_R.json)
|
||||
* [`e39fb1e8b8c9d0d9da3307a260fee2bf05ad0f6dfa9456b90a031893b7131e2e ./artix7/tile_type_PCIE_NULL.json`](./artix7/tile_type_PCIE_NULL.json)
|
||||
* [`30e27f1479d7cd53afa17cc4f68da1c334072c05121bb5d00558aa95d1950b51 ./artix7/tile_type_PCIE_TOP.json`](./artix7/tile_type_PCIE_TOP.json)
|
||||
* [`80437b8acb8a79337e8604d2766a332b7816d8c7fbe1af5861da0a9189e27279 ./artix7/tile_type_RIOB33.json`](./artix7/tile_type_RIOB33.json)
|
||||
* [`9e082720755498836ae16cb09db4a3deb7915b57cf717a53bcfb59b49d4a980a ./artix7/tile_type_RIOB33_SING.json`](./artix7/tile_type_RIOB33_SING.json)
|
||||
* [`c558aadec95a82ba7f5fd7ebee72eff73f4f59ae45cf837481f017ae752f90df ./artix7/tile_type_RIOI3.json`](./artix7/tile_type_RIOI3.json)
|
||||
* [`3a774afda9268b4b78c94d97f2c82b61537aa16dced637ca4e69ec42a8ac3a74 ./artix7/tile_type_RIOI3_SING.json`](./artix7/tile_type_RIOI3_SING.json)
|
||||
* [`ff45bb72c86e2b1e88af816947d699e9d908c73e041d25a096036bbc396ce631 ./artix7/tile_type_RIOI3_TBYTESRC.json`](./artix7/tile_type_RIOI3_TBYTESRC.json)
|
||||
* [`7a1281adf9833c32c2b64ad874598a09b8a14578e8d14e2ab5dd7efab65b05ad ./artix7/tile_type_RIOI3_TBYTETERM.json`](./artix7/tile_type_RIOI3_TBYTETERM.json)
|
||||
* [`149e968062620a4cb5e16e85098b9f7240a64cb50e437fbd8f437ee031d82904 ./artix7/tile_type_R_TERM_INT_GTX.json`](./artix7/tile_type_R_TERM_INT_GTX.json)
|
||||
* [`7fdd280c9986b37a81b9f1963679a2fb71f4426108e301f419d1f8817a3ccde3 ./artix7/tile_type_R_TERM_INT.json`](./artix7/tile_type_R_TERM_INT.json)
|
||||
* [`13025cce4075e992a43f68e5ad8b59dba49ffdafd7735b5e81b7a416e34706c8 ./artix7/tile_type_TERM_CMT.json`](./artix7/tile_type_TERM_CMT.json)
|
||||
* [`23fc2dd5d45bd155822efb3b40b885999b389ddddc1bd50b6ea1e6ae09b0d2a8 ./artix7/tile_type_T_TERM_INT.json`](./artix7/tile_type_T_TERM_INT.json)
|
||||
* [`8e5aa8d4838cbb4c8da2cd821fecf563e945ec8b55bfccfdbeee615e0e076389 ./artix7/tile_type_VBRK_EXT.json`](./artix7/tile_type_VBRK_EXT.json)
|
||||
* [`6331c61d466365b90461b3f907fc150388566d478c935076f72e853eb31e3b23 ./artix7/tile_type_VBRK.json`](./artix7/tile_type_VBRK.json)
|
||||
* [`19035b8ca97a918c6029371c3caed0a81d0874582dbe82396c3b9fe03abb606a ./artix7/tile_type_VFRAME.json`](./artix7/tile_type_VFRAME.json)
|
||||
* [`d77b40f729b66962f0197a5e31b43860326401b6116ac36e727411319adac0f2 ./artix7/settings.sh`](./artix7/settings.sh)
|
||||
* [`1964c2803e6b0f4d372b5a14e1ef9e4091808c2c7c00bd28133b0009fbed245d ./artix7/site_type_BSCAN.json`](./artix7/site_type_BSCAN.json)
|
||||
* [`4fa1d86ce4dbfc4613a7ebb55a3e13991cd3e75b2e2114a337c2f02a0e87e678 ./artix7/site_type_BUFGCTRL.json`](./artix7/site_type_BUFGCTRL.json)
|
||||
* [`8ba38d2e8bc24d17cc8e48864851b8aebac7ca474dad7f6a8dd1f1132d7baed3 ./artix7/site_type_BUFHCE.json`](./artix7/site_type_BUFHCE.json)
|
||||
* [`5740037dbc51ac28ac205289ea1a86b6b41cf9a537f80c0ad5034970183cfbf4 ./artix7/site_type_BUFIO.json`](./artix7/site_type_BUFIO.json)
|
||||
* [`cba48853673d59e4f8c4359ad897f806c91268454958d83d8568d0e4ec4cc4dd ./artix7/site_type_BUFMRCE.json`](./artix7/site_type_BUFMRCE.json)
|
||||
* [`131fe7fddda638714900780dc66a032b7f9f417a4b387273cb3da3f6294ca76d ./artix7/site_type_BUFR.json`](./artix7/site_type_BUFR.json)
|
||||
* [`4d7dfb734e9cd51094ebb026bea0104ac72fc1747fd196e68bedda363155ad1b ./artix7/site_type_CAPTURE.json`](./artix7/site_type_CAPTURE.json)
|
||||
* [`d6d095ed918127a2970d71c73cf668124fc000fcf37ad5eec803dbd9efbe9a17 ./artix7/site_type_DCIRESET.json`](./artix7/site_type_DCIRESET.json)
|
||||
* [`012311ea9db7d8d1a88c6a8ad13bec27d8d77295f854aa74846f14b28cefcc75 ./artix7/site_type_DNA_PORT.json`](./artix7/site_type_DNA_PORT.json)
|
||||
* [`5552d8b433594c63d8ff68025dc32b4ce01926526d693641857449e3c0695dd0 ./artix7/site_type_DSP48E1.json`](./artix7/site_type_DSP48E1.json)
|
||||
* [`d2075b59398f90a9222e687c7d78a7e298b857932927574af45cd3c0ac27d3c0 ./artix7/site_type_EFUSE_USR.json`](./artix7/site_type_EFUSE_USR.json)
|
||||
* [`677f42ebcf8a1c4ad29e66b332b8cf6385224b0b055763034e064bc817edc3e2 ./artix7/site_type_FIFO18E1.json`](./artix7/site_type_FIFO18E1.json)
|
||||
* [`2f5700b15d191e1792237013dbe68cdbf9cc70d7fbe5126fb614dbe136b6ff66 ./artix7/site_type_FRAME_ECC.json`](./artix7/site_type_FRAME_ECC.json)
|
||||
* [`870e61cb994da5a84914ddecb729bbc4f37e432c27c48b763326eb673ea207ea ./artix7/site_type_GTPE2_CHANNEL.json`](./artix7/site_type_GTPE2_CHANNEL.json)
|
||||
* [`2d2ba2a7d336fef2f08b04f5aea599676fe002ad6f68736f66be1e7c5d4ab7a2 ./artix7/site_type_GTPE2_COMMON.json`](./artix7/site_type_GTPE2_COMMON.json)
|
||||
* [`ccfb41b477859def7583e7a32b8e2e65dd6356a7c3771761b8561625a7cb5591 ./artix7/site_type_IBUFDS_GTE2.json`](./artix7/site_type_IBUFDS_GTE2.json)
|
||||
* [`8cec0f1eb9788e3875fa13a951f12391234eb7d489c07bd138c64fa6cd006814 ./artix7/site_type_ICAP.json`](./artix7/site_type_ICAP.json)
|
||||
* [`b9075f486aa2a14c65b7f2714f1f5d0c94c1721ebd4ff29abcf21b979daab978 ./artix7/site_type_IDELAYCTRL.json`](./artix7/site_type_IDELAYCTRL.json)
|
||||
* [`045824ab1f5f70f41a2889303322e37d98f68be4b0a778b34f687e7473eb9193 ./artix7/site_type_IDELAYE2.json`](./artix7/site_type_IDELAYE2.json)
|
||||
* [`3a19f338249dba79b78d286d8270c87c58687bb72414a778b5a7e687cbb07555 ./artix7/site_type_ILOGICE3.json`](./artix7/site_type_ILOGICE3.json)
|
||||
* [`c38bda752c26d6bc96b7d0c932d32a985d95a612994b257d06497b3b8544c1b4 ./artix7/site_type_IN_FIFO.json`](./artix7/site_type_IN_FIFO.json)
|
||||
* [`6494bc80cf0758385e3ffafc1586e15faf8e8586f4bfcaac856ec4925c2a3fa5 ./artix7/site_type_IOB33.json`](./artix7/site_type_IOB33.json)
|
||||
* [`fa3a3c52d649446e2b10cebbaf965f008dfdbe3b2ff6ea5652fb2e3ab5ec2119 ./artix7/site_type_IOB33M.json`](./artix7/site_type_IOB33M.json)
|
||||
* [`5a779859f0ac32fd0b1e67e592031e2a6817499c10d950fbceb67ec60981958e ./artix7/site_type_IOB33S.json`](./artix7/site_type_IOB33S.json)
|
||||
* [`57f36c456bb9936328761cba5d98ac11aef35480951e4bbd01ebff87f281da35 ./artix7/site_type_IPAD.json`](./artix7/site_type_IPAD.json)
|
||||
* [`6ca708c74131a6cc465ad7140101e1b53673dda44b9e9b05427e5ee043d812e0 ./artix7/site_type_MMCME2_ADV.json`](./artix7/site_type_MMCME2_ADV.json)
|
||||
* [`e2635cc5529a1718ebebaeadc83d75767d6837d9a21def7ff1865369834a3bae ./artix7/site_type_OLOGICE3.json`](./artix7/site_type_OLOGICE3.json)
|
||||
* [`9f63a604386b226e8b4a28dd5e30bbe7c31da95775c2a8099ffe4c42dd7cc4cd ./artix7/site_type_OPAD.json`](./artix7/site_type_OPAD.json)
|
||||
* [`483078ba9991cd9f8f69350fe3568f26898eab3a4685ef330558dc59b77ad32e ./artix7/site_type_OUT_FIFO.json`](./artix7/site_type_OUT_FIFO.json)
|
||||
* [`868ff8634196b4ff0821b60a92f22b9d706962b6a956dc0da95610cae414b16a ./artix7/site_type_PCIE_2_1.json`](./artix7/site_type_PCIE_2_1.json)
|
||||
* [`07a29aede8c9f0d1e7c3c50cae199a7fd395091b563cd2369550455dd66828fc ./artix7/site_type_PHASER_IN_PHY.json`](./artix7/site_type_PHASER_IN_PHY.json)
|
||||
* [`2c7d3e7499eb21294df24c71109b9e58163248de7b232b6fab1f528cbec0ddcf ./artix7/site_type_PHASER_OUT_PHY.json`](./artix7/site_type_PHASER_OUT_PHY.json)
|
||||
* [`ee33d28bc9369ef379c2729fb1c7a24a47970a2d076c7c041c8ecb5738924fd7 ./artix7/site_type_PHASER_REF.json`](./artix7/site_type_PHASER_REF.json)
|
||||
* [`d6b9ed9f4910dd7461c38dfeb87ca706eaf1253bd15ded1df8f820919ddb4ea1 ./artix7/site_type_PHY_CONTROL.json`](./artix7/site_type_PHY_CONTROL.json)
|
||||
* [`29472966a4f054633c77544609f47018a6753e7c5212006c83c0d7db80145489 ./artix7/site_type_PLLE2_ADV.json`](./artix7/site_type_PLLE2_ADV.json)
|
||||
* [`dde67b650f00ad996f86aae5828f5fdab981c28e28f8c2353fdfcceafbcab591 ./artix7/site_type_PMV2.json`](./artix7/site_type_PMV2.json)
|
||||
* [`c552b72eaaaca5aa774fbf7b9929290a7395eab514477ba38b5a180965e7831b ./artix7/site_type_RAMB18E1.json`](./artix7/site_type_RAMB18E1.json)
|
||||
* [`66051f9ee1ab46b59987a37a42cf3442da3cef15fa5533f006117caff47486d6 ./artix7/site_type_RAMBFIFO36E1.json`](./artix7/site_type_RAMBFIFO36E1.json)
|
||||
* [`2b5d948347739c21fdb4fad7dbb1b5a4637182e6852e548edf8ff6ba63322a9a ./artix7/site_type_SLICEL.json`](./artix7/site_type_SLICEL.json)
|
||||
* [`2c85b664ba4c6d5f0b39df0ac4507feefa2137e56c24adb03b8f455955dcc2db ./artix7/site_type_SLICEM.json`](./artix7/site_type_SLICEM.json)
|
||||
* [`8a3bf7142d6a657e5d434ff066ff35a9267c47416474867565fd1abc0845c5b2 ./artix7/site_type_STARTUP.json`](./artix7/site_type_STARTUP.json)
|
||||
* [`8e5baf846e629316cefb781c26c09b6a39ca509d03dd381967c3e92f429dbda3 ./artix7/site_type_TIEOFF.json`](./artix7/site_type_TIEOFF.json)
|
||||
* [`a8bbff4d452d9a984b6b86eadabb083ec48ada24359e00c9eb99b8e8b6cb8a20 ./artix7/site_type_USR_ACCESS.json`](./artix7/site_type_USR_ACCESS.json)
|
||||
* [`ad77b4609302b54b2f371cc0f50262a507a19521c6dd86391acf3c7e5f20d887 ./artix7/site_type_XADC.json`](./artix7/site_type_XADC.json)
|
||||
* [`cece037771908d5d6b065651f94ed799dd028504365044431ae5ea88ffd44234 ./artix7/tileconn.json`](./artix7/tileconn.json)
|
||||
* [`ce74444d4f416951cb1aaff3a6197624ae94ab961ef5960c718752d70f775500 ./artix7/tilegrid.json`](./artix7/tilegrid.json)
|
||||
* [`56db412abc3d12c12bee1cfe4c5aaac0ea9e3668be3a9e058e86673272a6cd69 ./artix7/tile_type_BRAM_INT_INTERFACE_L.json`](./artix7/tile_type_BRAM_INT_INTERFACE_L.json)
|
||||
* [`5fde8c4861cb1dd36ec4a39aa3b4dc10df5401e17bed982a09c6a7577b0ff01d ./artix7/tile_type_BRAM_INT_INTERFACE_R.json`](./artix7/tile_type_BRAM_INT_INTERFACE_R.json)
|
||||
* [`3374015c97e4a10e64a853d0fecdd44588859115f76423ede1588232591cb343 ./artix7/tile_type_BRAM_L.json`](./artix7/tile_type_BRAM_L.json)
|
||||
* [`0e48e69982688b07098a1fac5167024f02e6ed3afae55377b5ede8f6a16f146d ./artix7/tile_type_BRAM_R.json`](./artix7/tile_type_BRAM_R.json)
|
||||
* [`d90e2b9eebb7221e94297a13a987100bdbd070bad88a70f9d758a6d1a5036133 ./artix7/tile_type_BRKH_BRAM.json`](./artix7/tile_type_BRKH_BRAM.json)
|
||||
* [`1ca1d22fbf2ab0ce39ea4da8e2c8d6833418f5f4d7ec02e62dbdcad671c2479c ./artix7/tile_type_BRKH_B_TERM_INT.json`](./artix7/tile_type_BRKH_B_TERM_INT.json)
|
||||
* [`b23ca51a084ef98835710b9c1c0deae6b78deacbc8c6a8f1c02b0d61db93d02d ./artix7/tile_type_BRKH_CLB.json`](./artix7/tile_type_BRKH_CLB.json)
|
||||
* [`61823ee1e9156a284970ef49d1b4ebbeb4afd57aad594b4f5f37db5ee0659370 ./artix7/tile_type_BRKH_CLK.json`](./artix7/tile_type_BRKH_CLK.json)
|
||||
* [`9f636390fc90eccc4f98ad1ef1ff526b85d40bb052024b7d5f90ca09cb7e17f9 ./artix7/tile_type_BRKH_CMT.json`](./artix7/tile_type_BRKH_CMT.json)
|
||||
* [`0629a079029b418b01308d21bfc6309ffcf8476bf57328a8c5b3cc9623bb8406 ./artix7/tile_type_BRKH_DSP_L.json`](./artix7/tile_type_BRKH_DSP_L.json)
|
||||
* [`e7d63108a6369354166d3bbdf134b0ef5ca9e7f443e9a0fe514fa7ff602a0388 ./artix7/tile_type_BRKH_DSP_R.json`](./artix7/tile_type_BRKH_DSP_R.json)
|
||||
* [`e6013cdb3a761a93bcb7520182721200220052aa68d794c706200192aa4bb7ec ./artix7/tile_type_BRKH_GTX.json`](./artix7/tile_type_BRKH_GTX.json)
|
||||
* [`3d51f166ab08934045829433645f61766439fe712bfeb9cf272b164a994b75dc ./artix7/tile_type_BRKH_INT.json`](./artix7/tile_type_BRKH_INT.json)
|
||||
* [`f5a7617297ccd63e39841118f8ebc260410daa7cfe998a74969d3d44595fcaa4 ./artix7/tile_type_BRKH_TERM_INT.json`](./artix7/tile_type_BRKH_TERM_INT.json)
|
||||
* [`c991fd82f6e918d5f687fe1099dffa7b951fc3b7761eb782fcd3bcb4a8a4ff66 ./artix7/tile_type_B_TERM_INT.json`](./artix7/tile_type_B_TERM_INT.json)
|
||||
* [`6f7fc06f6c36cffbad9b57a2c315c2fc0f557d65d8bf47999e7f29ac7da7330b ./artix7/tile_type_CFG_CENTER_BOT.json`](./artix7/tile_type_CFG_CENTER_BOT.json)
|
||||
* [`d3a4e5424572b0ad0814a902f7f66323a7dfc32f3055d57e854bbf70fa330b8e ./artix7/tile_type_CFG_CENTER_MID.json`](./artix7/tile_type_CFG_CENTER_MID.json)
|
||||
* [`d3455134d42c1421ff6ef4c964b05388d2eb54b41b6d45373827d61aede50d44 ./artix7/tile_type_CFG_CENTER_TOP.json`](./artix7/tile_type_CFG_CENTER_TOP.json)
|
||||
* [`a203272826ea9f1eeb3e6056e9d2e3e0cb99fe713c2ad8be18d3f7f4c1b11ade ./artix7/tile_type_CLBLL_L.json`](./artix7/tile_type_CLBLL_L.json)
|
||||
* [`44eeaa2e4604c23dd197edb3ca87ef397b2b1ccfea09d3b81bda3aeb84bd0e29 ./artix7/tile_type_CLBLL_R.json`](./artix7/tile_type_CLBLL_R.json)
|
||||
* [`e0281b9beb15fb0f7f8f1adacf6f522b1ad3185fd4231eff3d6c9cbb09520af8 ./artix7/tile_type_CLBLM_L.json`](./artix7/tile_type_CLBLM_L.json)
|
||||
* [`4ff52e67caee84d274b09104c35839d72d3da64382844e241e47e522420efe32 ./artix7/tile_type_CLBLM_R.json`](./artix7/tile_type_CLBLM_R.json)
|
||||
* [`f96926eab4db048265f7705066f4dc10123216696493a20d04dc37421287fc24 ./artix7/tile_type_CLK_BUFG_BOT_R.json`](./artix7/tile_type_CLK_BUFG_BOT_R.json)
|
||||
* [`3619d7654fd3b2c3683e665b07ebfe3bf186c73243e4786a4f813c65e96a2953 ./artix7/tile_type_CLK_BUFG_REBUF.json`](./artix7/tile_type_CLK_BUFG_REBUF.json)
|
||||
* [`e55843644057f2bac2de32800d13a6678adfc7ace6f3f87bc7d9308a890ab4cf ./artix7/tile_type_CLK_BUFG_TOP_R.json`](./artix7/tile_type_CLK_BUFG_TOP_R.json)
|
||||
* [`330e832ab39944e545dc4368d740d7008eb206ae174a314d428b2a69759c734a ./artix7/tile_type_CLK_FEED.json`](./artix7/tile_type_CLK_FEED.json)
|
||||
* [`a4e3af127e5b84f02331bf0902f9c8b476e07eb66d0f654737cc2c7a31eb7124 ./artix7/tile_type_CLK_HROW_BOT_R.json`](./artix7/tile_type_CLK_HROW_BOT_R.json)
|
||||
* [`df19db73d751056f630aad7200696d075ca374da013ec2e65c21cc5b22aaf3a8 ./artix7/tile_type_CLK_HROW_TOP_R.json`](./artix7/tile_type_CLK_HROW_TOP_R.json)
|
||||
* [`e301aed166fe1b17371b11f8c09be6b4ca67a29215ab4765a2b2b73a090f3faa ./artix7/tile_type_CLK_MTBF2.json`](./artix7/tile_type_CLK_MTBF2.json)
|
||||
* [`0267636db7d2bc3bc61aaf4d72ca49057ad61d3a66d847bd8485bc1e19856dc3 ./artix7/tile_type_CLK_PMV2.json`](./artix7/tile_type_CLK_PMV2.json)
|
||||
* [`dde992fee973fc9234219c412cc885cd56b00a4ec9da11495fd0b336bd354081 ./artix7/tile_type_CLK_PMV2_SVT.json`](./artix7/tile_type_CLK_PMV2_SVT.json)
|
||||
* [`930097848128274de976b51a22e25b82b6d9cd6201e234ffd125cc5c00978a23 ./artix7/tile_type_CLK_PMVIOB.json`](./artix7/tile_type_CLK_PMVIOB.json)
|
||||
* [`0747fc22ad9c6a769108d363b083c866bbe41089845c4b2f0de78fb9fc6970ff ./artix7/tile_type_CLK_PMV.json`](./artix7/tile_type_CLK_PMV.json)
|
||||
* [`cb231767fed449d9a3fca540404c46b81afdcd1ebfdf078966ba164e51c249bd ./artix7/tile_type_CLK_TERM.json`](./artix7/tile_type_CLK_TERM.json)
|
||||
* [`366f32ea0b98ac3fac3b4562669757c044ddc9c6128af3c01106959b0a4c19b0 ./artix7/tile_type_CMT_FIFO_L.json`](./artix7/tile_type_CMT_FIFO_L.json)
|
||||
* [`76e2d0f5ab4525eb473ec74fe375ed677b9f24a74c9d9b1e45cf9219a2b75820 ./artix7/tile_type_CMT_FIFO_R.json`](./artix7/tile_type_CMT_FIFO_R.json)
|
||||
* [`925d42b6185298b570a4746ac1f2ef996c0524b7500075275ef42650580dcb77 ./artix7/tile_type_CMT_PMV.json`](./artix7/tile_type_CMT_PMV.json)
|
||||
* [`7bcf64a7ea3a66da50aae5e789a31389358ab44c8ddf2e128ca66c2520d75438 ./artix7/tile_type_CMT_PMV_L.json`](./artix7/tile_type_CMT_PMV_L.json)
|
||||
* [`17c0cc33e5650d528c4fcb70efcc5354976e3b911b2f2e647c9b835b06ad2d34 ./artix7/tile_type_CMT_TOP_L_LOWER_B.json`](./artix7/tile_type_CMT_TOP_L_LOWER_B.json)
|
||||
* [`5f8bbb7ab0e5059b5dfca1a8b9ec54577c2d74d3c4b62a287424587e3b2f54e7 ./artix7/tile_type_CMT_TOP_L_LOWER_T.json`](./artix7/tile_type_CMT_TOP_L_LOWER_T.json)
|
||||
* [`5c0cc2c6aa116b31c21617da63cdd08fa7cad9fb5d32c199d7fe87b37430674d ./artix7/tile_type_CMT_TOP_L_UPPER_B.json`](./artix7/tile_type_CMT_TOP_L_UPPER_B.json)
|
||||
* [`66ef32256a5ed5eabf808e45f41300c829e5906a37b6820c41efc61dcef6f823 ./artix7/tile_type_CMT_TOP_L_UPPER_T.json`](./artix7/tile_type_CMT_TOP_L_UPPER_T.json)
|
||||
* [`006c0f3ae43a0601f78e12599ecf1f057df5e48b253432b1d56f1457d204ceae ./artix7/tile_type_CMT_TOP_R_LOWER_B.json`](./artix7/tile_type_CMT_TOP_R_LOWER_B.json)
|
||||
* [`94cbbc28123830f1c3402e03974f1a941a18c06259aa0c666ce9341777c78f4e ./artix7/tile_type_CMT_TOP_R_LOWER_T.json`](./artix7/tile_type_CMT_TOP_R_LOWER_T.json)
|
||||
* [`fcba6389824828c4ba0e51b1794a0350ed01043c57536d332d00ee2167e0ea95 ./artix7/tile_type_CMT_TOP_R_UPPER_B.json`](./artix7/tile_type_CMT_TOP_R_UPPER_B.json)
|
||||
* [`7d59357d3b6e1ffef42781449f4a273c906d13ccdc37c6260ab6df86a2c01b6e ./artix7/tile_type_CMT_TOP_R_UPPER_T.json`](./artix7/tile_type_CMT_TOP_R_UPPER_T.json)
|
||||
* [`48e9fb2ac16461732deca6c7f8fa4e7700ca6c1387b778edcd1a2e7a70ddea7a ./artix7/tile_type_DSP_L.json`](./artix7/tile_type_DSP_L.json)
|
||||
* [`093148b3a94a6c10913d3ffd62e68fc1e1a86d157c55f6142298ddebcefaf1fc ./artix7/tile_type_DSP_R.json`](./artix7/tile_type_DSP_R.json)
|
||||
* [`56c016d56fd36bbc8bb2f849b9002c798c705c5f34c999d3480b483571a7bf7a ./artix7/tile_type_GTP_CHANNEL_0.json`](./artix7/tile_type_GTP_CHANNEL_0.json)
|
||||
* [`6ec66aeb66441ad3f6428ae244751f145e9993528a018d601d4527c5ee3e3f96 ./artix7/tile_type_GTP_CHANNEL_1.json`](./artix7/tile_type_GTP_CHANNEL_1.json)
|
||||
* [`ed3c6a6af10c0d48982a047f3f7ac74fe3fbc174ace3af880a589fba45dd42ed ./artix7/tile_type_GTP_CHANNEL_2.json`](./artix7/tile_type_GTP_CHANNEL_2.json)
|
||||
* [`7a7ed978605314dcacaabaeaf9d31bc91a537e17484a294b0ae59a2ac7c1e734 ./artix7/tile_type_GTP_CHANNEL_3.json`](./artix7/tile_type_GTP_CHANNEL_3.json)
|
||||
* [`8eb3b5942619031579a02a02e285a0455be63c5730b366cbc8988cc2b9cb3a47 ./artix7/tile_type_GTP_COMMON.json`](./artix7/tile_type_GTP_COMMON.json)
|
||||
* [`706d3462d4fe1c9c4421df976136e934d54d71f2c4ee53f87b699c4c0924d4db ./artix7/tile_type_GTP_INT_INTERFACE.json`](./artix7/tile_type_GTP_INT_INTERFACE.json)
|
||||
* [`6e04d570c84732729e7020c86d69154abad88e9fea01c204d29c0ad34af56d9e ./artix7/tile_type_HCLK_BRAM.json`](./artix7/tile_type_HCLK_BRAM.json)
|
||||
* [`db4869b63b9c903c55aaa7dbce47052c1c39042c7184c3f88b85cef5677a4e68 ./artix7/tile_type_HCLK_CLB.json`](./artix7/tile_type_HCLK_CLB.json)
|
||||
* [`5605e47e54ced33c70c9a4a5d6ad7ea6bd2a4621bcc29a2bc98f84cbb5318729 ./artix7/tile_type_HCLK_CMT.json`](./artix7/tile_type_HCLK_CMT.json)
|
||||
* [`ea5aef6b3a0f6237bdce2d22c01961f1868f2a4ec17bc57967c59ebd8c98e781 ./artix7/tile_type_HCLK_CMT_L.json`](./artix7/tile_type_HCLK_CMT_L.json)
|
||||
* [`cad72613fa22fd079d8359b70e361dfee47a39fecddd21bd4ca6261440e6c7f2 ./artix7/tile_type_HCLK_DSP_L.json`](./artix7/tile_type_HCLK_DSP_L.json)
|
||||
* [`c94881752dbd2d1cee70510d5a9776e45eb1b9bc98299bae7556dd94d84ac9ee ./artix7/tile_type_HCLK_DSP_R.json`](./artix7/tile_type_HCLK_DSP_R.json)
|
||||
* [`e97bf2f0562ec9f3c9bd28d31bad32a131fbb13440096c9a1106a42d7c30a8a2 ./artix7/tile_type_HCLK_FEEDTHRU_1.json`](./artix7/tile_type_HCLK_FEEDTHRU_1.json)
|
||||
* [`1224c1e07a74106abfe790911cad14631d2d7b9e071551ae87ce22e94586a254 ./artix7/tile_type_HCLK_FEEDTHRU_2.json`](./artix7/tile_type_HCLK_FEEDTHRU_2.json)
|
||||
* [`9153c00fb532285a3f5908aac04444f66f556be6510b14ead6a4e00090235723 ./artix7/tile_type_HCLK_FIFO_L.json`](./artix7/tile_type_HCLK_FIFO_L.json)
|
||||
* [`0b238152eba5a5bce46a5cf14fe175d87d7394fcb1772d8cb1690b0ebadc66e4 ./artix7/tile_type_HCLK_GTX.json`](./artix7/tile_type_HCLK_GTX.json)
|
||||
* [`addd808e24003e2f2b51003726d6395d07eed6e77bfcc3c1a3cfa02df67f608d ./artix7/tile_type_HCLK_INT_INTERFACE.json`](./artix7/tile_type_HCLK_INT_INTERFACE.json)
|
||||
* [`e62be537ade1cf2be5768604f1567f7be8296c7eeb6dbce01def983d471958df ./artix7/tile_type_HCLK_IOB.json`](./artix7/tile_type_HCLK_IOB.json)
|
||||
* [`6d725f338f9ead2b40d8e4377fec02d57daee72677f6ce7c8761128ce4f37742 ./artix7/tile_type_HCLK_IOI3.json`](./artix7/tile_type_HCLK_IOI3.json)
|
||||
* [`6efc0af3e02fcbd170b76ea081d748a6eba14c4fb4e766a42f4dee47b94d03c5 ./artix7/tile_type_HCLK_L_BOT_UTURN.json`](./artix7/tile_type_HCLK_L_BOT_UTURN.json)
|
||||
* [`aa4205dbd7787658bb57f66dd471c3b4bdcb0420123db01d9da7fe8c2b4782b0 ./artix7/tile_type_HCLK_L.json`](./artix7/tile_type_HCLK_L.json)
|
||||
* [`94fba32801db0f18d065791ff922b0a4dc11ee6c37a6485b1dbfeafc881ae026 ./artix7/tile_type_HCLK_R_BOT_UTURN.json`](./artix7/tile_type_HCLK_R_BOT_UTURN.json)
|
||||
* [`427b35722adcb30006e8ece93b5c4e463feefd74a130b0ca03db59bce8cc45fe ./artix7/tile_type_HCLK_R.json`](./artix7/tile_type_HCLK_R.json)
|
||||
* [`9ec44fc735677e9a8f5fa71f0bfe6e05bab6975f4d32d1fc6999b5fb34fe263e ./artix7/tile_type_HCLK_TERM_GTX.json`](./artix7/tile_type_HCLK_TERM_GTX.json)
|
||||
* [`d4af410c0b97ec9222abfddba4a91b1f23942431eb13cf37dcd8ed4a0c00f50a ./artix7/tile_type_HCLK_TERM.json`](./artix7/tile_type_HCLK_TERM.json)
|
||||
* [`a47ab1f6d74cc4b94e338db09d6a3267b6d650b473d5e021f4e73aa7375d89dc ./artix7/tile_type_HCLK_VBRK.json`](./artix7/tile_type_HCLK_VBRK.json)
|
||||
* [`7c110a1f341e637d750a585efadeabd92789fb15f9ec32d3efc187b884d357da ./artix7/tile_type_HCLK_VFRAME.json`](./artix7/tile_type_HCLK_VFRAME.json)
|
||||
* [`aa13f4ec5d440ccf5560a552c9cb1b69021dd6b4a096a72f09c769b79033ad7d ./artix7/tile_type_INT_FEEDTHRU_1.json`](./artix7/tile_type_INT_FEEDTHRU_1.json)
|
||||
* [`a00f2d8da58bafb44fa201f24861ba12205fe494d1d75301c8d21118f0ceaa92 ./artix7/tile_type_INT_FEEDTHRU_2.json`](./artix7/tile_type_INT_FEEDTHRU_2.json)
|
||||
* [`870df57fc52c7fd9b124a91870f9f27ba06368b1da9aab8ce7de6e67778f8c80 ./artix7/tile_type_INT_INTERFACE_L.json`](./artix7/tile_type_INT_INTERFACE_L.json)
|
||||
* [`2624e9b62c62d561bf82898fa9cac9dc627f54d51d09e93f034f21484ac5ea69 ./artix7/tile_type_INT_INTERFACE_R.json`](./artix7/tile_type_INT_INTERFACE_R.json)
|
||||
* [`64a43c04cf6d619fb84df28ca6fd4b943422f588bc11e5035a8f8214bd9fd109 ./artix7/tile_type_INT_L.json`](./artix7/tile_type_INT_L.json)
|
||||
* [`16e33e1cec76e45e2b143b706bc84e69954f7440245d23859659e7cdc62e628c ./artix7/tile_type_INT_R.json`](./artix7/tile_type_INT_R.json)
|
||||
* [`d9b299aea8d485728aae7c9eb157308b12f923baa0c73709801dcecbd30fe5df ./artix7/tile_type_IO_INT_INTERFACE_L.json`](./artix7/tile_type_IO_INT_INTERFACE_L.json)
|
||||
* [`08363c3524ca1c9efd46b575beac2450990a560a876128c1b1e029a86f8f6aed ./artix7/tile_type_IO_INT_INTERFACE_R.json`](./artix7/tile_type_IO_INT_INTERFACE_R.json)
|
||||
* [`9afc4fdd483ee7f6ed781220dd5e65d46fff7d0c408010b7e7ac24b39c6fa112 ./artix7/tile_type_LIOB33.json`](./artix7/tile_type_LIOB33.json)
|
||||
* [`47f49959e2cd589f023dc2a6c98f5f48ef9fa21fec9717280614ff8b9c72c347 ./artix7/tile_type_LIOB33_SING.json`](./artix7/tile_type_LIOB33_SING.json)
|
||||
* [`cc31c69ecb8245b52b0e62311e028dc2dccd658817a0e14ccce10f499e88c0e3 ./artix7/tile_type_LIOI3.json`](./artix7/tile_type_LIOI3.json)
|
||||
* [`7eca0d27597eba0cf91baff2bf2084d48a4efc0f39268eddcf066662de9ad6b9 ./artix7/tile_type_LIOI3_SING.json`](./artix7/tile_type_LIOI3_SING.json)
|
||||
* [`c48539f3910201f7069804cdbacb83d0721f6b95a68cfee2ec8d6035893409c4 ./artix7/tile_type_LIOI3_TBYTESRC.json`](./artix7/tile_type_LIOI3_TBYTESRC.json)
|
||||
* [`ecfab821b2dae9221e64343a6de46e812623ffbd99b117ff01a847e1caba81a9 ./artix7/tile_type_LIOI3_TBYTETERM.json`](./artix7/tile_type_LIOI3_TBYTETERM.json)
|
||||
* [`8451737d70e6dce0211b85e2343a1daa5fac47017a95f7b19f85ae3efa21cca3 ./artix7/tile_type_L_TERM_INT.json`](./artix7/tile_type_L_TERM_INT.json)
|
||||
* [`9e361342e80dac0278cc6acc0a6b52b1236aa74a04be3a2671556a867b7c92d3 ./artix7/tile_type_MONITOR_BOT.json`](./artix7/tile_type_MONITOR_BOT.json)
|
||||
* [`2b3850d81e0f4fbb6a9bf049de77b99b644c65fbef79fe51b04e4e7ec762d379 ./artix7/tile_type_MONITOR_MID.json`](./artix7/tile_type_MONITOR_MID.json)
|
||||
* [`e85d9d434b86fbf79062ea765d2565e2f9645c1f321653ff25fd3b1e0c6d303d ./artix7/tile_type_MONITOR_TOP.json`](./artix7/tile_type_MONITOR_TOP.json)
|
||||
* [`2ce6ba0efbc6fa49637a90e7c003140d6a5b5fac401c243a3e75505909a5bc7f ./artix7/tile_type_NULL.json`](./artix7/tile_type_NULL.json)
|
||||
* [`86335dda91660eafb7cb39f40706ab11f4113bb96fab2835ad6e3c210b25a5db ./artix7/tile_type_PCIE_BOT.json`](./artix7/tile_type_PCIE_BOT.json)
|
||||
* [`27848877c1f6de2425823155a1387d56a26802ff4400a68945eda10c6aa7f394 ./artix7/tile_type_PCIE_INT_INTERFACE_L.json`](./artix7/tile_type_PCIE_INT_INTERFACE_L.json)
|
||||
* [`d8353f3b93905313827c71114ce17c1ece756843487ff11a86cfd8488723b409 ./artix7/tile_type_PCIE_INT_INTERFACE_R.json`](./artix7/tile_type_PCIE_INT_INTERFACE_R.json)
|
||||
* [`d61def0be37737195c1490b8a0141d490b82be3813664c59ca876035492662fc ./artix7/tile_type_PCIE_NULL.json`](./artix7/tile_type_PCIE_NULL.json)
|
||||
* [`c0c1ea1ee074c261ae528f40af0889bf87d0f2d1b1dc8fa9d91b9f434dbe0ba0 ./artix7/tile_type_PCIE_TOP.json`](./artix7/tile_type_PCIE_TOP.json)
|
||||
* [`8e995e366365b71079600c13337e024426712aa8b9678c13e9da3d12d23b767f ./artix7/tile_type_RIOB33.json`](./artix7/tile_type_RIOB33.json)
|
||||
* [`8ac59745346f219d3f6e4ee9b93083953e895e1ad571bef583a3ad809971c19f ./artix7/tile_type_RIOB33_SING.json`](./artix7/tile_type_RIOB33_SING.json)
|
||||
* [`423861b9d981b7190a5b572cfc3c5625b225f0ccdab2902d2ecce8288ce1bf8c ./artix7/tile_type_RIOI3.json`](./artix7/tile_type_RIOI3.json)
|
||||
* [`bab573b5cb97e3023c66354e35d21ce8cbbe5f354f6a78ef666e0cbb1b4904a9 ./artix7/tile_type_RIOI3_SING.json`](./artix7/tile_type_RIOI3_SING.json)
|
||||
* [`b748c1e71731f0c80bb73b8dd1600a6c70a3ca549c77bde0043cba922e945578 ./artix7/tile_type_RIOI3_TBYTESRC.json`](./artix7/tile_type_RIOI3_TBYTESRC.json)
|
||||
* [`86cf1f5de171b322f0ef68187b091f4a70f903893dcaaaa0a1f3fc13305ad0ee ./artix7/tile_type_RIOI3_TBYTETERM.json`](./artix7/tile_type_RIOI3_TBYTETERM.json)
|
||||
* [`0a786cf51d4102ca179cbde5121024f9a565cac9e0cf7cdf6a2f934dae431ed2 ./artix7/tile_type_R_TERM_INT_GTX.json`](./artix7/tile_type_R_TERM_INT_GTX.json)
|
||||
* [`1e2b6e49f515d4ba18d6384e5824ce447e49416788380caf767335d7d5207b0f ./artix7/tile_type_R_TERM_INT.json`](./artix7/tile_type_R_TERM_INT.json)
|
||||
* [`0b54b5d401ce831f2e39513c933bcd07cad9af7b29e26fb5b5fd8c2fbffa1490 ./artix7/tile_type_TERM_CMT.json`](./artix7/tile_type_TERM_CMT.json)
|
||||
* [`10a3d1ddfae1aef0790f09c8a075d3ee655b64bfd72db454dd0f7a5fdf5c9595 ./artix7/tile_type_T_TERM_INT.json`](./artix7/tile_type_T_TERM_INT.json)
|
||||
* [`27033dfca5462da31e805a4d29e54d69ceb5de3487a364e40630073fcefbb408 ./artix7/tile_type_VBRK_EXT.json`](./artix7/tile_type_VBRK_EXT.json)
|
||||
* [`5e7547acab0a27e3e47521b350da09e6a82d8c1a1e4259996d63a60f768f2f63 ./artix7/tile_type_VBRK.json`](./artix7/tile_type_VBRK.json)
|
||||
* [`d41f88c544effafefbf13060f1710a622d282fd24214b36bbe0164a3a17b3399 ./artix7/tile_type_VFRAME.json`](./artix7/tile_type_VFRAME.json)
|
||||
* [`ef0724733da87455426a0f833642d96e9d206d047f4eb97072c3093f80c40d7d ./artix7/xc7a35tcpg236-1.yaml`](./artix7/xc7a35tcpg236-1.yaml)
|
||||
* [`ef0724733da87455426a0f833642d96e9d206d047f4eb97072c3093f80c40d7d ./artix7/xc7a35tcsg324-1.yaml`](./artix7/xc7a35tcsg324-1.yaml)
|
||||
* [`41c360b1e2f7e08b9051f1160a34954ce4c05a445a07f226f1f4059caf1fa1d3 ./artix7/xc7a50tfgg484-1.yaml`](./artix7/xc7a50tfgg484-1.yaml)
|
||||
|
|
@ -294,16 +300,21 @@ Results have checksums;
|
|||
|
||||
### Settings
|
||||
|
||||
Created using following [settings.sh (sha256: 2daf6a69dd6d20df7b1273ff43c5c340abe36f8229d297646865edcfd91eff18)](https://github.com/SymbiFlow/prjxray/blob/a0cfca860872a99ac81b223ee1e5e9ae567b9590/database/kintex7/settings.sh)
|
||||
Created using following [settings.sh (sha256: 555d484e8c10c35897ac446eb7a1bbebf0606c56dcd19caa9c8d916bb77cad64)](https://github.com/SymbiFlow/prjxray/blob/b43bf3539f51ed8a755ae245682cd660ca23d813/database/kintex7/settings.sh)
|
||||
```shell
|
||||
export XRAY_DATABASE="kintex7"
|
||||
export XRAY_PART="xc7k70tfbg676-2"
|
||||
export XRAY_ROI_FRAMES="0x00000000:0xffffffff"
|
||||
|
||||
export XRAY_ROI="SLICE_X0Y50:SLICE_X19Y99 DSP48_X0Y20:DSP48_X0Y39 RAMB18_X0Y20:RAMB18_X0Y39 RAMB36_X0Y10:RAMB36_X0Y19"
|
||||
export XRAY_ROI_FRAMES="0x00400100:0x004006ff"
|
||||
|
||||
# Part of CMT X0Y1
|
||||
export XRAY_ROI_GRID_X1="9"
|
||||
export XRAY_ROI_GRID_X2="38"
|
||||
# Include VBRK / VTERM
|
||||
export XRAY_ROI_GRID_Y1="104"
|
||||
export XRAY_ROI_GRID_Y2="156"
|
||||
|
||||
# Choose the first N High Range I/Os
|
||||
export XRAY_PIN_00="K25"
|
||||
export XRAY_PIN_01="K26"
|
||||
|
|
@ -350,7 +361,7 @@ Results have checksums;
|
|||
* [`e7f5d16940fde9397f69d5f52c2a6339641191dc9dba4466e8b7f9e5f6a735bf ./kintex7/segbits_clblm_r.db`](./kintex7/segbits_clblm_r.db)
|
||||
* [`9ed8769618df03902c73e78312467108c7b74b903ac61d1bbbba1fd9710e6d3b ./kintex7/segbits_int_l.db`](./kintex7/segbits_int_l.db)
|
||||
* [`dbf6cba5bbba95d7d78d9b51d236d8819dc776c2ebc540521e5b48d3a2c1390f ./kintex7/segbits_int_r.db`](./kintex7/segbits_int_r.db)
|
||||
* [`2daf6a69dd6d20df7b1273ff43c5c340abe36f8229d297646865edcfd91eff18 ./kintex7/settings.sh`](./kintex7/settings.sh)
|
||||
* [`8f5b7a7924adec5132208cf8e851e81bcb01a5c61f8839eb5a5de0b20b924510 ./kintex7/tilegrid.json`](./kintex7/tilegrid.json)
|
||||
* [`555d484e8c10c35897ac446eb7a1bbebf0606c56dcd19caa9c8d916bb77cad64 ./kintex7/settings.sh`](./kintex7/settings.sh)
|
||||
* [`a895427419c90ce0e5189c1e8872e4c79b26be82863e11e0022693188236ca05 ./kintex7/tilegrid.json`](./kintex7/tilegrid.json)
|
||||
* [`68426295ab4a35e367c9dff93e4f9b807afd43fe83418cb2da7465cd4d7177a2 ./kintex7/xc7k70tfbg676-2.yaml`](./kintex7/xc7k70tfbg676-2.yaml)
|
||||
|
||||
|
|
|
|||
|
|
@ -1,112 +1,112 @@
|
|||
{
|
||||
"info": {
|
||||
"GRID_X_MAX": 47,
|
||||
"GRID_X_MIN": 18,
|
||||
"GRID_Y_MAX": 52,
|
||||
"GRID_Y_MIN": 0
|
||||
},
|
||||
"ports": [
|
||||
{
|
||||
"name": "clk",
|
||||
"node": "CLK_HROW_TOP_R_X60Y130/CLK_HROW_CK_BUFHCLK_L0",
|
||||
"pin": "G13",
|
||||
"wire": "HCLK_VBRK_X34Y130/HCLK_VBRK_CK_BUFHCLK0"
|
||||
"info": {
|
||||
"GRID_X_MAX": 47,
|
||||
"GRID_X_MIN": 18,
|
||||
"GRID_Y_MAX": 52,
|
||||
"GRID_Y_MIN": 0
|
||||
},
|
||||
{
|
||||
"name": "din[0]",
|
||||
"node": "INT_R_X9Y102/NE2BEG3",
|
||||
"pin": "E15",
|
||||
"wire": "VBRK_X29Y108/VBRK_NE2A3"
|
||||
},
|
||||
{
|
||||
"name": "din[1]",
|
||||
"node": "INT_R_X9Y105/NE2BEG3",
|
||||
"pin": "E16",
|
||||
"wire": "VBRK_X29Y111/VBRK_NE2A3"
|
||||
},
|
||||
{
|
||||
"name": "din[2]",
|
||||
"node": "INT_R_X9Y108/NE2BEG3",
|
||||
"pin": "D15",
|
||||
"wire": "VBRK_X29Y114/VBRK_NE2A3"
|
||||
},
|
||||
{
|
||||
"name": "din[3]",
|
||||
"node": "INT_R_X9Y111/NE2BEG3",
|
||||
"pin": "C15",
|
||||
"wire": "VBRK_X29Y117/VBRK_NE2A3"
|
||||
},
|
||||
{
|
||||
"name": "din[4]",
|
||||
"node": "INT_R_X9Y114/NE2BEG3",
|
||||
"pin": "J17",
|
||||
"wire": "VBRK_X29Y120/VBRK_NE2A3"
|
||||
},
|
||||
{
|
||||
"name": "din[5]",
|
||||
"node": "INT_R_X9Y117/NE2BEG3",
|
||||
"pin": "J18",
|
||||
"wire": "VBRK_X29Y123/VBRK_NE2A3"
|
||||
},
|
||||
{
|
||||
"name": "din[6]",
|
||||
"node": "INT_R_X9Y120/NE2BEG3",
|
||||
"pin": "K15",
|
||||
"wire": "VBRK_X29Y126/VBRK_NE2A3"
|
||||
},
|
||||
{
|
||||
"name": "din[7]",
|
||||
"node": "INT_R_X9Y123/NE2BEG3",
|
||||
"pin": "J15",
|
||||
"wire": "VBRK_X29Y129/VBRK_NE2A3"
|
||||
},
|
||||
{
|
||||
"name": "dout[0]",
|
||||
"node": "INT_L_X10Y125/SW6BEG0",
|
||||
"pin": "U12",
|
||||
"wire": "VBRK_X29Y131/VBRK_SW4A0"
|
||||
},
|
||||
{
|
||||
"name": "dout[1]",
|
||||
"node": "INT_L_X10Y128/SW6BEG0",
|
||||
"pin": "V12",
|
||||
"wire": "VBRK_X29Y134/VBRK_SW4A0"
|
||||
},
|
||||
{
|
||||
"name": "dout[2]",
|
||||
"node": "INT_L_X10Y131/SW6BEG0",
|
||||
"pin": "V10",
|
||||
"wire": "VBRK_X29Y137/VBRK_SW4A0"
|
||||
},
|
||||
{
|
||||
"name": "dout[3]",
|
||||
"node": "INT_L_X10Y134/SW6BEG0",
|
||||
"pin": "V11",
|
||||
"wire": "VBRK_X29Y140/VBRK_SW4A0"
|
||||
},
|
||||
{
|
||||
"name": "dout[4]",
|
||||
"node": "INT_L_X10Y137/SW6BEG0",
|
||||
"pin": "U14",
|
||||
"wire": "VBRK_X29Y143/VBRK_SW4A0"
|
||||
},
|
||||
{
|
||||
"name": "dout[5]",
|
||||
"node": "INT_L_X10Y140/SW6BEG0",
|
||||
"pin": "V14",
|
||||
"wire": "VBRK_X29Y146/VBRK_SW4A0"
|
||||
},
|
||||
{
|
||||
"name": "dout[6]",
|
||||
"node": "INT_L_X10Y143/SW6BEG0",
|
||||
"pin": "T13",
|
||||
"wire": "VBRK_X29Y149/VBRK_SW4A0"
|
||||
},
|
||||
{
|
||||
"name": "dout[7]",
|
||||
"node": "INT_L_X10Y146/SW6BEG0",
|
||||
"pin": "U13",
|
||||
"wire": "VBRK_X29Y152/VBRK_SW4A0"
|
||||
}
|
||||
]
|
||||
}
|
||||
"ports": [
|
||||
{
|
||||
"name": "clk",
|
||||
"node": "CLK_HROW_TOP_R_X60Y130/CLK_HROW_CK_BUFHCLK_L0",
|
||||
"pin": "G13",
|
||||
"wire": "HCLK_VBRK_X34Y130/HCLK_VBRK_CK_BUFHCLK0"
|
||||
},
|
||||
{
|
||||
"name": "din[0]",
|
||||
"node": "INT_R_X9Y102/NE2BEG3",
|
||||
"pin": "E15",
|
||||
"wire": "VBRK_X29Y108/VBRK_NE2A3"
|
||||
},
|
||||
{
|
||||
"name": "din[1]",
|
||||
"node": "INT_R_X9Y105/NE2BEG3",
|
||||
"pin": "E16",
|
||||
"wire": "VBRK_X29Y111/VBRK_NE2A3"
|
||||
},
|
||||
{
|
||||
"name": "din[2]",
|
||||
"node": "INT_R_X9Y108/NE2BEG3",
|
||||
"pin": "D15",
|
||||
"wire": "VBRK_X29Y114/VBRK_NE2A3"
|
||||
},
|
||||
{
|
||||
"name": "din[3]",
|
||||
"node": "INT_R_X9Y111/NE2BEG3",
|
||||
"pin": "C15",
|
||||
"wire": "VBRK_X29Y117/VBRK_NE2A3"
|
||||
},
|
||||
{
|
||||
"name": "din[4]",
|
||||
"node": "INT_R_X9Y114/NE2BEG3",
|
||||
"pin": "J17",
|
||||
"wire": "VBRK_X29Y120/VBRK_NE2A3"
|
||||
},
|
||||
{
|
||||
"name": "din[5]",
|
||||
"node": "INT_R_X9Y117/NE2BEG3",
|
||||
"pin": "J18",
|
||||
"wire": "VBRK_X29Y123/VBRK_NE2A3"
|
||||
},
|
||||
{
|
||||
"name": "din[6]",
|
||||
"node": "INT_R_X9Y120/NE2BEG3",
|
||||
"pin": "K15",
|
||||
"wire": "VBRK_X29Y126/VBRK_NE2A3"
|
||||
},
|
||||
{
|
||||
"name": "din[7]",
|
||||
"node": "INT_R_X9Y123/NE2BEG3",
|
||||
"pin": "J15",
|
||||
"wire": "VBRK_X29Y129/VBRK_NE2A3"
|
||||
},
|
||||
{
|
||||
"name": "dout[0]",
|
||||
"node": "INT_L_X10Y125/SW6BEG0",
|
||||
"pin": "U12",
|
||||
"wire": "VBRK_X29Y131/VBRK_SW4A0"
|
||||
},
|
||||
{
|
||||
"name": "dout[1]",
|
||||
"node": "INT_L_X10Y128/SW6BEG0",
|
||||
"pin": "V12",
|
||||
"wire": "VBRK_X29Y134/VBRK_SW4A0"
|
||||
},
|
||||
{
|
||||
"name": "dout[2]",
|
||||
"node": "INT_L_X10Y131/SW6BEG0",
|
||||
"pin": "V10",
|
||||
"wire": "VBRK_X29Y137/VBRK_SW4A0"
|
||||
},
|
||||
{
|
||||
"name": "dout[3]",
|
||||
"node": "INT_L_X10Y134/SW6BEG0",
|
||||
"pin": "V11",
|
||||
"wire": "VBRK_X29Y140/VBRK_SW4A0"
|
||||
},
|
||||
{
|
||||
"name": "dout[4]",
|
||||
"node": "INT_L_X10Y137/SW6BEG0",
|
||||
"pin": "U14",
|
||||
"wire": "VBRK_X29Y143/VBRK_SW4A0"
|
||||
},
|
||||
{
|
||||
"name": "dout[5]",
|
||||
"node": "INT_L_X10Y140/SW6BEG0",
|
||||
"pin": "V14",
|
||||
"wire": "VBRK_X29Y146/VBRK_SW4A0"
|
||||
},
|
||||
{
|
||||
"name": "dout[6]",
|
||||
"node": "INT_L_X10Y143/SW6BEG0",
|
||||
"pin": "T13",
|
||||
"wire": "VBRK_X29Y149/VBRK_SW4A0"
|
||||
},
|
||||
{
|
||||
"name": "dout[7]",
|
||||
"node": "INT_L_X10Y146/SW6BEG0",
|
||||
"pin": "U13",
|
||||
"wire": "VBRK_X29Y152/VBRK_SW4A0"
|
||||
}
|
||||
]
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,112 +1,112 @@
|
|||
{
|
||||
"info": {
|
||||
"GRID_X_MAX": 47,
|
||||
"GRID_X_MIN": 18,
|
||||
"GRID_Y_MAX": 52,
|
||||
"GRID_Y_MIN": 0
|
||||
},
|
||||
"ports": [
|
||||
{
|
||||
"name": "clk",
|
||||
"node": "CLK_HROW_TOP_R_X60Y130/CLK_HROW_CK_BUFHCLK_L0",
|
||||
"pin": "E3",
|
||||
"wire": "HCLK_VBRK_X34Y130/HCLK_VBRK_CK_BUFHCLK0"
|
||||
"info": {
|
||||
"GRID_X_MAX": 47,
|
||||
"GRID_X_MIN": 18,
|
||||
"GRID_Y_MAX": 52,
|
||||
"GRID_Y_MIN": 0
|
||||
},
|
||||
{
|
||||
"name": "din[0]",
|
||||
"node": "INT_R_X9Y102/NE2BEG3",
|
||||
"pin": "A8",
|
||||
"wire": "VBRK_X29Y108/VBRK_NE2A3"
|
||||
},
|
||||
{
|
||||
"name": "din[1]",
|
||||
"node": "INT_R_X9Y105/NE2BEG3",
|
||||
"pin": "C11",
|
||||
"wire": "VBRK_X29Y111/VBRK_NE2A3"
|
||||
},
|
||||
{
|
||||
"name": "din[2]",
|
||||
"node": "INT_R_X9Y108/NE2BEG3",
|
||||
"pin": "C10",
|
||||
"wire": "VBRK_X29Y114/VBRK_NE2A3"
|
||||
},
|
||||
{
|
||||
"name": "din[3]",
|
||||
"node": "INT_R_X9Y111/NE2BEG3",
|
||||
"pin": "A10",
|
||||
"wire": "VBRK_X29Y117/VBRK_NE2A3"
|
||||
},
|
||||
{
|
||||
"name": "din[4]",
|
||||
"node": "INT_R_X9Y114/NE2BEG3",
|
||||
"pin": "D9",
|
||||
"wire": "VBRK_X29Y120/VBRK_NE2A3"
|
||||
},
|
||||
{
|
||||
"name": "din[5]",
|
||||
"node": "INT_R_X9Y117/NE2BEG3",
|
||||
"pin": "C9",
|
||||
"wire": "VBRK_X29Y123/VBRK_NE2A3"
|
||||
},
|
||||
{
|
||||
"name": "din[6]",
|
||||
"node": "INT_R_X9Y120/NE2BEG3",
|
||||
"pin": "B9",
|
||||
"wire": "VBRK_X29Y126/VBRK_NE2A3"
|
||||
},
|
||||
{
|
||||
"name": "din[7]",
|
||||
"node": "INT_R_X9Y123/NE2BEG3",
|
||||
"pin": "B8",
|
||||
"wire": "VBRK_X29Y129/VBRK_NE2A3"
|
||||
},
|
||||
{
|
||||
"name": "dout[0]",
|
||||
"node": "INT_R_X17Y125/SE6BEG0",
|
||||
"pin": "H5",
|
||||
"wire": ""
|
||||
},
|
||||
{
|
||||
"name": "dout[1]",
|
||||
"node": "INT_R_X17Y128/SE6BEG0",
|
||||
"pin": "J5",
|
||||
"wire": ""
|
||||
},
|
||||
{
|
||||
"name": "dout[2]",
|
||||
"node": "INT_L_X10Y131/SW6BEG0",
|
||||
"pin": "T9",
|
||||
"wire": "VBRK_X29Y137/VBRK_SW4A0"
|
||||
},
|
||||
{
|
||||
"name": "dout[3]",
|
||||
"node": "INT_L_X10Y134/SW6BEG0",
|
||||
"pin": "T10",
|
||||
"wire": "VBRK_X29Y140/VBRK_SW4A0"
|
||||
},
|
||||
{
|
||||
"name": "dout[4]",
|
||||
"node": "INT_R_X17Y137/SE6BEG0",
|
||||
"pin": "F6",
|
||||
"wire": ""
|
||||
},
|
||||
{
|
||||
"name": "dout[5]",
|
||||
"node": "INT_R_X17Y140/SE6BEG0",
|
||||
"pin": "J4",
|
||||
"wire": ""
|
||||
},
|
||||
{
|
||||
"name": "dout[6]",
|
||||
"node": "INT_R_X17Y143/SE6BEG0",
|
||||
"pin": "J2",
|
||||
"wire": ""
|
||||
},
|
||||
{
|
||||
"name": "dout[7]",
|
||||
"node": "INT_R_X17Y146/SE6BEG0",
|
||||
"pin": "H6",
|
||||
"wire": ""
|
||||
}
|
||||
]
|
||||
}
|
||||
"ports": [
|
||||
{
|
||||
"name": "clk",
|
||||
"node": "CLK_HROW_TOP_R_X60Y130/CLK_HROW_CK_BUFHCLK_L0",
|
||||
"pin": "E3",
|
||||
"wire": "HCLK_VBRK_X34Y130/HCLK_VBRK_CK_BUFHCLK0"
|
||||
},
|
||||
{
|
||||
"name": "din[0]",
|
||||
"node": "INT_R_X9Y102/NE2BEG3",
|
||||
"pin": "A8",
|
||||
"wire": "VBRK_X29Y108/VBRK_NE2A3"
|
||||
},
|
||||
{
|
||||
"name": "din[1]",
|
||||
"node": "INT_R_X9Y105/NE2BEG3",
|
||||
"pin": "C11",
|
||||
"wire": "VBRK_X29Y111/VBRK_NE2A3"
|
||||
},
|
||||
{
|
||||
"name": "din[2]",
|
||||
"node": "INT_R_X9Y108/NE2BEG3",
|
||||
"pin": "C10",
|
||||
"wire": "VBRK_X29Y114/VBRK_NE2A3"
|
||||
},
|
||||
{
|
||||
"name": "din[3]",
|
||||
"node": "INT_R_X9Y111/NE2BEG3",
|
||||
"pin": "A10",
|
||||
"wire": "VBRK_X29Y117/VBRK_NE2A3"
|
||||
},
|
||||
{
|
||||
"name": "din[4]",
|
||||
"node": "INT_R_X9Y114/NE2BEG3",
|
||||
"pin": "D9",
|
||||
"wire": "VBRK_X29Y120/VBRK_NE2A3"
|
||||
},
|
||||
{
|
||||
"name": "din[5]",
|
||||
"node": "INT_R_X9Y117/NE2BEG3",
|
||||
"pin": "C9",
|
||||
"wire": "VBRK_X29Y123/VBRK_NE2A3"
|
||||
},
|
||||
{
|
||||
"name": "din[6]",
|
||||
"node": "INT_R_X9Y120/NE2BEG3",
|
||||
"pin": "B9",
|
||||
"wire": "VBRK_X29Y126/VBRK_NE2A3"
|
||||
},
|
||||
{
|
||||
"name": "din[7]",
|
||||
"node": "INT_R_X9Y123/NE2BEG3",
|
||||
"pin": "B8",
|
||||
"wire": "VBRK_X29Y129/VBRK_NE2A3"
|
||||
},
|
||||
{
|
||||
"name": "dout[0]",
|
||||
"node": "INT_R_X17Y125/SE6BEG0",
|
||||
"pin": "H5",
|
||||
"wire": ""
|
||||
},
|
||||
{
|
||||
"name": "dout[1]",
|
||||
"node": "INT_R_X17Y128/SE6BEG0",
|
||||
"pin": "J5",
|
||||
"wire": ""
|
||||
},
|
||||
{
|
||||
"name": "dout[2]",
|
||||
"node": "INT_L_X10Y131/SW6BEG0",
|
||||
"pin": "T9",
|
||||
"wire": "VBRK_X29Y137/VBRK_SW4A0"
|
||||
},
|
||||
{
|
||||
"name": "dout[3]",
|
||||
"node": "INT_L_X10Y134/SW6BEG0",
|
||||
"pin": "T10",
|
||||
"wire": "VBRK_X29Y140/VBRK_SW4A0"
|
||||
},
|
||||
{
|
||||
"name": "dout[4]",
|
||||
"node": "INT_R_X17Y137/SE6BEG0",
|
||||
"pin": "F6",
|
||||
"wire": ""
|
||||
},
|
||||
{
|
||||
"name": "dout[5]",
|
||||
"node": "INT_R_X17Y140/SE6BEG0",
|
||||
"pin": "J4",
|
||||
"wire": ""
|
||||
},
|
||||
{
|
||||
"name": "dout[6]",
|
||||
"node": "INT_R_X17Y143/SE6BEG0",
|
||||
"pin": "J2",
|
||||
"wire": ""
|
||||
},
|
||||
{
|
||||
"name": "dout[7]",
|
||||
"node": "INT_R_X17Y146/SE6BEG0",
|
||||
"pin": "H6",
|
||||
"wire": ""
|
||||
}
|
||||
]
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,112 +1,112 @@
|
|||
{
|
||||
"info": {
|
||||
"GRID_X_MAX": 47,
|
||||
"GRID_X_MIN": 18,
|
||||
"GRID_Y_MAX": 52,
|
||||
"GRID_Y_MIN": 0
|
||||
},
|
||||
"ports": [
|
||||
{
|
||||
"name": "clk",
|
||||
"node": "CLK_HROW_TOP_R_X60Y130/CLK_HROW_CK_BUFHCLK_L0",
|
||||
"pin": "W5",
|
||||
"wire": "HCLK_VBRK_X34Y130/HCLK_VBRK_CK_BUFHCLK0"
|
||||
"info": {
|
||||
"GRID_X_MAX": 47,
|
||||
"GRID_X_MIN": 18,
|
||||
"GRID_Y_MAX": 52,
|
||||
"GRID_Y_MIN": 0
|
||||
},
|
||||
{
|
||||
"name": "din[0]",
|
||||
"node": "INT_R_X9Y102/NE2BEG3",
|
||||
"pin": "V17",
|
||||
"wire": "VBRK_X29Y108/VBRK_NE2A3"
|
||||
},
|
||||
{
|
||||
"name": "din[1]",
|
||||
"node": "INT_R_X9Y105/NE2BEG3",
|
||||
"pin": "V16",
|
||||
"wire": "VBRK_X29Y111/VBRK_NE2A3"
|
||||
},
|
||||
{
|
||||
"name": "din[2]",
|
||||
"node": "INT_R_X9Y108/NE2BEG3",
|
||||
"pin": "W16",
|
||||
"wire": "VBRK_X29Y114/VBRK_NE2A3"
|
||||
},
|
||||
{
|
||||
"name": "din[3]",
|
||||
"node": "INT_R_X9Y111/NE2BEG3",
|
||||
"pin": "W17",
|
||||
"wire": "VBRK_X29Y117/VBRK_NE2A3"
|
||||
},
|
||||
{
|
||||
"name": "din[4]",
|
||||
"node": "INT_R_X9Y114/NE2BEG3",
|
||||
"pin": "W15",
|
||||
"wire": "VBRK_X29Y120/VBRK_NE2A3"
|
||||
},
|
||||
{
|
||||
"name": "din[5]",
|
||||
"node": "INT_R_X9Y117/NE2BEG3",
|
||||
"pin": "V15",
|
||||
"wire": "VBRK_X29Y123/VBRK_NE2A3"
|
||||
},
|
||||
{
|
||||
"name": "din[6]",
|
||||
"node": "INT_R_X9Y120/NE2BEG3",
|
||||
"pin": "W14",
|
||||
"wire": "VBRK_X29Y126/VBRK_NE2A3"
|
||||
},
|
||||
{
|
||||
"name": "din[7]",
|
||||
"node": "INT_R_X9Y123/NE2BEG3",
|
||||
"pin": "W13",
|
||||
"wire": "VBRK_X29Y129/VBRK_NE2A3"
|
||||
},
|
||||
{
|
||||
"name": "dout[0]",
|
||||
"node": "INT_L_X10Y125/SW6BEG0",
|
||||
"pin": "U16",
|
||||
"wire": "VBRK_X29Y131/VBRK_SW4A0"
|
||||
},
|
||||
{
|
||||
"name": "dout[1]",
|
||||
"node": "INT_L_X10Y128/SW6BEG0",
|
||||
"pin": "E19",
|
||||
"wire": "VBRK_X29Y134/VBRK_SW4A0"
|
||||
},
|
||||
{
|
||||
"name": "dout[2]",
|
||||
"node": "INT_L_X10Y131/SW6BEG0",
|
||||
"pin": "U19",
|
||||
"wire": "VBRK_X29Y137/VBRK_SW4A0"
|
||||
},
|
||||
{
|
||||
"name": "dout[3]",
|
||||
"node": "INT_L_X10Y134/SW6BEG0",
|
||||
"pin": "V19",
|
||||
"wire": "VBRK_X29Y140/VBRK_SW4A0"
|
||||
},
|
||||
{
|
||||
"name": "dout[4]",
|
||||
"node": "INT_L_X10Y137/SW6BEG0",
|
||||
"pin": "W18",
|
||||
"wire": "VBRK_X29Y143/VBRK_SW4A0"
|
||||
},
|
||||
{
|
||||
"name": "dout[5]",
|
||||
"node": "INT_L_X10Y140/SW6BEG0",
|
||||
"pin": "U15",
|
||||
"wire": "VBRK_X29Y146/VBRK_SW4A0"
|
||||
},
|
||||
{
|
||||
"name": "dout[6]",
|
||||
"node": "INT_L_X10Y143/SW6BEG0",
|
||||
"pin": "U14",
|
||||
"wire": "VBRK_X29Y149/VBRK_SW4A0"
|
||||
},
|
||||
{
|
||||
"name": "dout[7]",
|
||||
"node": "INT_L_X10Y146/SW6BEG0",
|
||||
"pin": "V14",
|
||||
"wire": "VBRK_X29Y152/VBRK_SW4A0"
|
||||
}
|
||||
]
|
||||
}
|
||||
"ports": [
|
||||
{
|
||||
"name": "clk",
|
||||
"node": "CLK_HROW_TOP_R_X60Y130/CLK_HROW_CK_BUFHCLK_L0",
|
||||
"pin": "W5",
|
||||
"wire": "HCLK_VBRK_X34Y130/HCLK_VBRK_CK_BUFHCLK0"
|
||||
},
|
||||
{
|
||||
"name": "din[0]",
|
||||
"node": "INT_R_X9Y102/NE2BEG3",
|
||||
"pin": "V17",
|
||||
"wire": "VBRK_X29Y108/VBRK_NE2A3"
|
||||
},
|
||||
{
|
||||
"name": "din[1]",
|
||||
"node": "INT_R_X9Y105/NE2BEG3",
|
||||
"pin": "V16",
|
||||
"wire": "VBRK_X29Y111/VBRK_NE2A3"
|
||||
},
|
||||
{
|
||||
"name": "din[2]",
|
||||
"node": "INT_R_X9Y108/NE2BEG3",
|
||||
"pin": "W16",
|
||||
"wire": "VBRK_X29Y114/VBRK_NE2A3"
|
||||
},
|
||||
{
|
||||
"name": "din[3]",
|
||||
"node": "INT_R_X9Y111/NE2BEG3",
|
||||
"pin": "W17",
|
||||
"wire": "VBRK_X29Y117/VBRK_NE2A3"
|
||||
},
|
||||
{
|
||||
"name": "din[4]",
|
||||
"node": "INT_R_X9Y114/NE2BEG3",
|
||||
"pin": "W15",
|
||||
"wire": "VBRK_X29Y120/VBRK_NE2A3"
|
||||
},
|
||||
{
|
||||
"name": "din[5]",
|
||||
"node": "INT_R_X9Y117/NE2BEG3",
|
||||
"pin": "V15",
|
||||
"wire": "VBRK_X29Y123/VBRK_NE2A3"
|
||||
},
|
||||
{
|
||||
"name": "din[6]",
|
||||
"node": "INT_R_X9Y120/NE2BEG3",
|
||||
"pin": "W14",
|
||||
"wire": "VBRK_X29Y126/VBRK_NE2A3"
|
||||
},
|
||||
{
|
||||
"name": "din[7]",
|
||||
"node": "INT_R_X9Y123/NE2BEG3",
|
||||
"pin": "W13",
|
||||
"wire": "VBRK_X29Y129/VBRK_NE2A3"
|
||||
},
|
||||
{
|
||||
"name": "dout[0]",
|
||||
"node": "INT_L_X10Y125/SW6BEG0",
|
||||
"pin": "U16",
|
||||
"wire": "VBRK_X29Y131/VBRK_SW4A0"
|
||||
},
|
||||
{
|
||||
"name": "dout[1]",
|
||||
"node": "INT_L_X10Y128/SW6BEG0",
|
||||
"pin": "E19",
|
||||
"wire": "VBRK_X29Y134/VBRK_SW4A0"
|
||||
},
|
||||
{
|
||||
"name": "dout[2]",
|
||||
"node": "INT_L_X10Y131/SW6BEG0",
|
||||
"pin": "U19",
|
||||
"wire": "VBRK_X29Y137/VBRK_SW4A0"
|
||||
},
|
||||
{
|
||||
"name": "dout[3]",
|
||||
"node": "INT_L_X10Y134/SW6BEG0",
|
||||
"pin": "V19",
|
||||
"wire": "VBRK_X29Y140/VBRK_SW4A0"
|
||||
},
|
||||
{
|
||||
"name": "dout[4]",
|
||||
"node": "INT_L_X10Y137/SW6BEG0",
|
||||
"pin": "W18",
|
||||
"wire": "VBRK_X29Y143/VBRK_SW4A0"
|
||||
},
|
||||
{
|
||||
"name": "dout[5]",
|
||||
"node": "INT_L_X10Y140/SW6BEG0",
|
||||
"pin": "U15",
|
||||
"wire": "VBRK_X29Y146/VBRK_SW4A0"
|
||||
},
|
||||
{
|
||||
"name": "dout[6]",
|
||||
"node": "INT_L_X10Y143/SW6BEG0",
|
||||
"pin": "U14",
|
||||
"wire": "VBRK_X29Y149/VBRK_SW4A0"
|
||||
},
|
||||
{
|
||||
"name": "dout[7]",
|
||||
"node": "INT_L_X10Y146/SW6BEG0",
|
||||
"pin": "V14",
|
||||
"wire": "VBRK_X29Y152/VBRK_SW4A0"
|
||||
}
|
||||
]
|
||||
}
|
||||
|
|
|
|||
|
|
@ -250,6 +250,7 @@ bit 01_10
|
|||
bit 01_100
|
||||
bit 01_101
|
||||
bit 01_102
|
||||
bit 01_103
|
||||
bit 01_104
|
||||
bit 01_105
|
||||
bit 01_106
|
||||
|
|
@ -301,6 +302,7 @@ bit 01_162
|
|||
bit 01_164
|
||||
bit 01_165
|
||||
bit 01_166
|
||||
bit 01_167
|
||||
bit 01_168
|
||||
bit 01_169
|
||||
bit 01_17
|
||||
|
|
@ -353,6 +355,7 @@ bit 01_226
|
|||
bit 01_228
|
||||
bit 01_229
|
||||
bit 01_230
|
||||
bit 01_231
|
||||
bit 01_232
|
||||
bit 01_233
|
||||
bit 01_234
|
||||
|
|
@ -405,6 +408,7 @@ bit 01_290
|
|||
bit 01_292
|
||||
bit 01_293
|
||||
bit 01_294
|
||||
bit 01_295
|
||||
bit 01_296
|
||||
bit 01_297
|
||||
bit 01_298
|
||||
|
|
@ -429,6 +433,7 @@ bit 01_34
|
|||
bit 01_36
|
||||
bit 01_37
|
||||
bit 01_38
|
||||
bit 01_39
|
||||
bit 01_40
|
||||
bit 01_41
|
||||
bit 01_42
|
||||
|
|
@ -7993,6 +7998,198 @@ bit 25_96
|
|||
bit 25_97
|
||||
bit 25_98
|
||||
bit 25_99
|
||||
bit 27_01
|
||||
bit 27_02
|
||||
bit 27_06
|
||||
bit 27_07
|
||||
bit 27_09
|
||||
bit 27_10
|
||||
bit 27_102
|
||||
bit 27_103
|
||||
bit 27_105
|
||||
bit 27_106
|
||||
bit 27_107
|
||||
bit 27_109
|
||||
bit 27_110
|
||||
bit 27_111
|
||||
bit 27_112
|
||||
bit 27_113
|
||||
bit 27_114
|
||||
bit 27_115
|
||||
bit 27_116
|
||||
bit 27_117
|
||||
bit 27_118
|
||||
bit 27_119
|
||||
bit 27_120
|
||||
bit 27_121
|
||||
bit 27_122
|
||||
bit 27_123
|
||||
bit 27_126
|
||||
bit 27_127
|
||||
bit 27_129
|
||||
bit 27_130
|
||||
bit 27_134
|
||||
bit 27_135
|
||||
bit 27_137
|
||||
bit 27_138
|
||||
bit 27_14
|
||||
bit 27_142
|
||||
bit 27_143
|
||||
bit 27_15
|
||||
bit 27_17
|
||||
bit 27_177
|
||||
bit 27_178
|
||||
bit 27_18
|
||||
bit 27_182
|
||||
bit 27_183
|
||||
bit 27_185
|
||||
bit 27_186
|
||||
bit 27_190
|
||||
bit 27_191
|
||||
bit 27_193
|
||||
bit 27_194
|
||||
bit 27_197
|
||||
bit 27_198
|
||||
bit 27_199
|
||||
bit 27_200
|
||||
bit 27_201
|
||||
bit 27_202
|
||||
bit 27_203
|
||||
bit 27_204
|
||||
bit 27_205
|
||||
bit 27_206
|
||||
bit 27_207
|
||||
bit 27_208
|
||||
bit 27_209
|
||||
bit 27_210
|
||||
bit 27_211
|
||||
bit 27_213
|
||||
bit 27_214
|
||||
bit 27_215
|
||||
bit 27_217
|
||||
bit 27_218
|
||||
bit 27_22
|
||||
bit 27_222
|
||||
bit 27_223
|
||||
bit 27_225
|
||||
bit 27_226
|
||||
bit 27_23
|
||||
bit 27_230
|
||||
bit 27_231
|
||||
bit 27_233
|
||||
bit 27_234
|
||||
bit 27_238
|
||||
bit 27_239
|
||||
bit 27_241
|
||||
bit 27_242
|
||||
bit 27_246
|
||||
bit 27_247
|
||||
bit 27_249
|
||||
bit 27_25
|
||||
bit 27_250
|
||||
bit 27_252
|
||||
bit 27_253
|
||||
bit 27_254
|
||||
bit 27_255
|
||||
bit 27_256
|
||||
bit 27_257
|
||||
bit 27_258
|
||||
bit 27_259
|
||||
bit 27_26
|
||||
bit 27_260
|
||||
bit 27_261
|
||||
bit 27_262
|
||||
bit 27_263
|
||||
bit 27_264
|
||||
bit 27_265
|
||||
bit 27_266
|
||||
bit 27_267
|
||||
bit 27_268
|
||||
bit 27_269
|
||||
bit 27_270
|
||||
bit 27_271
|
||||
bit 27_273
|
||||
bit 27_274
|
||||
bit 27_275
|
||||
bit 27_276
|
||||
bit 27_277
|
||||
bit 27_278
|
||||
bit 27_279
|
||||
bit 27_281
|
||||
bit 27_282
|
||||
bit 27_283
|
||||
bit 27_284
|
||||
bit 27_285
|
||||
bit 27_286
|
||||
bit 27_287
|
||||
bit 27_289
|
||||
bit 27_290
|
||||
bit 27_294
|
||||
bit 27_295
|
||||
bit 27_297
|
||||
bit 27_298
|
||||
bit 27_30
|
||||
bit 27_302
|
||||
bit 27_303
|
||||
bit 27_305
|
||||
bit 27_306
|
||||
bit 27_31
|
||||
bit 27_310
|
||||
bit 27_311
|
||||
bit 27_313
|
||||
bit 27_314
|
||||
bit 27_318
|
||||
bit 27_319
|
||||
bit 27_33
|
||||
bit 27_34
|
||||
bit 27_35
|
||||
bit 27_36
|
||||
bit 27_37
|
||||
bit 27_38
|
||||
bit 27_39
|
||||
bit 27_41
|
||||
bit 27_42
|
||||
bit 27_43
|
||||
bit 27_44
|
||||
bit 27_45
|
||||
bit 27_46
|
||||
bit 27_47
|
||||
bit 27_49
|
||||
bit 27_50
|
||||
bit 27_51
|
||||
bit 27_52
|
||||
bit 27_53
|
||||
bit 27_54
|
||||
bit 27_55
|
||||
bit 27_56
|
||||
bit 27_57
|
||||
bit 27_58
|
||||
bit 27_59
|
||||
bit 27_60
|
||||
bit 27_61
|
||||
bit 27_62
|
||||
bit 27_63
|
||||
bit 27_64
|
||||
bit 27_65
|
||||
bit 27_66
|
||||
bit 27_67
|
||||
bit 27_68
|
||||
bit 27_70
|
||||
bit 27_71
|
||||
bit 27_73
|
||||
bit 27_74
|
||||
bit 27_78
|
||||
bit 27_79
|
||||
bit 27_81
|
||||
bit 27_82
|
||||
bit 27_86
|
||||
bit 27_87
|
||||
bit 27_89
|
||||
bit 27_90
|
||||
bit 27_94
|
||||
bit 27_95
|
||||
bit 27_97
|
||||
bit 27_98
|
||||
bit 30_02
|
||||
bit 30_101
|
||||
bit 30_124
|
||||
|
|
|
|||
|
|
@ -8003,6 +8003,198 @@ bit 25_96
|
|||
bit 25_97
|
||||
bit 25_98
|
||||
bit 25_99
|
||||
bit 27_01
|
||||
bit 27_02
|
||||
bit 27_06
|
||||
bit 27_07
|
||||
bit 27_09
|
||||
bit 27_10
|
||||
bit 27_102
|
||||
bit 27_103
|
||||
bit 27_105
|
||||
bit 27_106
|
||||
bit 27_107
|
||||
bit 27_109
|
||||
bit 27_110
|
||||
bit 27_111
|
||||
bit 27_112
|
||||
bit 27_113
|
||||
bit 27_114
|
||||
bit 27_115
|
||||
bit 27_116
|
||||
bit 27_117
|
||||
bit 27_118
|
||||
bit 27_119
|
||||
bit 27_120
|
||||
bit 27_121
|
||||
bit 27_122
|
||||
bit 27_123
|
||||
bit 27_126
|
||||
bit 27_127
|
||||
bit 27_129
|
||||
bit 27_130
|
||||
bit 27_134
|
||||
bit 27_135
|
||||
bit 27_137
|
||||
bit 27_138
|
||||
bit 27_14
|
||||
bit 27_142
|
||||
bit 27_143
|
||||
bit 27_15
|
||||
bit 27_17
|
||||
bit 27_177
|
||||
bit 27_178
|
||||
bit 27_18
|
||||
bit 27_182
|
||||
bit 27_183
|
||||
bit 27_185
|
||||
bit 27_186
|
||||
bit 27_190
|
||||
bit 27_191
|
||||
bit 27_193
|
||||
bit 27_194
|
||||
bit 27_197
|
||||
bit 27_198
|
||||
bit 27_199
|
||||
bit 27_200
|
||||
bit 27_201
|
||||
bit 27_202
|
||||
bit 27_203
|
||||
bit 27_204
|
||||
bit 27_205
|
||||
bit 27_206
|
||||
bit 27_207
|
||||
bit 27_208
|
||||
bit 27_209
|
||||
bit 27_210
|
||||
bit 27_211
|
||||
bit 27_213
|
||||
bit 27_214
|
||||
bit 27_215
|
||||
bit 27_217
|
||||
bit 27_218
|
||||
bit 27_22
|
||||
bit 27_222
|
||||
bit 27_223
|
||||
bit 27_225
|
||||
bit 27_226
|
||||
bit 27_23
|
||||
bit 27_230
|
||||
bit 27_231
|
||||
bit 27_233
|
||||
bit 27_234
|
||||
bit 27_238
|
||||
bit 27_239
|
||||
bit 27_241
|
||||
bit 27_242
|
||||
bit 27_246
|
||||
bit 27_247
|
||||
bit 27_249
|
||||
bit 27_25
|
||||
bit 27_250
|
||||
bit 27_252
|
||||
bit 27_253
|
||||
bit 27_254
|
||||
bit 27_255
|
||||
bit 27_256
|
||||
bit 27_257
|
||||
bit 27_258
|
||||
bit 27_259
|
||||
bit 27_26
|
||||
bit 27_260
|
||||
bit 27_261
|
||||
bit 27_262
|
||||
bit 27_263
|
||||
bit 27_264
|
||||
bit 27_265
|
||||
bit 27_266
|
||||
bit 27_267
|
||||
bit 27_268
|
||||
bit 27_269
|
||||
bit 27_270
|
||||
bit 27_271
|
||||
bit 27_273
|
||||
bit 27_274
|
||||
bit 27_275
|
||||
bit 27_276
|
||||
bit 27_277
|
||||
bit 27_278
|
||||
bit 27_279
|
||||
bit 27_281
|
||||
bit 27_282
|
||||
bit 27_283
|
||||
bit 27_284
|
||||
bit 27_285
|
||||
bit 27_286
|
||||
bit 27_287
|
||||
bit 27_289
|
||||
bit 27_290
|
||||
bit 27_294
|
||||
bit 27_295
|
||||
bit 27_297
|
||||
bit 27_298
|
||||
bit 27_30
|
||||
bit 27_302
|
||||
bit 27_303
|
||||
bit 27_305
|
||||
bit 27_306
|
||||
bit 27_31
|
||||
bit 27_310
|
||||
bit 27_311
|
||||
bit 27_313
|
||||
bit 27_314
|
||||
bit 27_318
|
||||
bit 27_319
|
||||
bit 27_33
|
||||
bit 27_34
|
||||
bit 27_35
|
||||
bit 27_36
|
||||
bit 27_37
|
||||
bit 27_38
|
||||
bit 27_39
|
||||
bit 27_41
|
||||
bit 27_42
|
||||
bit 27_43
|
||||
bit 27_44
|
||||
bit 27_45
|
||||
bit 27_46
|
||||
bit 27_47
|
||||
bit 27_49
|
||||
bit 27_50
|
||||
bit 27_51
|
||||
bit 27_52
|
||||
bit 27_53
|
||||
bit 27_54
|
||||
bit 27_55
|
||||
bit 27_56
|
||||
bit 27_57
|
||||
bit 27_58
|
||||
bit 27_59
|
||||
bit 27_60
|
||||
bit 27_61
|
||||
bit 27_62
|
||||
bit 27_63
|
||||
bit 27_64
|
||||
bit 27_65
|
||||
bit 27_66
|
||||
bit 27_67
|
||||
bit 27_68
|
||||
bit 27_70
|
||||
bit 27_71
|
||||
bit 27_73
|
||||
bit 27_74
|
||||
bit 27_78
|
||||
bit 27_79
|
||||
bit 27_81
|
||||
bit 27_82
|
||||
bit 27_86
|
||||
bit 27_87
|
||||
bit 27_89
|
||||
bit 27_90
|
||||
bit 27_94
|
||||
bit 27_95
|
||||
bit 27_97
|
||||
bit 27_98
|
||||
bit 30_02
|
||||
bit 30_101
|
||||
bit 30_124
|
||||
|
|
|
|||
|
|
@ -250,6 +250,7 @@ bit 01_10
|
|||
bit 01_100
|
||||
bit 01_101
|
||||
bit 01_102
|
||||
bit 01_103
|
||||
bit 01_104
|
||||
bit 01_105
|
||||
bit 01_106
|
||||
|
|
@ -301,6 +302,7 @@ bit 01_162
|
|||
bit 01_164
|
||||
bit 01_165
|
||||
bit 01_166
|
||||
bit 01_167
|
||||
bit 01_168
|
||||
bit 01_169
|
||||
bit 01_17
|
||||
|
|
@ -353,6 +355,7 @@ bit 01_226
|
|||
bit 01_228
|
||||
bit 01_229
|
||||
bit 01_230
|
||||
bit 01_231
|
||||
bit 01_232
|
||||
bit 01_233
|
||||
bit 01_234
|
||||
|
|
@ -405,6 +408,7 @@ bit 01_290
|
|||
bit 01_292
|
||||
bit 01_293
|
||||
bit 01_294
|
||||
bit 01_295
|
||||
bit 01_296
|
||||
bit 01_297
|
||||
bit 01_298
|
||||
|
|
@ -429,6 +433,7 @@ bit 01_34
|
|||
bit 01_36
|
||||
bit 01_37
|
||||
bit 01_38
|
||||
bit 01_39
|
||||
bit 01_40
|
||||
bit 01_41
|
||||
bit 01_42
|
||||
|
|
|
|||
|
|
@ -0,0 +1,192 @@
|
|||
BRAM_L.RAMB18_Y0.INIT_A[0] 27_73
|
||||
BRAM_L.RAMB18_Y0.INIT_A[10] 27_129
|
||||
BRAM_L.RAMB18_Y0.INIT_A[11] 27_113
|
||||
BRAM_L.RAMB18_Y0.INIT_A[12] 27_97
|
||||
BRAM_L.RAMB18_Y0.INIT_A[1] 27_65
|
||||
BRAM_L.RAMB18_Y0.INIT_A[13] 27_81
|
||||
BRAM_L.RAMB18_Y0.INIT_A[14] 27_49
|
||||
BRAM_L.RAMB18_Y0.INIT_A[15] 27_33
|
||||
BRAM_L.RAMB18_Y0.INIT_A[16] 27_17
|
||||
BRAM_L.RAMB18_Y0.INIT_A[17] 27_01
|
||||
BRAM_L.RAMB18_Y0.INIT_A[2] 27_137
|
||||
BRAM_L.RAMB18_Y0.INIT_A[3] 27_121
|
||||
BRAM_L.RAMB18_Y0.INIT_A[4] 27_105
|
||||
BRAM_L.RAMB18_Y0.INIT_A[5] 27_89
|
||||
BRAM_L.RAMB18_Y0.INIT_A[6] 27_57
|
||||
BRAM_L.RAMB18_Y0.INIT_A[7] 27_41
|
||||
BRAM_L.RAMB18_Y0.INIT_A[8] 27_25
|
||||
BRAM_L.RAMB18_Y0.INIT_A[9] 27_09
|
||||
BRAM_L.RAMB18_Y0.INIT_B[0] 27_79
|
||||
BRAM_L.RAMB18_Y0.INIT_B[10] 27_135
|
||||
BRAM_L.RAMB18_Y0.INIT_B[11] 27_119
|
||||
BRAM_L.RAMB18_Y0.INIT_B[12] 27_103
|
||||
BRAM_L.RAMB18_Y0.INIT_B[1] 27_71
|
||||
BRAM_L.RAMB18_Y0.INIT_B[13] 27_87
|
||||
BRAM_L.RAMB18_Y0.INIT_B[14] 27_55
|
||||
BRAM_L.RAMB18_Y0.INIT_B[15] 27_39
|
||||
BRAM_L.RAMB18_Y0.INIT_B[16] 27_23
|
||||
BRAM_L.RAMB18_Y0.INIT_B[17] 27_07
|
||||
BRAM_L.RAMB18_Y0.INIT_B[2] 27_143
|
||||
BRAM_L.RAMB18_Y0.INIT_B[3] 27_127
|
||||
BRAM_L.RAMB18_Y0.INIT_B[4] 27_111
|
||||
BRAM_L.RAMB18_Y0.INIT_B[5] 27_95
|
||||
BRAM_L.RAMB18_Y0.INIT_B[6] 27_63
|
||||
BRAM_L.RAMB18_Y0.INIT_B[7] 27_47
|
||||
BRAM_L.RAMB18_Y0.INIT_B[8] 27_31
|
||||
BRAM_L.RAMB18_Y0.INIT_B[9] 27_15
|
||||
BRAM_L.RAMB18_Y0.READ_WIDTH_A_B0 27_35
|
||||
BRAM_L.RAMB18_Y0.READ_WIDTH_A_B1 27_36
|
||||
BRAM_L.RAMB18_Y0.READ_WIDTH_A_B2 27_37
|
||||
BRAM_L.RAMB18_Y0.READ_WIDTH_B_B0 27_43
|
||||
BRAM_L.RAMB18_Y0.READ_WIDTH_B_B1 27_44
|
||||
BRAM_L.RAMB18_Y0.READ_WIDTH_B_B2 27_45
|
||||
BRAM_L.RAMB18_Y0.SRVAL_A[0] 27_74
|
||||
BRAM_L.RAMB18_Y0.SRVAL_A[10] 27_130
|
||||
BRAM_L.RAMB18_Y0.SRVAL_A[11] 27_114
|
||||
BRAM_L.RAMB18_Y0.SRVAL_A[12] 27_98
|
||||
BRAM_L.RAMB18_Y0.SRVAL_A[1] 27_66
|
||||
BRAM_L.RAMB18_Y0.SRVAL_A[13] 27_82
|
||||
BRAM_L.RAMB18_Y0.SRVAL_A[14] 27_50
|
||||
BRAM_L.RAMB18_Y0.SRVAL_A[15] 27_34
|
||||
BRAM_L.RAMB18_Y0.SRVAL_A[16] 27_18
|
||||
BRAM_L.RAMB18_Y0.SRVAL_A[17] 27_02
|
||||
BRAM_L.RAMB18_Y0.SRVAL_A[2] 27_138
|
||||
BRAM_L.RAMB18_Y0.SRVAL_A[3] 27_122
|
||||
BRAM_L.RAMB18_Y0.SRVAL_A[4] 27_106
|
||||
BRAM_L.RAMB18_Y0.SRVAL_A[5] 27_90
|
||||
BRAM_L.RAMB18_Y0.SRVAL_A[6] 27_58
|
||||
BRAM_L.RAMB18_Y0.SRVAL_A[7] 27_42
|
||||
BRAM_L.RAMB18_Y0.SRVAL_A[8] 27_26
|
||||
BRAM_L.RAMB18_Y0.SRVAL_A[9] 27_10
|
||||
BRAM_L.RAMB18_Y0.SRVAL_B[0] 27_78
|
||||
BRAM_L.RAMB18_Y0.SRVAL_B[10] 27_134
|
||||
BRAM_L.RAMB18_Y0.SRVAL_B[11] 27_118
|
||||
BRAM_L.RAMB18_Y0.SRVAL_B[12] 27_102
|
||||
BRAM_L.RAMB18_Y0.SRVAL_B[1] 27_70
|
||||
BRAM_L.RAMB18_Y0.SRVAL_B[13] 27_86
|
||||
BRAM_L.RAMB18_Y0.SRVAL_B[14] 27_54
|
||||
BRAM_L.RAMB18_Y0.SRVAL_B[15] 27_38
|
||||
BRAM_L.RAMB18_Y0.SRVAL_B[16] 27_22
|
||||
BRAM_L.RAMB18_Y0.SRVAL_B[17] 27_06
|
||||
BRAM_L.RAMB18_Y0.SRVAL_B[2] 27_142
|
||||
BRAM_L.RAMB18_Y0.SRVAL_B[3] 27_126
|
||||
BRAM_L.RAMB18_Y0.SRVAL_B[4] 27_110
|
||||
BRAM_L.RAMB18_Y0.SRVAL_B[5] 27_94
|
||||
BRAM_L.RAMB18_Y0.SRVAL_B[6] 27_62
|
||||
BRAM_L.RAMB18_Y0.SRVAL_B[7] 27_46
|
||||
BRAM_L.RAMB18_Y0.SRVAL_B[8] 27_30
|
||||
BRAM_L.RAMB18_Y0.SRVAL_B[9] 27_14
|
||||
BRAM_L.RAMB18_Y0.WRITE_MODE_A_NO_CHANGE 27_64
|
||||
BRAM_L.RAMB18_Y0.WRITE_MODE_A_READ_FIRST 27_56
|
||||
BRAM_L.RAMB18_Y0.WRITE_MODE_B_NO_CHANGE 27_68
|
||||
BRAM_L.RAMB18_Y0.WRITE_MODE_B_READ_FIRST 27_67
|
||||
BRAM_L.RAMB18_Y0.WRITE_WIDTH_A_B0 27_51
|
||||
BRAM_L.RAMB18_Y0.WRITE_WIDTH_A_B1 27_52
|
||||
BRAM_L.RAMB18_Y0.WRITE_WIDTH_A_B2 27_53
|
||||
BRAM_L.RAMB18_Y0.WRITE_WIDTH_B_B0 27_59
|
||||
BRAM_L.RAMB18_Y0.WRITE_WIDTH_B_B1 27_60
|
||||
BRAM_L.RAMB18_Y0.WRITE_WIDTH_B_B2 27_61
|
||||
BRAM_L.RAMB18_Y0.ZINV_CLKARDCLK 27_107
|
||||
BRAM_L.RAMB18_Y0.ZINV_CLKBWRCLK 27_109
|
||||
BRAM_L.RAMB18_Y0.ZINV_ENARDEN 27_112
|
||||
BRAM_L.RAMB18_Y0.ZINV_ENBWREN 27_115
|
||||
BRAM_L.RAMB18_Y0.ZINV_RSTRAMARSTRAM 27_116
|
||||
BRAM_L.RAMB18_Y0.ZINV_RSTRAMB 27_117
|
||||
BRAM_L.RAMB18_Y0.ZINV_RSTREGARSTREG 27_120
|
||||
BRAM_L.RAMB18_Y0.ZINV_RSTREGB 27_123
|
||||
BRAM_L.RAMB18_Y1.INIT_A[0] 27_249
|
||||
BRAM_L.RAMB18_Y1.INIT_A[10] 27_305
|
||||
BRAM_L.RAMB18_Y1.INIT_A[11] 27_289
|
||||
BRAM_L.RAMB18_Y1.INIT_A[12] 27_273
|
||||
BRAM_L.RAMB18_Y1.INIT_A[1] 27_241
|
||||
BRAM_L.RAMB18_Y1.INIT_A[13] 27_257
|
||||
BRAM_L.RAMB18_Y1.INIT_A[14] 27_225
|
||||
BRAM_L.RAMB18_Y1.INIT_A[15] 27_209
|
||||
BRAM_L.RAMB18_Y1.INIT_A[16] 27_193
|
||||
BRAM_L.RAMB18_Y1.INIT_A[17] 27_177
|
||||
BRAM_L.RAMB18_Y1.INIT_A[2] 27_313
|
||||
BRAM_L.RAMB18_Y1.INIT_A[3] 27_297
|
||||
BRAM_L.RAMB18_Y1.INIT_A[4] 27_281
|
||||
BRAM_L.RAMB18_Y1.INIT_A[5] 27_265
|
||||
BRAM_L.RAMB18_Y1.INIT_A[6] 27_233
|
||||
BRAM_L.RAMB18_Y1.INIT_A[7] 27_217
|
||||
BRAM_L.RAMB18_Y1.INIT_A[8] 27_201
|
||||
BRAM_L.RAMB18_Y1.INIT_A[9] 27_185
|
||||
BRAM_L.RAMB18_Y1.INIT_B[0] 27_255
|
||||
BRAM_L.RAMB18_Y1.INIT_B[10] 27_311
|
||||
BRAM_L.RAMB18_Y1.INIT_B[11] 27_295
|
||||
BRAM_L.RAMB18_Y1.INIT_B[12] 27_279
|
||||
BRAM_L.RAMB18_Y1.INIT_B[1] 27_247
|
||||
BRAM_L.RAMB18_Y1.INIT_B[13] 27_263
|
||||
BRAM_L.RAMB18_Y1.INIT_B[14] 27_231
|
||||
BRAM_L.RAMB18_Y1.INIT_B[15] 27_215
|
||||
BRAM_L.RAMB18_Y1.INIT_B[16] 27_199
|
||||
BRAM_L.RAMB18_Y1.INIT_B[17] 27_183
|
||||
BRAM_L.RAMB18_Y1.INIT_B[2] 27_319
|
||||
BRAM_L.RAMB18_Y1.INIT_B[3] 27_303
|
||||
BRAM_L.RAMB18_Y1.INIT_B[4] 27_287
|
||||
BRAM_L.RAMB18_Y1.INIT_B[5] 27_271
|
||||
BRAM_L.RAMB18_Y1.INIT_B[6] 27_239
|
||||
BRAM_L.RAMB18_Y1.INIT_B[7] 27_223
|
||||
BRAM_L.RAMB18_Y1.INIT_B[8] 27_207
|
||||
BRAM_L.RAMB18_Y1.INIT_B[9] 27_191
|
||||
BRAM_L.RAMB18_Y1.READ_WIDTH_A_B0 27_285
|
||||
BRAM_L.RAMB18_Y1.READ_WIDTH_A_B1 27_284
|
||||
BRAM_L.RAMB18_Y1.READ_WIDTH_A_B2 27_283
|
||||
BRAM_L.RAMB18_Y1.READ_WIDTH_B_B0 27_277
|
||||
BRAM_L.RAMB18_Y1.READ_WIDTH_B_B1 27_276
|
||||
BRAM_L.RAMB18_Y1.READ_WIDTH_B_B2 27_275
|
||||
BRAM_L.RAMB18_Y1.SRVAL_A[0] 27_250
|
||||
BRAM_L.RAMB18_Y1.SRVAL_A[10] 27_306
|
||||
BRAM_L.RAMB18_Y1.SRVAL_A[11] 27_290
|
||||
BRAM_L.RAMB18_Y1.SRVAL_A[12] 27_274
|
||||
BRAM_L.RAMB18_Y1.SRVAL_A[1] 27_242
|
||||
BRAM_L.RAMB18_Y1.SRVAL_A[13] 27_258
|
||||
BRAM_L.RAMB18_Y1.SRVAL_A[14] 27_226
|
||||
BRAM_L.RAMB18_Y1.SRVAL_A[15] 27_210
|
||||
BRAM_L.RAMB18_Y1.SRVAL_A[16] 27_194
|
||||
BRAM_L.RAMB18_Y1.SRVAL_A[17] 27_178
|
||||
BRAM_L.RAMB18_Y1.SRVAL_A[2] 27_314
|
||||
BRAM_L.RAMB18_Y1.SRVAL_A[3] 27_298
|
||||
BRAM_L.RAMB18_Y1.SRVAL_A[4] 27_282
|
||||
BRAM_L.RAMB18_Y1.SRVAL_A[5] 27_266
|
||||
BRAM_L.RAMB18_Y1.SRVAL_A[6] 27_234
|
||||
BRAM_L.RAMB18_Y1.SRVAL_A[7] 27_218
|
||||
BRAM_L.RAMB18_Y1.SRVAL_A[8] 27_202
|
||||
BRAM_L.RAMB18_Y1.SRVAL_A[9] 27_186
|
||||
BRAM_L.RAMB18_Y1.SRVAL_B[0] 27_254
|
||||
BRAM_L.RAMB18_Y1.SRVAL_B[10] 27_310
|
||||
BRAM_L.RAMB18_Y1.SRVAL_B[11] 27_294
|
||||
BRAM_L.RAMB18_Y1.SRVAL_B[12] 27_278
|
||||
BRAM_L.RAMB18_Y1.SRVAL_B[1] 27_246
|
||||
BRAM_L.RAMB18_Y1.SRVAL_B[13] 27_262
|
||||
BRAM_L.RAMB18_Y1.SRVAL_B[14] 27_230
|
||||
BRAM_L.RAMB18_Y1.SRVAL_B[15] 27_214
|
||||
BRAM_L.RAMB18_Y1.SRVAL_B[16] 27_198
|
||||
BRAM_L.RAMB18_Y1.SRVAL_B[17] 27_182
|
||||
BRAM_L.RAMB18_Y1.SRVAL_B[2] 27_318
|
||||
BRAM_L.RAMB18_Y1.SRVAL_B[3] 27_302
|
||||
BRAM_L.RAMB18_Y1.SRVAL_B[4] 27_286
|
||||
BRAM_L.RAMB18_Y1.SRVAL_B[5] 27_270
|
||||
BRAM_L.RAMB18_Y1.SRVAL_B[6] 27_238
|
||||
BRAM_L.RAMB18_Y1.SRVAL_B[7] 27_222
|
||||
BRAM_L.RAMB18_Y1.SRVAL_B[8] 27_206
|
||||
BRAM_L.RAMB18_Y1.SRVAL_B[9] 27_190
|
||||
BRAM_L.RAMB18_Y1.WRITE_MODE_A_NO_CHANGE 27_256
|
||||
BRAM_L.RAMB18_Y1.WRITE_MODE_A_READ_FIRST 27_264
|
||||
BRAM_L.RAMB18_Y1.WRITE_MODE_B_NO_CHANGE 27_252
|
||||
BRAM_L.RAMB18_Y1.WRITE_MODE_B_READ_FIRST 27_253
|
||||
BRAM_L.RAMB18_Y1.WRITE_WIDTH_A_B0 27_269
|
||||
BRAM_L.RAMB18_Y1.WRITE_WIDTH_A_B1 27_268
|
||||
BRAM_L.RAMB18_Y1.WRITE_WIDTH_A_B2 27_267
|
||||
BRAM_L.RAMB18_Y1.WRITE_WIDTH_B_B0 27_261
|
||||
BRAM_L.RAMB18_Y1.WRITE_WIDTH_B_B1 27_260
|
||||
BRAM_L.RAMB18_Y1.WRITE_WIDTH_B_B2 27_259
|
||||
BRAM_L.RAMB18_Y1.ZINV_CLKARDCLK 27_213
|
||||
BRAM_L.RAMB18_Y1.ZINV_CLKBWRCLK 27_211
|
||||
BRAM_L.RAMB18_Y1.ZINV_ENARDEN 27_208
|
||||
BRAM_L.RAMB18_Y1.ZINV_ENBWREN 27_205
|
||||
BRAM_L.RAMB18_Y1.ZINV_RSTRAMARSTRAM 27_204
|
||||
BRAM_L.RAMB18_Y1.ZINV_RSTRAMB 27_203
|
||||
BRAM_L.RAMB18_Y1.ZINV_RSTREGARSTREG 27_200
|
||||
BRAM_L.RAMB18_Y1.ZINV_RSTREGB 27_197
|
||||
|
|
@ -0,0 +1,192 @@
|
|||
BRAM_R.RAMB18_Y0.INIT_A[0] 27_73
|
||||
BRAM_R.RAMB18_Y0.INIT_A[10] 27_129
|
||||
BRAM_R.RAMB18_Y0.INIT_A[11] 27_113
|
||||
BRAM_R.RAMB18_Y0.INIT_A[12] 27_97
|
||||
BRAM_R.RAMB18_Y0.INIT_A[1] 27_65
|
||||
BRAM_R.RAMB18_Y0.INIT_A[13] 27_81
|
||||
BRAM_R.RAMB18_Y0.INIT_A[14] 27_49
|
||||
BRAM_R.RAMB18_Y0.INIT_A[15] 27_33
|
||||
BRAM_R.RAMB18_Y0.INIT_A[16] 27_17
|
||||
BRAM_R.RAMB18_Y0.INIT_A[17] 27_01
|
||||
BRAM_R.RAMB18_Y0.INIT_A[2] 27_137
|
||||
BRAM_R.RAMB18_Y0.INIT_A[3] 27_121
|
||||
BRAM_R.RAMB18_Y0.INIT_A[4] 27_105
|
||||
BRAM_R.RAMB18_Y0.INIT_A[5] 27_89
|
||||
BRAM_R.RAMB18_Y0.INIT_A[6] 27_57
|
||||
BRAM_R.RAMB18_Y0.INIT_A[7] 27_41
|
||||
BRAM_R.RAMB18_Y0.INIT_A[8] 27_25
|
||||
BRAM_R.RAMB18_Y0.INIT_A[9] 27_09
|
||||
BRAM_R.RAMB18_Y0.INIT_B[0] 27_79
|
||||
BRAM_R.RAMB18_Y0.INIT_B[10] 27_135
|
||||
BRAM_R.RAMB18_Y0.INIT_B[11] 27_119
|
||||
BRAM_R.RAMB18_Y0.INIT_B[12] 27_103
|
||||
BRAM_R.RAMB18_Y0.INIT_B[1] 27_71
|
||||
BRAM_R.RAMB18_Y0.INIT_B[13] 27_87
|
||||
BRAM_R.RAMB18_Y0.INIT_B[14] 27_55
|
||||
BRAM_R.RAMB18_Y0.INIT_B[15] 27_39
|
||||
BRAM_R.RAMB18_Y0.INIT_B[16] 27_23
|
||||
BRAM_R.RAMB18_Y0.INIT_B[17] 27_07
|
||||
BRAM_R.RAMB18_Y0.INIT_B[2] 27_143
|
||||
BRAM_R.RAMB18_Y0.INIT_B[3] 27_127
|
||||
BRAM_R.RAMB18_Y0.INIT_B[4] 27_111
|
||||
BRAM_R.RAMB18_Y0.INIT_B[5] 27_95
|
||||
BRAM_R.RAMB18_Y0.INIT_B[6] 27_63
|
||||
BRAM_R.RAMB18_Y0.INIT_B[7] 27_47
|
||||
BRAM_R.RAMB18_Y0.INIT_B[8] 27_31
|
||||
BRAM_R.RAMB18_Y0.INIT_B[9] 27_15
|
||||
BRAM_R.RAMB18_Y0.READ_WIDTH_A_B0 27_35
|
||||
BRAM_R.RAMB18_Y0.READ_WIDTH_A_B1 27_36
|
||||
BRAM_R.RAMB18_Y0.READ_WIDTH_A_B2 27_37
|
||||
BRAM_R.RAMB18_Y0.READ_WIDTH_B_B0 27_43
|
||||
BRAM_R.RAMB18_Y0.READ_WIDTH_B_B1 27_44
|
||||
BRAM_R.RAMB18_Y0.READ_WIDTH_B_B2 27_45
|
||||
BRAM_R.RAMB18_Y0.SRVAL_A[0] 27_74
|
||||
BRAM_R.RAMB18_Y0.SRVAL_A[10] 27_130
|
||||
BRAM_R.RAMB18_Y0.SRVAL_A[11] 27_114
|
||||
BRAM_R.RAMB18_Y0.SRVAL_A[12] 27_98
|
||||
BRAM_R.RAMB18_Y0.SRVAL_A[1] 27_66
|
||||
BRAM_R.RAMB18_Y0.SRVAL_A[13] 27_82
|
||||
BRAM_R.RAMB18_Y0.SRVAL_A[14] 27_50
|
||||
BRAM_R.RAMB18_Y0.SRVAL_A[15] 27_34
|
||||
BRAM_R.RAMB18_Y0.SRVAL_A[16] 27_18
|
||||
BRAM_R.RAMB18_Y0.SRVAL_A[17] 27_02
|
||||
BRAM_R.RAMB18_Y0.SRVAL_A[2] 27_138
|
||||
BRAM_R.RAMB18_Y0.SRVAL_A[3] 27_122
|
||||
BRAM_R.RAMB18_Y0.SRVAL_A[4] 27_106
|
||||
BRAM_R.RAMB18_Y0.SRVAL_A[5] 27_90
|
||||
BRAM_R.RAMB18_Y0.SRVAL_A[6] 27_58
|
||||
BRAM_R.RAMB18_Y0.SRVAL_A[7] 27_42
|
||||
BRAM_R.RAMB18_Y0.SRVAL_A[8] 27_26
|
||||
BRAM_R.RAMB18_Y0.SRVAL_A[9] 27_10
|
||||
BRAM_R.RAMB18_Y0.SRVAL_B[0] 27_78
|
||||
BRAM_R.RAMB18_Y0.SRVAL_B[10] 27_134
|
||||
BRAM_R.RAMB18_Y0.SRVAL_B[11] 27_118
|
||||
BRAM_R.RAMB18_Y0.SRVAL_B[12] 27_102
|
||||
BRAM_R.RAMB18_Y0.SRVAL_B[1] 27_70
|
||||
BRAM_R.RAMB18_Y0.SRVAL_B[13] 27_86
|
||||
BRAM_R.RAMB18_Y0.SRVAL_B[14] 27_54
|
||||
BRAM_R.RAMB18_Y0.SRVAL_B[15] 27_38
|
||||
BRAM_R.RAMB18_Y0.SRVAL_B[16] 27_22
|
||||
BRAM_R.RAMB18_Y0.SRVAL_B[17] 27_06
|
||||
BRAM_R.RAMB18_Y0.SRVAL_B[2] 27_142
|
||||
BRAM_R.RAMB18_Y0.SRVAL_B[3] 27_126
|
||||
BRAM_R.RAMB18_Y0.SRVAL_B[4] 27_110
|
||||
BRAM_R.RAMB18_Y0.SRVAL_B[5] 27_94
|
||||
BRAM_R.RAMB18_Y0.SRVAL_B[6] 27_62
|
||||
BRAM_R.RAMB18_Y0.SRVAL_B[7] 27_46
|
||||
BRAM_R.RAMB18_Y0.SRVAL_B[8] 27_30
|
||||
BRAM_R.RAMB18_Y0.SRVAL_B[9] 27_14
|
||||
BRAM_R.RAMB18_Y0.WRITE_MODE_A_NO_CHANGE 27_64
|
||||
BRAM_R.RAMB18_Y0.WRITE_MODE_A_READ_FIRST 27_56
|
||||
BRAM_R.RAMB18_Y0.WRITE_MODE_B_NO_CHANGE 27_68
|
||||
BRAM_R.RAMB18_Y0.WRITE_MODE_B_READ_FIRST 27_67
|
||||
BRAM_R.RAMB18_Y0.WRITE_WIDTH_A_B0 27_51
|
||||
BRAM_R.RAMB18_Y0.WRITE_WIDTH_A_B1 27_52
|
||||
BRAM_R.RAMB18_Y0.WRITE_WIDTH_A_B2 27_53
|
||||
BRAM_R.RAMB18_Y0.WRITE_WIDTH_B_B0 27_59
|
||||
BRAM_R.RAMB18_Y0.WRITE_WIDTH_B_B1 27_60
|
||||
BRAM_R.RAMB18_Y0.WRITE_WIDTH_B_B2 27_61
|
||||
BRAM_R.RAMB18_Y0.ZINV_CLKARDCLK 27_107
|
||||
BRAM_R.RAMB18_Y0.ZINV_CLKBWRCLK 27_109
|
||||
BRAM_R.RAMB18_Y0.ZINV_ENARDEN 27_112
|
||||
BRAM_R.RAMB18_Y0.ZINV_ENBWREN 27_115
|
||||
BRAM_R.RAMB18_Y0.ZINV_RSTRAMARSTRAM 27_116
|
||||
BRAM_R.RAMB18_Y0.ZINV_RSTRAMB 27_117
|
||||
BRAM_R.RAMB18_Y0.ZINV_RSTREGARSTREG 27_120
|
||||
BRAM_R.RAMB18_Y0.ZINV_RSTREGB 27_123
|
||||
BRAM_R.RAMB18_Y1.INIT_A[0] 27_249
|
||||
BRAM_R.RAMB18_Y1.INIT_A[10] 27_305
|
||||
BRAM_R.RAMB18_Y1.INIT_A[11] 27_289
|
||||
BRAM_R.RAMB18_Y1.INIT_A[12] 27_273
|
||||
BRAM_R.RAMB18_Y1.INIT_A[1] 27_241
|
||||
BRAM_R.RAMB18_Y1.INIT_A[13] 27_257
|
||||
BRAM_R.RAMB18_Y1.INIT_A[14] 27_225
|
||||
BRAM_R.RAMB18_Y1.INIT_A[15] 27_209
|
||||
BRAM_R.RAMB18_Y1.INIT_A[16] 27_193
|
||||
BRAM_R.RAMB18_Y1.INIT_A[17] 27_177
|
||||
BRAM_R.RAMB18_Y1.INIT_A[2] 27_313
|
||||
BRAM_R.RAMB18_Y1.INIT_A[3] 27_297
|
||||
BRAM_R.RAMB18_Y1.INIT_A[4] 27_281
|
||||
BRAM_R.RAMB18_Y1.INIT_A[5] 27_265
|
||||
BRAM_R.RAMB18_Y1.INIT_A[6] 27_233
|
||||
BRAM_R.RAMB18_Y1.INIT_A[7] 27_217
|
||||
BRAM_R.RAMB18_Y1.INIT_A[8] 27_201
|
||||
BRAM_R.RAMB18_Y1.INIT_A[9] 27_185
|
||||
BRAM_R.RAMB18_Y1.INIT_B[0] 27_255
|
||||
BRAM_R.RAMB18_Y1.INIT_B[10] 27_311
|
||||
BRAM_R.RAMB18_Y1.INIT_B[11] 27_295
|
||||
BRAM_R.RAMB18_Y1.INIT_B[12] 27_279
|
||||
BRAM_R.RAMB18_Y1.INIT_B[1] 27_247
|
||||
BRAM_R.RAMB18_Y1.INIT_B[13] 27_263
|
||||
BRAM_R.RAMB18_Y1.INIT_B[14] 27_231
|
||||
BRAM_R.RAMB18_Y1.INIT_B[15] 27_215
|
||||
BRAM_R.RAMB18_Y1.INIT_B[16] 27_199
|
||||
BRAM_R.RAMB18_Y1.INIT_B[17] 27_183
|
||||
BRAM_R.RAMB18_Y1.INIT_B[2] 27_319
|
||||
BRAM_R.RAMB18_Y1.INIT_B[3] 27_303
|
||||
BRAM_R.RAMB18_Y1.INIT_B[4] 27_287
|
||||
BRAM_R.RAMB18_Y1.INIT_B[5] 27_271
|
||||
BRAM_R.RAMB18_Y1.INIT_B[6] 27_239
|
||||
BRAM_R.RAMB18_Y1.INIT_B[7] 27_223
|
||||
BRAM_R.RAMB18_Y1.INIT_B[8] 27_207
|
||||
BRAM_R.RAMB18_Y1.INIT_B[9] 27_191
|
||||
BRAM_R.RAMB18_Y1.READ_WIDTH_A_B0 27_285
|
||||
BRAM_R.RAMB18_Y1.READ_WIDTH_A_B1 27_284
|
||||
BRAM_R.RAMB18_Y1.READ_WIDTH_A_B2 27_283
|
||||
BRAM_R.RAMB18_Y1.READ_WIDTH_B_B0 27_277
|
||||
BRAM_R.RAMB18_Y1.READ_WIDTH_B_B1 27_276
|
||||
BRAM_R.RAMB18_Y1.READ_WIDTH_B_B2 27_275
|
||||
BRAM_R.RAMB18_Y1.SRVAL_A[0] 27_250
|
||||
BRAM_R.RAMB18_Y1.SRVAL_A[10] 27_306
|
||||
BRAM_R.RAMB18_Y1.SRVAL_A[11] 27_290
|
||||
BRAM_R.RAMB18_Y1.SRVAL_A[12] 27_274
|
||||
BRAM_R.RAMB18_Y1.SRVAL_A[1] 27_242
|
||||
BRAM_R.RAMB18_Y1.SRVAL_A[13] 27_258
|
||||
BRAM_R.RAMB18_Y1.SRVAL_A[14] 27_226
|
||||
BRAM_R.RAMB18_Y1.SRVAL_A[15] 27_210
|
||||
BRAM_R.RAMB18_Y1.SRVAL_A[16] 27_194
|
||||
BRAM_R.RAMB18_Y1.SRVAL_A[17] 27_178
|
||||
BRAM_R.RAMB18_Y1.SRVAL_A[2] 27_314
|
||||
BRAM_R.RAMB18_Y1.SRVAL_A[3] 27_298
|
||||
BRAM_R.RAMB18_Y1.SRVAL_A[4] 27_282
|
||||
BRAM_R.RAMB18_Y1.SRVAL_A[5] 27_266
|
||||
BRAM_R.RAMB18_Y1.SRVAL_A[6] 27_234
|
||||
BRAM_R.RAMB18_Y1.SRVAL_A[7] 27_218
|
||||
BRAM_R.RAMB18_Y1.SRVAL_A[8] 27_202
|
||||
BRAM_R.RAMB18_Y1.SRVAL_A[9] 27_186
|
||||
BRAM_R.RAMB18_Y1.SRVAL_B[0] 27_254
|
||||
BRAM_R.RAMB18_Y1.SRVAL_B[10] 27_310
|
||||
BRAM_R.RAMB18_Y1.SRVAL_B[11] 27_294
|
||||
BRAM_R.RAMB18_Y1.SRVAL_B[12] 27_278
|
||||
BRAM_R.RAMB18_Y1.SRVAL_B[1] 27_246
|
||||
BRAM_R.RAMB18_Y1.SRVAL_B[13] 27_262
|
||||
BRAM_R.RAMB18_Y1.SRVAL_B[14] 27_230
|
||||
BRAM_R.RAMB18_Y1.SRVAL_B[15] 27_214
|
||||
BRAM_R.RAMB18_Y1.SRVAL_B[16] 27_198
|
||||
BRAM_R.RAMB18_Y1.SRVAL_B[17] 27_182
|
||||
BRAM_R.RAMB18_Y1.SRVAL_B[2] 27_318
|
||||
BRAM_R.RAMB18_Y1.SRVAL_B[3] 27_302
|
||||
BRAM_R.RAMB18_Y1.SRVAL_B[4] 27_286
|
||||
BRAM_R.RAMB18_Y1.SRVAL_B[5] 27_270
|
||||
BRAM_R.RAMB18_Y1.SRVAL_B[6] 27_238
|
||||
BRAM_R.RAMB18_Y1.SRVAL_B[7] 27_222
|
||||
BRAM_R.RAMB18_Y1.SRVAL_B[8] 27_206
|
||||
BRAM_R.RAMB18_Y1.SRVAL_B[9] 27_190
|
||||
BRAM_R.RAMB18_Y1.WRITE_MODE_A_NO_CHANGE 27_256
|
||||
BRAM_R.RAMB18_Y1.WRITE_MODE_A_READ_FIRST 27_264
|
||||
BRAM_R.RAMB18_Y1.WRITE_MODE_B_NO_CHANGE 27_252
|
||||
BRAM_R.RAMB18_Y1.WRITE_MODE_B_READ_FIRST 27_253
|
||||
BRAM_R.RAMB18_Y1.WRITE_WIDTH_A_B0 27_269
|
||||
BRAM_R.RAMB18_Y1.WRITE_WIDTH_A_B1 27_268
|
||||
BRAM_R.RAMB18_Y1.WRITE_WIDTH_A_B2 27_267
|
||||
BRAM_R.RAMB18_Y1.WRITE_WIDTH_B_B0 27_261
|
||||
BRAM_R.RAMB18_Y1.WRITE_WIDTH_B_B1 27_260
|
||||
BRAM_R.RAMB18_Y1.WRITE_WIDTH_B_B2 27_259
|
||||
BRAM_R.RAMB18_Y1.ZINV_CLKARDCLK 27_213
|
||||
BRAM_R.RAMB18_Y1.ZINV_CLKBWRCLK 27_211
|
||||
BRAM_R.RAMB18_Y1.ZINV_ENARDEN 27_208
|
||||
BRAM_R.RAMB18_Y1.ZINV_ENBWREN 27_205
|
||||
BRAM_R.RAMB18_Y1.ZINV_RSTRAMARSTRAM 27_204
|
||||
BRAM_R.RAMB18_Y1.ZINV_RSTRAMB 27_203
|
||||
BRAM_R.RAMB18_Y1.ZINV_RSTREGARSTREG 27_200
|
||||
BRAM_R.RAMB18_Y1.ZINV_RSTREGB 27_197
|
||||
|
|
@ -202,6 +202,7 @@ CLBLL_L.SLICEL_X0.C5FF.ZINI 31_41
|
|||
CLBLL_L.SLICEL_X0.C5FF.ZRST 01_47
|
||||
CLBLL_L.SLICEL_X0.C5FFMUX.IN_A 31_45
|
||||
CLBLL_L.SLICEL_X0.C5FFMUX.IN_B 30_39
|
||||
CLBLL_L.SLICEL_X0.CARRY4.ACY0 !30_00 !30_02 !30_03 30_01 30_12 30_15 31_03
|
||||
CLBLL_L.SLICEL_X0.CARRY4.ACY0 30_15
|
||||
CLBLL_L.SLICEL_X0.CARRY4.BCY0 01_15
|
||||
CLBLL_L.SLICEL_X0.CARRY4.CCY0 30_48
|
||||
|
|
@ -602,6 +603,7 @@ CLBLL_L.SLICEL_X1.C5FF.ZRST 00_44
|
|||
CLBLL_L.SLICEL_X1.C5FFMUX.IN_A 31_44
|
||||
CLBLL_L.SLICEL_X1.C5FFMUX.IN_B 31_39
|
||||
CLBLL_L.SLICEL_X1.CARRY4.ACY0 31_14
|
||||
CLBLL_L.SLICEL_X1.CARRY4.BCY0 !31_24 !31_25 !31_26 00_08 31_27 31_29 31_30
|
||||
CLBLL_L.SLICEL_X1.CARRY4.BCY0 00_08
|
||||
CLBLL_L.SLICEL_X1.CARRY4.CCY0 31_48
|
||||
CLBLL_L.SLICEL_X1.CARRY4.DCY0 31_49
|
||||
|
|
|
|||
|
|
@ -202,6 +202,7 @@ CLBLL_R.SLICEL_X0.C5FF.ZINI 31_41
|
|||
CLBLL_R.SLICEL_X0.C5FF.ZRST 01_47
|
||||
CLBLL_R.SLICEL_X0.C5FFMUX.IN_A 31_45
|
||||
CLBLL_R.SLICEL_X0.C5FFMUX.IN_B 30_39
|
||||
CLBLL_R.SLICEL_X0.CARRY4.ACY0 !30_00 !30_02 !30_03 30_01 30_12 30_15 31_03
|
||||
CLBLL_R.SLICEL_X0.CARRY4.ACY0 30_15
|
||||
CLBLL_R.SLICEL_X0.CARRY4.BCY0 01_15
|
||||
CLBLL_R.SLICEL_X0.CARRY4.CCY0 30_48
|
||||
|
|
@ -602,6 +603,7 @@ CLBLL_R.SLICEL_X1.C5FF.ZRST 00_44
|
|||
CLBLL_R.SLICEL_X1.C5FFMUX.IN_A 31_44
|
||||
CLBLL_R.SLICEL_X1.C5FFMUX.IN_B 31_39
|
||||
CLBLL_R.SLICEL_X1.CARRY4.ACY0 31_14
|
||||
CLBLL_R.SLICEL_X1.CARRY4.BCY0 !31_24 !31_25 !31_26 00_08 31_27 31_29 31_30
|
||||
CLBLL_R.SLICEL_X1.CARRY4.BCY0 00_08
|
||||
CLBLL_R.SLICEL_X1.CARRY4.CCY0 31_48
|
||||
CLBLL_R.SLICEL_X1.CARRY4.DCY0 31_49
|
||||
|
|
|
|||
|
|
@ -195,6 +195,7 @@ CLBLM_L.SLICEL_X1.C5FF.ZRST 00_44
|
|||
CLBLM_L.SLICEL_X1.C5FFMUX.IN_A 31_44
|
||||
CLBLM_L.SLICEL_X1.C5FFMUX.IN_B 31_39
|
||||
CLBLM_L.SLICEL_X1.CARRY4.ACY0 31_14
|
||||
CLBLM_L.SLICEL_X1.CARRY4.BCY0 !31_24 !31_25 !31_26 00_08 31_27 31_29 31_30
|
||||
CLBLM_L.SLICEL_X1.CARRY4.BCY0 00_08
|
||||
CLBLM_L.SLICEL_X1.CARRY4.CCY0 31_48
|
||||
CLBLM_L.SLICEL_X1.CARRY4.DCY0 31_49
|
||||
|
|
@ -408,6 +409,7 @@ CLBLM_L.SLICEM_X0.AFFMUX.F7 !30_02 !30_03 30_00 30_01
|
|||
CLBLM_L.SLICEM_X0.AFFMUX.O5 !30_01 !30_02 30_00 30_03
|
||||
CLBLM_L.SLICEM_X0.AFFMUX.O6 !30_00 !30_01 !30_02 30_03
|
||||
CLBLM_L.SLICEM_X0.AFFMUX.XOR !30_00 !30_01 !30_03 30_02
|
||||
CLBLM_L.SLICEM_X0.ALUT.DI1MUX.AI 00_00
|
||||
CLBLM_L.SLICEM_X0.ALUT.INIT[00] 34_15
|
||||
CLBLM_L.SLICEM_X0.ALUT.INIT[01] 35_15
|
||||
CLBLM_L.SLICEM_X0.ALUT.INIT[02] 34_14
|
||||
|
|
@ -507,6 +509,7 @@ CLBLM_L.SLICEM_X0.BFFMUX.F8 !30_24 !30_25 30_26 30_27
|
|||
CLBLM_L.SLICEM_X0.BFFMUX.O5 !30_25 !30_26 30_24 30_27
|
||||
CLBLM_L.SLICEM_X0.BFFMUX.O6 !30_25 !30_26 !30_27 30_24
|
||||
CLBLM_L.SLICEM_X0.BFFMUX.XOR !30_24 !30_26 !30_27 30_25
|
||||
CLBLM_L.SLICEM_X0.BLUT.DI1MUX.BI 00_20
|
||||
CLBLM_L.SLICEM_X0.BLUT.INIT[00] 34_31
|
||||
CLBLM_L.SLICEM_X0.BLUT.INIT[01] 35_31
|
||||
CLBLM_L.SLICEM_X0.BLUT.INIT[02] 34_30
|
||||
|
|
@ -591,6 +594,7 @@ CLBLM_L.SLICEM_X0.C5FF.ZINI 31_41
|
|||
CLBLM_L.SLICEM_X0.C5FF.ZRST 01_47
|
||||
CLBLM_L.SLICEM_X0.C5FFMUX.IN_A 31_45
|
||||
CLBLM_L.SLICEM_X0.C5FFMUX.IN_B 30_39
|
||||
CLBLM_L.SLICEM_X0.CARRY4.ACY0 !30_00 !30_02 !30_03 30_01 30_12 30_15 31_03
|
||||
CLBLM_L.SLICEM_X0.CARRY4.ACY0 30_15
|
||||
CLBLM_L.SLICEM_X0.CARRY4.BCY0 01_15
|
||||
CLBLM_L.SLICEM_X0.CARRY4.CCY0 30_48
|
||||
|
|
@ -612,6 +616,7 @@ CLBLM_L.SLICEM_X0.CFFMUX.O5 !30_36 !30_37 30_35 30_38
|
|||
CLBLM_L.SLICEM_X0.CFFMUX.O6 !30_35 !30_36 !30_37 30_38
|
||||
CLBLM_L.SLICEM_X0.CFFMUX.XOR !30_35 !30_36 !30_38 30_37
|
||||
CLBLM_L.SLICEM_X0.CLKINV 01_51
|
||||
CLBLM_L.SLICEM_X0.CLUT.DI1MUX.CI 01_43
|
||||
CLBLM_L.SLICEM_X0.CLUT.INIT[00] 34_47
|
||||
CLBLM_L.SLICEM_X0.CLUT.INIT[01] 35_47
|
||||
CLBLM_L.SLICEM_X0.CLUT.INIT[02] 34_46
|
||||
|
|
|
|||
|
|
@ -195,6 +195,7 @@ CLBLM_R.SLICEL_X1.C5FF.ZRST 00_44
|
|||
CLBLM_R.SLICEL_X1.C5FFMUX.IN_A 31_44
|
||||
CLBLM_R.SLICEL_X1.C5FFMUX.IN_B 31_39
|
||||
CLBLM_R.SLICEL_X1.CARRY4.ACY0 31_14
|
||||
CLBLM_R.SLICEL_X1.CARRY4.BCY0 !31_24 !31_25 !31_26 00_08 31_27 31_29 31_30
|
||||
CLBLM_R.SLICEL_X1.CARRY4.BCY0 00_08
|
||||
CLBLM_R.SLICEL_X1.CARRY4.CCY0 31_48
|
||||
CLBLM_R.SLICEL_X1.CARRY4.DCY0 31_49
|
||||
|
|
@ -408,6 +409,7 @@ CLBLM_R.SLICEM_X0.AFFMUX.F7 !30_02 !30_03 30_00 30_01
|
|||
CLBLM_R.SLICEM_X0.AFFMUX.O5 !30_01 !30_02 30_00 30_03
|
||||
CLBLM_R.SLICEM_X0.AFFMUX.O6 !30_00 !30_01 !30_02 30_03
|
||||
CLBLM_R.SLICEM_X0.AFFMUX.XOR !30_00 !30_01 !30_03 30_02
|
||||
CLBLM_R.SLICEM_X0.ALUT.DI1MUX.AI 00_00
|
||||
CLBLM_R.SLICEM_X0.ALUT.INIT[00] 34_15
|
||||
CLBLM_R.SLICEM_X0.ALUT.INIT[01] 35_15
|
||||
CLBLM_R.SLICEM_X0.ALUT.INIT[02] 34_14
|
||||
|
|
@ -507,6 +509,7 @@ CLBLM_R.SLICEM_X0.BFFMUX.F8 !30_24 !30_25 30_26 30_27
|
|||
CLBLM_R.SLICEM_X0.BFFMUX.O5 !30_25 !30_26 30_24 30_27
|
||||
CLBLM_R.SLICEM_X0.BFFMUX.O6 !30_25 !30_26 !30_27 30_24
|
||||
CLBLM_R.SLICEM_X0.BFFMUX.XOR !30_24 !30_26 !30_27 30_25
|
||||
CLBLM_R.SLICEM_X0.BLUT.DI1MUX.BI 00_20
|
||||
CLBLM_R.SLICEM_X0.BLUT.INIT[00] 34_31
|
||||
CLBLM_R.SLICEM_X0.BLUT.INIT[01] 35_31
|
||||
CLBLM_R.SLICEM_X0.BLUT.INIT[02] 34_30
|
||||
|
|
@ -591,6 +594,7 @@ CLBLM_R.SLICEM_X0.C5FF.ZINI 31_41
|
|||
CLBLM_R.SLICEM_X0.C5FF.ZRST 01_47
|
||||
CLBLM_R.SLICEM_X0.C5FFMUX.IN_A 31_45
|
||||
CLBLM_R.SLICEM_X0.C5FFMUX.IN_B 30_39
|
||||
CLBLM_R.SLICEM_X0.CARRY4.ACY0 !30_00 !30_02 !30_03 30_01 30_12 30_15 31_03
|
||||
CLBLM_R.SLICEM_X0.CARRY4.ACY0 30_15
|
||||
CLBLM_R.SLICEM_X0.CARRY4.BCY0 01_15
|
||||
CLBLM_R.SLICEM_X0.CARRY4.CCY0 30_48
|
||||
|
|
@ -612,6 +616,7 @@ CLBLM_R.SLICEM_X0.CFFMUX.O5 !30_36 !30_37 30_35 30_38
|
|||
CLBLM_R.SLICEM_X0.CFFMUX.O6 !30_35 !30_36 !30_37 30_38
|
||||
CLBLM_R.SLICEM_X0.CFFMUX.XOR !30_35 !30_36 !30_38 30_37
|
||||
CLBLM_R.SLICEM_X0.CLKINV 01_51
|
||||
CLBLM_R.SLICEM_X0.CLUT.DI1MUX.CI 01_43
|
||||
CLBLM_R.SLICEM_X0.CLUT.INIT[00] 34_47
|
||||
CLBLM_R.SLICEM_X0.CLUT.INIT[01] 35_47
|
||||
CLBLM_R.SLICEM_X0.CLUT.INIT[02] 34_46
|
||||
|
|
|
|||
|
|
@ -752,6 +752,7 @@ INT_L.FAN_ALT7.EL1END2 !22_32 17_32 23_32 24_32 25_32
|
|||
INT_L.FAN_ALT7.ER1END1 !23_32 16_32 22_32 24_32 25_32
|
||||
INT_L.FAN_ALT7.FAN_BOUNCE3 !22_32 20_32 23_32 24_32 25_32
|
||||
INT_L.FAN_ALT7.FAN_BOUNCE5 !23_32 20_32 22_32 24_32 25_32
|
||||
INT_L.FAN_ALT7.GFAN1 !22_32 !23_32 !24_32 01_39 21_32 25_32
|
||||
INT_L.FAN_ALT7.GFAN1 !22_32 !23_32 !24_32 21_32 25_32
|
||||
INT_L.FAN_ALT7.LOGIC_OUTS_L14 !22_32 21_32 23_32 24_32 25_32
|
||||
INT_L.FAN_ALT7.LOGIC_OUTS_L2 !23_32 21_32 22_32 24_32 25_32
|
||||
|
|
|
|||
|
|
@ -1,12 +1,14 @@
|
|||
export XRAY_DATABASE="artix7"
|
||||
export XRAY_PART="xc7a50tfgg484-1"
|
||||
export XRAY_ROI="SLICE_X12Y100:SLICE_X27Y149"
|
||||
export XRAY_ROI_FRAMES="0x00000000:0xffffffff"
|
||||
|
||||
# Leave some CLBs to the left to allow easy ROI entering
|
||||
export XRAY_ROI="SLICE_X8Y100:SLICE_X27Y149 RAMB18_X0Y40:RAMB18_X0Y59 RAMB36_X0Y20:RAMB36_X0Y29 DSP48_X0Y40:DSP48_X0Y59"
|
||||
export XRAY_ROI_GRID_X1="18"
|
||||
export XRAY_ROI_GRID_X2="47"
|
||||
# All CLB's in part, all BRAM's in part, all DSP's in part.
|
||||
export XRAY_ROI="SLICE_X0Y0:SLICE_X65Y99 SLICE_X0Y100:SLICE_X57Y149 RAMB18_X0Y0:RAMB18_X1Y59 RAMB36_X0Y0:RAMB36_X1Y29 RAMB18_X2Y0:RAMB18_X2Y39 RAMB36_X2Y0:RAMB36_X2Y19 DSP48_X0Y0:DSP48_X1Y59"
|
||||
|
||||
# Most of CMT X0Y2.
|
||||
export XRAY_ROI_GRID_X1="9"
|
||||
export XRAY_ROI_GRID_X2="58"
|
||||
# Include VBRK / VTERM
|
||||
export XRAY_ROI_GRID_Y1="0"
|
||||
export XRAY_ROI_GRID_Y2="52"
|
||||
|
||||
|
|
|
|||
|
|
@ -1,39 +1,39 @@
|
|||
{
|
||||
"type": "BSCAN",
|
||||
"site_pips": {},
|
||||
"site_pins": {
|
||||
"TDI": {
|
||||
"direction": "OUT"
|
||||
"site_pins": {
|
||||
"CAPTURE": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TDO": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"UPDATE": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"RESET": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"RUNTEST": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SHIFT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TMS": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TDI": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TCK": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SEL": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DRCK": {
|
||||
"direction": "OUT"
|
||||
}
|
||||
},
|
||||
"SEL": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CAPTURE": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SHIFT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TDO": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"RESET": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TCK": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"UPDATE": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DRCK": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"RUNTEST": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TMS": {
|
||||
"direction": "OUT"
|
||||
}
|
||||
}
|
||||
}
|
||||
"site_pips": {},
|
||||
"type": "BSCAN"
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,82 +1,82 @@
|
|||
{
|
||||
"type": "BUFGCTRL",
|
||||
"site_pips": {
|
||||
"CE0INV:CE0": {
|
||||
"to_pin": "OUT",
|
||||
"from_pin": "CE0"
|
||||
"site_pins": {
|
||||
"IGNORE1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"I1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CE1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"S1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CE0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"S0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"I0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"IGNORE0": {
|
||||
"direction": "IN"
|
||||
}
|
||||
},
|
||||
"S0INV:S0_B": {
|
||||
"to_pin": "OUT",
|
||||
"from_pin": "S0_B"
|
||||
"site_pips": {
|
||||
"IGNORE0INV:IGNORE0": {
|
||||
"from_pin": "IGNORE0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"IGNORE1INV:IGNORE1_B": {
|
||||
"from_pin": "IGNORE1_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"S0INV:S0_B": {
|
||||
"from_pin": "S0_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"IGNORE1INV:IGNORE1": {
|
||||
"from_pin": "IGNORE1",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"S1INV:S1_B": {
|
||||
"from_pin": "S1_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"CE1INV:CE1": {
|
||||
"from_pin": "CE1",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"CE0INV:CE0_B": {
|
||||
"from_pin": "CE0_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"CE1INV:CE1_B": {
|
||||
"from_pin": "CE1_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"S1INV:S1": {
|
||||
"from_pin": "S1",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"S0INV:S0": {
|
||||
"from_pin": "S0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"CE0INV:CE0": {
|
||||
"from_pin": "CE0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"IGNORE0INV:IGNORE0_B": {
|
||||
"from_pin": "IGNORE0_B",
|
||||
"to_pin": "OUT"
|
||||
}
|
||||
},
|
||||
"CE1INV:CE1_B": {
|
||||
"to_pin": "OUT",
|
||||
"from_pin": "CE1_B"
|
||||
},
|
||||
"IGNORE0INV:IGNORE0_B": {
|
||||
"to_pin": "OUT",
|
||||
"from_pin": "IGNORE0_B"
|
||||
},
|
||||
"CE1INV:CE1": {
|
||||
"to_pin": "OUT",
|
||||
"from_pin": "CE1"
|
||||
},
|
||||
"S0INV:S0": {
|
||||
"to_pin": "OUT",
|
||||
"from_pin": "S0"
|
||||
},
|
||||
"IGNORE1INV:IGNORE1": {
|
||||
"to_pin": "OUT",
|
||||
"from_pin": "IGNORE1"
|
||||
},
|
||||
"S1INV:S1": {
|
||||
"to_pin": "OUT",
|
||||
"from_pin": "S1"
|
||||
},
|
||||
"IGNORE1INV:IGNORE1_B": {
|
||||
"to_pin": "OUT",
|
||||
"from_pin": "IGNORE1_B"
|
||||
},
|
||||
"IGNORE0INV:IGNORE0": {
|
||||
"to_pin": "OUT",
|
||||
"from_pin": "IGNORE0"
|
||||
},
|
||||
"S1INV:S1_B": {
|
||||
"to_pin": "OUT",
|
||||
"from_pin": "S1_B"
|
||||
},
|
||||
"CE0INV:CE0_B": {
|
||||
"to_pin": "OUT",
|
||||
"from_pin": "CE0_B"
|
||||
}
|
||||
},
|
||||
"site_pins": {
|
||||
"O": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"I0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"IGNORE0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"IGNORE1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"S0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"I1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CE1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CE0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"S1": {
|
||||
"direction": "IN"
|
||||
}
|
||||
}
|
||||
}
|
||||
"type": "BUFGCTRL"
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,24 +1,24 @@
|
|||
{
|
||||
"type": "BUFHCE",
|
||||
"site_pips": {
|
||||
"CEINV:CE_B": {
|
||||
"to_pin": "OUT",
|
||||
"from_pin": "CE_B"
|
||||
"site_pins": {
|
||||
"O": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CE": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"I": {
|
||||
"direction": "IN"
|
||||
}
|
||||
},
|
||||
"CEINV:CE": {
|
||||
"to_pin": "OUT",
|
||||
"from_pin": "CE"
|
||||
}
|
||||
},
|
||||
"site_pins": {
|
||||
"I": {
|
||||
"direction": "IN"
|
||||
"site_pips": {
|
||||
"CEINV:CE_B": {
|
||||
"from_pin": "CE_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"CEINV:CE": {
|
||||
"from_pin": "CE",
|
||||
"to_pin": "OUT"
|
||||
}
|
||||
},
|
||||
"CE": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O": {
|
||||
"direction": "OUT"
|
||||
}
|
||||
}
|
||||
}
|
||||
"type": "BUFHCE"
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,12 +1,12 @@
|
|||
{
|
||||
"type": "BUFIO",
|
||||
"site_pips": {},
|
||||
"site_pins": {
|
||||
"I": {
|
||||
"direction": "IN"
|
||||
"site_pins": {
|
||||
"O": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"I": {
|
||||
"direction": "IN"
|
||||
}
|
||||
},
|
||||
"O": {
|
||||
"direction": "OUT"
|
||||
}
|
||||
}
|
||||
}
|
||||
"site_pips": {},
|
||||
"type": "BUFIO"
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,24 +1,24 @@
|
|||
{
|
||||
"type": "BUFMRCE",
|
||||
"site_pips": {
|
||||
"CEINV:CE_B": {
|
||||
"to_pin": "OUT",
|
||||
"from_pin": "CE_B"
|
||||
"site_pins": {
|
||||
"O": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CE": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"I": {
|
||||
"direction": "IN"
|
||||
}
|
||||
},
|
||||
"CEINV:CE": {
|
||||
"to_pin": "OUT",
|
||||
"from_pin": "CE"
|
||||
}
|
||||
},
|
||||
"site_pins": {
|
||||
"I": {
|
||||
"direction": "IN"
|
||||
"site_pips": {
|
||||
"CEINV:CE_B": {
|
||||
"from_pin": "CE_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"CEINV:CE": {
|
||||
"from_pin": "CE",
|
||||
"to_pin": "OUT"
|
||||
}
|
||||
},
|
||||
"CE": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O": {
|
||||
"direction": "OUT"
|
||||
}
|
||||
}
|
||||
}
|
||||
"type": "BUFMRCE"
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,18 +1,18 @@
|
|||
{
|
||||
"type": "BUFR",
|
||||
"site_pips": {},
|
||||
"site_pins": {
|
||||
"I": {
|
||||
"direction": "IN"
|
||||
"site_pins": {
|
||||
"CLR": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CE": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"I": {
|
||||
"direction": "IN"
|
||||
}
|
||||
},
|
||||
"CE": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CLR": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O": {
|
||||
"direction": "OUT"
|
||||
}
|
||||
}
|
||||
}
|
||||
"site_pips": {},
|
||||
"type": "BUFR"
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,12 +1,12 @@
|
|||
{
|
||||
"type": "CAPTURE",
|
||||
"site_pips": {},
|
||||
"site_pins": {
|
||||
"CAP": {
|
||||
"direction": "IN"
|
||||
"site_pins": {
|
||||
"CLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CAP": {
|
||||
"direction": "IN"
|
||||
}
|
||||
},
|
||||
"CLK": {
|
||||
"direction": "IN"
|
||||
}
|
||||
}
|
||||
}
|
||||
"site_pips": {},
|
||||
"type": "CAPTURE"
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,12 +1,12 @@
|
|||
{
|
||||
"type": "DCIRESET",
|
||||
"site_pips": {},
|
||||
"site_pins": {
|
||||
"RST": {
|
||||
"direction": "IN"
|
||||
"site_pins": {
|
||||
"LOCKED": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"RST": {
|
||||
"direction": "IN"
|
||||
}
|
||||
},
|
||||
"LOCKED": {
|
||||
"direction": "OUT"
|
||||
}
|
||||
}
|
||||
}
|
||||
"site_pips": {},
|
||||
"type": "DCIRESET"
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,21 +1,21 @@
|
|||
{
|
||||
"type": "DNA_PORT",
|
||||
"site_pips": {},
|
||||
"site_pins": {
|
||||
"SHIFT": {
|
||||
"direction": "IN"
|
||||
"site_pins": {
|
||||
"CLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DOUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"READ": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SHIFT": {
|
||||
"direction": "IN"
|
||||
}
|
||||
},
|
||||
"READ": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DOUT": {
|
||||
"direction": "OUT"
|
||||
}
|
||||
}
|
||||
}
|
||||
"site_pips": {},
|
||||
"type": "DNA_PORT"
|
||||
}
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,102 +1,102 @@
|
|||
{
|
||||
"type": "EFUSE_USR",
|
||||
"site_pips": {},
|
||||
"site_pins": {
|
||||
"EFUSEUSR19": {
|
||||
"direction": "OUT"
|
||||
"site_pins": {
|
||||
"EFUSEUSR7": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR12": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR19": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR20": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR13": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR29": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR14": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR9": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR15": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR11": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR23": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR26": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR30": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR24": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR28": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR10": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR21": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR5": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR22": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR6": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR27": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR17": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR8": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR18": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR31": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR16": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR25": {
|
||||
"direction": "OUT"
|
||||
}
|
||||
},
|
||||
"EFUSEUSR23": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR7": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR5": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR11": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR22": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR27": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR9": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR24": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR8": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR20": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR13": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR26": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR31": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR10": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR14": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR30": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR21": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR28": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR6": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR15": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR18": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR25": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR29": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR16": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR17": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR12": {
|
||||
"direction": "OUT"
|
||||
}
|
||||
}
|
||||
}
|
||||
"site_pips": {},
|
||||
"type": "EFUSE_USR"
|
||||
}
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,171 +1,171 @@
|
|||
{
|
||||
"type": "FRAME_ECC",
|
||||
"site_pips": {},
|
||||
"site_pins": {
|
||||
"FAR18": {
|
||||
"direction": "OUT"
|
||||
"site_pins": {
|
||||
"SYNDROME1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNBIT2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR24": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNDROME2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR21": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR23": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNDROME10": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNBIT1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNDROME7": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR13": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNWORD5": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR8": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNBIT4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNWORD0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNDROMEVALID": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR14": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR7": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNWORD1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"ECCERROR": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR12": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR18": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNWORD4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR10": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNWORD2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNWORD6": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR9": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR11": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR5": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"ECCERRORSINGLE": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNDROME11": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNDROME12": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR15": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR16": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNDROME9": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNDROME3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNBIT0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR19": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNDROME8": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR6": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNDROME4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR17": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR22": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNWORD3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNDROME5": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR25": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNBIT3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR20": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNDROME0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNDROME6": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CRCERROR": {
|
||||
"direction": "OUT"
|
||||
}
|
||||
},
|
||||
"SYNWORD3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR20": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNDROME5": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR6": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR10": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNDROME12": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNDROME8": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR15": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR14": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNDROME1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNWORD6": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNWORD1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNBIT4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR23": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CRCERROR": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNDROMEVALID": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNBIT3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNDROME2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNDROME10": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR13": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR21": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNBIT2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR22": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"ECCERROR": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR11": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR16": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNWORD5": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNWORD4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR7": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNDROME0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNDROME3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR12": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNDROME7": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR5": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNDROME9": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNWORD2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR24": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR9": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNWORD0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR8": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR17": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNBIT0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR25": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNDROME6": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNDROME4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNDROME11": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"ECCERRORSINGLE": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNBIT1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR19": {
|
||||
"direction": "OUT"
|
||||
}
|
||||
}
|
||||
}
|
||||
"site_pips": {},
|
||||
"type": "FRAME_ECC"
|
||||
}
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -1,33 +1,33 @@
|
|||
{
|
||||
"type": "IBUFDS_GTE2",
|
||||
"site_pips": {
|
||||
"CLKTESTSIGINV:CLKTESTSIG_B": {
|
||||
"to_pin": "OUT",
|
||||
"from_pin": "CLKTESTSIG_B"
|
||||
"site_pins": {
|
||||
"CLKTESTSIG": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ODIV2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CEB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"I": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"IB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O": {
|
||||
"direction": "OUT"
|
||||
}
|
||||
},
|
||||
"CLKTESTSIGINV:CLKTESTSIG": {
|
||||
"to_pin": "OUT",
|
||||
"from_pin": "CLKTESTSIG"
|
||||
}
|
||||
},
|
||||
"site_pins": {
|
||||
"O": {
|
||||
"direction": "OUT"
|
||||
"site_pips": {
|
||||
"CLKTESTSIGINV:CLKTESTSIG": {
|
||||
"from_pin": "CLKTESTSIG",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"CLKTESTSIGINV:CLKTESTSIG_B": {
|
||||
"from_pin": "CLKTESTSIG_B",
|
||||
"to_pin": "OUT"
|
||||
}
|
||||
},
|
||||
"IB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CLKTESTSIG": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"I": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CEB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ODIV2": {
|
||||
"direction": "OUT"
|
||||
}
|
||||
}
|
||||
}
|
||||
"type": "IBUFDS_GTE2"
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,207 +1,207 @@
|
|||
{
|
||||
"type": "ICAP",
|
||||
"site_pips": {},
|
||||
"site_pins": {
|
||||
"CSIB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"I0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O26": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"O4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"I3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"I22": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O16": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"I24": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O9": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"I11": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O7": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"O3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"O13": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"O23": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"O6": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"O10": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"O11": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"RDWRB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"I28": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"I8": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O27": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"I9": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"I7": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O8": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"I12": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"I29": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O24": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"O31": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"O30": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"I21": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"I20": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"I31": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"I30": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"I1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"I23": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"I26": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"O0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"O12": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"O5": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"O29": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"O2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"I19": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O25": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"I6": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"I10": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O21": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"O18": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"I15": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O20": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"O17": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"I18": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"I2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O28": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"I17": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"I5": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O22": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"I13": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O14": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"I4": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"I25": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"I16": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O15": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"O19": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"I27": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"I14": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CLK": {
|
||||
"direction": "IN"
|
||||
}
|
||||
}
|
||||
}
|
||||
"site_pins": {
|
||||
"O19": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"O5": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"I9": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"I23": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O24": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"I30": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"I15": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O13": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"I2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"O27": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"I31": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"I26": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O30": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"RDWRB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"I3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"I11": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"I1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O9": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"I20": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O15": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"I21": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"I16": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O12": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"O17": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"O0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"I8": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"I24": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"I25": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CSIB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O20": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"O29": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"O31": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"O7": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"O8": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"O28": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"I27": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O16": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"I17": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"I18": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"I12": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O25": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"I10": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"I7": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"I13": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O22": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"O23": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"I29": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"I28": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O10": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"O11": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"O21": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"O6": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"I22": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"I14": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"I6": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O26": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"I19": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"I4": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"I5": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O18": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"I0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O14": {
|
||||
"direction": "OUT"
|
||||
}
|
||||
},
|
||||
"site_pips": {},
|
||||
"type": "ICAP"
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,27 +1,27 @@
|
|||
{
|
||||
"type": "IDELAYCTRL",
|
||||
"site_pips": {},
|
||||
"site_pins": {
|
||||
"UPPULSEOUT": {
|
||||
"direction": "OUT"
|
||||
"site_pins": {
|
||||
"OUTN1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"RST": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"UPPULSEOUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DNPULSEOUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"OUTN65": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"REFCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"RDY": {
|
||||
"direction": "OUT"
|
||||
}
|
||||
},
|
||||
"RST": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"REFCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DNPULSEOUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"RDY": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"OUTN1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"OUTN65": {
|
||||
"direction": "OUT"
|
||||
}
|
||||
}
|
||||
}
|
||||
"site_pips": {},
|
||||
"type": "IDELAYCTRL"
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,100 +1,100 @@
|
|||
{
|
||||
"type": "IDELAYE2",
|
||||
"site_pips": {
|
||||
"CINV:C_B": {
|
||||
"to_pin": "OUT",
|
||||
"from_pin": "C_B"
|
||||
"site_pins": {
|
||||
"IFDLY1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DATAIN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"INC": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"C": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CNTVALUEOUT2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"IFDLY2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CNTVALUEOUT1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"LDPIPEEN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"IFDLY0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CNTVALUEIN1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"LD": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"IDATAIN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CNTVALUEOUT4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CNTVALUEOUT0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CE": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CNTVALUEIN2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CNTVALUEIN0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CINVCTRL": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CNTVALUEOUT3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CNTVALUEIN4": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DATAOUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"REGRST": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CNTVALUEIN3": {
|
||||
"direction": "IN"
|
||||
}
|
||||
},
|
||||
"IDATAININV:IDATAIN_B": {
|
||||
"to_pin": "OUT",
|
||||
"from_pin": "IDATAIN_B"
|
||||
"site_pips": {
|
||||
"IDATAININV:IDATAIN_B": {
|
||||
"from_pin": "IDATAIN_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"DATAININV:DATAIN": {
|
||||
"from_pin": "DATAIN",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"CINV:C_B": {
|
||||
"from_pin": "C_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"IDATAININV:IDATAIN": {
|
||||
"from_pin": "IDATAIN",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"CINV:C": {
|
||||
"from_pin": "C",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"DATAININV:DATAIN_B": {
|
||||
"from_pin": "DATAIN_B",
|
||||
"to_pin": "OUT"
|
||||
}
|
||||
},
|
||||
"DATAININV:DATAIN": {
|
||||
"to_pin": "OUT",
|
||||
"from_pin": "DATAIN"
|
||||
},
|
||||
"IDATAININV:IDATAIN": {
|
||||
"to_pin": "OUT",
|
||||
"from_pin": "IDATAIN"
|
||||
},
|
||||
"CINV:C": {
|
||||
"to_pin": "OUT",
|
||||
"from_pin": "C"
|
||||
},
|
||||
"DATAININV:DATAIN_B": {
|
||||
"to_pin": "OUT",
|
||||
"from_pin": "DATAIN_B"
|
||||
}
|
||||
},
|
||||
"site_pins": {
|
||||
"LDPIPEEN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CNTVALUEIN4": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"IDATAIN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CNTVALUEOUT0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATAOUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CNTVALUEIN3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"REGRST": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"IFDLY1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CNTVALUEOUT2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CINVCTRL": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"INC": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CE": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CNTVALUEIN1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"LD": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CNTVALUEOUT4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CNTVALUEOUT3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATAIN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CNTVALUEIN2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"C": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CNTVALUEOUT1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CNTVALUEIN0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"IFDLY0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"IFDLY2": {
|
||||
"direction": "IN"
|
||||
}
|
||||
}
|
||||
}
|
||||
"type": "IDELAYE2"
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,208 +1,208 @@
|
|||
{
|
||||
"type": "ILOGICE3",
|
||||
"site_pips": {
|
||||
"CLKBINV:CLKB_B": {
|
||||
"to_pin": "OUT",
|
||||
"from_pin": "CLKB_B"
|
||||
"site_pins": {
|
||||
"TFB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"OFB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"BITSLIP": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CLKDIV": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"REV": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SHIFTOUT1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q5": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SHIFTIN1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SHIFTOUT2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DYNCLKSEL": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CLKDIVP": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CE1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CLKB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q8": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q6": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DYNCLKDIVSEL": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"OCLKB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SHIFTIN2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SR": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CE2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q7": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DYNCLKDIVPSEL": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DDLY": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"OCLK": {
|
||||
"direction": "IN"
|
||||
}
|
||||
},
|
||||
"CLKINV:CLK": {
|
||||
"to_pin": "OUT",
|
||||
"from_pin": "CLK"
|
||||
"site_pips": {
|
||||
"IFFDELMUXE3:1": {
|
||||
"from_pin": "1",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"CE1USED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"CLKBINV:CLKB_B": {
|
||||
"from_pin": "CLKB_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"DINV:D_B": {
|
||||
"from_pin": "D_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"CLKINV:CLK": {
|
||||
"from_pin": "CLK",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"ZHOLD_FABRIC_INV:D_B": {
|
||||
"from_pin": "D_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"CLKBINV:CLKB": {
|
||||
"from_pin": "CLKB",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"SRUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"ZHOLD_IFF_INV:D": {
|
||||
"from_pin": "D",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"IFFDELMUXE3:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"IDELMUXE3:2": {
|
||||
"from_pin": "2",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"D2OFFBYP_SEL:T": {
|
||||
"from_pin": "T",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"DINV:D": {
|
||||
"from_pin": "D",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"ZHOLD_FABRIC_INV:D": {
|
||||
"from_pin": "D",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"IMUX:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"REVUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"IMUX:1": {
|
||||
"from_pin": "1",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"IDELMUXE3:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"D2OFFBYP_SEL:GND": {
|
||||
"from_pin": "GND",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"D2OBYP_SEL:GND": {
|
||||
"from_pin": "GND",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"IFFMUX:1": {
|
||||
"from_pin": "1",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"CLKINV:CLK_B": {
|
||||
"from_pin": "CLK_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"IFFDELMUXE3:2": {
|
||||
"from_pin": "2",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"IFFMUX:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"ZHOLD_IFF_INV:D_B": {
|
||||
"from_pin": "D_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"IDELMUXE3:1": {
|
||||
"from_pin": "1",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"D2OBYP_SEL:T": {
|
||||
"from_pin": "T",
|
||||
"to_pin": "OUT"
|
||||
}
|
||||
},
|
||||
"ZHOLD_IFF_INV:D": {
|
||||
"to_pin": "OUT",
|
||||
"from_pin": "D"
|
||||
},
|
||||
"ZHOLD_FABRIC_INV:D_B": {
|
||||
"to_pin": "OUT",
|
||||
"from_pin": "D_B"
|
||||
},
|
||||
"D2OBYP_SEL:T": {
|
||||
"to_pin": "OUT",
|
||||
"from_pin": "T"
|
||||
},
|
||||
"CLKINV:CLK_B": {
|
||||
"to_pin": "OUT",
|
||||
"from_pin": "CLK_B"
|
||||
},
|
||||
"IDELMUXE3:2": {
|
||||
"to_pin": "OUT",
|
||||
"from_pin": "2"
|
||||
},
|
||||
"IFFMUX:0": {
|
||||
"to_pin": "OUT",
|
||||
"from_pin": "0"
|
||||
},
|
||||
"D2OFFBYP_SEL:T": {
|
||||
"to_pin": "OUT",
|
||||
"from_pin": "T"
|
||||
},
|
||||
"IFFMUX:1": {
|
||||
"to_pin": "OUT",
|
||||
"from_pin": "1"
|
||||
},
|
||||
"CLKBINV:CLKB": {
|
||||
"to_pin": "OUT",
|
||||
"from_pin": "CLKB"
|
||||
},
|
||||
"IMUX:0": {
|
||||
"to_pin": "OUT",
|
||||
"from_pin": "0"
|
||||
},
|
||||
"D2OFFBYP_SEL:GND": {
|
||||
"to_pin": "OUT",
|
||||
"from_pin": "GND"
|
||||
},
|
||||
"IFFDELMUXE3:1": {
|
||||
"to_pin": "OUT",
|
||||
"from_pin": "1"
|
||||
},
|
||||
"DINV:D_B": {
|
||||
"to_pin": "OUT",
|
||||
"from_pin": "D_B"
|
||||
},
|
||||
"IMUX:1": {
|
||||
"to_pin": "OUT",
|
||||
"from_pin": "1"
|
||||
},
|
||||
"IFFDELMUXE3:2": {
|
||||
"to_pin": "OUT",
|
||||
"from_pin": "2"
|
||||
},
|
||||
"ZHOLD_IFF_INV:D_B": {
|
||||
"to_pin": "OUT",
|
||||
"from_pin": "D_B"
|
||||
},
|
||||
"CE1USED:0": {
|
||||
"to_pin": "OUT",
|
||||
"from_pin": "0"
|
||||
},
|
||||
"IDELMUXE3:0": {
|
||||
"to_pin": "OUT",
|
||||
"from_pin": "0"
|
||||
},
|
||||
"DINV:D": {
|
||||
"to_pin": "OUT",
|
||||
"from_pin": "D"
|
||||
},
|
||||
"ZHOLD_FABRIC_INV:D": {
|
||||
"to_pin": "OUT",
|
||||
"from_pin": "D"
|
||||
},
|
||||
"IFFDELMUXE3:0": {
|
||||
"to_pin": "OUT",
|
||||
"from_pin": "0"
|
||||
},
|
||||
"REVUSED:0": {
|
||||
"to_pin": "OUT",
|
||||
"from_pin": "0"
|
||||
},
|
||||
"SRUSED:0": {
|
||||
"to_pin": "OUT",
|
||||
"from_pin": "0"
|
||||
},
|
||||
"IDELMUXE3:1": {
|
||||
"to_pin": "OUT",
|
||||
"from_pin": "1"
|
||||
},
|
||||
"D2OBYP_SEL:GND": {
|
||||
"to_pin": "OUT",
|
||||
"from_pin": "GND"
|
||||
}
|
||||
},
|
||||
"site_pins": {
|
||||
"Q8": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CE1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"OCLKB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CLKDIVP": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CLKB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"BITSLIP": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DYNCLKSEL": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"REV": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q7": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DYNCLKDIVSEL": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SHIFTIN1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SHIFTOUT1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TFB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q5": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"OCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q6": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SHIFTOUT2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"OFB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SHIFTIN2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SR": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CE2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DYNCLKDIVPSEL": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DDLY": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CLKDIV": {
|
||||
"direction": "IN"
|
||||
}
|
||||
}
|
||||
}
|
||||
"type": "ILOGICE3"
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,453 +1,453 @@
|
|||
{
|
||||
"type": "IN_FIFO",
|
||||
"site_pips": {},
|
||||
"site_pins": {
|
||||
"SCANIN2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q83": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q67": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D31": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q62": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D12": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D67": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q14": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D81": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q21": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"ALMOSTEMPTY": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D13": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D72": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D61": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q81": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D22": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q71": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q05": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q32": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTREADDISB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q10": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D20": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q70": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SCANIN1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SCANENB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D02": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D80": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ALMOSTFULL": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q84": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D73": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q43": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q55": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q13": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SCANOUT1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q22": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SCANOUT2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTMODEB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D66": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q65": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q47": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FULL": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q15": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q30": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D21": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D92": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q04": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q51": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D53": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q56": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q90": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q96": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D65": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"RDCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q92": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D32": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D60": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q27": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q02": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q64": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q20": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D90": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q00": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q87": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D42": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"WREN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D51": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D10": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q91": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q61": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D01": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D71": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q16": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q57": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q74": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q34": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SCANIN0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D70": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q66": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q42": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q11": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D91": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q80": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"WRCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q82": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D03": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q26": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SCANIN3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q97": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q06": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q01": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D56": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q41": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q73": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"RESET": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SCANOUT0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q50": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D43": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q95": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q25": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D11": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D54": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q86": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D55": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q53": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q45": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D93": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTWRITEDISB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q63": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q03": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q54": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q94": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D00": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q33": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D30": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q46": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D63": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"RDEN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"EMPTY": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q07": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D64": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q52": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q85": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D50": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q44": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D52": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q60": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q12": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q93": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D33": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q31": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q23": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q76": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D82": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q75": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q35": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q24": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D57": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q77": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D40": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q40": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q36": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q72": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q37": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D62": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SCANOUT3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q17": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D83": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D23": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D41": {
|
||||
"direction": "IN"
|
||||
}
|
||||
}
|
||||
}
|
||||
"site_pins": {
|
||||
"Q61": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q73": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D91": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q00": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D41": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D02": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q84": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D70": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q60": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D51": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D22": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D92": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTWRITEDISB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SCANIN0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D00": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q11": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q16": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D53": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q40": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D65": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D11": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D30": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q12": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D50": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q32": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"ALMOSTEMPTY": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q07": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q35": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q55": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D67": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q93": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q85": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D56": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q30": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q67": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q71": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SCANOUT0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q52": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q86": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D40": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D62": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q51": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q25": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q92": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q97": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"ALMOSTFULL": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D42": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q96": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q31": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q54": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q82": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SCANIN1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q63": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SCANIN3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D57": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D82": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D31": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"RDEN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q66": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q91": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q21": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"RESET": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q47": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D01": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D52": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q04": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q20": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q01": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D13": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D23": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q17": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q87": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q06": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D72": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D20": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTMODEB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D03": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q26": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D71": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q22": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q37": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EMPTY": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q03": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q27": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q95": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D61": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D80": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D55": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q81": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D32": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D54": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q64": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D12": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q13": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q94": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FULL": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D64": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D60": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SCANOUT1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q36": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D83": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D33": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q53": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q34": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"WRCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D10": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q44": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTREADDISB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"WREN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q75": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q33": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SCANOUT2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D21": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q42": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q65": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SCANENB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q23": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D81": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q80": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q43": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q77": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q76": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q50": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q24": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SCANOUT3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q56": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q83": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D43": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q57": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q90": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q62": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D93": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q74": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D63": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q70": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q02": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q14": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D73": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D66": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q72": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SCANIN2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q10": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q46": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D90": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"RDCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q05": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q41": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q15": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q45": {
|
||||
"direction": "OUT"
|
||||
}
|
||||
},
|
||||
"site_pips": {},
|
||||
"type": "IN_FIFO"
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,94 +1,94 @@
|
|||
{
|
||||
"type": "IOB33",
|
||||
"site_pips": {
|
||||
"PADOUTUSED:0": {
|
||||
"to_pin": "OUT",
|
||||
"from_pin": "0"
|
||||
"site_pins": {
|
||||
"PD_INT_EN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIFFI_IN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIFFO_OUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DIFF_TERM_INT_EN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PADOUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"T": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"IBUFDISABLE": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"T_OUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"INTERMDISABLE": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PU_INT_EN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O_OUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"KEEPER_INT_EN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"T_IN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"I": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"O": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIFFO_IN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O_IN": {
|
||||
"direction": "IN"
|
||||
}
|
||||
},
|
||||
"IBUFDISABLE_SEL:GND": {
|
||||
"to_pin": "OUT",
|
||||
"from_pin": "GND"
|
||||
"site_pips": {
|
||||
"IBUFDISABLE_SEL:I": {
|
||||
"from_pin": "I",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"OUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"TUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"INTERMDISABLE_SEL:I": {
|
||||
"from_pin": "I",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"IUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"PADOUTUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"INTERMDISABLE_SEL:GND": {
|
||||
"from_pin": "GND",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"DIFFI_INUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"IBUFDISABLE_SEL:GND": {
|
||||
"from_pin": "GND",
|
||||
"to_pin": "OUT"
|
||||
}
|
||||
},
|
||||
"DIFFI_INUSED:0": {
|
||||
"to_pin": "OUT",
|
||||
"from_pin": "0"
|
||||
},
|
||||
"IBUFDISABLE_SEL:I": {
|
||||
"to_pin": "OUT",
|
||||
"from_pin": "I"
|
||||
},
|
||||
"INTERMDISABLE_SEL:GND": {
|
||||
"to_pin": "OUT",
|
||||
"from_pin": "GND"
|
||||
},
|
||||
"OUSED:0": {
|
||||
"to_pin": "OUT",
|
||||
"from_pin": "0"
|
||||
},
|
||||
"IUSED:0": {
|
||||
"to_pin": "OUT",
|
||||
"from_pin": "0"
|
||||
},
|
||||
"INTERMDISABLE_SEL:I": {
|
||||
"to_pin": "OUT",
|
||||
"from_pin": "I"
|
||||
},
|
||||
"TUSED:0": {
|
||||
"to_pin": "OUT",
|
||||
"from_pin": "0"
|
||||
}
|
||||
},
|
||||
"site_pins": {
|
||||
"T": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"IBUFDISABLE": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"KEEPER_INT_EN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O_IN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIFFI_IN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"T_IN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O_OUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DIFF_TERM_INT_EN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIFFO_OUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DIFFO_IN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"I": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"T_OUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PADOUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PD_INT_EN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PU_INT_EN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"INTERMDISABLE": {
|
||||
"direction": "IN"
|
||||
}
|
||||
}
|
||||
}
|
||||
"type": "IOB33"
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,106 +1,106 @@
|
|||
{
|
||||
"type": "IOB33M",
|
||||
"site_pips": {
|
||||
"DIFFO_OUTUSED:0": {
|
||||
"to_pin": "OUT",
|
||||
"from_pin": "0"
|
||||
"site_pins": {
|
||||
"T_OUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DIFFI_IN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIFFO_OUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PD_INT_EN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIFF_TERM_INT_EN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PADOUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"IBUFDISABLE": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"KEEPER_INT_EN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"INTERMDISABLE": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PU_INT_EN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O_OUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"O_IN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"T_IN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"I": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"O": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIFFO_IN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"T": {
|
||||
"direction": "IN"
|
||||
}
|
||||
},
|
||||
"O_OUTUSED:0": {
|
||||
"to_pin": "OUT",
|
||||
"from_pin": "0"
|
||||
"site_pips": {
|
||||
"INTERMDISABLE_SEL:GND": {
|
||||
"from_pin": "GND",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"T_OUTUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"INTERMDISABLE_SEL:I": {
|
||||
"from_pin": "I",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"IUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"DIFFI_INUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"IBUFDISABLE_SEL:GND": {
|
||||
"from_pin": "GND",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"OUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"IBUFDISABLE_SEL:I": {
|
||||
"from_pin": "I",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"PADOUTUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"O_OUTUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"DIFFO_OUTUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"TUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
}
|
||||
},
|
||||
"IBUFDISABLE_SEL:I": {
|
||||
"to_pin": "OUT",
|
||||
"from_pin": "I"
|
||||
},
|
||||
"INTERMDISABLE_SEL:GND": {
|
||||
"to_pin": "OUT",
|
||||
"from_pin": "GND"
|
||||
},
|
||||
"TUSED:0": {
|
||||
"to_pin": "OUT",
|
||||
"from_pin": "0"
|
||||
},
|
||||
"PADOUTUSED:0": {
|
||||
"to_pin": "OUT",
|
||||
"from_pin": "0"
|
||||
},
|
||||
"IBUFDISABLE_SEL:GND": {
|
||||
"to_pin": "OUT",
|
||||
"from_pin": "GND"
|
||||
},
|
||||
"INTERMDISABLE_SEL:I": {
|
||||
"to_pin": "OUT",
|
||||
"from_pin": "I"
|
||||
},
|
||||
"DIFFI_INUSED:0": {
|
||||
"to_pin": "OUT",
|
||||
"from_pin": "0"
|
||||
},
|
||||
"IUSED:0": {
|
||||
"to_pin": "OUT",
|
||||
"from_pin": "0"
|
||||
},
|
||||
"T_OUTUSED:0": {
|
||||
"to_pin": "OUT",
|
||||
"from_pin": "0"
|
||||
},
|
||||
"OUSED:0": {
|
||||
"to_pin": "OUT",
|
||||
"from_pin": "0"
|
||||
}
|
||||
},
|
||||
"site_pins": {
|
||||
"T": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"IBUFDISABLE": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"KEEPER_INT_EN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O_IN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIFFO_OUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PD_INT_EN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIFFI_IN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"T_IN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIFF_TERM_INT_EN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"T_OUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DIFFO_IN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"I": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"O_OUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PADOUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PU_INT_EN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"INTERMDISABLE": {
|
||||
"direction": "IN"
|
||||
}
|
||||
}
|
||||
}
|
||||
"type": "IOB33M"
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,114 +1,114 @@
|
|||
{
|
||||
"type": "IOB33S",
|
||||
"site_pips": {
|
||||
"DIFFO_INUSED:0": {
|
||||
"to_pin": "OUT",
|
||||
"from_pin": "0"
|
||||
"site_pins": {
|
||||
"T_OUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DIFFI_IN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIFFO_OUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PD_INT_EN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIFF_TERM_INT_EN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PADOUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"IBUFDISABLE": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"KEEPER_INT_EN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"INTERMDISABLE": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PU_INT_EN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O_OUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"O_IN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"T_IN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"I": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"O": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIFFO_IN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"T": {
|
||||
"direction": "IN"
|
||||
}
|
||||
},
|
||||
"TINMUX:1": {
|
||||
"to_pin": "OUT",
|
||||
"from_pin": "1"
|
||||
"site_pips": {
|
||||
"INTERMDISABLE_SEL:I": {
|
||||
"from_pin": "I",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"IUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"OUTMUX:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"DIFFI_INUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"IBUFDISABLE_SEL:GND": {
|
||||
"from_pin": "GND",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"OINMUX:1": {
|
||||
"from_pin": "1",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"TINMUX:1": {
|
||||
"from_pin": "1",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"IBUFDISABLE_SEL:I": {
|
||||
"from_pin": "I",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"DIFFO_INUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"PADOUTUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"OUTMUX:1": {
|
||||
"from_pin": "1",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"OINMUX:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"INTERMDISABLE_SEL:GND": {
|
||||
"from_pin": "GND",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"TINMUX:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
}
|
||||
},
|
||||
"IBUFDISABLE_SEL:I": {
|
||||
"to_pin": "OUT",
|
||||
"from_pin": "I"
|
||||
},
|
||||
"INTERMDISABLE_SEL:GND": {
|
||||
"to_pin": "OUT",
|
||||
"from_pin": "GND"
|
||||
},
|
||||
"OINMUX:1": {
|
||||
"to_pin": "OUT",
|
||||
"from_pin": "1"
|
||||
},
|
||||
"OUTMUX:0": {
|
||||
"to_pin": "OUT",
|
||||
"from_pin": "0"
|
||||
},
|
||||
"OINMUX:0": {
|
||||
"to_pin": "OUT",
|
||||
"from_pin": "0"
|
||||
},
|
||||
"OUTMUX:1": {
|
||||
"to_pin": "OUT",
|
||||
"from_pin": "1"
|
||||
},
|
||||
"PADOUTUSED:0": {
|
||||
"to_pin": "OUT",
|
||||
"from_pin": "0"
|
||||
},
|
||||
"IBUFDISABLE_SEL:GND": {
|
||||
"to_pin": "OUT",
|
||||
"from_pin": "GND"
|
||||
},
|
||||
"DIFFI_INUSED:0": {
|
||||
"to_pin": "OUT",
|
||||
"from_pin": "0"
|
||||
},
|
||||
"TINMUX:0": {
|
||||
"to_pin": "OUT",
|
||||
"from_pin": "0"
|
||||
},
|
||||
"IUSED:0": {
|
||||
"to_pin": "OUT",
|
||||
"from_pin": "0"
|
||||
},
|
||||
"INTERMDISABLE_SEL:I": {
|
||||
"to_pin": "OUT",
|
||||
"from_pin": "I"
|
||||
}
|
||||
},
|
||||
"site_pins": {
|
||||
"T": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"IBUFDISABLE": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"KEEPER_INT_EN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O_IN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIFFO_OUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PD_INT_EN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIFFI_IN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"T_IN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIFF_TERM_INT_EN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"T_OUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DIFFO_IN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"I": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"O_OUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PADOUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PU_INT_EN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"INTERMDISABLE": {
|
||||
"direction": "IN"
|
||||
}
|
||||
}
|
||||
}
|
||||
"type": "IOB33S"
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,9 +1,9 @@
|
|||
{
|
||||
"type": "IPAD",
|
||||
"site_pips": {},
|
||||
"site_pins": {
|
||||
"O": {
|
||||
"direction": "OUT"
|
||||
}
|
||||
}
|
||||
}
|
||||
"site_pins": {
|
||||
"O": {
|
||||
"direction": "OUT"
|
||||
}
|
||||
},
|
||||
"site_pips": {},
|
||||
"type": "IPAD"
|
||||
}
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,210 +1,210 @@
|
|||
{
|
||||
"type": "OLOGICE3",
|
||||
"site_pips": {
|
||||
"T2INV:T2": {
|
||||
"to_pin": "OUT",
|
||||
"from_pin": "T2"
|
||||
"site_pins": {
|
||||
"TFB": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TBYTEOUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"OFB": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"OQ": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CLKDIV": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TCE": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D6": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D4": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D8": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TBYTEIN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TQ": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SHIFTOUT1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"T2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CLKDIVFB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CLKDIVF": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"IOCLKGLITCH": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SHIFTIN1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SHIFTOUT2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D7": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CLKDIVB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CLKB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D5": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"T1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SHIFTIN2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"OCE": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"REV": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SR": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"T3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"T4": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D1": {
|
||||
"direction": "IN"
|
||||
}
|
||||
},
|
||||
"T1INV:T1_B": {
|
||||
"to_pin": "OUT",
|
||||
"from_pin": "T1_B"
|
||||
"site_pips": {
|
||||
"T1USED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"OREVUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"CLKINV:CLK": {
|
||||
"from_pin": "CLK",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"TMUX:T1": {
|
||||
"from_pin": "T1",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"CLKINV:CLK_B": {
|
||||
"from_pin": "CLK_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"D2INV:D2": {
|
||||
"from_pin": "D2",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"OMUX:D1": {
|
||||
"from_pin": "D1",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"D1INV:D1_B": {
|
||||
"from_pin": "D1_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"OMUX:OUTFF": {
|
||||
"from_pin": "OUTFF",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"TQUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"OFBUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"TFBUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"TCEUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"TMUX:TFF": {
|
||||
"from_pin": "TFF",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"O1USED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"T2INV:T2_B": {
|
||||
"from_pin": "T2_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"T1INV:T1_B": {
|
||||
"from_pin": "T1_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"T2INV:T2": {
|
||||
"from_pin": "T2",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"OQUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"TSRUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"D1INV:D1": {
|
||||
"from_pin": "D1",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"OCEUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"TREVUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"T1INV:T1": {
|
||||
"from_pin": "T1",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"D2INV:D2_B": {
|
||||
"from_pin": "D2_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"OSRUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
}
|
||||
},
|
||||
"OQUSED:0": {
|
||||
"to_pin": "OUT",
|
||||
"from_pin": "0"
|
||||
},
|
||||
"OFBUSED:0": {
|
||||
"to_pin": "OUT",
|
||||
"from_pin": "0"
|
||||
},
|
||||
"T1USED:0": {
|
||||
"to_pin": "OUT",
|
||||
"from_pin": "0"
|
||||
},
|
||||
"D1INV:D1_B": {
|
||||
"to_pin": "OUT",
|
||||
"from_pin": "D1_B"
|
||||
},
|
||||
"TFBUSED:0": {
|
||||
"to_pin": "OUT",
|
||||
"from_pin": "0"
|
||||
},
|
||||
"CLKINV:CLK_B": {
|
||||
"to_pin": "OUT",
|
||||
"from_pin": "CLK_B"
|
||||
},
|
||||
"OCEUSED:0": {
|
||||
"to_pin": "OUT",
|
||||
"from_pin": "0"
|
||||
},
|
||||
"D1INV:D1": {
|
||||
"to_pin": "OUT",
|
||||
"from_pin": "D1"
|
||||
},
|
||||
"OREVUSED:0": {
|
||||
"to_pin": "OUT",
|
||||
"from_pin": "0"
|
||||
},
|
||||
"OSRUSED:0": {
|
||||
"to_pin": "OUT",
|
||||
"from_pin": "0"
|
||||
},
|
||||
"TQUSED:0": {
|
||||
"to_pin": "OUT",
|
||||
"from_pin": "0"
|
||||
},
|
||||
"D2INV:D2": {
|
||||
"to_pin": "OUT",
|
||||
"from_pin": "D2"
|
||||
},
|
||||
"O1USED:0": {
|
||||
"to_pin": "OUT",
|
||||
"from_pin": "0"
|
||||
},
|
||||
"CLKINV:CLK": {
|
||||
"to_pin": "OUT",
|
||||
"from_pin": "CLK"
|
||||
},
|
||||
"TMUX:T1": {
|
||||
"to_pin": "OUT",
|
||||
"from_pin": "T1"
|
||||
},
|
||||
"TSRUSED:0": {
|
||||
"to_pin": "OUT",
|
||||
"from_pin": "0"
|
||||
},
|
||||
"TREVUSED:0": {
|
||||
"to_pin": "OUT",
|
||||
"from_pin": "0"
|
||||
},
|
||||
"TCEUSED:0": {
|
||||
"to_pin": "OUT",
|
||||
"from_pin": "0"
|
||||
},
|
||||
"TMUX:TFF": {
|
||||
"to_pin": "OUT",
|
||||
"from_pin": "TFF"
|
||||
},
|
||||
"OMUX:D1": {
|
||||
"to_pin": "OUT",
|
||||
"from_pin": "D1"
|
||||
},
|
||||
"OMUX:OUTFF": {
|
||||
"to_pin": "OUT",
|
||||
"from_pin": "OUTFF"
|
||||
},
|
||||
"T1INV:T1": {
|
||||
"to_pin": "OUT",
|
||||
"from_pin": "T1"
|
||||
},
|
||||
"D2INV:D2_B": {
|
||||
"to_pin": "OUT",
|
||||
"from_pin": "D2_B"
|
||||
},
|
||||
"T2INV:T2_B": {
|
||||
"to_pin": "OUT",
|
||||
"from_pin": "T2_B"
|
||||
}
|
||||
},
|
||||
"site_pins": {
|
||||
"T2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TBYTEOUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D6": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D8": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CLKDIVB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CLKB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"REV": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"T1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D5": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TFB": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SHIFTIN1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SHIFTOUT1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"T4": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D4": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TQ": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"T3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"OCE": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SHIFTOUT2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"OFB": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CLKDIVF": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"OQ": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SHIFTIN2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SR": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"IOCLKGLITCH": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CLKDIVFB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TCE": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TBYTEIN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D7": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CLKDIV": {
|
||||
"direction": "IN"
|
||||
}
|
||||
}
|
||||
}
|
||||
"type": "OLOGICE3"
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,9 +1,9 @@
|
|||
{
|
||||
"type": "OPAD",
|
||||
"site_pips": {},
|
||||
"site_pins": {
|
||||
"I": {
|
||||
"direction": "IN"
|
||||
}
|
||||
}
|
||||
}
|
||||
"site_pins": {
|
||||
"I": {
|
||||
"direction": "IN"
|
||||
}
|
||||
},
|
||||
"site_pips": {},
|
||||
"type": "OPAD"
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,453 +1,453 @@
|
|||
{
|
||||
"type": "OUT_FIFO",
|
||||
"site_pips": {},
|
||||
"site_pins": {
|
||||
"SCANIN2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q83": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D07": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D31": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D75": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q62": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D12": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D67": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q53": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D90": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ALMOSTEMPTY": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q67": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D13": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D72": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"RDCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q81": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D22": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D46": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q82": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q03": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D87": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q10": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q21": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D20": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q70": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SCANIN1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SCANENB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D24": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D80": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ALMOSTFULL": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D44": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D37": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q41": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q43": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q55": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q13": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SCANOUT1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D73": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q22": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SCANOUT2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D27": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q42": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D94": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D66": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q65": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D36": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"FULL": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D85": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D15": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D84": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D21": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D92": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q51": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D53": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q56": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D34": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q90": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D65": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D14": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D50": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D32": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D76": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D97": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q64": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q20": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SCANOUT3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q92": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D42": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"WREN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D51": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D10": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q91": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D16": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q61": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D01": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D71": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q57": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D45": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D96": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D81": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SCANIN0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D70": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q66": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D05": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q11": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D61": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D86": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D91": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"WRCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D17": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D03": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q80": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SCANIN3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D93": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTMODEB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q01": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D56": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D60": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D06": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D77": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D52": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D04": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"RESET": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SCANOUT0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q50": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D43": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D74": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D11": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D54": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D55": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D35": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q93": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTWRITEDISB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q63": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q00": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q54": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q30": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D00": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q33": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D30": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q32": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D63": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"RDEN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"EMPTY": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D64": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q52": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D26": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q73": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q60": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q12": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D83": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTREADDISB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D33": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q31": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q23": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D82": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q02": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D25": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D57": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D40": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q40": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q72": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q71": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D62": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D02": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D95": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D47": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D23": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D41": {
|
||||
"direction": "IN"
|
||||
}
|
||||
}
|
||||
}
|
||||
"site_pins": {
|
||||
"D02": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q73": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D91": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q00": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D41": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D05": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D81": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D70": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q60": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D34": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D44": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ALMOSTEMPTY": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D51": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D55": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D92": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTWRITEDISB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SCANIN0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D00": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D46": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D24": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q40": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D97": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D11": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D30": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q12": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D50": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D40": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D95": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"WREN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D77": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q55": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D67": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q93": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q52": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D56": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D36": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q67": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q21": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SCANOUT0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D62": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D16": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q51": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D31": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D86": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q92": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"ALMOSTFULL": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D42": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D90": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q31": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D26": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SCANIN1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SCANIN3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D15": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q70": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D57": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D87": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D61": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"RDEN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q66": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q91": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q71": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"RESET": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D72": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D01": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D52": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q20": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D47": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q01": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D13": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D23": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q61": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D82": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D20": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTMODEB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D03": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q30": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q22": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D14": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"EMPTY": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q03": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q63": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D35": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D80": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D06": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q81": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D32": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D54": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q64": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q13": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D85": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"FULL": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D64": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D60": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SCANOUT1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q32": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D83": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D96": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D33": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D76": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q11": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"WRCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D10": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D71": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D04": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D45": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTREADDISB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D74": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D63": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q33": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SCANOUT2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D21": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q65": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D66": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q42": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D07": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SCANENB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q23": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"RDCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q80": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q43": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q54": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q50": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SCANOUT3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q56": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q83": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D43": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q57": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q90": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q62": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D93": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D37": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D22": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q72": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D17": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D65": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D84": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q02": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D12": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D75": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D73": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D53": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q53": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SCANIN2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q10": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D25": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D27": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q41": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D94": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q82": {
|
||||
"direction": "OUT"
|
||||
}
|
||||
},
|
||||
"site_pips": {},
|
||||
"type": "OUT_FIFO"
|
||||
}
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,291 +1,291 @@
|
|||
{
|
||||
"type": "PHASER_IN_PHY",
|
||||
"site_pips": {
|
||||
"RSTINV:RST": {
|
||||
"to_pin": "OUT",
|
||||
"from_pin": "RST"
|
||||
},
|
||||
"RSTINV:RST_B": {
|
||||
"to_pin": "OUT",
|
||||
"from_pin": "RST_B"
|
||||
}
|
||||
},
|
||||
"site_pins": {
|
||||
"PHASELOCKED": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"ICLKDIV": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ICLK": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"ENCALIB1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COUNTERREADVAL5": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SCANIN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COUNTERREADVAL3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SELCALORSTG1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COUNTERLOADVAL2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SYSCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SCANENB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SCANCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COUNTERREADEN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ENCALIB0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ENSTG1ADJUSTB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"STG1REGR2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN7": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"RCLK": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"COUNTERLOADVAL3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COUNTERLOADVAL4": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN8": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"MEMREFCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"STG1REGL0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"FREQREFCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ENCALIBPHY1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"STG1REGL3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"STG1INCDEC": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COUNTERREADVAL4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHASEREFCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"STG1REGR7": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FINEENABLE": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"STG1REGR3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DQSFOUND": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"RANKSEL0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SCANOUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"STG1REGR1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"RANKSELPHY0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COUNTERLOADEN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"RANKSELPHY1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN9": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN12": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"STG1REGL8": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIVIDERST": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"STG1REGL5": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COUNTERLOADVAL1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"STG1READ": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"FINEINC": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"RANKSEL1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COUNTERREADVAL1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"ISERDESRST": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FINEOVERFLOW": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"COUNTERLOADVAL0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"RSTDQSFIND": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COUNTERREADVAL2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"STG1REGR0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"BURSTPENDING": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN5": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN6": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"EDGEADV": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"STG1LOAD": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN13": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"STG1REGL4": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"STG1REGR5": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"BURSTPENDINGPHY": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"COUNTERLOADVAL5": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DQSOUTOFRANGE": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"WRENABLE": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNCIN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN10": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN11": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"STG1REGR8": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"STG1REGL6": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"STG1REGR6": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"RST": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"STG1REGL7": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SCANMODEB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"STG1REGL2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ENSTG1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"STG1REGR4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"STG1OVERFLOW": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN4": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"ENCALIBPHY0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COUNTERREADVAL0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"STG1REGL1": {
|
||||
"direction": "IN"
|
||||
}
|
||||
}
|
||||
}
|
||||
"site_pins": {
|
||||
"FINEINC": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"STG1REGL7": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COUNTERLOADVAL0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SCANIN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COUNTERREADVAL1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"RANKSELPHY0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ENSTG1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"STG1READ": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"STG1REGR2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN6": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SCANOUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"STG1REGL0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"STG1INCDEC": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ICLKDIV": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"ENSTG1ADJUSTB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COUNTERREADVAL3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"WRENABLE": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"RANKSELPHY1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COUNTERLOADVAL2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PHASELOCKED": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"COUNTERREADVAL0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN9": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ENCALIBPHY0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"RANKSEL1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COUNTERREADVAL2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"COUNTERLOADVAL3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DQSFOUND": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SCANCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"RSTDQSFIND": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"STG1REGR7": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN11": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN7": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"FREQREFCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SCANMODEB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"RST": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"STG1REGL6": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIVIDERST": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COUNTERREADVAL5": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"ENCALIB1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SYSCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN4": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"STG1REGL8": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"BURSTPENDING": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COUNTERLOADVAL5": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COUNTERREADEN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COUNTERLOADVAL1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"STG1REGR0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"STG1REGL5": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ISERDESRST": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SELCALORSTG1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"STG1REGR3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"COUNTERLOADEN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"STG1OVERFLOW": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"COUNTERREADVAL4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"BURSTPENDINGPHY": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"STG1REGR4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PHASEREFCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"RCLK": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"STG1REGR6": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"STG1REGR1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN5": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ICLK": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SCANENB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"STG1REGL1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"FINEOVERFLOW": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DQSOUTOFRANGE": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"ENCALIB0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"STG1REGL2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"STG1REGR8": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EDGEADV": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"STG1REGL4": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ENCALIBPHY1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"STG1REGR5": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"RANKSEL0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COUNTERLOADVAL4": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SYNCIN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN10": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN8": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN12": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"FINEENABLE": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"STG1REGL3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"STG1LOAD": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN13": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"MEMREFCLK": {
|
||||
"direction": "IN"
|
||||
}
|
||||
},
|
||||
"site_pips": {
|
||||
"RSTINV:RST_B": {
|
||||
"from_pin": "RST_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"RSTINV:RST": {
|
||||
"from_pin": "RST",
|
||||
"to_pin": "OUT"
|
||||
}
|
||||
},
|
||||
"type": "PHASER_IN_PHY"
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,246 +1,246 @@
|
|||
{
|
||||
"type": "PHASER_OUT_PHY",
|
||||
"site_pips": {
|
||||
"RSTINV:RST": {
|
||||
"to_pin": "OUT",
|
||||
"from_pin": "RST"
|
||||
},
|
||||
"RSTINV:RST_B": {
|
||||
"to_pin": "OUT",
|
||||
"from_pin": "RST_B"
|
||||
}
|
||||
},
|
||||
"site_pins": {
|
||||
"TESTIN15": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COUNTERLOADVAL8": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIVIDERST": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COUNTERLOADVAL1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COUNTERREADVAL7": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"FINEINC": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN4": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ENCALIB1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COUNTERREADVAL4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"COUNTERLOADVAL6": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SCANIN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DTSBUS1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"COUNTERREADVAL3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CTSBUS0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"COUNTERREADVAL1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FINEOVERFLOW": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"COUNTERLOADVAL0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CTSBUS1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"OSERDESRST": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"COARSEENABLE": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COUNTERLOADVAL2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"RDENABLE": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYSCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"OCLK": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"BURSTPENDING": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SCANCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN14": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN5": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COUNTERREADEN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COUNTERREADVAL8": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"ENCALIB0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"EDGEADV": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN7": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COARSEINC": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN6": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN13": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"OCLKDIV": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"COUNTERLOADVAL3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COARSEOVERFLOW": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN11": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN8": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"MEMREFCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"COUNTERLOADVAL5": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DTSBUS0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FREQREFCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ENCALIBPHY1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ENCALIBPHY0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DQSBUS1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"COUNTERLOADVAL7": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN10": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SELFINEOCLKDELAY": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHASEREFCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COUNTERREADVAL5": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DQSBUS0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FINEENABLE": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"OCLKDELAYED": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"RST": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SYNCIN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"BURSTPENDINGPHY": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COUNTERREADVAL0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"COUNTERLOADVAL4": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SCANOUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SCANMODEB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SCANENB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COUNTERLOADEN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COUNTERREADVAL2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"COUNTERREADVAL6": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN9": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN12": {
|
||||
"direction": "IN"
|
||||
}
|
||||
}
|
||||
}
|
||||
"site_pins": {
|
||||
"FINEINC": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN5": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COUNTERREADVAL5": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"ENCALIB1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COARSEOVERFLOW": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"COUNTERLOADVAL0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"OCLKDIV": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN4": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COUNTERREADVAL3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"BURSTPENDING": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COUNTERLOADVAL5": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COUNTERREADEN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIVIDERST": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COARSEENABLE": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COUNTERLOADVAL1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN15": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COARSEINC": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SELFINEOCLKDELAY": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FINEOVERFLOW": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN11": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DTSBUS0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SCANOUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"COUNTERLOADEN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"FINEENABLE": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN13": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COUNTERREADVAL4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"BURSTPENDINGPHY": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COUNTERLOADVAL2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHASEREFCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"OCLK": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYSCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN14": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"RDENABLE": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SCANIN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CTSBUS1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"COUNTERLOADVAL7": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DTSBUS1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"COUNTERREADVAL1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"COUNTERREADVAL8": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"COUNTERREADVAL7": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"RST": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN6": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ENCALIB0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COUNTERREADVAL0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"MEMREFCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN9": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ENCALIBPHY0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"EDGEADV": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COUNTERREADVAL2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"COUNTERREADVAL6": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"ENCALIBPHY1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CTSBUS0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"COUNTERLOADVAL3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COUNTERLOADVAL4": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"OCLKDELAYED": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"OSERDESRST": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNCIN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COUNTERLOADVAL8": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SCANCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SCANENB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN8": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DQSBUS0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN12": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DQSBUS1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SCANMODEB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN7": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN10": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"FREQREFCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COUNTERLOADVAL6": {
|
||||
"direction": "IN"
|
||||
}
|
||||
},
|
||||
"site_pips": {
|
||||
"RSTINV:RST_B": {
|
||||
"from_pin": "RST_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"RSTINV:RST": {
|
||||
"from_pin": "RST",
|
||||
"to_pin": "OUT"
|
||||
}
|
||||
},
|
||||
"type": "PHASER_OUT_PHY"
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,89 +1,89 @@
|
|||
{
|
||||
"type": "PHASER_REF",
|
||||
"site_pips": {
|
||||
"PWRDWNINV:PWRDWN_B": {
|
||||
"to_pin": "OUT",
|
||||
"from_pin": "PWRDWN_B"
|
||||
"site_pins": {
|
||||
"TESTIN5": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT7": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"RST": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CLKOUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PWRDWN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TMUXOUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN6": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"LOCKED": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN4": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN7": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT5": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CLKIN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT6": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT4": {
|
||||
"direction": "OUT"
|
||||
}
|
||||
},
|
||||
"RSTINV:RST": {
|
||||
"to_pin": "OUT",
|
||||
"from_pin": "RST"
|
||||
"site_pips": {
|
||||
"RSTINV:RST_B": {
|
||||
"from_pin": "RST_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"PWRDWNINV:PWRDWN": {
|
||||
"from_pin": "PWRDWN",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"RSTINV:RST": {
|
||||
"from_pin": "RST",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"PWRDWNINV:PWRDWN_B": {
|
||||
"from_pin": "PWRDWN_B",
|
||||
"to_pin": "OUT"
|
||||
}
|
||||
},
|
||||
"RSTINV:RST_B": {
|
||||
"to_pin": "OUT",
|
||||
"from_pin": "RST_B"
|
||||
},
|
||||
"PWRDWNINV:PWRDWN": {
|
||||
"to_pin": "OUT",
|
||||
"from_pin": "PWRDWN"
|
||||
}
|
||||
},
|
||||
"site_pins": {
|
||||
"TESTOUT3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TMUXOUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN4": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CLKOUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"LOCKED": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"RST": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT7": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN5": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN6": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PWRDWN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT5": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT6": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN7": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CLKIN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN1": {
|
||||
"direction": "IN"
|
||||
}
|
||||
}
|
||||
}
|
||||
"type": "PHASER_REF"
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,318 +1,318 @@
|
|||
{
|
||||
"type": "PHY_CONTROL",
|
||||
"site_pips": {},
|
||||
"site_pins": {
|
||||
"AUXOUTPUT1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PHYCTLWD25": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"INRANKB1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PHYCTLWD30": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUTPUT2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTINPUT7": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD20": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTINPUT10": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUTPUT12": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PHYCTLWD18": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD14": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"INBURSTPENDING3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUTPUT15": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PHYCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTINPUT11": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"OUTBURSTPENDING3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"MEMREFCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"OUTBURSTPENDING0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PHYCTLMSTREMPTY": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"OUTBURSTPENDING1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PHYCTLWD1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD19": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD29": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTINPUT3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTINPUT9": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PCENABLECALIB1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PHYCTLWD26": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"AUXOUTPUT2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PHYCTLWD5": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTINPUT8": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"READCALIBENABLE": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD11": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTSELECT2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"INBURSTPENDING1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PHYCTLWD27": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTINPUT5": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUTPUT10": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PHYCTLWD21": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUTPUT4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUTPUT5": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTINPUT4": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"INRANKA0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUTPUT8": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PHYCTLWD28": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUTPUT14": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUTPUT13": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PHYCTLWD9": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD4": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"INRANKC0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"REFDLLLOCK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"WRITECALIBENABLE": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWRENABLE": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLREADY": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTINPUT6": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"INRANKC1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PHYCTLWD8": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD15": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD17": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"INBURSTPENDING2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"INBURSTPENDING0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PHYCTLWD13": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"AUXOUTPUT0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PHYCTLWD10": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD7": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTINPUT0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"RESET": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLFULL": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PHYCTLWD24": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"INRANKA1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PHYCTLWD6": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLALMOSTFULL": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"INRANKD1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"INRANKD0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUTPUT9": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PHYCTLWD23": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PLLLOCK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD12": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTINPUT12": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PCENABLECALIB0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PHYCTLWD16": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"AUXOUTPUT3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUTPUT3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PHYCTLWD22": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUTPUT0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNCIN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"INRANKB0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTSELECT1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTINPUT13": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTSELECT0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUTPUT11": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTINPUT14": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTINPUT2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTINPUT1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTINPUT15": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD31": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUTPUT7": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PHYCTLEMPTY": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"OUTBURSTPENDING2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUTPUT6": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PHYCTLWD3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUTPUT1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SCANENABLEN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD0": {
|
||||
"direction": "IN"
|
||||
}
|
||||
}
|
||||
}
|
||||
"site_pins": {
|
||||
"PHYCTLALMOSTFULL": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"AUXOUTPUT3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PHYCTLWD10": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTINPUT15": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"OUTBURSTPENDING0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTINPUT0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD16": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUTPUT5": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUTPUT14": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"INRANKC1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"AUXOUTPUT0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"INRANKA1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTINPUT10": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD24": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD8": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD17": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTINPUT1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"INRANKB1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PHYCTLWD7": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLFULL": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PHYCTLWD11": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWRENABLE": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD26": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD23": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"INBURSTPENDING0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"INRANKC0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PHYCTLWD19": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"INRANKB0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PHYCTLWD9": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTSELECT2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTINPUT4": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUTPUT10": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PHYCTLWD2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUTPUT12": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"INRANKD1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PHYCTLWD28": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUTPUT6": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PHYCTLEMPTY": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUTPUT8": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUTPUT7": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"OUTBURSTPENDING1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"INRANKD0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUTPUT0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PHYCTLWD5": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTINPUT13": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"OUTBURSTPENDING3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTINPUT12": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"RESET": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD31": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTINPUT3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD29": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUTPUT4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUTPUT11": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PCENABLECALIB1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTINPUT11": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUTPUT15": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUTPUT2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUTPUT9": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"INBURSTPENDING3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PHYCTLWD3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PLLLOCK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"REFDLLLOCK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTINPUT7": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD27": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD6": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD18": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTINPUT5": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"OUTBURSTPENDING2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PHYCTLWD21": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTSELECT1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"AUXOUTPUT2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PHYCTLWD15": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTINPUT6": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD22": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTSELECT0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD4": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"WRITECALIBENABLE": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"INBURSTPENDING1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTINPUT14": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD12": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTINPUT8": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLMSTREMPTY": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD20": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD25": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUTPUT13": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"INRANKA0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"READCALIBENABLE": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PCENABLECALIB0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"AUXOUTPUT1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNCIN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SCANENABLEN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD30": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTINPUT2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUTPUT1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"INBURSTPENDING2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUTPUT3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PHYCTLWD14": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTINPUT9": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD13": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLREADY": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"MEMREFCLK": {
|
||||
"direction": "IN"
|
||||
}
|
||||
},
|
||||
"site_pips": {},
|
||||
"type": "PHY_CONTROL"
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,493 +1,493 @@
|
|||
{
|
||||
"type": "PLLE2_ADV",
|
||||
"site_pips": {
|
||||
"CLKINSELINV:CLKINSEL": {
|
||||
"to_pin": "OUT",
|
||||
"from_pin": "CLKINSEL"
|
||||
},
|
||||
"RSTINV:RST": {
|
||||
"to_pin": "OUT",
|
||||
"from_pin": "RST"
|
||||
},
|
||||
"RSTINV:RST_B": {
|
||||
"to_pin": "OUT",
|
||||
"from_pin": "RST_B"
|
||||
},
|
||||
"PWRDWNINV:PWRDWN_B": {
|
||||
"to_pin": "OUT",
|
||||
"from_pin": "PWRDWN_B"
|
||||
},
|
||||
"CLKINSELINV:CLKINSEL_B": {
|
||||
"to_pin": "OUT",
|
||||
"from_pin": "CLKINSEL_B"
|
||||
},
|
||||
"PWRDWNINV:PWRDWN": {
|
||||
"to_pin": "OUT",
|
||||
"from_pin": "PWRDWN"
|
||||
}
|
||||
},
|
||||
"site_pins": {
|
||||
"TESTIN15": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DO9": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DI0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT57": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TMUXOUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CLKIN1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DI15": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN5": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DADDR0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT21": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT22": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT31": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT14": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT62": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN17": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN20": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DO14": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN27": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CLKOUT5": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT7": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT43": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN14": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DRDY": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT36": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO5": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN25": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT27": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT8": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DADDR6": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN7": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT26": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT40": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DI3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT11": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT51": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN16": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT45": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN8": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DEN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN22": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT23": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT48": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DADDR1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DO3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT50": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT32": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CLKFBIN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DO8": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DO1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN21": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DI13": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DO12": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT33": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DI6": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN26": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CLKINSEL": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DI8": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT55": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT60": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DADDR4": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DADDR2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT38": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO10": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CLKOUT0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN30": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN18": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT6": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT58": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT53": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CLKFBOUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN28": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN9": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT20": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN12": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DO13": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DI2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DO0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO11": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN19": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DI12": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"LOCKED": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN4": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT15": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO6": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT19": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT24": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT61": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT59": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DI1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DI14": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT37": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT46": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CLKOUT1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT54": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT44": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT29": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT9": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN23": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DO15": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CLKIN2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DI10": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT13": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO7": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN6": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT49": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT5": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DI4": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN13": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT28": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DI5": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CLKOUT3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT34": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT56": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DI11": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT10": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT47": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN29": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DWE": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT16": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT35": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN10": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN11": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT63": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CLKOUT2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DI7": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DO4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT25": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DADDR3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT41": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"RST": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT42": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT52": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT39": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DADDR5": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT17": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT12": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT30": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN24": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PWRDWN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN31": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DI9": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT18": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CLKOUT4": {
|
||||
"direction": "OUT"
|
||||
}
|
||||
}
|
||||
}
|
||||
"site_pins": {
|
||||
"TESTOUT13": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT10": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CLKOUT1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT41": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DI5": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DO13": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT56": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT23": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO11": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT17": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO9": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN24": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN18": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT54": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN20": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT11": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN6": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT62": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DWE": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT22": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN19": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DI4": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN13": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DI0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DRDY": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT28": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DI3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DI13": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DADDR5": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT9": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT15": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DI6": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN14": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DI11": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT33": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN27": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT49": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT16": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT7": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DADDR4": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT50": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT5": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO12": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT57": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT31": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN17": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DI2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT32": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CLKOUT0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN9": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DI9": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PWRDWN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT59": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CLKOUT4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TMUXOUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT24": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CLKFBOUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN4": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT63": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DADDR0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT21": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DI15": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CLKOUT5": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN11": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN7": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT12": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN30": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT36": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DI7": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT6": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN25": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CLKOUT3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO14": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT14": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CLKIN1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT38": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DADDR1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT45": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN26": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT60": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"LOCKED": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT55": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DI10": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN15": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DADDR3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN8": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DEN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT53": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT27": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT37": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN31": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN22": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DADDR6": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN29": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT51": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT29": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT39": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO15": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DI12": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT35": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN16": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT47": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DADDR2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT58": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN5": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT18": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT52": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT40": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO5": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN21": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DO6": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CLKFBIN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"RST": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT8": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO7": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN28": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT25": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT61": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CLKINSEL": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DI1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DI8": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CLKOUT2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CLKIN2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DO8": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT48": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT20": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN23": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT34": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DI14": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT46": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT42": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN12": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DO3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT44": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT43": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN10": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT30": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT19": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO10": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT26": {
|
||||
"direction": "OUT"
|
||||
}
|
||||
},
|
||||
"site_pips": {
|
||||
"CLKINSELINV:CLKINSEL_B": {
|
||||
"from_pin": "CLKINSEL_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"RSTINV:RST_B": {
|
||||
"from_pin": "RST_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"RSTINV:RST": {
|
||||
"from_pin": "RST",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"CLKINSELINV:CLKINSEL": {
|
||||
"from_pin": "CLKINSEL",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"PWRDWNINV:PWRDWN": {
|
||||
"from_pin": "PWRDWN",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"PWRDWNINV:PWRDWN_B": {
|
||||
"from_pin": "PWRDWN_B",
|
||||
"to_pin": "OUT"
|
||||
}
|
||||
},
|
||||
"type": "PLLE2_ADV"
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,27 +1,27 @@
|
|||
{
|
||||
"type": "PMV2",
|
||||
"site_pips": {},
|
||||
"site_pins": {
|
||||
"O": {
|
||||
"direction": "OUT"
|
||||
"site_pins": {
|
||||
"ODIV2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"ODIV4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"A0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"EN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"A1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"A2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O": {
|
||||
"direction": "OUT"
|
||||
}
|
||||
},
|
||||
"A1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"A2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"A0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ODIV4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ODIV2": {
|
||||
"direction": "OUT"
|
||||
}
|
||||
}
|
||||
}
|
||||
"site_pips": {},
|
||||
"type": "PMV2"
|
||||
}
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -1,45 +1,45 @@
|
|||
{
|
||||
"type": "STARTUP",
|
||||
"site_pips": {},
|
||||
"site_pins": {
|
||||
"GTS": {
|
||||
"direction": "IN"
|
||||
"site_pins": {
|
||||
"USRDONEO": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CFGCLK": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"GTS": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PREQ": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CFGMCLK": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PACK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"GSR": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"KEYCLEARB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"USRCCLKO": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"USRDONETS": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"USRCCLKTS": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"EOS": {
|
||||
"direction": "OUT"
|
||||
}
|
||||
},
|
||||
"USRCCLKO": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CFGCLK": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"USRCCLKTS": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"USRDONETS": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PREQ": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PACK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"EOS": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CFGMCLK": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"GSR": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"KEYCLEARB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"USRDONEO": {
|
||||
"direction": "IN"
|
||||
}
|
||||
}
|
||||
}
|
||||
"site_pips": {},
|
||||
"type": "STARTUP"
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,12 +1,12 @@
|
|||
{
|
||||
"type": "TIEOFF",
|
||||
"site_pips": {},
|
||||
"site_pins": {
|
||||
"HARD1": {
|
||||
"direction": "OUT"
|
||||
"site_pins": {
|
||||
"HARD0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"HARD1": {
|
||||
"direction": "OUT"
|
||||
}
|
||||
},
|
||||
"HARD0": {
|
||||
"direction": "OUT"
|
||||
}
|
||||
}
|
||||
}
|
||||
"site_pips": {},
|
||||
"type": "TIEOFF"
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,108 +1,108 @@
|
|||
{
|
||||
"type": "USR_ACCESS",
|
||||
"site_pips": {},
|
||||
"site_pins": {
|
||||
"DATA2": {
|
||||
"direction": "OUT"
|
||||
"site_pins": {
|
||||
"DATA14": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA19": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA22": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATAVALID": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA8": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA13": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA12": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA7": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA5": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA10": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA21": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA28": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA17": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA23": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CFGCLK": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA16": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA18": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA30": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA9": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA26": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA29": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA24": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA27": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA6": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA25": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA31": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA15": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA20": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA11": {
|
||||
"direction": "OUT"
|
||||
}
|
||||
},
|
||||
"DATA20": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA17": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA24": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA13": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA14": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA27": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CFGCLK": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA11": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA9": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA30": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA10": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA29": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA31": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA15": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA18": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA8": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA22": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA23": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA6": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA25": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA5": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA16": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA12": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA19": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA26": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA7": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA28": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA21": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATAVALID": {
|
||||
"direction": "OUT"
|
||||
}
|
||||
}
|
||||
}
|
||||
"site_pips": {},
|
||||
"type": "USR_ACCESS"
|
||||
}
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,476 +1,476 @@
|
|||
{
|
||||
"pips": {
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B0->>INT_INTERFACE_LOGIC_OUTS_L0": {
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B0",
|
||||
"can_invert": "0",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L0"
|
||||
"wires": [
|
||||
"INT_INTERFACE_EE4A0",
|
||||
"INT_INTERFACE_BRAM_IMUX30",
|
||||
"INT_INTERFACE_BYP1",
|
||||
"INT_INTERFACE_BRAM_IMUX18",
|
||||
"INT_INTERFACE_SE4C2",
|
||||
"INT_INTERFACE_NW2A1",
|
||||
"INT_INTERFACE_SW4A3",
|
||||
"INT_INTERFACE_WL1END3",
|
||||
"INT_INTERFACE_WW4END1",
|
||||
"INT_INTERFACE_FAN1",
|
||||
"INT_INTERFACE_NE4BEG2",
|
||||
"INT_INTERFACE_NE4BEG3",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B9",
|
||||
"INT_INTERFACE_WW4B3",
|
||||
"INT_INTERFACE_LH6",
|
||||
"INT_INTERFACE_WW4C3",
|
||||
"INT_INTERFACE_BRAM_IMUX19",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX0",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L20",
|
||||
"INT_INTERFACE_BRAM_IMUX39",
|
||||
"INT_INTERFACE_WW2END2",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B1",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L18",
|
||||
"INT_INTERFACE_NW4END0",
|
||||
"INT_INTERFACE_EE4C1",
|
||||
"INT_INTERFACE_LH3",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX39",
|
||||
"INT_INTERFACE_BRAM_IMUX3",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B15",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX22",
|
||||
"INT_INTERFACE_WW4A3",
|
||||
"INT_INTERFACE_WW4END2",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX24",
|
||||
"INT_INTERFACE_BRAM_IMUX43",
|
||||
"INT_INTERFACE_BRAM_IMUX21",
|
||||
"INT_INTERFACE_MONITOR_N",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B2",
|
||||
"INT_INTERFACE_NE2A3",
|
||||
"INT_INTERFACE_NW4A2",
|
||||
"INT_INTERFACE_BRAM_IMUX28",
|
||||
"INT_INTERFACE_EL1BEG3",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX32",
|
||||
"L_INT_INTER_DQS_IOTOPHASER",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L22",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX6",
|
||||
"INT_INTERFACE_SE2A2",
|
||||
"INT_INTERFACE_LH7",
|
||||
"INT_INTERFACE_EL1BEG0",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX25",
|
||||
"INT_INTERFACE_BRAM_IMUX14",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B6",
|
||||
"INT_INTERFACE_SW4A2",
|
||||
"INT_INTERFACE_SE4BEG0",
|
||||
"INT_INTERFACE_CLK1",
|
||||
"INT_INTERFACE_EE4BEG2",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B0",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L3",
|
||||
"INT_INTERFACE_PHASER_TO_IO_OCLKDIV",
|
||||
"INT_INTERFACE_NW4END1",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX35",
|
||||
"INT_INTERFACE_EL1BEG2",
|
||||
"INT_INTERFACE_BRAM_IMUX11",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX4",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX20",
|
||||
"INT_INTERFACE_NE4C3",
|
||||
"INT_INTERFACE_BRAM_IMUX40",
|
||||
"INT_INTERFACE_WW2A2",
|
||||
"INT_INTERFACE_BRAM_IMUX26",
|
||||
"INT_INTERFACE_LH8",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B3",
|
||||
"INT_INTERFACE_NW4A1",
|
||||
"INT_INTERFACE_BRAM_IMUX44",
|
||||
"INT_INTERFACE_FAN0",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L10",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B4",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX18",
|
||||
"INT_INTERFACE_MONITOR_P",
|
||||
"INT_INTERFACE_EE2BEG3",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX47",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L11",
|
||||
"INT_INTERFACE_BRAM_IMUX24",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L19",
|
||||
"INT_INTERFACE_SE4BEG2",
|
||||
"INT_INTERFACE_BRAM_IMUX27",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX12",
|
||||
"INT_INTERFACE_BRAM_IMUX4",
|
||||
"INT_INTERFACE_EE4C0",
|
||||
"INT_INTERFACE_WL1END2",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L5",
|
||||
"INT_INTERFACE_BRAM_IMUX8",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B17",
|
||||
"INT_INTERFACE_NW4END2",
|
||||
"INT_INTERFACE_BRAM_IMUX16",
|
||||
"INT_INTERFACE_BLOCK_OUTS_L_B0",
|
||||
"INT_INTERFACE_NW2A2",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX43",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L23",
|
||||
"INT_INTERFACE_WW4END3",
|
||||
"INT_INTERFACE_BYP2",
|
||||
"INT_INTERFACE_SE2A3",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L8",
|
||||
"INT_INTERFACE_EE4BEG1",
|
||||
"INT_INTERFACE_BRAM_IMUX35",
|
||||
"INT_INTERFACE_BRAM_IMUX41",
|
||||
"INT_INTERFACE_WW2END3",
|
||||
"INT_INTERFACE_SW4END2",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX3",
|
||||
"INT_INTERFACE_WW4END0",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B23",
|
||||
"INT_INTERFACE_CLK0",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX15",
|
||||
"INT_INTERFACE_NE2A1",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX37",
|
||||
"INT_INTERFACE_PHASER_TO_IO_ICLKDIV",
|
||||
"INT_INTERFACE_NE4BEG1",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX31",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B16",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX7",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX44",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX21",
|
||||
"INT_INTERFACE_BYP5",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L15",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B11",
|
||||
"INT_INTERFACE_WW4B1",
|
||||
"INT_INTERFACE_NE4BEG0",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX14",
|
||||
"INT_INTERFACE_NE4C2",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX26",
|
||||
"INT_INTERFACE_WR1END2",
|
||||
"INT_INTERFACE_BRAM_IMUX0",
|
||||
"INT_INTERFACE_EE2BEG0",
|
||||
"INT_INTERFACE_BRAM_IMUX31",
|
||||
"INT_INTERFACE_BRAM_IMUX34",
|
||||
"INT_INTERFACE_PHASER_TO_IO_ICLK",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L6",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B14",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX45",
|
||||
"INT_INTERFACE_ER1BEG0",
|
||||
"INT_INTERFACE_NW2A3",
|
||||
"INT_INTERFACE_BRAM_IMUX23",
|
||||
"INT_INTERFACE_WR1END3",
|
||||
"INT_INTERFACE_LH12",
|
||||
"INT_INTERFACE_ER1BEG2",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B7",
|
||||
"INT_INTERFACE_NE4C0",
|
||||
"INT_INTERFACE_SE4BEG3",
|
||||
"INT_INTERFACE_PHASER_TO_IO_OCLK",
|
||||
"INT_INTERFACE_WW2END0",
|
||||
"INT_INTERFACE_WW4C0",
|
||||
"INT_INTERFACE_WL1END1",
|
||||
"INT_INTERFACE_NW2A0",
|
||||
"INT_INTERFACE_EE2A2",
|
||||
"INT_INTERFACE_BRAM_IMUX22",
|
||||
"INT_INTERFACE_EE4B2",
|
||||
"INT_INTERFACE_FAN6",
|
||||
"INT_INTERFACE_WW2END1",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B20",
|
||||
"INT_INTERFACE_LH2",
|
||||
"INT_INTERFACE_NW4A0",
|
||||
"INT_INTERFACE_SW2A2",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L14",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX33",
|
||||
"INT_INTERFACE_EE4B1",
|
||||
"INT_INTERFACE_WW4B2",
|
||||
"INT_INTERFACE_EE4C2",
|
||||
"INT_INTERFACE_SW4END1",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B12",
|
||||
"INT_INTERFACE_PHASER_TO_IO_OCLK1X_90",
|
||||
"INT_INTERFACE_SW2A0",
|
||||
"INT_INTERFACE_BRAM_IMUX45",
|
||||
"INT_INTERFACE_SW2A3",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX10",
|
||||
"INT_INTERFACE_BRAM_IMUX32",
|
||||
"INT_INTERFACE_EE4A3",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L2",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L0",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX9",
|
||||
"INT_INTERFACE_BRAM_IMUX12",
|
||||
"INT_INTERFACE_BRAM_IMUX17",
|
||||
"INT_INTERFACE_BRAM_IMUX2",
|
||||
"INT_INTERFACE_ER1BEG3",
|
||||
"INT_INTERFACE_WW4A2",
|
||||
"INT_INTERFACE_NE4C1",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX29",
|
||||
"INT_INTERFACE_BLOCK_OUTS_L_B2",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B19",
|
||||
"INT_INTERFACE_NW4END3",
|
||||
"INT_INTERFACE_EE2A1",
|
||||
"INT_INTERFACE_WW2A3",
|
||||
"INT_INTERFACE_WL1END0",
|
||||
"INT_INTERFACE_BYP4",
|
||||
"INT_INTERFACE_WW2A1",
|
||||
"INT_INTERFACE_EE4B0",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX23",
|
||||
"INT_INTERFACE_FAN3",
|
||||
"INT_INTERFACE_EE4B3",
|
||||
"INT_INTERFACE_SW4A0",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX17",
|
||||
"INT_INTERFACE_SE2A1",
|
||||
"INT_INTERFACE_WW4C1",
|
||||
"INT_INTERFACE_FAN5",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX40",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX34",
|
||||
"INT_INTERFACE_EE2A3",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L21",
|
||||
"INT_INTERFACE_EE4BEG3",
|
||||
"INT_INTERFACE_EE2BEG2",
|
||||
"INT_INTERFACE_BRAM_IMUX6",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX2",
|
||||
"INT_INTERFACE_BLOCK_OUTS_L_B3",
|
||||
"INT_INTERFACE_WR1END0",
|
||||
"INT_INTERFACE_BRAM_IMUX10",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L13",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX36",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B10",
|
||||
"INT_INTERFACE_WW4B0",
|
||||
"INT_INTERFACE_SW2A1",
|
||||
"INT_INTERFACE_WW2A0",
|
||||
"INT_INTERFACE_EE4A2",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B13",
|
||||
"INT_INTERFACE_EE4BEG0",
|
||||
"INT_INTERFACE_BRAM_IMUX42",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L1",
|
||||
"INT_INTERFACE_BRAM_IMUX5",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX42",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L9",
|
||||
"INT_INTERFACE_FAN2",
|
||||
"INT_INTERFACE_NW4A3",
|
||||
"INT_INTERFACE_BRAM_IMUX38",
|
||||
"INT_INTERFACE_SE2A0",
|
||||
"INT_INTERFACE_BRAM_IMUX29",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B21",
|
||||
"INT_INTERFACE_BRAM_IMUX9",
|
||||
"INT_INTERFACE_EE4C3",
|
||||
"INT_INTERFACE_BYP3",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L16",
|
||||
"INT_INTERFACE_BRAM_IMUX46",
|
||||
"INT_INTERFACE_BRAM_IMUX37",
|
||||
"INT_INTERFACE_BRAM_IMUX20",
|
||||
"INT_INTERFACE_LH1",
|
||||
"INT_INTERFACE_BYP7",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX5",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX13",
|
||||
"INT_INTERFACE_BRAM_IMUX15",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B22",
|
||||
"INT_INTERFACE_SE4BEG1",
|
||||
"INT_INTERFACE_BRAM_IMUX47",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX38",
|
||||
"INT_INTERFACE_SE4C3",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L7",
|
||||
"INT_INTERFACE_BRAM_IMUX1",
|
||||
"INT_INTERFACE_NE2A2",
|
||||
"INT_INTERFACE_FAN7",
|
||||
"INT_INTERFACE_EE2BEG1",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX16",
|
||||
"INT_INTERFACE_WW4A0",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B8",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L17",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX19",
|
||||
"INT_INTERFACE_LH4",
|
||||
"INT_INTERFACE_SE4C1",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX1",
|
||||
"INT_INTERFACE_BRAM_IMUX25",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX30",
|
||||
"INT_INTERFACE_WW4A1",
|
||||
"INT_INTERFACE_BRAM_IMUX7",
|
||||
"INT_INTERFACE_FAN4",
|
||||
"INT_INTERFACE_CTRL0",
|
||||
"INT_INTERFACE_WW4C2",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B18",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX8",
|
||||
"INT_INTERFACE_LH9",
|
||||
"INT_INTERFACE_ER1BEG1",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L12",
|
||||
"INT_INTERFACE_WR1END1",
|
||||
"INT_INTERFACE_SW4END3",
|
||||
"INT_INTERFACE_BYP0",
|
||||
"INT_INTERFACE_EE2A0",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX46",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX11",
|
||||
"INT_INTERFACE_SE4C0",
|
||||
"INT_INTERFACE_LH5",
|
||||
"INT_INTERFACE_BRAM_IMUX33",
|
||||
"INT_INTERFACE_LH10",
|
||||
"INT_INTERFACE_BRAM_IMUX36",
|
||||
"INT_INTERFACE_NE2A0",
|
||||
"INT_INTERFACE_BLOCK_OUTS_L_B1",
|
||||
"INT_INTERFACE_EL1BEG1",
|
||||
"INT_INTERFACE_LH11",
|
||||
"INT_INTERFACE_SW4A1",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B5",
|
||||
"INT_INTERFACE_BYP6",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L4",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX28",
|
||||
"INT_INTERFACE_CTRL1",
|
||||
"INT_INTERFACE_BRAM_IMUX13",
|
||||
"INT_INTERFACE_EE4A1",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX41",
|
||||
"INT_INTERFACE_SW4END0",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX27"
|
||||
],
|
||||
"pips": {
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B4->>INT_INTERFACE_LOGIC_OUTS_L4": {
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B4",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L4",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B1->>INT_INTERFACE_LOGIC_OUTS_L1": {
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B1",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L1",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B17->>INT_INTERFACE_LOGIC_OUTS_L17": {
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B17",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L17",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B22->>INT_INTERFACE_LOGIC_OUTS_L22": {
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B22",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L22",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B14->>INT_INTERFACE_LOGIC_OUTS_L14": {
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B14",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L14",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B18->>INT_INTERFACE_LOGIC_OUTS_L18": {
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B18",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L18",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B21->>INT_INTERFACE_LOGIC_OUTS_L21": {
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B21",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L21",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B7->>INT_INTERFACE_LOGIC_OUTS_L7": {
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B7",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L7",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B2->>INT_INTERFACE_LOGIC_OUTS_L2": {
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B2",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L2",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B19->>INT_INTERFACE_LOGIC_OUTS_L19": {
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B19",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L19",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B11->>INT_INTERFACE_LOGIC_OUTS_L11": {
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B11",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L11",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B23->>INT_INTERFACE_LOGIC_OUTS_L23": {
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B23",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L23",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B3->>INT_INTERFACE_LOGIC_OUTS_L3": {
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B3",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L3",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B6->>INT_INTERFACE_LOGIC_OUTS_L6": {
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B6",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L6",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B0->>INT_INTERFACE_LOGIC_OUTS_L0": {
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B0",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L0",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B13->>INT_INTERFACE_LOGIC_OUTS_L13": {
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B13",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L13",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B12->>INT_INTERFACE_LOGIC_OUTS_L12": {
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B12",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L12",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B15->>INT_INTERFACE_LOGIC_OUTS_L15": {
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B15",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L15",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B20->>INT_INTERFACE_LOGIC_OUTS_L20": {
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B20",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L20",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B10->>INT_INTERFACE_LOGIC_OUTS_L10": {
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B10",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L10",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B16->>INT_INTERFACE_LOGIC_OUTS_L16": {
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B16",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L16",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B9->>INT_INTERFACE_LOGIC_OUTS_L9": {
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B9",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L9",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B8->>INT_INTERFACE_LOGIC_OUTS_L8": {
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B8",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L8",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B5->>INT_INTERFACE_LOGIC_OUTS_L5": {
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B5",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L5",
|
||||
"can_invert": "0"
|
||||
}
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B12->>INT_INTERFACE_LOGIC_OUTS_L12": {
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B12",
|
||||
"can_invert": "0",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L12"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B14->>INT_INTERFACE_LOGIC_OUTS_L14": {
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B14",
|
||||
"can_invert": "0",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L14"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B5->>INT_INTERFACE_LOGIC_OUTS_L5": {
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B5",
|
||||
"can_invert": "0",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L5"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B22->>INT_INTERFACE_LOGIC_OUTS_L22": {
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B22",
|
||||
"can_invert": "0",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L22"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B21->>INT_INTERFACE_LOGIC_OUTS_L21": {
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B21",
|
||||
"can_invert": "0",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L21"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B1->>INT_INTERFACE_LOGIC_OUTS_L1": {
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B1",
|
||||
"can_invert": "0",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L1"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B9->>INT_INTERFACE_LOGIC_OUTS_L9": {
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B9",
|
||||
"can_invert": "0",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L9"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B18->>INT_INTERFACE_LOGIC_OUTS_L18": {
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B18",
|
||||
"can_invert": "0",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L18"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B23->>INT_INTERFACE_LOGIC_OUTS_L23": {
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B23",
|
||||
"can_invert": "0",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L23"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B6->>INT_INTERFACE_LOGIC_OUTS_L6": {
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B6",
|
||||
"can_invert": "0",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L6"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B3->>INT_INTERFACE_LOGIC_OUTS_L3": {
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B3",
|
||||
"can_invert": "0",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L3"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B17->>INT_INTERFACE_LOGIC_OUTS_L17": {
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B17",
|
||||
"can_invert": "0",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L17"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B15->>INT_INTERFACE_LOGIC_OUTS_L15": {
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B15",
|
||||
"can_invert": "0",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L15"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B4->>INT_INTERFACE_LOGIC_OUTS_L4": {
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B4",
|
||||
"can_invert": "0",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L4"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B19->>INT_INTERFACE_LOGIC_OUTS_L19": {
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B19",
|
||||
"can_invert": "0",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L19"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B11->>INT_INTERFACE_LOGIC_OUTS_L11": {
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B11",
|
||||
"can_invert": "0",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L11"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B7->>INT_INTERFACE_LOGIC_OUTS_L7": {
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B7",
|
||||
"can_invert": "0",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L7"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B20->>INT_INTERFACE_LOGIC_OUTS_L20": {
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B20",
|
||||
"can_invert": "0",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L20"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B2->>INT_INTERFACE_LOGIC_OUTS_L2": {
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B2",
|
||||
"can_invert": "0",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L2"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B13->>INT_INTERFACE_LOGIC_OUTS_L13": {
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B13",
|
||||
"can_invert": "0",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L13"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B16->>INT_INTERFACE_LOGIC_OUTS_L16": {
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B16",
|
||||
"can_invert": "0",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L16"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B10->>INT_INTERFACE_LOGIC_OUTS_L10": {
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B10",
|
||||
"can_invert": "0",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L10"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B8->>INT_INTERFACE_LOGIC_OUTS_L8": {
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B8",
|
||||
"can_invert": "0",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L8"
|
||||
}
|
||||
},
|
||||
"wires": [
|
||||
"INT_INTERFACE_SE4BEG1",
|
||||
"INT_INTERFACE_WL1END2",
|
||||
"INT_INTERFACE_WR1END1",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B11",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L13",
|
||||
"INT_INTERFACE_EE4A1",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B3",
|
||||
"INT_INTERFACE_WW4A1",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L19",
|
||||
"INT_INTERFACE_BRAM_IMUX9",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B6",
|
||||
"INT_INTERFACE_SW2A2",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L1",
|
||||
"INT_INTERFACE_SW2A3",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX25",
|
||||
"INT_INTERFACE_SE4BEG2",
|
||||
"INT_INTERFACE_BRAM_IMUX28",
|
||||
"INT_INTERFACE_WW4A3",
|
||||
"INT_INTERFACE_CLK1",
|
||||
"INT_INTERFACE_LH8",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX41",
|
||||
"INT_INTERFACE_BRAM_IMUX22",
|
||||
"INT_INTERFACE_WW4C0",
|
||||
"INT_INTERFACE_WW4B1",
|
||||
"INT_INTERFACE_BLOCK_OUTS_L_B0",
|
||||
"INT_INTERFACE_BRAM_IMUX16",
|
||||
"INT_INTERFACE_WW2A2",
|
||||
"INT_INTERFACE_EE4A2",
|
||||
"INT_INTERFACE_WW2END0",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B1",
|
||||
"INT_INTERFACE_BRAM_IMUX43",
|
||||
"INT_INTERFACE_BRAM_IMUX45",
|
||||
"INT_INTERFACE_EE4C1",
|
||||
"INT_INTERFACE_BRAM_IMUX7",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX14",
|
||||
"INT_INTERFACE_SW4A3",
|
||||
"INT_INTERFACE_EE2BEG3",
|
||||
"INT_INTERFACE_NE4BEG2",
|
||||
"INT_INTERFACE_WW2END1",
|
||||
"INT_INTERFACE_SE4C3",
|
||||
"INT_INTERFACE_LH11",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B7",
|
||||
"INT_INTERFACE_SE4C0",
|
||||
"INT_INTERFACE_EE4BEG2",
|
||||
"INT_INTERFACE_BRAM_IMUX36",
|
||||
"INT_INTERFACE_BYP7",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX28",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L8",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX42",
|
||||
"INT_INTERFACE_ER1BEG2",
|
||||
"INT_INTERFACE_WW2END2",
|
||||
"INT_INTERFACE_EE4BEG3",
|
||||
"INT_INTERFACE_SE4BEG0",
|
||||
"INT_INTERFACE_WL1END1",
|
||||
"INT_INTERFACE_PHASER_TO_IO_OCLK1X_90",
|
||||
"INT_INTERFACE_NE2A0",
|
||||
"INT_INTERFACE_BRAM_IMUX19",
|
||||
"INT_INTERFACE_FAN0",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B4",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B10",
|
||||
"INT_INTERFACE_BRAM_IMUX3",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L5",
|
||||
"INT_INTERFACE_BRAM_IMUX14",
|
||||
"INT_INTERFACE_EE2BEG1",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B14",
|
||||
"INT_INTERFACE_BRAM_IMUX40",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B5",
|
||||
"INT_INTERFACE_EL1BEG0",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX29",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX8",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX22",
|
||||
"INT_INTERFACE_BRAM_IMUX12",
|
||||
"INT_INTERFACE_MONITOR_P",
|
||||
"INT_INTERFACE_CLK0",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B20",
|
||||
"INT_INTERFACE_NW4A1",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX7",
|
||||
"INT_INTERFACE_BLOCK_OUTS_L_B2",
|
||||
"INT_INTERFACE_WR1END0",
|
||||
"INT_INTERFACE_NW4END0",
|
||||
"INT_INTERFACE_EE2A2",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX26",
|
||||
"INT_INTERFACE_BYP0",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX39",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX44",
|
||||
"INT_INTERFACE_FAN6",
|
||||
"INT_INTERFACE_SW2A0",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX46",
|
||||
"INT_INTERFACE_NW4END3",
|
||||
"INT_INTERFACE_BRAM_IMUX18",
|
||||
"INT_INTERFACE_EE4B0",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L22",
|
||||
"INT_INTERFACE_SW4END0",
|
||||
"INT_INTERFACE_NE4C0",
|
||||
"INT_INTERFACE_EE4A3",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L3",
|
||||
"INT_INTERFACE_WW4C2",
|
||||
"INT_INTERFACE_BRAM_IMUX5",
|
||||
"INT_INTERFACE_EE4C2",
|
||||
"INT_INTERFACE_WW4B3",
|
||||
"INT_INTERFACE_EE2BEG2",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX19",
|
||||
"INT_INTERFACE_EE4C3",
|
||||
"INT_INTERFACE_WW4C1",
|
||||
"INT_INTERFACE_SE4C2",
|
||||
"INT_INTERFACE_BRAM_IMUX32",
|
||||
"INT_INTERFACE_BLOCK_OUTS_L_B1",
|
||||
"INT_INTERFACE_BRAM_IMUX15",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L23",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L11",
|
||||
"INT_INTERFACE_BRAM_IMUX37",
|
||||
"INT_INTERFACE_EL1BEG1",
|
||||
"INT_INTERFACE_PHASER_TO_IO_ICLKDIV",
|
||||
"INT_INTERFACE_WL1END3",
|
||||
"INT_INTERFACE_BRAM_IMUX27",
|
||||
"INT_INTERFACE_SW4A2",
|
||||
"INT_INTERFACE_ER1BEG3",
|
||||
"INT_INTERFACE_LH6",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX38",
|
||||
"INT_INTERFACE_SW4A1",
|
||||
"INT_INTERFACE_SW4A0",
|
||||
"INT_INTERFACE_BYP2",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX3",
|
||||
"INT_INTERFACE_NE2A1",
|
||||
"INT_INTERFACE_WL1END0",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B19",
|
||||
"INT_INTERFACE_WW4B0",
|
||||
"INT_INTERFACE_CTRL0",
|
||||
"INT_INTERFACE_WW2END3",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B16",
|
||||
"INT_INTERFACE_NE4BEG3",
|
||||
"INT_INTERFACE_BRAM_IMUX8",
|
||||
"INT_INTERFACE_SE2A0",
|
||||
"INT_INTERFACE_PHASER_TO_IO_ICLK",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B9",
|
||||
"INT_INTERFACE_EE4B2",
|
||||
"INT_INTERFACE_NE2A2",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX31",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX32",
|
||||
"INT_INTERFACE_NW2A1",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX33",
|
||||
"INT_INTERFACE_FAN7",
|
||||
"INT_INTERFACE_EE2BEG0",
|
||||
"INT_INTERFACE_LH1",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX37",
|
||||
"INT_INTERFACE_BRAM_IMUX17",
|
||||
"INT_INTERFACE_BRAM_IMUX13",
|
||||
"INT_INTERFACE_LH5",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX4",
|
||||
"INT_INTERFACE_SW4END2",
|
||||
"INT_INTERFACE_LH4",
|
||||
"INT_INTERFACE_LH12",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L18",
|
||||
"INT_INTERFACE_NW2A3",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L16",
|
||||
"INT_INTERFACE_BRAM_IMUX2",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX36",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B8",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX2",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L2",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX0",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B12",
|
||||
"INT_INTERFACE_EL1BEG3",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B15",
|
||||
"INT_INTERFACE_BLOCK_OUTS_L_B3",
|
||||
"INT_INTERFACE_SE4BEG3",
|
||||
"INT_INTERFACE_BRAM_IMUX39",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B22",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B0",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B17",
|
||||
"INT_INTERFACE_BRAM_IMUX31",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B2",
|
||||
"INT_INTERFACE_WW4END1",
|
||||
"INT_INTERFACE_BRAM_IMUX29",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX45",
|
||||
"INT_INTERFACE_BRAM_IMUX21",
|
||||
"INT_INTERFACE_WW2A3",
|
||||
"INT_INTERFACE_BRAM_IMUX4",
|
||||
"INT_INTERFACE_BRAM_IMUX0",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX6",
|
||||
"INT_INTERFACE_SE4C1",
|
||||
"INT_INTERFACE_NE4C2",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B13",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX18",
|
||||
"INT_INTERFACE_WW4END2",
|
||||
"INT_INTERFACE_PHASER_TO_IO_OCLK",
|
||||
"INT_INTERFACE_EE2A3",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX1",
|
||||
"INT_INTERFACE_EE4A0",
|
||||
"INT_INTERFACE_WW4A0",
|
||||
"INT_INTERFACE_FAN4",
|
||||
"INT_INTERFACE_BYP1",
|
||||
"INT_INTERFACE_FAN3",
|
||||
"INT_INTERFACE_BYP3",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX35",
|
||||
"INT_INTERFACE_CTRL1",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L10",
|
||||
"INT_INTERFACE_NW4A3",
|
||||
"INT_INTERFACE_MONITOR_N",
|
||||
"INT_INTERFACE_BRAM_IMUX6",
|
||||
"INT_INTERFACE_BRAM_IMUX33",
|
||||
"INT_INTERFACE_LH7",
|
||||
"INT_INTERFACE_BYP5",
|
||||
"INT_INTERFACE_NW2A2",
|
||||
"INT_INTERFACE_BRAM_IMUX44",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L9",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX16",
|
||||
"INT_INTERFACE_SE2A1",
|
||||
"INT_INTERFACE_BRAM_IMUX11",
|
||||
"INT_INTERFACE_BRAM_IMUX41",
|
||||
"INT_INTERFACE_WW2A1",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX13",
|
||||
"INT_INTERFACE_BYP6",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX23",
|
||||
"INT_INTERFACE_NW4END2",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX11",
|
||||
"INT_INTERFACE_NW2A0",
|
||||
"INT_INTERFACE_EE4B3",
|
||||
"INT_INTERFACE_BRAM_IMUX42",
|
||||
"INT_INTERFACE_BRAM_IMUX35",
|
||||
"INT_INTERFACE_NE2A3",
|
||||
"INT_INTERFACE_SW4END3",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B23",
|
||||
"INT_INTERFACE_NE4C1",
|
||||
"INT_INTERFACE_NW4A2",
|
||||
"INT_INTERFACE_NW4A0",
|
||||
"INT_INTERFACE_SE2A2",
|
||||
"INT_INTERFACE_WW4END3",
|
||||
"INT_INTERFACE_BRAM_IMUX10",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L15",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX43",
|
||||
"INT_INTERFACE_WR1END2",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX40",
|
||||
"INT_INTERFACE_BYP4",
|
||||
"INT_INTERFACE_LH2",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L21",
|
||||
"INT_INTERFACE_SW2A1",
|
||||
"INT_INTERFACE_WW4A2",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX47",
|
||||
"INT_INTERFACE_BRAM_IMUX1",
|
||||
"INT_INTERFACE_SE2A3",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L20",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L14",
|
||||
"INT_INTERFACE_WW4B2",
|
||||
"INT_INTERFACE_EL1BEG2",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX15",
|
||||
"INT_INTERFACE_FAN5",
|
||||
"INT_INTERFACE_EE4C0",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX34",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX21",
|
||||
"INT_INTERFACE_EE4B1",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX17",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B18",
|
||||
"INT_INTERFACE_ER1BEG0",
|
||||
"INT_INTERFACE_EE4BEG0",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX20",
|
||||
"INT_INTERFACE_WW4END0",
|
||||
"INT_INTERFACE_FAN1",
|
||||
"INT_INTERFACE_WW4C3",
|
||||
"INT_INTERFACE_LH9",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX30",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L17",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX10",
|
||||
"INT_INTERFACE_BRAM_IMUX46",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L0",
|
||||
"INT_INTERFACE_NE4BEG0",
|
||||
"INT_INTERFACE_EE2A0",
|
||||
"INT_INTERFACE_BRAM_IMUX25",
|
||||
"INT_INTERFACE_SW4END1",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L12",
|
||||
"INT_INTERFACE_BRAM_IMUX20",
|
||||
"INT_INTERFACE_BRAM_IMUX38",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX24",
|
||||
"L_INT_INTER_DQS_IOTOPHASER",
|
||||
"INT_INTERFACE_FAN2",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L6",
|
||||
"INT_INTERFACE_BRAM_IMUX34",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX5",
|
||||
"INT_INTERFACE_EE2A1",
|
||||
"INT_INTERFACE_LH3",
|
||||
"INT_INTERFACE_NW4END1",
|
||||
"INT_INTERFACE_WR1END3",
|
||||
"INT_INTERFACE_WW2A0",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX27",
|
||||
"INT_INTERFACE_NE4C3",
|
||||
"INT_INTERFACE_BRAM_IMUX23",
|
||||
"INT_INTERFACE_BRAM_IMUX47",
|
||||
"INT_INTERFACE_BRAM_IMUX26",
|
||||
"INT_INTERFACE_PHASER_TO_IO_OCLKDIV",
|
||||
"INT_INTERFACE_BRAM_IMUX24",
|
||||
"INT_INTERFACE_NE4BEG1",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX9",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX12",
|
||||
"INT_INTERFACE_ER1BEG1",
|
||||
"INT_INTERFACE_LH10",
|
||||
"INT_INTERFACE_EE4BEG1",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L4",
|
||||
"INT_INTERFACE_BRAM_IMUX30",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L7",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B21"
|
||||
],
|
||||
"tile_type": "BRAM_INT_INTERFACE_L",
|
||||
"sites": []
|
||||
}
|
||||
"tile_type": "BRAM_INT_INTERFACE_L",
|
||||
"sites": []
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,476 +1,476 @@
|
|||
{
|
||||
"pips": {
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B5->>INT_INTERFACE_LOGIC_OUTS5": {
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B5",
|
||||
"can_invert": "0",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS5"
|
||||
"wires": [
|
||||
"INT_INTERFACE_EE4A0",
|
||||
"INT_INTERFACE_BRAM_IMUX30",
|
||||
"INT_INTERFACE_BYP1",
|
||||
"INT_INTERFACE_BRAM_IMUX18",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX5",
|
||||
"INT_INTERFACE_LOGIC_OUTS6",
|
||||
"INT_INTERFACE_SE4C2",
|
||||
"INT_INTERFACE_NW2A1",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX0",
|
||||
"INT_INTERFACE_SW4A3",
|
||||
"INT_INTERFACE_WL1END3",
|
||||
"INT_INTERFACE_WW4END1",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX14",
|
||||
"INT_INTERFACE_FAN1",
|
||||
"INT_INTERFACE_NE4BEG2",
|
||||
"INT_INTERFACE_NE4BEG3",
|
||||
"INT_INTERFACE_WW4B3",
|
||||
"INT_INTERFACE_LH6",
|
||||
"INT_INTERFACE_LOGIC_OUTS10",
|
||||
"INT_INTERFACE_LOGIC_OUTS3",
|
||||
"INT_INTERFACE_WW4C3",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B12",
|
||||
"INT_INTERFACE_BRAM_IMUX19",
|
||||
"INT_INTERFACE_BRAM_IMUX39",
|
||||
"INT_INTERFACE_WW2END2",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX30",
|
||||
"INT_INTERFACE_NW4END0",
|
||||
"INT_INTERFACE_EE4C1",
|
||||
"INT_INTERFACE_LH3",
|
||||
"INT_INTERFACE_BRAM_IMUX3",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX42",
|
||||
"INT_INTERFACE_WW4A3",
|
||||
"INT_INTERFACE_WW4END2",
|
||||
"INT_INTERFACE_BRAM_IMUX43",
|
||||
"INT_INTERFACE_BRAM_IMUX21",
|
||||
"INT_INTERFACE_LOGIC_OUTS15",
|
||||
"INT_INTERFACE_MONITOR_N",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX34",
|
||||
"INT_INTERFACE_NE2A3",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX10",
|
||||
"INT_INTERFACE_NW4A2",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B23",
|
||||
"INT_INTERFACE_LOGIC_OUTS7",
|
||||
"INT_INTERFACE_BRAM_IMUX28",
|
||||
"INT_INTERFACE_EL1BEG3",
|
||||
"L_INT_INTER_DQS_IOTOPHASER",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX17",
|
||||
"INT_INTERFACE_SE2A2",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX19",
|
||||
"INT_INTERFACE_LH7",
|
||||
"INT_INTERFACE_EL1BEG0",
|
||||
"INT_INTERFACE_BRAM_IMUX14",
|
||||
"INT_INTERFACE_LOGIC_OUTS21",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX22",
|
||||
"INT_INTERFACE_SW4A2",
|
||||
"INT_INTERFACE_SE4BEG0",
|
||||
"INT_INTERFACE_CLK1",
|
||||
"INT_INTERFACE_EE4BEG2",
|
||||
"INT_INTERFACE_BLOCK_OUTS_B3",
|
||||
"INT_INTERFACE_LOGIC_OUTS19",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX13",
|
||||
"INT_INTERFACE_PHASER_TO_IO_OCLKDIV",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX45",
|
||||
"INT_INTERFACE_LOGIC_OUTS12",
|
||||
"INT_INTERFACE_NW4END1",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX33",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B11",
|
||||
"INT_INTERFACE_BRAM_IMUX11",
|
||||
"INT_INTERFACE_BLOCK_OUTS_B2",
|
||||
"INT_INTERFACE_EL1BEG2",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX37",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B8",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX43",
|
||||
"INT_INTERFACE_BRAM_IMUX40",
|
||||
"INT_INTERFACE_NE4C3",
|
||||
"INT_INTERFACE_WW2A2",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B0",
|
||||
"INT_INTERFACE_BRAM_IMUX26",
|
||||
"INT_INTERFACE_LH8",
|
||||
"INT_INTERFACE_NW4A1",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX3",
|
||||
"INT_INTERFACE_BRAM_IMUX44",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX2",
|
||||
"INT_INTERFACE_FAN0",
|
||||
"INT_INTERFACE_LOGIC_OUTS0",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX29",
|
||||
"INT_INTERFACE_EE2BEG3",
|
||||
"INT_INTERFACE_MONITOR_P",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX12",
|
||||
"INT_INTERFACE_BRAM_IMUX24",
|
||||
"INT_INTERFACE_SE4BEG2",
|
||||
"INT_INTERFACE_BRAM_IMUX27",
|
||||
"INT_INTERFACE_BRAM_IMUX4",
|
||||
"INT_INTERFACE_EE4C0",
|
||||
"INT_INTERFACE_WL1END2",
|
||||
"INT_INTERFACE_BRAM_IMUX8",
|
||||
"INT_INTERFACE_NW4END2",
|
||||
"INT_INTERFACE_BLOCK_OUTS_B1",
|
||||
"INT_INTERFACE_BRAM_IMUX16",
|
||||
"INT_INTERFACE_NW2A2",
|
||||
"INT_INTERFACE_WW4END3",
|
||||
"INT_INTERFACE_BYP2",
|
||||
"INT_INTERFACE_SE2A3",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX8",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B20",
|
||||
"INT_INTERFACE_EE4BEG1",
|
||||
"INT_INTERFACE_BRAM_IMUX35",
|
||||
"INT_INTERFACE_BRAM_IMUX41",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX15",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX36",
|
||||
"INT_INTERFACE_SW4END2",
|
||||
"INT_INTERFACE_WW2END3",
|
||||
"INT_INTERFACE_WW4END0",
|
||||
"INT_INTERFACE_CLK0",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B9",
|
||||
"INT_INTERFACE_NE2A1",
|
||||
"INT_INTERFACE_PHASER_TO_IO_ICLKDIV",
|
||||
"INT_INTERFACE_LOGIC_OUTS4",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX39",
|
||||
"INT_INTERFACE_NE4BEG1",
|
||||
"INT_INTERFACE_LOGIC_OUTS18",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B13",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX4",
|
||||
"INT_INTERFACE_BYP5",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B1",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX21",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B6",
|
||||
"INT_INTERFACE_WW4B1",
|
||||
"INT_INTERFACE_NE4BEG0",
|
||||
"INT_INTERFACE_LOGIC_OUTS8",
|
||||
"INT_INTERFACE_NE4C2",
|
||||
"INT_INTERFACE_WR1END2",
|
||||
"INT_INTERFACE_BRAM_IMUX0",
|
||||
"INT_INTERFACE_EE2BEG0",
|
||||
"INT_INTERFACE_BRAM_IMUX31",
|
||||
"INT_INTERFACE_BRAM_IMUX34",
|
||||
"INT_INTERFACE_PHASER_TO_IO_ICLK",
|
||||
"INT_INTERFACE_LOGIC_OUTS1",
|
||||
"INT_INTERFACE_ER1BEG0",
|
||||
"INT_INTERFACE_LOGIC_OUTS13",
|
||||
"INT_INTERFACE_NW2A3",
|
||||
"INT_INTERFACE_BRAM_IMUX23",
|
||||
"INT_INTERFACE_WR1END3",
|
||||
"INT_INTERFACE_LH12",
|
||||
"INT_INTERFACE_LOGIC_OUTS5",
|
||||
"INT_INTERFACE_NE4C0",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX7",
|
||||
"INT_INTERFACE_SE4BEG3",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B4",
|
||||
"INT_INTERFACE_PHASER_TO_IO_OCLK",
|
||||
"INT_INTERFACE_WW2END0",
|
||||
"INT_INTERFACE_WW4C0",
|
||||
"INT_INTERFACE_WL1END1",
|
||||
"INT_INTERFACE_NW2A0",
|
||||
"INT_INTERFACE_EE2A2",
|
||||
"INT_INTERFACE_BRAM_IMUX22",
|
||||
"INT_INTERFACE_EE4B2",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX32",
|
||||
"INT_INTERFACE_FAN6",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B3",
|
||||
"INT_INTERFACE_WW2END1",
|
||||
"INT_INTERFACE_LH2",
|
||||
"INT_INTERFACE_NW4A0",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX24",
|
||||
"INT_INTERFACE_SW2A2",
|
||||
"INT_INTERFACE_EE4B1",
|
||||
"INT_INTERFACE_WW4B2",
|
||||
"INT_INTERFACE_EE4C2",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B14",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX41",
|
||||
"INT_INTERFACE_SW4END1",
|
||||
"INT_INTERFACE_PHASER_TO_IO_OCLK1X_90",
|
||||
"INT_INTERFACE_SW2A0",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX18",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX40",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B19",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX38",
|
||||
"INT_INTERFACE_BRAM_IMUX45",
|
||||
"INT_INTERFACE_SW2A3",
|
||||
"INT_INTERFACE_LOGIC_OUTS11",
|
||||
"INT_INTERFACE_BRAM_IMUX32",
|
||||
"INT_INTERFACE_EE4A3",
|
||||
"INT_INTERFACE_BRAM_IMUX12",
|
||||
"INT_INTERFACE_BRAM_IMUX17",
|
||||
"INT_INTERFACE_BRAM_IMUX2",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B2",
|
||||
"INT_INTERFACE_ER1BEG3",
|
||||
"INT_INTERFACE_WW4A2",
|
||||
"INT_INTERFACE_NE4C1",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B22",
|
||||
"INT_INTERFACE_NW4END3",
|
||||
"INT_INTERFACE_EE2A1",
|
||||
"INT_INTERFACE_WW2A3",
|
||||
"INT_INTERFACE_WL1END0",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B17",
|
||||
"INT_INTERFACE_WW2A1",
|
||||
"INT_INTERFACE_BYP4",
|
||||
"INT_INTERFACE_FAN3",
|
||||
"INT_INTERFACE_EE4B0",
|
||||
"INT_INTERFACE_EE4B3",
|
||||
"INT_INTERFACE_SW4A0",
|
||||
"INT_INTERFACE_SE2A1",
|
||||
"INT_INTERFACE_WW4C1",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX9",
|
||||
"INT_INTERFACE_FAN5",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX25",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B5",
|
||||
"INT_INTERFACE_EE2A3",
|
||||
"INT_INTERFACE_EE4BEG3",
|
||||
"INT_INTERFACE_EE2BEG2",
|
||||
"INT_INTERFACE_BRAM_IMUX6",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX6",
|
||||
"INT_INTERFACE_WR1END0",
|
||||
"INT_INTERFACE_BRAM_IMUX10",
|
||||
"INT_INTERFACE_LOGIC_OUTS23",
|
||||
"INT_INTERFACE_WW4B0",
|
||||
"INT_INTERFACE_SW2A1",
|
||||
"INT_INTERFACE_WW2A0",
|
||||
"INT_INTERFACE_EE4A2",
|
||||
"INT_INTERFACE_LOGIC_OUTS20",
|
||||
"INT_INTERFACE_EE4BEG0",
|
||||
"INT_INTERFACE_BRAM_IMUX42",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B18",
|
||||
"INT_INTERFACE_BRAM_IMUX5",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B10",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B21",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX28",
|
||||
"INT_INTERFACE_FAN2",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX20",
|
||||
"INT_INTERFACE_NW4A3",
|
||||
"INT_INTERFACE_BRAM_IMUX38",
|
||||
"INT_INTERFACE_LOGIC_OUTS14",
|
||||
"INT_INTERFACE_SE2A0",
|
||||
"INT_INTERFACE_BRAM_IMUX29",
|
||||
"INT_INTERFACE_BRAM_IMUX9",
|
||||
"INT_INTERFACE_EE4C3",
|
||||
"INT_INTERFACE_BYP3",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX11",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B7",
|
||||
"INT_INTERFACE_BRAM_IMUX46",
|
||||
"INT_INTERFACE_BRAM_IMUX37",
|
||||
"INT_INTERFACE_BRAM_IMUX20",
|
||||
"INT_INTERFACE_LH1",
|
||||
"INT_INTERFACE_BYP7",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B15",
|
||||
"INT_INTERFACE_BRAM_IMUX15",
|
||||
"INT_INTERFACE_SE4BEG1",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX44",
|
||||
"INT_INTERFACE_BRAM_IMUX47",
|
||||
"INT_INTERFACE_SE4C3",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX23",
|
||||
"INT_INTERFACE_BRAM_IMUX1",
|
||||
"INT_INTERFACE_NE2A2",
|
||||
"INT_INTERFACE_FAN7",
|
||||
"INT_INTERFACE_EE2BEG1",
|
||||
"INT_INTERFACE_WW4A0",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX35",
|
||||
"INT_INTERFACE_LH4",
|
||||
"INT_INTERFACE_LOGIC_OUTS17",
|
||||
"INT_INTERFACE_SE4C1",
|
||||
"INT_INTERFACE_BRAM_IMUX25",
|
||||
"INT_INTERFACE_BRAM_IMUX7",
|
||||
"INT_INTERFACE_LOGIC_OUTS16",
|
||||
"INT_INTERFACE_WW4A1",
|
||||
"INT_INTERFACE_FAN4",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX31",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX27",
|
||||
"INT_INTERFACE_CTRL0",
|
||||
"INT_INTERFACE_WW4C2",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX47",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX26",
|
||||
"INT_INTERFACE_LH9",
|
||||
"INT_INTERFACE_ER1BEG1",
|
||||
"INT_INTERFACE_WR1END1",
|
||||
"INT_INTERFACE_LOGIC_OUTS22",
|
||||
"INT_INTERFACE_SW4END3",
|
||||
"INT_INTERFACE_BYP0",
|
||||
"INT_INTERFACE_SE4C0",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX16",
|
||||
"INT_INTERFACE_LH5",
|
||||
"INT_INTERFACE_LH10",
|
||||
"INT_INTERFACE_EE2A0",
|
||||
"INT_INTERFACE_BRAM_IMUX33",
|
||||
"INT_INTERFACE_LH11",
|
||||
"INT_INTERFACE_BRAM_IMUX36",
|
||||
"INT_INTERFACE_NE2A0",
|
||||
"INT_INTERFACE_EL1BEG1",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX46",
|
||||
"INT_INTERFACE_SW4A1",
|
||||
"INT_INTERFACE_BLOCK_OUTS_B0",
|
||||
"INT_INTERFACE_LOGIC_OUTS9",
|
||||
"INT_INTERFACE_BYP6",
|
||||
"INT_INTERFACE_CTRL1",
|
||||
"INT_INTERFACE_BRAM_IMUX13",
|
||||
"INT_INTERFACE_EE4A1",
|
||||
"INT_INTERFACE_LOGIC_OUTS2",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B16",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX1",
|
||||
"INT_INTERFACE_SW4END0",
|
||||
"INT_INTERFACE_ER1BEG2"
|
||||
],
|
||||
"pips": {
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B10->>INT_INTERFACE_LOGIC_OUTS10": {
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B10",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS10",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B16->>INT_INTERFACE_LOGIC_OUTS16": {
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B16",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS16",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B4->>INT_INTERFACE_LOGIC_OUTS4": {
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B4",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS4",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B7->>INT_INTERFACE_LOGIC_OUTS7": {
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B7",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS7",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B1->>INT_INTERFACE_LOGIC_OUTS1": {
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B1",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS1",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B12->>INT_INTERFACE_LOGIC_OUTS12": {
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B12",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS12",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B5->>INT_INTERFACE_LOGIC_OUTS5": {
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B5",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS5",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B15->>INT_INTERFACE_LOGIC_OUTS15": {
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B15",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS15",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B18->>INT_INTERFACE_LOGIC_OUTS18": {
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B18",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS18",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B2->>INT_INTERFACE_LOGIC_OUTS2": {
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B2",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS2",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B19->>INT_INTERFACE_LOGIC_OUTS19": {
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B19",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS19",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B6->>INT_INTERFACE_LOGIC_OUTS6": {
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B6",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS6",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B11->>INT_INTERFACE_LOGIC_OUTS11": {
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B11",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS11",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B8->>INT_INTERFACE_LOGIC_OUTS8": {
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B8",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS8",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B3->>INT_INTERFACE_LOGIC_OUTS3": {
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B3",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS3",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B21->>INT_INTERFACE_LOGIC_OUTS21": {
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B21",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS21",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B20->>INT_INTERFACE_LOGIC_OUTS20": {
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B20",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS20",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B14->>INT_INTERFACE_LOGIC_OUTS14": {
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B14",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS14",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B17->>INT_INTERFACE_LOGIC_OUTS17": {
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B17",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS17",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B9->>INT_INTERFACE_LOGIC_OUTS9": {
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B9",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS9",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B23->>INT_INTERFACE_LOGIC_OUTS23": {
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B23",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS23",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B22->>INT_INTERFACE_LOGIC_OUTS22": {
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B22",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS22",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B13->>INT_INTERFACE_LOGIC_OUTS13": {
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B13",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS13",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B0->>INT_INTERFACE_LOGIC_OUTS0": {
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B0",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS0",
|
||||
"can_invert": "0"
|
||||
}
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B20->>INT_INTERFACE_LOGIC_OUTS20": {
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B20",
|
||||
"can_invert": "0",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS20"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B23->>INT_INTERFACE_LOGIC_OUTS23": {
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B23",
|
||||
"can_invert": "0",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS23"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B14->>INT_INTERFACE_LOGIC_OUTS14": {
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B14",
|
||||
"can_invert": "0",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS14"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B3->>INT_INTERFACE_LOGIC_OUTS3": {
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B3",
|
||||
"can_invert": "0",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS3"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B6->>INT_INTERFACE_LOGIC_OUTS6": {
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B6",
|
||||
"can_invert": "0",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS6"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B12->>INT_INTERFACE_LOGIC_OUTS12": {
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B12",
|
||||
"can_invert": "0",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS12"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B4->>INT_INTERFACE_LOGIC_OUTS4": {
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B4",
|
||||
"can_invert": "0",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS4"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B13->>INT_INTERFACE_LOGIC_OUTS13": {
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B13",
|
||||
"can_invert": "0",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS13"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B19->>INT_INTERFACE_LOGIC_OUTS19": {
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B19",
|
||||
"can_invert": "0",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS19"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B0->>INT_INTERFACE_LOGIC_OUTS0": {
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B0",
|
||||
"can_invert": "0",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B8->>INT_INTERFACE_LOGIC_OUTS8": {
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B8",
|
||||
"can_invert": "0",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS8"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B1->>INT_INTERFACE_LOGIC_OUTS1": {
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B1",
|
||||
"can_invert": "0",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS1"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B11->>INT_INTERFACE_LOGIC_OUTS11": {
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B11",
|
||||
"can_invert": "0",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS11"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B16->>INT_INTERFACE_LOGIC_OUTS16": {
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B16",
|
||||
"can_invert": "0",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS16"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B9->>INT_INTERFACE_LOGIC_OUTS9": {
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B9",
|
||||
"can_invert": "0",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS9"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B15->>INT_INTERFACE_LOGIC_OUTS15": {
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B15",
|
||||
"can_invert": "0",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS15"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B18->>INT_INTERFACE_LOGIC_OUTS18": {
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B18",
|
||||
"can_invert": "0",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS18"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B2->>INT_INTERFACE_LOGIC_OUTS2": {
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B2",
|
||||
"can_invert": "0",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS2"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B21->>INT_INTERFACE_LOGIC_OUTS21": {
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B21",
|
||||
"can_invert": "0",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS21"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B7->>INT_INTERFACE_LOGIC_OUTS7": {
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B7",
|
||||
"can_invert": "0",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS7"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B10->>INT_INTERFACE_LOGIC_OUTS10": {
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B10",
|
||||
"can_invert": "0",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS10"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B22->>INT_INTERFACE_LOGIC_OUTS22": {
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B22",
|
||||
"can_invert": "0",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS22"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B17->>INT_INTERFACE_LOGIC_OUTS17": {
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B17",
|
||||
"can_invert": "0",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS17"
|
||||
}
|
||||
},
|
||||
"wires": [
|
||||
"INT_INTERFACE_SE4BEG1",
|
||||
"INT_INTERFACE_WL1END2",
|
||||
"INT_INTERFACE_WR1END1",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B9",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B12",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX46",
|
||||
"INT_INTERFACE_BLOCK_OUTS_B3",
|
||||
"INT_INTERFACE_EE4A1",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX43",
|
||||
"INT_INTERFACE_WW4A1",
|
||||
"INT_INTERFACE_BRAM_IMUX9",
|
||||
"INT_INTERFACE_SW2A2",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B10",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX7",
|
||||
"INT_INTERFACE_SW2A3",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX13",
|
||||
"INT_INTERFACE_SE4BEG2",
|
||||
"INT_INTERFACE_BRAM_IMUX28",
|
||||
"INT_INTERFACE_WW4A3",
|
||||
"INT_INTERFACE_CLK1",
|
||||
"INT_INTERFACE_LH8",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B22",
|
||||
"INT_INTERFACE_BRAM_IMUX22",
|
||||
"INT_INTERFACE_WW4C0",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX35",
|
||||
"INT_INTERFACE_WW4B1",
|
||||
"INT_INTERFACE_LOGIC_OUTS4",
|
||||
"INT_INTERFACE_BRAM_IMUX16",
|
||||
"INT_INTERFACE_LOGIC_OUTS1",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX34",
|
||||
"INT_INTERFACE_WW2A2",
|
||||
"INT_INTERFACE_LOGIC_OUTS0",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX9",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B11",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX25",
|
||||
"INT_INTERFACE_EE4A2",
|
||||
"INT_INTERFACE_LOGIC_OUTS20",
|
||||
"INT_INTERFACE_WW2END0",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX10",
|
||||
"INT_INTERFACE_BRAM_IMUX43",
|
||||
"INT_INTERFACE_BRAM_IMUX45",
|
||||
"INT_INTERFACE_EE4C1",
|
||||
"INT_INTERFACE_BRAM_IMUX7",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX31",
|
||||
"INT_INTERFACE_LOGIC_OUTS18",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B20",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX6",
|
||||
"INT_INTERFACE_SW4A3",
|
||||
"INT_INTERFACE_EE2BEG3",
|
||||
"INT_INTERFACE_NE4BEG2",
|
||||
"INT_INTERFACE_WW2END1",
|
||||
"INT_INTERFACE_SE4C3",
|
||||
"INT_INTERFACE_LOGIC_OUTS3",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX28",
|
||||
"INT_INTERFACE_LH11",
|
||||
"INT_INTERFACE_SE4C0",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B14",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX27",
|
||||
"INT_INTERFACE_BLOCK_OUTS_B2",
|
||||
"INT_INTERFACE_EE4BEG2",
|
||||
"INT_INTERFACE_BRAM_IMUX36",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX3",
|
||||
"INT_INTERFACE_BYP7",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B1",
|
||||
"INT_INTERFACE_ER1BEG2",
|
||||
"INT_INTERFACE_WW2END2",
|
||||
"INT_INTERFACE_EE4BEG3",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX30",
|
||||
"INT_INTERFACE_SE4BEG0",
|
||||
"INT_INTERFACE_WL1END1",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX26",
|
||||
"INT_INTERFACE_PHASER_TO_IO_OCLK1X_90",
|
||||
"INT_INTERFACE_NE2A0",
|
||||
"INT_INTERFACE_LOGIC_OUTS2",
|
||||
"INT_INTERFACE_BRAM_IMUX19",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX47",
|
||||
"INT_INTERFACE_FAN0",
|
||||
"INT_INTERFACE_BRAM_IMUX3",
|
||||
"INT_INTERFACE_BRAM_IMUX14",
|
||||
"INT_INTERFACE_EE2BEG1",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B7",
|
||||
"INT_INTERFACE_BRAM_IMUX40",
|
||||
"INT_INTERFACE_EL1BEG0",
|
||||
"INT_INTERFACE_BRAM_IMUX12",
|
||||
"INT_INTERFACE_MONITOR_P",
|
||||
"INT_INTERFACE_LOGIC_OUTS16",
|
||||
"INT_INTERFACE_CLK0",
|
||||
"INT_INTERFACE_NW4A1",
|
||||
"INT_INTERFACE_WR1END0",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX19",
|
||||
"INT_INTERFACE_NW4END0",
|
||||
"INT_INTERFACE_EE2A2",
|
||||
"INT_INTERFACE_LOGIC_OUTS8",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX0",
|
||||
"INT_INTERFACE_BYP0",
|
||||
"INT_INTERFACE_LOGIC_OUTS9",
|
||||
"INT_INTERFACE_LOGIC_OUTS17",
|
||||
"INT_INTERFACE_FAN6",
|
||||
"INT_INTERFACE_SW2A0",
|
||||
"INT_INTERFACE_NW4END3",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B21",
|
||||
"INT_INTERFACE_BRAM_IMUX18",
|
||||
"INT_INTERFACE_EE4B0",
|
||||
"INT_INTERFACE_SW4END0",
|
||||
"INT_INTERFACE_NE4C0",
|
||||
"INT_INTERFACE_EE4A3",
|
||||
"INT_INTERFACE_WW4C2",
|
||||
"INT_INTERFACE_BRAM_IMUX5",
|
||||
"INT_INTERFACE_EE4C2",
|
||||
"INT_INTERFACE_WW4B3",
|
||||
"INT_INTERFACE_EE2BEG2",
|
||||
"INT_INTERFACE_EE4C3",
|
||||
"INT_INTERFACE_WW4C1",
|
||||
"INT_INTERFACE_SE4C2",
|
||||
"INT_INTERFACE_BRAM_IMUX32",
|
||||
"INT_INTERFACE_BRAM_IMUX15",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX42",
|
||||
"INT_INTERFACE_BRAM_IMUX37",
|
||||
"INT_INTERFACE_EL1BEG1",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX41",
|
||||
"INT_INTERFACE_PHASER_TO_IO_ICLKDIV",
|
||||
"INT_INTERFACE_WL1END3",
|
||||
"INT_INTERFACE_BRAM_IMUX27",
|
||||
"INT_INTERFACE_SW4A2",
|
||||
"INT_INTERFACE_ER1BEG3",
|
||||
"INT_INTERFACE_LH6",
|
||||
"INT_INTERFACE_SW4A1",
|
||||
"INT_INTERFACE_SW4A0",
|
||||
"INT_INTERFACE_BYP2",
|
||||
"INT_INTERFACE_NE2A1",
|
||||
"INT_INTERFACE_WL1END0",
|
||||
"INT_INTERFACE_WW4B0",
|
||||
"INT_INTERFACE_CTRL0",
|
||||
"INT_INTERFACE_WW2END3",
|
||||
"INT_INTERFACE_LOGIC_OUTS14",
|
||||
"INT_INTERFACE_NE4BEG3",
|
||||
"INT_INTERFACE_LOGIC_OUTS11",
|
||||
"INT_INTERFACE_BRAM_IMUX8",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B18",
|
||||
"INT_INTERFACE_SE2A0",
|
||||
"INT_INTERFACE_PHASER_TO_IO_ICLK",
|
||||
"INT_INTERFACE_EE4B2",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX36",
|
||||
"INT_INTERFACE_NE2A2",
|
||||
"INT_INTERFACE_LOGIC_OUTS5",
|
||||
"INT_INTERFACE_NW2A1",
|
||||
"INT_INTERFACE_LOGIC_OUTS10",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX8",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX32",
|
||||
"INT_INTERFACE_FAN7",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX20",
|
||||
"INT_INTERFACE_EE2BEG0",
|
||||
"INT_INTERFACE_LH1",
|
||||
"INT_INTERFACE_BRAM_IMUX17",
|
||||
"INT_INTERFACE_BRAM_IMUX13",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B0",
|
||||
"INT_INTERFACE_LH5",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B3",
|
||||
"INT_INTERFACE_LH4",
|
||||
"INT_INTERFACE_SW4END2",
|
||||
"INT_INTERFACE_LH12",
|
||||
"INT_INTERFACE_NW2A3",
|
||||
"INT_INTERFACE_LOGIC_OUTS19",
|
||||
"INT_INTERFACE_BRAM_IMUX2",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B5",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX12",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX23",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX38",
|
||||
"INT_INTERFACE_EL1BEG3",
|
||||
"INT_INTERFACE_LOGIC_OUTS23",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B8",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B6",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B2",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B19",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX15",
|
||||
"INT_INTERFACE_SE4BEG3",
|
||||
"INT_INTERFACE_BRAM_IMUX39",
|
||||
"INT_INTERFACE_BRAM_IMUX31",
|
||||
"INT_INTERFACE_WW4END1",
|
||||
"INT_INTERFACE_BRAM_IMUX29",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX1",
|
||||
"INT_INTERFACE_BRAM_IMUX21",
|
||||
"INT_INTERFACE_WW2A3",
|
||||
"INT_INTERFACE_BRAM_IMUX4",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX16",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX44",
|
||||
"INT_INTERFACE_BRAM_IMUX0",
|
||||
"INT_INTERFACE_NE4C2",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX24",
|
||||
"INT_INTERFACE_SE4C1",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B13",
|
||||
"INT_INTERFACE_WW4END2",
|
||||
"INT_INTERFACE_PHASER_TO_IO_OCLK",
|
||||
"INT_INTERFACE_EE2A3",
|
||||
"INT_INTERFACE_EE4A0",
|
||||
"INT_INTERFACE_WW4A0",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX40",
|
||||
"INT_INTERFACE_FAN4",
|
||||
"INT_INTERFACE_BYP1",
|
||||
"INT_INTERFACE_FAN3",
|
||||
"INT_INTERFACE_CTRL1",
|
||||
"INT_INTERFACE_BYP3",
|
||||
"INT_INTERFACE_NW4A3",
|
||||
"INT_INTERFACE_MONITOR_N",
|
||||
"INT_INTERFACE_BRAM_IMUX6",
|
||||
"INT_INTERFACE_BRAM_IMUX33",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX33",
|
||||
"INT_INTERFACE_LH7",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX45",
|
||||
"INT_INTERFACE_BYP5",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B23",
|
||||
"INT_INTERFACE_NW2A2",
|
||||
"INT_INTERFACE_BRAM_IMUX44",
|
||||
"INT_INTERFACE_SE2A1",
|
||||
"INT_INTERFACE_BRAM_IMUX11",
|
||||
"INT_INTERFACE_BRAM_IMUX41",
|
||||
"INT_INTERFACE_WW2A1",
|
||||
"INT_INTERFACE_LOGIC_OUTS21",
|
||||
"INT_INTERFACE_BYP6",
|
||||
"INT_INTERFACE_NW4END2",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX18",
|
||||
"INT_INTERFACE_NW2A0",
|
||||
"INT_INTERFACE_LOGIC_OUTS12",
|
||||
"INT_INTERFACE_EE4B3",
|
||||
"INT_INTERFACE_BRAM_IMUX42",
|
||||
"INT_INTERFACE_BRAM_IMUX35",
|
||||
"INT_INTERFACE_NE2A3",
|
||||
"INT_INTERFACE_SW4END3",
|
||||
"INT_INTERFACE_NE4C1",
|
||||
"INT_INTERFACE_NW4A2",
|
||||
"INT_INTERFACE_NW4A0",
|
||||
"INT_INTERFACE_SE2A2",
|
||||
"INT_INTERFACE_WW4END3",
|
||||
"INT_INTERFACE_BRAM_IMUX10",
|
||||
"INT_INTERFACE_WR1END2",
|
||||
"INT_INTERFACE_BYP4",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX39",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX21",
|
||||
"INT_INTERFACE_LH2",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX4",
|
||||
"INT_INTERFACE_SW2A1",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B4",
|
||||
"INT_INTERFACE_WW4A2",
|
||||
"INT_INTERFACE_BRAM_IMUX1",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B17",
|
||||
"INT_INTERFACE_SE2A3",
|
||||
"INT_INTERFACE_LOGIC_OUTS7",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX11",
|
||||
"INT_INTERFACE_WW4B2",
|
||||
"INT_INTERFACE_EL1BEG2",
|
||||
"INT_INTERFACE_FAN5",
|
||||
"INT_INTERFACE_EE4C0",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX29",
|
||||
"INT_INTERFACE_EE4B1",
|
||||
"INT_INTERFACE_ER1BEG0",
|
||||
"INT_INTERFACE_EE4BEG0",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX2",
|
||||
"INT_INTERFACE_WW4END0",
|
||||
"INT_INTERFACE_FAN1",
|
||||
"INT_INTERFACE_LOGIC_OUTS15",
|
||||
"INT_INTERFACE_WW4C3",
|
||||
"INT_INTERFACE_LH9",
|
||||
"INT_INTERFACE_LOGIC_OUTS6",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX22",
|
||||
"INT_INTERFACE_BRAM_IMUX46",
|
||||
"INT_INTERFACE_NE4BEG0",
|
||||
"INT_INTERFACE_EE2A0",
|
||||
"INT_INTERFACE_BRAM_IMUX25",
|
||||
"INT_INTERFACE_SW4END1",
|
||||
"INT_INTERFACE_BRAM_IMUX20",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX17",
|
||||
"INT_INTERFACE_BRAM_IMUX38",
|
||||
"L_INT_INTER_DQS_IOTOPHASER",
|
||||
"INT_INTERFACE_FAN2",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B16",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX5",
|
||||
"INT_INTERFACE_BRAM_IMUX34",
|
||||
"INT_INTERFACE_EE2A1",
|
||||
"INT_INTERFACE_LH3",
|
||||
"INT_INTERFACE_NW4END1",
|
||||
"INT_INTERFACE_WR1END3",
|
||||
"INT_INTERFACE_LOGIC_OUTS22",
|
||||
"INT_INTERFACE_WW2A0",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX14",
|
||||
"INT_INTERFACE_BLOCK_OUTS_B0",
|
||||
"INT_INTERFACE_NE4C3",
|
||||
"INT_INTERFACE_BRAM_IMUX23",
|
||||
"INT_INTERFACE_BRAM_IMUX47",
|
||||
"INT_INTERFACE_BRAM_IMUX26",
|
||||
"INT_INTERFACE_BLOCK_OUTS_B1",
|
||||
"INT_INTERFACE_PHASER_TO_IO_OCLKDIV",
|
||||
"INT_INTERFACE_BRAM_IMUX24",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX37",
|
||||
"INT_INTERFACE_NE4BEG1",
|
||||
"INT_INTERFACE_ER1BEG1",
|
||||
"INT_INTERFACE_LH10",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B15",
|
||||
"INT_INTERFACE_EE4BEG1",
|
||||
"INT_INTERFACE_BRAM_IMUX30",
|
||||
"INT_INTERFACE_LOGIC_OUTS13"
|
||||
],
|
||||
"tile_type": "BRAM_INT_INTERFACE_R",
|
||||
"sites": []
|
||||
}
|
||||
"tile_type": "BRAM_INT_INTERFACE_R",
|
||||
"sites": []
|
||||
}
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -1,71 +1,71 @@
|
|||
{
|
||||
"pips": {},
|
||||
"wires": [
|
||||
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU3",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU11",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU11",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU13",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU6",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU7",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU11",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU1",
|
||||
"BRKH_BRAM_CASCADEA_R",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU13",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU4",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU9",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU2",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU14",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU4",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU10",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU12",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU12",
|
||||
"BRKH_BRAM_CASCADEB_R",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU5",
|
||||
"BRKH_BRAM_CASCADEB_L",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU9",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU12",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU11",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU3",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU8",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU10",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU14",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU1",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU4",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU13",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU0",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU5",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU7",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU13",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU6",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU8",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU2",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU5",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU9",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU3",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU9",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU7",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU14",
|
||||
"BRKH_BRAM_CASCADEA_L",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU4",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU0",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU10",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU6",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU7",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU2",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU0",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU5",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU2",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU0",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU3",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU8",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU10",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU8",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU6",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU12",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU1",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU14",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU1"
|
||||
],
|
||||
"tile_type": "BRKH_BRAM",
|
||||
"sites": []
|
||||
}
|
||||
"wires": [
|
||||
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU14",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU3",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU5",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU1",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU8",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU3",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU7",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU9",
|
||||
"BRKH_BRAM_CASCADEB_R",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU6",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU3",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU11",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU2",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU13",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU6",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU8",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU0",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU13",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU2",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU5",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU9",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU1",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU1",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU14",
|
||||
"BRKH_BRAM_CASCADEB_L",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU7",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU11",
|
||||
"BRKH_BRAM_CASCADEA_L",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU11",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU14",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU1",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU9",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU12",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU12",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU9",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU0",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU8",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU2",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU10",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU3",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU6",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU10",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU12",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU4",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU4",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU6",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU14",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU4",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU10",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU2",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU13",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU11",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU0",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU10",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU13",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU0",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU7",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU5",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU5",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU8",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU12",
|
||||
"BRKH_BRAM_CASCADEA_R",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU4",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU7"
|
||||
],
|
||||
"pips": {},
|
||||
"tile_type": "BRKH_BRAM",
|
||||
"sites": []
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,125 +1,125 @@
|
|||
{
|
||||
"pips": {},
|
||||
"wires": [
|
||||
"B_TERM_UTURN_INT_SW6C0",
|
||||
"B_TERM_UTURN_INT_LVB_L0",
|
||||
"B_TERM_UTURN_INT_LVB5",
|
||||
"B_TERM_UTURN_INT_SE6D3",
|
||||
"B_TERM_UTURN_INT_LV4",
|
||||
"B_TERM_UTURN_INT_SS2BEG3",
|
||||
"B_TERM_UTURN_INT_SS6B1",
|
||||
"B_TERM_UTURN_INT_SE2BEG0",
|
||||
"B_TERM_UTURN_INT_LV_L5",
|
||||
"B_TERM_UTURN_INT_SE6D1",
|
||||
"B_TERM_UTURN_INT_LV2",
|
||||
"B_TERM_UTURN_INT_LVB_L2",
|
||||
"B_TERM_UTURN_INT_SS6BEG3",
|
||||
"B_TERM_UTURN_INT_LVB1",
|
||||
"B_TERM_UTURN_INT_SL1BEG2",
|
||||
"B_TERM_UTURN_INT_SL1BEG1",
|
||||
"B_TERM_UTURN_INT_SS6BEG1",
|
||||
"B_TERM_UTURN_INT_LVB2",
|
||||
"B_TERM_UTURN_INT_SE6A2",
|
||||
"B_TERM_UTURN_INT_SS6D3",
|
||||
"B_TERM_UTURN_INT_SS6BEG0",
|
||||
"B_TERM_UTURN_INT_LV9",
|
||||
"B_TERM_UTURN_INT_SE2BEG2",
|
||||
"B_TERM_UTURN_INT_LV_L2",
|
||||
"B_TERM_UTURN_INT_SE6B2",
|
||||
"B_TERM_UTURN_INT_LVB_L3",
|
||||
"B_TERM_UTURN_INT_LV7",
|
||||
"B_TERM_UTURN_INT_SS6D2",
|
||||
"B_TERM_UTURN_INT_LVB_L4",
|
||||
"B_TERM_UTURN_INT_SW6C2",
|
||||
"B_TERM_UTURN_INT_SS6B3",
|
||||
"B_TERM_UTURN_INT_SS2A1",
|
||||
"B_TERM_UTURN_INT_SE2BEG1",
|
||||
"B_TERM_UTURN_INT_SS6A2",
|
||||
"B_TERM_UTURN_INT_SE6A0",
|
||||
"B_TERM_UTURN_INT_LV6",
|
||||
"B_TERM_UTURN_INT_LV_L6",
|
||||
"B_TERM_UTURN_INT_SS2A2",
|
||||
"B_TERM_UTURN_INT_WR1BEG0",
|
||||
"B_TERM_UTURN_INT_SE6B0",
|
||||
"B_TERM_UTURN_INT_SL1BEG0",
|
||||
"B_TERM_UTURN_INT_SW6A3",
|
||||
"B_TERM_UTURN_INT_LVB0",
|
||||
"B_TERM_UTURN_INT_LVB_L1",
|
||||
"B_TERM_UTURN_INT_SE6C0",
|
||||
"B_TERM_UTURN_INT_LV_L9",
|
||||
"B_TERM_UTURN_INT_SW6B2",
|
||||
"B_TERM_UTURN_INT_LVB3",
|
||||
"B_TERM_UTURN_INT_SW2BEG0",
|
||||
"B_TERM_UTURN_INT_SW6A1",
|
||||
"B_TERM_UTURN_INT_SE6D2",
|
||||
"B_TERM_UTURN_INT_LV_L3",
|
||||
"B_TERM_UTURN_INT_SR1BEG3",
|
||||
"B_TERM_UTURN_INT_FAN_BOUNCE6",
|
||||
"B_TERM_UTURN_INT_SW6END_N0_3",
|
||||
"B_TERM_UTURN_INT_SE6B1",
|
||||
"B_TERM_UTURN_INT_LV5",
|
||||
"B_TERM_UTURN_INT_SR1BEG2",
|
||||
"B_TERM_UTURN_INT_FAN_BOUNCE2",
|
||||
"B_TERM_UTURN_INT_SW6A2",
|
||||
"B_TERM_UTURN_INT_SS2BEG2",
|
||||
"B_TERM_UTURN_INT_SS6D0",
|
||||
"B_TERM_UTURN_INT_SE6A1",
|
||||
"B_TERM_UTURN_INT_SS6A0",
|
||||
"B_TERM_UTURN_INT_SS2BEG1",
|
||||
"B_TERM_UTURN_INT_SE6C3",
|
||||
"B_TERM_UTURN_INT_SS6C2",
|
||||
"B_TERM_UTURN_INT_FAN_BOUNCE4",
|
||||
"B_TERM_UTURN_INT_SS6A3",
|
||||
"B_TERM_UTURN_INT_SW6D2",
|
||||
"B_TERM_UTURN_INT_SS6E3",
|
||||
"B_TERM_UTURN_INT_SW2BEG2",
|
||||
"B_TERM_UTURN_INT_LV_L8",
|
||||
"B_TERM_UTURN_INT_SW6B3",
|
||||
"B_TERM_UTURN_INT_SW6B1",
|
||||
"B_TERM_UTURN_INT_SW2BEG1",
|
||||
"B_TERM_UTURN_INT_LVB4",
|
||||
"B_TERM_UTURN_INT_SS2BEG0",
|
||||
"B_TERM_UTURN_INT_SR1BEG1",
|
||||
"B_TERM_UTURN_INT_SE6C2",
|
||||
"B_TERM_UTURN_INT_SW2BEG3",
|
||||
"B_TERM_UTURN_INT_WR1END0",
|
||||
"B_TERM_UTURN_INT_LV_L7",
|
||||
"B_TERM_UTURN_INT_SW6D1",
|
||||
"B_TERM_UTURN_INT_LVB_L5",
|
||||
"B_TERM_UTURN_INT_SE6C1",
|
||||
"B_TERM_UTURN_INT_LV18",
|
||||
"B_TERM_UTURN_INT_SW6D3",
|
||||
"B_TERM_UTURN_INT_SL1BEG3",
|
||||
"B_TERM_UTURN_INT_SS6E1",
|
||||
"B_TERM_UTURN_INT_SW6C3",
|
||||
"B_TERM_UTURN_INT_SS2A3",
|
||||
"B_TERM_UTURN_INT_SS6E0",
|
||||
"B_TERM_UTURN_INT_ER1BEG0",
|
||||
"B_TERM_UTURN_INT_ER1END_N3_3",
|
||||
"B_TERM_UTURN_INT_SE6B3",
|
||||
"B_TERM_UTURN_INT_SS6B2",
|
||||
"B_TERM_UTURN_INT_SW6B0",
|
||||
"B_TERM_UTURN_INT_SW6A0",
|
||||
"B_TERM_UTURN_INT_LV3",
|
||||
"B_TERM_UTURN_INT_SS6C3",
|
||||
"B_TERM_UTURN_INT_LV8",
|
||||
"B_TERM_UTURN_INT_SE6A3",
|
||||
"B_TERM_UTURN_INT_SS6C1",
|
||||
"B_TERM_UTURN_INT_SS6B0",
|
||||
"B_TERM_UTURN_INT_SS6C0",
|
||||
"B_TERM_UTURN_INT_SW6C1",
|
||||
"B_TERM_UTURN_INT_SS6D1",
|
||||
"B_TERM_UTURN_INT_LV_L4",
|
||||
"B_TERM_UTURN_INT_SS2A0",
|
||||
"B_TERM_UTURN_INT_SS6A1",
|
||||
"B_TERM_UTURN_INT_SS6BEG2",
|
||||
"B_TERM_UTURN_INT_SS6E2",
|
||||
"B_TERM_UTURN_INT_SW6D0",
|
||||
"B_TERM_UTURN_INT_SE6D0",
|
||||
"B_TERM_UTURN_INT_LV_L18",
|
||||
"B_TERM_UTURN_INT_FAN_BOUNCE0",
|
||||
"B_TERM_UTURN_INT_SE2BEG3"
|
||||
],
|
||||
"tile_type": "BRKH_B_TERM_INT",
|
||||
"sites": []
|
||||
}
|
||||
"wires": [
|
||||
"B_TERM_UTURN_INT_SS2A1",
|
||||
"B_TERM_UTURN_INT_SW6C0",
|
||||
"B_TERM_UTURN_INT_LV3",
|
||||
"B_TERM_UTURN_INT_LVB_L1",
|
||||
"B_TERM_UTURN_INT_SE6A1",
|
||||
"B_TERM_UTURN_INT_SS6D0",
|
||||
"B_TERM_UTURN_INT_SS6B3",
|
||||
"B_TERM_UTURN_INT_LVB3",
|
||||
"B_TERM_UTURN_INT_SS6BEG1",
|
||||
"B_TERM_UTURN_INT_SS6E2",
|
||||
"B_TERM_UTURN_INT_LV_L5",
|
||||
"B_TERM_UTURN_INT_SE6D3",
|
||||
"B_TERM_UTURN_INT_LV_L2",
|
||||
"B_TERM_UTURN_INT_SE6C0",
|
||||
"B_TERM_UTURN_INT_LV5",
|
||||
"B_TERM_UTURN_INT_LV9",
|
||||
"B_TERM_UTURN_INT_SE6B3",
|
||||
"B_TERM_UTURN_INT_LV2",
|
||||
"B_TERM_UTURN_INT_LVB1",
|
||||
"B_TERM_UTURN_INT_ER1BEG0",
|
||||
"B_TERM_UTURN_INT_SS2BEG1",
|
||||
"B_TERM_UTURN_INT_SW2BEG2",
|
||||
"B_TERM_UTURN_INT_SS6BEG2",
|
||||
"B_TERM_UTURN_INT_FAN_BOUNCE0",
|
||||
"B_TERM_UTURN_INT_SW6END_N0_3",
|
||||
"B_TERM_UTURN_INT_LV7",
|
||||
"B_TERM_UTURN_INT_SS6B2",
|
||||
"B_TERM_UTURN_INT_SS6E3",
|
||||
"B_TERM_UTURN_INT_SW6C1",
|
||||
"B_TERM_UTURN_INT_LVB4",
|
||||
"B_TERM_UTURN_INT_SE6C2",
|
||||
"B_TERM_UTURN_INT_SS2BEG3",
|
||||
"B_TERM_UTURN_INT_LVB_L2",
|
||||
"B_TERM_UTURN_INT_SS6A2",
|
||||
"B_TERM_UTURN_INT_SW6D2",
|
||||
"B_TERM_UTURN_INT_SL1BEG1",
|
||||
"B_TERM_UTURN_INT_LV_L3",
|
||||
"B_TERM_UTURN_INT_SS2BEG2",
|
||||
"B_TERM_UTURN_INT_LVB2",
|
||||
"B_TERM_UTURN_INT_SR1BEG1",
|
||||
"B_TERM_UTURN_INT_ER1END_N3_3",
|
||||
"B_TERM_UTURN_INT_SS6A3",
|
||||
"B_TERM_UTURN_INT_SW6A1",
|
||||
"B_TERM_UTURN_INT_SL1BEG0",
|
||||
"B_TERM_UTURN_INT_SS6B1",
|
||||
"B_TERM_UTURN_INT_SE2BEG2",
|
||||
"B_TERM_UTURN_INT_LV_L9",
|
||||
"B_TERM_UTURN_INT_SS6BEG3",
|
||||
"B_TERM_UTURN_INT_SL1BEG3",
|
||||
"B_TERM_UTURN_INT_LV_L6",
|
||||
"B_TERM_UTURN_INT_LVB5",
|
||||
"B_TERM_UTURN_INT_LVB_L4",
|
||||
"B_TERM_UTURN_INT_SR1BEG2",
|
||||
"B_TERM_UTURN_INT_SS2A3",
|
||||
"B_TERM_UTURN_INT_SS6D1",
|
||||
"B_TERM_UTURN_INT_LVB0",
|
||||
"B_TERM_UTURN_INT_LV_L4",
|
||||
"B_TERM_UTURN_INT_SS6C3",
|
||||
"B_TERM_UTURN_INT_FAN_BOUNCE4",
|
||||
"B_TERM_UTURN_INT_SW6C3",
|
||||
"B_TERM_UTURN_INT_LV6",
|
||||
"B_TERM_UTURN_INT_SS6BEG0",
|
||||
"B_TERM_UTURN_INT_LV_L7",
|
||||
"B_TERM_UTURN_INT_SW6B0",
|
||||
"B_TERM_UTURN_INT_SS6D3",
|
||||
"B_TERM_UTURN_INT_FAN_BOUNCE2",
|
||||
"B_TERM_UTURN_INT_SS6D2",
|
||||
"B_TERM_UTURN_INT_SW6D3",
|
||||
"B_TERM_UTURN_INT_SL1BEG2",
|
||||
"B_TERM_UTURN_INT_SW6D1",
|
||||
"B_TERM_UTURN_INT_SS6C1",
|
||||
"B_TERM_UTURN_INT_LVB_L5",
|
||||
"B_TERM_UTURN_INT_SS2A2",
|
||||
"B_TERM_UTURN_INT_SS6E0",
|
||||
"B_TERM_UTURN_INT_SW2BEG1",
|
||||
"B_TERM_UTURN_INT_SW6A0",
|
||||
"B_TERM_UTURN_INT_SE2BEG0",
|
||||
"B_TERM_UTURN_INT_LV4",
|
||||
"B_TERM_UTURN_INT_SS6A0",
|
||||
"B_TERM_UTURN_INT_SW6A2",
|
||||
"B_TERM_UTURN_INT_SE6D2",
|
||||
"B_TERM_UTURN_INT_SE6C3",
|
||||
"B_TERM_UTURN_INT_FAN_BOUNCE6",
|
||||
"B_TERM_UTURN_INT_LV_L18",
|
||||
"B_TERM_UTURN_INT_LVB_L3",
|
||||
"B_TERM_UTURN_INT_LV18",
|
||||
"B_TERM_UTURN_INT_SR1BEG3",
|
||||
"B_TERM_UTURN_INT_SS6C0",
|
||||
"B_TERM_UTURN_INT_SE6D1",
|
||||
"B_TERM_UTURN_INT_SE6B1",
|
||||
"B_TERM_UTURN_INT_SE6A2",
|
||||
"B_TERM_UTURN_INT_SS2BEG0",
|
||||
"B_TERM_UTURN_INT_SW6B1",
|
||||
"B_TERM_UTURN_INT_SE6B2",
|
||||
"B_TERM_UTURN_INT_SE2BEG3",
|
||||
"B_TERM_UTURN_INT_WR1END0",
|
||||
"B_TERM_UTURN_INT_SW6B2",
|
||||
"B_TERM_UTURN_INT_SE6B0",
|
||||
"B_TERM_UTURN_INT_SS6C2",
|
||||
"B_TERM_UTURN_INT_SW2BEG3",
|
||||
"B_TERM_UTURN_INT_SE2BEG1",
|
||||
"B_TERM_UTURN_INT_SE6A3",
|
||||
"B_TERM_UTURN_INT_SE6D0",
|
||||
"B_TERM_UTURN_INT_SS6A1",
|
||||
"B_TERM_UTURN_INT_LV8",
|
||||
"B_TERM_UTURN_INT_LVB_L0",
|
||||
"B_TERM_UTURN_INT_WR1BEG0",
|
||||
"B_TERM_UTURN_INT_SW2BEG0",
|
||||
"B_TERM_UTURN_INT_SW6A3",
|
||||
"B_TERM_UTURN_INT_SE6C1",
|
||||
"B_TERM_UTURN_INT_LV_L8",
|
||||
"B_TERM_UTURN_INT_SS6B0",
|
||||
"B_TERM_UTURN_INT_SW6B3",
|
||||
"B_TERM_UTURN_INT_SW6C2",
|
||||
"B_TERM_UTURN_INT_SW6D0",
|
||||
"B_TERM_UTURN_INT_SS2A0",
|
||||
"B_TERM_UTURN_INT_SS6E1",
|
||||
"B_TERM_UTURN_INT_SE6A0"
|
||||
],
|
||||
"pips": {},
|
||||
"tile_type": "BRKH_B_TERM_INT",
|
||||
"sites": []
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,11 +1,11 @@
|
|||
{
|
||||
"pips": {},
|
||||
"wires": [
|
||||
"BRKH_CLB_COUT0_L",
|
||||
"BRKH_CLB_COUT1_L",
|
||||
"BRKH_CLB_COUT1_R",
|
||||
"BRKH_CLB_COUT0_R"
|
||||
],
|
||||
"tile_type": "BRKH_CLB",
|
||||
"sites": []
|
||||
}
|
||||
"wires": [
|
||||
"BRKH_CLB_COUT0_R",
|
||||
"BRKH_CLB_COUT1_L",
|
||||
"BRKH_CLB_COUT0_L",
|
||||
"BRKH_CLB_COUT1_R"
|
||||
],
|
||||
"pips": {},
|
||||
"tile_type": "BRKH_CLB",
|
||||
"sites": []
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,135 +1,135 @@
|
|||
{
|
||||
"pips": {},
|
||||
"wires": [
|
||||
"BRKH_CLK_R_CK_BUFG_CASC28",
|
||||
"BRKH_CLK_CK_BUFG_CASC25",
|
||||
"BRKH_CLK_CK_BUFG_CASC22",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC11",
|
||||
"BRKH_CLK_R_CK_GCLK16",
|
||||
"BRKH_CLK_CK_BUFG_CASC2",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC30",
|
||||
"BRKH_CLK_CK_BUFG_CASC31",
|
||||
"BRKH_CLK_CK_BUFG_CASC5",
|
||||
"BRKH_CLK_CK_GCLK18",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC18",
|
||||
"BRKH_CLK_R_CK_GCLK22",
|
||||
"BRKH_CLK_CK_GCLK0",
|
||||
"BRKH_CLK_CK_BUFG_CASC7",
|
||||
"BRKH_CLK_CK_BUFG_CASC16",
|
||||
"BRKH_CLK_CK_GCLK1",
|
||||
"BRKH_CLK_CK_GCLK30",
|
||||
"BRKH_CLK_CK_BUFG_CASC18",
|
||||
"BRKH_CLK_CK_GCLK6",
|
||||
"BRKH_CLK_CK_GCLK10",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC21",
|
||||
"BRKH_CLK_R_CK_GCLK31",
|
||||
"BRKH_CLK_CK_BUFG_CASC14",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC4",
|
||||
"BRKH_CLK_CK_BUFG_CASC11",
|
||||
"BRKH_CLK_CK_GCLK8",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC10",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC0",
|
||||
"BRKH_CLK_R_CK_GCLK28",
|
||||
"BRKH_CLK_CK_GCLK14",
|
||||
"BRKH_CLK_CK_BUFG_CASC24",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC24",
|
||||
"BRKH_CLK_CK_BUFG_CASC0",
|
||||
"BRKH_CLK_CK_GCLK3",
|
||||
"BRKH_CLK_R_CK_GCLK8",
|
||||
"BRKH_CLK_R_CK_GCLK27",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC9",
|
||||
"BRKH_CLK_CK_BUFG_CASC9",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC6",
|
||||
"BRKH_CLK_R_CK_GCLK18",
|
||||
"BRKH_CLK_CK_GCLK19",
|
||||
"BRKH_CLK_CK_GCLK21",
|
||||
"BRKH_CLK_CK_BUFG_CASC27",
|
||||
"BRKH_CLK_CK_GCLK2",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC29",
|
||||
"BRKH_CLK_R_CK_GCLK3",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC17",
|
||||
"BRKH_CLK_R_CK_GCLK12",
|
||||
"BRKH_CLK_CK_BUFG_CASC28",
|
||||
"BRKH_CLK_R_CK_GCLK10",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC26",
|
||||
"BRKH_CLK_R_CK_GCLK19",
|
||||
"BRKH_CLK_CK_BUFG_CASC4",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC13",
|
||||
"BRKH_CLK_CK_BUFG_CASC17",
|
||||
"BRKH_CLK_CK_BUFG_CASC1",
|
||||
"BRKH_CLK_CK_GCLK24",
|
||||
"BRKH_CLK_CK_GCLK12",
|
||||
"BRKH_CLK_CK_GCLK9",
|
||||
"BRKH_CLK_R_CK_GCLK17",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC8",
|
||||
"BRKH_CLK_CK_GCLK11",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC31",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC27",
|
||||
"BRKH_CLK_CK_GCLK28",
|
||||
"BRKH_CLK_CK_BUFG_CASC13",
|
||||
"BRKH_CLK_CK_BUFG_CASC20",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC19",
|
||||
"BRKH_CLK_R_CK_GCLK29",
|
||||
"BRKH_CLK_CK_GCLK7",
|
||||
"BRKH_CLK_R_CK_GCLK23",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC20",
|
||||
"BRKH_CLK_CK_BUFG_CASC21",
|
||||
"BRKH_CLK_CK_BUFG_CASC30",
|
||||
"BRKH_CLK_CK_BUFG_CASC19",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC2",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC23",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC7",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC1",
|
||||
"BRKH_CLK_CK_BUFG_CASC3",
|
||||
"BRKH_CLK_CK_BUFG_CASC29",
|
||||
"BRKH_CLK_R_CK_GCLK21",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC25",
|
||||
"BRKH_CLK_R_CK_GCLK9",
|
||||
"BRKH_CLK_CK_GCLK16",
|
||||
"BRKH_CLK_R_CK_GCLK20",
|
||||
"BRKH_CLK_R_CK_GCLK14",
|
||||
"BRKH_CLK_R_CK_GCLK5",
|
||||
"BRKH_CLK_R_CK_GCLK25",
|
||||
"BRKH_CLK_CK_BUFG_CASC12",
|
||||
"BRKH_CLK_CK_GCLK22",
|
||||
"BRKH_CLK_CK_GCLK15",
|
||||
"BRKH_CLK_CK_GCLK5",
|
||||
"BRKH_CLK_R_CK_GCLK26",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC5",
|
||||
"BRKH_CLK_CK_GCLK13",
|
||||
"BRKH_CLK_R_CK_GCLK2",
|
||||
"BRKH_CLK_CK_GCLK20",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC12",
|
||||
"BRKH_CLK_CK_GCLK29",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC16",
|
||||
"BRKH_CLK_CK_GCLK31",
|
||||
"BRKH_CLK_R_CK_GCLK7",
|
||||
"BRKH_CLK_CK_GCLK27",
|
||||
"BRKH_CLK_R_CK_GCLK30",
|
||||
"BRKH_CLK_R_CK_GCLK24",
|
||||
"BRKH_CLK_R_CK_GCLK0",
|
||||
"BRKH_CLK_CK_GCLK17",
|
||||
"BRKH_CLK_CK_BUFG_CASC10",
|
||||
"BRKH_CLK_CK_BUFG_CASC8",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC15",
|
||||
"BRKH_CLK_CK_GCLK23",
|
||||
"BRKH_CLK_CK_GCLK25",
|
||||
"BRKH_CLK_CK_BUFG_CASC6",
|
||||
"BRKH_CLK_R_CK_GCLK11",
|
||||
"BRKH_CLK_R_CK_GCLK1",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC22",
|
||||
"BRKH_CLK_R_CK_GCLK6",
|
||||
"BRKH_CLK_R_CK_GCLK15",
|
||||
"BRKH_CLK_CK_GCLK26",
|
||||
"BRKH_CLK_R_CK_GCLK13",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC14",
|
||||
"BRKH_CLK_R_CK_GCLK4",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC3",
|
||||
"BRKH_CLK_CK_BUFG_CASC23",
|
||||
"BRKH_CLK_CK_BUFG_CASC15",
|
||||
"BRKH_CLK_CK_BUFG_CASC26",
|
||||
"BRKH_CLK_CK_GCLK4"
|
||||
],
|
||||
"tile_type": "BRKH_CLK",
|
||||
"sites": []
|
||||
}
|
||||
"wires": [
|
||||
"BRKH_CLK_CK_BUFG_CASC5",
|
||||
"BRKH_CLK_CK_GCLK7",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC10",
|
||||
"BRKH_CLK_CK_BUFG_CASC9",
|
||||
"BRKH_CLK_R_CK_GCLK5",
|
||||
"BRKH_CLK_CK_GCLK21",
|
||||
"BRKH_CLK_R_CK_GCLK2",
|
||||
"BRKH_CLK_CK_BUFG_CASC13",
|
||||
"BRKH_CLK_CK_GCLK15",
|
||||
"BRKH_CLK_CK_GCLK27",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC29",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC15",
|
||||
"BRKH_CLK_R_CK_GCLK14",
|
||||
"BRKH_CLK_R_CK_GCLK10",
|
||||
"BRKH_CLK_CK_BUFG_CASC14",
|
||||
"BRKH_CLK_CK_BUFG_CASC24",
|
||||
"BRKH_CLK_CK_GCLK12",
|
||||
"BRKH_CLK_CK_BUFG_CASC20",
|
||||
"BRKH_CLK_R_CK_GCLK26",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC26",
|
||||
"BRKH_CLK_R_CK_GCLK18",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC19",
|
||||
"BRKH_CLK_CK_GCLK11",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC6",
|
||||
"BRKH_CLK_CK_GCLK20",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC2",
|
||||
"BRKH_CLK_R_CK_GCLK22",
|
||||
"BRKH_CLK_CK_BUFG_CASC3",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC14",
|
||||
"BRKH_CLK_CK_BUFG_CASC15",
|
||||
"BRKH_CLK_CK_GCLK30",
|
||||
"BRKH_CLK_CK_BUFG_CASC31",
|
||||
"BRKH_CLK_CK_BUFG_CASC29",
|
||||
"BRKH_CLK_CK_BUFG_CASC23",
|
||||
"BRKH_CLK_CK_BUFG_CASC12",
|
||||
"BRKH_CLK_CK_GCLK18",
|
||||
"BRKH_CLK_R_CK_GCLK25",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC23",
|
||||
"BRKH_CLK_R_CK_GCLK3",
|
||||
"BRKH_CLK_CK_BUFG_CASC1",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC3",
|
||||
"BRKH_CLK_CK_GCLK23",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC1",
|
||||
"BRKH_CLK_CK_BUFG_CASC11",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC20",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC8",
|
||||
"BRKH_CLK_R_CK_GCLK20",
|
||||
"BRKH_CLK_CK_BUFG_CASC2",
|
||||
"BRKH_CLK_R_CK_GCLK15",
|
||||
"BRKH_CLK_R_CK_GCLK17",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC12",
|
||||
"BRKH_CLK_CK_GCLK25",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC11",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC21",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC30",
|
||||
"BRKH_CLK_R_CK_GCLK13",
|
||||
"BRKH_CLK_CK_GCLK13",
|
||||
"BRKH_CLK_CK_BUFG_CASC17",
|
||||
"BRKH_CLK_R_CK_GCLK8",
|
||||
"BRKH_CLK_CK_BUFG_CASC7",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC4",
|
||||
"BRKH_CLK_R_CK_GCLK27",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC25",
|
||||
"BRKH_CLK_R_CK_GCLK6",
|
||||
"BRKH_CLK_CK_BUFG_CASC8",
|
||||
"BRKH_CLK_CK_GCLK19",
|
||||
"BRKH_CLK_R_CK_GCLK7",
|
||||
"BRKH_CLK_R_CK_GCLK19",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC16",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC5",
|
||||
"BRKH_CLK_CK_BUFG_CASC19",
|
||||
"BRKH_CLK_CK_GCLK4",
|
||||
"BRKH_CLK_CK_GCLK26",
|
||||
"BRKH_CLK_CK_BUFG_CASC25",
|
||||
"BRKH_CLK_CK_BUFG_CASC22",
|
||||
"BRKH_CLK_R_CK_GCLK12",
|
||||
"BRKH_CLK_CK_GCLK29",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC27",
|
||||
"BRKH_CLK_CK_GCLK2",
|
||||
"BRKH_CLK_CK_BUFG_CASC21",
|
||||
"BRKH_CLK_R_CK_GCLK11",
|
||||
"BRKH_CLK_R_CK_GCLK21",
|
||||
"BRKH_CLK_R_CK_GCLK1",
|
||||
"BRKH_CLK_CK_GCLK1",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC18",
|
||||
"BRKH_CLK_CK_GCLK14",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC24",
|
||||
"BRKH_CLK_CK_BUFG_CASC16",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC28",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC7",
|
||||
"BRKH_CLK_R_CK_GCLK29",
|
||||
"BRKH_CLK_CK_BUFG_CASC30",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC22",
|
||||
"BRKH_CLK_CK_GCLK6",
|
||||
"BRKH_CLK_R_CK_GCLK23",
|
||||
"BRKH_CLK_CK_BUFG_CASC18",
|
||||
"BRKH_CLK_R_CK_GCLK0",
|
||||
"BRKH_CLK_CK_BUFG_CASC6",
|
||||
"BRKH_CLK_CK_GCLK28",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC31",
|
||||
"BRKH_CLK_CK_GCLK0",
|
||||
"BRKH_CLK_R_CK_GCLK16",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC17",
|
||||
"BRKH_CLK_R_CK_GCLK31",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC0",
|
||||
"BRKH_CLK_CK_BUFG_CASC26",
|
||||
"BRKH_CLK_R_CK_GCLK30",
|
||||
"BRKH_CLK_CK_GCLK17",
|
||||
"BRKH_CLK_CK_GCLK22",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC9",
|
||||
"BRKH_CLK_CK_BUFG_CASC10",
|
||||
"BRKH_CLK_CK_GCLK24",
|
||||
"BRKH_CLK_CK_GCLK8",
|
||||
"BRKH_CLK_R_CK_GCLK9",
|
||||
"BRKH_CLK_CK_GCLK5",
|
||||
"BRKH_CLK_CK_GCLK31",
|
||||
"BRKH_CLK_CK_GCLK10",
|
||||
"BRKH_CLK_CK_GCLK3",
|
||||
"BRKH_CLK_CK_BUFG_CASC0",
|
||||
"BRKH_CLK_R_CK_GCLK4",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC13",
|
||||
"BRKH_CLK_CK_BUFG_CASC4",
|
||||
"BRKH_CLK_R_CK_GCLK28",
|
||||
"BRKH_CLK_CK_BUFG_CASC27",
|
||||
"BRKH_CLK_R_CK_GCLK24",
|
||||
"BRKH_CLK_CK_GCLK16",
|
||||
"BRKH_CLK_CK_BUFG_CASC28",
|
||||
"BRKH_CLK_CK_GCLK9"
|
||||
],
|
||||
"pips": {},
|
||||
"tile_type": "BRKH_CLK",
|
||||
"sites": []
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,16 +1,16 @@
|
|||
{
|
||||
"pips": {},
|
||||
"wires": [
|
||||
"BRKH_CMT_FREQ_REF_NS1",
|
||||
"BRKH_CMT_PHYCTRL_SYNC_BB",
|
||||
"BRKH_CMT_PHASEREF1",
|
||||
"BRKH_CMT_FREQ_REF_NS3",
|
||||
"BRKH_CMT_PHASEREF0",
|
||||
"BRKH_CMT_FREQ_REF_NS2",
|
||||
"BRKH_CMT_PHASEREF_BELOW1",
|
||||
"BRKH_CMT_FREQ_REF_NS0",
|
||||
"BRKH_CMT_PHASEREF_BELOW0"
|
||||
],
|
||||
"tile_type": "BRKH_CMT",
|
||||
"sites": []
|
||||
}
|
||||
"wires": [
|
||||
"BRKH_CMT_PHASEREF1",
|
||||
"BRKH_CMT_FREQ_REF_NS2",
|
||||
"BRKH_CMT_PHASEREF0",
|
||||
"BRKH_CMT_FREQ_REF_NS1",
|
||||
"BRKH_CMT_PHASEREF_BELOW1",
|
||||
"BRKH_CMT_FREQ_REF_NS0",
|
||||
"BRKH_CMT_PHYCTRL_SYNC_BB",
|
||||
"BRKH_CMT_PHASEREF_BELOW0",
|
||||
"BRKH_CMT_FREQ_REF_NS3"
|
||||
],
|
||||
"pips": {},
|
||||
"tile_type": "BRKH_CMT",
|
||||
"sites": []
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,105 +1,105 @@
|
|||
{
|
||||
"pips": {},
|
||||
"wires": [
|
||||
"BRKH_DSP_PCIN15",
|
||||
"BRKH_DSP_BCIN12",
|
||||
"BRKH_DSP_PCIN6",
|
||||
"BRKH_DSP_PCIN31",
|
||||
"BRKH_DSP_PCIN37",
|
||||
"BRKH_DSP_PCIN29",
|
||||
"BRKH_DSP_ACIN15",
|
||||
"BRKH_DSP_ACIN8",
|
||||
"BRKH_DSP_ACIN2",
|
||||
"BRKH_DSP_PCIN36",
|
||||
"BRKH_DSP_PCIN46",
|
||||
"BRKH_DSP_PCIN43",
|
||||
"BRKH_DSP_BCIN8",
|
||||
"BRKH_DSP_BCIN7",
|
||||
"BRKH_DSP_BCIN11",
|
||||
"BRKH_DSP_BCIN13",
|
||||
"BRKH_DSP_ACIN13",
|
||||
"BRKH_DSP_ACIN9",
|
||||
"BRKH_DSP_PCIN19",
|
||||
"BRKH_DSP_BCIN17",
|
||||
"BRKH_DSP_PCIN44",
|
||||
"BRKH_DSP_PCIN8",
|
||||
"BRKH_DSP_PCIN24",
|
||||
"BRKH_DSP_PCIN13",
|
||||
"BRKH_DSP_PCIN18",
|
||||
"BRKH_DSP_ACIN27",
|
||||
"BRKH_DSP_PCIN17",
|
||||
"BRKH_DSP_BCIN0",
|
||||
"BRKH_DSP_ACIN1",
|
||||
"BRKH_DSP_PCIN35",
|
||||
"BRKH_DSP_BCIN15",
|
||||
"BRKH_DSP_ACIN28",
|
||||
"BRKH_DSP_PCIN21",
|
||||
"BRKH_DSP_PCIN42",
|
||||
"BRKH_DSP_BCIN5",
|
||||
"BRKH_DSP_BCIN10",
|
||||
"BRKH_DSP_ACIN29",
|
||||
"BRKH_DSP_ACIN26",
|
||||
"BRKH_DSP_PCIN16",
|
||||
"BRKH_DSP_ACIN6",
|
||||
"BRKH_DSP_BCIN2",
|
||||
"BRKH_DSP_ACIN11",
|
||||
"BRKH_DSP_MULTSIGNIN",
|
||||
"BRKH_DSP_PCIN2",
|
||||
"BRKH_DSP_PCIN12",
|
||||
"BRKH_DSP_PCIN10",
|
||||
"BRKH_DSP_CARRYCASCIN",
|
||||
"BRKH_DSP_PCIN26",
|
||||
"BRKH_DSP_PCIN4",
|
||||
"BRKH_DSP_PCIN20",
|
||||
"BRKH_DSP_ACIN0",
|
||||
"BRKH_DSP_ACIN5",
|
||||
"BRKH_DSP_PCIN5",
|
||||
"BRKH_DSP_PCIN3",
|
||||
"BRKH_DSP_PCIN39",
|
||||
"BRKH_DSP_PCIN30",
|
||||
"BRKH_DSP_ACIN25",
|
||||
"BRKH_DSP_PCIN40",
|
||||
"BRKH_DSP_PCIN22",
|
||||
"BRKH_DSP_PCIN1",
|
||||
"BRKH_DSP_ACIN7",
|
||||
"BRKH_DSP_BCIN3",
|
||||
"BRKH_DSP_PCIN34",
|
||||
"BRKH_DSP_BCIN9",
|
||||
"BRKH_DSP_ACIN10",
|
||||
"BRKH_DSP_ACIN17",
|
||||
"BRKH_DSP_ACIN14",
|
||||
"BRKH_DSP_ACIN3",
|
||||
"BRKH_DSP_ACIN20",
|
||||
"BRKH_DSP_BCIN1",
|
||||
"BRKH_DSP_PCIN11",
|
||||
"BRKH_DSP_ACIN12",
|
||||
"BRKH_DSP_PCIN28",
|
||||
"BRKH_DSP_PCIN47",
|
||||
"BRKH_DSP_PCIN7",
|
||||
"BRKH_DSP_PCIN41",
|
||||
"BRKH_DSP_BCIN16",
|
||||
"BRKH_DSP_ACIN24",
|
||||
"BRKH_DSP_ACIN19",
|
||||
"BRKH_DSP_ACIN22",
|
||||
"BRKH_DSP_BCIN4",
|
||||
"BRKH_DSP_PCIN33",
|
||||
"BRKH_DSP_PCIN9",
|
||||
"BRKH_DSP_PCIN14",
|
||||
"BRKH_DSP_PCIN38",
|
||||
"BRKH_DSP_ACIN16",
|
||||
"BRKH_DSP_ACIN23",
|
||||
"BRKH_DSP_BCIN14",
|
||||
"BRKH_DSP_PCIN25",
|
||||
"BRKH_DSP_ACIN4",
|
||||
"BRKH_DSP_ACIN21",
|
||||
"BRKH_DSP_PCIN23",
|
||||
"BRKH_DSP_PCIN0",
|
||||
"BRKH_DSP_PCIN27",
|
||||
"BRKH_DSP_PCIN45",
|
||||
"BRKH_DSP_ACIN18",
|
||||
"BRKH_DSP_BCIN6",
|
||||
"BRKH_DSP_PCIN32"
|
||||
],
|
||||
"tile_type": "BRKH_DSP_L",
|
||||
"sites": []
|
||||
}
|
||||
"wires": [
|
||||
"BRKH_DSP_PCIN36",
|
||||
"BRKH_DSP_BCIN10",
|
||||
"BRKH_DSP_PCIN1",
|
||||
"BRKH_DSP_ACIN2",
|
||||
"BRKH_DSP_BCIN1",
|
||||
"BRKH_DSP_ACIN6",
|
||||
"BRKH_DSP_MULTSIGNIN",
|
||||
"BRKH_DSP_ACIN8",
|
||||
"BRKH_DSP_PCIN13",
|
||||
"BRKH_DSP_BCIN6",
|
||||
"BRKH_DSP_ACIN28",
|
||||
"BRKH_DSP_PCIN4",
|
||||
"BRKH_DSP_PCIN43",
|
||||
"BRKH_DSP_ACIN9",
|
||||
"BRKH_DSP_BCIN15",
|
||||
"BRKH_DSP_ACIN5",
|
||||
"BRKH_DSP_BCIN2",
|
||||
"BRKH_DSP_PCIN16",
|
||||
"BRKH_DSP_PCIN44",
|
||||
"BRKH_DSP_PCIN25",
|
||||
"BRKH_DSP_ACIN12",
|
||||
"BRKH_DSP_BCIN14",
|
||||
"BRKH_DSP_ACIN4",
|
||||
"BRKH_DSP_PCIN2",
|
||||
"BRKH_DSP_PCIN28",
|
||||
"BRKH_DSP_PCIN14",
|
||||
"BRKH_DSP_PCIN8",
|
||||
"BRKH_DSP_ACIN21",
|
||||
"BRKH_DSP_PCIN6",
|
||||
"BRKH_DSP_ACIN18",
|
||||
"BRKH_DSP_BCIN13",
|
||||
"BRKH_DSP_ACIN0",
|
||||
"BRKH_DSP_PCIN15",
|
||||
"BRKH_DSP_PCIN3",
|
||||
"BRKH_DSP_PCIN18",
|
||||
"BRKH_DSP_PCIN32",
|
||||
"BRKH_DSP_CARRYCASCIN",
|
||||
"BRKH_DSP_ACIN7",
|
||||
"BRKH_DSP_PCIN9",
|
||||
"BRKH_DSP_PCIN27",
|
||||
"BRKH_DSP_PCIN17",
|
||||
"BRKH_DSP_PCIN45",
|
||||
"BRKH_DSP_PCIN26",
|
||||
"BRKH_DSP_BCIN8",
|
||||
"BRKH_DSP_PCIN46",
|
||||
"BRKH_DSP_PCIN34",
|
||||
"BRKH_DSP_ACIN17",
|
||||
"BRKH_DSP_PCIN40",
|
||||
"BRKH_DSP_PCIN20",
|
||||
"BRKH_DSP_PCIN12",
|
||||
"BRKH_DSP_PCIN7",
|
||||
"BRKH_DSP_ACIN24",
|
||||
"BRKH_DSP_PCIN21",
|
||||
"BRKH_DSP_BCIN5",
|
||||
"BRKH_DSP_PCIN31",
|
||||
"BRKH_DSP_BCIN4",
|
||||
"BRKH_DSP_ACIN20",
|
||||
"BRKH_DSP_ACIN27",
|
||||
"BRKH_DSP_PCIN41",
|
||||
"BRKH_DSP_PCIN11",
|
||||
"BRKH_DSP_PCIN39",
|
||||
"BRKH_DSP_ACIN11",
|
||||
"BRKH_DSP_PCIN33",
|
||||
"BRKH_DSP_PCIN30",
|
||||
"BRKH_DSP_PCIN37",
|
||||
"BRKH_DSP_ACIN15",
|
||||
"BRKH_DSP_ACIN16",
|
||||
"BRKH_DSP_ACIN10",
|
||||
"BRKH_DSP_PCIN38",
|
||||
"BRKH_DSP_ACIN26",
|
||||
"BRKH_DSP_BCIN9",
|
||||
"BRKH_DSP_ACIN14",
|
||||
"BRKH_DSP_ACIN3",
|
||||
"BRKH_DSP_PCIN29",
|
||||
"BRKH_DSP_PCIN10",
|
||||
"BRKH_DSP_BCIN12",
|
||||
"BRKH_DSP_PCIN24",
|
||||
"BRKH_DSP_BCIN7",
|
||||
"BRKH_DSP_PCIN22",
|
||||
"BRKH_DSP_PCIN19",
|
||||
"BRKH_DSP_PCIN47",
|
||||
"BRKH_DSP_ACIN22",
|
||||
"BRKH_DSP_ACIN25",
|
||||
"BRKH_DSP_ACIN23",
|
||||
"BRKH_DSP_BCIN0",
|
||||
"BRKH_DSP_ACIN13",
|
||||
"BRKH_DSP_PCIN0",
|
||||
"BRKH_DSP_ACIN29",
|
||||
"BRKH_DSP_ACIN19",
|
||||
"BRKH_DSP_ACIN1",
|
||||
"BRKH_DSP_PCIN5",
|
||||
"BRKH_DSP_PCIN35",
|
||||
"BRKH_DSP_BCIN11",
|
||||
"BRKH_DSP_PCIN42",
|
||||
"BRKH_DSP_BCIN3",
|
||||
"BRKH_DSP_BCIN17",
|
||||
"BRKH_DSP_BCIN16",
|
||||
"BRKH_DSP_PCIN23"
|
||||
],
|
||||
"pips": {},
|
||||
"tile_type": "BRKH_DSP_L",
|
||||
"sites": []
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,105 +1,105 @@
|
|||
{
|
||||
"pips": {},
|
||||
"wires": [
|
||||
"BRKH_DSP_PCIN15",
|
||||
"BRKH_DSP_BCIN12",
|
||||
"BRKH_DSP_PCIN6",
|
||||
"BRKH_DSP_PCIN31",
|
||||
"BRKH_DSP_PCIN37",
|
||||
"BRKH_DSP_PCIN29",
|
||||
"BRKH_DSP_ACIN15",
|
||||
"BRKH_DSP_ACIN8",
|
||||
"BRKH_DSP_ACIN2",
|
||||
"BRKH_DSP_PCIN36",
|
||||
"BRKH_DSP_PCIN46",
|
||||
"BRKH_DSP_PCIN43",
|
||||
"BRKH_DSP_BCIN8",
|
||||
"BRKH_DSP_BCIN7",
|
||||
"BRKH_DSP_BCIN11",
|
||||
"BRKH_DSP_BCIN13",
|
||||
"BRKH_DSP_ACIN13",
|
||||
"BRKH_DSP_ACIN9",
|
||||
"BRKH_DSP_PCIN19",
|
||||
"BRKH_DSP_BCIN17",
|
||||
"BRKH_DSP_PCIN44",
|
||||
"BRKH_DSP_PCIN8",
|
||||
"BRKH_DSP_PCIN24",
|
||||
"BRKH_DSP_PCIN13",
|
||||
"BRKH_DSP_PCIN18",
|
||||
"BRKH_DSP_ACIN27",
|
||||
"BRKH_DSP_PCIN17",
|
||||
"BRKH_DSP_BCIN0",
|
||||
"BRKH_DSP_ACIN1",
|
||||
"BRKH_DSP_PCIN35",
|
||||
"BRKH_DSP_BCIN15",
|
||||
"BRKH_DSP_ACIN28",
|
||||
"BRKH_DSP_PCIN21",
|
||||
"BRKH_DSP_PCIN42",
|
||||
"BRKH_DSP_BCIN5",
|
||||
"BRKH_DSP_BCIN10",
|
||||
"BRKH_DSP_ACIN29",
|
||||
"BRKH_DSP_ACIN26",
|
||||
"BRKH_DSP_PCIN16",
|
||||
"BRKH_DSP_ACIN6",
|
||||
"BRKH_DSP_BCIN2",
|
||||
"BRKH_DSP_ACIN11",
|
||||
"BRKH_DSP_MULTSIGNIN",
|
||||
"BRKH_DSP_PCIN2",
|
||||
"BRKH_DSP_PCIN12",
|
||||
"BRKH_DSP_PCIN10",
|
||||
"BRKH_DSP_CARRYCASCIN",
|
||||
"BRKH_DSP_PCIN26",
|
||||
"BRKH_DSP_PCIN4",
|
||||
"BRKH_DSP_PCIN20",
|
||||
"BRKH_DSP_ACIN0",
|
||||
"BRKH_DSP_ACIN5",
|
||||
"BRKH_DSP_PCIN5",
|
||||
"BRKH_DSP_PCIN3",
|
||||
"BRKH_DSP_PCIN39",
|
||||
"BRKH_DSP_PCIN30",
|
||||
"BRKH_DSP_ACIN25",
|
||||
"BRKH_DSP_PCIN40",
|
||||
"BRKH_DSP_PCIN22",
|
||||
"BRKH_DSP_PCIN1",
|
||||
"BRKH_DSP_ACIN7",
|
||||
"BRKH_DSP_BCIN3",
|
||||
"BRKH_DSP_PCIN34",
|
||||
"BRKH_DSP_BCIN9",
|
||||
"BRKH_DSP_ACIN10",
|
||||
"BRKH_DSP_ACIN17",
|
||||
"BRKH_DSP_ACIN14",
|
||||
"BRKH_DSP_ACIN3",
|
||||
"BRKH_DSP_ACIN20",
|
||||
"BRKH_DSP_BCIN1",
|
||||
"BRKH_DSP_PCIN11",
|
||||
"BRKH_DSP_ACIN12",
|
||||
"BRKH_DSP_PCIN28",
|
||||
"BRKH_DSP_PCIN47",
|
||||
"BRKH_DSP_PCIN7",
|
||||
"BRKH_DSP_PCIN41",
|
||||
"BRKH_DSP_BCIN16",
|
||||
"BRKH_DSP_ACIN24",
|
||||
"BRKH_DSP_ACIN19",
|
||||
"BRKH_DSP_ACIN22",
|
||||
"BRKH_DSP_BCIN4",
|
||||
"BRKH_DSP_PCIN33",
|
||||
"BRKH_DSP_PCIN9",
|
||||
"BRKH_DSP_PCIN14",
|
||||
"BRKH_DSP_PCIN38",
|
||||
"BRKH_DSP_ACIN16",
|
||||
"BRKH_DSP_ACIN23",
|
||||
"BRKH_DSP_BCIN14",
|
||||
"BRKH_DSP_PCIN25",
|
||||
"BRKH_DSP_ACIN4",
|
||||
"BRKH_DSP_ACIN21",
|
||||
"BRKH_DSP_PCIN23",
|
||||
"BRKH_DSP_PCIN0",
|
||||
"BRKH_DSP_PCIN27",
|
||||
"BRKH_DSP_PCIN45",
|
||||
"BRKH_DSP_ACIN18",
|
||||
"BRKH_DSP_BCIN6",
|
||||
"BRKH_DSP_PCIN32"
|
||||
],
|
||||
"tile_type": "BRKH_DSP_R",
|
||||
"sites": []
|
||||
}
|
||||
"wires": [
|
||||
"BRKH_DSP_PCIN36",
|
||||
"BRKH_DSP_BCIN10",
|
||||
"BRKH_DSP_PCIN1",
|
||||
"BRKH_DSP_ACIN2",
|
||||
"BRKH_DSP_BCIN1",
|
||||
"BRKH_DSP_ACIN6",
|
||||
"BRKH_DSP_MULTSIGNIN",
|
||||
"BRKH_DSP_ACIN8",
|
||||
"BRKH_DSP_PCIN13",
|
||||
"BRKH_DSP_BCIN6",
|
||||
"BRKH_DSP_ACIN28",
|
||||
"BRKH_DSP_PCIN4",
|
||||
"BRKH_DSP_PCIN43",
|
||||
"BRKH_DSP_ACIN9",
|
||||
"BRKH_DSP_BCIN15",
|
||||
"BRKH_DSP_ACIN5",
|
||||
"BRKH_DSP_BCIN2",
|
||||
"BRKH_DSP_PCIN16",
|
||||
"BRKH_DSP_PCIN44",
|
||||
"BRKH_DSP_PCIN25",
|
||||
"BRKH_DSP_ACIN12",
|
||||
"BRKH_DSP_BCIN14",
|
||||
"BRKH_DSP_ACIN4",
|
||||
"BRKH_DSP_PCIN2",
|
||||
"BRKH_DSP_PCIN28",
|
||||
"BRKH_DSP_PCIN14",
|
||||
"BRKH_DSP_PCIN8",
|
||||
"BRKH_DSP_ACIN21",
|
||||
"BRKH_DSP_PCIN6",
|
||||
"BRKH_DSP_ACIN18",
|
||||
"BRKH_DSP_BCIN13",
|
||||
"BRKH_DSP_ACIN0",
|
||||
"BRKH_DSP_PCIN15",
|
||||
"BRKH_DSP_PCIN3",
|
||||
"BRKH_DSP_PCIN18",
|
||||
"BRKH_DSP_PCIN32",
|
||||
"BRKH_DSP_CARRYCASCIN",
|
||||
"BRKH_DSP_ACIN7",
|
||||
"BRKH_DSP_PCIN9",
|
||||
"BRKH_DSP_PCIN27",
|
||||
"BRKH_DSP_PCIN17",
|
||||
"BRKH_DSP_PCIN45",
|
||||
"BRKH_DSP_PCIN26",
|
||||
"BRKH_DSP_BCIN8",
|
||||
"BRKH_DSP_PCIN46",
|
||||
"BRKH_DSP_PCIN34",
|
||||
"BRKH_DSP_ACIN17",
|
||||
"BRKH_DSP_PCIN40",
|
||||
"BRKH_DSP_PCIN20",
|
||||
"BRKH_DSP_PCIN12",
|
||||
"BRKH_DSP_PCIN7",
|
||||
"BRKH_DSP_ACIN24",
|
||||
"BRKH_DSP_PCIN21",
|
||||
"BRKH_DSP_BCIN5",
|
||||
"BRKH_DSP_PCIN31",
|
||||
"BRKH_DSP_BCIN4",
|
||||
"BRKH_DSP_ACIN20",
|
||||
"BRKH_DSP_ACIN27",
|
||||
"BRKH_DSP_PCIN41",
|
||||
"BRKH_DSP_PCIN11",
|
||||
"BRKH_DSP_PCIN39",
|
||||
"BRKH_DSP_ACIN11",
|
||||
"BRKH_DSP_PCIN33",
|
||||
"BRKH_DSP_PCIN30",
|
||||
"BRKH_DSP_PCIN37",
|
||||
"BRKH_DSP_ACIN15",
|
||||
"BRKH_DSP_ACIN16",
|
||||
"BRKH_DSP_ACIN10",
|
||||
"BRKH_DSP_PCIN38",
|
||||
"BRKH_DSP_ACIN26",
|
||||
"BRKH_DSP_BCIN9",
|
||||
"BRKH_DSP_ACIN14",
|
||||
"BRKH_DSP_ACIN3",
|
||||
"BRKH_DSP_PCIN29",
|
||||
"BRKH_DSP_PCIN10",
|
||||
"BRKH_DSP_BCIN12",
|
||||
"BRKH_DSP_PCIN24",
|
||||
"BRKH_DSP_BCIN7",
|
||||
"BRKH_DSP_PCIN22",
|
||||
"BRKH_DSP_PCIN19",
|
||||
"BRKH_DSP_PCIN47",
|
||||
"BRKH_DSP_ACIN22",
|
||||
"BRKH_DSP_ACIN25",
|
||||
"BRKH_DSP_ACIN23",
|
||||
"BRKH_DSP_BCIN0",
|
||||
"BRKH_DSP_ACIN13",
|
||||
"BRKH_DSP_PCIN0",
|
||||
"BRKH_DSP_ACIN29",
|
||||
"BRKH_DSP_ACIN19",
|
||||
"BRKH_DSP_ACIN1",
|
||||
"BRKH_DSP_PCIN5",
|
||||
"BRKH_DSP_PCIN35",
|
||||
"BRKH_DSP_BCIN11",
|
||||
"BRKH_DSP_PCIN42",
|
||||
"BRKH_DSP_BCIN3",
|
||||
"BRKH_DSP_BCIN17",
|
||||
"BRKH_DSP_BCIN16",
|
||||
"BRKH_DSP_PCIN23"
|
||||
],
|
||||
"pips": {},
|
||||
"tile_type": "BRKH_DSP_R",
|
||||
"sites": []
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,104 +1,104 @@
|
|||
{
|
||||
"pips": {
|
||||
"BRKH_GTX.BRKH_GTX_SOUTHREFCLK1_UPPER->BRKH_GTX_SOUTHREFCLK1_LOWER": {
|
||||
"can_invert": "0",
|
||||
"src_wire": "BRKH_GTX_SOUTHREFCLK1_UPPER",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "BRKH_GTX_SOUTHREFCLK1_LOWER"
|
||||
"wires": [
|
||||
"BRKH_GTX_NORTHREFCLK0_UPPER",
|
||||
"BRKH_GTX_REFCLK0_UPPER",
|
||||
"BRKH_GTX_SOUTHREFCLK0_UPPER",
|
||||
"BRKH_GTX_SOUTHREFCLK1_UPPER",
|
||||
"BRKH_GTX_SOUTHREFCLK0_LOWER",
|
||||
"BRKH_GTX_NORTHREFCLK1_UPPER",
|
||||
"BRKH_GTX_REFCLK1_LOWER",
|
||||
"BRKH_GTX_REFCLK1_UPPER",
|
||||
"BRKH_GTX_REFCLK0_LOWER",
|
||||
"BRKH_GTX_SOUTHREFCLK1_LOWER",
|
||||
"BRKH_GTX_NORTHREFCLK1_LOWER",
|
||||
"BRKH_GTX_NORTHREFCLK0_LOWER"
|
||||
],
|
||||
"pips": {
|
||||
"BRKH_GTX.BRKH_GTX_REFCLK0_LOWER->BRKH_GTX_NORTHREFCLK0_UPPER": {
|
||||
"src_wire": "BRKH_GTX_REFCLK0_LOWER",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"can_invert": "0",
|
||||
"dst_wire": "BRKH_GTX_NORTHREFCLK0_UPPER"
|
||||
},
|
||||
"BRKH_GTX.BRKH_GTX_SOUTHREFCLK1_UPPER->BRKH_GTX_SOUTHREFCLK1_LOWER": {
|
||||
"src_wire": "BRKH_GTX_SOUTHREFCLK1_UPPER",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"can_invert": "0",
|
||||
"dst_wire": "BRKH_GTX_SOUTHREFCLK1_LOWER"
|
||||
},
|
||||
"BRKH_GTX.BRKH_GTX_NORTHREFCLK1_LOWER->BRKH_GTX_NORTHREFCLK1_UPPER": {
|
||||
"src_wire": "BRKH_GTX_NORTHREFCLK1_LOWER",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"can_invert": "0",
|
||||
"dst_wire": "BRKH_GTX_NORTHREFCLK1_UPPER"
|
||||
},
|
||||
"BRKH_GTX.BRKH_GTX_REFCLK1_UPPER->BRKH_GTX_SOUTHREFCLK1_LOWER": {
|
||||
"src_wire": "BRKH_GTX_REFCLK1_UPPER",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"can_invert": "0",
|
||||
"dst_wire": "BRKH_GTX_SOUTHREFCLK1_LOWER"
|
||||
},
|
||||
"BRKH_GTX.BRKH_GTX_SOUTHREFCLK0_UPPER->BRKH_GTX_SOUTHREFCLK0_LOWER": {
|
||||
"src_wire": "BRKH_GTX_SOUTHREFCLK0_UPPER",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"can_invert": "0",
|
||||
"dst_wire": "BRKH_GTX_SOUTHREFCLK0_LOWER"
|
||||
},
|
||||
"BRKH_GTX.BRKH_GTX_REFCLK1_LOWER->BRKH_GTX_NORTHREFCLK0_UPPER": {
|
||||
"src_wire": "BRKH_GTX_REFCLK1_LOWER",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"can_invert": "0",
|
||||
"dst_wire": "BRKH_GTX_NORTHREFCLK0_UPPER"
|
||||
},
|
||||
"BRKH_GTX.BRKH_GTX_REFCLK1_LOWER->BRKH_GTX_NORTHREFCLK1_UPPER": {
|
||||
"src_wire": "BRKH_GTX_REFCLK1_LOWER",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"can_invert": "0",
|
||||
"dst_wire": "BRKH_GTX_NORTHREFCLK1_UPPER"
|
||||
},
|
||||
"BRKH_GTX.BRKH_GTX_REFCLK0_UPPER->BRKH_GTX_SOUTHREFCLK0_LOWER": {
|
||||
"src_wire": "BRKH_GTX_REFCLK0_UPPER",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"can_invert": "0",
|
||||
"dst_wire": "BRKH_GTX_SOUTHREFCLK0_LOWER"
|
||||
},
|
||||
"BRKH_GTX.BRKH_GTX_REFCLK1_UPPER->BRKH_GTX_SOUTHREFCLK0_LOWER": {
|
||||
"src_wire": "BRKH_GTX_REFCLK1_UPPER",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"can_invert": "0",
|
||||
"dst_wire": "BRKH_GTX_SOUTHREFCLK0_LOWER"
|
||||
},
|
||||
"BRKH_GTX.BRKH_GTX_NORTHREFCLK0_LOWER->BRKH_GTX_NORTHREFCLK0_UPPER": {
|
||||
"src_wire": "BRKH_GTX_NORTHREFCLK0_LOWER",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"can_invert": "0",
|
||||
"dst_wire": "BRKH_GTX_NORTHREFCLK0_UPPER"
|
||||
},
|
||||
"BRKH_GTX.BRKH_GTX_REFCLK0_UPPER->BRKH_GTX_SOUTHREFCLK1_LOWER": {
|
||||
"src_wire": "BRKH_GTX_REFCLK0_UPPER",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"can_invert": "0",
|
||||
"dst_wire": "BRKH_GTX_SOUTHREFCLK1_LOWER"
|
||||
},
|
||||
"BRKH_GTX.BRKH_GTX_REFCLK0_LOWER->BRKH_GTX_NORTHREFCLK1_UPPER": {
|
||||
"src_wire": "BRKH_GTX_REFCLK0_LOWER",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"can_invert": "0",
|
||||
"dst_wire": "BRKH_GTX_NORTHREFCLK1_UPPER"
|
||||
}
|
||||
},
|
||||
"BRKH_GTX.BRKH_GTX_REFCLK1_UPPER->BRKH_GTX_SOUTHREFCLK1_LOWER": {
|
||||
"can_invert": "0",
|
||||
"src_wire": "BRKH_GTX_REFCLK1_UPPER",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "BRKH_GTX_SOUTHREFCLK1_LOWER"
|
||||
},
|
||||
"BRKH_GTX.BRKH_GTX_REFCLK0_UPPER->BRKH_GTX_SOUTHREFCLK1_LOWER": {
|
||||
"can_invert": "0",
|
||||
"src_wire": "BRKH_GTX_REFCLK0_UPPER",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "BRKH_GTX_SOUTHREFCLK1_LOWER"
|
||||
},
|
||||
"BRKH_GTX.BRKH_GTX_SOUTHREFCLK0_UPPER->BRKH_GTX_SOUTHREFCLK0_LOWER": {
|
||||
"can_invert": "0",
|
||||
"src_wire": "BRKH_GTX_SOUTHREFCLK0_UPPER",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "BRKH_GTX_SOUTHREFCLK0_LOWER"
|
||||
},
|
||||
"BRKH_GTX.BRKH_GTX_REFCLK0_UPPER->BRKH_GTX_SOUTHREFCLK0_LOWER": {
|
||||
"can_invert": "0",
|
||||
"src_wire": "BRKH_GTX_REFCLK0_UPPER",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "BRKH_GTX_SOUTHREFCLK0_LOWER"
|
||||
},
|
||||
"BRKH_GTX.BRKH_GTX_REFCLK1_UPPER->BRKH_GTX_SOUTHREFCLK0_LOWER": {
|
||||
"can_invert": "0",
|
||||
"src_wire": "BRKH_GTX_REFCLK1_UPPER",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "BRKH_GTX_SOUTHREFCLK0_LOWER"
|
||||
},
|
||||
"BRKH_GTX.BRKH_GTX_NORTHREFCLK0_LOWER->BRKH_GTX_NORTHREFCLK0_UPPER": {
|
||||
"can_invert": "0",
|
||||
"src_wire": "BRKH_GTX_NORTHREFCLK0_LOWER",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "BRKH_GTX_NORTHREFCLK0_UPPER"
|
||||
},
|
||||
"BRKH_GTX.BRKH_GTX_NORTHREFCLK1_LOWER->BRKH_GTX_NORTHREFCLK1_UPPER": {
|
||||
"can_invert": "0",
|
||||
"src_wire": "BRKH_GTX_NORTHREFCLK1_LOWER",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "BRKH_GTX_NORTHREFCLK1_UPPER"
|
||||
},
|
||||
"BRKH_GTX.BRKH_GTX_REFCLK0_LOWER->BRKH_GTX_NORTHREFCLK0_UPPER": {
|
||||
"can_invert": "0",
|
||||
"src_wire": "BRKH_GTX_REFCLK0_LOWER",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "BRKH_GTX_NORTHREFCLK0_UPPER"
|
||||
},
|
||||
"BRKH_GTX.BRKH_GTX_REFCLK0_LOWER->BRKH_GTX_NORTHREFCLK1_UPPER": {
|
||||
"can_invert": "0",
|
||||
"src_wire": "BRKH_GTX_REFCLK0_LOWER",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "BRKH_GTX_NORTHREFCLK1_UPPER"
|
||||
},
|
||||
"BRKH_GTX.BRKH_GTX_REFCLK1_LOWER->BRKH_GTX_NORTHREFCLK0_UPPER": {
|
||||
"can_invert": "0",
|
||||
"src_wire": "BRKH_GTX_REFCLK1_LOWER",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "BRKH_GTX_NORTHREFCLK0_UPPER"
|
||||
},
|
||||
"BRKH_GTX.BRKH_GTX_REFCLK1_LOWER->BRKH_GTX_NORTHREFCLK1_UPPER": {
|
||||
"can_invert": "0",
|
||||
"src_wire": "BRKH_GTX_REFCLK1_LOWER",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "BRKH_GTX_NORTHREFCLK1_UPPER"
|
||||
}
|
||||
},
|
||||
"wires": [
|
||||
"BRKH_GTX_SOUTHREFCLK0_UPPER",
|
||||
"BRKH_GTX_REFCLK0_UPPER",
|
||||
"BRKH_GTX_NORTHREFCLK0_LOWER",
|
||||
"BRKH_GTX_REFCLK1_LOWER",
|
||||
"BRKH_GTX_NORTHREFCLK1_LOWER",
|
||||
"BRKH_GTX_SOUTHREFCLK1_LOWER",
|
||||
"BRKH_GTX_NORTHREFCLK0_UPPER",
|
||||
"BRKH_GTX_NORTHREFCLK1_UPPER",
|
||||
"BRKH_GTX_REFCLK0_LOWER",
|
||||
"BRKH_GTX_REFCLK1_UPPER",
|
||||
"BRKH_GTX_SOUTHREFCLK1_UPPER",
|
||||
"BRKH_GTX_SOUTHREFCLK0_LOWER"
|
||||
],
|
||||
"tile_type": "BRKH_GTX",
|
||||
"sites": []
|
||||
}
|
||||
"tile_type": "BRKH_GTX",
|
||||
"sites": []
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,367 +1,367 @@
|
|||
{
|
||||
"pips": {
|
||||
"BRKH_INT.BRKH_INT_NL1BEG0->>BRKH_INT_NL1BEG0_SLOW": {
|
||||
"src_wire": "BRKH_INT_NL1BEG0",
|
||||
"can_invert": "0",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "BRKH_INT_NL1BEG0_SLOW"
|
||||
"wires": [
|
||||
"BRKH_INT_SS6B3",
|
||||
"BRKH_INT_NE6A3",
|
||||
"BRKH_INT_SS6C0",
|
||||
"BRKH_INT_NN6C1",
|
||||
"BRKH_INT_NE2BEG1",
|
||||
"BRKH_INT_LV6",
|
||||
"BRKH_INT_SS2A1",
|
||||
"BRKH_INT_SS6END2",
|
||||
"BRKH_INT_SS6END_N0_3",
|
||||
"BRKH_INT_NN2BEG3",
|
||||
"BRKH_INT_NE6A2",
|
||||
"BRKH_INT_SS6A2",
|
||||
"BRKH_INT_NW6A3",
|
||||
"BRKH_INT_FAN_BOUNCE_S3_0",
|
||||
"BRKH_INT_SW6D3",
|
||||
"BRKH_INT_SW2A0",
|
||||
"BRKH_INT_BYP_BOUNCE2",
|
||||
"BRKH_INT_NN6D0",
|
||||
"BRKH_INT_SR1END2",
|
||||
"BRKH_INT_NN6D2",
|
||||
"BRKH_INT_L_LV11",
|
||||
"BRKH_INT_LVB_L12",
|
||||
"BRKH_INT_SS6B2",
|
||||
"BRKH_INT_SS6D1",
|
||||
"BRKH_INT_NE2END_S3_0",
|
||||
"BRKH_INT_BYP_BOUNCE7",
|
||||
"BRKH_INT_NN2BEG2",
|
||||
"BRKH_INT_NE6A0",
|
||||
"BRKH_INT_NW6D0",
|
||||
"BRKH_INT_LVB_L10",
|
||||
"BRKH_INT_SW6E1",
|
||||
"BRKH_INT_FAN_BOUNCE_S3_6",
|
||||
"BRKH_INT_NE6C3",
|
||||
"BRKH_INT_NN2A3",
|
||||
"BRKH_INT_LV4",
|
||||
"BRKH_INT_SW6D1",
|
||||
"BRKH_INT_NW6A1",
|
||||
"BRKH_INT_SS6D2",
|
||||
"BRKH_INT_NW2BEG2",
|
||||
"BRKH_INT_LV10",
|
||||
"BRKH_INT_NL1BEG2_SLOW",
|
||||
"BRKH_INT_SL1END2_SLOW",
|
||||
"BRKH_INT_WR1END_S1_0",
|
||||
"BRKH_INT_SW6B1",
|
||||
"BRKH_INT_SR1END3",
|
||||
"BRKH_INT_L_LV5",
|
||||
"BRKH_INT_LV8",
|
||||
"BRKH_INT_NW6C2",
|
||||
"BRKH_INT_SS2END3",
|
||||
"BRKH_INT_L_LV3",
|
||||
"BRKH_INT_SS6A0",
|
||||
"BRKH_INT_L_LV13",
|
||||
"BRKH_INT_LVB11",
|
||||
"BRKH_INT_NW6B0",
|
||||
"BRKH_INT_SW6B0",
|
||||
"BRKH_INT_LVB9",
|
||||
"BRKH_INT_NE6B3",
|
||||
"BRKH_INT_SW6E3",
|
||||
"BRKH_INT_LV9",
|
||||
"BRKH_INT_SW6B3",
|
||||
"BRKH_INT_NN6B2",
|
||||
"BRKH_INT_L_LV7",
|
||||
"BRKH_INT_NR1BEG1_SLOW",
|
||||
"BRKH_INT_SE6D1",
|
||||
"BRKH_INT_SE6E1",
|
||||
"BRKH_INT_SS6C2",
|
||||
"BRKH_INT_SS6B0",
|
||||
"BRKH_INT_NW6D1",
|
||||
"BRKH_INT_LVB_L7",
|
||||
"BRKH_INT_SE6E0",
|
||||
"BRKH_INT_SE6C3",
|
||||
"BRKH_INT_NN2A1",
|
||||
"BRKH_INT_LV15",
|
||||
"BRKH_INT_NN2END_S2_0",
|
||||
"BRKH_INT_NN6B0",
|
||||
"BRKH_INT_SS6C3",
|
||||
"BRKH_INT_SR1END3_SLOW",
|
||||
"BRKH_INT_FAN_BOUNCE_S3_4",
|
||||
"BRKH_INT_NN6E0",
|
||||
"BRKH_INT_SE6E2",
|
||||
"BRKH_INT_SS2A3",
|
||||
"BRKH_INT_SE6B0",
|
||||
"BRKH_INT_LV7",
|
||||
"BRKH_INT_NN6E2",
|
||||
"BRKH_INT_LVB_L6",
|
||||
"BRKH_INT_SS2A2",
|
||||
"BRKH_INT_LVB_L2",
|
||||
"BRKH_INT_WL1BEG3",
|
||||
"BRKH_INT_SE6C2",
|
||||
"BRKH_INT_NL1BEG0",
|
||||
"BRKH_INT_NN2A2",
|
||||
"BRKH_INT_SS6E1",
|
||||
"BRKH_INT_SE2A3",
|
||||
"BRKH_INT_LVB_L9",
|
||||
"BRKH_INT_NE6D1",
|
||||
"BRKH_INT_SS6E3",
|
||||
"BRKH_INT_SW2A1",
|
||||
"BRKH_INT_NR1BEG3_SLOW",
|
||||
"BRKH_INT_NN6A2",
|
||||
"BRKH_INT_NE2BEG3",
|
||||
"BRKH_INT_LVB10",
|
||||
"BRKH_INT_BYP_BOUNCE6",
|
||||
"BRKH_INT_L_LV12",
|
||||
"BRKH_INT_EL1BEG3",
|
||||
"BRKH_INT_SW6C1",
|
||||
"BRKH_INT_NW6B2",
|
||||
"BRKH_INT_L_LV0",
|
||||
"BRKH_INT_SL1END3",
|
||||
"BRKH_INT_NR1BEG1",
|
||||
"BRKH_INT_NN6A3",
|
||||
"BRKH_INT_SL1END3_SLOW",
|
||||
"BRKH_INT_SW2A3",
|
||||
"BRKH_INT_BYP_BOUNCE3",
|
||||
"BRKH_INT_SS6D3",
|
||||
"BRKH_INT_NW6B1",
|
||||
"BRKH_INT_LVB8",
|
||||
"BRKH_INT_SS6D0",
|
||||
"BRKH_INT_NN6A0",
|
||||
"BRKH_INT_SE6C0",
|
||||
"BRKH_INT_SE2A0",
|
||||
"BRKH_INT_SS2END0",
|
||||
"BRKH_INT_NN6D1",
|
||||
"BRKH_INT_L_LV15",
|
||||
"BRKH_INT_NL1BEG1",
|
||||
"BRKH_INT_L_LV10",
|
||||
"BRKH_INT_SE6C1",
|
||||
"BRKH_INT_SW2A2",
|
||||
"BRKH_INT_LVB3",
|
||||
"BRKH_INT_NW6C0",
|
||||
"BRKH_INT_NN6C0",
|
||||
"BRKH_INT_SS2END1",
|
||||
"BRKH_INT_SS6END1",
|
||||
"BRKH_INT_NE6B1",
|
||||
"BRKH_INT_SR1END1",
|
||||
"BRKH_INT_NN6A1",
|
||||
"BRKH_INT_NN2BEG1",
|
||||
"BRKH_INT_L_LV8",
|
||||
"BRKH_INT_NE6D0",
|
||||
"BRKH_INT_WW2END3",
|
||||
"BRKH_INT_LV2",
|
||||
"BRKH_INT_SW6E2",
|
||||
"BRKH_INT_NE6D2",
|
||||
"BRKH_INT_L_LV17",
|
||||
"BRKH_INT_LV14",
|
||||
"BRKH_INT_NN6C2",
|
||||
"BRKH_INT_LV5",
|
||||
"BRKH_INT_LVB2",
|
||||
"BRKH_INT_NN6D3",
|
||||
"BRKH_INT_NN6BEG0",
|
||||
"BRKH_INT_SW6D0",
|
||||
"BRKH_INT_NW6D3",
|
||||
"BRKH_INT_NR1BEG3",
|
||||
"BRKH_INT_SE2A2",
|
||||
"BRKH_INT_EL1END_S3_0",
|
||||
"BRKH_INT_SE6D2",
|
||||
"BRKH_INT_NN6C3",
|
||||
"BRKH_INT_NE6D3",
|
||||
"BRKH_INT_SE6D3",
|
||||
"BRKH_INT_SW6D2",
|
||||
"BRKH_INT_NL1BEG2",
|
||||
"BRKH_INT_NE6C1",
|
||||
"BRKH_INT_NW2BEG1",
|
||||
"BRKH_INT_SS6E2",
|
||||
"BRKH_INT_NW6C1",
|
||||
"BRKH_INT_SS6C1",
|
||||
"BRKH_INT_LV3",
|
||||
"BRKH_INT_NE2BEG2",
|
||||
"BRKH_INT_SS2END_N0_3",
|
||||
"BRKH_INT_SS6B1",
|
||||
"BRKH_INT_SE6B3",
|
||||
"BRKH_INT_FAN_BOUNCE_S3_2",
|
||||
"BRKH_INT_L_LV4",
|
||||
"BRKH_INT_NL1END_S3_0",
|
||||
"BRKH_INT_SW6C0",
|
||||
"BRKH_INT_SS2END2",
|
||||
"BRKH_INT_ER1END3",
|
||||
"BRKH_INT_SL1END0",
|
||||
"BRKH_INT_LVB1",
|
||||
"BRKH_INT_LVB_L3",
|
||||
"BRKH_INT_NN6B3",
|
||||
"BRKH_INT_LVB_L4",
|
||||
"BRKH_INT_SE6B1",
|
||||
"BRKH_INT_NW6B3",
|
||||
"BRKH_INT_NN2BEG0",
|
||||
"BRKH_INT_SR1END1_SLOW",
|
||||
"BRKH_INT_L_LV9",
|
||||
"BRKH_INT_LV11",
|
||||
"BRKH_INT_SW6C2",
|
||||
"BRKH_INT_WL1END3",
|
||||
"BRKH_INT_LVB_L1",
|
||||
"BRKH_INT_SS6A1",
|
||||
"BRKH_INT_L_LV14",
|
||||
"BRKH_INT_LVB_L11",
|
||||
"BRKH_INT_NN6BEG2",
|
||||
"BRKH_INT_SW6B2",
|
||||
"BRKH_INT_L_LV16",
|
||||
"BRKH_INT_LV12",
|
||||
"BRKH_INT_LV16",
|
||||
"BRKH_INT_ER1BEG_S0",
|
||||
"BRKH_INT_NN6E3",
|
||||
"BRKH_INT_SS6END3",
|
||||
"BRKH_INT_NR1BEG0",
|
||||
"BRKH_INT_L_LV6",
|
||||
"BRKH_INT_NW6D2",
|
||||
"BRKH_INT_NW6A0",
|
||||
"BRKH_INT_LVB_L5",
|
||||
"BRKH_INT_SW2END3",
|
||||
"BRKH_INT_NN6E1",
|
||||
"BRKH_INT_NE2BEG0",
|
||||
"BRKH_INT_SL1END2",
|
||||
"BRKH_INT_NL1BEG0_SLOW",
|
||||
"BRKH_INT_SL1END1_SLOW",
|
||||
"BRKH_INT_NR1BEG2_SLOW",
|
||||
"BRKH_INT_NR1BEG2",
|
||||
"BRKH_INT_SW6END3",
|
||||
"BRKH_INT_NE6C2",
|
||||
"BRKH_INT_SS6A3",
|
||||
"BRKH_INT_NW6END_S0_0",
|
||||
"BRKH_INT_NW2END_S0_0",
|
||||
"BRKH_INT_SE6E3",
|
||||
"BRKH_INT_NR1BEG0_SLOW",
|
||||
"BRKH_INT_NE6B0",
|
||||
"BRKH_INT_NE6A1",
|
||||
"BRKH_INT_NL1BEG1_SLOW",
|
||||
"BRKH_INT_NN6END_S1_0",
|
||||
"BRKH_INT_SR1END_N3_3",
|
||||
"BRKH_INT_SE6B2",
|
||||
"BRKH_INT_SE2A1",
|
||||
"BRKH_INT_L_LV2",
|
||||
"BRKH_INT_SL1END0_SLOW",
|
||||
"BRKH_INT_NN6B1",
|
||||
"BRKH_INT_WR1BEG_S0",
|
||||
"BRKH_INT_SS6E0",
|
||||
"BRKH_INT_SR1END2_SLOW",
|
||||
"BRKH_INT_LVB_L8",
|
||||
"BRKH_INT_LV17",
|
||||
"BRKH_INT_NW2BEG0",
|
||||
"BRKH_INT_NW6C3",
|
||||
"BRKH_INT_SE6D0",
|
||||
"BRKH_INT_SS2A0",
|
||||
"BRKH_INT_LV0",
|
||||
"BRKH_INT_LVB4",
|
||||
"BRKH_INT_NE6B2",
|
||||
"BRKH_INT_SW6E0",
|
||||
"BRKH_INT_SW6C3",
|
||||
"BRKH_INT_LV13",
|
||||
"BRKH_INT_SL1END1",
|
||||
"BRKH_INT_NW2BEG3",
|
||||
"BRKH_INT_NW6A2",
|
||||
"BRKH_INT_NN6BEG1",
|
||||
"BRKH_INT_NN6BEG3",
|
||||
"BRKH_INT_WW4END_S0_0",
|
||||
"BRKH_INT_LVB6",
|
||||
"BRKH_INT_L_LV1",
|
||||
"BRKH_INT_SS6END0",
|
||||
"BRKH_INT_NE6C0",
|
||||
"BRKH_INT_NN2A0",
|
||||
"BRKH_INT_LVB12",
|
||||
"BRKH_INT_LVB5",
|
||||
"BRKH_INT_LV1",
|
||||
"BRKH_INT_LVB7"
|
||||
],
|
||||
"pips": {
|
||||
"BRKH_INT.BRKH_INT_NL1BEG2->>BRKH_INT_NL1BEG2_SLOW": {
|
||||
"src_wire": "BRKH_INT_NL1BEG2",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "BRKH_INT_NL1BEG2_SLOW",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRKH_INT.BRKH_INT_NR1BEG0->>BRKH_INT_NR1BEG0_SLOW": {
|
||||
"src_wire": "BRKH_INT_NR1BEG0",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "BRKH_INT_NR1BEG0_SLOW",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRKH_INT.BRKH_INT_SL1END0_SLOW->>BRKH_INT_SL1END0": {
|
||||
"src_wire": "BRKH_INT_SL1END0_SLOW",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "BRKH_INT_SL1END0",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRKH_INT.BRKH_INT_NR1BEG1->>BRKH_INT_NR1BEG1_SLOW": {
|
||||
"src_wire": "BRKH_INT_NR1BEG1",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "BRKH_INT_NR1BEG1_SLOW",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRKH_INT.BRKH_INT_NR1BEG2->>BRKH_INT_NR1BEG2_SLOW": {
|
||||
"src_wire": "BRKH_INT_NR1BEG2",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "BRKH_INT_NR1BEG2_SLOW",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRKH_INT.BRKH_INT_SR1END3_SLOW->>BRKH_INT_SR1END3": {
|
||||
"src_wire": "BRKH_INT_SR1END3_SLOW",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "BRKH_INT_SR1END3",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRKH_INT.BRKH_INT_NL1BEG1->>BRKH_INT_NL1BEG1_SLOW": {
|
||||
"src_wire": "BRKH_INT_NL1BEG1",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "BRKH_INT_NL1BEG1_SLOW",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRKH_INT.BRKH_INT_SL1END2_SLOW->>BRKH_INT_SL1END2": {
|
||||
"src_wire": "BRKH_INT_SL1END2_SLOW",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "BRKH_INT_SL1END2",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRKH_INT.BRKH_INT_NL1BEG0->>BRKH_INT_NL1BEG0_SLOW": {
|
||||
"src_wire": "BRKH_INT_NL1BEG0",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "BRKH_INT_NL1BEG0_SLOW",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRKH_INT.BRKH_INT_SR1END2_SLOW->>BRKH_INT_SR1END2": {
|
||||
"src_wire": "BRKH_INT_SR1END2_SLOW",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "BRKH_INT_SR1END2",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRKH_INT.BRKH_INT_NR1BEG3->>BRKH_INT_NR1BEG3_SLOW": {
|
||||
"src_wire": "BRKH_INT_NR1BEG3",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "BRKH_INT_NR1BEG3_SLOW",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRKH_INT.BRKH_INT_SL1END3_SLOW->>BRKH_INT_SL1END3": {
|
||||
"src_wire": "BRKH_INT_SL1END3_SLOW",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "BRKH_INT_SL1END3",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRKH_INT.BRKH_INT_SR1END1_SLOW->>BRKH_INT_SR1END1": {
|
||||
"src_wire": "BRKH_INT_SR1END1_SLOW",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "BRKH_INT_SR1END1",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRKH_INT.BRKH_INT_SL1END1_SLOW->>BRKH_INT_SL1END1": {
|
||||
"src_wire": "BRKH_INT_SL1END1_SLOW",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "BRKH_INT_SL1END1",
|
||||
"can_invert": "0"
|
||||
}
|
||||
},
|
||||
"BRKH_INT.BRKH_INT_SL1END3_SLOW->>BRKH_INT_SL1END3": {
|
||||
"src_wire": "BRKH_INT_SL1END3_SLOW",
|
||||
"can_invert": "0",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "BRKH_INT_SL1END3"
|
||||
},
|
||||
"BRKH_INT.BRKH_INT_SL1END2_SLOW->>BRKH_INT_SL1END2": {
|
||||
"src_wire": "BRKH_INT_SL1END2_SLOW",
|
||||
"can_invert": "0",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "BRKH_INT_SL1END2"
|
||||
},
|
||||
"BRKH_INT.BRKH_INT_NR1BEG3->>BRKH_INT_NR1BEG3_SLOW": {
|
||||
"src_wire": "BRKH_INT_NR1BEG3",
|
||||
"can_invert": "0",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "BRKH_INT_NR1BEG3_SLOW"
|
||||
},
|
||||
"BRKH_INT.BRKH_INT_NR1BEG1->>BRKH_INT_NR1BEG1_SLOW": {
|
||||
"src_wire": "BRKH_INT_NR1BEG1",
|
||||
"can_invert": "0",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "BRKH_INT_NR1BEG1_SLOW"
|
||||
},
|
||||
"BRKH_INT.BRKH_INT_SL1END1_SLOW->>BRKH_INT_SL1END1": {
|
||||
"src_wire": "BRKH_INT_SL1END1_SLOW",
|
||||
"can_invert": "0",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "BRKH_INT_SL1END1"
|
||||
},
|
||||
"BRKH_INT.BRKH_INT_NL1BEG1->>BRKH_INT_NL1BEG1_SLOW": {
|
||||
"src_wire": "BRKH_INT_NL1BEG1",
|
||||
"can_invert": "0",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "BRKH_INT_NL1BEG1_SLOW"
|
||||
},
|
||||
"BRKH_INT.BRKH_INT_SR1END1_SLOW->>BRKH_INT_SR1END1": {
|
||||
"src_wire": "BRKH_INT_SR1END1_SLOW",
|
||||
"can_invert": "0",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "BRKH_INT_SR1END1"
|
||||
},
|
||||
"BRKH_INT.BRKH_INT_NL1BEG2->>BRKH_INT_NL1BEG2_SLOW": {
|
||||
"src_wire": "BRKH_INT_NL1BEG2",
|
||||
"can_invert": "0",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "BRKH_INT_NL1BEG2_SLOW"
|
||||
},
|
||||
"BRKH_INT.BRKH_INT_NR1BEG2->>BRKH_INT_NR1BEG2_SLOW": {
|
||||
"src_wire": "BRKH_INT_NR1BEG2",
|
||||
"can_invert": "0",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "BRKH_INT_NR1BEG2_SLOW"
|
||||
},
|
||||
"BRKH_INT.BRKH_INT_SR1END3_SLOW->>BRKH_INT_SR1END3": {
|
||||
"src_wire": "BRKH_INT_SR1END3_SLOW",
|
||||
"can_invert": "0",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "BRKH_INT_SR1END3"
|
||||
},
|
||||
"BRKH_INT.BRKH_INT_SR1END2_SLOW->>BRKH_INT_SR1END2": {
|
||||
"src_wire": "BRKH_INT_SR1END2_SLOW",
|
||||
"can_invert": "0",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "BRKH_INT_SR1END2"
|
||||
},
|
||||
"BRKH_INT.BRKH_INT_NR1BEG0->>BRKH_INT_NR1BEG0_SLOW": {
|
||||
"src_wire": "BRKH_INT_NR1BEG0",
|
||||
"can_invert": "0",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "BRKH_INT_NR1BEG0_SLOW"
|
||||
},
|
||||
"BRKH_INT.BRKH_INT_SL1END0_SLOW->>BRKH_INT_SL1END0": {
|
||||
"src_wire": "BRKH_INT_SL1END0_SLOW",
|
||||
"can_invert": "0",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "BRKH_INT_SL1END0"
|
||||
}
|
||||
},
|
||||
"wires": [
|
||||
"BRKH_INT_SS6C0",
|
||||
"BRKH_INT_SS6B2",
|
||||
"BRKH_INT_SE6E1",
|
||||
"BRKH_INT_NW2BEG1",
|
||||
"BRKH_INT_NL1END_S3_0",
|
||||
"BRKH_INT_NR1BEG0",
|
||||
"BRKH_INT_NR1BEG3",
|
||||
"BRKH_INT_LVB8",
|
||||
"BRKH_INT_BYP_BOUNCE7",
|
||||
"BRKH_INT_EL1END_S3_0",
|
||||
"BRKH_INT_NE6D2",
|
||||
"BRKH_INT_LVB_L10",
|
||||
"BRKH_INT_NN6E1",
|
||||
"BRKH_INT_LV8",
|
||||
"BRKH_INT_L_LV15",
|
||||
"BRKH_INT_LV15",
|
||||
"BRKH_INT_NE6B1",
|
||||
"BRKH_INT_SW6C3",
|
||||
"BRKH_INT_NW6A0",
|
||||
"BRKH_INT_NL1BEG1",
|
||||
"BRKH_INT_NE2BEG2",
|
||||
"BRKH_INT_NN6BEG0",
|
||||
"BRKH_INT_LVB2",
|
||||
"BRKH_INT_L_LV17",
|
||||
"BRKH_INT_SS6END0",
|
||||
"BRKH_INT_NN6C1",
|
||||
"BRKH_INT_SS6C2",
|
||||
"BRKH_INT_SS2END2",
|
||||
"BRKH_INT_SR1END_N3_3",
|
||||
"BRKH_INT_LVB10",
|
||||
"BRKH_INT_L_LV8",
|
||||
"BRKH_INT_LV14",
|
||||
"BRKH_INT_NN6C0",
|
||||
"BRKH_INT_LV10",
|
||||
"BRKH_INT_NW6D3",
|
||||
"BRKH_INT_NE6C1",
|
||||
"BRKH_INT_NE6A2",
|
||||
"BRKH_INT_LVB3",
|
||||
"BRKH_INT_NN6D1",
|
||||
"BRKH_INT_NN6B2",
|
||||
"BRKH_INT_NW6C1",
|
||||
"BRKH_INT_SE6D1",
|
||||
"BRKH_INT_SL1END1",
|
||||
"BRKH_INT_SR1END1_SLOW",
|
||||
"BRKH_INT_LV3",
|
||||
"BRKH_INT_SS2A0",
|
||||
"BRKH_INT_SS6A1",
|
||||
"BRKH_INT_SS6B0",
|
||||
"BRKH_INT_NE6B2",
|
||||
"BRKH_INT_L_LV14",
|
||||
"BRKH_INT_LVB_L8",
|
||||
"BRKH_INT_NN2A1",
|
||||
"BRKH_INT_LVB12",
|
||||
"BRKH_INT_L_LV6",
|
||||
"BRKH_INT_NN6B0",
|
||||
"BRKH_INT_LVB_L5",
|
||||
"BRKH_INT_LVB11",
|
||||
"BRKH_INT_LV7",
|
||||
"BRKH_INT_SL1END0",
|
||||
"BRKH_INT_SE6E0",
|
||||
"BRKH_INT_NW6C3",
|
||||
"BRKH_INT_NE2BEG1",
|
||||
"BRKH_INT_NN2END_S2_0",
|
||||
"BRKH_INT_LVB_L12",
|
||||
"BRKH_INT_LV13",
|
||||
"BRKH_INT_SS6B3",
|
||||
"BRKH_INT_NN6A2",
|
||||
"BRKH_INT_NR1BEG2",
|
||||
"BRKH_INT_L_LV0",
|
||||
"BRKH_INT_NW6B2",
|
||||
"BRKH_INT_NL1BEG2",
|
||||
"BRKH_INT_SS6A3",
|
||||
"BRKH_INT_LV17",
|
||||
"BRKH_INT_L_LV12",
|
||||
"BRKH_INT_NE6B0",
|
||||
"BRKH_INT_WW2END3",
|
||||
"BRKH_INT_SR1END1",
|
||||
"BRKH_INT_NW6A2",
|
||||
"BRKH_INT_SW2A3",
|
||||
"BRKH_INT_NN6A3",
|
||||
"BRKH_INT_NW2BEG0",
|
||||
"BRKH_INT_NN2BEG3",
|
||||
"BRKH_INT_LV9",
|
||||
"BRKH_INT_NN6E2",
|
||||
"BRKH_INT_SE6D0",
|
||||
"BRKH_INT_NW2BEG3",
|
||||
"BRKH_INT_SS6E2",
|
||||
"BRKH_INT_NN6E0",
|
||||
"BRKH_INT_NL1BEG0",
|
||||
"BRKH_INT_NE6D3",
|
||||
"BRKH_INT_LV4",
|
||||
"BRKH_INT_NE6D1",
|
||||
"BRKH_INT_L_LV9",
|
||||
"BRKH_INT_EL1BEG3",
|
||||
"BRKH_INT_NN6END_S1_0",
|
||||
"BRKH_INT_SE2A2",
|
||||
"BRKH_INT_SW6D2",
|
||||
"BRKH_INT_SW6C1",
|
||||
"BRKH_INT_SW6D1",
|
||||
"BRKH_INT_L_LV7",
|
||||
"BRKH_INT_SS6END1",
|
||||
"BRKH_INT_NR1BEG0_SLOW",
|
||||
"BRKH_INT_L_LV4",
|
||||
"BRKH_INT_SW6B1",
|
||||
"BRKH_INT_LVB5",
|
||||
"BRKH_INT_SL1END3_SLOW",
|
||||
"BRKH_INT_LV16",
|
||||
"BRKH_INT_SS6A0",
|
||||
"BRKH_INT_NN6A1",
|
||||
"BRKH_INT_SL1END1_SLOW",
|
||||
"BRKH_INT_SE6C2",
|
||||
"BRKH_INT_SS2END3",
|
||||
"BRKH_INT_NN6BEG2",
|
||||
"BRKH_INT_NW6B0",
|
||||
"BRKH_INT_SS2A1",
|
||||
"BRKH_INT_SS6END_N0_3",
|
||||
"BRKH_INT_NE2BEG0",
|
||||
"BRKH_INT_WL1END3",
|
||||
"BRKH_INT_SS6D1",
|
||||
"BRKH_INT_BYP_BOUNCE3",
|
||||
"BRKH_INT_SS6A2",
|
||||
"BRKH_INT_SR1END3_SLOW",
|
||||
"BRKH_INT_SW2A1",
|
||||
"BRKH_INT_NE6C2",
|
||||
"BRKH_INT_SR1END2_SLOW",
|
||||
"BRKH_INT_SS6END3",
|
||||
"BRKH_INT_SS6D3",
|
||||
"BRKH_INT_FAN_BOUNCE_S3_0",
|
||||
"BRKH_INT_FAN_BOUNCE_S3_2",
|
||||
"BRKH_INT_NN6D0",
|
||||
"BRKH_INT_NW2END_S0_0",
|
||||
"BRKH_INT_SS6B1",
|
||||
"BRKH_INT_NN2A0",
|
||||
"BRKH_INT_LVB_L11",
|
||||
"BRKH_INT_SL1END0_SLOW",
|
||||
"BRKH_INT_SS2END_N0_3",
|
||||
"BRKH_INT_SS2END1",
|
||||
"BRKH_INT_NW6B1",
|
||||
"BRKH_INT_SE6C3",
|
||||
"BRKH_INT_NW2BEG2",
|
||||
"BRKH_INT_WW4END_S0_0",
|
||||
"BRKH_INT_SE6B1",
|
||||
"BRKH_INT_SE6B2",
|
||||
"BRKH_INT_WR1END_S1_0",
|
||||
"BRKH_INT_LVB6",
|
||||
"BRKH_INT_LVB4",
|
||||
"BRKH_INT_NN6B1",
|
||||
"BRKH_INT_SR1END2",
|
||||
"BRKH_INT_NE6A1",
|
||||
"BRKH_INT_SE6B3",
|
||||
"BRKH_INT_NN2A2",
|
||||
"BRKH_INT_L_LV2",
|
||||
"BRKH_INT_SW6B0",
|
||||
"BRKH_INT_SE2A3",
|
||||
"BRKH_INT_LVB7",
|
||||
"BRKH_INT_SE6D2",
|
||||
"BRKH_INT_NW6D0",
|
||||
"BRKH_INT_NN2BEG2",
|
||||
"BRKH_INT_NE6D0",
|
||||
"BRKH_INT_NN6C3",
|
||||
"BRKH_INT_SS6E3",
|
||||
"BRKH_INT_SE6C1",
|
||||
"BRKH_INT_SS6E1",
|
||||
"BRKH_INT_NN2BEG1",
|
||||
"BRKH_INT_ER1END3",
|
||||
"BRKH_INT_NE2BEG3",
|
||||
"BRKH_INT_SS6END2",
|
||||
"BRKH_INT_L_LV5",
|
||||
"BRKH_INT_SL1END2",
|
||||
"BRKH_INT_SS2A2",
|
||||
"BRKH_INT_L_LV13",
|
||||
"BRKH_INT_SW2END3",
|
||||
"BRKH_INT_LVB_L1",
|
||||
"BRKH_INT_SE6E3",
|
||||
"BRKH_INT_SW6C0",
|
||||
"BRKH_INT_NR1BEG1",
|
||||
"BRKH_INT_LV11",
|
||||
"BRKH_INT_L_LV3",
|
||||
"BRKH_INT_NL1BEG1_SLOW",
|
||||
"BRKH_INT_NL1BEG0_SLOW",
|
||||
"BRKH_INT_LVB_L2",
|
||||
"BRKH_INT_SE6B0",
|
||||
"BRKH_INT_SW6C2",
|
||||
"BRKH_INT_NN6D3",
|
||||
"BRKH_INT_NE6A0",
|
||||
"BRKH_INT_L_LV1",
|
||||
"BRKH_INT_NW6D2",
|
||||
"BRKH_INT_SW2A2",
|
||||
"BRKH_INT_NN6BEG1",
|
||||
"BRKH_INT_SW6D0",
|
||||
"BRKH_INT_LVB_L6",
|
||||
"BRKH_INT_SW6E2",
|
||||
"BRKH_INT_SR1END3",
|
||||
"BRKH_INT_L_LV10",
|
||||
"BRKH_INT_NW6D1",
|
||||
"BRKH_INT_NW6A1",
|
||||
"BRKH_INT_NR1BEG3_SLOW",
|
||||
"BRKH_INT_SW6END3",
|
||||
"BRKH_INT_NN2A3",
|
||||
"BRKH_INT_NN6C2",
|
||||
"BRKH_INT_L_LV16",
|
||||
"BRKH_INT_NW6C0",
|
||||
"BRKH_INT_LV5",
|
||||
"BRKH_INT_LVB_L7",
|
||||
"BRKH_INT_SS2END0",
|
||||
"BRKH_INT_LV12",
|
||||
"BRKH_INT_SL1END2_SLOW",
|
||||
"BRKH_INT_SE6D3",
|
||||
"BRKH_INT_BYP_BOUNCE6",
|
||||
"BRKH_INT_SW6B2",
|
||||
"BRKH_INT_BYP_BOUNCE2",
|
||||
"BRKH_INT_LV0",
|
||||
"BRKH_INT_NW6B3",
|
||||
"BRKH_INT_SW6D3",
|
||||
"BRKH_INT_NN6BEG3",
|
||||
"BRKH_INT_NN2BEG0",
|
||||
"BRKH_INT_LVB1",
|
||||
"BRKH_INT_NW6A3",
|
||||
"BRKH_INT_NE2END_S3_0",
|
||||
"BRKH_INT_LV2",
|
||||
"BRKH_INT_NE6C3",
|
||||
"BRKH_INT_LVB_L4",
|
||||
"BRKH_INT_WL1BEG3",
|
||||
"BRKH_INT_NR1BEG1_SLOW",
|
||||
"BRKH_INT_SE6E2",
|
||||
"BRKH_INT_SS2A3",
|
||||
"BRKH_INT_SW6B3",
|
||||
"BRKH_INT_NE6C0",
|
||||
"BRKH_INT_L_LV11",
|
||||
"BRKH_INT_LVB_L3",
|
||||
"BRKH_INT_LVB9",
|
||||
"BRKH_INT_NW6C2",
|
||||
"BRKH_INT_NE6B3",
|
||||
"BRKH_INT_FAN_BOUNCE_S3_4",
|
||||
"BRKH_INT_SS6C3",
|
||||
"BRKH_INT_LV6",
|
||||
"BRKH_INT_ER1BEG_S0",
|
||||
"BRKH_INT_FAN_BOUNCE_S3_6",
|
||||
"BRKH_INT_SS6D2",
|
||||
"BRKH_INT_WR1BEG_S0",
|
||||
"BRKH_INT_SE6C0",
|
||||
"BRKH_INT_NR1BEG2_SLOW",
|
||||
"BRKH_INT_LV1",
|
||||
"BRKH_INT_SL1END3",
|
||||
"BRKH_INT_SE2A1",
|
||||
"BRKH_INT_SW2A0",
|
||||
"BRKH_INT_SW6E1",
|
||||
"BRKH_INT_NW6END_S0_0",
|
||||
"BRKH_INT_SW6E0",
|
||||
"BRKH_INT_NN6D2",
|
||||
"BRKH_INT_SS6C1",
|
||||
"BRKH_INT_LVB_L9",
|
||||
"BRKH_INT_NN6A0",
|
||||
"BRKH_INT_SE2A0",
|
||||
"BRKH_INT_NL1BEG2_SLOW",
|
||||
"BRKH_INT_SW6E3",
|
||||
"BRKH_INT_SS6E0",
|
||||
"BRKH_INT_NE6A3",
|
||||
"BRKH_INT_NN6B3",
|
||||
"BRKH_INT_NN6E3",
|
||||
"BRKH_INT_SS6D0"
|
||||
],
|
||||
"tile_type": "BRKH_INT",
|
||||
"sites": []
|
||||
}
|
||||
"tile_type": "BRKH_INT",
|
||||
"sites": []
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,124 +1,124 @@
|
|||
{
|
||||
"pips": {},
|
||||
"wires": [
|
||||
"T_TERM_UTURN_INT_SE6D1",
|
||||
"T_TERM_UTURN_INT_LVB1",
|
||||
"T_TERM_UTURN_INT_SE6B0",
|
||||
"T_TERM_UTURN_INT_SL1END1_SLOW",
|
||||
"T_TERM_UTURN_INT_WR1END_S1_0",
|
||||
"T_TERM_UTURN_INT_SW6B1",
|
||||
"T_TERM_INT_UTURN_LV_R6",
|
||||
"T_TERM_UTURN_INT_SS2A3",
|
||||
"T_TERM_UTURN_INT_SS6E3",
|
||||
"T_TERM_UTURN_INT_SW6B0",
|
||||
"T_TERM_UTURN_INT_SW6B3",
|
||||
"T_TERM_INT_UTURN_LV_R16",
|
||||
"T_TERM_INT_UTURN_LV_R2",
|
||||
"T_TERM_UTURN_INT_SE6D2",
|
||||
"T_TERM_UTURN_INT_SL1END3_SLOW",
|
||||
"T_TERM_UTURN_INT_LV_L16",
|
||||
"T_TERM_UTURN_INT_SE6C3",
|
||||
"T_TERM_UTURN_INT_SE6B1",
|
||||
"T_TERM_UTURN_INT_SE2A0",
|
||||
"T_TERM_UTURN_INT_LV_L17",
|
||||
"T_TERM_UTURN_INT_SS6END2",
|
||||
"T_TERM_UTURN_INT_SW6D0",
|
||||
"T_TERM_UTURN_INT_SS2END2",
|
||||
"T_TERM_UTURN_INT_SW6E1",
|
||||
"T_TERM_UTURN_INT_SS6D2",
|
||||
"T_TERM_UTURN_INT_SR1END2_SLOW",
|
||||
"T_TERM_UTURN_INT_SW6D2",
|
||||
"T_TERM_UTURN_INT_SE6E2",
|
||||
"T_TERM_UTURN_INT_LVB2",
|
||||
"T_TERM_UTURN_INT_SE6C1",
|
||||
"T_TERM_UTURN_INT_LVB_L0",
|
||||
"T_TERM_UTURN_INT_SW6D3",
|
||||
"T_TERM_UTURN_INT_LV_L7",
|
||||
"T_TERM_UTURN_INT_LV_L3",
|
||||
"T_TERM_UTURN_INT_SS6C2",
|
||||
"T_TERM_UTURN_INT_SW2A2",
|
||||
"T_TERM_UTURN_INT_LVB_L4",
|
||||
"T_TERM_UTURN_INT_SS6END0",
|
||||
"T_TERM_INT_UTURN_LV_R9",
|
||||
"T_TERM_UTURN_INT_SW6C2",
|
||||
"T_TERM_UTURN_INT_WR1BEG_S0",
|
||||
"T_TERM_UTURN_INT_SS6C0",
|
||||
"T_TERM_UTURN_INT_SS6D1",
|
||||
"T_TERM_UTURN_INT_SE6D0",
|
||||
"T_TERM_UTURN_INT_SS2A0",
|
||||
"T_TERM_UTURN_INT_FAN_BOUNCE_S3_2",
|
||||
"T_TERM_UTURN_INT_SS6E1",
|
||||
"T_TERM_UTURN_INT_SS6A2",
|
||||
"T_TERM_UTURN_INT_SW6E3",
|
||||
"T_TERM_UTURN_INT_SE6C2",
|
||||
"T_TERM_UTURN_INT_SW6B2",
|
||||
"T_TERM_UTURN_INT_SS6B0",
|
||||
"T_TERM_UTURN_INT_SS6C1",
|
||||
"T_TERM_UTURN_INT_SS6A0",
|
||||
"T_TERM_UTURN_INT_LVB_L2",
|
||||
"T_TERM_INT_UTURN_LV_R5",
|
||||
"T_TERM_UTURN_INT_SE6E3",
|
||||
"T_TERM_UTURN_INT_SE2A2",
|
||||
"T_TERM_UTURN_INT_LV_L6",
|
||||
"T_TERM_UTURN_INT_SS2A1",
|
||||
"T_TERM_UTURN_INT_SR1END3_SLOW",
|
||||
"T_TERM_UTURN_INT_LVB_L5",
|
||||
"T_TERM_UTURN_INT_SE2A3",
|
||||
"T_TERM_UTURN_INT_SL1END2_SLOW",
|
||||
"T_TERM_UTURN_INT_SS2END0",
|
||||
"T_TERM_UTURN_INT_ER1END3",
|
||||
"T_TERM_UTURN_INT_SS2A2",
|
||||
"T_TERM_UTURN_INT_LV_L4",
|
||||
"T_TERM_UTURN_INT_SW6C1",
|
||||
"T_TERM_INT_UTURN_LV_R7",
|
||||
"T_TERM_UTURN_INT_SW6C3",
|
||||
"T_TERM_UTURN_INT_SW2A1",
|
||||
"T_TERM_UTURN_INT_SS2END3",
|
||||
"T_TERM_UTURN_INT_FAN_BOUNCE_S3_4",
|
||||
"T_TERM_UTURN_INT_FAN_BOUNCE_S3_6",
|
||||
"T_TERM_UTURN_INT_SS6C3",
|
||||
"T_TERM_UTURN_INT_LVB_L3",
|
||||
"T_TERM_UTURN_INT_SW6E0",
|
||||
"T_TERM_UTURN_INT_SW2A0",
|
||||
"T_TERM_INT_UTURN_LV_R3",
|
||||
"T_TERM_UTURN_INT_SE6C0",
|
||||
"T_TERM_UTURN_INT_SS2END1",
|
||||
"T_TERM_INT_UTURN_LV_R4",
|
||||
"T_TERM_UTURN_INT_SE6B2",
|
||||
"T_TERM_UTURN_INT_SL1END0_SLOW",
|
||||
"T_TERM_UTURN_INT_LVB4",
|
||||
"T_TERM_UTURN_INT_LV_L2",
|
||||
"T_TERM_UTURN_INT_SW6C0",
|
||||
"T_TERM_UTURN_INT_LVB_L1",
|
||||
"T_TERM_UTURN_INT_SS6E2",
|
||||
"T_TERM_UTURN_INT_SS6B2",
|
||||
"T_TERM_UTURN_INT_SW2A3",
|
||||
"T_TERM_UTURN_INT_SE6D3",
|
||||
"T_TERM_UTURN_INT_SS6D3",
|
||||
"T_TERM_UTURN_INT_SR1END1_SLOW",
|
||||
"T_TERM_UTURN_INT_LVB3",
|
||||
"T_TERM_UTURN_INT_SE6E0",
|
||||
"T_TERM_UTURN_INT_SS6A3",
|
||||
"T_TERM_UTURN_INT_LVB5",
|
||||
"T_TERM_UTURN_INT_LV_L9",
|
||||
"T_TERM_UTURN_INT_SS6B1",
|
||||
"T_TERM_UTURN_INT_SS6E0",
|
||||
"T_TERM_UTURN_INT_SS6D0",
|
||||
"T_TERM_UTURN_INT_SW6D1",
|
||||
"T_TERM_UTURN_INT_SE6B3",
|
||||
"T_TERM_UTURN_INT_SS6END1",
|
||||
"T_TERM_UTURN_INT_LV_L5",
|
||||
"T_TERM_UTURN_INT_LVB0",
|
||||
"T_TERM_UTURN_INT_SE6E1",
|
||||
"T_TERM_UTURN_INT_FAN_BOUNCE_S3_0",
|
||||
"T_TERM_UTURN_INT_SE2A1",
|
||||
"T_TERM_UTURN_INT_SS6B3",
|
||||
"T_TERM_INT_UTURN_LV_R17",
|
||||
"T_TERM_UTURN_INT_SS6END3",
|
||||
"T_TERM_UTURN_INT_SS6A1",
|
||||
"T_TERM_UTURN_INT_SW6E2",
|
||||
"T_TERM_UTURN_INT_ER1BEG_S0"
|
||||
],
|
||||
"tile_type": "BRKH_TERM_INT",
|
||||
"sites": []
|
||||
}
|
||||
"wires": [
|
||||
"T_TERM_UTURN_INT_SE6D1",
|
||||
"T_TERM_UTURN_INT_LV_L9",
|
||||
"T_TERM_UTURN_INT_SS6C2",
|
||||
"T_TERM_UTURN_INT_WR1BEG_S0",
|
||||
"T_TERM_UTURN_INT_SE6B0",
|
||||
"T_TERM_UTURN_INT_LVB_L3",
|
||||
"T_TERM_UTURN_INT_LVB_L5",
|
||||
"T_TERM_UTURN_INT_FAN_BOUNCE_S3_2",
|
||||
"T_TERM_UTURN_INT_SW2A1",
|
||||
"T_TERM_UTURN_INT_SL1END2_SLOW",
|
||||
"T_TERM_UTURN_INT_LVB_L1",
|
||||
"T_TERM_UTURN_INT_FAN_BOUNCE_S3_0",
|
||||
"T_TERM_UTURN_INT_SE6D3",
|
||||
"T_TERM_UTURN_INT_SL1END1_SLOW",
|
||||
"T_TERM_UTURN_INT_SW6B1",
|
||||
"T_TERM_UTURN_INT_LV_L6",
|
||||
"T_TERM_UTURN_INT_SS6E1",
|
||||
"T_TERM_UTURN_INT_LVB_L0",
|
||||
"T_TERM_UTURN_INT_SS2END0",
|
||||
"T_TERM_UTURN_INT_SW6E1",
|
||||
"T_TERM_UTURN_INT_SW6E2",
|
||||
"T_TERM_UTURN_INT_LVB0",
|
||||
"T_TERM_UTURN_INT_LVB4",
|
||||
"T_TERM_INT_UTURN_LV_R3",
|
||||
"T_TERM_UTURN_INT_SS6END2",
|
||||
"T_TERM_UTURN_INT_SS2A2",
|
||||
"T_TERM_UTURN_INT_SW6D1",
|
||||
"T_TERM_UTURN_INT_SR1END3_SLOW",
|
||||
"T_TERM_UTURN_INT_LV_L16",
|
||||
"T_TERM_UTURN_INT_SS6E3",
|
||||
"T_TERM_UTURN_INT_SS2A3",
|
||||
"T_TERM_INT_UTURN_LV_R4",
|
||||
"T_TERM_UTURN_INT_SS2END1",
|
||||
"T_TERM_UTURN_INT_LVB2",
|
||||
"T_TERM_UTURN_INT_LV_L2",
|
||||
"T_TERM_INT_UTURN_LV_R6",
|
||||
"T_TERM_INT_UTURN_LV_R2",
|
||||
"T_TERM_UTURN_INT_SS6B2",
|
||||
"T_TERM_UTURN_INT_SS2END3",
|
||||
"T_TERM_UTURN_INT_SS2END2",
|
||||
"T_TERM_UTURN_INT_SS6E2",
|
||||
"T_TERM_UTURN_INT_SE6C0",
|
||||
"T_TERM_UTURN_INT_SW2A3",
|
||||
"T_TERM_UTURN_INT_SR1END2_SLOW",
|
||||
"T_TERM_UTURN_INT_SS6A2",
|
||||
"T_TERM_UTURN_INT_SW6D3",
|
||||
"T_TERM_UTURN_INT_SS6E0",
|
||||
"T_TERM_UTURN_INT_FAN_BOUNCE_S3_6",
|
||||
"T_TERM_UTURN_INT_SS6C0",
|
||||
"T_TERM_UTURN_INT_SW6C1",
|
||||
"T_TERM_UTURN_INT_ER1END3",
|
||||
"T_TERM_UTURN_INT_SS6C1",
|
||||
"T_TERM_UTURN_INT_SE6D0",
|
||||
"T_TERM_UTURN_INT_SS6A3",
|
||||
"T_TERM_UTURN_INT_SE6E3",
|
||||
"T_TERM_UTURN_INT_SE2A0",
|
||||
"T_TERM_UTURN_INT_LVB_L4",
|
||||
"T_TERM_UTURN_INT_SS6B1",
|
||||
"T_TERM_UTURN_INT_SW6D0",
|
||||
"T_TERM_UTURN_INT_LVB5",
|
||||
"T_TERM_UTURN_INT_SS6A1",
|
||||
"T_TERM_UTURN_INT_SS6D2",
|
||||
"T_TERM_UTURN_INT_SS6A0",
|
||||
"T_TERM_UTURN_INT_SE6E2",
|
||||
"T_TERM_UTURN_INT_SE6D2",
|
||||
"T_TERM_UTURN_INT_SW6D2",
|
||||
"T_TERM_UTURN_INT_FAN_BOUNCE_S3_4",
|
||||
"T_TERM_UTURN_INT_ER1BEG_S0",
|
||||
"T_TERM_UTURN_INT_SE6C3",
|
||||
"T_TERM_UTURN_INT_SS6END0",
|
||||
"T_TERM_UTURN_INT_SS6B3",
|
||||
"T_TERM_UTURN_INT_SE6C2",
|
||||
"T_TERM_UTURN_INT_SE2A2",
|
||||
"T_TERM_INT_UTURN_LV_R7",
|
||||
"T_TERM_UTURN_INT_SS6B0",
|
||||
"T_TERM_INT_UTURN_LV_R16",
|
||||
"T_TERM_UTURN_INT_SW6B0",
|
||||
"T_TERM_UTURN_INT_SW6C2",
|
||||
"T_TERM_UTURN_INT_LV_L4",
|
||||
"T_TERM_UTURN_INT_SW2A2",
|
||||
"T_TERM_UTURN_INT_SE6C1",
|
||||
"T_TERM_UTURN_INT_LV_L7",
|
||||
"T_TERM_INT_UTURN_LV_R17",
|
||||
"T_TERM_UTURN_INT_LVB3",
|
||||
"T_TERM_UTURN_INT_SS6C3",
|
||||
"T_TERM_UTURN_INT_SL1END0_SLOW",
|
||||
"T_TERM_UTURN_INT_SS6D3",
|
||||
"T_TERM_INT_UTURN_LV_R9",
|
||||
"T_TERM_UTURN_INT_SW6C0",
|
||||
"T_TERM_UTURN_INT_SE2A1",
|
||||
"T_TERM_UTURN_INT_SS6END3",
|
||||
"T_TERM_UTURN_INT_LV_L3",
|
||||
"T_TERM_UTURN_INT_SS6D1",
|
||||
"T_TERM_UTURN_INT_LVB1",
|
||||
"T_TERM_UTURN_INT_SW6E0",
|
||||
"T_TERM_UTURN_INT_SE6E1",
|
||||
"T_TERM_UTURN_INT_SS6D0",
|
||||
"T_TERM_UTURN_INT_SE6E0",
|
||||
"T_TERM_UTURN_INT_SS2A1",
|
||||
"T_TERM_UTURN_INT_SE6B2",
|
||||
"T_TERM_UTURN_INT_SR1END1_SLOW",
|
||||
"T_TERM_UTURN_INT_LV_L17",
|
||||
"T_TERM_UTURN_INT_SW6B3",
|
||||
"T_TERM_UTURN_INT_SS2A0",
|
||||
"T_TERM_UTURN_INT_LVB_L2",
|
||||
"T_TERM_UTURN_INT_SW6B2",
|
||||
"T_TERM_INT_UTURN_LV_R5",
|
||||
"T_TERM_UTURN_INT_SE6B1",
|
||||
"T_TERM_UTURN_INT_SS6END1",
|
||||
"T_TERM_UTURN_INT_WR1END_S1_0",
|
||||
"T_TERM_UTURN_INT_SE6B3",
|
||||
"T_TERM_UTURN_INT_LV_L5",
|
||||
"T_TERM_UTURN_INT_SL1END3_SLOW",
|
||||
"T_TERM_UTURN_INT_SE2A3",
|
||||
"T_TERM_UTURN_INT_SW6C3",
|
||||
"T_TERM_UTURN_INT_SW6E3",
|
||||
"T_TERM_UTURN_INT_SW2A0"
|
||||
],
|
||||
"pips": {},
|
||||
"tile_type": "BRKH_TERM_INT",
|
||||
"sites": []
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,125 +1,125 @@
|
|||
{
|
||||
"pips": {},
|
||||
"wires": [
|
||||
"B_TERM_UTURN_INT_SW6C0",
|
||||
"B_TERM_UTURN_INT_LVB_L0",
|
||||
"B_TERM_UTURN_INT_LVB5",
|
||||
"B_TERM_UTURN_INT_SE6D3",
|
||||
"B_TERM_UTURN_INT_LV4",
|
||||
"B_TERM_UTURN_INT_SS2BEG3",
|
||||
"B_TERM_UTURN_INT_SS6B1",
|
||||
"B_TERM_UTURN_INT_SE2BEG0",
|
||||
"B_TERM_UTURN_INT_LV_L5",
|
||||
"B_TERM_UTURN_INT_SE6D1",
|
||||
"B_TERM_UTURN_INT_LV2",
|
||||
"B_TERM_UTURN_INT_LVB_L2",
|
||||
"B_TERM_UTURN_INT_SS6BEG3",
|
||||
"B_TERM_UTURN_INT_LVB1",
|
||||
"B_TERM_UTURN_INT_SL1BEG2",
|
||||
"B_TERM_UTURN_INT_SL1BEG1",
|
||||
"B_TERM_UTURN_INT_SS6BEG1",
|
||||
"B_TERM_UTURN_INT_LVB2",
|
||||
"B_TERM_UTURN_INT_SE6A2",
|
||||
"B_TERM_UTURN_INT_SS6D3",
|
||||
"B_TERM_UTURN_INT_SS6BEG0",
|
||||
"B_TERM_UTURN_INT_LV9",
|
||||
"B_TERM_UTURN_INT_SE2BEG2",
|
||||
"B_TERM_UTURN_INT_LV_L2",
|
||||
"B_TERM_UTURN_INT_SE6B2",
|
||||
"B_TERM_UTURN_INT_LVB_L3",
|
||||
"B_TERM_UTURN_INT_LV7",
|
||||
"B_TERM_UTURN_INT_SS6D2",
|
||||
"B_TERM_UTURN_INT_LVB_L4",
|
||||
"B_TERM_UTURN_INT_SW6C2",
|
||||
"B_TERM_UTURN_INT_SS6B3",
|
||||
"B_TERM_UTURN_INT_SS2A1",
|
||||
"B_TERM_UTURN_INT_SE2BEG1",
|
||||
"B_TERM_UTURN_INT_SS6A2",
|
||||
"B_TERM_UTURN_INT_SE6A0",
|
||||
"B_TERM_UTURN_INT_LV6",
|
||||
"B_TERM_UTURN_INT_LV_L6",
|
||||
"B_TERM_UTURN_INT_SS2A2",
|
||||
"B_TERM_UTURN_INT_WR1BEG0",
|
||||
"B_TERM_UTURN_INT_SE6B0",
|
||||
"B_TERM_UTURN_INT_SL1BEG0",
|
||||
"B_TERM_UTURN_INT_SW6A3",
|
||||
"B_TERM_UTURN_INT_LVB0",
|
||||
"B_TERM_UTURN_INT_LVB_L1",
|
||||
"B_TERM_UTURN_INT_SE6C0",
|
||||
"B_TERM_UTURN_INT_LV_L9",
|
||||
"B_TERM_UTURN_INT_SW6B2",
|
||||
"B_TERM_UTURN_INT_LVB3",
|
||||
"B_TERM_UTURN_INT_SW2BEG0",
|
||||
"B_TERM_UTURN_INT_SW6A1",
|
||||
"B_TERM_UTURN_INT_SE6D2",
|
||||
"B_TERM_UTURN_INT_LV_L3",
|
||||
"B_TERM_UTURN_INT_SR1BEG3",
|
||||
"B_TERM_UTURN_INT_FAN_BOUNCE6",
|
||||
"B_TERM_UTURN_INT_SW6END_N0_3",
|
||||
"B_TERM_UTURN_INT_SE6B1",
|
||||
"B_TERM_UTURN_INT_LV5",
|
||||
"B_TERM_UTURN_INT_SR1BEG2",
|
||||
"B_TERM_UTURN_INT_FAN_BOUNCE2",
|
||||
"B_TERM_UTURN_INT_SW6A2",
|
||||
"B_TERM_UTURN_INT_SS2BEG2",
|
||||
"B_TERM_UTURN_INT_SS6D0",
|
||||
"B_TERM_UTURN_INT_SE6A1",
|
||||
"B_TERM_UTURN_INT_SS6A0",
|
||||
"B_TERM_UTURN_INT_SS2BEG1",
|
||||
"B_TERM_UTURN_INT_SE6C3",
|
||||
"B_TERM_UTURN_INT_SS6C2",
|
||||
"B_TERM_UTURN_INT_FAN_BOUNCE4",
|
||||
"B_TERM_UTURN_INT_SS6A3",
|
||||
"B_TERM_UTURN_INT_SW6D2",
|
||||
"B_TERM_UTURN_INT_SS6E3",
|
||||
"B_TERM_UTURN_INT_SW2BEG2",
|
||||
"B_TERM_UTURN_INT_LV_L8",
|
||||
"B_TERM_UTURN_INT_SW6B3",
|
||||
"B_TERM_UTURN_INT_SW6B1",
|
||||
"B_TERM_UTURN_INT_SW2BEG1",
|
||||
"B_TERM_UTURN_INT_LVB4",
|
||||
"B_TERM_UTURN_INT_SS2BEG0",
|
||||
"B_TERM_UTURN_INT_SR1BEG1",
|
||||
"B_TERM_UTURN_INT_SE6C2",
|
||||
"B_TERM_UTURN_INT_SW2BEG3",
|
||||
"B_TERM_UTURN_INT_WR1END0",
|
||||
"B_TERM_UTURN_INT_LV_L7",
|
||||
"B_TERM_UTURN_INT_SW6D1",
|
||||
"B_TERM_UTURN_INT_LVB_L5",
|
||||
"B_TERM_UTURN_INT_SE6C1",
|
||||
"B_TERM_UTURN_INT_LV18",
|
||||
"B_TERM_UTURN_INT_SW6D3",
|
||||
"B_TERM_UTURN_INT_SL1BEG3",
|
||||
"B_TERM_UTURN_INT_SS6E1",
|
||||
"B_TERM_UTURN_INT_SW6C3",
|
||||
"B_TERM_UTURN_INT_SS2A3",
|
||||
"B_TERM_UTURN_INT_SS6E0",
|
||||
"B_TERM_UTURN_INT_ER1BEG0",
|
||||
"B_TERM_UTURN_INT_ER1END_N3_3",
|
||||
"B_TERM_UTURN_INT_SE6B3",
|
||||
"B_TERM_UTURN_INT_SS6B2",
|
||||
"B_TERM_UTURN_INT_SW6B0",
|
||||
"B_TERM_UTURN_INT_SW6A0",
|
||||
"B_TERM_UTURN_INT_LV3",
|
||||
"B_TERM_UTURN_INT_SS6C3",
|
||||
"B_TERM_UTURN_INT_LV8",
|
||||
"B_TERM_UTURN_INT_SE6A3",
|
||||
"B_TERM_UTURN_INT_SS6C1",
|
||||
"B_TERM_UTURN_INT_SS6B0",
|
||||
"B_TERM_UTURN_INT_SS6C0",
|
||||
"B_TERM_UTURN_INT_SW6C1",
|
||||
"B_TERM_UTURN_INT_SS6D1",
|
||||
"B_TERM_UTURN_INT_LV_L4",
|
||||
"B_TERM_UTURN_INT_SS2A0",
|
||||
"B_TERM_UTURN_INT_SS6A1",
|
||||
"B_TERM_UTURN_INT_SS6BEG2",
|
||||
"B_TERM_UTURN_INT_SS6E2",
|
||||
"B_TERM_UTURN_INT_SW6D0",
|
||||
"B_TERM_UTURN_INT_SE6D0",
|
||||
"B_TERM_UTURN_INT_LV_L18",
|
||||
"B_TERM_UTURN_INT_FAN_BOUNCE0",
|
||||
"B_TERM_UTURN_INT_SE2BEG3"
|
||||
],
|
||||
"tile_type": "B_TERM_INT",
|
||||
"sites": []
|
||||
}
|
||||
"wires": [
|
||||
"B_TERM_UTURN_INT_SS2A1",
|
||||
"B_TERM_UTURN_INT_SW6C0",
|
||||
"B_TERM_UTURN_INT_LV3",
|
||||
"B_TERM_UTURN_INT_LVB_L1",
|
||||
"B_TERM_UTURN_INT_SE6A1",
|
||||
"B_TERM_UTURN_INT_SS6D0",
|
||||
"B_TERM_UTURN_INT_SS6B3",
|
||||
"B_TERM_UTURN_INT_LVB3",
|
||||
"B_TERM_UTURN_INT_SS6BEG1",
|
||||
"B_TERM_UTURN_INT_SS6E2",
|
||||
"B_TERM_UTURN_INT_LV_L5",
|
||||
"B_TERM_UTURN_INT_SE6D3",
|
||||
"B_TERM_UTURN_INT_LV_L2",
|
||||
"B_TERM_UTURN_INT_SE6C0",
|
||||
"B_TERM_UTURN_INT_LV5",
|
||||
"B_TERM_UTURN_INT_LV9",
|
||||
"B_TERM_UTURN_INT_SE6B3",
|
||||
"B_TERM_UTURN_INT_LV2",
|
||||
"B_TERM_UTURN_INT_LVB1",
|
||||
"B_TERM_UTURN_INT_ER1BEG0",
|
||||
"B_TERM_UTURN_INT_SS2BEG1",
|
||||
"B_TERM_UTURN_INT_SW2BEG2",
|
||||
"B_TERM_UTURN_INT_SS6BEG2",
|
||||
"B_TERM_UTURN_INT_FAN_BOUNCE0",
|
||||
"B_TERM_UTURN_INT_SW6END_N0_3",
|
||||
"B_TERM_UTURN_INT_LV7",
|
||||
"B_TERM_UTURN_INT_SS6B2",
|
||||
"B_TERM_UTURN_INT_SS6E3",
|
||||
"B_TERM_UTURN_INT_SW6C1",
|
||||
"B_TERM_UTURN_INT_LVB4",
|
||||
"B_TERM_UTURN_INT_SE6C2",
|
||||
"B_TERM_UTURN_INT_SS2BEG3",
|
||||
"B_TERM_UTURN_INT_LVB_L2",
|
||||
"B_TERM_UTURN_INT_SS6A2",
|
||||
"B_TERM_UTURN_INT_SW6D2",
|
||||
"B_TERM_UTURN_INT_SL1BEG1",
|
||||
"B_TERM_UTURN_INT_LV_L3",
|
||||
"B_TERM_UTURN_INT_SS2BEG2",
|
||||
"B_TERM_UTURN_INT_LVB2",
|
||||
"B_TERM_UTURN_INT_SR1BEG1",
|
||||
"B_TERM_UTURN_INT_ER1END_N3_3",
|
||||
"B_TERM_UTURN_INT_SS6A3",
|
||||
"B_TERM_UTURN_INT_SW6A1",
|
||||
"B_TERM_UTURN_INT_SL1BEG0",
|
||||
"B_TERM_UTURN_INT_SS6B1",
|
||||
"B_TERM_UTURN_INT_SE2BEG2",
|
||||
"B_TERM_UTURN_INT_LV_L9",
|
||||
"B_TERM_UTURN_INT_SS6BEG3",
|
||||
"B_TERM_UTURN_INT_SL1BEG3",
|
||||
"B_TERM_UTURN_INT_LV_L6",
|
||||
"B_TERM_UTURN_INT_LVB5",
|
||||
"B_TERM_UTURN_INT_LVB_L4",
|
||||
"B_TERM_UTURN_INT_SR1BEG2",
|
||||
"B_TERM_UTURN_INT_SS2A3",
|
||||
"B_TERM_UTURN_INT_SS6D1",
|
||||
"B_TERM_UTURN_INT_LVB0",
|
||||
"B_TERM_UTURN_INT_LV_L4",
|
||||
"B_TERM_UTURN_INT_SS6C3",
|
||||
"B_TERM_UTURN_INT_FAN_BOUNCE4",
|
||||
"B_TERM_UTURN_INT_SW6C3",
|
||||
"B_TERM_UTURN_INT_LV6",
|
||||
"B_TERM_UTURN_INT_SS6BEG0",
|
||||
"B_TERM_UTURN_INT_LV_L7",
|
||||
"B_TERM_UTURN_INT_SW6B0",
|
||||
"B_TERM_UTURN_INT_SS6D3",
|
||||
"B_TERM_UTURN_INT_FAN_BOUNCE2",
|
||||
"B_TERM_UTURN_INT_SS6D2",
|
||||
"B_TERM_UTURN_INT_SW6D3",
|
||||
"B_TERM_UTURN_INT_SL1BEG2",
|
||||
"B_TERM_UTURN_INT_SW6D1",
|
||||
"B_TERM_UTURN_INT_SS6C1",
|
||||
"B_TERM_UTURN_INT_LVB_L5",
|
||||
"B_TERM_UTURN_INT_SS2A2",
|
||||
"B_TERM_UTURN_INT_SS6E0",
|
||||
"B_TERM_UTURN_INT_SW2BEG1",
|
||||
"B_TERM_UTURN_INT_SW6A0",
|
||||
"B_TERM_UTURN_INT_SE2BEG0",
|
||||
"B_TERM_UTURN_INT_LV4",
|
||||
"B_TERM_UTURN_INT_SS6A0",
|
||||
"B_TERM_UTURN_INT_SW6A2",
|
||||
"B_TERM_UTURN_INT_SE6D2",
|
||||
"B_TERM_UTURN_INT_SE6C3",
|
||||
"B_TERM_UTURN_INT_FAN_BOUNCE6",
|
||||
"B_TERM_UTURN_INT_LV_L18",
|
||||
"B_TERM_UTURN_INT_LVB_L3",
|
||||
"B_TERM_UTURN_INT_LV18",
|
||||
"B_TERM_UTURN_INT_SR1BEG3",
|
||||
"B_TERM_UTURN_INT_SS6C0",
|
||||
"B_TERM_UTURN_INT_SE6D1",
|
||||
"B_TERM_UTURN_INT_SE6B1",
|
||||
"B_TERM_UTURN_INT_SE6A2",
|
||||
"B_TERM_UTURN_INT_SS2BEG0",
|
||||
"B_TERM_UTURN_INT_SW6B1",
|
||||
"B_TERM_UTURN_INT_SE6B2",
|
||||
"B_TERM_UTURN_INT_SE2BEG3",
|
||||
"B_TERM_UTURN_INT_WR1END0",
|
||||
"B_TERM_UTURN_INT_SW6B2",
|
||||
"B_TERM_UTURN_INT_SE6B0",
|
||||
"B_TERM_UTURN_INT_SS6C2",
|
||||
"B_TERM_UTURN_INT_SW2BEG3",
|
||||
"B_TERM_UTURN_INT_SE2BEG1",
|
||||
"B_TERM_UTURN_INT_SE6A3",
|
||||
"B_TERM_UTURN_INT_SE6D0",
|
||||
"B_TERM_UTURN_INT_SS6A1",
|
||||
"B_TERM_UTURN_INT_LV8",
|
||||
"B_TERM_UTURN_INT_LVB_L0",
|
||||
"B_TERM_UTURN_INT_WR1BEG0",
|
||||
"B_TERM_UTURN_INT_SW2BEG0",
|
||||
"B_TERM_UTURN_INT_SW6A3",
|
||||
"B_TERM_UTURN_INT_SE6C1",
|
||||
"B_TERM_UTURN_INT_LV_L8",
|
||||
"B_TERM_UTURN_INT_SS6B0",
|
||||
"B_TERM_UTURN_INT_SW6B3",
|
||||
"B_TERM_UTURN_INT_SW6C2",
|
||||
"B_TERM_UTURN_INT_SW6D0",
|
||||
"B_TERM_UTURN_INT_SS2A0",
|
||||
"B_TERM_UTURN_INT_SS6E1",
|
||||
"B_TERM_UTURN_INT_SE6A0"
|
||||
],
|
||||
"pips": {},
|
||||
"tile_type": "B_TERM_INT",
|
||||
"sites": []
|
||||
}
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -1,261 +1,261 @@
|
|||
{
|
||||
"pips": {},
|
||||
"wires": [
|
||||
"CLK_FEED_CK_GCLK13",
|
||||
"CLK_FEED_CK_BUFG_CASC3",
|
||||
"CLK_FEED_WW4B2",
|
||||
"CLK_FEED_EE4B2",
|
||||
"CLK_FEED_CK_GCLK26",
|
||||
"CLK_FEED_WW2A0",
|
||||
"CLK_FEED_EE4A2",
|
||||
"CLK_FEED_R_CK_BUFG_CASC25",
|
||||
"CLK_FEED_R_CK_GCLK4",
|
||||
"CLK_FEED_R_CK_BUFG_CASC4",
|
||||
"CLK_FEED_EE4BEG1",
|
||||
"CLK_FEED_CK_GCLK29",
|
||||
"CLK_FEED_WW4C0",
|
||||
"CLK_FEED_EE4BEG2",
|
||||
"CLK_FEED_CK_GCLK19",
|
||||
"CLK_FEED_CK_BUFG_CASC22",
|
||||
"CLK_FEED_CK_BUFG_CASC5",
|
||||
"CLK_FEED_R_CK_BUFG_CASC29",
|
||||
"CLK_FEED_SW4END1",
|
||||
"CLK_FEED_LH12",
|
||||
"CLK_FEED_CK_BUFG_CASC13",
|
||||
"CLK_FEED_CK_BUFG_CASC7",
|
||||
"CLK_FEED_WW4END3",
|
||||
"CLK_FEED_SE4C1",
|
||||
"CLK_FEED_CK_GCLK9",
|
||||
"CLK_FEED_EE4C3",
|
||||
"CLK_FEED_R_CK_BUFG_CASC22",
|
||||
"CLK_FEED_R_CK_BUFG_CASC19",
|
||||
"CLK_FEED_WW2END0",
|
||||
"CLK_FEED_CK_GCLK2",
|
||||
"CLK_FEED_R_CK_BUFG_CASC11",
|
||||
"CLK_FEED_R_CK_GCLK11",
|
||||
"CLK_FEED_CK_GCLK15",
|
||||
"CLK_FEED_R_CK_BUFG_CASC5",
|
||||
"CLK_FEED_R_CK_BUFG_CASC16",
|
||||
"CLK_FEED_NE4BEG0",
|
||||
"CLK_FEED_SE4BEG3",
|
||||
"CLK_FEED_WW4A2",
|
||||
"CLK_FEED_SE4BEG1",
|
||||
"CLK_FEED_CK_GCLK0",
|
||||
"CLK_FEED_WW2A2",
|
||||
"CLK_FEED_R_CK_GCLK13",
|
||||
"CLK_FEED_R_CK_BUFG_CASC24",
|
||||
"CLK_FEED_R_CK_BUFG_CASC13",
|
||||
"CLK_FEED_CK_GCLK17",
|
||||
"CLK_FEED_CK_BUFG_CASC11",
|
||||
"CLK_FEED_EE4BEG0",
|
||||
"CLK_FEED_CK_GCLK11",
|
||||
"CLK_FEED_CK_GCLK27",
|
||||
"CLK_FEED_R_CK_GCLK0",
|
||||
"CLK_FEED_R_CK_GCLK5",
|
||||
"CLK_FEED_CK_GCLK3",
|
||||
"CLK_FEED_CK_BUFG_CASC2",
|
||||
"CLK_FEED_LH10",
|
||||
"CLK_FEED_SE4C0",
|
||||
"CLK_FEED_LH3",
|
||||
"CLK_FEED_WW2A3",
|
||||
"CLK_FEED_NW4A1",
|
||||
"CLK_FEED_R_CK_BUFG_CASC14",
|
||||
"CLK_FEED_R_CK_BUFG_CASC30",
|
||||
"CLK_FEED_LH5",
|
||||
"CLK_FEED_NW4A2",
|
||||
"CLK_FEED_WW4END1",
|
||||
"CLK_FEED_EE2BEG2",
|
||||
"CLK_FEED_WL1END0",
|
||||
"CLK_FEED_NE4BEG3",
|
||||
"CLK_FEED_WL1END1",
|
||||
"CLK_FEED_SW2A1",
|
||||
"CLK_FEED_EE2BEG0",
|
||||
"CLK_FEED_CK_GCLK7",
|
||||
"CLK_FEED_CK_GCLK22",
|
||||
"CLK_FEED_EE4A1",
|
||||
"CLK_FEED_EE4BEG3",
|
||||
"CLK_FEED_R_CK_BUFG_CASC20",
|
||||
"CLK_FEED_CK_BUFG_CASC8",
|
||||
"CLK_FEED_EE2BEG1",
|
||||
"CLK_FEED_SW4END0",
|
||||
"CLK_FEED_CK_BUFG_CASC12",
|
||||
"CLK_FEED_SE4BEG2",
|
||||
"CLK_FEED_NE2A3",
|
||||
"CLK_FEED_LH8",
|
||||
"CLK_FEED_R_CK_BUFG_CASC0",
|
||||
"CLK_FEED_WR1END1",
|
||||
"CLK_FEED_NE4BEG2",
|
||||
"CLK_FEED_R_CK_GCLK25",
|
||||
"CLK_FEED_WW4END2",
|
||||
"CLK_FEED_SW4A3",
|
||||
"CLK_FEED_LH11",
|
||||
"CLK_FEED_EE4C1",
|
||||
"CLK_FEED_R_CK_GCLK29",
|
||||
"CLK_FEED_R_CK_GCLK27",
|
||||
"CLK_FEED_NE4C0",
|
||||
"CLK_FEED_CK_GCLK24",
|
||||
"CLK_FEED_CK_GCLK14",
|
||||
"CLK_FEED_R_CK_BUFG_CASC9",
|
||||
"CLK_FEED_SE4C2",
|
||||
"CLK_FEED_R_CK_BUFG_CASC1",
|
||||
"CLK_FEED_ER1BEG1",
|
||||
"CLK_FEED_R_CK_GCLK6",
|
||||
"CLK_FEED_MONITOR_P",
|
||||
"CLK_FEED_CK_GCLK1",
|
||||
"CLK_FEED_R_CK_BUFG_CASC18",
|
||||
"CLK_FEED_R_CK_BUFG_CASC21",
|
||||
"CLK_FEED_WW4C3",
|
||||
"CLK_FEED_R_CK_GCLK21",
|
||||
"CLK_FEED_R_CK_GCLK24",
|
||||
"CLK_FEED_WW2END2",
|
||||
"CLK_FEED_SE2A1",
|
||||
"CLK_FEED_WW4A3",
|
||||
"CLK_FEED_CK_GCLK8",
|
||||
"CLK_FEED_CK_GCLK20",
|
||||
"CLK_FEED_CK_BUFG_CASC10",
|
||||
"CLK_FEED_CK_BUFG_CASC0",
|
||||
"CLK_FEED_EL1BEG1",
|
||||
"CLK_FEED_R_CK_GCLK12",
|
||||
"CLK_FEED_R_CK_GCLK8",
|
||||
"CLK_FEED_CK_GCLK6",
|
||||
"CLK_FEED_R_CK_BUFG_CASC27",
|
||||
"CLK_FEED_CK_BUFG_CASC21",
|
||||
"CLK_FEED_R_CK_BUFG_CASC26",
|
||||
"CLK_FEED_EE2BEG3",
|
||||
"CLK_FEED_LH7",
|
||||
"CLK_FEED_CK_BUFG_CASC9",
|
||||
"CLK_FEED_SW4A0",
|
||||
"CLK_FEED_LH9",
|
||||
"CLK_FEED_SW4A2",
|
||||
"CLK_FEED_CK_BUFG_CASC26",
|
||||
"CLK_FEED_R_CK_BUFG_CASC31",
|
||||
"CLK_FEED_R_CK_GCLK28",
|
||||
"CLK_FEED_MONITOR_N",
|
||||
"CLK_FEED_R_CK_BUFG_CASC28",
|
||||
"CLK_FEED_CK_GCLK21",
|
||||
"CLK_FEED_EE4B3",
|
||||
"CLK_FEED_NE2A1",
|
||||
"CLK_FEED_CK_GCLK25",
|
||||
"CLK_FEED_CK_BUFG_CASC23",
|
||||
"CLK_FEED_R_CK_BUFG_CASC7",
|
||||
"CLK_FEED_SW4END2",
|
||||
"CLK_FEED_EE2A1",
|
||||
"CLK_FEED_SE2A3",
|
||||
"CLK_FEED_SW2A0",
|
||||
"CLK_FEED_NE2A2",
|
||||
"CLK_FEED_R_CK_GCLK17",
|
||||
"CLK_FEED_CK_BUFG_CASC20",
|
||||
"CLK_FEED_WW4C2",
|
||||
"CLK_FEED_NE4BEG1",
|
||||
"CLK_FEED_CK_GCLK12",
|
||||
"CLK_FEED_R_CK_GCLK23",
|
||||
"CLK_FEED_NW2A1",
|
||||
"CLK_FEED_EE4B0",
|
||||
"CLK_FEED_NE4C2",
|
||||
"CLK_FEED_R_CK_GCLK15",
|
||||
"CLK_FEED_WW4B0",
|
||||
"CLK_FEED_CK_BUFG_CASC19",
|
||||
"CLK_FEED_R_CK_BUFG_CASC6",
|
||||
"CLK_FEED_R_CK_GCLK20",
|
||||
"CLK_FEED_R_CK_BUFG_CASC3",
|
||||
"CLK_FEED_WW2END1",
|
||||
"CLK_FEED_CK_BUFG_CASC25",
|
||||
"CLK_FEED_NW2A3",
|
||||
"CLK_FEED_R_CK_GCLK1",
|
||||
"CLK_FEED_WR1END0",
|
||||
"CLK_FEED_EE4A3",
|
||||
"CLK_FEED_R_CK_GCLK10",
|
||||
"CLK_FEED_R_CK_BUFG_CASC17",
|
||||
"CLK_FEED_NW2A2",
|
||||
"CLK_FEED_LH4",
|
||||
"CLK_FEED_EE2A0",
|
||||
"CLK_FEED_ER1BEG2",
|
||||
"CLK_FEED_ER1BEG3",
|
||||
"CLK_FEED_WW4A0",
|
||||
"CLK_FEED_CK_BUFG_CASC18",
|
||||
"CLK_FEED_WR1END3",
|
||||
"CLK_FEED_LH1",
|
||||
"CLK_FEED_EE2A3",
|
||||
"CLK_FEED_NW4A3",
|
||||
"CLK_FEED_WW2END3",
|
||||
"CLK_FEED_CK_BUFG_CASC27",
|
||||
"CLK_FEED_SE4C3",
|
||||
"CLK_FEED_NW4END2",
|
||||
"CLK_FEED_CK_BUFG_CASC1",
|
||||
"CLK_FEED_EE4C0",
|
||||
"CLK_FEED_CK_GCLK10",
|
||||
"CLK_FEED_R_CK_GCLK30",
|
||||
"CLK_FEED_WL1END3",
|
||||
"CLK_FEED_NW2A0",
|
||||
"CLK_FEED_NW4A0",
|
||||
"CLK_FEED_ER1BEG0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC23",
|
||||
"CLK_FEED_WW4A1",
|
||||
"CLK_FEED_CK_BUFG_CASC15",
|
||||
"CLK_FEED_LH2",
|
||||
"CLK_FEED_SW2A2",
|
||||
"CLK_FEED_R_CK_BUFG_CASC2",
|
||||
"CLK_FEED_CK_GCLK18",
|
||||
"CLK_FEED_CK_GCLK31",
|
||||
"CLK_FEED_R_CK_GCLK3",
|
||||
"CLK_FEED_LH6",
|
||||
"CLK_FEED_CK_GCLK4",
|
||||
"CLK_FEED_R_CK_GCLK2",
|
||||
"CLK_FEED_NW4END3",
|
||||
"CLK_FEED_NE4C1",
|
||||
"CLK_FEED_CK_BUFG_CASC31",
|
||||
"CLK_FEED_R_CK_GCLK7",
|
||||
"CLK_FEED_WW2A1",
|
||||
"CLK_FEED_R_CK_GCLK16",
|
||||
"CLK_FEED_SE4BEG0",
|
||||
"CLK_FEED_NW4END1",
|
||||
"CLK_FEED_WL1END2",
|
||||
"CLK_FEED_NW4END0",
|
||||
"CLK_FEED_SE2A0",
|
||||
"CLK_FEED_CK_GCLK5",
|
||||
"CLK_FEED_CK_BUFG_CASC4",
|
||||
"CLK_FEED_WR1END2",
|
||||
"CLK_FEED_SW4END3",
|
||||
"CLK_FEED_WW4END0",
|
||||
"CLK_FEED_EE4B1",
|
||||
"CLK_FEED_SW4A1",
|
||||
"CLK_FEED_CK_GCLK28",
|
||||
"CLK_FEED_NE4C3",
|
||||
"CLK_FEED_CK_BUFG_CASC17",
|
||||
"CLK_FEED_CK_GCLK23",
|
||||
"CLK_FEED_R_CK_GCLK18",
|
||||
"CLK_FEED_EE2A2",
|
||||
"CLK_FEED_R_CK_GCLK19",
|
||||
"CLK_FEED_CK_BUFG_CASC6",
|
||||
"CLK_FEED_CK_BUFG_CASC16",
|
||||
"CLK_FEED_R_CK_BUFG_CASC10",
|
||||
"CLK_FEED_R_CK_BUFG_CASC15",
|
||||
"CLK_FEED_R_CK_BUFG_CASC8",
|
||||
"CLK_FEED_NE2A0",
|
||||
"CLK_FEED_SE2A2",
|
||||
"CLK_FEED_R_CK_GCLK22",
|
||||
"CLK_FEED_SW2A3",
|
||||
"CLK_FEED_EE4A0",
|
||||
"CLK_FEED_CK_GCLK30",
|
||||
"CLK_FEED_EL1BEG3",
|
||||
"CLK_FEED_WW4C1",
|
||||
"CLK_FEED_R_CK_GCLK26",
|
||||
"CLK_FEED_CK_BUFG_CASC28",
|
||||
"CLK_FEED_EL1BEG0",
|
||||
"CLK_FEED_R_CK_GCLK31",
|
||||
"CLK_FEED_CK_BUFG_CASC24",
|
||||
"CLK_FEED_EE4C2",
|
||||
"CLK_FEED_R_CK_GCLK9",
|
||||
"CLK_FEED_R_CK_BUFG_CASC12",
|
||||
"CLK_FEED_WW4B3",
|
||||
"CLK_FEED_CK_BUFG_CASC30",
|
||||
"CLK_FEED_CK_BUFG_CASC14",
|
||||
"CLK_FEED_EL1BEG2",
|
||||
"CLK_FEED_CK_GCLK16",
|
||||
"CLK_FEED_CK_BUFG_CASC29",
|
||||
"CLK_FEED_R_CK_GCLK14",
|
||||
"CLK_FEED_WW4B1"
|
||||
],
|
||||
"tile_type": "CLK_FEED",
|
||||
"sites": []
|
||||
}
|
||||
"wires": [
|
||||
"CLK_FEED_NE2A0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC28",
|
||||
"CLK_FEED_CK_GCLK19",
|
||||
"CLK_FEED_ER1BEG3",
|
||||
"CLK_FEED_CK_BUFG_CASC29",
|
||||
"CLK_FEED_R_CK_GCLK18",
|
||||
"CLK_FEED_R_CK_GCLK6",
|
||||
"CLK_FEED_R_CK_GCLK31",
|
||||
"CLK_FEED_CK_BUFG_CASC1",
|
||||
"CLK_FEED_LH7",
|
||||
"CLK_FEED_CK_BUFG_CASC3",
|
||||
"CLK_FEED_WW4B2",
|
||||
"CLK_FEED_LH12",
|
||||
"CLK_FEED_R_CK_BUFG_CASC14",
|
||||
"CLK_FEED_EE4A3",
|
||||
"CLK_FEED_CK_BUFG_CASC13",
|
||||
"CLK_FEED_ER1BEG0",
|
||||
"CLK_FEED_SW4END3",
|
||||
"CLK_FEED_WL1END0",
|
||||
"CLK_FEED_SW2A0",
|
||||
"CLK_FEED_R_CK_GCLK13",
|
||||
"CLK_FEED_CK_BUFG_CASC26",
|
||||
"CLK_FEED_SE4BEG1",
|
||||
"CLK_FEED_CK_BUFG_CASC7",
|
||||
"CLK_FEED_CK_BUFG_CASC5",
|
||||
"CLK_FEED_CK_GCLK18",
|
||||
"CLK_FEED_WW4A3",
|
||||
"CLK_FEED_R_CK_BUFG_CASC10",
|
||||
"CLK_FEED_WW4C2",
|
||||
"CLK_FEED_NW4END3",
|
||||
"CLK_FEED_CK_GCLK27",
|
||||
"CLK_FEED_R_CK_GCLK3",
|
||||
"CLK_FEED_CK_BUFG_CASC21",
|
||||
"CLK_FEED_WW2END0",
|
||||
"CLK_FEED_WW2A1",
|
||||
"CLK_FEED_R_CK_BUFG_CASC22",
|
||||
"CLK_FEED_R_CK_BUFG_CASC0",
|
||||
"CLK_FEED_CK_GCLK12",
|
||||
"CLK_FEED_WW2A2",
|
||||
"CLK_FEED_CK_BUFG_CASC10",
|
||||
"CLK_FEED_EE4A2",
|
||||
"CLK_FEED_EE4B0",
|
||||
"CLK_FEED_CK_BUFG_CASC12",
|
||||
"CLK_FEED_R_CK_BUFG_CASC25",
|
||||
"CLK_FEED_EE4A1",
|
||||
"CLK_FEED_R_CK_BUFG_CASC17",
|
||||
"CLK_FEED_R_CK_BUFG_CASC30",
|
||||
"CLK_FEED_CK_GCLK15",
|
||||
"CLK_FEED_R_CK_BUFG_CASC26",
|
||||
"CLK_FEED_WW2END1",
|
||||
"CLK_FEED_ER1BEG1",
|
||||
"CLK_FEED_EL1BEG0",
|
||||
"CLK_FEED_NE4C3",
|
||||
"CLK_FEED_WW4C0",
|
||||
"CLK_FEED_CK_GCLK24",
|
||||
"CLK_FEED_NE2A2",
|
||||
"CLK_FEED_SE4BEG3",
|
||||
"CLK_FEED_CK_BUFG_CASC4",
|
||||
"CLK_FEED_CK_GCLK23",
|
||||
"CLK_FEED_CK_BUFG_CASC20",
|
||||
"CLK_FEED_R_CK_GCLK12",
|
||||
"CLK_FEED_R_CK_BUFG_CASC27",
|
||||
"CLK_FEED_SE4C3",
|
||||
"CLK_FEED_NW4A2",
|
||||
"CLK_FEED_CK_GCLK22",
|
||||
"CLK_FEED_R_CK_GCLK9",
|
||||
"CLK_FEED_CK_GCLK17",
|
||||
"CLK_FEED_CK_BUFG_CASC6",
|
||||
"CLK_FEED_MONITOR_P",
|
||||
"CLK_FEED_NW2A2",
|
||||
"CLK_FEED_EE4BEG1",
|
||||
"CLK_FEED_R_CK_GCLK14",
|
||||
"CLK_FEED_EE4C0",
|
||||
"CLK_FEED_EE4BEG3",
|
||||
"CLK_FEED_NE2A1",
|
||||
"CLK_FEED_WL1END3",
|
||||
"CLK_FEED_CK_GCLK28",
|
||||
"CLK_FEED_WW4B1",
|
||||
"CLK_FEED_WW4END1",
|
||||
"CLK_FEED_SW4END0",
|
||||
"CLK_FEED_R_CK_GCLK17",
|
||||
"CLK_FEED_R_CK_BUFG_CASC11",
|
||||
"CLK_FEED_WW4C1",
|
||||
"CLK_FEED_EL1BEG3",
|
||||
"CLK_FEED_SE2A3",
|
||||
"CLK_FEED_R_CK_GCLK22",
|
||||
"CLK_FEED_NE4C0",
|
||||
"CLK_FEED_WW2A3",
|
||||
"CLK_FEED_NW4END1",
|
||||
"CLK_FEED_SE2A2",
|
||||
"CLK_FEED_EE4B2",
|
||||
"CLK_FEED_R_CK_GCLK29",
|
||||
"CLK_FEED_WW2END3",
|
||||
"CLK_FEED_LH4",
|
||||
"CLK_FEED_WL1END2",
|
||||
"CLK_FEED_CK_GCLK2",
|
||||
"CLK_FEED_R_CK_GCLK25",
|
||||
"CLK_FEED_R_CK_BUFG_CASC13",
|
||||
"CLK_FEED_CK_BUFG_CASC27",
|
||||
"CLK_FEED_NW2A1",
|
||||
"CLK_FEED_SW4A3",
|
||||
"CLK_FEED_CK_BUFG_CASC31",
|
||||
"CLK_FEED_CK_GCLK1",
|
||||
"CLK_FEED_LH1",
|
||||
"CLK_FEED_CK_GCLK14",
|
||||
"CLK_FEED_R_CK_GCLK2",
|
||||
"CLK_FEED_R_CK_BUFG_CASC2",
|
||||
"CLK_FEED_WR1END0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC20",
|
||||
"CLK_FEED_NE4C1",
|
||||
"CLK_FEED_CK_GCLK16",
|
||||
"CLK_FEED_R_CK_GCLK5",
|
||||
"CLK_FEED_SE4C0",
|
||||
"CLK_FEED_EL1BEG1",
|
||||
"CLK_FEED_EL1BEG2",
|
||||
"CLK_FEED_EE4B1",
|
||||
"CLK_FEED_CK_BUFG_CASC22",
|
||||
"CLK_FEED_WR1END1",
|
||||
"CLK_FEED_NW4END0",
|
||||
"CLK_FEED_EE2BEG1",
|
||||
"CLK_FEED_R_CK_GCLK23",
|
||||
"CLK_FEED_R_CK_GCLK1",
|
||||
"CLK_FEED_LH2",
|
||||
"CLK_FEED_SW2A2",
|
||||
"CLK_FEED_ER1BEG2",
|
||||
"CLK_FEED_WL1END1",
|
||||
"CLK_FEED_NW4A1",
|
||||
"CLK_FEED_SW4A2",
|
||||
"CLK_FEED_CK_GCLK10",
|
||||
"CLK_FEED_CK_BUFG_CASC14",
|
||||
"CLK_FEED_CK_BUFG_CASC28",
|
||||
"CLK_FEED_CK_BUFG_CASC18",
|
||||
"CLK_FEED_R_CK_GCLK24",
|
||||
"CLK_FEED_EE2A1",
|
||||
"CLK_FEED_R_CK_BUFG_CASC15",
|
||||
"CLK_FEED_SW2A1",
|
||||
"CLK_FEED_CK_BUFG_CASC8",
|
||||
"CLK_FEED_CK_BUFG_CASC2",
|
||||
"CLK_FEED_R_CK_BUFG_CASC8",
|
||||
"CLK_FEED_R_CK_GCLK0",
|
||||
"CLK_FEED_WW4B3",
|
||||
"CLK_FEED_CK_GCLK3",
|
||||
"CLK_FEED_LH3",
|
||||
"CLK_FEED_SE2A0",
|
||||
"CLK_FEED_NE4C2",
|
||||
"CLK_FEED_WW4C3",
|
||||
"CLK_FEED_NW4A0",
|
||||
"CLK_FEED_EE4B3",
|
||||
"CLK_FEED_R_CK_GCLK20",
|
||||
"CLK_FEED_CK_BUFG_CASC25",
|
||||
"CLK_FEED_EE2A3",
|
||||
"CLK_FEED_R_CK_GCLK28",
|
||||
"CLK_FEED_LH11",
|
||||
"CLK_FEED_WW4B0",
|
||||
"CLK_FEED_CK_GCLK4",
|
||||
"CLK_FEED_CK_GCLK13",
|
||||
"CLK_FEED_WW2END2",
|
||||
"CLK_FEED_SW4END2",
|
||||
"CLK_FEED_NW2A0",
|
||||
"CLK_FEED_R_CK_GCLK30",
|
||||
"CLK_FEED_R_CK_BUFG_CASC1",
|
||||
"CLK_FEED_CK_GCLK25",
|
||||
"CLK_FEED_CK_BUFG_CASC19",
|
||||
"CLK_FEED_WW4A2",
|
||||
"CLK_FEED_R_CK_BUFG_CASC6",
|
||||
"CLK_FEED_R_CK_BUFG_CASC29",
|
||||
"CLK_FEED_SW4END1",
|
||||
"CLK_FEED_LH10",
|
||||
"CLK_FEED_CK_BUFG_CASC0",
|
||||
"CLK_FEED_NE4BEG3",
|
||||
"CLK_FEED_R_CK_GCLK26",
|
||||
"CLK_FEED_CK_GCLK7",
|
||||
"CLK_FEED_R_CK_BUFG_CASC16",
|
||||
"CLK_FEED_CK_BUFG_CASC23",
|
||||
"CLK_FEED_EE2BEG0",
|
||||
"CLK_FEED_CK_GCLK26",
|
||||
"CLK_FEED_CK_BUFG_CASC15",
|
||||
"CLK_FEED_SW4A1",
|
||||
"CLK_FEED_WW4A0",
|
||||
"CLK_FEED_CK_BUFG_CASC17",
|
||||
"CLK_FEED_NE2A3",
|
||||
"CLK_FEED_CK_GCLK21",
|
||||
"CLK_FEED_NE4BEG0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC23",
|
||||
"CLK_FEED_NE4BEG1",
|
||||
"CLK_FEED_WW4END0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC12",
|
||||
"CLK_FEED_SE4BEG2",
|
||||
"CLK_FEED_EE2BEG3",
|
||||
"CLK_FEED_R_CK_GCLK7",
|
||||
"CLK_FEED_R_CK_GCLK8",
|
||||
"CLK_FEED_CK_BUFG_CASC30",
|
||||
"CLK_FEED_WW4A1",
|
||||
"CLK_FEED_EE4BEG0",
|
||||
"CLK_FEED_WR1END2",
|
||||
"CLK_FEED_CK_BUFG_CASC24",
|
||||
"CLK_FEED_R_CK_GCLK16",
|
||||
"CLK_FEED_R_CK_GCLK10",
|
||||
"CLK_FEED_CK_BUFG_CASC16",
|
||||
"CLK_FEED_R_CK_BUFG_CASC5",
|
||||
"CLK_FEED_CK_GCLK5",
|
||||
"CLK_FEED_R_CK_BUFG_CASC18",
|
||||
"CLK_FEED_NE4BEG2",
|
||||
"CLK_FEED_R_CK_GCLK11",
|
||||
"CLK_FEED_R_CK_GCLK4",
|
||||
"CLK_FEED_R_CK_BUFG_CASC7",
|
||||
"CLK_FEED_SE4C1",
|
||||
"CLK_FEED_CK_GCLK20",
|
||||
"CLK_FEED_NW4END2",
|
||||
"CLK_FEED_EE4BEG2",
|
||||
"CLK_FEED_CK_GCLK30",
|
||||
"CLK_FEED_SE2A1",
|
||||
"CLK_FEED_CK_GCLK29",
|
||||
"CLK_FEED_R_CK_GCLK27",
|
||||
"CLK_FEED_LH6",
|
||||
"CLK_FEED_CK_GCLK9",
|
||||
"CLK_FEED_SW4A0",
|
||||
"CLK_FEED_EE4C1",
|
||||
"CLK_FEED_CK_BUFG_CASC11",
|
||||
"CLK_FEED_CK_GCLK8",
|
||||
"CLK_FEED_R_CK_BUFG_CASC9",
|
||||
"CLK_FEED_R_CK_BUFG_CASC3",
|
||||
"CLK_FEED_WW4END2",
|
||||
"CLK_FEED_CK_GCLK6",
|
||||
"CLK_FEED_EE2A2",
|
||||
"CLK_FEED_EE4C3",
|
||||
"CLK_FEED_NW2A3",
|
||||
"CLK_FEED_R_CK_BUFG_CASC24",
|
||||
"CLK_FEED_EE2A0",
|
||||
"CLK_FEED_R_CK_GCLK19",
|
||||
"CLK_FEED_EE2BEG2",
|
||||
"CLK_FEED_R_CK_BUFG_CASC19",
|
||||
"CLK_FEED_WW4END3",
|
||||
"CLK_FEED_CK_GCLK31",
|
||||
"CLK_FEED_SW2A3",
|
||||
"CLK_FEED_SE4C2",
|
||||
"CLK_FEED_EE4C2",
|
||||
"CLK_FEED_SE4BEG0",
|
||||
"CLK_FEED_LH9",
|
||||
"CLK_FEED_R_CK_GCLK15",
|
||||
"CLK_FEED_LH5",
|
||||
"CLK_FEED_NW4A3",
|
||||
"CLK_FEED_R_CK_BUFG_CASC4",
|
||||
"CLK_FEED_R_CK_BUFG_CASC21",
|
||||
"CLK_FEED_CK_GCLK0",
|
||||
"CLK_FEED_MONITOR_N",
|
||||
"CLK_FEED_CK_GCLK11",
|
||||
"CLK_FEED_R_CK_BUFG_CASC31",
|
||||
"CLK_FEED_R_CK_GCLK21",
|
||||
"CLK_FEED_WW2A0",
|
||||
"CLK_FEED_CK_BUFG_CASC9",
|
||||
"CLK_FEED_EE4A0",
|
||||
"CLK_FEED_WR1END3",
|
||||
"CLK_FEED_LH8"
|
||||
],
|
||||
"pips": {},
|
||||
"tile_type": "CLK_FEED",
|
||||
"sites": []
|
||||
}
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -1,365 +1,365 @@
|
|||
{
|
||||
"pips": {},
|
||||
"wires": [
|
||||
"CLK_FEED_CK_GCLK13",
|
||||
"CLK_FEED_CK_BUFG_CASC3",
|
||||
"CLK_FEED_WW4B2",
|
||||
"CLK_FEED_EE4B2",
|
||||
"CLK_FEED_CK_GCLK26",
|
||||
"CLK_FEED_WW2A0",
|
||||
"CLK_PMV_BYP3_0",
|
||||
"CLK_FEED_EE4A2",
|
||||
"CLK_FEED_R_CK_BUFG_CASC25",
|
||||
"CLK_PMV_FAN5_0",
|
||||
"CLK_FEED_R_CK_GCLK4",
|
||||
"CLK_FEED_R_CK_BUFG_CASC4",
|
||||
"CLK_PMV_LOGIC_OUTS18_0",
|
||||
"CLK_PMV_FAN1_0",
|
||||
"CLK_FEED_EE4BEG1",
|
||||
"CLK_FEED_CK_GCLK29",
|
||||
"CLK_PMV_IMUX46_0",
|
||||
"CLK_FEED_WW4C0",
|
||||
"CLK_FEED_EE4BEG2",
|
||||
"CLK_PMV_BYP0_0",
|
||||
"CLK_PMV_LOGIC_OUTS8_0",
|
||||
"CLK_FEED_CK_GCLK19",
|
||||
"CLK_FEED_CK_BUFG_CASC22",
|
||||
"CLK_PMV_IMUX44_0",
|
||||
"CLK_FEED_CK_BUFG_CASC5",
|
||||
"CLK_FEED_R_CK_BUFG_CASC29",
|
||||
"CLK_PMV_IMUX36_0",
|
||||
"CLK_FEED_SW4END1",
|
||||
"CLK_PMV_BYP5_0",
|
||||
"CLK_PMV_IMUX2_0",
|
||||
"CLK_FEED_LH12",
|
||||
"CLK_PMV_IMUX5_0",
|
||||
"CLK_FEED_CK_BUFG_CASC13",
|
||||
"CLK_FEED_CK_BUFG_CASC7",
|
||||
"CLK_FEED_WW4END3",
|
||||
"CLK_FEED_SE4C1",
|
||||
"CLK_FEED_CK_GCLK9",
|
||||
"CLK_PMV_LOGIC_OUTS17_0",
|
||||
"CLK_PMV_IMUX25_0",
|
||||
"CLK_FEED_EE4C3",
|
||||
"CLK_FEED_R_CK_BUFG_CASC22",
|
||||
"CLK_FEED_R_CK_BUFG_CASC19",
|
||||
"CLK_FEED_WW2END0",
|
||||
"CLK_FEED_CK_GCLK2",
|
||||
"CLK_FEED_R_CK_BUFG_CASC11",
|
||||
"CLK_FEED_R_CK_GCLK11",
|
||||
"CLK_FEED_CK_GCLK15",
|
||||
"CLK_PMV_LOGIC_OUTS5_0",
|
||||
"CLK_PMV_CTRL0_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC5",
|
||||
"CLK_FEED_R_CK_BUFG_CASC16",
|
||||
"CLK_PMV_FAN0_0",
|
||||
"CLK_PMV_IMUX43_0",
|
||||
"CLK_FEED_NE4BEG0",
|
||||
"CLK_FEED_SE4BEG3",
|
||||
"CLK_FEED_WW4A2",
|
||||
"CLK_FEED_SE4BEG1",
|
||||
"CLK_FEED_CK_GCLK0",
|
||||
"CLK_FEED_WW2A2",
|
||||
"CLK_FEED_R_CK_GCLK13",
|
||||
"CLK_FEED_R_CK_BUFG_CASC24",
|
||||
"CLK_PMV_IMUX17_0",
|
||||
"CLK_MTBF2_EN",
|
||||
"CLK_FEED_R_CK_BUFG_CASC13",
|
||||
"CLK_FEED_CK_GCLK17",
|
||||
"CLK_FEED_CK_BUFG_CASC11",
|
||||
"CLK_FEED_EE4BEG0",
|
||||
"CLK_PMV_IMUX13_0",
|
||||
"CLK_FEED_CK_GCLK11",
|
||||
"CLK_PMV_IMUX20_0",
|
||||
"CLK_FEED_CK_GCLK27",
|
||||
"CLK_FEED_CK_BUFG_CASC2",
|
||||
"CLK_FEED_CK_GCLK3",
|
||||
"CLK_FEED_R_CK_GCLK5",
|
||||
"CLK_FEED_R_CK_GCLK0",
|
||||
"CLK_FEED_LH10",
|
||||
"CLK_MTBF2_Q6B",
|
||||
"CLK_PMV_IMUX22_0",
|
||||
"CLK_FEED_SE4C0",
|
||||
"CLK_FEED_LH3",
|
||||
"CLK_PMV_LOGIC_OUTS10_0",
|
||||
"CLK_PMV_IMUX7_0",
|
||||
"CLK_PMV_IMUX31_0",
|
||||
"CLK_FEED_WW2A3",
|
||||
"CLK_FEED_NW4A1",
|
||||
"CLK_FEED_R_CK_BUFG_CASC14",
|
||||
"CLK_PMV_IMUX28_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC30",
|
||||
"CLK_FEED_LH5",
|
||||
"CLK_FEED_NW4A2",
|
||||
"CLK_PMV_BYP1_0",
|
||||
"CLK_FEED_WW4END1",
|
||||
"CLK_FEED_EE2BEG2",
|
||||
"CLK_FEED_WL1END0",
|
||||
"CLK_FEED_NE4BEG3",
|
||||
"CLK_PMV_IMUX42_0",
|
||||
"CLK_PMV_FAN3_0",
|
||||
"CLK_FEED_WL1END1",
|
||||
"CLK_FEED_SW2A1",
|
||||
"CLK_PMV_LOGIC_OUTS6_0",
|
||||
"CLK_FEED_EE2BEG0",
|
||||
"CLK_FEED_CK_GCLK7",
|
||||
"CLK_PMV_IMUX40_0",
|
||||
"CLK_FEED_CK_GCLK22",
|
||||
"CLK_FEED_EE4A1",
|
||||
"CLK_FEED_EE4BEG3",
|
||||
"CLK_FEED_R_CK_BUFG_CASC20",
|
||||
"CLK_FEED_CK_BUFG_CASC8",
|
||||
"CLK_FEED_EE2BEG1",
|
||||
"CLK_FEED_SW4END0",
|
||||
"CLK_FEED_CK_BUFG_CASC12",
|
||||
"CLK_FEED_SE4BEG2",
|
||||
"CLK_FEED_NE2A3",
|
||||
"CLK_MTBF2_Q5B",
|
||||
"CLK_FEED_LH8",
|
||||
"CLK_FEED_R_CK_BUFG_CASC0",
|
||||
"CLK_PMV_IMUX29_0",
|
||||
"CLK_PMV_LOGIC_OUTS13_0",
|
||||
"CLK_FEED_WR1END1",
|
||||
"CLK_FEED_NE4BEG2",
|
||||
"CLK_FEED_R_CK_GCLK25",
|
||||
"CLK_MTBF2_Q0B",
|
||||
"CLK_FEED_WW4END2",
|
||||
"CLK_FEED_SW4A3",
|
||||
"CLK_PMV_IMUX26_0",
|
||||
"CLK_FEED_LH11",
|
||||
"CLK_PMV_IMUX0_0",
|
||||
"CLK_PMV_IMUX11_0",
|
||||
"CLK_FEED_EE4C1",
|
||||
"CLK_PMV_LOGIC_OUTS16_0",
|
||||
"CLK_PMV_IMUX15_0",
|
||||
"CLK_FEED_R_CK_GCLK29",
|
||||
"CLK_FEED_R_CK_GCLK27",
|
||||
"CLK_FEED_NE4C0",
|
||||
"CLK_FEED_CK_GCLK24",
|
||||
"CLK_FEED_CK_GCLK14",
|
||||
"CLK_FEED_R_CK_BUFG_CASC9",
|
||||
"CLK_FEED_SE4C2",
|
||||
"CLK_PMV_LOGIC_OUTS4_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC1",
|
||||
"CLK_FEED_ER1BEG1",
|
||||
"CLK_PMV_IMUX41_0",
|
||||
"CLK_FEED_R_CK_GCLK6",
|
||||
"CLK_FEED_MONITOR_P",
|
||||
"CLK_FEED_CK_GCLK1",
|
||||
"CLK_FEED_R_CK_BUFG_CASC18",
|
||||
"CLK_PMV_IMUX45_0",
|
||||
"CLK_PMV_IMUX8_0",
|
||||
"CLK_FEED_WW4C3",
|
||||
"CLK_PMV_LOGIC_OUTS12_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC21",
|
||||
"CLK_FEED_R_CK_GCLK21",
|
||||
"CLK_FEED_R_CK_GCLK24",
|
||||
"CLK_FEED_WW2END2",
|
||||
"CLK_FEED_SE2A1",
|
||||
"CLK_FEED_WW4A3",
|
||||
"CLK_FEED_CK_GCLK8",
|
||||
"CLK_FEED_CK_GCLK20",
|
||||
"CLK_FEED_CK_BUFG_CASC10",
|
||||
"CLK_PMV_LOGIC_OUTS23_0",
|
||||
"CLK_FEED_CK_BUFG_CASC0",
|
||||
"CLK_FEED_EL1BEG1",
|
||||
"CLK_PMV_IMUX34_0",
|
||||
"CLK_FEED_R_CK_GCLK12",
|
||||
"CLK_FEED_CK_GCLK6",
|
||||
"CLK_FEED_R_CK_GCLK8",
|
||||
"CLK_FEED_R_CK_BUFG_CASC27",
|
||||
"CLK_FEED_CK_BUFG_CASC21",
|
||||
"CLK_FEED_R_CK_BUFG_CASC26",
|
||||
"CLK_FEED_EE2BEG3",
|
||||
"CLK_FEED_LH7",
|
||||
"CLK_FEED_SW4A0",
|
||||
"CLK_PMV_LOGIC_OUTS1_0",
|
||||
"CLK_FEED_CK_BUFG_CASC9",
|
||||
"CLK_PMV_FAN7_0",
|
||||
"CLK_PMV_LOGIC_OUTS20_0",
|
||||
"CLK_FEED_LH9",
|
||||
"CLK_MTBF2_Q4B",
|
||||
"CLK_FEED_SW4A2",
|
||||
"CLK_FEED_CK_BUFG_CASC26",
|
||||
"CLK_FEED_R_CK_BUFG_CASC31",
|
||||
"CLK_FEED_R_CK_GCLK28",
|
||||
"CLK_PMV_LOGIC_OUTS14_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC28",
|
||||
"CLK_FEED_CK_GCLK21",
|
||||
"CLK_FEED_MONITOR_N",
|
||||
"CLK_PMV_LOGIC_OUTS3_0",
|
||||
"CLK_FEED_EE4B3",
|
||||
"CLK_PMV_IMUX24_0",
|
||||
"CLK_PMV_LOGIC_OUTS15_0",
|
||||
"CLK_PMV_IMUX1_0",
|
||||
"CLK_FEED_NE2A1",
|
||||
"CLK_FEED_CK_GCLK25",
|
||||
"CLK_PMV_FAN2_0",
|
||||
"CLK_FEED_CK_BUFG_CASC23",
|
||||
"CLK_FEED_R_CK_BUFG_CASC7",
|
||||
"CLK_FEED_SW4END2",
|
||||
"CLK_PMV_CLK1_0",
|
||||
"CLK_PMV_BYP4_0",
|
||||
"CLK_PMV_IMUX32_0",
|
||||
"CLK_PMV_IMUX9_0",
|
||||
"CLK_FEED_EE2A1",
|
||||
"CLK_FEED_SE2A3",
|
||||
"CLK_FEED_SW2A0",
|
||||
"CLK_FEED_NE2A2",
|
||||
"CLK_FEED_R_CK_GCLK17",
|
||||
"CLK_FEED_CK_BUFG_CASC20",
|
||||
"CLK_FEED_WW4C2",
|
||||
"CLK_MTBF2_RESET",
|
||||
"CLK_FEED_NE4BEG1",
|
||||
"CLK_FEED_CK_GCLK12",
|
||||
"CLK_FEED_R_CK_GCLK23",
|
||||
"CLK_FEED_NW2A1",
|
||||
"CLK_FEED_EE4B0",
|
||||
"CLK_FEED_NE4C2",
|
||||
"CLK_PMV_IMUX10_0",
|
||||
"CLK_FEED_R_CK_GCLK15",
|
||||
"CLK_PMV_LOGIC_OUTS9_0",
|
||||
"CLK_FEED_WW4B0",
|
||||
"CLK_FEED_CK_BUFG_CASC19",
|
||||
"CLK_PMV_BYP2_0",
|
||||
"CLK_MTBF2_Q1B",
|
||||
"CLK_FEED_R_CK_BUFG_CASC6",
|
||||
"CLK_FEED_R_CK_GCLK20",
|
||||
"CLK_PMV_LOGIC_OUTS2_0",
|
||||
"CLK_FEED_WW2END1",
|
||||
"CLK_FEED_R_CK_BUFG_CASC3",
|
||||
"CLK_PMV_LOGIC_OUTS7_0",
|
||||
"CLK_FEED_CK_BUFG_CASC25",
|
||||
"CLK_PMV_FAN6_0",
|
||||
"CLK_PMV_IMUX37_0",
|
||||
"CLK_FEED_NW2A3",
|
||||
"CLK_FEED_R_CK_GCLK1",
|
||||
"CLK_FEED_WR1END0",
|
||||
"CLK_FEED_EE4A3",
|
||||
"CLK_FEED_R_CK_GCLK10",
|
||||
"CLK_FEED_R_CK_BUFG_CASC17",
|
||||
"CLK_FEED_NW2A2",
|
||||
"CLK_PMV_IMUX4_0",
|
||||
"CLK_FEED_LH4",
|
||||
"CLK_FEED_EE2A0",
|
||||
"CLK_PMV_IMUX35_0",
|
||||
"CLK_PMV_IMUX16_0",
|
||||
"CLK_FEED_ER1BEG2",
|
||||
"CLK_FEED_ER1BEG3",
|
||||
"CLK_FEED_WW4A0",
|
||||
"CLK_FEED_CK_BUFG_CASC18",
|
||||
"CLK_FEED_WR1END3",
|
||||
"CLK_FEED_LH1",
|
||||
"CLK_FEED_EE2A3",
|
||||
"CLK_FEED_NW4A3",
|
||||
"CLK_FEED_WW2END3",
|
||||
"CLK_FEED_CK_BUFG_CASC27",
|
||||
"CLK_FEED_SE4C3",
|
||||
"CLK_MTBF2_CLK",
|
||||
"CLK_PMV_IMUX23_0",
|
||||
"CLK_PMV_IMUX38_0",
|
||||
"CLK_PMV_IMUX12_0",
|
||||
"CLK_FEED_CK_BUFG_CASC1",
|
||||
"CLK_FEED_NW4END2",
|
||||
"CLK_FEED_EE4C0",
|
||||
"CLK_FEED_CK_GCLK10",
|
||||
"CLK_FEED_R_CK_GCLK30",
|
||||
"CLK_FEED_WL1END3",
|
||||
"CLK_FEED_NW2A0",
|
||||
"CLK_FEED_ER1BEG0",
|
||||
"CLK_FEED_NW4A0",
|
||||
"CLK_FEED_WW4A1",
|
||||
"CLK_FEED_R_CK_BUFG_CASC23",
|
||||
"CLK_FEED_CK_BUFG_CASC15",
|
||||
"CLK_FEED_LH2",
|
||||
"CLK_FEED_SW2A2",
|
||||
"CLK_MTBF2_Q3B",
|
||||
"CLK_PMV_BYP6_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC2",
|
||||
"CLK_PMV_IMUX3_0",
|
||||
"CLK_FEED_CK_GCLK31",
|
||||
"CLK_FEED_CK_GCLK18",
|
||||
"CLK_FEED_R_CK_GCLK3",
|
||||
"CLK_FEED_LH6",
|
||||
"CLK_FEED_CK_GCLK4",
|
||||
"CLK_FEED_R_CK_GCLK2",
|
||||
"CLK_PMV_IMUX21_0",
|
||||
"CLK_FEED_NW4END3",
|
||||
"CLK_FEED_NE4C1",
|
||||
"CLK_MTBF2_DIN",
|
||||
"CLK_FEED_CK_BUFG_CASC31",
|
||||
"CLK_FEED_R_CK_GCLK7",
|
||||
"CLK_FEED_WW2A1",
|
||||
"CLK_FEED_R_CK_GCLK16",
|
||||
"CLK_PMV_IMUX33_0",
|
||||
"CLK_PMV_IMUX18_0",
|
||||
"CLK_FEED_SE4BEG0",
|
||||
"CLK_FEED_WL1END2",
|
||||
"CLK_FEED_NW4END1",
|
||||
"CLK_FEED_NW4END0",
|
||||
"CLK_PMV_LOGIC_OUTS11_0",
|
||||
"CLK_FEED_SE2A0",
|
||||
"CLK_FEED_CK_GCLK5",
|
||||
"CLK_FEED_CK_BUFG_CASC4",
|
||||
"CLK_FEED_WR1END2",
|
||||
"CLK_FEED_SW4END3",
|
||||
"CLK_FEED_WW4END0",
|
||||
"CLK_PMV_CTRL1_0",
|
||||
"CLK_PMV_LOGIC_OUTS21_0",
|
||||
"CLK_FEED_EE4B1",
|
||||
"CLK_FEED_SW4A1",
|
||||
"CLK_FEED_CK_GCLK28",
|
||||
"CLK_FEED_NE4C3",
|
||||
"CLK_FEED_CK_BUFG_CASC17",
|
||||
"CLK_FEED_CK_GCLK23",
|
||||
"CLK_PMV_IMUX19_0",
|
||||
"CLK_FEED_R_CK_GCLK18",
|
||||
"CLK_FEED_EE2A2",
|
||||
"CLK_FEED_R_CK_GCLK19",
|
||||
"CLK_FEED_CK_BUFG_CASC6",
|
||||
"CLK_FEED_CK_BUFG_CASC16",
|
||||
"CLK_FEED_NE2A0",
|
||||
"CLK_MTBF2_Q2B",
|
||||
"CLK_FEED_R_CK_BUFG_CASC8",
|
||||
"CLK_PMV_LOGIC_OUTS0_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC15",
|
||||
"CLK_FEED_R_CK_BUFG_CASC10",
|
||||
"CLK_PMV_IMUX39_0",
|
||||
"CLK_PMV_IMUX6_0",
|
||||
"CLK_FEED_SE2A2",
|
||||
"CLK_FEED_R_CK_GCLK22",
|
||||
"CLK_FEED_SW2A3",
|
||||
"CLK_FEED_EE4A0",
|
||||
"CLK_FEED_CK_GCLK30",
|
||||
"CLK_PMV_CLK0_0",
|
||||
"CLK_FEED_EL1BEG3",
|
||||
"CLK_FEED_WW4C1",
|
||||
"CLK_PMV_FAN4_0",
|
||||
"CLK_FEED_R_CK_GCLK26",
|
||||
"CLK_PMV_LOGIC_OUTS22_0",
|
||||
"CLK_FEED_CK_BUFG_CASC28",
|
||||
"CLK_FEED_EL1BEG0",
|
||||
"CLK_PMV_LOGIC_OUTS19_0",
|
||||
"CLK_FEED_R_CK_GCLK31",
|
||||
"CLK_MTBF2_Q7B",
|
||||
"CLK_PMV_IMUX30_0",
|
||||
"CLK_PMV_IMUX27_0",
|
||||
"CLK_FEED_CK_BUFG_CASC24",
|
||||
"CLK_FEED_EE4C2",
|
||||
"CLK_PMV_IMUX47_0",
|
||||
"CLK_FEED_R_CK_GCLK9",
|
||||
"CLK_FEED_R_CK_BUFG_CASC12",
|
||||
"CLK_PMV_IMUX14_0",
|
||||
"CLK_FEED_WW4B3",
|
||||
"CLK_FEED_CK_BUFG_CASC30",
|
||||
"CLK_FEED_CK_BUFG_CASC14",
|
||||
"CLK_PMV_BYP7_0",
|
||||
"CLK_FEED_EL1BEG2",
|
||||
"CLK_FEED_CK_GCLK16",
|
||||
"CLK_FEED_CK_BUFG_CASC29",
|
||||
"CLK_FEED_R_CK_GCLK14",
|
||||
"CLK_FEED_WW4B1"
|
||||
],
|
||||
"tile_type": "CLK_MTBF2",
|
||||
"sites": []
|
||||
}
|
||||
"wires": [
|
||||
"CLK_FEED_NE2A0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC28",
|
||||
"CLK_FEED_CK_GCLK19",
|
||||
"CLK_FEED_ER1BEG3",
|
||||
"CLK_FEED_CK_BUFG_CASC29",
|
||||
"CLK_FEED_R_CK_GCLK18",
|
||||
"CLK_FEED_R_CK_GCLK31",
|
||||
"CLK_PMV_CLK1_0",
|
||||
"CLK_FEED_CK_BUFG_CASC1",
|
||||
"CLK_FEED_R_CK_GCLK6",
|
||||
"CLK_FEED_LH7",
|
||||
"CLK_FEED_CK_BUFG_CASC3",
|
||||
"CLK_FEED_WW4B2",
|
||||
"CLK_FEED_LH12",
|
||||
"CLK_FEED_R_CK_BUFG_CASC14",
|
||||
"CLK_FEED_EE4A3",
|
||||
"CLK_FEED_CK_BUFG_CASC13",
|
||||
"CLK_PMV_IMUX28_0",
|
||||
"CLK_PMV_IMUX24_0",
|
||||
"CLK_FEED_ER1BEG0",
|
||||
"CLK_PMV_IMUX44_0",
|
||||
"CLK_FEED_SW4END3",
|
||||
"CLK_FEED_WL1END0",
|
||||
"CLK_FEED_SW2A0",
|
||||
"CLK_PMV_IMUX15_0",
|
||||
"CLK_PMV_IMUX43_0",
|
||||
"CLK_PMV_FAN0_0",
|
||||
"CLK_FEED_R_CK_GCLK13",
|
||||
"CLK_PMV_FAN1_0",
|
||||
"CLK_FEED_CK_BUFG_CASC26",
|
||||
"CLK_FEED_SE4BEG1",
|
||||
"CLK_FEED_CK_BUFG_CASC7",
|
||||
"CLK_PMV_IMUX11_0",
|
||||
"CLK_PMV_LOGIC_OUTS12_0",
|
||||
"CLK_FEED_CK_BUFG_CASC5",
|
||||
"CLK_FEED_CK_GCLK18",
|
||||
"CLK_PMV_BYP0_0",
|
||||
"CLK_FEED_WW4A3",
|
||||
"CLK_FEED_R_CK_BUFG_CASC10",
|
||||
"CLK_FEED_WW4C2",
|
||||
"CLK_FEED_NW4END3",
|
||||
"CLK_FEED_CK_GCLK27",
|
||||
"CLK_PMV_IMUX33_0",
|
||||
"CLK_FEED_R_CK_GCLK3",
|
||||
"CLK_FEED_CK_BUFG_CASC21",
|
||||
"CLK_FEED_WW2END0",
|
||||
"CLK_FEED_WW2A1",
|
||||
"CLK_PMV_LOGIC_OUTS18_0",
|
||||
"CLK_PMV_IMUX26_0",
|
||||
"CLK_MTBF2_Q3B",
|
||||
"CLK_FEED_R_CK_BUFG_CASC22",
|
||||
"CLK_PMV_LOGIC_OUTS3_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC0",
|
||||
"CLK_FEED_EE4A2",
|
||||
"CLK_FEED_CK_GCLK12",
|
||||
"CLK_FEED_EE4B0",
|
||||
"CLK_FEED_WW2A2",
|
||||
"CLK_FEED_CK_BUFG_CASC10",
|
||||
"CLK_FEED_CK_BUFG_CASC12",
|
||||
"CLK_FEED_R_CK_BUFG_CASC25",
|
||||
"CLK_FEED_EE4A1",
|
||||
"CLK_PMV_LOGIC_OUTS23_0",
|
||||
"CLK_PMV_IMUX29_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC17",
|
||||
"CLK_PMV_LOGIC_OUTS5_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC30",
|
||||
"CLK_PMV_IMUX31_0",
|
||||
"CLK_FEED_CK_GCLK15",
|
||||
"CLK_FEED_R_CK_BUFG_CASC26",
|
||||
"CLK_FEED_WW2END1",
|
||||
"CLK_FEED_ER1BEG1",
|
||||
"CLK_FEED_EL1BEG0",
|
||||
"CLK_PMV_LOGIC_OUTS1_0",
|
||||
"CLK_PMV_LOGIC_OUTS21_0",
|
||||
"CLK_FEED_NE4C3",
|
||||
"CLK_FEED_WW4C0",
|
||||
"CLK_PMV_IMUX20_0",
|
||||
"CLK_PMV_BYP4_0",
|
||||
"CLK_FEED_CK_GCLK24",
|
||||
"CLK_FEED_NE2A2",
|
||||
"CLK_FEED_SE4BEG3",
|
||||
"CLK_PMV_LOGIC_OUTS16_0",
|
||||
"CLK_PMV_IMUX16_0",
|
||||
"CLK_FEED_CK_BUFG_CASC4",
|
||||
"CLK_PMV_IMUX9_0",
|
||||
"CLK_FEED_CK_GCLK23",
|
||||
"CLK_FEED_CK_BUFG_CASC20",
|
||||
"CLK_FEED_R_CK_GCLK12",
|
||||
"CLK_FEED_R_CK_BUFG_CASC27",
|
||||
"CLK_FEED_SE4C3",
|
||||
"CLK_FEED_CK_GCLK22",
|
||||
"CLK_FEED_NW4A2",
|
||||
"CLK_FEED_R_CK_GCLK9",
|
||||
"CLK_FEED_CK_GCLK17",
|
||||
"CLK_PMV_BYP7_0",
|
||||
"CLK_FEED_CK_BUFG_CASC6",
|
||||
"CLK_FEED_MONITOR_P",
|
||||
"CLK_FEED_NW2A2",
|
||||
"CLK_FEED_EE4BEG1",
|
||||
"CLK_FEED_R_CK_GCLK14",
|
||||
"CLK_FEED_EE4C0",
|
||||
"CLK_PMV_IMUX2_0",
|
||||
"CLK_FEED_EE4BEG3",
|
||||
"CLK_FEED_NE2A1",
|
||||
"CLK_FEED_WL1END3",
|
||||
"CLK_FEED_CK_GCLK28",
|
||||
"CLK_MTBF2_Q1B",
|
||||
"CLK_PMV_IMUX35_0",
|
||||
"CLK_PMV_LOGIC_OUTS7_0",
|
||||
"CLK_FEED_WW4B1",
|
||||
"CLK_FEED_SW4END0",
|
||||
"CLK_FEED_WW4END1",
|
||||
"CLK_FEED_R_CK_GCLK17",
|
||||
"CLK_FEED_R_CK_BUFG_CASC11",
|
||||
"CLK_MTBF2_Q0B",
|
||||
"CLK_FEED_WW4C1",
|
||||
"CLK_FEED_EL1BEG3",
|
||||
"CLK_MTBF2_DIN",
|
||||
"CLK_PMV_IMUX17_0",
|
||||
"CLK_FEED_SE2A3",
|
||||
"CLK_FEED_R_CK_GCLK22",
|
||||
"CLK_FEED_NE4C0",
|
||||
"CLK_FEED_WW2A3",
|
||||
"CLK_FEED_NW4END1",
|
||||
"CLK_MTBF2_Q4B",
|
||||
"CLK_PMV_IMUX8_0",
|
||||
"CLK_MTBF2_Q2B",
|
||||
"CLK_FEED_SE2A2",
|
||||
"CLK_FEED_EE4B2",
|
||||
"CLK_MTBF2_Q5B",
|
||||
"CLK_FEED_R_CK_GCLK29",
|
||||
"CLK_FEED_WW2END3",
|
||||
"CLK_FEED_LH4",
|
||||
"CLK_FEED_WL1END2",
|
||||
"CLK_FEED_CK_GCLK2",
|
||||
"CLK_FEED_R_CK_GCLK25",
|
||||
"CLK_PMV_FAN3_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC13",
|
||||
"CLK_FEED_CK_BUFG_CASC27",
|
||||
"CLK_FEED_NW2A1",
|
||||
"CLK_FEED_SW4A3",
|
||||
"CLK_FEED_CK_BUFG_CASC31",
|
||||
"CLK_PMV_BYP3_0",
|
||||
"CLK_FEED_CK_GCLK1",
|
||||
"CLK_FEED_LH1",
|
||||
"CLK_FEED_CK_GCLK14",
|
||||
"CLK_FEED_R_CK_GCLK2",
|
||||
"CLK_FEED_R_CK_BUFG_CASC2",
|
||||
"CLK_PMV_CLK0_0",
|
||||
"CLK_FEED_WR1END0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC20",
|
||||
"CLK_FEED_NE4C1",
|
||||
"CLK_FEED_CK_GCLK16",
|
||||
"CLK_PMV_FAN2_0",
|
||||
"CLK_FEED_R_CK_GCLK5",
|
||||
"CLK_FEED_SE4C0",
|
||||
"CLK_FEED_EL1BEG2",
|
||||
"CLK_FEED_EL1BEG1",
|
||||
"CLK_FEED_EE4B1",
|
||||
"CLK_FEED_CK_BUFG_CASC22",
|
||||
"CLK_PMV_IMUX40_0",
|
||||
"CLK_FEED_WR1END1",
|
||||
"CLK_FEED_NW4END0",
|
||||
"CLK_PMV_IMUX42_0",
|
||||
"CLK_FEED_EE2BEG1",
|
||||
"CLK_FEED_R_CK_GCLK23",
|
||||
"CLK_FEED_R_CK_GCLK1",
|
||||
"CLK_FEED_LH2",
|
||||
"CLK_FEED_SW2A2",
|
||||
"CLK_FEED_ER1BEG2",
|
||||
"CLK_FEED_WL1END1",
|
||||
"CLK_PMV_IMUX47_0",
|
||||
"CLK_FEED_NW4A1",
|
||||
"CLK_PMV_BYP1_0",
|
||||
"CLK_PMV_IMUX5_0",
|
||||
"CLK_FEED_SW4A2",
|
||||
"CLK_FEED_CK_GCLK10",
|
||||
"CLK_FEED_CK_BUFG_CASC14",
|
||||
"CLK_FEED_CK_BUFG_CASC28",
|
||||
"CLK_PMV_FAN7_0",
|
||||
"CLK_FEED_CK_BUFG_CASC18",
|
||||
"CLK_FEED_R_CK_GCLK24",
|
||||
"CLK_FEED_EE2A1",
|
||||
"CLK_FEED_R_CK_BUFG_CASC15",
|
||||
"CLK_PMV_LOGIC_OUTS10_0",
|
||||
"CLK_FEED_SW2A1",
|
||||
"CLK_FEED_CK_BUFG_CASC8",
|
||||
"CLK_PMV_IMUX45_0",
|
||||
"CLK_FEED_CK_BUFG_CASC2",
|
||||
"CLK_FEED_R_CK_BUFG_CASC8",
|
||||
"CLK_PMV_BYP2_0",
|
||||
"CLK_PMV_IMUX14_0",
|
||||
"CLK_FEED_R_CK_GCLK0",
|
||||
"CLK_FEED_WW4B3",
|
||||
"CLK_PMV_IMUX7_0",
|
||||
"CLK_MTBF2_RESET",
|
||||
"CLK_FEED_CK_GCLK3",
|
||||
"CLK_FEED_LH3",
|
||||
"CLK_PMV_IMUX6_0",
|
||||
"CLK_FEED_SE2A0",
|
||||
"CLK_FEED_NE4C2",
|
||||
"CLK_FEED_WW4C3",
|
||||
"CLK_PMV_IMUX38_0",
|
||||
"CLK_PMV_FAN6_0",
|
||||
"CLK_FEED_EE4B3",
|
||||
"CLK_FEED_NW4A0",
|
||||
"CLK_FEED_CK_BUFG_CASC25",
|
||||
"CLK_FEED_R_CK_GCLK20",
|
||||
"CLK_FEED_EE2A3",
|
||||
"CLK_FEED_R_CK_GCLK28",
|
||||
"CLK_FEED_LH11",
|
||||
"CLK_FEED_WW4B0",
|
||||
"CLK_PMV_IMUX30_0",
|
||||
"CLK_PMV_FAN4_0",
|
||||
"CLK_FEED_CK_GCLK4",
|
||||
"CLK_FEED_CK_GCLK13",
|
||||
"CLK_FEED_WW2END2",
|
||||
"CLK_FEED_SW4END2",
|
||||
"CLK_PMV_LOGIC_OUTS4_0",
|
||||
"CLK_PMV_LOGIC_OUTS6_0",
|
||||
"CLK_FEED_NW2A0",
|
||||
"CLK_FEED_R_CK_GCLK30",
|
||||
"CLK_FEED_R_CK_BUFG_CASC1",
|
||||
"CLK_FEED_CK_GCLK25",
|
||||
"CLK_PMV_IMUX1_0",
|
||||
"CLK_FEED_CK_BUFG_CASC19",
|
||||
"CLK_PMV_IMUX34_0",
|
||||
"CLK_FEED_WW4A2",
|
||||
"CLK_MTBF2_EN",
|
||||
"CLK_FEED_R_CK_BUFG_CASC6",
|
||||
"CLK_PMV_LOGIC_OUTS17_0",
|
||||
"CLK_PMV_LOGIC_OUTS9_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC29",
|
||||
"CLK_FEED_SW4END1",
|
||||
"CLK_FEED_LH10",
|
||||
"CLK_FEED_CK_BUFG_CASC0",
|
||||
"CLK_PMV_IMUX21_0",
|
||||
"CLK_FEED_NE4BEG3",
|
||||
"CLK_FEED_R_CK_GCLK26",
|
||||
"CLK_PMV_IMUX41_0",
|
||||
"CLK_PMV_IMUX46_0",
|
||||
"CLK_PMV_IMUX25_0",
|
||||
"CLK_PMV_IMUX39_0",
|
||||
"CLK_FEED_CK_GCLK7",
|
||||
"CLK_FEED_CK_BUFG_CASC23",
|
||||
"CLK_FEED_R_CK_BUFG_CASC16",
|
||||
"CLK_FEED_EE2BEG0",
|
||||
"CLK_FEED_CK_GCLK26",
|
||||
"CLK_FEED_CK_BUFG_CASC15",
|
||||
"CLK_FEED_SW4A1",
|
||||
"CLK_FEED_WW4A0",
|
||||
"CLK_PMV_IMUX22_0",
|
||||
"CLK_PMV_LOGIC_OUTS11_0",
|
||||
"CLK_PMV_BYP5_0",
|
||||
"CLK_PMV_LOGIC_OUTS15_0",
|
||||
"CLK_FEED_NE2A3",
|
||||
"CLK_FEED_CK_BUFG_CASC17",
|
||||
"CLK_FEED_CK_GCLK21",
|
||||
"CLK_MTBF2_CLK",
|
||||
"CLK_PMV_LOGIC_OUTS0_0",
|
||||
"CLK_FEED_NE4BEG0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC23",
|
||||
"CLK_FEED_NE4BEG1",
|
||||
"CLK_PMV_LOGIC_OUTS19_0",
|
||||
"CLK_FEED_WW4END0",
|
||||
"CLK_MTBF2_Q7B",
|
||||
"CLK_FEED_R_CK_BUFG_CASC12",
|
||||
"CLK_FEED_SE4BEG2",
|
||||
"CLK_FEED_EE2BEG3",
|
||||
"CLK_FEED_R_CK_GCLK7",
|
||||
"CLK_PMV_IMUX4_0",
|
||||
"CLK_FEED_CK_BUFG_CASC30",
|
||||
"CLK_FEED_R_CK_GCLK8",
|
||||
"CLK_FEED_WW4A1",
|
||||
"CLK_FEED_EE4BEG0",
|
||||
"CLK_FEED_WR1END2",
|
||||
"CLK_FEED_CK_BUFG_CASC24",
|
||||
"CLK_FEED_R_CK_GCLK16",
|
||||
"CLK_FEED_R_CK_GCLK10",
|
||||
"CLK_FEED_CK_BUFG_CASC16",
|
||||
"CLK_MTBF2_Q6B",
|
||||
"CLK_FEED_R_CK_BUFG_CASC5",
|
||||
"CLK_FEED_CK_GCLK5",
|
||||
"CLK_FEED_R_CK_BUFG_CASC18",
|
||||
"CLK_FEED_NE4BEG2",
|
||||
"CLK_PMV_LOGIC_OUTS20_0",
|
||||
"CLK_FEED_R_CK_GCLK4",
|
||||
"CLK_FEED_R_CK_GCLK11",
|
||||
"CLK_PMV_IMUX12_0",
|
||||
"CLK_PMV_IMUX37_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC7",
|
||||
"CLK_PMV_IMUX18_0",
|
||||
"CLK_FEED_SE4C1",
|
||||
"CLK_FEED_CK_GCLK20",
|
||||
"CLK_PMV_LOGIC_OUTS8_0",
|
||||
"CLK_FEED_NW4END2",
|
||||
"CLK_FEED_EE4BEG2",
|
||||
"CLK_FEED_CK_GCLK30",
|
||||
"CLK_FEED_SE2A1",
|
||||
"CLK_FEED_LH6",
|
||||
"CLK_FEED_CK_GCLK29",
|
||||
"CLK_FEED_R_CK_GCLK27",
|
||||
"CLK_FEED_EE4C1",
|
||||
"CLK_FEED_SW4A0",
|
||||
"CLK_FEED_CK_GCLK9",
|
||||
"CLK_FEED_CK_BUFG_CASC11",
|
||||
"CLK_FEED_CK_GCLK8",
|
||||
"CLK_FEED_R_CK_BUFG_CASC9",
|
||||
"CLK_FEED_R_CK_BUFG_CASC3",
|
||||
"CLK_FEED_WW4END2",
|
||||
"CLK_FEED_CK_GCLK6",
|
||||
"CLK_FEED_EE2A2",
|
||||
"CLK_PMV_LOGIC_OUTS14_0",
|
||||
"CLK_PMV_LOGIC_OUTS2_0",
|
||||
"CLK_FEED_EE4C3",
|
||||
"CLK_FEED_NW2A3",
|
||||
"CLK_PMV_CTRL0_0",
|
||||
"CLK_PMV_LOGIC_OUTS22_0",
|
||||
"CLK_PMV_IMUX0_0",
|
||||
"CLK_FEED_EE2A0",
|
||||
"CLK_PMV_FAN5_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC24",
|
||||
"CLK_PMV_BYP6_0",
|
||||
"CLK_FEED_R_CK_GCLK19",
|
||||
"CLK_FEED_EE2BEG2",
|
||||
"CLK_FEED_R_CK_BUFG_CASC19",
|
||||
"CLK_FEED_WW4END3",
|
||||
"CLK_FEED_CK_GCLK31",
|
||||
"CLK_FEED_SW2A3",
|
||||
"CLK_PMV_IMUX23_0",
|
||||
"CLK_PMV_IMUX19_0",
|
||||
"CLK_PMV_IMUX36_0",
|
||||
"CLK_FEED_SE4C2",
|
||||
"CLK_FEED_EE4C2",
|
||||
"CLK_PMV_IMUX13_0",
|
||||
"CLK_FEED_SE4BEG0",
|
||||
"CLK_PMV_IMUX27_0",
|
||||
"CLK_FEED_LH9",
|
||||
"CLK_FEED_R_CK_GCLK15",
|
||||
"CLK_PMV_IMUX3_0",
|
||||
"CLK_PMV_CTRL1_0",
|
||||
"CLK_FEED_LH5",
|
||||
"CLK_PMV_LOGIC_OUTS13_0",
|
||||
"CLK_FEED_NW4A3",
|
||||
"CLK_PMV_IMUX10_0",
|
||||
"CLK_PMV_IMUX32_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC4",
|
||||
"CLK_FEED_R_CK_BUFG_CASC21",
|
||||
"CLK_FEED_CK_GCLK0",
|
||||
"CLK_FEED_MONITOR_N",
|
||||
"CLK_FEED_CK_GCLK11",
|
||||
"CLK_FEED_R_CK_BUFG_CASC31",
|
||||
"CLK_FEED_WW2A0",
|
||||
"CLK_FEED_EE4A0",
|
||||
"CLK_FEED_CK_BUFG_CASC9",
|
||||
"CLK_FEED_R_CK_GCLK21",
|
||||
"CLK_FEED_WR1END3",
|
||||
"CLK_FEED_LH8"
|
||||
],
|
||||
"pips": {},
|
||||
"tile_type": "CLK_MTBF2",
|
||||
"sites": []
|
||||
}
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,377 +1,377 @@
|
|||
{
|
||||
"pips": {},
|
||||
"wires": [
|
||||
"CLK_FEED_CK_GCLK13",
|
||||
"CLK_FEED_CK_BUFG_CASC3",
|
||||
"CLK_FEED_WW4B2",
|
||||
"CLK_FEED_EE4B2",
|
||||
"CLK_FEED_CK_GCLK26",
|
||||
"CLK_FEED_WW2A0",
|
||||
"CLK_PMV_BYP3_0",
|
||||
"CLK_FEED_EE4A2",
|
||||
"CLK_FEED_R_CK_BUFG_CASC25",
|
||||
"CLK_PMV_FAN5_0",
|
||||
"CLK_FEED_R_CK_GCLK4",
|
||||
"CLK_FEED_R_CK_BUFG_CASC4",
|
||||
"CLK_PMV_LOGIC_OUTS18_0",
|
||||
"CLK_PMV_FAN1_0",
|
||||
"CLK_FEED_EE4BEG1",
|
||||
"CLK_FEED_CK_GCLK29",
|
||||
"CLK_PMV_IMUX46_0",
|
||||
"CLK_FEED_WW4C0",
|
||||
"CLK_FEED_EE4BEG2",
|
||||
"CLK_PMV_BYP0_0",
|
||||
"CLK_PMV_LOGIC_OUTS8_0",
|
||||
"CLK_FEED_CK_GCLK19",
|
||||
"CLK_FEED_CK_BUFG_CASC22",
|
||||
"CLK_PMV_IMUX44_0",
|
||||
"CLK_FEED_CK_BUFG_CASC5",
|
||||
"CLK_FEED_R_CK_BUFG_CASC29",
|
||||
"CLK_PMV_IMUX36_0",
|
||||
"CLK_FEED_SW4END1",
|
||||
"CLK_PMV_BYP5_0",
|
||||
"CLK_PMV_IMUX2_0",
|
||||
"CLK_FEED_LH12",
|
||||
"CLK_PMV_IMUX5_0",
|
||||
"CLK_FEED_CK_BUFG_CASC13",
|
||||
"CLK_FEED_CK_BUFG_CASC7",
|
||||
"CLK_FEED_WW4END3",
|
||||
"CLK_FEED_SE4C1",
|
||||
"CLK_FEED_CK_GCLK9",
|
||||
"CLK_PMV_LOGIC_OUTS17_0",
|
||||
"CLK_PMV_IMUX25_0",
|
||||
"CLK_FEED_EE4C3",
|
||||
"CLK_FEED_R_CK_BUFG_CASC22",
|
||||
"CLK_FEED_R_CK_GCLK14",
|
||||
"CLK_FEED_WW2END0",
|
||||
"CLK_FEED_CK_GCLK2",
|
||||
"CLK_FEED_R_CK_BUFG_CASC19",
|
||||
"CLK_FEED_R_CK_BUFG_CASC11",
|
||||
"CLK_FEED_R_CK_GCLK11",
|
||||
"CLK_FEED_CK_GCLK15",
|
||||
"CLK_PMV_LOGIC_OUTS5_0",
|
||||
"CLK_PMV_CTRL0_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC5",
|
||||
"CLK_FEED_R_CK_BUFG_CASC16",
|
||||
"CLK_PMV_FAN0_0",
|
||||
"CLK_PMV_IMUX43_0",
|
||||
"CLK_FEED_NE4BEG0",
|
||||
"CLK_FEED_SE4BEG3",
|
||||
"CLK_FEED_WW4A2",
|
||||
"CLK_FEED_SE4BEG1",
|
||||
"CLK_PMV2_A1",
|
||||
"CLK_FEED_CK_GCLK0",
|
||||
"CLK_FEED_WW2A2",
|
||||
"CLK_FEED_R_CK_GCLK13",
|
||||
"CLK_FEED_R_CK_BUFG_CASC24",
|
||||
"CLK_PMV_IMUX17_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC13",
|
||||
"CLK_FEED_CK_GCLK17",
|
||||
"CLK_FEED_CK_BUFG_CASC11",
|
||||
"CLK_FEED_EE4BEG0",
|
||||
"CLK_PMV_IMUX13_0",
|
||||
"CLK_FEED_CK_GCLK11",
|
||||
"CLK_PMV_IMUX20_0",
|
||||
"CLK_FEED_CK_GCLK27",
|
||||
"CLK_FEED_CK_BUFG_CASC2",
|
||||
"CLK_FEED_CK_GCLK3",
|
||||
"CLK_FEED_R_CK_GCLK5",
|
||||
"CLK_FEED_R_CK_GCLK0",
|
||||
"CLK_FEED_LH10",
|
||||
"CLK_PMV_IMUX22_0",
|
||||
"CLK_FEED_SE4C0",
|
||||
"CLK_PMV2_A0",
|
||||
"CLK_FEED_LH3",
|
||||
"CLK_PMV_LOGIC_OUTS10_0",
|
||||
"CLK_PMV_IMUX7_0",
|
||||
"CLK_PMV_IMUX31_0",
|
||||
"CLK_FEED_WW2A3",
|
||||
"CLK_FEED_NW4A1",
|
||||
"CLK_FEED_R_CK_BUFG_CASC14",
|
||||
"CLK_PMV_IMUX28_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC30",
|
||||
"CLK_FEED_LH5",
|
||||
"CLK_FEED_NW4A2",
|
||||
"CLK_PMV_BYP1_0",
|
||||
"CLK_FEED_WW4END1",
|
||||
"CLK_FEED_EE2BEG2",
|
||||
"CLK_FEED_WL1END0",
|
||||
"CLK_FEED_NE4BEG3",
|
||||
"CLK_PMV_IMUX42_0",
|
||||
"CLK_PMV_FAN3_0",
|
||||
"CLK_FEED_WL1END1",
|
||||
"CLK_FEED_SW2A1",
|
||||
"CLK_PMV_LOGIC_OUTS6_0",
|
||||
"CLK_FEED_EE2BEG0",
|
||||
"CLK_FEED_CK_GCLK7",
|
||||
"CLK_PMV_IMUX40_0",
|
||||
"CLK_FEED_CK_GCLK22",
|
||||
"CLK_FEED_EE4A1",
|
||||
"CLK_FEED_EE4BEG3",
|
||||
"CLK_FEED_R_CK_BUFG_CASC20",
|
||||
"CLK_FEED_CK_BUFG_CASC8",
|
||||
"CLK_FEED_EE2BEG1",
|
||||
"CLK_FEED_SW4END0",
|
||||
"CLK_FEED_CK_BUFG_CASC12",
|
||||
"CLK_FEED_SE4BEG2",
|
||||
"CLK_FEED_NE2A3",
|
||||
"CLK_FEED_LH8",
|
||||
"CLK_FEED_R_CK_BUFG_CASC0",
|
||||
"CLK_PMV_LOGIC_OUTS13_0",
|
||||
"CLK_PMV_IMUX29_0",
|
||||
"CLK_FEED_WR1END1",
|
||||
"CLK_FEED_NE4BEG2",
|
||||
"CLK_FEED_R_CK_GCLK25",
|
||||
"CLK_FEED_WW4END2",
|
||||
"CLK_FEED_SW4A3",
|
||||
"CLK_PMV_IMUX26_0",
|
||||
"CLK_FEED_LH11",
|
||||
"CLK_PMV_IMUX0_0",
|
||||
"CLK_PMV_IMUX11_0",
|
||||
"CLK_FEED_EE4C1",
|
||||
"CLK_PMV_LOGIC_OUTS16_0",
|
||||
"CLK_PMV_IMUX15_0",
|
||||
"CLK_FEED_R_CK_GCLK29",
|
||||
"CLK_FEED_R_CK_GCLK27",
|
||||
"CLK_FEED_NE4C0",
|
||||
"CLK_FEED_CK_GCLK24",
|
||||
"CLK_FEED_CK_GCLK14",
|
||||
"CLK_FEED_R_CK_BUFG_CASC9",
|
||||
"CLK_FEED_SE4C2",
|
||||
"CLK_PMV_LOGIC_OUTS4_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC1",
|
||||
"CLK_FEED_ER1BEG1",
|
||||
"CLK_PMV_IMUX41_0",
|
||||
"CLK_FEED_R_CK_GCLK6",
|
||||
"CLK_FEED_MONITOR_P",
|
||||
"CLK_FEED_CK_GCLK1",
|
||||
"CLK_FEED_R_CK_BUFG_CASC18",
|
||||
"CLK_PMV_IMUX45_0",
|
||||
"CLK_PMV_IMUX8_0",
|
||||
"CLK_FEED_WW4C3",
|
||||
"CLK_PMV_LOGIC_OUTS12_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC21",
|
||||
"CLK_FEED_R_CK_GCLK21",
|
||||
"CLK_FEED_R_CK_GCLK24",
|
||||
"CLK_FEED_WW2END2",
|
||||
"CLK_FEED_SE2A1",
|
||||
"CLK_FEED_WW4A3",
|
||||
"CLK_FEED_CK_GCLK8",
|
||||
"CLK_FEED_CK_GCLK20",
|
||||
"CLK_FEED_CK_BUFG_CASC10",
|
||||
"CLK_PMV_LOGIC_OUTS23_0",
|
||||
"CLK_FEED_CK_BUFG_CASC0",
|
||||
"CLK_FEED_EL1BEG1",
|
||||
"CLK_PMV_IMUX34_0",
|
||||
"CLK_FEED_R_CK_GCLK12",
|
||||
"CLK_FEED_CK_GCLK6",
|
||||
"CLK_FEED_R_CK_GCLK8",
|
||||
"CLK_FEED_R_CK_BUFG_CASC27",
|
||||
"CLK_FEED_CK_BUFG_CASC21",
|
||||
"CLK_FEED_R_CK_BUFG_CASC26",
|
||||
"CLK_FEED_EE2BEG3",
|
||||
"CLK_FEED_LH7",
|
||||
"CLK_FEED_SW4A0",
|
||||
"CLK_PMV_LOGIC_OUTS1_0",
|
||||
"CLK_FEED_CK_BUFG_CASC9",
|
||||
"CLK_PMV_FAN7_0",
|
||||
"CLK_PMV_LOGIC_OUTS20_0",
|
||||
"CLK_FEED_LH9",
|
||||
"CLK_FEED_SW4A2",
|
||||
"CLK_FEED_CK_BUFG_CASC26",
|
||||
"CLK_FEED_R_CK_BUFG_CASC31",
|
||||
"CLK_FEED_R_CK_GCLK28",
|
||||
"CLK_PMV_LOGIC_OUTS14_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC28",
|
||||
"CLK_FEED_CK_GCLK21",
|
||||
"CLK_FEED_MONITOR_N",
|
||||
"CLK_PMV_LOGIC_OUTS3_0",
|
||||
"CLK_FEED_EE4B3",
|
||||
"CLK_PMV_IMUX24_0",
|
||||
"CLK_PMV_LOGIC_OUTS15_0",
|
||||
"CLK_PMV_IMUX1_0",
|
||||
"CLK_FEED_NE2A1",
|
||||
"CLK_FEED_CK_GCLK25",
|
||||
"CLK_PMV_FAN2_0",
|
||||
"CLK_FEED_CK_BUFG_CASC23",
|
||||
"CLK_FEED_R_CK_BUFG_CASC7",
|
||||
"CLK_FEED_SW4END2",
|
||||
"CLK_PMV_BYP4_0",
|
||||
"CLK_PMV_CLK1_0",
|
||||
"CLK_PMV_IMUX32_0",
|
||||
"CLK_PMV_IMUX9_0",
|
||||
"CLK_FEED_EE2A1",
|
||||
"CLK_FEED_SE2A3",
|
||||
"CLK_FEED_SW2A0",
|
||||
"CLK_FEED_NE2A2",
|
||||
"CLK_FEED_R_CK_GCLK17",
|
||||
"CLK_FEED_CK_BUFG_CASC20",
|
||||
"CLK_FEED_WW4C2",
|
||||
"CLK_FEED_NE4BEG1",
|
||||
"CLK_FEED_CK_GCLK12",
|
||||
"CLK_FEED_R_CK_GCLK23",
|
||||
"CLK_FEED_NW2A1",
|
||||
"CLK_FEED_EE4B0",
|
||||
"CLK_FEED_NE4C2",
|
||||
"CLK_PMV_IMUX10_0",
|
||||
"CLK_FEED_R_CK_GCLK15",
|
||||
"CLK_PMV_LOGIC_OUTS9_0",
|
||||
"CLK_FEED_WW4B0",
|
||||
"CLK_FEED_CK_BUFG_CASC19",
|
||||
"CLK_PMV_BYP2_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC6",
|
||||
"CLK_FEED_R_CK_GCLK20",
|
||||
"CLK_PMV_LOGIC_OUTS2_0",
|
||||
"CLK_FEED_WW2END1",
|
||||
"CLK_FEED_R_CK_BUFG_CASC3",
|
||||
"CLK_PMV_LOGIC_OUTS7_0",
|
||||
"CLK_FEED_CK_BUFG_CASC25",
|
||||
"CLK_PMV_FAN6_0",
|
||||
"CLK_PMV_IMUX37_0",
|
||||
"CLK_FEED_NW2A3",
|
||||
"CLK_FEED_R_CK_GCLK1",
|
||||
"CLK_FEED_WR1END0",
|
||||
"CLK_FEED_EE4A3",
|
||||
"CLK_FEED_R_CK_GCLK10",
|
||||
"CLK_FEED_R_CK_BUFG_CASC17",
|
||||
"CLK_FEED_NW2A2",
|
||||
"CLK_PMV_IMUX4_0",
|
||||
"CLK_FEED_LH4",
|
||||
"CLK_FEED_EE2A0",
|
||||
"CLK_PMV_IMUX35_0",
|
||||
"CLK_PMV_IMUX16_0",
|
||||
"CLK_FEED_ER1BEG2",
|
||||
"CLK_PMV2_ODIV2",
|
||||
"CLK_FEED_ER1BEG3",
|
||||
"CLK_FEED_WW4A0",
|
||||
"CLK_FEED_CK_BUFG_CASC18",
|
||||
"CLK_FEED_WR1END3",
|
||||
"CLK_PMV2_A2",
|
||||
"CLK_FEED_LH1",
|
||||
"CLK_FEED_EE2A3",
|
||||
"CLK_FEED_NW4A3",
|
||||
"CLK_FEED_WW2END3",
|
||||
"CLK_FEED_CK_BUFG_CASC27",
|
||||
"CLK_FEED_SE4C3",
|
||||
"CLK_PMV_IMUX23_0",
|
||||
"CLK_PMV_IMUX38_0",
|
||||
"CLK_PMV_IMUX12_0",
|
||||
"CLK_FEED_CK_BUFG_CASC1",
|
||||
"CLK_FEED_NW4END2",
|
||||
"CLK_FEED_EE4C0",
|
||||
"CLK_FEED_CK_GCLK10",
|
||||
"CLK_FEED_R_CK_GCLK30",
|
||||
"CLK_FEED_WL1END3",
|
||||
"CLK_FEED_NW2A0",
|
||||
"CLK_FEED_ER1BEG0",
|
||||
"CLK_FEED_NW4A0",
|
||||
"CLK_FEED_WW4A1",
|
||||
"CLK_FEED_R_CK_BUFG_CASC23",
|
||||
"CLK_FEED_CK_BUFG_CASC15",
|
||||
"CLK_FEED_LH2",
|
||||
"CLK_FEED_SW2A2",
|
||||
"CLK_PMV_BYP6_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC2",
|
||||
"CLK_PMV_IMUX3_0",
|
||||
"CLK_FEED_CK_GCLK31",
|
||||
"CLK_FEED_CK_GCLK18",
|
||||
"CLK_FEED_R_CK_GCLK3",
|
||||
"CLK_FEED_LH6",
|
||||
"CLK_FEED_CK_GCLK4",
|
||||
"CLK_FEED_R_CK_GCLK2",
|
||||
"CLK_PMV_IMUX21_0",
|
||||
"CLK_FEED_NW4END3",
|
||||
"CLK_FEED_NE4C1",
|
||||
"CLK_FEED_CK_BUFG_CASC31",
|
||||
"CLK_FEED_R_CK_GCLK7",
|
||||
"CLK_FEED_WW2A1",
|
||||
"CLK_FEED_R_CK_GCLK16",
|
||||
"CLK_PMV_IMUX33_0",
|
||||
"CLK_PMV_IMUX18_0",
|
||||
"CLK_FEED_SE4BEG0",
|
||||
"CLK_FEED_WL1END2",
|
||||
"CLK_FEED_NW4END1",
|
||||
"CLK_FEED_NW4END0",
|
||||
"CLK_PMV_LOGIC_OUTS11_0",
|
||||
"CLK_FEED_SE2A0",
|
||||
"CLK_FEED_CK_GCLK5",
|
||||
"CLK_FEED_CK_BUFG_CASC4",
|
||||
"CLK_FEED_WR1END2",
|
||||
"CLK_FEED_SW4END3",
|
||||
"CLK_FEED_WW4END0",
|
||||
"CLK_PMV_CTRL1_0",
|
||||
"CLK_PMV_LOGIC_OUTS21_0",
|
||||
"CLK_FEED_EE4B1",
|
||||
"CLK_FEED_SW4A1",
|
||||
"CLK_FEED_CK_GCLK28",
|
||||
"CLK_FEED_NE4C3",
|
||||
"CLK_FEED_CK_BUFG_CASC17",
|
||||
"CLK_FEED_CK_GCLK23",
|
||||
"CLK_PMV_IMUX19_0",
|
||||
"CLK_FEED_R_CK_GCLK18",
|
||||
"CLK_FEED_EE2A2",
|
||||
"CLK_FEED_R_CK_GCLK19",
|
||||
"CLK_FEED_CK_BUFG_CASC6",
|
||||
"CLK_FEED_CK_BUFG_CASC16",
|
||||
"CLK_FEED_NE2A0",
|
||||
"CLK_PMV_LOGIC_OUTS0_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC15",
|
||||
"CLK_FEED_R_CK_BUFG_CASC10",
|
||||
"CLK_FEED_R_CK_BUFG_CASC8",
|
||||
"CLK_PMV_IMUX6_0",
|
||||
"CLK_PMV_IMUX39_0",
|
||||
"CLK_FEED_SE2A2",
|
||||
"CLK_FEED_R_CK_GCLK22",
|
||||
"CLK_FEED_SW2A3",
|
||||
"CLK_FEED_EE4A0",
|
||||
"CLK_FEED_CK_GCLK30",
|
||||
"CLK_PMV_CLK0_0",
|
||||
"CLK_FEED_EL1BEG3",
|
||||
"CLK_FEED_WW4C1",
|
||||
"CLK_PMV_FAN4_0",
|
||||
"CLK_FEED_R_CK_GCLK26",
|
||||
"CLK_PMV_LOGIC_OUTS22_0",
|
||||
"CLK_FEED_CK_BUFG_CASC28",
|
||||
"CLK_FEED_EL1BEG0",
|
||||
"CLK_PMV_LOGIC_OUTS19_0",
|
||||
"CLK_FEED_R_CK_GCLK31",
|
||||
"CLK_PMV_IMUX47_0",
|
||||
"CLK_PMV_IMUX30_0",
|
||||
"CLK_PMV_IMUX27_0",
|
||||
"CLK_FEED_CK_BUFG_CASC24",
|
||||
"CLK_FEED_EE4C2",
|
||||
"CLK_PMV2_ODIV4",
|
||||
"CLK_FEED_R_CK_GCLK9",
|
||||
"CLK_FEED_R_CK_BUFG_CASC12",
|
||||
"CLK_PMV_IMUX14_0",
|
||||
"CLK_FEED_WW4B3",
|
||||
"CLK_PMV2_O",
|
||||
"CLK_FEED_CK_BUFG_CASC30",
|
||||
"CLK_FEED_CK_BUFG_CASC14",
|
||||
"CLK_PMV_BYP7_0",
|
||||
"CLK_FEED_EL1BEG2",
|
||||
"CLK_FEED_CK_GCLK16",
|
||||
"CLK_FEED_CK_BUFG_CASC29",
|
||||
"CLK_PMV2_EN",
|
||||
"CLK_FEED_WW4B1"
|
||||
],
|
||||
"tile_type": "CLK_PMV2",
|
||||
"sites": [
|
||||
{
|
||||
"site_pins": {
|
||||
"ODIV4": "CLK_PMV2_ODIV4",
|
||||
"A2": "CLK_PMV2_A2",
|
||||
"A1": "CLK_PMV2_A1",
|
||||
"EN": "CLK_PMV2_EN",
|
||||
"ODIV2": "CLK_PMV2_ODIV2",
|
||||
"A0": "CLK_PMV2_A0",
|
||||
"O": "CLK_PMV2_O"
|
||||
},
|
||||
"type": "PMV2",
|
||||
"prefix": "PMV",
|
||||
"name": "X0Y0",
|
||||
"x_coord": 0,
|
||||
"y_coord": 0
|
||||
}
|
||||
]
|
||||
}
|
||||
"wires": [
|
||||
"CLK_FEED_NE2A0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC28",
|
||||
"CLK_FEED_CK_GCLK19",
|
||||
"CLK_FEED_ER1BEG3",
|
||||
"CLK_FEED_CK_BUFG_CASC29",
|
||||
"CLK_FEED_R_CK_GCLK18",
|
||||
"CLK_FEED_R_CK_GCLK31",
|
||||
"CLK_PMV_CLK1_0",
|
||||
"CLK_FEED_CK_BUFG_CASC1",
|
||||
"CLK_FEED_R_CK_GCLK6",
|
||||
"CLK_FEED_LH7",
|
||||
"CLK_FEED_CK_BUFG_CASC3",
|
||||
"CLK_FEED_WW4B2",
|
||||
"CLK_FEED_LH12",
|
||||
"CLK_FEED_R_CK_BUFG_CASC14",
|
||||
"CLK_FEED_EE4A3",
|
||||
"CLK_FEED_CK_BUFG_CASC13",
|
||||
"CLK_PMV_IMUX28_0",
|
||||
"CLK_PMV_IMUX24_0",
|
||||
"CLK_FEED_ER1BEG0",
|
||||
"CLK_PMV_IMUX44_0",
|
||||
"CLK_FEED_SW4END3",
|
||||
"CLK_FEED_WL1END0",
|
||||
"CLK_FEED_SW2A0",
|
||||
"CLK_PMV_IMUX15_0",
|
||||
"CLK_PMV_IMUX43_0",
|
||||
"CLK_PMV_FAN0_0",
|
||||
"CLK_FEED_R_CK_GCLK13",
|
||||
"CLK_PMV_FAN1_0",
|
||||
"CLK_FEED_CK_BUFG_CASC26",
|
||||
"CLK_FEED_SE4BEG1",
|
||||
"CLK_FEED_CK_BUFG_CASC7",
|
||||
"CLK_PMV_IMUX11_0",
|
||||
"CLK_PMV_LOGIC_OUTS12_0",
|
||||
"CLK_FEED_CK_BUFG_CASC5",
|
||||
"CLK_FEED_CK_GCLK18",
|
||||
"CLK_PMV_BYP0_0",
|
||||
"CLK_FEED_WW4A3",
|
||||
"CLK_FEED_R_CK_BUFG_CASC10",
|
||||
"CLK_FEED_WW4C2",
|
||||
"CLK_FEED_NW4END3",
|
||||
"CLK_FEED_CK_GCLK27",
|
||||
"CLK_PMV_IMUX33_0",
|
||||
"CLK_FEED_R_CK_GCLK3",
|
||||
"CLK_FEED_CK_BUFG_CASC21",
|
||||
"CLK_FEED_WW2END0",
|
||||
"CLK_FEED_WW2A1",
|
||||
"CLK_PMV_LOGIC_OUTS18_0",
|
||||
"CLK_PMV_IMUX26_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC22",
|
||||
"CLK_PMV2_EN",
|
||||
"CLK_PMV_LOGIC_OUTS3_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC0",
|
||||
"CLK_FEED_CK_GCLK12",
|
||||
"CLK_FEED_EE4A2",
|
||||
"CLK_FEED_EE4B0",
|
||||
"CLK_FEED_WW2A2",
|
||||
"CLK_FEED_CK_BUFG_CASC10",
|
||||
"CLK_FEED_CK_BUFG_CASC12",
|
||||
"CLK_FEED_R_CK_BUFG_CASC25",
|
||||
"CLK_FEED_EE4A1",
|
||||
"CLK_PMV_LOGIC_OUTS23_0",
|
||||
"CLK_PMV_IMUX29_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC17",
|
||||
"CLK_PMV_LOGIC_OUTS5_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC30",
|
||||
"CLK_PMV_IMUX31_0",
|
||||
"CLK_FEED_CK_GCLK15",
|
||||
"CLK_FEED_R_CK_BUFG_CASC26",
|
||||
"CLK_FEED_WW2END1",
|
||||
"CLK_PMV2_ODIV2",
|
||||
"CLK_FEED_ER1BEG1",
|
||||
"CLK_FEED_EL1BEG0",
|
||||
"CLK_PMV_LOGIC_OUTS1_0",
|
||||
"CLK_PMV_LOGIC_OUTS21_0",
|
||||
"CLK_FEED_NE4C3",
|
||||
"CLK_FEED_WW4C0",
|
||||
"CLK_PMV_IMUX20_0",
|
||||
"CLK_PMV_BYP4_0",
|
||||
"CLK_FEED_CK_GCLK24",
|
||||
"CLK_FEED_NE2A2",
|
||||
"CLK_FEED_SE4BEG3",
|
||||
"CLK_PMV_LOGIC_OUTS16_0",
|
||||
"CLK_PMV_IMUX16_0",
|
||||
"CLK_FEED_CK_BUFG_CASC4",
|
||||
"CLK_PMV_IMUX9_0",
|
||||
"CLK_FEED_CK_GCLK23",
|
||||
"CLK_FEED_CK_BUFG_CASC20",
|
||||
"CLK_FEED_R_CK_GCLK12",
|
||||
"CLK_FEED_R_CK_BUFG_CASC27",
|
||||
"CLK_FEED_SE4C3",
|
||||
"CLK_FEED_CK_GCLK22",
|
||||
"CLK_FEED_NW4A2",
|
||||
"CLK_FEED_R_CK_GCLK9",
|
||||
"CLK_FEED_CK_GCLK17",
|
||||
"CLK_PMV_BYP7_0",
|
||||
"CLK_FEED_CK_BUFG_CASC6",
|
||||
"CLK_FEED_MONITOR_P",
|
||||
"CLK_FEED_NW2A2",
|
||||
"CLK_FEED_EE4BEG1",
|
||||
"CLK_FEED_R_CK_GCLK14",
|
||||
"CLK_FEED_EE4C0",
|
||||
"CLK_PMV_IMUX2_0",
|
||||
"CLK_FEED_EE4BEG3",
|
||||
"CLK_FEED_NE2A1",
|
||||
"CLK_FEED_WL1END3",
|
||||
"CLK_FEED_CK_GCLK28",
|
||||
"CLK_PMV_IMUX35_0",
|
||||
"CLK_PMV_LOGIC_OUTS7_0",
|
||||
"CLK_FEED_WW4B1",
|
||||
"CLK_FEED_SW4END0",
|
||||
"CLK_FEED_WW4END1",
|
||||
"CLK_FEED_R_CK_GCLK17",
|
||||
"CLK_FEED_R_CK_BUFG_CASC11",
|
||||
"CLK_FEED_WW4C1",
|
||||
"CLK_FEED_EL1BEG3",
|
||||
"CLK_PMV_IMUX17_0",
|
||||
"CLK_FEED_SE2A3",
|
||||
"CLK_FEED_R_CK_GCLK22",
|
||||
"CLK_FEED_NE4C0",
|
||||
"CLK_FEED_WW2A3",
|
||||
"CLK_FEED_NW4END1",
|
||||
"CLK_PMV_IMUX8_0",
|
||||
"CLK_FEED_SE2A2",
|
||||
"CLK_FEED_EE4B2",
|
||||
"CLK_FEED_R_CK_GCLK29",
|
||||
"CLK_FEED_WW2END3",
|
||||
"CLK_FEED_LH4",
|
||||
"CLK_FEED_WL1END2",
|
||||
"CLK_FEED_CK_GCLK2",
|
||||
"CLK_FEED_R_CK_GCLK25",
|
||||
"CLK_PMV_FAN3_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC13",
|
||||
"CLK_FEED_CK_BUFG_CASC27",
|
||||
"CLK_FEED_NW2A1",
|
||||
"CLK_FEED_SW4A3",
|
||||
"CLK_FEED_CK_BUFG_CASC31",
|
||||
"CLK_PMV_BYP3_0",
|
||||
"CLK_FEED_CK_GCLK1",
|
||||
"CLK_FEED_LH1",
|
||||
"CLK_FEED_CK_GCLK14",
|
||||
"CLK_FEED_R_CK_GCLK2",
|
||||
"CLK_FEED_R_CK_BUFG_CASC2",
|
||||
"CLK_PMV_CLK0_0",
|
||||
"CLK_FEED_WR1END0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC20",
|
||||
"CLK_FEED_NE4C1",
|
||||
"CLK_FEED_CK_GCLK16",
|
||||
"CLK_PMV_FAN2_0",
|
||||
"CLK_FEED_R_CK_GCLK5",
|
||||
"CLK_FEED_SE4C0",
|
||||
"CLK_FEED_EL1BEG2",
|
||||
"CLK_FEED_EL1BEG1",
|
||||
"CLK_FEED_EE4B1",
|
||||
"CLK_PMV2_A0",
|
||||
"CLK_FEED_CK_BUFG_CASC22",
|
||||
"CLK_PMV_IMUX40_0",
|
||||
"CLK_FEED_WR1END1",
|
||||
"CLK_FEED_NW4END0",
|
||||
"CLK_PMV_IMUX42_0",
|
||||
"CLK_FEED_EE2BEG1",
|
||||
"CLK_FEED_R_CK_GCLK23",
|
||||
"CLK_PMV2_A2",
|
||||
"CLK_FEED_R_CK_GCLK1",
|
||||
"CLK_FEED_LH2",
|
||||
"CLK_FEED_SW2A2",
|
||||
"CLK_FEED_ER1BEG2",
|
||||
"CLK_FEED_WL1END1",
|
||||
"CLK_PMV_IMUX47_0",
|
||||
"CLK_FEED_NW4A1",
|
||||
"CLK_PMV_BYP1_0",
|
||||
"CLK_PMV_IMUX5_0",
|
||||
"CLK_FEED_SW4A2",
|
||||
"CLK_FEED_CK_GCLK10",
|
||||
"CLK_FEED_CK_BUFG_CASC14",
|
||||
"CLK_FEED_CK_BUFG_CASC28",
|
||||
"CLK_PMV_FAN7_0",
|
||||
"CLK_FEED_CK_BUFG_CASC18",
|
||||
"CLK_FEED_R_CK_GCLK24",
|
||||
"CLK_FEED_EE2A1",
|
||||
"CLK_FEED_R_CK_BUFG_CASC15",
|
||||
"CLK_PMV_LOGIC_OUTS10_0",
|
||||
"CLK_FEED_SW2A1",
|
||||
"CLK_FEED_CK_BUFG_CASC8",
|
||||
"CLK_PMV_IMUX45_0",
|
||||
"CLK_FEED_CK_BUFG_CASC2",
|
||||
"CLK_FEED_R_CK_BUFG_CASC8",
|
||||
"CLK_PMV_BYP2_0",
|
||||
"CLK_PMV_IMUX14_0",
|
||||
"CLK_FEED_R_CK_GCLK0",
|
||||
"CLK_FEED_WW4B3",
|
||||
"CLK_PMV_IMUX7_0",
|
||||
"CLK_FEED_CK_GCLK3",
|
||||
"CLK_FEED_LH3",
|
||||
"CLK_PMV_IMUX6_0",
|
||||
"CLK_FEED_SE2A0",
|
||||
"CLK_FEED_NE4C2",
|
||||
"CLK_FEED_WW4C3",
|
||||
"CLK_PMV_IMUX38_0",
|
||||
"CLK_PMV_FAN6_0",
|
||||
"CLK_FEED_EE4B3",
|
||||
"CLK_PMV2_ODIV4",
|
||||
"CLK_FEED_NW4A0",
|
||||
"CLK_FEED_CK_BUFG_CASC25",
|
||||
"CLK_FEED_R_CK_GCLK20",
|
||||
"CLK_FEED_EE2A3",
|
||||
"CLK_FEED_R_CK_GCLK28",
|
||||
"CLK_FEED_LH11",
|
||||
"CLK_FEED_WW4B0",
|
||||
"CLK_PMV_IMUX30_0",
|
||||
"CLK_PMV_FAN4_0",
|
||||
"CLK_FEED_CK_GCLK4",
|
||||
"CLK_FEED_CK_GCLK13",
|
||||
"CLK_FEED_WW2END2",
|
||||
"CLK_FEED_SW4END2",
|
||||
"CLK_PMV_LOGIC_OUTS4_0",
|
||||
"CLK_PMV_LOGIC_OUTS6_0",
|
||||
"CLK_FEED_NW2A0",
|
||||
"CLK_FEED_R_CK_GCLK30",
|
||||
"CLK_FEED_R_CK_BUFG_CASC1",
|
||||
"CLK_FEED_CK_GCLK25",
|
||||
"CLK_PMV_IMUX1_0",
|
||||
"CLK_FEED_CK_BUFG_CASC19",
|
||||
"CLK_PMV_IMUX34_0",
|
||||
"CLK_FEED_WW4A2",
|
||||
"CLK_FEED_R_CK_BUFG_CASC6",
|
||||
"CLK_PMV_LOGIC_OUTS17_0",
|
||||
"CLK_PMV_LOGIC_OUTS9_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC29",
|
||||
"CLK_FEED_SW4END1",
|
||||
"CLK_FEED_LH10",
|
||||
"CLK_FEED_CK_BUFG_CASC0",
|
||||
"CLK_PMV_IMUX21_0",
|
||||
"CLK_FEED_NE4BEG3",
|
||||
"CLK_FEED_R_CK_GCLK26",
|
||||
"CLK_PMV_IMUX41_0",
|
||||
"CLK_PMV_IMUX46_0",
|
||||
"CLK_PMV_IMUX25_0",
|
||||
"CLK_PMV_IMUX39_0",
|
||||
"CLK_FEED_CK_GCLK7",
|
||||
"CLK_FEED_CK_BUFG_CASC23",
|
||||
"CLK_FEED_R_CK_BUFG_CASC16",
|
||||
"CLK_FEED_EE2BEG0",
|
||||
"CLK_FEED_CK_GCLK26",
|
||||
"CLK_FEED_CK_BUFG_CASC15",
|
||||
"CLK_FEED_SW4A1",
|
||||
"CLK_FEED_WW4A0",
|
||||
"CLK_PMV_IMUX22_0",
|
||||
"CLK_PMV_LOGIC_OUTS11_0",
|
||||
"CLK_PMV_BYP5_0",
|
||||
"CLK_PMV_LOGIC_OUTS15_0",
|
||||
"CLK_FEED_NE2A3",
|
||||
"CLK_FEED_CK_BUFG_CASC17",
|
||||
"CLK_FEED_CK_GCLK21",
|
||||
"CLK_PMV_LOGIC_OUTS0_0",
|
||||
"CLK_FEED_NE4BEG0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC23",
|
||||
"CLK_FEED_NE4BEG1",
|
||||
"CLK_PMV_LOGIC_OUTS19_0",
|
||||
"CLK_FEED_WW4END0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC12",
|
||||
"CLK_FEED_SE4BEG2",
|
||||
"CLK_FEED_EE2BEG3",
|
||||
"CLK_FEED_R_CK_GCLK7",
|
||||
"CLK_PMV_IMUX4_0",
|
||||
"CLK_FEED_CK_BUFG_CASC30",
|
||||
"CLK_PMV2_A1",
|
||||
"CLK_FEED_R_CK_GCLK8",
|
||||
"CLK_FEED_WW4A1",
|
||||
"CLK_FEED_EE4BEG0",
|
||||
"CLK_FEED_WR1END2",
|
||||
"CLK_FEED_CK_BUFG_CASC24",
|
||||
"CLK_FEED_R_CK_GCLK16",
|
||||
"CLK_FEED_R_CK_GCLK10",
|
||||
"CLK_FEED_CK_BUFG_CASC16",
|
||||
"CLK_FEED_R_CK_BUFG_CASC5",
|
||||
"CLK_FEED_CK_GCLK5",
|
||||
"CLK_FEED_R_CK_BUFG_CASC18",
|
||||
"CLK_FEED_NE4BEG2",
|
||||
"CLK_FEED_R_CK_GCLK11",
|
||||
"CLK_PMV_LOGIC_OUTS20_0",
|
||||
"CLK_FEED_R_CK_GCLK4",
|
||||
"CLK_PMV_IMUX12_0",
|
||||
"CLK_PMV_IMUX37_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC7",
|
||||
"CLK_PMV_IMUX18_0",
|
||||
"CLK_FEED_SE4C1",
|
||||
"CLK_FEED_CK_GCLK20",
|
||||
"CLK_PMV_LOGIC_OUTS8_0",
|
||||
"CLK_FEED_NW4END2",
|
||||
"CLK_FEED_EE4BEG2",
|
||||
"CLK_FEED_CK_GCLK30",
|
||||
"CLK_FEED_SE2A1",
|
||||
"CLK_FEED_LH6",
|
||||
"CLK_FEED_CK_GCLK29",
|
||||
"CLK_FEED_R_CK_GCLK27",
|
||||
"CLK_FEED_EE4C1",
|
||||
"CLK_FEED_SW4A0",
|
||||
"CLK_FEED_CK_GCLK9",
|
||||
"CLK_FEED_CK_BUFG_CASC11",
|
||||
"CLK_FEED_CK_GCLK8",
|
||||
"CLK_FEED_R_CK_BUFG_CASC9",
|
||||
"CLK_FEED_R_CK_BUFG_CASC3",
|
||||
"CLK_FEED_WW4END2",
|
||||
"CLK_FEED_CK_GCLK6",
|
||||
"CLK_FEED_EE2A2",
|
||||
"CLK_PMV_LOGIC_OUTS2_0",
|
||||
"CLK_PMV_LOGIC_OUTS14_0",
|
||||
"CLK_FEED_EE4C3",
|
||||
"CLK_FEED_NW2A3",
|
||||
"CLK_PMV_CTRL0_0",
|
||||
"CLK_PMV_LOGIC_OUTS22_0",
|
||||
"CLK_PMV_IMUX0_0",
|
||||
"CLK_FEED_EE2A0",
|
||||
"CLK_PMV_FAN5_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC24",
|
||||
"CLK_PMV_BYP6_0",
|
||||
"CLK_FEED_R_CK_GCLK19",
|
||||
"CLK_FEED_EE2BEG2",
|
||||
"CLK_FEED_R_CK_BUFG_CASC19",
|
||||
"CLK_FEED_WW4END3",
|
||||
"CLK_FEED_CK_GCLK31",
|
||||
"CLK_FEED_SW2A3",
|
||||
"CLK_PMV_IMUX23_0",
|
||||
"CLK_PMV_IMUX19_0",
|
||||
"CLK_PMV_IMUX36_0",
|
||||
"CLK_FEED_SE4C2",
|
||||
"CLK_FEED_EE4C2",
|
||||
"CLK_PMV_IMUX13_0",
|
||||
"CLK_FEED_SE4BEG0",
|
||||
"CLK_PMV_IMUX27_0",
|
||||
"CLK_FEED_LH9",
|
||||
"CLK_PMV2_O",
|
||||
"CLK_FEED_R_CK_GCLK15",
|
||||
"CLK_PMV_IMUX3_0",
|
||||
"CLK_PMV_CTRL1_0",
|
||||
"CLK_FEED_LH5",
|
||||
"CLK_PMV_LOGIC_OUTS13_0",
|
||||
"CLK_FEED_NW4A3",
|
||||
"CLK_PMV_IMUX10_0",
|
||||
"CLK_PMV_IMUX32_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC4",
|
||||
"CLK_FEED_R_CK_BUFG_CASC21",
|
||||
"CLK_FEED_CK_GCLK0",
|
||||
"CLK_FEED_MONITOR_N",
|
||||
"CLK_FEED_CK_GCLK11",
|
||||
"CLK_FEED_R_CK_BUFG_CASC31",
|
||||
"CLK_FEED_WW2A0",
|
||||
"CLK_FEED_EE4A0",
|
||||
"CLK_FEED_CK_BUFG_CASC9",
|
||||
"CLK_FEED_R_CK_GCLK21",
|
||||
"CLK_FEED_WR1END3",
|
||||
"CLK_FEED_LH8"
|
||||
],
|
||||
"pips": {},
|
||||
"tile_type": "CLK_PMV2",
|
||||
"sites": [
|
||||
{
|
||||
"type": "PMV2",
|
||||
"name": "X0Y0",
|
||||
"site_pins": {
|
||||
"EN": "CLK_PMV2_EN",
|
||||
"A0": "CLK_PMV2_A0",
|
||||
"ODIV2": "CLK_PMV2_ODIV2",
|
||||
"A2": "CLK_PMV2_A2",
|
||||
"ODIV4": "CLK_PMV2_ODIV4",
|
||||
"A1": "CLK_PMV2_A1",
|
||||
"O": "CLK_PMV2_O"
|
||||
},
|
||||
"y_coord": 0,
|
||||
"x_coord": 0,
|
||||
"prefix": "PMV"
|
||||
}
|
||||
]
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,360 +1,360 @@
|
|||
{
|
||||
"pips": {},
|
||||
"wires": [
|
||||
"CLK_FEED_CK_GCLK13",
|
||||
"CLK_FEED_CK_BUFG_CASC3",
|
||||
"CLK_FEED_WW4B2",
|
||||
"CLK_FEED_EE4B2",
|
||||
"CLK_FEED_CK_GCLK26",
|
||||
"CLK_FEED_WW2A0",
|
||||
"CLK_PMV_BYP3_0",
|
||||
"CLK_FEED_EE4A2",
|
||||
"CLK_FEED_R_CK_BUFG_CASC25",
|
||||
"CLK_PMV_FAN5_0",
|
||||
"CLK_FEED_R_CK_GCLK4",
|
||||
"CLK_FEED_R_CK_BUFG_CASC4",
|
||||
"CLK_PMV_LOGIC_OUTS18_0",
|
||||
"CLK_PMV_FAN1_0",
|
||||
"CLK_FEED_EE4BEG1",
|
||||
"CLK_FEED_CK_GCLK29",
|
||||
"CLK_PMV_IMUX46_0",
|
||||
"CLK_FEED_WW4C0",
|
||||
"CLK_FEED_EE4BEG2",
|
||||
"CLK_PMV_BYP0_0",
|
||||
"CLK_PMV_LOGIC_OUTS8_0",
|
||||
"CLK_FEED_CK_GCLK19",
|
||||
"CLK_FEED_CK_BUFG_CASC22",
|
||||
"CLK_PMV_IMUX44_0",
|
||||
"CLK_FEED_CK_BUFG_CASC5",
|
||||
"CLK_FEED_R_CK_BUFG_CASC29",
|
||||
"CLK_PMV_IMUX36_0",
|
||||
"CLK_FEED_SW4END1",
|
||||
"CLK_PMV_BYP5_0",
|
||||
"CLK_PMV_IMUX2_0",
|
||||
"CLK_FEED_LH12",
|
||||
"CLK_PMV_IMUX5_0",
|
||||
"CLK_FEED_CK_BUFG_CASC13",
|
||||
"CLK_FEED_CK_BUFG_CASC7",
|
||||
"CLK_FEED_WW4END3",
|
||||
"CLK_FEED_SE4C1",
|
||||
"CLK_FEED_CK_GCLK9",
|
||||
"CLK_PMV_LOGIC_OUTS17_0",
|
||||
"CLK_PMV_IMUX25_0",
|
||||
"CLK_FEED_EE4C3",
|
||||
"CLK_FEED_R_CK_BUFG_CASC22",
|
||||
"CLK_FEED_R_CK_GCLK14",
|
||||
"CLK_FEED_WW2END0",
|
||||
"CLK_FEED_CK_GCLK2",
|
||||
"CLK_FEED_R_CK_BUFG_CASC19",
|
||||
"CLK_FEED_R_CK_BUFG_CASC11",
|
||||
"CLK_FEED_R_CK_GCLK11",
|
||||
"CLK_FEED_CK_GCLK15",
|
||||
"CLK_PMV_LOGIC_OUTS5_0",
|
||||
"CLK_PMV_CTRL0_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC5",
|
||||
"CLK_FEED_R_CK_BUFG_CASC16",
|
||||
"CLK_PMV_FAN0_0",
|
||||
"CLK_PMV_IMUX43_0",
|
||||
"CLK_FEED_NE4BEG0",
|
||||
"CLK_FEED_SE4BEG3",
|
||||
"CLK_FEED_WW4A2",
|
||||
"CLK_FEED_SE4BEG1",
|
||||
"CLK_PMV2_A1",
|
||||
"CLK_FEED_CK_GCLK0",
|
||||
"CLK_FEED_WW2A2",
|
||||
"CLK_FEED_R_CK_GCLK13",
|
||||
"CLK_FEED_R_CK_BUFG_CASC24",
|
||||
"CLK_PMV_IMUX17_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC13",
|
||||
"CLK_FEED_CK_GCLK17",
|
||||
"CLK_FEED_CK_BUFG_CASC11",
|
||||
"CLK_FEED_EE4BEG0",
|
||||
"CLK_PMV_IMUX13_0",
|
||||
"CLK_FEED_CK_GCLK11",
|
||||
"CLK_PMV_IMUX20_0",
|
||||
"CLK_FEED_CK_GCLK27",
|
||||
"CLK_FEED_CK_BUFG_CASC2",
|
||||
"CLK_FEED_CK_GCLK3",
|
||||
"CLK_FEED_R_CK_GCLK5",
|
||||
"CLK_FEED_R_CK_GCLK0",
|
||||
"CLK_FEED_LH10",
|
||||
"CLK_PMV_IMUX22_0",
|
||||
"CLK_FEED_SE4C0",
|
||||
"CLK_PMV2_A0",
|
||||
"CLK_FEED_LH3",
|
||||
"CLK_PMV_LOGIC_OUTS10_0",
|
||||
"CLK_PMV_IMUX7_0",
|
||||
"CLK_PMV_IMUX31_0",
|
||||
"CLK_FEED_WW2A3",
|
||||
"CLK_FEED_NW4A1",
|
||||
"CLK_FEED_R_CK_BUFG_CASC14",
|
||||
"CLK_PMV_IMUX28_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC30",
|
||||
"CLK_FEED_LH5",
|
||||
"CLK_FEED_NW4A2",
|
||||
"CLK_PMV_BYP1_0",
|
||||
"CLK_FEED_WW4END1",
|
||||
"CLK_FEED_EE2BEG2",
|
||||
"CLK_FEED_WL1END0",
|
||||
"CLK_FEED_NE4BEG3",
|
||||
"CLK_PMV_IMUX42_0",
|
||||
"CLK_PMV_FAN3_0",
|
||||
"CLK_FEED_WL1END1",
|
||||
"CLK_FEED_SW2A1",
|
||||
"CLK_PMV_LOGIC_OUTS6_0",
|
||||
"CLK_FEED_EE2BEG0",
|
||||
"CLK_FEED_CK_GCLK7",
|
||||
"CLK_PMV_IMUX40_0",
|
||||
"CLK_FEED_CK_GCLK22",
|
||||
"CLK_FEED_EE4A1",
|
||||
"CLK_FEED_EE4BEG3",
|
||||
"CLK_FEED_R_CK_BUFG_CASC20",
|
||||
"CLK_FEED_CK_BUFG_CASC8",
|
||||
"CLK_FEED_EE2BEG1",
|
||||
"CLK_FEED_SW4END0",
|
||||
"CLK_FEED_CK_BUFG_CASC12",
|
||||
"CLK_FEED_SE4BEG2",
|
||||
"CLK_FEED_NE2A3",
|
||||
"CLK_FEED_LH8",
|
||||
"CLK_FEED_R_CK_BUFG_CASC0",
|
||||
"CLK_PMV_LOGIC_OUTS13_0",
|
||||
"CLK_PMV_IMUX29_0",
|
||||
"CLK_FEED_WR1END1",
|
||||
"CLK_FEED_NE4BEG2",
|
||||
"CLK_FEED_R_CK_GCLK25",
|
||||
"CLK_FEED_WW4END2",
|
||||
"CLK_FEED_SW4A3",
|
||||
"CLK_PMV_IMUX26_0",
|
||||
"CLK_FEED_LH11",
|
||||
"CLK_PMV_IMUX0_0",
|
||||
"CLK_PMV_IMUX11_0",
|
||||
"CLK_FEED_EE4C1",
|
||||
"CLK_PMV_LOGIC_OUTS16_0",
|
||||
"CLK_PMV_IMUX15_0",
|
||||
"CLK_FEED_R_CK_GCLK29",
|
||||
"CLK_FEED_R_CK_GCLK27",
|
||||
"CLK_FEED_NE4C0",
|
||||
"CLK_FEED_CK_GCLK24",
|
||||
"CLK_FEED_CK_GCLK14",
|
||||
"CLK_FEED_R_CK_BUFG_CASC9",
|
||||
"CLK_FEED_SE4C2",
|
||||
"CLK_PMV_LOGIC_OUTS4_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC1",
|
||||
"CLK_FEED_ER1BEG1",
|
||||
"CLK_PMV_IMUX41_0",
|
||||
"CLK_FEED_R_CK_GCLK6",
|
||||
"CLK_FEED_MONITOR_P",
|
||||
"CLK_FEED_CK_GCLK1",
|
||||
"CLK_FEED_R_CK_BUFG_CASC18",
|
||||
"CLK_PMV_IMUX45_0",
|
||||
"CLK_PMV_IMUX8_0",
|
||||
"CLK_FEED_WW4C3",
|
||||
"CLK_PMV_LOGIC_OUTS12_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC21",
|
||||
"CLK_FEED_R_CK_GCLK21",
|
||||
"CLK_FEED_R_CK_GCLK24",
|
||||
"CLK_FEED_WW2END2",
|
||||
"CLK_FEED_SE2A1",
|
||||
"CLK_FEED_WW4A3",
|
||||
"CLK_FEED_CK_GCLK8",
|
||||
"CLK_FEED_CK_GCLK20",
|
||||
"CLK_FEED_CK_BUFG_CASC10",
|
||||
"CLK_PMV_LOGIC_OUTS23_0",
|
||||
"CLK_FEED_CK_BUFG_CASC0",
|
||||
"CLK_FEED_EL1BEG1",
|
||||
"CLK_PMV_IMUX34_0",
|
||||
"CLK_FEED_R_CK_GCLK12",
|
||||
"CLK_FEED_CK_GCLK6",
|
||||
"CLK_FEED_R_CK_GCLK8",
|
||||
"CLK_FEED_R_CK_BUFG_CASC27",
|
||||
"CLK_FEED_CK_BUFG_CASC21",
|
||||
"CLK_FEED_R_CK_BUFG_CASC26",
|
||||
"CLK_FEED_EE2BEG3",
|
||||
"CLK_FEED_LH7",
|
||||
"CLK_FEED_SW4A0",
|
||||
"CLK_PMV_LOGIC_OUTS1_0",
|
||||
"CLK_FEED_CK_BUFG_CASC9",
|
||||
"CLK_PMV_FAN7_0",
|
||||
"CLK_PMV_LOGIC_OUTS20_0",
|
||||
"CLK_FEED_LH9",
|
||||
"CLK_FEED_SW4A2",
|
||||
"CLK_FEED_CK_BUFG_CASC26",
|
||||
"CLK_FEED_R_CK_BUFG_CASC31",
|
||||
"CLK_FEED_R_CK_GCLK28",
|
||||
"CLK_PMV_LOGIC_OUTS14_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC28",
|
||||
"CLK_FEED_CK_GCLK21",
|
||||
"CLK_FEED_MONITOR_N",
|
||||
"CLK_PMV_LOGIC_OUTS3_0",
|
||||
"CLK_FEED_EE4B3",
|
||||
"CLK_PMV_IMUX24_0",
|
||||
"CLK_PMV_LOGIC_OUTS15_0",
|
||||
"CLK_PMV_IMUX1_0",
|
||||
"CLK_FEED_NE2A1",
|
||||
"CLK_FEED_CK_GCLK25",
|
||||
"CLK_PMV_FAN2_0",
|
||||
"CLK_FEED_CK_BUFG_CASC23",
|
||||
"CLK_FEED_R_CK_BUFG_CASC7",
|
||||
"CLK_FEED_SW4END2",
|
||||
"CLK_PMV_BYP4_0",
|
||||
"CLK_PMV_CLK1_0",
|
||||
"CLK_PMV_IMUX32_0",
|
||||
"CLK_PMV_IMUX9_0",
|
||||
"CLK_FEED_EE2A1",
|
||||
"CLK_FEED_SE2A3",
|
||||
"CLK_FEED_SW2A0",
|
||||
"CLK_FEED_NE2A2",
|
||||
"CLK_FEED_R_CK_GCLK17",
|
||||
"CLK_FEED_CK_BUFG_CASC20",
|
||||
"CLK_FEED_WW4C2",
|
||||
"CLK_FEED_NE4BEG1",
|
||||
"CLK_FEED_CK_GCLK12",
|
||||
"CLK_FEED_R_CK_GCLK23",
|
||||
"CLK_FEED_NW2A1",
|
||||
"CLK_FEED_EE4B0",
|
||||
"CLK_FEED_NE4C2",
|
||||
"CLK_PMV_IMUX10_0",
|
||||
"CLK_FEED_R_CK_GCLK15",
|
||||
"CLK_PMV_LOGIC_OUTS9_0",
|
||||
"CLK_FEED_WW4B0",
|
||||
"CLK_FEED_CK_BUFG_CASC19",
|
||||
"CLK_PMV_BYP2_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC6",
|
||||
"CLK_FEED_R_CK_GCLK20",
|
||||
"CLK_PMV_LOGIC_OUTS2_0",
|
||||
"CLK_FEED_WW2END1",
|
||||
"CLK_FEED_R_CK_BUFG_CASC3",
|
||||
"CLK_PMV_LOGIC_OUTS7_0",
|
||||
"CLK_FEED_CK_BUFG_CASC25",
|
||||
"CLK_PMV_FAN6_0",
|
||||
"CLK_PMV_IMUX37_0",
|
||||
"CLK_FEED_NW2A3",
|
||||
"CLK_FEED_R_CK_GCLK1",
|
||||
"CLK_FEED_WR1END0",
|
||||
"CLK_FEED_EE4A3",
|
||||
"CLK_FEED_R_CK_GCLK10",
|
||||
"CLK_FEED_R_CK_BUFG_CASC17",
|
||||
"CLK_FEED_NW2A2",
|
||||
"CLK_PMV_IMUX4_0",
|
||||
"CLK_FEED_LH4",
|
||||
"CLK_FEED_EE2A0",
|
||||
"CLK_PMV_IMUX35_0",
|
||||
"CLK_PMV_IMUX16_0",
|
||||
"CLK_FEED_ER1BEG2",
|
||||
"CLK_PMV2_ODIV2",
|
||||
"CLK_FEED_ER1BEG3",
|
||||
"CLK_FEED_WW4A0",
|
||||
"CLK_FEED_CK_BUFG_CASC18",
|
||||
"CLK_FEED_WR1END3",
|
||||
"CLK_PMV2_A2",
|
||||
"CLK_FEED_LH1",
|
||||
"CLK_FEED_EE2A3",
|
||||
"CLK_FEED_NW4A3",
|
||||
"CLK_FEED_WW2END3",
|
||||
"CLK_FEED_CK_BUFG_CASC27",
|
||||
"CLK_FEED_SE4C3",
|
||||
"CLK_PMV_IMUX23_0",
|
||||
"CLK_PMV_IMUX38_0",
|
||||
"CLK_PMV_IMUX12_0",
|
||||
"CLK_FEED_CK_BUFG_CASC1",
|
||||
"CLK_FEED_NW4END2",
|
||||
"CLK_FEED_EE4C0",
|
||||
"CLK_FEED_CK_GCLK10",
|
||||
"CLK_FEED_R_CK_GCLK30",
|
||||
"CLK_FEED_WL1END3",
|
||||
"CLK_FEED_NW2A0",
|
||||
"CLK_FEED_ER1BEG0",
|
||||
"CLK_FEED_NW4A0",
|
||||
"CLK_FEED_WW4A1",
|
||||
"CLK_FEED_R_CK_BUFG_CASC23",
|
||||
"CLK_FEED_CK_BUFG_CASC15",
|
||||
"CLK_FEED_LH2",
|
||||
"CLK_FEED_SW2A2",
|
||||
"CLK_PMV_BYP6_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC2",
|
||||
"CLK_PMV_IMUX3_0",
|
||||
"CLK_FEED_CK_GCLK31",
|
||||
"CLK_FEED_CK_GCLK18",
|
||||
"CLK_FEED_R_CK_GCLK3",
|
||||
"CLK_FEED_LH6",
|
||||
"CLK_FEED_CK_GCLK4",
|
||||
"CLK_FEED_R_CK_GCLK2",
|
||||
"CLK_PMV_IMUX21_0",
|
||||
"CLK_FEED_NW4END3",
|
||||
"CLK_FEED_NE4C1",
|
||||
"CLK_FEED_CK_BUFG_CASC31",
|
||||
"CLK_FEED_R_CK_GCLK7",
|
||||
"CLK_FEED_WW2A1",
|
||||
"CLK_FEED_R_CK_GCLK16",
|
||||
"CLK_PMV_IMUX33_0",
|
||||
"CLK_PMV_IMUX18_0",
|
||||
"CLK_FEED_SE4BEG0",
|
||||
"CLK_FEED_WL1END2",
|
||||
"CLK_FEED_NW4END1",
|
||||
"CLK_FEED_NW4END0",
|
||||
"CLK_PMV_LOGIC_OUTS11_0",
|
||||
"CLK_FEED_SE2A0",
|
||||
"CLK_FEED_CK_GCLK5",
|
||||
"CLK_FEED_CK_BUFG_CASC4",
|
||||
"CLK_FEED_WR1END2",
|
||||
"CLK_FEED_SW4END3",
|
||||
"CLK_FEED_WW4END0",
|
||||
"CLK_PMV_CTRL1_0",
|
||||
"CLK_PMV_LOGIC_OUTS21_0",
|
||||
"CLK_FEED_EE4B1",
|
||||
"CLK_FEED_SW4A1",
|
||||
"CLK_FEED_CK_GCLK28",
|
||||
"CLK_FEED_NE4C3",
|
||||
"CLK_FEED_CK_BUFG_CASC17",
|
||||
"CLK_FEED_CK_GCLK23",
|
||||
"CLK_PMV_IMUX19_0",
|
||||
"CLK_FEED_R_CK_GCLK18",
|
||||
"CLK_FEED_EE2A2",
|
||||
"CLK_FEED_R_CK_GCLK19",
|
||||
"CLK_FEED_CK_BUFG_CASC6",
|
||||
"CLK_FEED_CK_BUFG_CASC16",
|
||||
"CLK_FEED_NE2A0",
|
||||
"CLK_PMV_LOGIC_OUTS0_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC15",
|
||||
"CLK_FEED_R_CK_BUFG_CASC10",
|
||||
"CLK_FEED_R_CK_BUFG_CASC8",
|
||||
"CLK_PMV_IMUX6_0",
|
||||
"CLK_PMV_IMUX39_0",
|
||||
"CLK_FEED_SE2A2",
|
||||
"CLK_FEED_R_CK_GCLK22",
|
||||
"CLK_FEED_SW2A3",
|
||||
"CLK_FEED_EE4A0",
|
||||
"CLK_FEED_CK_GCLK30",
|
||||
"CLK_PMV_CLK0_0",
|
||||
"CLK_FEED_EL1BEG3",
|
||||
"CLK_FEED_WW4C1",
|
||||
"CLK_PMV_FAN4_0",
|
||||
"CLK_FEED_R_CK_GCLK26",
|
||||
"CLK_PMV_LOGIC_OUTS22_0",
|
||||
"CLK_FEED_CK_BUFG_CASC28",
|
||||
"CLK_FEED_EL1BEG0",
|
||||
"CLK_PMV_LOGIC_OUTS19_0",
|
||||
"CLK_FEED_R_CK_GCLK31",
|
||||
"CLK_PMV_IMUX47_0",
|
||||
"CLK_PMV_IMUX30_0",
|
||||
"CLK_PMV_IMUX27_0",
|
||||
"CLK_FEED_CK_BUFG_CASC24",
|
||||
"CLK_FEED_EE4C2",
|
||||
"CLK_PMV2_ODIV4",
|
||||
"CLK_FEED_R_CK_GCLK9",
|
||||
"CLK_FEED_R_CK_BUFG_CASC12",
|
||||
"CLK_PMV_IMUX14_0",
|
||||
"CLK_FEED_WW4B3",
|
||||
"CLK_PMV2_O",
|
||||
"CLK_FEED_CK_BUFG_CASC30",
|
||||
"CLK_FEED_CK_BUFG_CASC14",
|
||||
"CLK_PMV_BYP7_0",
|
||||
"CLK_FEED_EL1BEG2",
|
||||
"CLK_FEED_CK_GCLK16",
|
||||
"CLK_FEED_CK_BUFG_CASC29",
|
||||
"CLK_PMV2_EN",
|
||||
"CLK_FEED_WW4B1"
|
||||
],
|
||||
"tile_type": "CLK_PMV2_SVT",
|
||||
"sites": []
|
||||
}
|
||||
"wires": [
|
||||
"CLK_FEED_NE2A0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC28",
|
||||
"CLK_FEED_CK_GCLK19",
|
||||
"CLK_FEED_ER1BEG3",
|
||||
"CLK_FEED_CK_BUFG_CASC29",
|
||||
"CLK_FEED_R_CK_GCLK18",
|
||||
"CLK_FEED_R_CK_GCLK31",
|
||||
"CLK_PMV_CLK1_0",
|
||||
"CLK_FEED_CK_BUFG_CASC1",
|
||||
"CLK_FEED_R_CK_GCLK6",
|
||||
"CLK_FEED_LH7",
|
||||
"CLK_FEED_CK_BUFG_CASC3",
|
||||
"CLK_FEED_WW4B2",
|
||||
"CLK_FEED_LH12",
|
||||
"CLK_FEED_R_CK_BUFG_CASC14",
|
||||
"CLK_FEED_EE4A3",
|
||||
"CLK_FEED_CK_BUFG_CASC13",
|
||||
"CLK_PMV_IMUX28_0",
|
||||
"CLK_PMV_IMUX24_0",
|
||||
"CLK_FEED_ER1BEG0",
|
||||
"CLK_PMV_IMUX44_0",
|
||||
"CLK_FEED_SW4END3",
|
||||
"CLK_FEED_WL1END0",
|
||||
"CLK_FEED_SW2A0",
|
||||
"CLK_PMV_IMUX15_0",
|
||||
"CLK_PMV_IMUX43_0",
|
||||
"CLK_PMV_FAN0_0",
|
||||
"CLK_FEED_R_CK_GCLK13",
|
||||
"CLK_PMV_FAN1_0",
|
||||
"CLK_FEED_CK_BUFG_CASC26",
|
||||
"CLK_FEED_SE4BEG1",
|
||||
"CLK_FEED_CK_BUFG_CASC7",
|
||||
"CLK_PMV_IMUX11_0",
|
||||
"CLK_PMV_LOGIC_OUTS12_0",
|
||||
"CLK_FEED_CK_BUFG_CASC5",
|
||||
"CLK_FEED_CK_GCLK18",
|
||||
"CLK_PMV_BYP0_0",
|
||||
"CLK_FEED_WW4A3",
|
||||
"CLK_FEED_R_CK_BUFG_CASC10",
|
||||
"CLK_FEED_WW4C2",
|
||||
"CLK_FEED_NW4END3",
|
||||
"CLK_FEED_CK_GCLK27",
|
||||
"CLK_PMV_IMUX33_0",
|
||||
"CLK_FEED_R_CK_GCLK3",
|
||||
"CLK_FEED_CK_BUFG_CASC21",
|
||||
"CLK_FEED_WW2END0",
|
||||
"CLK_FEED_WW2A1",
|
||||
"CLK_PMV_LOGIC_OUTS18_0",
|
||||
"CLK_PMV_IMUX26_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC22",
|
||||
"CLK_PMV2_EN",
|
||||
"CLK_PMV_LOGIC_OUTS3_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC0",
|
||||
"CLK_FEED_CK_GCLK12",
|
||||
"CLK_FEED_EE4A2",
|
||||
"CLK_FEED_EE4B0",
|
||||
"CLK_FEED_WW2A2",
|
||||
"CLK_FEED_CK_BUFG_CASC10",
|
||||
"CLK_FEED_CK_BUFG_CASC12",
|
||||
"CLK_FEED_R_CK_BUFG_CASC25",
|
||||
"CLK_FEED_EE4A1",
|
||||
"CLK_PMV_LOGIC_OUTS23_0",
|
||||
"CLK_PMV_IMUX29_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC17",
|
||||
"CLK_PMV_LOGIC_OUTS5_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC30",
|
||||
"CLK_PMV_IMUX31_0",
|
||||
"CLK_FEED_CK_GCLK15",
|
||||
"CLK_FEED_R_CK_BUFG_CASC26",
|
||||
"CLK_FEED_WW2END1",
|
||||
"CLK_PMV2_ODIV2",
|
||||
"CLK_FEED_ER1BEG1",
|
||||
"CLK_FEED_EL1BEG0",
|
||||
"CLK_PMV_LOGIC_OUTS1_0",
|
||||
"CLK_PMV_LOGIC_OUTS21_0",
|
||||
"CLK_FEED_NE4C3",
|
||||
"CLK_FEED_WW4C0",
|
||||
"CLK_PMV_IMUX20_0",
|
||||
"CLK_PMV_BYP4_0",
|
||||
"CLK_FEED_CK_GCLK24",
|
||||
"CLK_FEED_NE2A2",
|
||||
"CLK_FEED_SE4BEG3",
|
||||
"CLK_PMV_LOGIC_OUTS16_0",
|
||||
"CLK_PMV_IMUX16_0",
|
||||
"CLK_FEED_CK_BUFG_CASC4",
|
||||
"CLK_PMV_IMUX9_0",
|
||||
"CLK_FEED_CK_GCLK23",
|
||||
"CLK_FEED_CK_BUFG_CASC20",
|
||||
"CLK_FEED_R_CK_GCLK12",
|
||||
"CLK_FEED_R_CK_BUFG_CASC27",
|
||||
"CLK_FEED_SE4C3",
|
||||
"CLK_FEED_CK_GCLK22",
|
||||
"CLK_FEED_NW4A2",
|
||||
"CLK_FEED_R_CK_GCLK9",
|
||||
"CLK_FEED_CK_GCLK17",
|
||||
"CLK_PMV_BYP7_0",
|
||||
"CLK_FEED_CK_BUFG_CASC6",
|
||||
"CLK_FEED_MONITOR_P",
|
||||
"CLK_FEED_NW2A2",
|
||||
"CLK_FEED_EE4BEG1",
|
||||
"CLK_FEED_R_CK_GCLK14",
|
||||
"CLK_FEED_EE4C0",
|
||||
"CLK_PMV_IMUX2_0",
|
||||
"CLK_FEED_EE4BEG3",
|
||||
"CLK_FEED_NE2A1",
|
||||
"CLK_FEED_WL1END3",
|
||||
"CLK_FEED_CK_GCLK28",
|
||||
"CLK_PMV_IMUX35_0",
|
||||
"CLK_PMV_LOGIC_OUTS7_0",
|
||||
"CLK_FEED_WW4B1",
|
||||
"CLK_FEED_SW4END0",
|
||||
"CLK_FEED_WW4END1",
|
||||
"CLK_FEED_R_CK_GCLK17",
|
||||
"CLK_FEED_R_CK_BUFG_CASC11",
|
||||
"CLK_FEED_WW4C1",
|
||||
"CLK_FEED_EL1BEG3",
|
||||
"CLK_PMV_IMUX17_0",
|
||||
"CLK_FEED_SE2A3",
|
||||
"CLK_FEED_R_CK_GCLK22",
|
||||
"CLK_FEED_NE4C0",
|
||||
"CLK_FEED_WW2A3",
|
||||
"CLK_FEED_NW4END1",
|
||||
"CLK_PMV_IMUX8_0",
|
||||
"CLK_FEED_SE2A2",
|
||||
"CLK_FEED_EE4B2",
|
||||
"CLK_FEED_R_CK_GCLK29",
|
||||
"CLK_FEED_WW2END3",
|
||||
"CLK_FEED_LH4",
|
||||
"CLK_FEED_WL1END2",
|
||||
"CLK_FEED_CK_GCLK2",
|
||||
"CLK_FEED_R_CK_GCLK25",
|
||||
"CLK_PMV_FAN3_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC13",
|
||||
"CLK_FEED_CK_BUFG_CASC27",
|
||||
"CLK_FEED_NW2A1",
|
||||
"CLK_FEED_SW4A3",
|
||||
"CLK_FEED_CK_BUFG_CASC31",
|
||||
"CLK_PMV_BYP3_0",
|
||||
"CLK_FEED_CK_GCLK1",
|
||||
"CLK_FEED_LH1",
|
||||
"CLK_FEED_CK_GCLK14",
|
||||
"CLK_FEED_R_CK_GCLK2",
|
||||
"CLK_FEED_R_CK_BUFG_CASC2",
|
||||
"CLK_PMV_CLK0_0",
|
||||
"CLK_FEED_WR1END0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC20",
|
||||
"CLK_FEED_NE4C1",
|
||||
"CLK_FEED_CK_GCLK16",
|
||||
"CLK_PMV_FAN2_0",
|
||||
"CLK_FEED_R_CK_GCLK5",
|
||||
"CLK_FEED_SE4C0",
|
||||
"CLK_FEED_EL1BEG2",
|
||||
"CLK_FEED_EL1BEG1",
|
||||
"CLK_FEED_EE4B1",
|
||||
"CLK_PMV2_A0",
|
||||
"CLK_FEED_CK_BUFG_CASC22",
|
||||
"CLK_PMV_IMUX40_0",
|
||||
"CLK_FEED_WR1END1",
|
||||
"CLK_FEED_NW4END0",
|
||||
"CLK_PMV_IMUX42_0",
|
||||
"CLK_FEED_EE2BEG1",
|
||||
"CLK_FEED_R_CK_GCLK23",
|
||||
"CLK_PMV2_A2",
|
||||
"CLK_FEED_R_CK_GCLK1",
|
||||
"CLK_FEED_LH2",
|
||||
"CLK_FEED_SW2A2",
|
||||
"CLK_FEED_ER1BEG2",
|
||||
"CLK_FEED_WL1END1",
|
||||
"CLK_PMV_IMUX47_0",
|
||||
"CLK_FEED_NW4A1",
|
||||
"CLK_PMV_BYP1_0",
|
||||
"CLK_PMV_IMUX5_0",
|
||||
"CLK_FEED_SW4A2",
|
||||
"CLK_FEED_CK_GCLK10",
|
||||
"CLK_FEED_CK_BUFG_CASC14",
|
||||
"CLK_FEED_CK_BUFG_CASC28",
|
||||
"CLK_PMV_FAN7_0",
|
||||
"CLK_FEED_CK_BUFG_CASC18",
|
||||
"CLK_FEED_R_CK_GCLK24",
|
||||
"CLK_FEED_EE2A1",
|
||||
"CLK_FEED_R_CK_BUFG_CASC15",
|
||||
"CLK_PMV_LOGIC_OUTS10_0",
|
||||
"CLK_FEED_SW2A1",
|
||||
"CLK_FEED_CK_BUFG_CASC8",
|
||||
"CLK_PMV_IMUX45_0",
|
||||
"CLK_FEED_CK_BUFG_CASC2",
|
||||
"CLK_FEED_R_CK_BUFG_CASC8",
|
||||
"CLK_PMV_BYP2_0",
|
||||
"CLK_PMV_IMUX14_0",
|
||||
"CLK_FEED_R_CK_GCLK0",
|
||||
"CLK_FEED_WW4B3",
|
||||
"CLK_PMV_IMUX7_0",
|
||||
"CLK_FEED_CK_GCLK3",
|
||||
"CLK_FEED_LH3",
|
||||
"CLK_PMV_IMUX6_0",
|
||||
"CLK_FEED_SE2A0",
|
||||
"CLK_FEED_NE4C2",
|
||||
"CLK_FEED_WW4C3",
|
||||
"CLK_PMV_IMUX38_0",
|
||||
"CLK_PMV_FAN6_0",
|
||||
"CLK_FEED_EE4B3",
|
||||
"CLK_PMV2_ODIV4",
|
||||
"CLK_FEED_NW4A0",
|
||||
"CLK_FEED_CK_BUFG_CASC25",
|
||||
"CLK_FEED_R_CK_GCLK20",
|
||||
"CLK_FEED_EE2A3",
|
||||
"CLK_FEED_R_CK_GCLK28",
|
||||
"CLK_FEED_LH11",
|
||||
"CLK_FEED_WW4B0",
|
||||
"CLK_PMV_IMUX30_0",
|
||||
"CLK_PMV_FAN4_0",
|
||||
"CLK_FEED_CK_GCLK4",
|
||||
"CLK_FEED_CK_GCLK13",
|
||||
"CLK_FEED_WW2END2",
|
||||
"CLK_FEED_SW4END2",
|
||||
"CLK_PMV_LOGIC_OUTS4_0",
|
||||
"CLK_PMV_LOGIC_OUTS6_0",
|
||||
"CLK_FEED_NW2A0",
|
||||
"CLK_FEED_R_CK_GCLK30",
|
||||
"CLK_FEED_R_CK_BUFG_CASC1",
|
||||
"CLK_FEED_CK_GCLK25",
|
||||
"CLK_PMV_IMUX1_0",
|
||||
"CLK_FEED_CK_BUFG_CASC19",
|
||||
"CLK_PMV_IMUX34_0",
|
||||
"CLK_FEED_WW4A2",
|
||||
"CLK_FEED_R_CK_BUFG_CASC6",
|
||||
"CLK_PMV_LOGIC_OUTS17_0",
|
||||
"CLK_PMV_LOGIC_OUTS9_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC29",
|
||||
"CLK_FEED_SW4END1",
|
||||
"CLK_FEED_LH10",
|
||||
"CLK_FEED_CK_BUFG_CASC0",
|
||||
"CLK_PMV_IMUX21_0",
|
||||
"CLK_FEED_NE4BEG3",
|
||||
"CLK_FEED_R_CK_GCLK26",
|
||||
"CLK_PMV_IMUX41_0",
|
||||
"CLK_PMV_IMUX46_0",
|
||||
"CLK_PMV_IMUX25_0",
|
||||
"CLK_PMV_IMUX39_0",
|
||||
"CLK_FEED_CK_GCLK7",
|
||||
"CLK_FEED_CK_BUFG_CASC23",
|
||||
"CLK_FEED_R_CK_BUFG_CASC16",
|
||||
"CLK_FEED_EE2BEG0",
|
||||
"CLK_FEED_CK_GCLK26",
|
||||
"CLK_FEED_CK_BUFG_CASC15",
|
||||
"CLK_FEED_SW4A1",
|
||||
"CLK_FEED_WW4A0",
|
||||
"CLK_PMV_IMUX22_0",
|
||||
"CLK_PMV_LOGIC_OUTS11_0",
|
||||
"CLK_PMV_BYP5_0",
|
||||
"CLK_PMV_LOGIC_OUTS15_0",
|
||||
"CLK_FEED_NE2A3",
|
||||
"CLK_FEED_CK_BUFG_CASC17",
|
||||
"CLK_FEED_CK_GCLK21",
|
||||
"CLK_PMV_LOGIC_OUTS0_0",
|
||||
"CLK_FEED_NE4BEG0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC23",
|
||||
"CLK_FEED_NE4BEG1",
|
||||
"CLK_PMV_LOGIC_OUTS19_0",
|
||||
"CLK_FEED_WW4END0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC12",
|
||||
"CLK_FEED_SE4BEG2",
|
||||
"CLK_FEED_EE2BEG3",
|
||||
"CLK_FEED_R_CK_GCLK7",
|
||||
"CLK_PMV_IMUX4_0",
|
||||
"CLK_FEED_CK_BUFG_CASC30",
|
||||
"CLK_PMV2_A1",
|
||||
"CLK_FEED_R_CK_GCLK8",
|
||||
"CLK_FEED_WW4A1",
|
||||
"CLK_FEED_EE4BEG0",
|
||||
"CLK_FEED_WR1END2",
|
||||
"CLK_FEED_CK_BUFG_CASC24",
|
||||
"CLK_FEED_R_CK_GCLK16",
|
||||
"CLK_FEED_R_CK_GCLK10",
|
||||
"CLK_FEED_CK_BUFG_CASC16",
|
||||
"CLK_FEED_R_CK_BUFG_CASC5",
|
||||
"CLK_FEED_CK_GCLK5",
|
||||
"CLK_FEED_R_CK_BUFG_CASC18",
|
||||
"CLK_FEED_NE4BEG2",
|
||||
"CLK_FEED_R_CK_GCLK11",
|
||||
"CLK_PMV_LOGIC_OUTS20_0",
|
||||
"CLK_FEED_R_CK_GCLK4",
|
||||
"CLK_PMV_IMUX12_0",
|
||||
"CLK_PMV_IMUX37_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC7",
|
||||
"CLK_PMV_IMUX18_0",
|
||||
"CLK_FEED_SE4C1",
|
||||
"CLK_FEED_CK_GCLK20",
|
||||
"CLK_PMV_LOGIC_OUTS8_0",
|
||||
"CLK_FEED_NW4END2",
|
||||
"CLK_FEED_EE4BEG2",
|
||||
"CLK_FEED_CK_GCLK30",
|
||||
"CLK_FEED_SE2A1",
|
||||
"CLK_FEED_LH6",
|
||||
"CLK_FEED_CK_GCLK29",
|
||||
"CLK_FEED_R_CK_GCLK27",
|
||||
"CLK_FEED_EE4C1",
|
||||
"CLK_FEED_SW4A0",
|
||||
"CLK_FEED_CK_GCLK9",
|
||||
"CLK_FEED_CK_BUFG_CASC11",
|
||||
"CLK_FEED_CK_GCLK8",
|
||||
"CLK_FEED_R_CK_BUFG_CASC9",
|
||||
"CLK_FEED_R_CK_BUFG_CASC3",
|
||||
"CLK_FEED_WW4END2",
|
||||
"CLK_FEED_CK_GCLK6",
|
||||
"CLK_FEED_EE2A2",
|
||||
"CLK_PMV_LOGIC_OUTS2_0",
|
||||
"CLK_PMV_LOGIC_OUTS14_0",
|
||||
"CLK_FEED_EE4C3",
|
||||
"CLK_FEED_NW2A3",
|
||||
"CLK_PMV_CTRL0_0",
|
||||
"CLK_PMV_LOGIC_OUTS22_0",
|
||||
"CLK_PMV_IMUX0_0",
|
||||
"CLK_FEED_EE2A0",
|
||||
"CLK_PMV_FAN5_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC24",
|
||||
"CLK_PMV_BYP6_0",
|
||||
"CLK_FEED_R_CK_GCLK19",
|
||||
"CLK_FEED_EE2BEG2",
|
||||
"CLK_FEED_R_CK_BUFG_CASC19",
|
||||
"CLK_FEED_WW4END3",
|
||||
"CLK_FEED_CK_GCLK31",
|
||||
"CLK_FEED_SW2A3",
|
||||
"CLK_PMV_IMUX23_0",
|
||||
"CLK_PMV_IMUX19_0",
|
||||
"CLK_PMV_IMUX36_0",
|
||||
"CLK_FEED_SE4C2",
|
||||
"CLK_FEED_EE4C2",
|
||||
"CLK_PMV_IMUX13_0",
|
||||
"CLK_FEED_SE4BEG0",
|
||||
"CLK_PMV_IMUX27_0",
|
||||
"CLK_FEED_LH9",
|
||||
"CLK_PMV2_O",
|
||||
"CLK_FEED_R_CK_GCLK15",
|
||||
"CLK_PMV_IMUX3_0",
|
||||
"CLK_PMV_CTRL1_0",
|
||||
"CLK_FEED_LH5",
|
||||
"CLK_PMV_LOGIC_OUTS13_0",
|
||||
"CLK_FEED_NW4A3",
|
||||
"CLK_PMV_IMUX10_0",
|
||||
"CLK_PMV_IMUX32_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC4",
|
||||
"CLK_FEED_R_CK_BUFG_CASC21",
|
||||
"CLK_FEED_CK_GCLK0",
|
||||
"CLK_FEED_MONITOR_N",
|
||||
"CLK_FEED_CK_GCLK11",
|
||||
"CLK_FEED_R_CK_BUFG_CASC31",
|
||||
"CLK_FEED_WW2A0",
|
||||
"CLK_FEED_EE4A0",
|
||||
"CLK_FEED_CK_BUFG_CASC9",
|
||||
"CLK_FEED_R_CK_GCLK21",
|
||||
"CLK_FEED_WR1END3",
|
||||
"CLK_FEED_LH8"
|
||||
],
|
||||
"pips": {},
|
||||
"tile_type": "CLK_PMV2_SVT",
|
||||
"sites": []
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,359 +1,359 @@
|
|||
{
|
||||
"pips": {},
|
||||
"wires": [
|
||||
"CLK_FEED_CK_GCLK13",
|
||||
"CLK_FEED_CK_BUFG_CASC3",
|
||||
"CLK_FEED_WW4B2",
|
||||
"CLK_FEED_EE4B2",
|
||||
"CLK_FEED_CK_GCLK26",
|
||||
"CLK_FEED_WW2A0",
|
||||
"CLK_PMV_BYP3_0",
|
||||
"CLK_FEED_EE4A2",
|
||||
"CLK_FEED_R_CK_BUFG_CASC25",
|
||||
"CLK_PMV_FAN5_0",
|
||||
"CLK_FEED_R_CK_GCLK4",
|
||||
"CLK_FEED_R_CK_BUFG_CASC4",
|
||||
"CLK_PMV_LOGIC_OUTS18_0",
|
||||
"CLK_PMV_FAN1_0",
|
||||
"CLK_FEED_EE4BEG1",
|
||||
"CLK_FEED_CK_GCLK29",
|
||||
"CLK_PMV_IMUX46_0",
|
||||
"CLK_PMVIOB_EN",
|
||||
"CLK_FEED_WW4C0",
|
||||
"CLK_FEED_EE4BEG2",
|
||||
"CLK_PMV_BYP0_0",
|
||||
"CLK_PMV_LOGIC_OUTS8_0",
|
||||
"CLK_FEED_CK_GCLK19",
|
||||
"CLK_FEED_CK_BUFG_CASC22",
|
||||
"CLK_PMV_IMUX44_0",
|
||||
"CLK_FEED_CK_BUFG_CASC5",
|
||||
"CLK_FEED_R_CK_BUFG_CASC29",
|
||||
"CLK_PMV_IMUX36_0",
|
||||
"CLK_FEED_SW4END1",
|
||||
"CLK_PMV_BYP5_0",
|
||||
"CLK_PMV_IMUX2_0",
|
||||
"CLK_FEED_LH12",
|
||||
"CLK_PMV_IMUX5_0",
|
||||
"CLK_FEED_CK_BUFG_CASC13",
|
||||
"CLK_FEED_CK_BUFG_CASC7",
|
||||
"CLK_FEED_WW4END3",
|
||||
"CLK_FEED_SE4C1",
|
||||
"CLK_FEED_CK_GCLK9",
|
||||
"CLK_PMV_LOGIC_OUTS17_0",
|
||||
"CLK_PMV_IMUX25_0",
|
||||
"CLK_FEED_EE4C3",
|
||||
"CLK_FEED_R_CK_BUFG_CASC22",
|
||||
"CLK_FEED_WW2END0",
|
||||
"CLK_FEED_CK_GCLK2",
|
||||
"CLK_FEED_R_CK_BUFG_CASC19",
|
||||
"CLK_FEED_R_CK_BUFG_CASC11",
|
||||
"CLK_FEED_R_CK_GCLK11",
|
||||
"CLK_FEED_CK_GCLK15",
|
||||
"CLK_PMV_LOGIC_OUTS5_0",
|
||||
"CLK_PMV_CTRL0_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC5",
|
||||
"CLK_FEED_R_CK_BUFG_CASC16",
|
||||
"CLK_PMV_FAN0_0",
|
||||
"CLK_PMV_IMUX43_0",
|
||||
"CLK_FEED_NE4BEG0",
|
||||
"CLK_FEED_SE4BEG3",
|
||||
"CLK_FEED_WW4A2",
|
||||
"CLK_FEED_SE4BEG1",
|
||||
"CLK_FEED_CK_GCLK0",
|
||||
"CLK_FEED_WW2A2",
|
||||
"CLK_FEED_R_CK_GCLK13",
|
||||
"CLK_FEED_R_CK_BUFG_CASC24",
|
||||
"CLK_PMV_IMUX17_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC13",
|
||||
"CLK_FEED_CK_GCLK17",
|
||||
"CLK_FEED_CK_BUFG_CASC11",
|
||||
"CLK_FEED_EE4BEG0",
|
||||
"CLK_PMV_IMUX13_0",
|
||||
"CLK_FEED_CK_GCLK11",
|
||||
"CLK_PMV_IMUX20_0",
|
||||
"CLK_FEED_CK_GCLK27",
|
||||
"CLK_FEED_CK_BUFG_CASC2",
|
||||
"CLK_FEED_CK_GCLK3",
|
||||
"CLK_FEED_R_CK_GCLK5",
|
||||
"CLK_FEED_R_CK_GCLK0",
|
||||
"CLK_FEED_LH10",
|
||||
"CLK_PMV_IMUX22_0",
|
||||
"CLK_FEED_SE4C0",
|
||||
"CLK_FEED_LH3",
|
||||
"CLK_PMV_LOGIC_OUTS10_0",
|
||||
"CLK_PMV_IMUX7_0",
|
||||
"CLK_PMV_IMUX31_0",
|
||||
"CLK_FEED_WW2A3",
|
||||
"CLK_FEED_NW4A1",
|
||||
"CLK_FEED_R_CK_BUFG_CASC14",
|
||||
"CLK_PMV_IMUX28_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC30",
|
||||
"CLK_FEED_LH5",
|
||||
"CLK_FEED_NW4A2",
|
||||
"CLK_PMV_BYP1_0",
|
||||
"CLK_PMVIOB_O",
|
||||
"CLK_FEED_WW4END1",
|
||||
"CLK_FEED_EE2BEG2",
|
||||
"CLK_FEED_WL1END0",
|
||||
"CLK_FEED_NE4BEG3",
|
||||
"CLK_PMV_IMUX42_0",
|
||||
"CLK_PMVIOB_A1",
|
||||
"CLK_PMV_FAN3_0",
|
||||
"CLK_FEED_WL1END1",
|
||||
"CLK_FEED_SW2A1",
|
||||
"CLK_PMV_LOGIC_OUTS6_0",
|
||||
"CLK_FEED_EE2BEG0",
|
||||
"CLK_FEED_CK_GCLK7",
|
||||
"CLK_PMV_IMUX40_0",
|
||||
"CLK_FEED_CK_GCLK22",
|
||||
"CLK_FEED_EE4A1",
|
||||
"CLK_FEED_EE4BEG3",
|
||||
"CLK_FEED_R_CK_BUFG_CASC20",
|
||||
"CLK_FEED_CK_BUFG_CASC8",
|
||||
"CLK_FEED_EE2BEG1",
|
||||
"CLK_FEED_SW4END0",
|
||||
"CLK_FEED_CK_BUFG_CASC12",
|
||||
"CLK_FEED_SE4BEG2",
|
||||
"CLK_FEED_NE2A3",
|
||||
"CLK_FEED_LH8",
|
||||
"CLK_FEED_R_CK_BUFG_CASC0",
|
||||
"CLK_PMV_LOGIC_OUTS13_0",
|
||||
"CLK_PMV_IMUX29_0",
|
||||
"CLK_FEED_WR1END1",
|
||||
"CLK_FEED_NE4BEG2",
|
||||
"CLK_FEED_R_CK_GCLK25",
|
||||
"CLK_FEED_WW4END2",
|
||||
"CLK_FEED_SW4A3",
|
||||
"CLK_PMV_IMUX26_0",
|
||||
"CLK_FEED_LH11",
|
||||
"CLK_PMV_IMUX0_0",
|
||||
"CLK_PMV_IMUX11_0",
|
||||
"CLK_FEED_EE4C1",
|
||||
"CLK_PMV_LOGIC_OUTS16_0",
|
||||
"CLK_PMV_IMUX15_0",
|
||||
"CLK_FEED_R_CK_GCLK29",
|
||||
"CLK_FEED_R_CK_GCLK27",
|
||||
"CLK_FEED_NE4C0",
|
||||
"CLK_FEED_CK_GCLK24",
|
||||
"CLK_FEED_CK_GCLK14",
|
||||
"CLK_FEED_R_CK_BUFG_CASC9",
|
||||
"CLK_FEED_SE4C2",
|
||||
"CLK_PMV_LOGIC_OUTS4_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC1",
|
||||
"CLK_FEED_ER1BEG1",
|
||||
"CLK_PMV_IMUX41_0",
|
||||
"CLK_FEED_R_CK_GCLK6",
|
||||
"CLK_FEED_MONITOR_P",
|
||||
"CLK_FEED_CK_GCLK1",
|
||||
"CLK_FEED_R_CK_BUFG_CASC18",
|
||||
"CLK_PMV_IMUX45_0",
|
||||
"CLK_PMV_IMUX8_0",
|
||||
"CLK_FEED_WW4C3",
|
||||
"CLK_PMV_LOGIC_OUTS12_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC21",
|
||||
"CLK_FEED_R_CK_GCLK21",
|
||||
"CLK_FEED_R_CK_GCLK24",
|
||||
"CLK_FEED_WW2END2",
|
||||
"CLK_FEED_SE2A1",
|
||||
"CLK_FEED_WW4A3",
|
||||
"CLK_FEED_CK_GCLK8",
|
||||
"CLK_FEED_CK_GCLK20",
|
||||
"CLK_FEED_CK_BUFG_CASC10",
|
||||
"CLK_PMV_LOGIC_OUTS23_0",
|
||||
"CLK_FEED_CK_BUFG_CASC0",
|
||||
"CLK_FEED_EL1BEG1",
|
||||
"CLK_PMV_IMUX34_0",
|
||||
"CLK_FEED_R_CK_GCLK12",
|
||||
"CLK_FEED_CK_GCLK6",
|
||||
"CLK_FEED_R_CK_GCLK8",
|
||||
"CLK_FEED_R_CK_BUFG_CASC27",
|
||||
"CLK_FEED_CK_BUFG_CASC21",
|
||||
"CLK_FEED_R_CK_BUFG_CASC26",
|
||||
"CLK_FEED_EE2BEG3",
|
||||
"CLK_FEED_LH7",
|
||||
"CLK_PMV_LOGIC_OUTS1_0",
|
||||
"CLK_FEED_SW4A0",
|
||||
"CLK_FEED_CK_BUFG_CASC9",
|
||||
"CLK_PMV_FAN7_0",
|
||||
"CLK_PMV_LOGIC_OUTS20_0",
|
||||
"CLK_FEED_LH9",
|
||||
"CLK_FEED_SW4A2",
|
||||
"CLK_FEED_CK_BUFG_CASC26",
|
||||
"CLK_FEED_R_CK_BUFG_CASC31",
|
||||
"CLK_FEED_R_CK_GCLK28",
|
||||
"CLK_PMV_LOGIC_OUTS14_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC28",
|
||||
"CLK_FEED_CK_GCLK21",
|
||||
"CLK_FEED_MONITOR_N",
|
||||
"CLK_PMV_LOGIC_OUTS3_0",
|
||||
"CLK_FEED_EE4B3",
|
||||
"CLK_PMV_IMUX24_0",
|
||||
"CLK_PMV_IMUX1_0",
|
||||
"CLK_PMV_LOGIC_OUTS15_0",
|
||||
"CLK_FEED_NE2A1",
|
||||
"CLK_FEED_CK_GCLK25",
|
||||
"CLK_PMV_FAN2_0",
|
||||
"CLK_FEED_CK_BUFG_CASC23",
|
||||
"CLK_FEED_R_CK_BUFG_CASC7",
|
||||
"CLK_FEED_SW4END2",
|
||||
"CLK_PMV_BYP4_0",
|
||||
"CLK_PMV_CLK1_0",
|
||||
"CLK_PMV_IMUX32_0",
|
||||
"CLK_PMV_IMUX9_0",
|
||||
"CLK_FEED_EE2A1",
|
||||
"CLK_FEED_SE2A3",
|
||||
"CLK_FEED_SW2A0",
|
||||
"CLK_FEED_NE2A2",
|
||||
"CLK_FEED_R_CK_GCLK17",
|
||||
"CLK_FEED_CK_BUFG_CASC20",
|
||||
"CLK_FEED_WW4C2",
|
||||
"CLK_FEED_NE4BEG1",
|
||||
"CLK_FEED_CK_GCLK12",
|
||||
"CLK_FEED_R_CK_GCLK23",
|
||||
"CLK_FEED_NW2A1",
|
||||
"CLK_FEED_EE4B0",
|
||||
"CLK_FEED_NE4C2",
|
||||
"CLK_PMV_IMUX10_0",
|
||||
"CLK_FEED_R_CK_GCLK15",
|
||||
"CLK_FEED_WW4B0",
|
||||
"CLK_PMV_LOGIC_OUTS9_0",
|
||||
"CLK_FEED_CK_BUFG_CASC19",
|
||||
"CLK_PMV_BYP2_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC6",
|
||||
"CLK_FEED_R_CK_GCLK20",
|
||||
"CLK_PMV_LOGIC_OUTS2_0",
|
||||
"CLK_FEED_WW2END1",
|
||||
"CLK_FEED_R_CK_BUFG_CASC3",
|
||||
"CLK_PMV_LOGIC_OUTS7_0",
|
||||
"CLK_FEED_CK_BUFG_CASC25",
|
||||
"CLK_PMV_FAN6_0",
|
||||
"CLK_PMV_IMUX37_0",
|
||||
"CLK_FEED_NW2A3",
|
||||
"CLK_FEED_R_CK_GCLK1",
|
||||
"CLK_FEED_WR1END0",
|
||||
"CLK_FEED_EE4A3",
|
||||
"CLK_FEED_R_CK_GCLK10",
|
||||
"CLK_FEED_R_CK_BUFG_CASC17",
|
||||
"CLK_FEED_NW2A2",
|
||||
"CLK_PMV_IMUX4_0",
|
||||
"CLK_FEED_LH4",
|
||||
"CLK_FEED_EE2A0",
|
||||
"CLK_PMV_IMUX35_0",
|
||||
"CLK_PMV_IMUX16_0",
|
||||
"CLK_FEED_ER1BEG2",
|
||||
"CLK_FEED_ER1BEG3",
|
||||
"CLK_FEED_WW4A0",
|
||||
"CLK_FEED_CK_BUFG_CASC18",
|
||||
"CLK_FEED_WR1END3",
|
||||
"CLK_PMVIOB_ODIV4",
|
||||
"CLK_FEED_LH1",
|
||||
"CLK_FEED_EE2A3",
|
||||
"CLK_FEED_NW4A3",
|
||||
"CLK_FEED_WW2END3",
|
||||
"CLK_FEED_CK_BUFG_CASC27",
|
||||
"CLK_FEED_SE4C3",
|
||||
"CLK_PMV_IMUX23_0",
|
||||
"CLK_PMV_IMUX38_0",
|
||||
"CLK_PMV_IMUX12_0",
|
||||
"CLK_FEED_CK_BUFG_CASC1",
|
||||
"CLK_FEED_NW4END2",
|
||||
"CLK_FEED_EE4C0",
|
||||
"CLK_FEED_CK_GCLK10",
|
||||
"CLK_FEED_R_CK_GCLK30",
|
||||
"CLK_FEED_WL1END3",
|
||||
"CLK_FEED_NW2A0",
|
||||
"CLK_FEED_ER1BEG0",
|
||||
"CLK_FEED_NW4A0",
|
||||
"CLK_FEED_WW4A1",
|
||||
"CLK_FEED_R_CK_BUFG_CASC23",
|
||||
"CLK_FEED_CK_BUFG_CASC15",
|
||||
"CLK_FEED_LH2",
|
||||
"CLK_FEED_SW2A2",
|
||||
"CLK_PMV_BYP6_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC2",
|
||||
"CLK_PMV_IMUX3_0",
|
||||
"CLK_FEED_CK_GCLK31",
|
||||
"CLK_FEED_CK_GCLK18",
|
||||
"CLK_PMVIOB_ODIV2",
|
||||
"CLK_FEED_R_CK_GCLK3",
|
||||
"CLK_FEED_LH6",
|
||||
"CLK_FEED_CK_GCLK4",
|
||||
"CLK_FEED_R_CK_GCLK2",
|
||||
"CLK_PMV_IMUX21_0",
|
||||
"CLK_FEED_NW4END3",
|
||||
"CLK_FEED_NE4C1",
|
||||
"CLK_FEED_CK_BUFG_CASC31",
|
||||
"CLK_FEED_R_CK_GCLK7",
|
||||
"CLK_FEED_WW2A1",
|
||||
"CLK_FEED_R_CK_GCLK16",
|
||||
"CLK_PMV_IMUX33_0",
|
||||
"CLK_PMV_IMUX18_0",
|
||||
"CLK_FEED_SE4BEG0",
|
||||
"CLK_FEED_WL1END2",
|
||||
"CLK_FEED_NW4END1",
|
||||
"CLK_FEED_NW4END0",
|
||||
"CLK_PMV_LOGIC_OUTS11_0",
|
||||
"CLK_FEED_SE2A0",
|
||||
"CLK_FEED_CK_GCLK5",
|
||||
"CLK_FEED_CK_BUFG_CASC4",
|
||||
"CLK_FEED_WR1END2",
|
||||
"CLK_FEED_SW4END3",
|
||||
"CLK_FEED_WW4END0",
|
||||
"CLK_PMV_CTRL1_0",
|
||||
"CLK_PMV_LOGIC_OUTS21_0",
|
||||
"CLK_FEED_EE4B1",
|
||||
"CLK_FEED_SW4A1",
|
||||
"CLK_FEED_CK_GCLK28",
|
||||
"CLK_FEED_NE4C3",
|
||||
"CLK_FEED_CK_BUFG_CASC17",
|
||||
"CLK_FEED_CK_GCLK23",
|
||||
"CLK_PMV_IMUX19_0",
|
||||
"CLK_FEED_R_CK_GCLK18",
|
||||
"CLK_FEED_EE2A2",
|
||||
"CLK_FEED_R_CK_GCLK19",
|
||||
"CLK_FEED_CK_BUFG_CASC6",
|
||||
"CLK_FEED_CK_BUFG_CASC16",
|
||||
"CLK_FEED_NE2A0",
|
||||
"CLK_PMV_LOGIC_OUTS0_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC15",
|
||||
"CLK_FEED_R_CK_BUFG_CASC10",
|
||||
"CLK_FEED_R_CK_BUFG_CASC8",
|
||||
"CLK_PMV_IMUX6_0",
|
||||
"CLK_PMV_IMUX39_0",
|
||||
"CLK_FEED_SE2A2",
|
||||
"CLK_FEED_R_CK_GCLK22",
|
||||
"CLK_FEED_SW2A3",
|
||||
"CLK_FEED_EE4A0",
|
||||
"CLK_FEED_CK_GCLK30",
|
||||
"CLK_PMV_CLK0_0",
|
||||
"CLK_FEED_EL1BEG3",
|
||||
"CLK_FEED_WW4C1",
|
||||
"CLK_PMV_FAN4_0",
|
||||
"CLK_FEED_R_CK_GCLK26",
|
||||
"CLK_PMV_LOGIC_OUTS22_0",
|
||||
"CLK_FEED_CK_BUFG_CASC28",
|
||||
"CLK_FEED_EL1BEG0",
|
||||
"CLK_PMV_IMUX47_0",
|
||||
"CLK_FEED_R_CK_GCLK31",
|
||||
"CLK_PMV_LOGIC_OUTS19_0",
|
||||
"CLK_PMV_IMUX30_0",
|
||||
"CLK_PMV_IMUX27_0",
|
||||
"CLK_FEED_CK_BUFG_CASC24",
|
||||
"CLK_FEED_EE4C2",
|
||||
"CLK_FEED_R_CK_GCLK9",
|
||||
"CLK_FEED_R_CK_BUFG_CASC12",
|
||||
"CLK_PMV_IMUX14_0",
|
||||
"CLK_FEED_WW4B3",
|
||||
"CLK_FEED_CK_BUFG_CASC30",
|
||||
"CLK_FEED_CK_BUFG_CASC14",
|
||||
"CLK_PMV_BYP7_0",
|
||||
"CLK_FEED_EL1BEG2",
|
||||
"CLK_PMVIOB_A0",
|
||||
"CLK_FEED_CK_BUFG_CASC29",
|
||||
"CLK_FEED_CK_GCLK16",
|
||||
"CLK_FEED_R_CK_GCLK14",
|
||||
"CLK_FEED_WW4B1"
|
||||
],
|
||||
"tile_type": "CLK_PMVIOB",
|
||||
"sites": []
|
||||
}
|
||||
"wires": [
|
||||
"CLK_FEED_NE2A0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC28",
|
||||
"CLK_FEED_CK_GCLK19",
|
||||
"CLK_FEED_ER1BEG3",
|
||||
"CLK_FEED_CK_BUFG_CASC29",
|
||||
"CLK_FEED_R_CK_GCLK18",
|
||||
"CLK_FEED_R_CK_GCLK31",
|
||||
"CLK_PMV_CLK1_0",
|
||||
"CLK_FEED_CK_BUFG_CASC1",
|
||||
"CLK_FEED_R_CK_GCLK6",
|
||||
"CLK_FEED_LH7",
|
||||
"CLK_FEED_CK_BUFG_CASC3",
|
||||
"CLK_FEED_WW4B2",
|
||||
"CLK_PMVIOB_ODIV4",
|
||||
"CLK_FEED_LH12",
|
||||
"CLK_FEED_R_CK_BUFG_CASC14",
|
||||
"CLK_FEED_EE4A3",
|
||||
"CLK_FEED_CK_BUFG_CASC13",
|
||||
"CLK_PMV_IMUX28_0",
|
||||
"CLK_PMV_IMUX24_0",
|
||||
"CLK_FEED_ER1BEG0",
|
||||
"CLK_PMVIOB_ODIV2",
|
||||
"CLK_PMV_IMUX44_0",
|
||||
"CLK_FEED_SW4END3",
|
||||
"CLK_FEED_WL1END0",
|
||||
"CLK_FEED_SW2A0",
|
||||
"CLK_PMV_IMUX15_0",
|
||||
"CLK_PMV_IMUX43_0",
|
||||
"CLK_PMV_FAN0_0",
|
||||
"CLK_FEED_R_CK_GCLK13",
|
||||
"CLK_PMV_FAN1_0",
|
||||
"CLK_FEED_CK_BUFG_CASC26",
|
||||
"CLK_FEED_SE4BEG1",
|
||||
"CLK_FEED_CK_BUFG_CASC7",
|
||||
"CLK_PMV_IMUX11_0",
|
||||
"CLK_PMV_LOGIC_OUTS12_0",
|
||||
"CLK_FEED_CK_BUFG_CASC5",
|
||||
"CLK_FEED_CK_GCLK18",
|
||||
"CLK_PMV_BYP0_0",
|
||||
"CLK_FEED_WW4A3",
|
||||
"CLK_FEED_R_CK_BUFG_CASC10",
|
||||
"CLK_FEED_WW4C2",
|
||||
"CLK_FEED_NW4END3",
|
||||
"CLK_FEED_CK_GCLK27",
|
||||
"CLK_PMV_IMUX33_0",
|
||||
"CLK_FEED_R_CK_GCLK3",
|
||||
"CLK_FEED_CK_BUFG_CASC21",
|
||||
"CLK_FEED_WW2END0",
|
||||
"CLK_FEED_WW2A1",
|
||||
"CLK_PMV_LOGIC_OUTS18_0",
|
||||
"CLK_PMV_IMUX26_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC22",
|
||||
"CLK_PMV_LOGIC_OUTS3_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC0",
|
||||
"CLK_FEED_CK_GCLK12",
|
||||
"CLK_FEED_EE4A2",
|
||||
"CLK_FEED_EE4B0",
|
||||
"CLK_FEED_WW2A2",
|
||||
"CLK_FEED_CK_BUFG_CASC10",
|
||||
"CLK_FEED_CK_BUFG_CASC12",
|
||||
"CLK_FEED_R_CK_BUFG_CASC25",
|
||||
"CLK_FEED_EE4A1",
|
||||
"CLK_PMV_LOGIC_OUTS23_0",
|
||||
"CLK_PMV_IMUX29_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC17",
|
||||
"CLK_PMV_LOGIC_OUTS5_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC30",
|
||||
"CLK_PMV_IMUX31_0",
|
||||
"CLK_FEED_CK_GCLK15",
|
||||
"CLK_PMVIOB_EN",
|
||||
"CLK_FEED_R_CK_BUFG_CASC26",
|
||||
"CLK_FEED_WW2END1",
|
||||
"CLK_FEED_ER1BEG1",
|
||||
"CLK_FEED_EL1BEG0",
|
||||
"CLK_PMV_LOGIC_OUTS1_0",
|
||||
"CLK_PMV_LOGIC_OUTS21_0",
|
||||
"CLK_FEED_NE4C3",
|
||||
"CLK_FEED_WW4C0",
|
||||
"CLK_PMV_IMUX20_0",
|
||||
"CLK_PMV_BYP4_0",
|
||||
"CLK_FEED_CK_GCLK24",
|
||||
"CLK_FEED_NE2A2",
|
||||
"CLK_FEED_SE4BEG3",
|
||||
"CLK_PMV_LOGIC_OUTS16_0",
|
||||
"CLK_PMV_IMUX16_0",
|
||||
"CLK_FEED_CK_BUFG_CASC4",
|
||||
"CLK_PMV_IMUX9_0",
|
||||
"CLK_FEED_CK_GCLK23",
|
||||
"CLK_FEED_CK_BUFG_CASC20",
|
||||
"CLK_FEED_R_CK_GCLK12",
|
||||
"CLK_FEED_R_CK_BUFG_CASC27",
|
||||
"CLK_FEED_SE4C3",
|
||||
"CLK_FEED_CK_GCLK22",
|
||||
"CLK_FEED_NW4A2",
|
||||
"CLK_FEED_R_CK_GCLK9",
|
||||
"CLK_FEED_CK_GCLK17",
|
||||
"CLK_PMV_BYP7_0",
|
||||
"CLK_FEED_CK_BUFG_CASC6",
|
||||
"CLK_FEED_MONITOR_P",
|
||||
"CLK_FEED_NW2A2",
|
||||
"CLK_FEED_EE4BEG1",
|
||||
"CLK_FEED_R_CK_GCLK14",
|
||||
"CLK_FEED_EE4C0",
|
||||
"CLK_PMV_IMUX2_0",
|
||||
"CLK_FEED_EE4BEG3",
|
||||
"CLK_FEED_NE2A1",
|
||||
"CLK_FEED_WL1END3",
|
||||
"CLK_FEED_CK_GCLK28",
|
||||
"CLK_PMV_IMUX35_0",
|
||||
"CLK_PMV_LOGIC_OUTS7_0",
|
||||
"CLK_FEED_WW4B1",
|
||||
"CLK_FEED_SW4END0",
|
||||
"CLK_FEED_WW4END1",
|
||||
"CLK_FEED_R_CK_GCLK17",
|
||||
"CLK_FEED_R_CK_BUFG_CASC11",
|
||||
"CLK_FEED_WW4C1",
|
||||
"CLK_FEED_EL1BEG3",
|
||||
"CLK_PMV_IMUX17_0",
|
||||
"CLK_FEED_SE2A3",
|
||||
"CLK_FEED_R_CK_GCLK22",
|
||||
"CLK_FEED_NE4C0",
|
||||
"CLK_FEED_WW2A3",
|
||||
"CLK_FEED_NW4END1",
|
||||
"CLK_PMV_IMUX8_0",
|
||||
"CLK_FEED_SE2A2",
|
||||
"CLK_FEED_EE4B2",
|
||||
"CLK_FEED_R_CK_GCLK29",
|
||||
"CLK_FEED_WW2END3",
|
||||
"CLK_FEED_LH4",
|
||||
"CLK_FEED_WL1END2",
|
||||
"CLK_FEED_CK_GCLK2",
|
||||
"CLK_FEED_R_CK_GCLK25",
|
||||
"CLK_PMV_FAN3_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC13",
|
||||
"CLK_FEED_CK_BUFG_CASC27",
|
||||
"CLK_FEED_NW2A1",
|
||||
"CLK_FEED_SW4A3",
|
||||
"CLK_FEED_CK_BUFG_CASC31",
|
||||
"CLK_PMV_BYP3_0",
|
||||
"CLK_FEED_CK_GCLK1",
|
||||
"CLK_FEED_LH1",
|
||||
"CLK_FEED_CK_GCLK14",
|
||||
"CLK_FEED_R_CK_GCLK2",
|
||||
"CLK_FEED_R_CK_BUFG_CASC2",
|
||||
"CLK_PMV_CLK0_0",
|
||||
"CLK_FEED_WR1END0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC20",
|
||||
"CLK_FEED_NE4C1",
|
||||
"CLK_FEED_CK_GCLK16",
|
||||
"CLK_PMV_FAN2_0",
|
||||
"CLK_FEED_R_CK_GCLK5",
|
||||
"CLK_FEED_SE4C0",
|
||||
"CLK_FEED_EL1BEG2",
|
||||
"CLK_FEED_EL1BEG1",
|
||||
"CLK_FEED_EE4B1",
|
||||
"CLK_FEED_CK_BUFG_CASC22",
|
||||
"CLK_PMV_IMUX40_0",
|
||||
"CLK_FEED_WR1END1",
|
||||
"CLK_FEED_NW4END0",
|
||||
"CLK_PMV_IMUX42_0",
|
||||
"CLK_FEED_EE2BEG1",
|
||||
"CLK_FEED_R_CK_GCLK23",
|
||||
"CLK_PMVIOB_A0",
|
||||
"CLK_FEED_R_CK_GCLK1",
|
||||
"CLK_FEED_LH2",
|
||||
"CLK_FEED_SW2A2",
|
||||
"CLK_FEED_ER1BEG2",
|
||||
"CLK_FEED_WL1END1",
|
||||
"CLK_PMV_IMUX47_0",
|
||||
"CLK_FEED_NW4A1",
|
||||
"CLK_PMV_BYP1_0",
|
||||
"CLK_PMV_IMUX5_0",
|
||||
"CLK_FEED_SW4A2",
|
||||
"CLK_FEED_CK_GCLK10",
|
||||
"CLK_FEED_CK_BUFG_CASC14",
|
||||
"CLK_FEED_CK_BUFG_CASC28",
|
||||
"CLK_PMV_FAN7_0",
|
||||
"CLK_FEED_CK_BUFG_CASC18",
|
||||
"CLK_FEED_R_CK_GCLK24",
|
||||
"CLK_FEED_EE2A1",
|
||||
"CLK_FEED_R_CK_BUFG_CASC15",
|
||||
"CLK_PMV_LOGIC_OUTS10_0",
|
||||
"CLK_FEED_SW2A1",
|
||||
"CLK_FEED_CK_BUFG_CASC8",
|
||||
"CLK_PMV_IMUX45_0",
|
||||
"CLK_FEED_CK_BUFG_CASC2",
|
||||
"CLK_FEED_R_CK_BUFG_CASC8",
|
||||
"CLK_PMV_BYP2_0",
|
||||
"CLK_PMV_IMUX14_0",
|
||||
"CLK_FEED_R_CK_GCLK0",
|
||||
"CLK_FEED_WW4B3",
|
||||
"CLK_PMV_IMUX7_0",
|
||||
"CLK_FEED_CK_GCLK3",
|
||||
"CLK_FEED_LH3",
|
||||
"CLK_PMV_IMUX6_0",
|
||||
"CLK_FEED_SE2A0",
|
||||
"CLK_FEED_NE4C2",
|
||||
"CLK_FEED_WW4C3",
|
||||
"CLK_PMV_IMUX38_0",
|
||||
"CLK_PMV_FAN6_0",
|
||||
"CLK_FEED_EE4B3",
|
||||
"CLK_FEED_NW4A0",
|
||||
"CLK_FEED_CK_BUFG_CASC25",
|
||||
"CLK_FEED_R_CK_GCLK20",
|
||||
"CLK_FEED_EE2A3",
|
||||
"CLK_FEED_R_CK_GCLK28",
|
||||
"CLK_FEED_LH11",
|
||||
"CLK_FEED_WW4B0",
|
||||
"CLK_PMV_IMUX30_0",
|
||||
"CLK_PMV_FAN4_0",
|
||||
"CLK_FEED_CK_GCLK4",
|
||||
"CLK_FEED_CK_GCLK13",
|
||||
"CLK_FEED_WW2END2",
|
||||
"CLK_FEED_SW4END2",
|
||||
"CLK_PMV_LOGIC_OUTS4_0",
|
||||
"CLK_PMV_LOGIC_OUTS6_0",
|
||||
"CLK_FEED_NW2A0",
|
||||
"CLK_FEED_R_CK_GCLK30",
|
||||
"CLK_FEED_R_CK_BUFG_CASC1",
|
||||
"CLK_FEED_CK_GCLK25",
|
||||
"CLK_PMV_IMUX1_0",
|
||||
"CLK_FEED_CK_BUFG_CASC19",
|
||||
"CLK_PMV_IMUX34_0",
|
||||
"CLK_FEED_WW4A2",
|
||||
"CLK_FEED_R_CK_BUFG_CASC6",
|
||||
"CLK_PMV_LOGIC_OUTS17_0",
|
||||
"CLK_PMV_LOGIC_OUTS9_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC29",
|
||||
"CLK_FEED_SW4END1",
|
||||
"CLK_FEED_LH10",
|
||||
"CLK_FEED_CK_BUFG_CASC0",
|
||||
"CLK_PMV_IMUX21_0",
|
||||
"CLK_FEED_NE4BEG3",
|
||||
"CLK_FEED_R_CK_GCLK26",
|
||||
"CLK_PMV_IMUX41_0",
|
||||
"CLK_PMV_IMUX46_0",
|
||||
"CLK_PMV_IMUX25_0",
|
||||
"CLK_PMV_IMUX39_0",
|
||||
"CLK_FEED_CK_GCLK7",
|
||||
"CLK_FEED_CK_BUFG_CASC23",
|
||||
"CLK_FEED_R_CK_BUFG_CASC16",
|
||||
"CLK_FEED_EE2BEG0",
|
||||
"CLK_FEED_CK_GCLK26",
|
||||
"CLK_FEED_CK_BUFG_CASC15",
|
||||
"CLK_FEED_SW4A1",
|
||||
"CLK_PMVIOB_O",
|
||||
"CLK_FEED_WW4A0",
|
||||
"CLK_PMV_IMUX22_0",
|
||||
"CLK_PMV_LOGIC_OUTS11_0",
|
||||
"CLK_PMV_BYP5_0",
|
||||
"CLK_PMV_LOGIC_OUTS15_0",
|
||||
"CLK_FEED_NE2A3",
|
||||
"CLK_FEED_CK_BUFG_CASC17",
|
||||
"CLK_FEED_CK_GCLK21",
|
||||
"CLK_PMV_LOGIC_OUTS0_0",
|
||||
"CLK_FEED_NE4BEG0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC23",
|
||||
"CLK_FEED_NE4BEG1",
|
||||
"CLK_PMV_LOGIC_OUTS19_0",
|
||||
"CLK_FEED_WW4END0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC12",
|
||||
"CLK_FEED_SE4BEG2",
|
||||
"CLK_FEED_EE2BEG3",
|
||||
"CLK_FEED_R_CK_GCLK7",
|
||||
"CLK_PMV_IMUX4_0",
|
||||
"CLK_FEED_CK_BUFG_CASC30",
|
||||
"CLK_FEED_R_CK_GCLK8",
|
||||
"CLK_FEED_WW4A1",
|
||||
"CLK_FEED_EE4BEG0",
|
||||
"CLK_FEED_WR1END2",
|
||||
"CLK_FEED_CK_BUFG_CASC24",
|
||||
"CLK_FEED_R_CK_GCLK16",
|
||||
"CLK_FEED_R_CK_GCLK10",
|
||||
"CLK_FEED_CK_BUFG_CASC16",
|
||||
"CLK_FEED_R_CK_BUFG_CASC5",
|
||||
"CLK_FEED_CK_GCLK5",
|
||||
"CLK_FEED_R_CK_BUFG_CASC18",
|
||||
"CLK_PMVIOB_A1",
|
||||
"CLK_FEED_NE4BEG2",
|
||||
"CLK_FEED_R_CK_GCLK11",
|
||||
"CLK_FEED_R_CK_GCLK4",
|
||||
"CLK_PMV_LOGIC_OUTS20_0",
|
||||
"CLK_PMV_IMUX12_0",
|
||||
"CLK_PMV_IMUX37_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC7",
|
||||
"CLK_PMV_IMUX18_0",
|
||||
"CLK_FEED_SE4C1",
|
||||
"CLK_FEED_CK_GCLK20",
|
||||
"CLK_PMV_LOGIC_OUTS8_0",
|
||||
"CLK_FEED_NW4END2",
|
||||
"CLK_FEED_EE4BEG2",
|
||||
"CLK_FEED_CK_GCLK30",
|
||||
"CLK_FEED_SE2A1",
|
||||
"CLK_FEED_LH6",
|
||||
"CLK_FEED_CK_GCLK29",
|
||||
"CLK_FEED_R_CK_GCLK27",
|
||||
"CLK_FEED_EE4C1",
|
||||
"CLK_FEED_SW4A0",
|
||||
"CLK_FEED_CK_GCLK9",
|
||||
"CLK_FEED_CK_BUFG_CASC11",
|
||||
"CLK_FEED_CK_GCLK8",
|
||||
"CLK_FEED_R_CK_BUFG_CASC9",
|
||||
"CLK_FEED_R_CK_BUFG_CASC3",
|
||||
"CLK_FEED_WW4END2",
|
||||
"CLK_FEED_CK_GCLK6",
|
||||
"CLK_FEED_EE2A2",
|
||||
"CLK_PMV_LOGIC_OUTS2_0",
|
||||
"CLK_PMV_LOGIC_OUTS14_0",
|
||||
"CLK_FEED_EE4C3",
|
||||
"CLK_FEED_NW2A3",
|
||||
"CLK_PMV_CTRL0_0",
|
||||
"CLK_PMV_LOGIC_OUTS22_0",
|
||||
"CLK_PMV_IMUX0_0",
|
||||
"CLK_FEED_EE2A0",
|
||||
"CLK_PMV_FAN5_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC24",
|
||||
"CLK_PMV_BYP6_0",
|
||||
"CLK_FEED_R_CK_GCLK19",
|
||||
"CLK_FEED_EE2BEG2",
|
||||
"CLK_FEED_R_CK_BUFG_CASC19",
|
||||
"CLK_FEED_WW4END3",
|
||||
"CLK_FEED_CK_GCLK31",
|
||||
"CLK_FEED_SW2A3",
|
||||
"CLK_PMV_IMUX23_0",
|
||||
"CLK_PMV_IMUX19_0",
|
||||
"CLK_PMV_IMUX36_0",
|
||||
"CLK_FEED_SE4C2",
|
||||
"CLK_FEED_EE4C2",
|
||||
"CLK_PMV_IMUX13_0",
|
||||
"CLK_FEED_SE4BEG0",
|
||||
"CLK_PMV_IMUX27_0",
|
||||
"CLK_FEED_LH9",
|
||||
"CLK_FEED_R_CK_GCLK15",
|
||||
"CLK_PMV_IMUX3_0",
|
||||
"CLK_PMV_CTRL1_0",
|
||||
"CLK_FEED_LH5",
|
||||
"CLK_PMV_LOGIC_OUTS13_0",
|
||||
"CLK_FEED_NW4A3",
|
||||
"CLK_PMV_IMUX10_0",
|
||||
"CLK_PMV_IMUX32_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC4",
|
||||
"CLK_FEED_R_CK_BUFG_CASC21",
|
||||
"CLK_FEED_CK_GCLK0",
|
||||
"CLK_FEED_MONITOR_N",
|
||||
"CLK_FEED_CK_GCLK11",
|
||||
"CLK_FEED_R_CK_BUFG_CASC31",
|
||||
"CLK_FEED_WW2A0",
|
||||
"CLK_FEED_EE4A0",
|
||||
"CLK_FEED_CK_BUFG_CASC9",
|
||||
"CLK_FEED_R_CK_GCLK21",
|
||||
"CLK_FEED_WR1END3",
|
||||
"CLK_FEED_LH8"
|
||||
],
|
||||
"pips": {},
|
||||
"tile_type": "CLK_PMVIOB",
|
||||
"sites": []
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,71 +1,71 @@
|
|||
{
|
||||
"pips": {},
|
||||
"wires": [
|
||||
"CLK_TERM_R_GCLK17",
|
||||
"CLK_TERM_R_GCLK20",
|
||||
"CLK_TERM_R_GCLK21",
|
||||
"CLK_TERM_R_GCLK16",
|
||||
"CLK_TERM_R_GCLK12",
|
||||
"CLK_TERM_R_GCLK5",
|
||||
"CLK_TERM_R_GCLK26",
|
||||
"CLK_TERM_R_GCLK4",
|
||||
"CLK_TERM_R_GCLK8",
|
||||
"CLK_TERM_R_GCLK10",
|
||||
"CLK_TERM_GCLK26",
|
||||
"CLK_TERM_GCLK30",
|
||||
"CLK_TERM_R_GCLK19",
|
||||
"CLK_TERM_R_GCLK25",
|
||||
"CLK_TERM_R_GCLK1",
|
||||
"CLK_TERM_R_GCLK3",
|
||||
"CLK_TERM_GCLK13",
|
||||
"CLK_TERM_GCLK3",
|
||||
"CLK_TERM_GCLK23",
|
||||
"CLK_TERM_GCLK14",
|
||||
"CLK_TERM_GCLK18",
|
||||
"CLK_TERM_GCLK22",
|
||||
"CLK_TERM_GCLK8",
|
||||
"CLK_TERM_GCLK15",
|
||||
"CLK_TERM_GCLK31",
|
||||
"CLK_TERM_GCLK0",
|
||||
"CLK_TERM_R_GCLK28",
|
||||
"CLK_TERM_R_GCLK11",
|
||||
"CLK_TERM_R_GCLK13",
|
||||
"CLK_TERM_R_GCLK14",
|
||||
"CLK_TERM_GCLK21",
|
||||
"CLK_TERM_R_GCLK29",
|
||||
"CLK_TERM_R_GCLK7",
|
||||
"CLK_TERM_GCLK27",
|
||||
"CLK_TERM_GCLK4",
|
||||
"CLK_TERM_GCLK7",
|
||||
"CLK_TERM_GCLK6",
|
||||
"CLK_TERM_GCLK5",
|
||||
"CLK_TERM_R_GCLK15",
|
||||
"CLK_TERM_R_GCLK22",
|
||||
"CLK_TERM_GCLK29",
|
||||
"CLK_TERM_R_GCLK18",
|
||||
"CLK_TERM_GCLK12",
|
||||
"CLK_TERM_GCLK9",
|
||||
"CLK_TERM_GCLK20",
|
||||
"CLK_TERM_GCLK19",
|
||||
"CLK_TERM_GCLK2",
|
||||
"CLK_TERM_GCLK24",
|
||||
"CLK_TERM_R_GCLK6",
|
||||
"CLK_TERM_R_GCLK31",
|
||||
"CLK_TERM_GCLK16",
|
||||
"CLK_TERM_R_GCLK0",
|
||||
"CLK_TERM_GCLK1",
|
||||
"CLK_TERM_GCLK25",
|
||||
"CLK_TERM_R_GCLK23",
|
||||
"CLK_TERM_R_GCLK24",
|
||||
"CLK_TERM_R_GCLK27",
|
||||
"CLK_TERM_R_GCLK30",
|
||||
"CLK_TERM_R_GCLK9",
|
||||
"CLK_TERM_GCLK11",
|
||||
"CLK_TERM_R_GCLK2",
|
||||
"CLK_TERM_GCLK17",
|
||||
"CLK_TERM_GCLK10",
|
||||
"CLK_TERM_GCLK28"
|
||||
],
|
||||
"tile_type": "CLK_TERM",
|
||||
"sites": []
|
||||
}
|
||||
"wires": [
|
||||
"CLK_TERM_R_GCLK22",
|
||||
"CLK_TERM_GCLK29",
|
||||
"CLK_TERM_GCLK1",
|
||||
"CLK_TERM_R_GCLK21",
|
||||
"CLK_TERM_R_GCLK18",
|
||||
"CLK_TERM_GCLK16",
|
||||
"CLK_TERM_GCLK27",
|
||||
"CLK_TERM_R_GCLK13",
|
||||
"CLK_TERM_GCLK24",
|
||||
"CLK_TERM_GCLK11",
|
||||
"CLK_TERM_GCLK13",
|
||||
"CLK_TERM_R_GCLK19",
|
||||
"CLK_TERM_R_GCLK3",
|
||||
"CLK_TERM_GCLK5",
|
||||
"CLK_TERM_R_GCLK11",
|
||||
"CLK_TERM_GCLK20",
|
||||
"CLK_TERM_GCLK28",
|
||||
"CLK_TERM_R_GCLK28",
|
||||
"CLK_TERM_GCLK15",
|
||||
"CLK_TERM_GCLK23",
|
||||
"CLK_TERM_GCLK2",
|
||||
"CLK_TERM_R_GCLK14",
|
||||
"CLK_TERM_GCLK3",
|
||||
"CLK_TERM_R_GCLK24",
|
||||
"CLK_TERM_GCLK19",
|
||||
"CLK_TERM_R_GCLK8",
|
||||
"CLK_TERM_R_GCLK0",
|
||||
"CLK_TERM_GCLK10",
|
||||
"CLK_TERM_GCLK22",
|
||||
"CLK_TERM_R_GCLK9",
|
||||
"CLK_TERM_GCLK21",
|
||||
"CLK_TERM_GCLK7",
|
||||
"CLK_TERM_GCLK17",
|
||||
"CLK_TERM_GCLK12",
|
||||
"CLK_TERM_R_GCLK15",
|
||||
"CLK_TERM_R_GCLK6",
|
||||
"CLK_TERM_R_GCLK29",
|
||||
"CLK_TERM_R_GCLK7",
|
||||
"CLK_TERM_R_GCLK1",
|
||||
"CLK_TERM_R_GCLK23",
|
||||
"CLK_TERM_R_GCLK16",
|
||||
"CLK_TERM_R_GCLK4",
|
||||
"CLK_TERM_GCLK26",
|
||||
"CLK_TERM_R_GCLK30",
|
||||
"CLK_TERM_GCLK14",
|
||||
"CLK_TERM_GCLK30",
|
||||
"CLK_TERM_R_GCLK2",
|
||||
"CLK_TERM_R_GCLK25",
|
||||
"CLK_TERM_R_GCLK5",
|
||||
"CLK_TERM_R_GCLK20",
|
||||
"CLK_TERM_GCLK9",
|
||||
"CLK_TERM_GCLK6",
|
||||
"CLK_TERM_GCLK31",
|
||||
"CLK_TERM_R_GCLK10",
|
||||
"CLK_TERM_R_GCLK26",
|
||||
"CLK_TERM_R_GCLK17",
|
||||
"CLK_TERM_GCLK18",
|
||||
"CLK_TERM_R_GCLK12",
|
||||
"CLK_TERM_R_GCLK31",
|
||||
"CLK_TERM_GCLK4",
|
||||
"CLK_TERM_GCLK0",
|
||||
"CLK_TERM_GCLK25",
|
||||
"CLK_TERM_GCLK8",
|
||||
"CLK_TERM_R_GCLK27"
|
||||
],
|
||||
"pips": {},
|
||||
"tile_type": "CLK_TERM",
|
||||
"sites": []
|
||||
}
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -1,230 +1,230 @@
|
|||
{
|
||||
"pips": {},
|
||||
"wires": [
|
||||
"CMT_PMV_IMUX16",
|
||||
"CMT_PMV_LOGIC_OUTS17",
|
||||
"CMT_PMV_LOGIC_OUTS10",
|
||||
"CMT_PMV_IMUX29",
|
||||
"CMT_PMV_BYP1",
|
||||
"CMT_PMV_BYP0",
|
||||
"L_TERM_INT_PHASER_TO_IO_ICLKDIV",
|
||||
"CMT_PMV_LOGIC_OUTS7",
|
||||
"CMT_PMV_IMUX45",
|
||||
"CMT_PMV_LOGIC_OUTS13",
|
||||
"CMT_PMV_SW2A0",
|
||||
"CMT_PMV_LOGIC_OUTS11",
|
||||
"CMT_PMV_WW4C3",
|
||||
"CMT_PMV_NW2A3",
|
||||
"CMT_PMV_NE4BEG2",
|
||||
"CMT_PMV_SW4A3",
|
||||
"CMT_PMV_EE4C1",
|
||||
"CMT_PMV_EE4B2",
|
||||
"CMT_PMV_IMUX39",
|
||||
"CMT_PMV_SW2A1",
|
||||
"CMT_PMV_LOGIC_OUTS21",
|
||||
"CMT_PMV_WW2END3",
|
||||
"CMT_PMV_IMUX22",
|
||||
"CMT_PMV_LH5",
|
||||
"CMT_PMV_IMUX40",
|
||||
"CMT_PMV_SW4A2",
|
||||
"CMT_PMV_WW4A3",
|
||||
"CMT_PMV_NW2A0",
|
||||
"CMT_PMV_SE4C2",
|
||||
"CMT_PMV_NW4END0",
|
||||
"CMT_PMV_LH9",
|
||||
"CMT_PMV_LOGIC_OUTS1",
|
||||
"CMT_PMV_EE4A2",
|
||||
"CMT_PMV_SE2A2",
|
||||
"CMT_PMV_ER1BEG1",
|
||||
"CMT_PMV_NW4A2",
|
||||
"CMT_PMV_SE4C0",
|
||||
"CMT_PMV_ER1BEG2",
|
||||
"CMT_PMV_NW4A3",
|
||||
"CMT_PMV_NW4END3",
|
||||
"CMT_PMV_WW4B1",
|
||||
"CMT_PMV_EE2BEG1",
|
||||
"CMT_PMV_EE4BEG1",
|
||||
"CMT_PMV_WL1END0",
|
||||
"CMT_PMV_SE4BEG0",
|
||||
"CMT_PMV_SW4A1",
|
||||
"CMT_PMV_IMUX7",
|
||||
"CMT_PMV_SW4END0",
|
||||
"CMT_PMV_EE4C3",
|
||||
"CMT_PMV_IMUX43",
|
||||
"CMT_PMV_NW2A1",
|
||||
"CMT_PMV_IMUX8",
|
||||
"CMT_PMV_IMUX19",
|
||||
"CMT_PMV_LH1",
|
||||
"CMT_PMV_IMUX1",
|
||||
"CMT_PMV_WR1END3",
|
||||
"CMT_PMV_IMUX12",
|
||||
"CMT_PMV_SE4BEG2",
|
||||
"CMT_PMV_LH12",
|
||||
"CMT_PMV_IMUX10",
|
||||
"CMT_PMV_LOGIC_OUTS12",
|
||||
"CMT_PMV_WW4B0",
|
||||
"CMT_PMV_SE2A1",
|
||||
"CMT_PMV_IMUX21",
|
||||
"CMT_PMV_IMUX25",
|
||||
"CMT_PMV_EE4BEG2",
|
||||
"CMT_PMV_LOGIC_OUTS16",
|
||||
"CMT_PMV_LOGIC_OUTS19",
|
||||
"CMT_PMV_FAN4",
|
||||
"CMT_PMV_SW2A3",
|
||||
"L_TERM_INT_PHASER_TO_IO_OCLK1X_90",
|
||||
"CMT_PMV_LH10",
|
||||
"CMT_PMV_CTRL0",
|
||||
"CMT_PMV_IMUX20",
|
||||
"CMT_PMV_WW4B3",
|
||||
"CMT_PMV_IMUX4",
|
||||
"CMT_PMV_NE2A2",
|
||||
"CMT_PMV_LOGIC_OUTS5",
|
||||
"CMT_PMV_MONITOR_P",
|
||||
"CMT_PMV_CLK0",
|
||||
"CMT_PMV_LOGIC_OUTS14",
|
||||
"CMT_PMV_EE4B0",
|
||||
"CMT_PMV_WW4A2",
|
||||
"CMT_PMV_WW4END3",
|
||||
"CMT_PMV_LOGIC_OUTS23",
|
||||
"CMT_PMV_IMUX32",
|
||||
"CMT_PMV_IMUX42",
|
||||
"CMT_PMV_LH4",
|
||||
"CMT_PMV_LOGIC_OUTS2",
|
||||
"CMT_PMV_LH8",
|
||||
"CMT_PMV_SE4BEG1",
|
||||
"CMT_PMV_IMUX27",
|
||||
"CMT_PMV_LH2",
|
||||
"CMT_PMV_BYP3",
|
||||
"CMT_PMV_WW4B2",
|
||||
"CMT_PMV_FAN3",
|
||||
"CMT_PMV_FAN6",
|
||||
"CMT_PMV_EE4B3",
|
||||
"CMT_PMV_WW4C2",
|
||||
"CMT_PMV_ER1BEG0",
|
||||
"CMT_PMV_SE4C1",
|
||||
"CMT_PMV_FAN7",
|
||||
"CMT_PMV_MONITOR_N",
|
||||
"CMT_PMV_WW2A0",
|
||||
"CMT_PMV_EE4A1",
|
||||
"CMT_PMV_BYP5",
|
||||
"CMT_PMV_IMUX28",
|
||||
"CMT_PMV_IMUX15",
|
||||
"CMT_PMV_WW2A1",
|
||||
"CMT_PMV_WW4A0",
|
||||
"CMT_PMV_CTRL1",
|
||||
"CMT_PMV_IMUX3",
|
||||
"CMT_PMV_CLK1",
|
||||
"CMT_PMV_EE2A2",
|
||||
"CMT_PMV_WW2END2",
|
||||
"CMT_PMV_NE4C1",
|
||||
"CMT_PMV_NE2A3",
|
||||
"CMT_PMV_NE2A1",
|
||||
"CMT_PMV_IMUX37",
|
||||
"CMT_PMV_EE2BEG3",
|
||||
"CMT_PMV_LOGIC_OUTS6",
|
||||
"CMT_PMV_LOGIC_OUTS9",
|
||||
"CMT_PMV_LOGIC_OUTS4",
|
||||
"CMT_PMV_NE4BEG3",
|
||||
"CMT_PMV_WR1END0",
|
||||
"CMT_PMV_BYP6",
|
||||
"CMT_PMV_FAN0",
|
||||
"CMT_PMV_IMUX6",
|
||||
"CMT_PMV_WW4C1",
|
||||
"CMT_PMV_NW2A2",
|
||||
"CMT_PMV_SW2A2",
|
||||
"CMT_PMV_IMUX36",
|
||||
"CMT_PMV_SW4A0",
|
||||
"CMT_PMV_IMUX35",
|
||||
"CMT_PMV_FAN1",
|
||||
"CMT_PMV_IMUX11",
|
||||
"CMT_PMV_EE4BEG0",
|
||||
"CMT_PMV_EE2A3",
|
||||
"CMT_PMV_WW4C0",
|
||||
"CMT_PMV_NE4BEG1",
|
||||
"CMT_PMV_NW4END1",
|
||||
"CMT_PMV_IMUX38",
|
||||
"CMT_PMV_EE4A0",
|
||||
"CMT_PMV_NW4A0",
|
||||
"CMT_PMV_BYP4",
|
||||
"CMT_PMV_NW4END2",
|
||||
"CMT_PMV_EE2A1",
|
||||
"CMT_PMV_WW4END0",
|
||||
"CMT_PMV_WW4END2",
|
||||
"CMT_PMV_WL1END2",
|
||||
"CMT_PMV_SE4C3",
|
||||
"CMT_PMV_IMUX13",
|
||||
"CMT_PMV_WW2A2",
|
||||
"CMT_PMV_LOGIC_OUTS8",
|
||||
"CMT_PMV_EE4C2",
|
||||
"CMT_PMV_EL1BEG1",
|
||||
"CMT_PMV_LOGIC_OUTS0",
|
||||
"CMT_PMV_SW4END3",
|
||||
"CMT_PMV_IMUX2",
|
||||
"CMT_PMV_IMUX14",
|
||||
"CMT_PMV_EL1BEG0",
|
||||
"CMT_PMV_IMUX0",
|
||||
"L_TERM_INT_PHASER_TO_IO_OCLKDIV",
|
||||
"CMT_PMV_EE2BEG2",
|
||||
"CMT_PMV_IMUX47",
|
||||
"CMT_PMV_EE4BEG3",
|
||||
"CMT_PMV_IMUX34",
|
||||
"CMT_PMV_IMUX46",
|
||||
"CMT_PMV_WW4A1",
|
||||
"CMT_PMV_LOGIC_OUTS18",
|
||||
"CMT_PMV_WW2END1",
|
||||
"CMT_PMV_SE2A0",
|
||||
"CMT_PMV_WW4END1",
|
||||
"CMT_PMV_IMUX26",
|
||||
"CMT_PMV_NE4C3",
|
||||
"CMT_PMV_IMUX33",
|
||||
"CMT_PMV_EE4A3",
|
||||
"L_TERM_INT_PHASER_TO_IO_OCLK",
|
||||
"CMT_PMV_LH3",
|
||||
"CMT_PMV_WR1END2",
|
||||
"CMT_PMV_EE2BEG0",
|
||||
"CMT_PMV_BYP2",
|
||||
"CMT_PMV_NE4C0",
|
||||
"CMT_PMV_BYP7",
|
||||
"CMT_PMV_EE2A0",
|
||||
"CMT_PMV_WW2END0",
|
||||
"CMT_PMV_SW4END1",
|
||||
"CMT_PMV_NW4A1",
|
||||
"CMT_PMV_EE4B1",
|
||||
"CMT_PMV_ER1BEG3",
|
||||
"CMT_PMV_LH7",
|
||||
"CMT_PMV_NE4C2",
|
||||
"CMT_PMV_SW4END2",
|
||||
"CMT_PMV_IMUX31",
|
||||
"CMT_PMV_IMUX24",
|
||||
"CMT_PMV_FAN5",
|
||||
"CMT_PMV_LOGIC_OUTS22",
|
||||
"CMT_PMV_IMUX23",
|
||||
"CMT_PMV_FAN2",
|
||||
"CMT_PMV_LOGIC_OUTS3",
|
||||
"CMT_PMV_LOGIC_OUTS15",
|
||||
"CMT_PMV_EL1BEG2",
|
||||
"CMT_PMV_LOGIC_OUTS20",
|
||||
"CMT_PMV_WW2A3",
|
||||
"CMT_PMV_WL1END1",
|
||||
"CMT_PMV_EL1BEG3",
|
||||
"CMT_PMV_IMUX5",
|
||||
"CMT_PMV_IMUX9",
|
||||
"CMT_PMV_LH6",
|
||||
"CMT_PMV_WL1END3",
|
||||
"CMT_PMV_LH11",
|
||||
"CMT_PMV_NE2A0",
|
||||
"CMT_PMV_IMUX18",
|
||||
"CMT_PMV_IMUX17",
|
||||
"CMT_PMV_WR1END1",
|
||||
"CMT_PMV_NE4BEG0",
|
||||
"CMT_PMV_IMUX30",
|
||||
"CMT_PMV_IMUX44",
|
||||
"CMT_PMV_IMUX41",
|
||||
"L_TERM_INT_PHASER_TO_IO_ICLK",
|
||||
"CMT_PMV_EE4C0",
|
||||
"CMT_PMV_SE2A3",
|
||||
"CMT_PMV_SE4BEG3"
|
||||
],
|
||||
"tile_type": "CMT_PMV",
|
||||
"sites": []
|
||||
}
|
||||
"wires": [
|
||||
"CMT_PMV_LOGIC_OUTS0",
|
||||
"CMT_PMV_EE4C1",
|
||||
"CMT_PMV_IMUX19",
|
||||
"CMT_PMV_IMUX29",
|
||||
"CMT_PMV_LH2",
|
||||
"CMT_PMV_IMUX11",
|
||||
"L_TERM_INT_PHASER_TO_IO_OCLK1X_90",
|
||||
"CMT_PMV_WW4A2",
|
||||
"CMT_PMV_WW2A1",
|
||||
"CMT_PMV_WW2END2",
|
||||
"L_TERM_INT_PHASER_TO_IO_OCLKDIV",
|
||||
"CMT_PMV_BYP1",
|
||||
"CMT_PMV_WL1END3",
|
||||
"CMT_PMV_EE4A0",
|
||||
"CMT_PMV_NW4END0",
|
||||
"CMT_PMV_LOGIC_OUTS8",
|
||||
"CMT_PMV_LOGIC_OUTS1",
|
||||
"CMT_PMV_WL1END2",
|
||||
"CMT_PMV_SW2A3",
|
||||
"L_TERM_INT_PHASER_TO_IO_OCLK",
|
||||
"CMT_PMV_EE4C2",
|
||||
"CMT_PMV_IMUX39",
|
||||
"CMT_PMV_IMUX43",
|
||||
"CMT_PMV_LOGIC_OUTS14",
|
||||
"CMT_PMV_LOGIC_OUTS13",
|
||||
"CMT_PMV_IMUX0",
|
||||
"CMT_PMV_SW4END3",
|
||||
"CMT_PMV_ER1BEG3",
|
||||
"CMT_PMV_NW2A3",
|
||||
"CMT_PMV_WW4A3",
|
||||
"CMT_PMV_SW4A2",
|
||||
"CMT_PMV_LH10",
|
||||
"CMT_PMV_BYP4",
|
||||
"CMT_PMV_EE2BEG2",
|
||||
"CMT_PMV_EL1BEG3",
|
||||
"CMT_PMV_IMUX8",
|
||||
"CMT_PMV_SE4BEG3",
|
||||
"CMT_PMV_IMUX35",
|
||||
"CMT_PMV_IMUX10",
|
||||
"CMT_PMV_SW4END1",
|
||||
"CMT_PMV_WL1END1",
|
||||
"CMT_PMV_WW2END3",
|
||||
"CMT_PMV_WW4END1",
|
||||
"CMT_PMV_EE4B0",
|
||||
"CMT_PMV_SW4A1",
|
||||
"CMT_PMV_CTRL1",
|
||||
"CMT_PMV_CLK0",
|
||||
"CMT_PMV_IMUX31",
|
||||
"CMT_PMV_EE4A3",
|
||||
"CMT_PMV_SW2A1",
|
||||
"CMT_PMV_WW2END1",
|
||||
"CMT_PMV_NW4END1",
|
||||
"CMT_PMV_LH3",
|
||||
"CMT_PMV_LH7",
|
||||
"CMT_PMV_LOGIC_OUTS2",
|
||||
"CMT_PMV_LH9",
|
||||
"CMT_PMV_SE2A3",
|
||||
"CMT_PMV_IMUX34",
|
||||
"CMT_PMV_NE4C1",
|
||||
"CMT_PMV_FAN0",
|
||||
"CMT_PMV_LH11",
|
||||
"CMT_PMV_WW2A3",
|
||||
"CMT_PMV_IMUX1",
|
||||
"CMT_PMV_IMUX13",
|
||||
"CMT_PMV_EL1BEG2",
|
||||
"CMT_PMV_LOGIC_OUTS17",
|
||||
"CMT_PMV_BYP6",
|
||||
"CMT_PMV_SW4A0",
|
||||
"CMT_PMV_WW4C0",
|
||||
"CMT_PMV_IMUX21",
|
||||
"CMT_PMV_IMUX12",
|
||||
"CMT_PMV_NE4BEG3",
|
||||
"CMT_PMV_LH4",
|
||||
"CMT_PMV_BYP3",
|
||||
"CMT_PMV_IMUX4",
|
||||
"CMT_PMV_IMUX47",
|
||||
"CMT_PMV_NE2A0",
|
||||
"CMT_PMV_WW4A1",
|
||||
"CMT_PMV_LH1",
|
||||
"CMT_PMV_NW4A0",
|
||||
"CMT_PMV_IMUX41",
|
||||
"CMT_PMV_LOGIC_OUTS11",
|
||||
"CMT_PMV_IMUX26",
|
||||
"CMT_PMV_NE4C0",
|
||||
"CMT_PMV_LOGIC_OUTS18",
|
||||
"CMT_PMV_IMUX15",
|
||||
"CMT_PMV_IMUX44",
|
||||
"CMT_PMV_NW4A2",
|
||||
"CMT_PMV_WW4END3",
|
||||
"CMT_PMV_IMUX42",
|
||||
"CMT_PMV_LOGIC_OUTS15",
|
||||
"CMT_PMV_SE4C3",
|
||||
"CMT_PMV_EE4BEG0",
|
||||
"CMT_PMV_SW2A0",
|
||||
"CMT_PMV_IMUX23",
|
||||
"CMT_PMV_BYP0",
|
||||
"CMT_PMV_LOGIC_OUTS21",
|
||||
"CMT_PMV_NE2A3",
|
||||
"CMT_PMV_WW2END0",
|
||||
"CMT_PMV_FAN7",
|
||||
"CMT_PMV_EE2BEG0",
|
||||
"CMT_PMV_NE4BEG0",
|
||||
"CMT_PMV_IMUX27",
|
||||
"CMT_PMV_NW2A2",
|
||||
"CMT_PMV_LOGIC_OUTS12",
|
||||
"CMT_PMV_WW4B1",
|
||||
"CMT_PMV_NE4BEG2",
|
||||
"CMT_PMV_MONITOR_N",
|
||||
"CMT_PMV_WW4B3",
|
||||
"CMT_PMV_LOGIC_OUTS4",
|
||||
"CMT_PMV_WR1END1",
|
||||
"CMT_PMV_LH5",
|
||||
"CMT_PMV_WR1END0",
|
||||
"CMT_PMV_LH12",
|
||||
"CMT_PMV_IMUX46",
|
||||
"CMT_PMV_EE4B3",
|
||||
"CMT_PMV_EE4A2",
|
||||
"CMT_PMV_NE4C2",
|
||||
"CMT_PMV_WW4C1",
|
||||
"CMT_PMV_WW4C3",
|
||||
"CMT_PMV_IMUX9",
|
||||
"CMT_PMV_LOGIC_OUTS7",
|
||||
"CMT_PMV_WW4B2",
|
||||
"CMT_PMV_EE4C0",
|
||||
"CMT_PMV_SE4C2",
|
||||
"CMT_PMV_LH6",
|
||||
"CMT_PMV_SE4BEG1",
|
||||
"CMT_PMV_WW4B0",
|
||||
"CMT_PMV_IMUX24",
|
||||
"CMT_PMV_SW4END0",
|
||||
"CMT_PMV_IMUX14",
|
||||
"CMT_PMV_FAN2",
|
||||
"CMT_PMV_LOGIC_OUTS9",
|
||||
"CMT_PMV_IMUX3",
|
||||
"CMT_PMV_WW4C2",
|
||||
"L_TERM_INT_PHASER_TO_IO_ICLKDIV",
|
||||
"CMT_PMV_WR1END2",
|
||||
"CMT_PMV_IMUX45",
|
||||
"CMT_PMV_EE4A1",
|
||||
"CMT_PMV_IMUX28",
|
||||
"CMT_PMV_NW4END3",
|
||||
"CMT_PMV_EE2A0",
|
||||
"CMT_PMV_EL1BEG0",
|
||||
"CMT_PMV_WW4A0",
|
||||
"CMT_PMV_EE2A3",
|
||||
"CMT_PMV_FAN3",
|
||||
"CMT_PMV_ER1BEG2",
|
||||
"CMT_PMV_IMUX17",
|
||||
"CMT_PMV_LH8",
|
||||
"CMT_PMV_EE2BEG1",
|
||||
"CMT_PMV_EE4C3",
|
||||
"CMT_PMV_NE4C3",
|
||||
"CMT_PMV_FAN5",
|
||||
"CMT_PMV_LOGIC_OUTS3",
|
||||
"CMT_PMV_FAN4",
|
||||
"CMT_PMV_BYP7",
|
||||
"CMT_PMV_SE4BEG2",
|
||||
"CMT_PMV_WR1END3",
|
||||
"CMT_PMV_SW4A3",
|
||||
"CMT_PMV_IMUX16",
|
||||
"CMT_PMV_CLK1",
|
||||
"CMT_PMV_LOGIC_OUTS6",
|
||||
"CMT_PMV_EE2BEG3",
|
||||
"CMT_PMV_NE2A1",
|
||||
"CMT_PMV_SW4END2",
|
||||
"CMT_PMV_SE4BEG0",
|
||||
"CMT_PMV_SW2A2",
|
||||
"CMT_PMV_EE4BEG3",
|
||||
"CMT_PMV_WL1END0",
|
||||
"CMT_PMV_LOGIC_OUTS23",
|
||||
"CMT_PMV_NW2A0",
|
||||
"CMT_PMV_WW2A2",
|
||||
"CMT_PMV_LOGIC_OUTS20",
|
||||
"CMT_PMV_NE4BEG1",
|
||||
"CMT_PMV_LOGIC_OUTS19",
|
||||
"CMT_PMV_IMUX18",
|
||||
"CMT_PMV_EE4BEG2",
|
||||
"CMT_PMV_NW4A3",
|
||||
"CMT_PMV_LOGIC_OUTS16",
|
||||
"CMT_PMV_IMUX33",
|
||||
"CMT_PMV_LOGIC_OUTS10",
|
||||
"CMT_PMV_IMUX30",
|
||||
"CMT_PMV_SE2A2",
|
||||
"CMT_PMV_IMUX37",
|
||||
"CMT_PMV_NW4A1",
|
||||
"CMT_PMV_WW4END0",
|
||||
"L_TERM_INT_PHASER_TO_IO_ICLK",
|
||||
"CMT_PMV_EE2A1",
|
||||
"CMT_PMV_IMUX5",
|
||||
"CMT_PMV_IMUX38",
|
||||
"CMT_PMV_IMUX7",
|
||||
"CMT_PMV_NE2A2",
|
||||
"CMT_PMV_SE2A0",
|
||||
"CMT_PMV_ER1BEG1",
|
||||
"CMT_PMV_EE2A2",
|
||||
"CMT_PMV_IMUX40",
|
||||
"CMT_PMV_NW2A1",
|
||||
"CMT_PMV_IMUX20",
|
||||
"CMT_PMV_WW2A0",
|
||||
"CMT_PMV_SE4C1",
|
||||
"CMT_PMV_MONITOR_P",
|
||||
"CMT_PMV_LOGIC_OUTS5",
|
||||
"CMT_PMV_EE4B1",
|
||||
"CMT_PMV_IMUX22",
|
||||
"CMT_PMV_ER1BEG0",
|
||||
"CMT_PMV_SE2A1",
|
||||
"CMT_PMV_LOGIC_OUTS22",
|
||||
"CMT_PMV_IMUX25",
|
||||
"CMT_PMV_FAN6",
|
||||
"CMT_PMV_CTRL0",
|
||||
"CMT_PMV_BYP5",
|
||||
"CMT_PMV_EE4BEG1",
|
||||
"CMT_PMV_WW4END2",
|
||||
"CMT_PMV_IMUX36",
|
||||
"CMT_PMV_EL1BEG1",
|
||||
"CMT_PMV_NW4END2",
|
||||
"CMT_PMV_IMUX6",
|
||||
"CMT_PMV_IMUX2",
|
||||
"CMT_PMV_EE4B2",
|
||||
"CMT_PMV_IMUX32",
|
||||
"CMT_PMV_BYP2",
|
||||
"CMT_PMV_FAN1",
|
||||
"CMT_PMV_SE4C0"
|
||||
],
|
||||
"pips": {},
|
||||
"tile_type": "CMT_PMV",
|
||||
"sites": []
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,230 +1,230 @@
|
|||
{
|
||||
"pips": {},
|
||||
"wires": [
|
||||
"CMT_PMV_IMUX16",
|
||||
"CMT_PMV_LOGIC_OUTS17",
|
||||
"CMT_PMV_LOGIC_OUTS10",
|
||||
"CMT_PMV_IMUX29",
|
||||
"CMT_PMV_BYP1",
|
||||
"CMT_PMV_BYP0",
|
||||
"L_TERM_INT_PHASER_TO_IO_ICLKDIV",
|
||||
"CMT_PMV_LOGIC_OUTS7",
|
||||
"CMT_PMV_IMUX45",
|
||||
"CMT_PMV_LOGIC_OUTS13",
|
||||
"CMT_PMV_SW2A0",
|
||||
"CMT_PMV_LOGIC_OUTS11",
|
||||
"CMT_PMV_WW4C3",
|
||||
"CMT_PMV_NW2A3",
|
||||
"CMT_PMV_NE4BEG2",
|
||||
"CMT_PMV_SW4A3",
|
||||
"CMT_PMV_EE4C1",
|
||||
"CMT_PMV_EE4B2",
|
||||
"CMT_PMV_IMUX39",
|
||||
"CMT_PMV_SW2A1",
|
||||
"CMT_PMV_LOGIC_OUTS21",
|
||||
"CMT_PMV_WW2END3",
|
||||
"CMT_PMV_IMUX22",
|
||||
"CMT_PMV_LH5",
|
||||
"CMT_PMV_IMUX40",
|
||||
"CMT_PMV_SW4A2",
|
||||
"CMT_PMV_WW4A3",
|
||||
"CMT_PMV_NW2A0",
|
||||
"CMT_PMV_SE4C2",
|
||||
"CMT_PMV_NW4END0",
|
||||
"CMT_PMV_LH9",
|
||||
"CMT_PMV_LOGIC_OUTS1",
|
||||
"CMT_PMV_EE4A2",
|
||||
"CMT_PMV_SE2A2",
|
||||
"CMT_PMV_ER1BEG1",
|
||||
"CMT_PMV_NW4A2",
|
||||
"CMT_PMV_SE4C0",
|
||||
"CMT_PMV_ER1BEG2",
|
||||
"CMT_PMV_NW4A3",
|
||||
"CMT_PMV_NW4END3",
|
||||
"CMT_PMV_WW4B1",
|
||||
"CMT_PMV_EE2BEG1",
|
||||
"CMT_PMV_EE4BEG1",
|
||||
"CMT_PMV_WL1END0",
|
||||
"CMT_PMV_SE4BEG0",
|
||||
"CMT_PMV_SW4A1",
|
||||
"CMT_PMV_IMUX7",
|
||||
"CMT_PMV_SW4END0",
|
||||
"CMT_PMV_EE4C3",
|
||||
"CMT_PMV_IMUX43",
|
||||
"CMT_PMV_NW2A1",
|
||||
"CMT_PMV_IMUX8",
|
||||
"CMT_PMV_IMUX19",
|
||||
"CMT_PMV_LH1",
|
||||
"CMT_PMV_IMUX1",
|
||||
"CMT_PMV_WR1END3",
|
||||
"CMT_PMV_IMUX12",
|
||||
"CMT_PMV_SE4BEG2",
|
||||
"CMT_PMV_LH12",
|
||||
"CMT_PMV_IMUX10",
|
||||
"CMT_PMV_LOGIC_OUTS12",
|
||||
"CMT_PMV_WW4B0",
|
||||
"CMT_PMV_SE2A1",
|
||||
"CMT_PMV_IMUX21",
|
||||
"CMT_PMV_IMUX25",
|
||||
"CMT_PMV_EE4BEG2",
|
||||
"CMT_PMV_LOGIC_OUTS16",
|
||||
"CMT_PMV_LOGIC_OUTS19",
|
||||
"CMT_PMV_FAN4",
|
||||
"CMT_PMV_SW2A3",
|
||||
"L_TERM_INT_PHASER_TO_IO_OCLK1X_90",
|
||||
"CMT_PMV_LH10",
|
||||
"CMT_PMV_CTRL0",
|
||||
"CMT_PMV_IMUX20",
|
||||
"CMT_PMV_WW4B3",
|
||||
"CMT_PMV_IMUX4",
|
||||
"CMT_PMV_NE2A2",
|
||||
"CMT_PMV_LOGIC_OUTS5",
|
||||
"CMT_PMV_MONITOR_P",
|
||||
"CMT_PMV_CLK0",
|
||||
"CMT_PMV_LOGIC_OUTS14",
|
||||
"CMT_PMV_EE4B0",
|
||||
"CMT_PMV_WW4A2",
|
||||
"CMT_PMV_WW4END3",
|
||||
"CMT_PMV_LOGIC_OUTS23",
|
||||
"CMT_PMV_IMUX32",
|
||||
"CMT_PMV_IMUX42",
|
||||
"CMT_PMV_LH4",
|
||||
"CMT_PMV_LOGIC_OUTS2",
|
||||
"CMT_PMV_LH8",
|
||||
"CMT_PMV_SE4BEG1",
|
||||
"CMT_PMV_IMUX27",
|
||||
"CMT_PMV_LH2",
|
||||
"CMT_PMV_BYP3",
|
||||
"CMT_PMV_WW4B2",
|
||||
"CMT_PMV_FAN3",
|
||||
"CMT_PMV_FAN6",
|
||||
"CMT_PMV_EE4B3",
|
||||
"CMT_PMV_WW4C2",
|
||||
"CMT_PMV_ER1BEG0",
|
||||
"CMT_PMV_SE4C1",
|
||||
"CMT_PMV_FAN7",
|
||||
"CMT_PMV_MONITOR_N",
|
||||
"CMT_PMV_WW2A0",
|
||||
"CMT_PMV_EE4A1",
|
||||
"CMT_PMV_BYP5",
|
||||
"CMT_PMV_IMUX28",
|
||||
"CMT_PMV_IMUX15",
|
||||
"CMT_PMV_WW2A1",
|
||||
"CMT_PMV_WW4A0",
|
||||
"CMT_PMV_CTRL1",
|
||||
"CMT_PMV_IMUX3",
|
||||
"CMT_PMV_CLK1",
|
||||
"CMT_PMV_EE2A2",
|
||||
"CMT_PMV_WW2END2",
|
||||
"CMT_PMV_NE4C1",
|
||||
"CMT_PMV_NE2A3",
|
||||
"CMT_PMV_NE2A1",
|
||||
"CMT_PMV_IMUX37",
|
||||
"CMT_PMV_EE2BEG3",
|
||||
"CMT_PMV_LOGIC_OUTS6",
|
||||
"CMT_PMV_LOGIC_OUTS9",
|
||||
"CMT_PMV_LOGIC_OUTS4",
|
||||
"CMT_PMV_NE4BEG3",
|
||||
"CMT_PMV_WR1END0",
|
||||
"CMT_PMV_BYP6",
|
||||
"CMT_PMV_FAN0",
|
||||
"CMT_PMV_IMUX6",
|
||||
"CMT_PMV_WW4C1",
|
||||
"CMT_PMV_NW2A2",
|
||||
"CMT_PMV_SW2A2",
|
||||
"CMT_PMV_IMUX36",
|
||||
"CMT_PMV_SW4A0",
|
||||
"CMT_PMV_IMUX35",
|
||||
"CMT_PMV_FAN1",
|
||||
"CMT_PMV_IMUX11",
|
||||
"CMT_PMV_EE4BEG0",
|
||||
"CMT_PMV_EE2A3",
|
||||
"CMT_PMV_WW4C0",
|
||||
"CMT_PMV_NE4BEG1",
|
||||
"CMT_PMV_NW4END1",
|
||||
"CMT_PMV_IMUX38",
|
||||
"CMT_PMV_EE4A0",
|
||||
"CMT_PMV_NW4A0",
|
||||
"CMT_PMV_BYP4",
|
||||
"CMT_PMV_NW4END2",
|
||||
"CMT_PMV_EE2A1",
|
||||
"CMT_PMV_WW4END0",
|
||||
"CMT_PMV_WW4END2",
|
||||
"CMT_PMV_WL1END2",
|
||||
"CMT_PMV_SE4C3",
|
||||
"CMT_PMV_IMUX13",
|
||||
"CMT_PMV_WW2A2",
|
||||
"CMT_PMV_LOGIC_OUTS8",
|
||||
"CMT_PMV_EE4C2",
|
||||
"CMT_PMV_EL1BEG1",
|
||||
"CMT_PMV_LOGIC_OUTS0",
|
||||
"CMT_PMV_SW4END3",
|
||||
"CMT_PMV_IMUX2",
|
||||
"CMT_PMV_IMUX14",
|
||||
"CMT_PMV_EL1BEG0",
|
||||
"CMT_PMV_IMUX0",
|
||||
"L_TERM_INT_PHASER_TO_IO_OCLKDIV",
|
||||
"CMT_PMV_EE2BEG2",
|
||||
"CMT_PMV_IMUX47",
|
||||
"CMT_PMV_EE4BEG3",
|
||||
"CMT_PMV_IMUX34",
|
||||
"CMT_PMV_IMUX46",
|
||||
"CMT_PMV_WW4A1",
|
||||
"CMT_PMV_LOGIC_OUTS18",
|
||||
"CMT_PMV_WW2END1",
|
||||
"CMT_PMV_SE2A0",
|
||||
"CMT_PMV_WW4END1",
|
||||
"CMT_PMV_IMUX26",
|
||||
"CMT_PMV_NE4C3",
|
||||
"CMT_PMV_IMUX33",
|
||||
"CMT_PMV_EE4A3",
|
||||
"L_TERM_INT_PHASER_TO_IO_OCLK",
|
||||
"CMT_PMV_LH3",
|
||||
"CMT_PMV_WR1END2",
|
||||
"CMT_PMV_EE2BEG0",
|
||||
"CMT_PMV_BYP2",
|
||||
"CMT_PMV_NE4C0",
|
||||
"CMT_PMV_BYP7",
|
||||
"CMT_PMV_EE2A0",
|
||||
"CMT_PMV_WW2END0",
|
||||
"CMT_PMV_SW4END1",
|
||||
"CMT_PMV_NW4A1",
|
||||
"CMT_PMV_EE4B1",
|
||||
"CMT_PMV_ER1BEG3",
|
||||
"CMT_PMV_LH7",
|
||||
"CMT_PMV_NE4C2",
|
||||
"CMT_PMV_SW4END2",
|
||||
"CMT_PMV_IMUX31",
|
||||
"CMT_PMV_IMUX24",
|
||||
"CMT_PMV_FAN5",
|
||||
"CMT_PMV_LOGIC_OUTS22",
|
||||
"CMT_PMV_IMUX23",
|
||||
"CMT_PMV_FAN2",
|
||||
"CMT_PMV_LOGIC_OUTS3",
|
||||
"CMT_PMV_LOGIC_OUTS15",
|
||||
"CMT_PMV_EL1BEG2",
|
||||
"CMT_PMV_LOGIC_OUTS20",
|
||||
"CMT_PMV_WW2A3",
|
||||
"CMT_PMV_WL1END1",
|
||||
"CMT_PMV_EL1BEG3",
|
||||
"CMT_PMV_IMUX5",
|
||||
"CMT_PMV_IMUX9",
|
||||
"CMT_PMV_LH6",
|
||||
"CMT_PMV_WL1END3",
|
||||
"CMT_PMV_LH11",
|
||||
"CMT_PMV_NE2A0",
|
||||
"CMT_PMV_IMUX18",
|
||||
"CMT_PMV_IMUX17",
|
||||
"CMT_PMV_WR1END1",
|
||||
"CMT_PMV_NE4BEG0",
|
||||
"CMT_PMV_IMUX30",
|
||||
"CMT_PMV_IMUX44",
|
||||
"CMT_PMV_IMUX41",
|
||||
"L_TERM_INT_PHASER_TO_IO_ICLK",
|
||||
"CMT_PMV_EE4C0",
|
||||
"CMT_PMV_SE2A3",
|
||||
"CMT_PMV_SE4BEG3"
|
||||
],
|
||||
"tile_type": "CMT_PMV_L",
|
||||
"sites": []
|
||||
}
|
||||
"wires": [
|
||||
"CMT_PMV_LOGIC_OUTS0",
|
||||
"CMT_PMV_EE4C1",
|
||||
"CMT_PMV_IMUX19",
|
||||
"CMT_PMV_IMUX29",
|
||||
"CMT_PMV_LH2",
|
||||
"CMT_PMV_IMUX11",
|
||||
"L_TERM_INT_PHASER_TO_IO_OCLK1X_90",
|
||||
"CMT_PMV_WW4A2",
|
||||
"CMT_PMV_WW2A1",
|
||||
"CMT_PMV_WW2END2",
|
||||
"L_TERM_INT_PHASER_TO_IO_OCLKDIV",
|
||||
"CMT_PMV_BYP1",
|
||||
"CMT_PMV_WL1END3",
|
||||
"CMT_PMV_EE4A0",
|
||||
"CMT_PMV_NW4END0",
|
||||
"CMT_PMV_LOGIC_OUTS8",
|
||||
"CMT_PMV_LOGIC_OUTS1",
|
||||
"CMT_PMV_WL1END2",
|
||||
"CMT_PMV_SW2A3",
|
||||
"L_TERM_INT_PHASER_TO_IO_OCLK",
|
||||
"CMT_PMV_EE4C2",
|
||||
"CMT_PMV_IMUX39",
|
||||
"CMT_PMV_IMUX43",
|
||||
"CMT_PMV_LOGIC_OUTS14",
|
||||
"CMT_PMV_LOGIC_OUTS13",
|
||||
"CMT_PMV_IMUX0",
|
||||
"CMT_PMV_SW4END3",
|
||||
"CMT_PMV_ER1BEG3",
|
||||
"CMT_PMV_NW2A3",
|
||||
"CMT_PMV_WW4A3",
|
||||
"CMT_PMV_SW4A2",
|
||||
"CMT_PMV_LH10",
|
||||
"CMT_PMV_BYP4",
|
||||
"CMT_PMV_EE2BEG2",
|
||||
"CMT_PMV_EL1BEG3",
|
||||
"CMT_PMV_IMUX8",
|
||||
"CMT_PMV_SE4BEG3",
|
||||
"CMT_PMV_IMUX35",
|
||||
"CMT_PMV_IMUX10",
|
||||
"CMT_PMV_SW4END1",
|
||||
"CMT_PMV_WL1END1",
|
||||
"CMT_PMV_WW2END3",
|
||||
"CMT_PMV_WW4END1",
|
||||
"CMT_PMV_EE4B0",
|
||||
"CMT_PMV_SW4A1",
|
||||
"CMT_PMV_CTRL1",
|
||||
"CMT_PMV_CLK0",
|
||||
"CMT_PMV_IMUX31",
|
||||
"CMT_PMV_EE4A3",
|
||||
"CMT_PMV_SW2A1",
|
||||
"CMT_PMV_WW2END1",
|
||||
"CMT_PMV_NW4END1",
|
||||
"CMT_PMV_LH3",
|
||||
"CMT_PMV_LH7",
|
||||
"CMT_PMV_LOGIC_OUTS2",
|
||||
"CMT_PMV_LH9",
|
||||
"CMT_PMV_SE2A3",
|
||||
"CMT_PMV_IMUX34",
|
||||
"CMT_PMV_NE4C1",
|
||||
"CMT_PMV_FAN0",
|
||||
"CMT_PMV_LH11",
|
||||
"CMT_PMV_WW2A3",
|
||||
"CMT_PMV_IMUX1",
|
||||
"CMT_PMV_IMUX13",
|
||||
"CMT_PMV_EL1BEG2",
|
||||
"CMT_PMV_LOGIC_OUTS17",
|
||||
"CMT_PMV_BYP6",
|
||||
"CMT_PMV_SW4A0",
|
||||
"CMT_PMV_WW4C0",
|
||||
"CMT_PMV_IMUX21",
|
||||
"CMT_PMV_IMUX12",
|
||||
"CMT_PMV_NE4BEG3",
|
||||
"CMT_PMV_LH4",
|
||||
"CMT_PMV_BYP3",
|
||||
"CMT_PMV_IMUX4",
|
||||
"CMT_PMV_IMUX47",
|
||||
"CMT_PMV_NE2A0",
|
||||
"CMT_PMV_WW4A1",
|
||||
"CMT_PMV_LH1",
|
||||
"CMT_PMV_NW4A0",
|
||||
"CMT_PMV_IMUX41",
|
||||
"CMT_PMV_LOGIC_OUTS11",
|
||||
"CMT_PMV_IMUX26",
|
||||
"CMT_PMV_NE4C0",
|
||||
"CMT_PMV_LOGIC_OUTS18",
|
||||
"CMT_PMV_IMUX15",
|
||||
"CMT_PMV_IMUX44",
|
||||
"CMT_PMV_NW4A2",
|
||||
"CMT_PMV_WW4END3",
|
||||
"CMT_PMV_IMUX42",
|
||||
"CMT_PMV_LOGIC_OUTS15",
|
||||
"CMT_PMV_SE4C3",
|
||||
"CMT_PMV_EE4BEG0",
|
||||
"CMT_PMV_SW2A0",
|
||||
"CMT_PMV_IMUX23",
|
||||
"CMT_PMV_BYP0",
|
||||
"CMT_PMV_LOGIC_OUTS21",
|
||||
"CMT_PMV_NE2A3",
|
||||
"CMT_PMV_WW2END0",
|
||||
"CMT_PMV_FAN7",
|
||||
"CMT_PMV_EE2BEG0",
|
||||
"CMT_PMV_NE4BEG0",
|
||||
"CMT_PMV_IMUX27",
|
||||
"CMT_PMV_NW2A2",
|
||||
"CMT_PMV_LOGIC_OUTS12",
|
||||
"CMT_PMV_WW4B1",
|
||||
"CMT_PMV_NE4BEG2",
|
||||
"CMT_PMV_MONITOR_N",
|
||||
"CMT_PMV_WW4B3",
|
||||
"CMT_PMV_LOGIC_OUTS4",
|
||||
"CMT_PMV_WR1END1",
|
||||
"CMT_PMV_LH5",
|
||||
"CMT_PMV_WR1END0",
|
||||
"CMT_PMV_LH12",
|
||||
"CMT_PMV_IMUX46",
|
||||
"CMT_PMV_EE4B3",
|
||||
"CMT_PMV_EE4A2",
|
||||
"CMT_PMV_NE4C2",
|
||||
"CMT_PMV_WW4C1",
|
||||
"CMT_PMV_WW4C3",
|
||||
"CMT_PMV_IMUX9",
|
||||
"CMT_PMV_LOGIC_OUTS7",
|
||||
"CMT_PMV_WW4B2",
|
||||
"CMT_PMV_EE4C0",
|
||||
"CMT_PMV_SE4C2",
|
||||
"CMT_PMV_LH6",
|
||||
"CMT_PMV_SE4BEG1",
|
||||
"CMT_PMV_WW4B0",
|
||||
"CMT_PMV_IMUX24",
|
||||
"CMT_PMV_SW4END0",
|
||||
"CMT_PMV_IMUX14",
|
||||
"CMT_PMV_FAN2",
|
||||
"CMT_PMV_LOGIC_OUTS9",
|
||||
"CMT_PMV_IMUX3",
|
||||
"CMT_PMV_WW4C2",
|
||||
"L_TERM_INT_PHASER_TO_IO_ICLKDIV",
|
||||
"CMT_PMV_WR1END2",
|
||||
"CMT_PMV_IMUX45",
|
||||
"CMT_PMV_EE4A1",
|
||||
"CMT_PMV_IMUX28",
|
||||
"CMT_PMV_NW4END3",
|
||||
"CMT_PMV_EE2A0",
|
||||
"CMT_PMV_EL1BEG0",
|
||||
"CMT_PMV_WW4A0",
|
||||
"CMT_PMV_EE2A3",
|
||||
"CMT_PMV_FAN3",
|
||||
"CMT_PMV_ER1BEG2",
|
||||
"CMT_PMV_IMUX17",
|
||||
"CMT_PMV_LH8",
|
||||
"CMT_PMV_EE2BEG1",
|
||||
"CMT_PMV_EE4C3",
|
||||
"CMT_PMV_NE4C3",
|
||||
"CMT_PMV_FAN5",
|
||||
"CMT_PMV_LOGIC_OUTS3",
|
||||
"CMT_PMV_FAN4",
|
||||
"CMT_PMV_BYP7",
|
||||
"CMT_PMV_SE4BEG2",
|
||||
"CMT_PMV_WR1END3",
|
||||
"CMT_PMV_SW4A3",
|
||||
"CMT_PMV_IMUX16",
|
||||
"CMT_PMV_CLK1",
|
||||
"CMT_PMV_LOGIC_OUTS6",
|
||||
"CMT_PMV_EE2BEG3",
|
||||
"CMT_PMV_NE2A1",
|
||||
"CMT_PMV_SW4END2",
|
||||
"CMT_PMV_SE4BEG0",
|
||||
"CMT_PMV_SW2A2",
|
||||
"CMT_PMV_EE4BEG3",
|
||||
"CMT_PMV_WL1END0",
|
||||
"CMT_PMV_LOGIC_OUTS23",
|
||||
"CMT_PMV_NW2A0",
|
||||
"CMT_PMV_WW2A2",
|
||||
"CMT_PMV_LOGIC_OUTS20",
|
||||
"CMT_PMV_NE4BEG1",
|
||||
"CMT_PMV_LOGIC_OUTS19",
|
||||
"CMT_PMV_IMUX18",
|
||||
"CMT_PMV_EE4BEG2",
|
||||
"CMT_PMV_NW4A3",
|
||||
"CMT_PMV_LOGIC_OUTS16",
|
||||
"CMT_PMV_IMUX33",
|
||||
"CMT_PMV_LOGIC_OUTS10",
|
||||
"CMT_PMV_IMUX30",
|
||||
"CMT_PMV_SE2A2",
|
||||
"CMT_PMV_IMUX37",
|
||||
"CMT_PMV_NW4A1",
|
||||
"CMT_PMV_WW4END0",
|
||||
"L_TERM_INT_PHASER_TO_IO_ICLK",
|
||||
"CMT_PMV_EE2A1",
|
||||
"CMT_PMV_IMUX5",
|
||||
"CMT_PMV_IMUX38",
|
||||
"CMT_PMV_IMUX7",
|
||||
"CMT_PMV_NE2A2",
|
||||
"CMT_PMV_SE2A0",
|
||||
"CMT_PMV_ER1BEG1",
|
||||
"CMT_PMV_EE2A2",
|
||||
"CMT_PMV_IMUX40",
|
||||
"CMT_PMV_NW2A1",
|
||||
"CMT_PMV_IMUX20",
|
||||
"CMT_PMV_WW2A0",
|
||||
"CMT_PMV_SE4C1",
|
||||
"CMT_PMV_MONITOR_P",
|
||||
"CMT_PMV_LOGIC_OUTS5",
|
||||
"CMT_PMV_EE4B1",
|
||||
"CMT_PMV_IMUX22",
|
||||
"CMT_PMV_ER1BEG0",
|
||||
"CMT_PMV_SE2A1",
|
||||
"CMT_PMV_LOGIC_OUTS22",
|
||||
"CMT_PMV_IMUX25",
|
||||
"CMT_PMV_FAN6",
|
||||
"CMT_PMV_CTRL0",
|
||||
"CMT_PMV_BYP5",
|
||||
"CMT_PMV_EE4BEG1",
|
||||
"CMT_PMV_WW4END2",
|
||||
"CMT_PMV_IMUX36",
|
||||
"CMT_PMV_EL1BEG1",
|
||||
"CMT_PMV_NW4END2",
|
||||
"CMT_PMV_IMUX6",
|
||||
"CMT_PMV_IMUX2",
|
||||
"CMT_PMV_EE4B2",
|
||||
"CMT_PMV_IMUX32",
|
||||
"CMT_PMV_BYP2",
|
||||
"CMT_PMV_FAN1",
|
||||
"CMT_PMV_SE4C0"
|
||||
],
|
||||
"pips": {},
|
||||
"tile_type": "CMT_PMV_L",
|
||||
"sites": []
|
||||
}
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue