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Revert regressions in segbits for CLB and INT. 

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
This commit is contained in:
Keith Rothman 2019-01-09 12:59:47 -08:00 committed by Tim 'mithro' Ansell
parent e396cb3cc2
commit a47c01d9ac
6 changed files with 4 additions and 8 deletions
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2
artix7/segbits_clbll_l.db
View File

@ -510,7 +510,7 @@ CLBLL_L.SLICEL_X1.C5FF.ZINI 31_42
CLBLL_L.SLICEL_X1.C5FF.ZRST 00_44
CLBLL_L.SLICEL_X1.C5FFMUX.IN_A 31_44
CLBLL_L.SLICEL_X1.C5FFMUX.IN_B 31_39
CLBLL_L.SLICEL_X1.CARRY4.ACY0 31_01 31_04 31_14 31_15
CLBLL_L.SLICEL_X1.CARRY4.ACY0 31_14
CLBLL_L.SLICEL_X1.CARRY4.BCY0 00_08
CLBLL_L.SLICEL_X1.CARRY4.CCY0 31_48
CLBLL_L.SLICEL_X1.CARRY4.DCY0 31_49

2
artix7/segbits_clbll_r.db
View File

@ -510,7 +510,7 @@ CLBLL_R.SLICEL_X1.C5FF.ZINI 31_42
CLBLL_R.SLICEL_X1.C5FF.ZRST 00_44
CLBLL_R.SLICEL_X1.C5FFMUX.IN_A 31_44
CLBLL_R.SLICEL_X1.C5FFMUX.IN_B 31_39
CLBLL_R.SLICEL_X1.CARRY4.ACY0 31_01 31_04 31_14 31_15
CLBLL_R.SLICEL_X1.CARRY4.ACY0 31_14
CLBLL_R.SLICEL_X1.CARRY4.BCY0 00_08
CLBLL_R.SLICEL_X1.CARRY4.CCY0 31_48
CLBLL_R.SLICEL_X1.CARRY4.DCY0 31_49

2
artix7/segbits_clblm_l.db
View File

@ -166,7 +166,7 @@ CLBLM_L.SLICEL_X1.C5FF.ZINI 31_42
CLBLM_L.SLICEL_X1.C5FF.ZRST 00_44
CLBLM_L.SLICEL_X1.C5FFMUX.IN_A 31_44
CLBLM_L.SLICEL_X1.C5FFMUX.IN_B 31_39
CLBLM_L.SLICEL_X1.CARRY4.ACY0 31_01 31_04 31_14 31_15
CLBLM_L.SLICEL_X1.CARRY4.ACY0 31_14
CLBLM_L.SLICEL_X1.CARRY4.BCY0 00_08
CLBLM_L.SLICEL_X1.CARRY4.CCY0 31_48
CLBLM_L.SLICEL_X1.CARRY4.DCY0 31_49

2
artix7/segbits_clblm_r.db
View File

@ -166,7 +166,7 @@ CLBLM_R.SLICEL_X1.C5FF.ZINI 31_42
CLBLM_R.SLICEL_X1.C5FF.ZRST 00_44
CLBLM_R.SLICEL_X1.C5FFMUX.IN_A 31_44
CLBLM_R.SLICEL_X1.C5FFMUX.IN_B 31_39
CLBLM_R.SLICEL_X1.CARRY4.ACY0 31_01 31_04 31_14 31_15
CLBLM_R.SLICEL_X1.CARRY4.ACY0 31_14
CLBLM_R.SLICEL_X1.CARRY4.BCY0 00_08
CLBLM_R.SLICEL_X1.CARRY4.CCY0 31_48
CLBLM_R.SLICEL_X1.CARRY4.DCY0 31_49

2
artix7/segbits_int_l.db
View File

@ -19,7 +19,6 @@ INT_L.BYP_ALT0.SL1END0 !23_07 19_06 22_07 24_07 25_07
INT_L.BYP_ALT0.SR1END_N3_3 !22_07 18_06 23_07 24_07 25_07
INT_L.BYP_ALT0.SS2END0 !22_07 !23_07 !25_07 16_07 24_07
INT_L.BYP_ALT0.SW2END0 !22_07 !23_07 !24_07 16_07 25_07
INT_L.BYP_ALT0.VCC_WIRE 31_02 31_26 31_37 31_62
INT_L.BYP_ALT0.WL1END0 !23_07 17_07 22_07 24_07 25_07
INT_L.BYP_ALT0.WR1END0 !22_07 16_07 23_07 24_07 25_07
INT_L.BYP_ALT0.WW2END_N0_3 !22_07 !23_07 !25_07 17_07 24_07
@ -44,7 +43,6 @@ INT_L.BYP_ALT1.SL1END0 !23_15 19_14 22_15 24_15 25_15
INT_L.BYP_ALT1.SR1BEG_S0 !22_15 18_14 23_15 24_15 25_15
INT_L.BYP_ALT1.SS2END0 !22_15 !23_15 !25_15 19_14 24_15
INT_L.BYP_ALT1.SW2END0 !22_15 !23_15 !24_15 19_14 25_15
INT_L.BYP_ALT1.VCC_WIRE 30_02 30_25 30_37 30_60
INT_L.BYP_ALT1.WL1END0 !23_15 16_15 22_15 24_15 25_15
INT_L.BYP_ALT1.WR1END1 !22_15 17_15 23_15 24_15 25_15
INT_L.BYP_ALT1.WW2END0 !22_15 !23_15 !25_15 18_14 24_15

2
artix7/segbits_int_r.db
View File

@ -19,7 +19,6 @@ INT_R.BYP_ALT0.SL1END0 !23_07 19_06 22_07 24_07 25_07
INT_R.BYP_ALT0.SR1END_N3_3 !22_07 18_06 23_07 24_07 25_07
INT_R.BYP_ALT0.SS2END0 !22_07 !23_07 !25_07 16_07 24_07
INT_R.BYP_ALT0.SW2END0 !22_07 !23_07 !24_07 16_07 25_07
INT_R.BYP_ALT0.VCC_WIRE 31_02 31_26 31_37 31_62
INT_R.BYP_ALT0.WL1END0 !23_07 17_07 22_07 24_07 25_07
INT_R.BYP_ALT0.WR1END0 !22_07 16_07 23_07 24_07 25_07
INT_R.BYP_ALT0.WW2END_N0_3 !22_07 !23_07 !25_07 17_07 24_07
@ -44,7 +43,6 @@ INT_R.BYP_ALT1.SL1END0 !23_15 19_14 22_15 24_15 25_15
INT_R.BYP_ALT1.SR1BEG_S0 !22_15 18_14 23_15 24_15 25_15
INT_R.BYP_ALT1.SS2END0 !22_15 !23_15 !25_15 19_14 24_15
INT_R.BYP_ALT1.SW2END0 !22_15 !23_15 !24_15 19_14 25_15
INT_R.BYP_ALT1.VCC_WIRE 30_02 30_25 30_37 30_60
INT_R.BYP_ALT1.WL1END0 !23_15 16_15 22_15 24_15 25_15
INT_R.BYP_ALT1.WR1END1 !22_15 17_15 23_15 24_15 25_15
INT_R.BYP_ALT1.WW2END0 !22_15 !23_15 !25_15 18_14 24_15