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prjxray-db
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Canonicalizing all the database files. 

Signed-off-by: Tim 'mithro' Ansell <me@mith.ro>
This commit is contained in:
Tim 'mithro' Ansell 2019-01-30 15:01:06 +11:00
parent 79aea5dea1
commit a111007f61
372 changed files with 121601 additions and 121603 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

814
Info.md
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@ -37,7 +37,7 @@ These files are released under the very permissive [CC0 1.0 Universal](COPYING).
# Details
Last updated on Fri Dec 7 06:43:38 UTC 2018 (2018-12-07T06:43:38+00:00).
Last updated on Wed Jan 30 04:31:46 UTC 2019 (2019-01-30T04:31:46+00:00).
Created using [Project X-Ray](https://github.com/SymbiFlow/prjxray) version [v0.0-1084-gafe50c6](https://github.com/SymbiFlow/prjxray/commit/afe50c68c464c0cd4a3fa92b6a07c9abbe41682f).
@ -53,23 +53,26 @@ Date: Wed Nov 28 14:28:03 2018 -0800
Rempips
```
## Database for [artix7](artix7/)
### Settings
Created using following [settings.sh (sha256: 5e7fd99c466d50e7074f812737417596ed2dd985a8f084bdb803ff06543d9b7f)](https://github.com/SymbiFlow/prjxray/blob/afe50c68c464c0cd4a3fa92b6a07c9abbe41682f/database/artix7/settings.sh)
Created using following [settings/artix7.sh (sha256: 15398c7d0dd8a20e2b3d586ec845e9b1c2292587e308711eacf4fd31508821d5)](https://github.com/SymbiFlow/prjxray/blob/afe50c68c464c0cd4a3fa92b6a07c9abbe41682f/settings/artix7.sh)
```shell
export XRAY_DATABASE="artix7"
export XRAY_PART="xc7a50tfgg484-1"
export XRAY_ROI_FRAMES="0x00000000:0xffffffff"
# All CLB's in part, all BRAM's in part, all DSP's in part.
# tcl queries IOB => don't bother adding
export XRAY_ROI_TILEGRID="SLICE_X0Y0:SLICE_X65Y99 SLICE_X0Y100:SLICE_X57Y149 RAMB18_X0Y0:RAMB18_X1Y59 RAMB36_X0Y0:RAMB36_X1Y29 RAMB18_X2Y0:RAMB18_X2Y39 RAMB36_X2Y0:RAMB36_X2Y19 DSP48_X0Y0:DSP48_X1Y59"
# These settings must remain in sync
export XRAY_ROI="SLICE_X0Y100:SLICE_X35Y149 RAMB18_X0Y40:RAMB18_X0Y59 RAMB36_X0Y20:RAMB36_X0Y29 DSP48_X0Y40:DSP48_X0Y59"
export XRAY_ROI="SLICE_X0Y100:SLICE_X35Y149 RAMB18_X0Y40:RAMB18_X0Y59 RAMB36_X0Y20:RAMB36_X0Y29 DSP48_X0Y40:DSP48_X0Y59 IOB_X0Y100:IOB_X0Y149"
# Most of CMT X0Y2.
export XRAY_ROI_GRID_X1="9"
export XRAY_ROI_GRID_X1="0"
export XRAY_ROI_GRID_X2="58"
# Include VBRK / VTERM
export XRAY_ROI_GRID_Y1="0"
@ -83,7 +86,9 @@ export XRAY_PIN_04="G21"
export XRAY_PIN_05="G22"
export XRAY_PIN_06="F21"
source $(dirname ${BASH_SOURCE[0]})/../../utils/environment.sh
source $(dirname ${BASH_SOURCE[0]})/../utils/environment.sh
init_db
```
### [Results](artix7/)
@ -92,6 +97,7 @@ Results have checksums;
* [`8c6097166bf4b43969c49894dc464d1202f19683d7287a63ec709bc867d97105 ./artix7/element_counts.csv`](./artix7/element_counts.csv)
* [`6864d8edcef442cb129f83b9c5cd27be85d1b4bded8007bbeadcfc70717f8c48 ./artix7/gridinfo/grid-xc7a50tfgg484-1-db.txt`](./artix7/gridinfo/grid-xc7a50tfgg484-1-db.txt)
* [`4c0a815ab8943181331f7aa9ac77655a0a640d9a409a602e4f24f8feb5f905e9 ./artix7/harness/README.md`](./artix7/harness/README.md)
* [`8416e8eef29e5defebbd3e45f60baa15cbcc22d66647a8da62ec7c42eff8b521 ./artix7/harness/arty-a7/pmod/design.bit`](./artix7/harness/arty-a7/pmod/design.bit)
* [`c98eefb677a5cd469b75223d6ceb0e95f5d331de00291193caed008f33ee746c ./artix7/harness/arty-a7/pmod/design.dcp`](./artix7/harness/arty-a7/pmod/design.dcp)
* [`13382ee7fffcd88636892517929e7c60a6e82bb63324a4e48414bb16eb81174b ./artix7/harness/arty-a7/pmod/design.json`](./artix7/harness/arty-a7/pmod/design.json)
@ -100,205 +106,208 @@ Results have checksums;
* [`578bbe948ecc1af59c3e9cda0aacd53841d31534a6ec156af9d2779aee8770f4 ./artix7/harness/arty-a7/swbut/design.dcp`](./artix7/harness/arty-a7/swbut/design.dcp)
* [`124264a1ac88ce1e72eef3d337dc1b67287413036e1e0bf4e1eb52df3cef17ee ./artix7/harness/arty-a7/swbut/design.json`](./artix7/harness/arty-a7/swbut/design.json)
* [`d8c1255df5bc352fbff05b9688b86becfc7d28ee82663256332e0a7b8ac4b338 ./artix7/harness/arty-a7/swbut/design.txt`](./artix7/harness/arty-a7/swbut/design.txt)
* [`c805c150d4a58e392a1c41046261fec0b2c76fe1cce5812253902fc95715ba54 ./artix7/harness/basys3/swbut/design.bit`](./artix7/harness/basys3/swbut/design.bit)
* [`29981e44415eaeff674c940dcd5b5be4fc5b04efa1c10f6a43eb054101e0c966 ./artix7/harness/basys3/swbut/design.dcp`](./artix7/harness/basys3/swbut/design.dcp)
* [`65cbe9fc850652b79386575b9d9f7bb157757b27d49a40fc5297cff3f22084df ./artix7/harness/basys3/swbut/design.json`](./artix7/harness/basys3/swbut/design.json)
* [`cd4000b96378f736d31686b381ebd4349898b3b8bd09606223c7ca48cb1a5aba ./artix7/harness/basys3/swbut/design.txt`](./artix7/harness/basys3/swbut/design.txt)
* [`4c0a815ab8943181331f7aa9ac77655a0a640d9a409a602e4f24f8feb5f905e9 ./artix7/harness/README.md`](./artix7/harness/README.md)
* [`f2a77cae77031e75a603d89470172ec265f0e125093e4038b8712c675f045d4b ./artix7/harness/basys3/swbut/design.bit`](./artix7/harness/basys3/swbut/design.bit)
* [`8cac3f210fcc33e78fe576841c286a19138be26004dee70397f93a0b3019e451 ./artix7/harness/basys3/swbut/design.dcp`](./artix7/harness/basys3/swbut/design.dcp)
* [`11d15eb449e9f42409e7187c26635d3facb6974cc0172819b4387ada2ff2532c ./artix7/harness/basys3/swbut/design.json`](./artix7/harness/basys3/swbut/design.json)
* [`9df8eac3c11e57d81b4bf4a927ade787f881f0ef46c8ab610ca529f35e887689 ./artix7/harness/basys3/swbut/design.txt`](./artix7/harness/basys3/swbut/design.txt)
* [`5acfc8680a96dfe832cbcf70e55d98617323e8f37405d3dca7bcfda9b31aef17 ./artix7/mask_clbll_l.db`](./artix7/mask_clbll_l.db)
* [`615472574699aeeb8471224558ce13e18f14c3e65e3b5a2ecc862ee6d3e89211 ./artix7/mask_clbll_r.db`](./artix7/mask_clbll_r.db)
* [`5acfc8680a96dfe832cbcf70e55d98617323e8f37405d3dca7bcfda9b31aef17 ./artix7/mask_clblm_l.db`](./artix7/mask_clblm_l.db)
* [`615472574699aeeb8471224558ce13e18f14c3e65e3b5a2ecc862ee6d3e89211 ./artix7/mask_clblm_r.db`](./artix7/mask_clblm_r.db)
* [`c5aabee9a52c0eb671d569264639b6903e85e76e50ce57af8b7033062e81c2f5 ./artix7/mask_hclk_l.db`](./artix7/mask_hclk_l.db)
* [`c5aabee9a52c0eb671d569264639b6903e85e76e50ce57af8b7033062e81c2f5 ./artix7/mask_hclk_r.db`](./artix7/mask_hclk_r.db)
* [`6baea72435613b87334f95cfe2b1ab36da4d57ada20b71a7dd870715b3e430c4 ./artix7/ppips_clbll_l.db`](./artix7/ppips_clbll_l.db)
* [`3955d590e8ee64c843bb80f911a08781c1bac63e71b577436ae1f44195a88e22 ./artix7/ppips_clbll_r.db`](./artix7/ppips_clbll_r.db)
* [`29f175153821dc13989eb580676ff0007e108d911275a74e7ebe45e819c14eaf ./artix7/ppips_clblm_l.db`](./artix7/ppips_clblm_l.db)
* [`52b53ae735d40632403283ab720db2172794a22c5245b3da7693b264d69a122d ./artix7/ppips_clblm_r.db`](./artix7/ppips_clblm_r.db)
* [`76d1e0bd4b7ad492cf3fe8698b2b5f46f7dcc5fe446984e5dccae373c63edafd ./artix7/mask_hclk_l.db`](./artix7/mask_hclk_l.db)
* [`76d1e0bd4b7ad492cf3fe8698b2b5f46f7dcc5fe446984e5dccae373c63edafd ./artix7/mask_hclk_r.db`](./artix7/mask_hclk_r.db)
* [`b4ffdb01ca695c7d52f34b88508aef6d596377fcffd7fa5e197212acc4b00e9a ./artix7/ppips_clbll_l.db`](./artix7/ppips_clbll_l.db)
* [`bb75573609f56f082544644ecbb39125d023809340f7a30180cb9df823585009 ./artix7/ppips_clbll_r.db`](./artix7/ppips_clbll_r.db)
* [`a5357b0c018ac9c8c1f8cccf3c36b69f66ffd0e29039dfadb5a829caafd71a73 ./artix7/ppips_clblm_l.db`](./artix7/ppips_clblm_l.db)
* [`15424ecbd5816143def2dcb20fc9cfae5ec4e11a1a5cfc1848e71b2904a1a713 ./artix7/ppips_clblm_r.db`](./artix7/ppips_clblm_r.db)
* [`6d35b568a51f9b6761da2470a71738b2477ef72c16068a529ae8eb52b65bf17a ./artix7/ppips_hclk_l.db`](./artix7/ppips_hclk_l.db)
* [`81e0696179a33bdf8d2279a53b406911a403d50224355e9ad29eccee01a70305 ./artix7/ppips_hclk_r.db`](./artix7/ppips_hclk_r.db)
* [`be617c15d1ec311b6249791414bbd69380fe90b476353cbb2fc2a7cb06f5029d ./artix7/ppips_int_l.db`](./artix7/ppips_int_l.db)
* [`a1423859c97a82dcfb114644f50b991db4ca7e0996e6d1ae4d2c97bfdfcb723d ./artix7/ppips_int_r.db`](./artix7/ppips_int_r.db)
* [`7966925d50ebf5296f273ac64d03614ce0f452209bc0a4bde2e3d30f2fbd9a53 ./artix7/segbits_bram_l.block_ram.db`](./artix7/segbits_bram_l.block_ram.db)
* [`aaa1d706495108244ce39af259fe7a0b636f3e5e0d911e2bce23f904d8816f1a ./artix7/segbits_bram_l.db`](./artix7/segbits_bram_l.db)
* [`7b958779367cfa8ab94fc1358241bf2704f0f165eb7809653d527ecef77bb6b1 ./artix7/segbits_bram_r.block_ram.db`](./artix7/segbits_bram_r.block_ram.db)
* [`c5335d22c23e0ef7dc23d66388d9586fef598680d429f96d4308a21a345edc22 ./artix7/segbits_bram_r.db`](./artix7/segbits_bram_r.db)
* [`71a9f4d45ff1bc97600e667cdef73e1af1d9c51774349b22b64af15119d1327d ./artix7/segbits_clbll_l.db`](./artix7/segbits_clbll_l.db)
* [`ee8c13190939fea8ce6a73b3890553b6eb3bfb44086b286c91643ba26346a70a ./artix7/segbits_clbll_r.db`](./artix7/segbits_clbll_r.db)
* [`07edc5ba0b0ecffe2307d0d3ba99c86137f8413ea8a607cecaf200975cb2faf1 ./artix7/segbits_clblm_l.db`](./artix7/segbits_clblm_l.db)
* [`8d2b473ddb30e63cf50cf9cd6eba36cffaa2315756280dc9b1da678f5f747774 ./artix7/segbits_clblm_r.db`](./artix7/segbits_clblm_r.db)
* [`df496c4d335fac0c379497ff0a75ba4f5c5c25bcce79f9c7a72d5f08066310db ./artix7/segbits_hclk_l.db`](./artix7/segbits_hclk_l.db)
* [`5e22f758a04eab3185b2453c9994aa2fa48f50ca8a6b49bf82e8fc4351f23a5c ./artix7/segbits_hclk_r.db`](./artix7/segbits_hclk_r.db)
* [`582158a8db52f7e08b4d0f20d4e2f9efcaa56bd836f06e1e8b0de3dbb909d698 ./artix7/segbits_int_l.db`](./artix7/segbits_int_l.db)
* [`c95a67762d97d31140eb9f251fb52d97674912633990438495bf8c37793eea06 ./artix7/segbits_int_r.db`](./artix7/segbits_int_r.db)
* [`5e7fd99c466d50e7074f812737417596ed2dd985a8f084bdb803ff06543d9b7f ./artix7/settings.sh`](./artix7/settings.sh)
* [`6a998dd55a7aa4ab33db25db7b5167d57f3d708713baf1fca394dc2940f12007 ./artix7/site_type_BSCAN.json`](./artix7/site_type_BSCAN.json)
* [`7f59ea08fa5dbf9ce84ea26f03f13cd02683fce9cdd98621e501e422bf09d165 ./artix7/site_type_BUFGCTRL.json`](./artix7/site_type_BUFGCTRL.json)
* [`2d6c78790d74503f0810356de3a765b380b319f09a41593bc8cbe8979defd1f7 ./artix7/site_type_BUFHCE.json`](./artix7/site_type_BUFHCE.json)
* [`7d2ad5e0c2a12242cabe03aa9a89bdc1ad4413720c45243809371e06be84a88b ./artix7/site_type_BUFIO.json`](./artix7/site_type_BUFIO.json)
* [`99ac6ee5e9381bc68e9e7c0ba1e75779a80360b3854b87cc124819a17cd23a75 ./artix7/site_type_BUFMRCE.json`](./artix7/site_type_BUFMRCE.json)
* [`ea18314ade2d867b7ee931c71ccca7780dcda5da63e4c986a5db37508c8df60a ./artix7/site_type_BUFR.json`](./artix7/site_type_BUFR.json)
* [`15b8fa9480b7f789bf65aca97263c2b97d120eb3ab79d4330d17e39c36bd0131 ./artix7/site_type_CAPTURE.json`](./artix7/site_type_CAPTURE.json)
* [`af89e5523c49b0ede53efd5c2304d1e1a5efb553b52ec873526923f2fd019705 ./artix7/site_type_DCIRESET.json`](./artix7/site_type_DCIRESET.json)
* [`79effefe83be725ab9cf4c1167e6e2582144317654c179b5076ae19f7462403b ./artix7/site_type_DNA_PORT.json`](./artix7/site_type_DNA_PORT.json)
* [`2326eb345b6c10062379bbb3c7afe5ebc4b9ecbc104f8947158dbae09c09e7c8 ./artix7/site_type_DSP48E1.json`](./artix7/site_type_DSP48E1.json)
* [`75db786def8e1871ca3fd7c65d6481a53464f000343b32155ee3a05dd86eb0b3 ./artix7/site_type_EFUSE_USR.json`](./artix7/site_type_EFUSE_USR.json)
* [`a9e6d74302ee507649432e33e31d21d8feaf6b51e2ae0f26a579c16f57f59512 ./artix7/site_type_FIFO18E1.json`](./artix7/site_type_FIFO18E1.json)
* [`0d1ff1869cb0c2ceb18b7d6e4d53abc15db8712ed4f6845c6ed093e0d28d2fe8 ./artix7/site_type_FRAME_ECC.json`](./artix7/site_type_FRAME_ECC.json)
* [`77cf2f8bdde15b54743f8ce3e919890f15954003786b0be8b5ae034e72fa7e27 ./artix7/site_type_GTPE2_CHANNEL.json`](./artix7/site_type_GTPE2_CHANNEL.json)
* [`bab2074cd8be6c79f978b03a2f7a631a6ed01fc5a8cd35b1a92348fb7854ecb0 ./artix7/site_type_GTPE2_COMMON.json`](./artix7/site_type_GTPE2_COMMON.json)
* [`e4b974ca43493be5444c2c2a4a0c243712e882499f8ca87efc38bdca267cc988 ./artix7/site_type_IBUFDS_GTE2.json`](./artix7/site_type_IBUFDS_GTE2.json)
* [`a2514cd2da5e5cabdc3babd476b014b6b44a2cc8fca19f2f2785cb207abbb751 ./artix7/site_type_ICAP.json`](./artix7/site_type_ICAP.json)
* [`d23176a42d861807d5bd2559e58f31e3ffe516d3c0597ace669c88f0f8bdd145 ./artix7/site_type_IDELAYCTRL.json`](./artix7/site_type_IDELAYCTRL.json)
* [`2bf5daae4d45e9b6d65fbfa7c73426c896bc071d9b577b57371f8570836acb86 ./artix7/site_type_IDELAYE2.json`](./artix7/site_type_IDELAYE2.json)
* [`05ffeb28332d5d17fc32b2410da41b0b97426a01bb4a3cd84849ab386b50c543 ./artix7/site_type_ILOGICE3.json`](./artix7/site_type_ILOGICE3.json)
* [`ef48fb9be2319b50b808ead0726bc6a037377fe10fbf3d22ca9acd29def80e2b ./artix7/site_type_IN_FIFO.json`](./artix7/site_type_IN_FIFO.json)
* [`c98ef8397786c5c71b2c5a43824ce47f0e46c93424eef58ad47bf0f7c7d42675 ./artix7/site_type_IOB33.json`](./artix7/site_type_IOB33.json)
* [`76e2eb01e49adb5b5d7586d57b5dc07b2104aac9295f173d2b2b3724a86a9eb0 ./artix7/site_type_IOB33M.json`](./artix7/site_type_IOB33M.json)
* [`ccdec6f60ba548d85b3b24345c0fbc4b5e703c0de936f12c09c5c0fb822fcf3e ./artix7/site_type_IOB33S.json`](./artix7/site_type_IOB33S.json)
* [`7d0bc5533db085e0ef68a2dbd16906b4936bb35efa4790953c2c4ee607f1ed28 ./artix7/site_type_IPAD.json`](./artix7/site_type_IPAD.json)
* [`bf073833d9a7b9e125d4829e464cdd67a61bf9195d0dd7854f1fa6397014aacc ./artix7/site_type_MMCME2_ADV.json`](./artix7/site_type_MMCME2_ADV.json)
* [`186eac82246b8b10da9abab93b15f638bdb8ef446ce0e4b4ceb797e2091132dd ./artix7/site_type_OLOGICE3.json`](./artix7/site_type_OLOGICE3.json)
* [`b4670a20c46552416276ba8e5442b4c3d24c6215650a212f00f874dc78371bca ./artix7/site_type_OPAD.json`](./artix7/site_type_OPAD.json)
* [`776619b1507bfe996cfa7b900058cff911bd96a29dac1b33e5b29aa662053aad ./artix7/site_type_OUT_FIFO.json`](./artix7/site_type_OUT_FIFO.json)
* [`06edd04ea43682f65f2d8cbc6282d5e10385c23e75bd61ddd99c4e6ce2b9fcf6 ./artix7/site_type_PCIE_2_1.json`](./artix7/site_type_PCIE_2_1.json)
* [`311eda695286ee7edd51cc78c3c6bdbe9901bcb515308a17572302af321fdbc4 ./artix7/site_type_PHASER_IN_PHY.json`](./artix7/site_type_PHASER_IN_PHY.json)
* [`2474fdfcd0bd228964e62f4875e9684e15984ee57e40b17f6759a5897148cba5 ./artix7/site_type_PHASER_OUT_PHY.json`](./artix7/site_type_PHASER_OUT_PHY.json)
* [`f8aefb394bd6cef6244a56a4376bf0a44ce368741dfbce8cf7f5df45a71c47a3 ./artix7/site_type_PHASER_REF.json`](./artix7/site_type_PHASER_REF.json)
* [`01733676f386e217548135ed297b2fa73e0d0d17003b84513708ed8508f447ce ./artix7/site_type_PHY_CONTROL.json`](./artix7/site_type_PHY_CONTROL.json)
* [`e314d184ac0bbe656ca4d34c33af80149b4d7dbe6798094de089462f78b52405 ./artix7/site_type_PLLE2_ADV.json`](./artix7/site_type_PLLE2_ADV.json)
* [`58897a08e0442222f117be75393c6b46360933abc71ff1de142ba7adcaabfa3f ./artix7/site_type_PMV2.json`](./artix7/site_type_PMV2.json)
* [`110126d521d4744019d75f9c0bdcef76851b2c8f003fed0d5dbb7f7806aadae7 ./artix7/site_type_RAMB18E1.json`](./artix7/site_type_RAMB18E1.json)
* [`1ab295693d283025d16966f5ed48515046fea1078529d48e0eab5eef732bcb40 ./artix7/site_type_RAMBFIFO36E1.json`](./artix7/site_type_RAMBFIFO36E1.json)
* [`586145c0b465d7ac945746193cf4f38ec5bb26bbc52997bce47d5fbdd9d0c241 ./artix7/site_type_SLICEL.json`](./artix7/site_type_SLICEL.json)
* [`201ecff6bb7d78c8597d467e55486fc00b2ad95a6a7dee0cd98346ab9e8c888a ./artix7/site_type_SLICEM.json`](./artix7/site_type_SLICEM.json)
* [`872bc95eb5f912fc95ca2ca18960b14b9cc20f00bf30b7227d0c6c9b0f3bbeb0 ./artix7/site_type_STARTUP.json`](./artix7/site_type_STARTUP.json)
* [`db8c88384575a7e0562692550bdba7a4089ea5fabe451bf58403d3a85af419a0 ./artix7/site_type_TIEOFF.json`](./artix7/site_type_TIEOFF.json)
* [`4d6130cb2604efae8ca5d628b95be2549083c16c639d335bdc906924e37ec28c ./artix7/site_type_USR_ACCESS.json`](./artix7/site_type_USR_ACCESS.json)
* [`dbf0ff3b27d1fac02572351765f1b17b3e950ed4e8fe95ac6bcd71012e4f7b2d ./artix7/site_type_XADC.json`](./artix7/site_type_XADC.json)
* [`22ec794e0d8e263d117dcc3606363c042b4cb186a14f4da81efbaa75d86037f3 ./artix7/tileconn.json`](./artix7/tileconn.json)
* [`3dcf45da1b1f6d0b0f4867c6cabd17366a383652f09b6838e3f906a4b5d1a677 ./artix7/tilegrid.json`](./artix7/tilegrid.json)
* [`a93b4be2b2832d1a9240b892f6d8db469f3d9cf6229cc6856a197e854f4abc8a ./artix7/tile_type_BRAM_INT_INTERFACE_L.json`](./artix7/tile_type_BRAM_INT_INTERFACE_L.json)
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* [`db6c15155f364bd395363fb230bf43119a0081e41d659b0afb01dc5144da723a ./artix7/tile_type_BRKH_BRAM.json`](./artix7/tile_type_BRKH_BRAM.json)
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* [`0d3e86aab90d3bb52dd77b187695d3cb3777e46336d1fc1725b6329b8902b626 ./artix7/tile_type_BRKH_CLK.json`](./artix7/tile_type_BRKH_CLK.json)
* [`7679aeafb655e2bd58deddc3ab9746ee00e801e4f6b3cd93e17d66f211beb288 ./artix7/tile_type_BRKH_CMT.json`](./artix7/tile_type_BRKH_CMT.json)
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* [`15db89f4dc5243d4e315e8130937270919397031ec30ec764fde6400f9b5d651 ./artix7/tile_type_BRKH_DSP_R.json`](./artix7/tile_type_BRKH_DSP_R.json)
* [`856754623cc87f0058d073999e25faab904f7edef7beb0a818e60ab853fa5b97 ./artix7/tile_type_BRKH_GTX.json`](./artix7/tile_type_BRKH_GTX.json)
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* [`b4cf053f06f3965af2f05b74e43eff6bdf24daf8ee2cb61ddeeee70e71ed660d ./artix7/tile_type_CFG_CENTER_BOT.json`](./artix7/tile_type_CFG_CENTER_BOT.json)
* [`82468ad16be6809588902afecfb06ec15ec7408b6cd1e3b99fe14430a62e11a2 ./artix7/tile_type_CFG_CENTER_MID.json`](./artix7/tile_type_CFG_CENTER_MID.json)
* [`413970a4868c43567623a14b4093be69899de10ebba2f62fd06137660b35b6dc ./artix7/tile_type_CFG_CENTER_TOP.json`](./artix7/tile_type_CFG_CENTER_TOP.json)
* [`51e08a3158bfddccb5c43b0dc7ff6f55fe303df871795fdd921b8963e619e95c ./artix7/tile_type_CLBLL_L.json`](./artix7/tile_type_CLBLL_L.json)
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* [`656de9ce6a18a058c083d07bae3433fde5899680ac68165e9e8430023c2f123c ./artix7/tile_type_CLK_BUFG_BOT_R.json`](./artix7/tile_type_CLK_BUFG_BOT_R.json)
* [`6aa792786a1fbb38c20f1aceba3936775473d8dff5529f7aa41e8da38eee4c0c ./artix7/tile_type_CLK_BUFG_REBUF.json`](./artix7/tile_type_CLK_BUFG_REBUF.json)
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* [`d6df6130236178fdfecd77e7ab871dd7f5f5d91270aff446bbc6082b5d611f50 ./artix7/tile_type_CLK_FEED.json`](./artix7/tile_type_CLK_FEED.json)
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* [`54365a8bfc347ca228266b6a682e0ccb1a5c98283c90efc3b738b962134d62ba ./artix7/tile_type_CLK_MTBF2.json`](./artix7/tile_type_CLK_MTBF2.json)
* [`60f5de137907091563bc64aadc4caab115d6527c31525c6ede9148b4f9b5f3d9 ./artix7/tile_type_CLK_PMV2.json`](./artix7/tile_type_CLK_PMV2.json)
* [`392df005504cbc65b160a7eacf01d885617b0c2869269ba5de7b490c069993fe ./artix7/tile_type_CLK_PMV2_SVT.json`](./artix7/tile_type_CLK_PMV2_SVT.json)
* [`aeb291f8b0d6e930b1a9dfeddf444f78cf7b8a3e1b4bfd68695a610b4a56df15 ./artix7/tile_type_CLK_PMVIOB.json`](./artix7/tile_type_CLK_PMVIOB.json)
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* [`f34c8817cd592fbd84bf5320aa2afe886e400219227e23106ab20bb14bf6b0e9 ./artix7/tile_type_CMT_FIFO_L.json`](./artix7/tile_type_CMT_FIFO_L.json)
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* [`05cf5e8fda8975612f1eaf0a08c8f9c18b9719d471cdd382241d8788698e6297 ./artix7/tile_type_LIOI3_TBYTETERM.json`](./artix7/tile_type_LIOI3_TBYTETERM.json)
* [`e1c8778875bb256d12ed385b622bce95d86f5bd46c7aa5748f74f0854e39f2fd ./artix7/tile_type_L_TERM_INT.json`](./artix7/tile_type_L_TERM_INT.json)
* [`37fadb30f0cef301907968b8129ae02704ba4c9d11caa42db31fed8734a4f2da ./artix7/tile_type_MONITOR_BOT.json`](./artix7/tile_type_MONITOR_BOT.json)
* [`f2e9686909e9dfa00edde4d8020bf7da5cc33be88c5f12cb0b9495146da427b3 ./artix7/tile_type_MONITOR_MID.json`](./artix7/tile_type_MONITOR_MID.json)
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* [`9900c1d7c03b75bb765c57b00b20fbefd09efeccb325afba72901b941d5db0de ./artix7/tile_type_CLK_FEED.json`](./artix7/tile_type_CLK_FEED.json)
* [`fa0923a2169819ecc93697c7255aef24e9dbee2a3c5d8c1df3f86956e0bc8b08 ./artix7/tile_type_CLK_HROW_BOT_R.json`](./artix7/tile_type_CLK_HROW_BOT_R.json)
* [`71f60f081cb9718ca95f3c004034dde427a1323ae4f71f94c68f3ecb961f1d2f ./artix7/tile_type_CLK_HROW_TOP_R.json`](./artix7/tile_type_CLK_HROW_TOP_R.json)
* [`3d200f97f5d0608d4577dcaf9ae59c34be18f4d1406aa71815d56327fc2a3564 ./artix7/tile_type_CLK_MTBF2.json`](./artix7/tile_type_CLK_MTBF2.json)
* [`0163ab8305f14d439e303fc072bf980549efd65c42494e468bc2b2e0bd3ff0a6 ./artix7/tile_type_CLK_PMV.json`](./artix7/tile_type_CLK_PMV.json)
* [`1e08a2d1f2c7e0ec12b0eec202c3759fbfc82fab01b9d0b5d1658299d8ac5506 ./artix7/tile_type_CLK_PMV2.json`](./artix7/tile_type_CLK_PMV2.json)
* [`bf52b93861ca5856dab593dde196a21ab8a9522b4eb58f13fe206beaba8c78f2 ./artix7/tile_type_CLK_PMV2_SVT.json`](./artix7/tile_type_CLK_PMV2_SVT.json)
* [`e7123b7dbeba2ebbf4a6ae04fb87bd114548befc9bb812d7bf4bee3401aa44fa ./artix7/tile_type_CLK_PMVIOB.json`](./artix7/tile_type_CLK_PMVIOB.json)
* [`42236b4ea5a40883822299aef2c5eb6ef2adb30c715145a9c36c5dd9e84e102e ./artix7/tile_type_CLK_TERM.json`](./artix7/tile_type_CLK_TERM.json)
* [`f985c5c1c1186eb314e1bd727b4195b88f69739fcb991efbafee963310b880f9 ./artix7/tile_type_CMT_FIFO_L.json`](./artix7/tile_type_CMT_FIFO_L.json)
* [`2209bb569563a8f748c4f54f28a5d870d9f873d1403cefc3c433174bb68d74f2 ./artix7/tile_type_CMT_FIFO_R.json`](./artix7/tile_type_CMT_FIFO_R.json)
* [`a3cce946e4fc43015cc0e0d5ed2305bbf1da982807029d4a72a5f3f76cb6e756 ./artix7/tile_type_CMT_PMV.json`](./artix7/tile_type_CMT_PMV.json)
* [`9207ebd19f94b6a3a9d8ea08f1fe78dcf592d3b5b5f541694a23d5dc1a9163e3 ./artix7/tile_type_CMT_PMV_L.json`](./artix7/tile_type_CMT_PMV_L.json)
* [`63d8187207a325d174e8d509014200531f3e11236e5064c2675871ca42fbbffa ./artix7/tile_type_CMT_TOP_L_LOWER_B.json`](./artix7/tile_type_CMT_TOP_L_LOWER_B.json)
* [`129c5c28dee6d7cc79263d280a391c07b5db326124ad1e973582643d9eadff3a ./artix7/tile_type_CMT_TOP_L_LOWER_T.json`](./artix7/tile_type_CMT_TOP_L_LOWER_T.json)
* [`3196f3226311d6da93de4941e326367c75d2433dcda15df9d1ca9a361f57b297 ./artix7/tile_type_CMT_TOP_L_UPPER_B.json`](./artix7/tile_type_CMT_TOP_L_UPPER_B.json)
* [`e008d249e1f1dafa57e4ac276826c60e24b7fd29ec4e5acafd078c0604631afc ./artix7/tile_type_CMT_TOP_L_UPPER_T.json`](./artix7/tile_type_CMT_TOP_L_UPPER_T.json)
* [`5b45ef7b0d9a366440da629a02330f51b6210652842fe723369e88f31df5d732 ./artix7/tile_type_CMT_TOP_R_LOWER_B.json`](./artix7/tile_type_CMT_TOP_R_LOWER_B.json)
* [`6260182cedf2857372997d8b9a9b3d28504931d1c7ff5176d718dd44935354f0 ./artix7/tile_type_CMT_TOP_R_LOWER_T.json`](./artix7/tile_type_CMT_TOP_R_LOWER_T.json)
* [`21e908de40301ce5b6d3a2479a5784c74f7227a1493941a5552845e794bdfa2b ./artix7/tile_type_CMT_TOP_R_UPPER_B.json`](./artix7/tile_type_CMT_TOP_R_UPPER_B.json)
* [`816d810709c3f54a33774c6a9acefe472cac1e5748d306e692524007b699ee35 ./artix7/tile_type_CMT_TOP_R_UPPER_T.json`](./artix7/tile_type_CMT_TOP_R_UPPER_T.json)
* [`acd1f4d85f068809d6b1aa29426168b9418923631cc514a9159e95bfff599350 ./artix7/tile_type_DSP_L.json`](./artix7/tile_type_DSP_L.json)
* [`bc2866210b36ed258d392e54b68d08171dd254eb1c976187259ce5bf403f920a ./artix7/tile_type_DSP_R.json`](./artix7/tile_type_DSP_R.json)
* [`01bb373548f7244412efb0a59b85203b18450d357c809b0c36ceaee46a81f3d1 ./artix7/tile_type_GTP_CHANNEL_0.json`](./artix7/tile_type_GTP_CHANNEL_0.json)
* [`e34491f9e8151c172f330dbddd41ee646dbb526772409174810ca8872df4e6a1 ./artix7/tile_type_GTP_CHANNEL_1.json`](./artix7/tile_type_GTP_CHANNEL_1.json)
* [`fcb1a2ac092a41409be635c1d61585f0e9d40d0ce86014e424ab99f2f50342ea ./artix7/tile_type_GTP_CHANNEL_2.json`](./artix7/tile_type_GTP_CHANNEL_2.json)
* [`3c29037183eb9e13bcb6100d35b3f8f633df4078fcccb4479e4163c2c4edff4e ./artix7/tile_type_GTP_CHANNEL_3.json`](./artix7/tile_type_GTP_CHANNEL_3.json)
* [`5fed3e1f4b1e13067c8af92aba2086eace7fdef9dd3dd2ab719953be12694bd1 ./artix7/tile_type_GTP_COMMON.json`](./artix7/tile_type_GTP_COMMON.json)
* [`a76c8162ac133ae09ea8ad8dae00ca8d55452bb619416bc6684e56c990c3ce17 ./artix7/tile_type_GTP_INT_INTERFACE.json`](./artix7/tile_type_GTP_INT_INTERFACE.json)
* [`05eb17dc54b29fac95e4b2ac067139b528c1bc7f5cb78b672e6941a2966ec7bb ./artix7/tile_type_HCLK_BRAM.json`](./artix7/tile_type_HCLK_BRAM.json)
* [`307db3c561c03036e0460d24af8d435631bbacef7f81c0385f6179673d818d50 ./artix7/tile_type_HCLK_CLB.json`](./artix7/tile_type_HCLK_CLB.json)
* [`318c1785d2059191307e3e12efc326475b060106d048550bfd2a7a48381257d0 ./artix7/tile_type_HCLK_CMT.json`](./artix7/tile_type_HCLK_CMT.json)
* [`4af6db5c406dd683670c77fe2dbfcfd64b0d079e59e3082cfc4e578789cddf45 ./artix7/tile_type_HCLK_CMT_L.json`](./artix7/tile_type_HCLK_CMT_L.json)
* [`cbcd13d3b6a78888a73e22e1e33e56c80b5fcb23c4d1baf938b4b6daa02173f7 ./artix7/tile_type_HCLK_DSP_L.json`](./artix7/tile_type_HCLK_DSP_L.json)
* [`dacc707f9e2db1d6752f833cf0559536423baf915a848b3ff641373f4762793f ./artix7/tile_type_HCLK_DSP_R.json`](./artix7/tile_type_HCLK_DSP_R.json)
* [`c1d33fee3af7b2ba311bad50d6f8b771303ebd8241e617ec638b1fcb8d2c4ee0 ./artix7/tile_type_HCLK_FEEDTHRU_1.json`](./artix7/tile_type_HCLK_FEEDTHRU_1.json)
* [`0e991e5fc85e54835a7de8da8456ee1300d97d798fb12d16c521a9163500a20c ./artix7/tile_type_HCLK_FEEDTHRU_2.json`](./artix7/tile_type_HCLK_FEEDTHRU_2.json)
* [`1631fbdf6e3158d6e372508b55e32e3e638b270e0ca606359b4ad060f6337cea ./artix7/tile_type_HCLK_FIFO_L.json`](./artix7/tile_type_HCLK_FIFO_L.json)
* [`7897a72ad8df7a9561af0cd339d07b78fda2d8978771ca314edb158eb6bf21d5 ./artix7/tile_type_HCLK_GTX.json`](./artix7/tile_type_HCLK_GTX.json)
* [`6a66fa18fdad81ae738e61f650066415a2adc7d15b15ab87b5080faff3edb9e1 ./artix7/tile_type_HCLK_INT_INTERFACE.json`](./artix7/tile_type_HCLK_INT_INTERFACE.json)
* [`51fbaa9613664a08814f372c5791189ceb855720997334f55e52872cc6d4c46f ./artix7/tile_type_HCLK_IOB.json`](./artix7/tile_type_HCLK_IOB.json)
* [`725ed17a96bdb3d91b1e0abd8b9705ac351c64fe1dd7d82e377009c0d9e0a746 ./artix7/tile_type_HCLK_IOI3.json`](./artix7/tile_type_HCLK_IOI3.json)
* [`2c39172c06f58c30f92d140c6c7c060777b1b3f397a23b9cf82a41a656da82ef ./artix7/tile_type_HCLK_L.json`](./artix7/tile_type_HCLK_L.json)
* [`4270980b733f54a17a34b5259579fd2e42d38efeeb42518967362c599def37c2 ./artix7/tile_type_HCLK_L_BOT_UTURN.json`](./artix7/tile_type_HCLK_L_BOT_UTURN.json)
* [`782d62d7a78ca8282570a945739057b1801795271764120ff4f20696a36e9354 ./artix7/tile_type_HCLK_R.json`](./artix7/tile_type_HCLK_R.json)
* [`0bc6c1727558cc3dfe8ee21ec2f2b03e6f0f362d3948b2afed0217e1fd1b2d32 ./artix7/tile_type_HCLK_R_BOT_UTURN.json`](./artix7/tile_type_HCLK_R_BOT_UTURN.json)
* [`5b459ee856bd5417b0c61831120d27cebb7f5c6ae4952470bdc6dc6bad6c5b49 ./artix7/tile_type_HCLK_TERM.json`](./artix7/tile_type_HCLK_TERM.json)
* [`ccc33563773bbe6157c016214acd36162575086bfa661e8fa53885a58dd2d43d ./artix7/tile_type_HCLK_TERM_GTX.json`](./artix7/tile_type_HCLK_TERM_GTX.json)
* [`e706c7cf142b8e806283d3cf030f89e30149bad7b2f156e739e2f41247922792 ./artix7/tile_type_HCLK_VBRK.json`](./artix7/tile_type_HCLK_VBRK.json)
* [`acabe2c19ef9286451b67f889608af10b57c4149be795c7b9e96c700e673741a ./artix7/tile_type_HCLK_VFRAME.json`](./artix7/tile_type_HCLK_VFRAME.json)
* [`fe9a6b9109c94abc0860142566f1d6c292b5313f2ebe641dbd3f4d41671d05a2 ./artix7/tile_type_INT_FEEDTHRU_1.json`](./artix7/tile_type_INT_FEEDTHRU_1.json)
* [`1ff618718c404f469eed1fc7499db1a7bcfa90bf152b317b07511d1e070d7622 ./artix7/tile_type_INT_FEEDTHRU_2.json`](./artix7/tile_type_INT_FEEDTHRU_2.json)
* [`08db2bc2bc634b16af1988b445a896ffdbe75e2275647657dd44dbc9e436ec9f ./artix7/tile_type_INT_INTERFACE_L.json`](./artix7/tile_type_INT_INTERFACE_L.json)
* [`3f04e660e8a477ae99b5349c70d4bb420ed61c823ead17915a2900cc2210ad46 ./artix7/tile_type_INT_INTERFACE_R.json`](./artix7/tile_type_INT_INTERFACE_R.json)
* [`cc47a410209b8beb6140d0216de2b298547116a90f4cd7cf9674785e838f4c36 ./artix7/tile_type_INT_L.json`](./artix7/tile_type_INT_L.json)
* [`784502f54f667eb147924b061bc62829588d0e43673f32fd9d45113b6f740457 ./artix7/tile_type_INT_R.json`](./artix7/tile_type_INT_R.json)
* [`ffedd570b50dfb9fdd8d1e5065da17d53319cda7e849848ec88d352c767e2d59 ./artix7/tile_type_IO_INT_INTERFACE_L.json`](./artix7/tile_type_IO_INT_INTERFACE_L.json)
* [`cf049a6c528634761c6067610f50110102caadc782a33b855f4059df8ed064d9 ./artix7/tile_type_IO_INT_INTERFACE_R.json`](./artix7/tile_type_IO_INT_INTERFACE_R.json)
* [`cef7db2efcd92f19a0775c1833e0dd23b3dcb4d016fa8516b7e69c4a658ac630 ./artix7/tile_type_LIOB33.json`](./artix7/tile_type_LIOB33.json)
* [`49276f934ed32b1ec0b2eac19b67178119fbc5674d022eec1de5be08b07c4e72 ./artix7/tile_type_LIOB33_SING.json`](./artix7/tile_type_LIOB33_SING.json)
* [`801140f147650d8b443e46fa51793181c264bc8d92c8767bb875ae838ae4a062 ./artix7/tile_type_LIOI3.json`](./artix7/tile_type_LIOI3.json)
* [`c2932bc581e8b38a7373f5a9a555263ce7aa9d96ad9c4e5675c599b11d86b67b ./artix7/tile_type_LIOI3_SING.json`](./artix7/tile_type_LIOI3_SING.json)
* [`b69c2ea84f06bfed085b2f50e1f4dd43033dd5f34ca19e67da42d6c80317cd23 ./artix7/tile_type_LIOI3_TBYTESRC.json`](./artix7/tile_type_LIOI3_TBYTESRC.json)
* [`44cf5e287a63932e7b6809f4fc3245ff380ae8ad24ed9b53b8cee45b719517b6 ./artix7/tile_type_LIOI3_TBYTETERM.json`](./artix7/tile_type_LIOI3_TBYTETERM.json)
* [`5c6ddebe6aef58fa126d2f1121f2c415737d513b90169c393dfcbe2655251716 ./artix7/tile_type_L_TERM_INT.json`](./artix7/tile_type_L_TERM_INT.json)
* [`c5d8bb0e44590428962e16d5083ce84e0d86d7e44e41670227b3e65ef5e65ecb ./artix7/tile_type_MONITOR_BOT.json`](./artix7/tile_type_MONITOR_BOT.json)
* [`238155141a620716bff1310b0cc61564b22764b06b87b1de89a018ddbebe41a3 ./artix7/tile_type_MONITOR_MID.json`](./artix7/tile_type_MONITOR_MID.json)
* [`1b1d6fc6914a51b801b8a1ea24adb9a8093b2a8b070dbfab0be5966a043489a9 ./artix7/tile_type_MONITOR_TOP.json`](./artix7/tile_type_MONITOR_TOP.json)
* [`880cdcd99af7ea01e4ee142860e0900c6c3503da3b3582837fedba1a2cafa852 ./artix7/tile_type_NULL.json`](./artix7/tile_type_NULL.json)
* [`a1553083f3d3f703f6fdc25b2e1b5b62e2a68d4371c4edcf3cb3aa8d8e99ec87 ./artix7/tile_type_PCIE_BOT.json`](./artix7/tile_type_PCIE_BOT.json)
* [`3e075fbce2e39f99504b7e799de6aa1146aafe32d545b0c7ba791d93751ac58b ./artix7/tile_type_PCIE_INT_INTERFACE_L.json`](./artix7/tile_type_PCIE_INT_INTERFACE_L.json)
* [`7640289b2a0635eba0172f8e37e452a53912620fe00572cf57fe4ac4ae0db2be ./artix7/tile_type_PCIE_INT_INTERFACE_R.json`](./artix7/tile_type_PCIE_INT_INTERFACE_R.json)
* [`944d9c69913b23cac150f0c80c14284d57fab43f69202a6cc63afaddce23221b ./artix7/tile_type_PCIE_NULL.json`](./artix7/tile_type_PCIE_NULL.json)
* [`dc29a2768d5aafea58e032f3d303e34e5e7dae896979ef2fc2fe70165b42cf3e ./artix7/tile_type_PCIE_TOP.json`](./artix7/tile_type_PCIE_TOP.json)
* [`a01a9bfa1d6ac7762d56b57487ab1f4efa8f53e77c6fa452adfa3aff120811fb ./artix7/tile_type_RIOB33.json`](./artix7/tile_type_RIOB33.json)
* [`66ea3a8940b40915699e7e2fa37b3d65403e7f5d51afe0daf14537e662da9385 ./artix7/tile_type_RIOB33_SING.json`](./artix7/tile_type_RIOB33_SING.json)
* [`96029c4d8a29149b3aa063bbcd3a64bbbf28f987e8e491d2630f7e78d47354b2 ./artix7/tile_type_RIOI3.json`](./artix7/tile_type_RIOI3.json)
* [`6c8c8745a8bcd8ebcf6396dfda55fd7b958b2de19ac1a926e412716b7d8dd2b2 ./artix7/tile_type_RIOI3_SING.json`](./artix7/tile_type_RIOI3_SING.json)
* [`89b4d83a435609119ca878a4cdbfc3fc31c8c30d66459bf3d84b4c8c012c1139 ./artix7/tile_type_RIOI3_TBYTESRC.json`](./artix7/tile_type_RIOI3_TBYTESRC.json)
* [`e188cfd52a8cd3edb869bd29a02e95e8cfc06688727982f9c364c54b5d20c409 ./artix7/tile_type_RIOI3_TBYTETERM.json`](./artix7/tile_type_RIOI3_TBYTETERM.json)
* [`16627ffc9c74acf89474ad03993367d2210f40d4ab07a8c71c98d9ad652f2ca8 ./artix7/tile_type_R_TERM_INT.json`](./artix7/tile_type_R_TERM_INT.json)
* [`fd664b568212b0479342de300f8efc07e8b521960fbb4b9abacb71336fca773b ./artix7/tile_type_R_TERM_INT_GTX.json`](./artix7/tile_type_R_TERM_INT_GTX.json)
* [`19503481fb531f7ddc5f92fdc7c97a817ce1cf550e128604041c771f2234b7fa ./artix7/tile_type_TERM_CMT.json`](./artix7/tile_type_TERM_CMT.json)
* [`f5ebbeee5575e5fbc1fb5d532f021e4ee8647de21b3874caac655d8c849a9ff3 ./artix7/tile_type_T_TERM_INT.json`](./artix7/tile_type_T_TERM_INT.json)
* [`dee783006fa5b5964d20457323cad59171a60397d730e9fe0840389587695727 ./artix7/tile_type_VBRK.json`](./artix7/tile_type_VBRK.json)
* [`04409fb1eb974ee5af7e8115bf16aacfd4bda61094c7c4644cc020762a45f6c8 ./artix7/tile_type_VBRK_EXT.json`](./artix7/tile_type_VBRK_EXT.json)
* [`004efcd7f9e172780ca7b8c379ec329bcfc52f86beaa1d997f41dbef7ac4a242 ./artix7/tile_type_VFRAME.json`](./artix7/tile_type_VFRAME.json)
* [`1604d48580815e26069c2b4909fcc50e8e8f974ad0beb349ced2329c302bb06b ./artix7/tileconn.json`](./artix7/tileconn.json)
* [`70fc6a01f6485a7229011d894a4e1832ab3ff01d39e319f9093d58b3dc94f226 ./artix7/tilegrid.json`](./artix7/tilegrid.json)
* [`4c20ee41ea32668919b7d91a7fabe38960e0ee4d5b3b83f1d18102d48895bf1c ./artix7/xc7a35tcpg236-1.json`](./artix7/xc7a35tcpg236-1.json)
* [`ef0724733da87455426a0f833642d96e9d206d047f4eb97072c3093f80c40d7d ./artix7/xc7a35tcpg236-1.yaml`](./artix7/xc7a35tcpg236-1.yaml)
* [`4c20ee41ea32668919b7d91a7fabe38960e0ee4d5b3b83f1d18102d48895bf1c ./artix7/xc7a35tcsg324-1.json`](./artix7/xc7a35tcsg324-1.json)
* [`ef0724733da87455426a0f833642d96e9d206d047f4eb97072c3093f80c40d7d ./artix7/xc7a35tcsg324-1.yaml`](./artix7/xc7a35tcsg324-1.yaml)
* [`bee2616f3f373813e4539952e1185dd6e39fb0aec4cd2a2b42451318c6cd2de0 ./artix7/xc7a50tfgg484-1.json`](./artix7/xc7a50tfgg484-1.json)
* [`41c360b1e2f7e08b9051f1160a34954ce4c05a445a07f226f1f4059caf1fa1d3 ./artix7/xc7a50tfgg484-1.yaml`](./artix7/xc7a50tfgg484-1.yaml)
## Database for [kintex7](kintex7/)
### Settings
Created using following [settings.sh (sha256: 63265e0520e5cc4aa92f47568fe01fdfd80c95fe76bb0a7fc3aefb3e1933ff45)](https://github.com/SymbiFlow/prjxray/blob/afe50c68c464c0cd4a3fa92b6a07c9abbe41682f/database/kintex7/settings.sh)
Created using following [settings/kintex7.sh (sha256: b15d95afeae26cb0236f2a17b411f0242e4af0f3664d49dda936465ad3fa2b25)](https://github.com/SymbiFlow/prjxray/blob/afe50c68c464c0cd4a3fa92b6a07c9abbe41682f/settings/kintex7.sh)
```shell
export XRAY_DATABASE="kintex7"
export XRAY_PART="xc7k70tfbg676-2"
@ -308,9 +317,9 @@ export XRAY_ROI_FRAMES="0x00000000:0xffffffff"
export XRAY_ROI_TILEGRID="SLICE_X0Y50:SLICE_X19Y99 DSP48_X0Y20:DSP48_X0Y39 RAMB18_X0Y20:RAMB18_X0Y39 RAMB36_X0Y10:RAMB36_X0Y19"
# These settings must remain in sync
export XRAY_ROI="SLICE_X0Y50:SLICE_X19Y99 DSP48_X0Y20:DSP48_X0Y39 RAMB18_X0Y20:RAMB18_X0Y39 RAMB36_X0Y10:RAMB36_X0Y19"
export XRAY_ROI="SLICE_X0Y50:SLICE_X19Y99 DSP48_X0Y20:DSP48_X0Y39 RAMB18_X0Y20:RAMB18_X0Y39 RAMB36_X0Y10:RAMB36_X0Y19 IOB_X0Y50:IOB_X0Y99"
# Part of CMT X0Y1
export XRAY_ROI_GRID_X1="9"
export XRAY_ROI_GRID_X1="0"
export XRAY_ROI_GRID_X2="38"
# Include VBRK / VTERM
export XRAY_ROI_GRID_Y1="104"
@ -325,7 +334,9 @@ export XRAY_PIN_04="M19"
export XRAY_PIN_05="M20"
export XRAY_PIN_06="M21"
source $(dirname ${BASH_SOURCE[0]})/../../utils/environment.sh
source $(dirname ${BASH_SOURCE[0]})/../utils/environment.sh
init_db
```
### [Results](kintex7/)
@ -337,194 +348,237 @@ Results have checksums;
* [`48d52092f62239a82141b89539c690a405a54822ba04d0e284d9ffd300811d8c ./kintex7/mask_clbll_r.db`](./kintex7/mask_clbll_r.db)
* [`2f2a37cca066562d79b6a7ecc89ff750c30db2cb355c0665379b356c7c8d41bd ./kintex7/mask_clblm_l.db`](./kintex7/mask_clblm_l.db)
* [`48d52092f62239a82141b89539c690a405a54822ba04d0e284d9ffd300811d8c ./kintex7/mask_clblm_r.db`](./kintex7/mask_clblm_r.db)
* [`c5aabee9a52c0eb671d569264639b6903e85e76e50ce57af8b7033062e81c2f5 ./kintex7/mask_hclk_l.db`](./kintex7/mask_hclk_l.db)
* [`c5aabee9a52c0eb671d569264639b6903e85e76e50ce57af8b7033062e81c2f5 ./kintex7/mask_hclk_r.db`](./kintex7/mask_hclk_r.db)
* [`6baea72435613b87334f95cfe2b1ab36da4d57ada20b71a7dd870715b3e430c4 ./kintex7/ppips_clbll_l.db`](./kintex7/ppips_clbll_l.db)
* [`3955d590e8ee64c843bb80f911a08781c1bac63e71b577436ae1f44195a88e22 ./kintex7/ppips_clbll_r.db`](./kintex7/ppips_clbll_r.db)
* [`29f175153821dc13989eb580676ff0007e108d911275a74e7ebe45e819c14eaf ./kintex7/ppips_clblm_l.db`](./kintex7/ppips_clblm_l.db)
* [`52b53ae735d40632403283ab720db2172794a22c5245b3da7693b264d69a122d ./kintex7/ppips_clblm_r.db`](./kintex7/ppips_clblm_r.db)
* [`76d1e0bd4b7ad492cf3fe8698b2b5f46f7dcc5fe446984e5dccae373c63edafd ./kintex7/mask_hclk_l.db`](./kintex7/mask_hclk_l.db)
* [`76d1e0bd4b7ad492cf3fe8698b2b5f46f7dcc5fe446984e5dccae373c63edafd ./kintex7/mask_hclk_r.db`](./kintex7/mask_hclk_r.db)
* [`b4ffdb01ca695c7d52f34b88508aef6d596377fcffd7fa5e197212acc4b00e9a ./kintex7/ppips_clbll_l.db`](./kintex7/ppips_clbll_l.db)
* [`bb75573609f56f082544644ecbb39125d023809340f7a30180cb9df823585009 ./kintex7/ppips_clbll_r.db`](./kintex7/ppips_clbll_r.db)
* [`a5357b0c018ac9c8c1f8cccf3c36b69f66ffd0e29039dfadb5a829caafd71a73 ./kintex7/ppips_clblm_l.db`](./kintex7/ppips_clblm_l.db)
* [`15424ecbd5816143def2dcb20fc9cfae5ec4e11a1a5cfc1848e71b2904a1a713 ./kintex7/ppips_clblm_r.db`](./kintex7/ppips_clblm_r.db)
* [`6d35b568a51f9b6761da2470a71738b2477ef72c16068a529ae8eb52b65bf17a ./kintex7/ppips_hclk_l.db`](./kintex7/ppips_hclk_l.db)
* [`81e0696179a33bdf8d2279a53b406911a403d50224355e9ad29eccee01a70305 ./kintex7/ppips_hclk_r.db`](./kintex7/ppips_hclk_r.db)
* [`be617c15d1ec311b6249791414bbd69380fe90b476353cbb2fc2a7cb06f5029d ./kintex7/ppips_int_l.db`](./kintex7/ppips_int_l.db)
* [`a1423859c97a82dcfb114644f50b991db4ca7e0996e6d1ae4d2c97bfdfcb723d ./kintex7/ppips_int_r.db`](./kintex7/ppips_int_r.db)
* [`7966925d50ebf5296f273ac64d03614ce0f452209bc0a4bde2e3d30f2fbd9a53 ./kintex7/segbits_bram_l.block_ram.db`](./kintex7/segbits_bram_l.block_ram.db)
* [`aaa1d706495108244ce39af259fe7a0b636f3e5e0d911e2bce23f904d8816f1a ./kintex7/segbits_bram_l.db`](./kintex7/segbits_bram_l.db)
* [`7b958779367cfa8ab94fc1358241bf2704f0f165eb7809653d527ecef77bb6b1 ./kintex7/segbits_bram_r.block_ram.db`](./kintex7/segbits_bram_r.block_ram.db)
* [`c5335d22c23e0ef7dc23d66388d9586fef598680d429f96d4308a21a345edc22 ./kintex7/segbits_bram_r.db`](./kintex7/segbits_bram_r.db)
* [`6ebf61394acdcf59009aa7f43248d87aaabde0bd13db4e64d180d6efeb32e4f9 ./kintex7/segbits_clbll_l.db`](./kintex7/segbits_clbll_l.db)
* [`f9165aded2d9ee5b60cda1bf043e38fd70f984f190cdf8f52aff7118ac07575d ./kintex7/segbits_clbll_r.db`](./kintex7/segbits_clbll_r.db)
* [`b2cb977a0bbdcbe3aab6b7bc162776799a2b9ada25b4f937b57073a906e8d167 ./kintex7/segbits_clblm_l.db`](./kintex7/segbits_clblm_l.db)
* [`6ed746de31fb69b018835239edcf191945982e9b705711e4b174031838b3bc90 ./kintex7/segbits_clblm_r.db`](./kintex7/segbits_clblm_r.db)
* [`df496c4d335fac0c379497ff0a75ba4f5c5c25bcce79f9c7a72d5f08066310db ./kintex7/segbits_hclk_l.db`](./kintex7/segbits_hclk_l.db)
* [`5e22f758a04eab3185b2453c9994aa2fa48f50ca8a6b49bf82e8fc4351f23a5c ./kintex7/segbits_hclk_r.db`](./kintex7/segbits_hclk_r.db)
* [`e1628ab6bdb2e040f019041a57101eff46a46b7d9010c5662b28570fddc26463 ./kintex7/segbits_int_l.db`](./kintex7/segbits_int_l.db)
* [`9f72ee9d65e9b05274b85cf1ef47bbb7438eb127925f11b23733736e25e2fec8 ./kintex7/segbits_int_r.db`](./kintex7/segbits_int_r.db)
* [`63265e0520e5cc4aa92f47568fe01fdfd80c95fe76bb0a7fc3aefb3e1933ff45 ./kintex7/settings.sh`](./kintex7/settings.sh)
* [`6a998dd55a7aa4ab33db25db7b5167d57f3d708713baf1fca394dc2940f12007 ./kintex7/site_type_BSCAN.json`](./kintex7/site_type_BSCAN.json)
* [`7f59ea08fa5dbf9ce84ea26f03f13cd02683fce9cdd98621e501e422bf09d165 ./kintex7/site_type_BUFGCTRL.json`](./kintex7/site_type_BUFGCTRL.json)
* [`2d6c78790d74503f0810356de3a765b380b319f09a41593bc8cbe8979defd1f7 ./kintex7/site_type_BUFHCE.json`](./kintex7/site_type_BUFHCE.json)
* [`7d2ad5e0c2a12242cabe03aa9a89bdc1ad4413720c45243809371e06be84a88b ./kintex7/site_type_BUFIO.json`](./kintex7/site_type_BUFIO.json)
* [`99ac6ee5e9381bc68e9e7c0ba1e75779a80360b3854b87cc124819a17cd23a75 ./kintex7/site_type_BUFMRCE.json`](./kintex7/site_type_BUFMRCE.json)
* [`ea18314ade2d867b7ee931c71ccca7780dcda5da63e4c986a5db37508c8df60a ./kintex7/site_type_BUFR.json`](./kintex7/site_type_BUFR.json)
* [`15b8fa9480b7f789bf65aca97263c2b97d120eb3ab79d4330d17e39c36bd0131 ./kintex7/site_type_CAPTURE.json`](./kintex7/site_type_CAPTURE.json)
* [`af89e5523c49b0ede53efd5c2304d1e1a5efb553b52ec873526923f2fd019705 ./kintex7/site_type_DCIRESET.json`](./kintex7/site_type_DCIRESET.json)
* [`79effefe83be725ab9cf4c1167e6e2582144317654c179b5076ae19f7462403b ./kintex7/site_type_DNA_PORT.json`](./kintex7/site_type_DNA_PORT.json)
* [`2326eb345b6c10062379bbb3c7afe5ebc4b9ecbc104f8947158dbae09c09e7c8 ./kintex7/site_type_DSP48E1.json`](./kintex7/site_type_DSP48E1.json)
* [`75db786def8e1871ca3fd7c65d6481a53464f000343b32155ee3a05dd86eb0b3 ./kintex7/site_type_EFUSE_USR.json`](./kintex7/site_type_EFUSE_USR.json)
* [`a9e6d74302ee507649432e33e31d21d8feaf6b51e2ae0f26a579c16f57f59512 ./kintex7/site_type_FIFO18E1.json`](./kintex7/site_type_FIFO18E1.json)
* [`0d1ff1869cb0c2ceb18b7d6e4d53abc15db8712ed4f6845c6ed093e0d28d2fe8 ./kintex7/site_type_FRAME_ECC.json`](./kintex7/site_type_FRAME_ECC.json)
* [`05ed1223045527c7e10b5a0d922d083578688f8a0810e875c278ba8d47d66c20 ./kintex7/site_type_GTXE2_CHANNEL.json`](./kintex7/site_type_GTXE2_CHANNEL.json)
* [`5737b0e28f7a90325af014732099cbb9f08ede99b3b1000fd5570f71c122bf40 ./kintex7/site_type_GTXE2_COMMON.json`](./kintex7/site_type_GTXE2_COMMON.json)
* [`e4b974ca43493be5444c2c2a4a0c243712e882499f8ca87efc38bdca267cc988 ./kintex7/site_type_IBUFDS_GTE2.json`](./kintex7/site_type_IBUFDS_GTE2.json)
* [`a2514cd2da5e5cabdc3babd476b014b6b44a2cc8fca19f2f2785cb207abbb751 ./kintex7/site_type_ICAP.json`](./kintex7/site_type_ICAP.json)
* [`d23176a42d861807d5bd2559e58f31e3ffe516d3c0597ace669c88f0f8bdd145 ./kintex7/site_type_IDELAYCTRL.json`](./kintex7/site_type_IDELAYCTRL.json)
* [`c1a434d73a7f5f724d409b15605b5f50d7f4ac5439a81318615abb2ba54df9bb ./kintex7/site_type_IDELAYE2_FINEDELAY.json`](./kintex7/site_type_IDELAYE2_FINEDELAY.json)
* [`2bf5daae4d45e9b6d65fbfa7c73426c896bc071d9b577b57371f8570836acb86 ./kintex7/site_type_IDELAYE2.json`](./kintex7/site_type_IDELAYE2.json)
* [`6f75612da1fead215c14b426955b95c43da5a5ecc2186ae44e6ef8b002a39601 ./kintex7/site_type_ILOGICE2.json`](./kintex7/site_type_ILOGICE2.json)
* [`05ffeb28332d5d17fc32b2410da41b0b97426a01bb4a3cd84849ab386b50c543 ./kintex7/site_type_ILOGICE3.json`](./kintex7/site_type_ILOGICE3.json)
* [`ef48fb9be2319b50b808ead0726bc6a037377fe10fbf3d22ca9acd29def80e2b ./kintex7/site_type_IN_FIFO.json`](./kintex7/site_type_IN_FIFO.json)
* [`cb9bf6a49c387a625cbe8afe2d163d934d8252144a4ebcb36ac141d6ee9de378 ./kintex7/site_type_IOB18.json`](./kintex7/site_type_IOB18.json)
* [`a724418b2e0edafa67d9d0c0b191e70996208605f776928e48e421ec3a9735b7 ./kintex7/site_type_IOB18M.json`](./kintex7/site_type_IOB18M.json)
* [`ed03ec4038f98d25d4ad1239ecc0fb7ab3c1e65ff5f0202dd2ce346f4c951169 ./kintex7/site_type_IOB18S.json`](./kintex7/site_type_IOB18S.json)
* [`c98ef8397786c5c71b2c5a43824ce47f0e46c93424eef58ad47bf0f7c7d42675 ./kintex7/site_type_IOB33.json`](./kintex7/site_type_IOB33.json)
* [`76e2eb01e49adb5b5d7586d57b5dc07b2104aac9295f173d2b2b3724a86a9eb0 ./kintex7/site_type_IOB33M.json`](./kintex7/site_type_IOB33M.json)
* [`ccdec6f60ba548d85b3b24345c0fbc4b5e703c0de936f12c09c5c0fb822fcf3e ./kintex7/site_type_IOB33S.json`](./kintex7/site_type_IOB33S.json)
* [`7d0bc5533db085e0ef68a2dbd16906b4936bb35efa4790953c2c4ee607f1ed28 ./kintex7/site_type_IPAD.json`](./kintex7/site_type_IPAD.json)
* [`bf073833d9a7b9e125d4829e464cdd67a61bf9195d0dd7854f1fa6397014aacc ./kintex7/site_type_MMCME2_ADV.json`](./kintex7/site_type_MMCME2_ADV.json)
* [`0f76338fa2b9ee17a822e82126c9b94afd83145fbae7f28ca40545bb63ae893a ./kintex7/site_type_ODELAYE2.json`](./kintex7/site_type_ODELAYE2.json)
* [`0b567e91c282fb210517867640479d683307861470b2e10f39c3300cdf3a6887 ./kintex7/site_type_OLOGICE2.json`](./kintex7/site_type_OLOGICE2.json)
* [`186eac82246b8b10da9abab93b15f638bdb8ef446ce0e4b4ceb797e2091132dd ./kintex7/site_type_OLOGICE3.json`](./kintex7/site_type_OLOGICE3.json)
* [`b4670a20c46552416276ba8e5442b4c3d24c6215650a212f00f874dc78371bca ./kintex7/site_type_OPAD.json`](./kintex7/site_type_OPAD.json)
* [`776619b1507bfe996cfa7b900058cff911bd96a29dac1b33e5b29aa662053aad ./kintex7/site_type_OUT_FIFO.json`](./kintex7/site_type_OUT_FIFO.json)
* [`06edd04ea43682f65f2d8cbc6282d5e10385c23e75bd61ddd99c4e6ce2b9fcf6 ./kintex7/site_type_PCIE_2_1.json`](./kintex7/site_type_PCIE_2_1.json)
* [`311eda695286ee7edd51cc78c3c6bdbe9901bcb515308a17572302af321fdbc4 ./kintex7/site_type_PHASER_IN_PHY.json`](./kintex7/site_type_PHASER_IN_PHY.json)
* [`2474fdfcd0bd228964e62f4875e9684e15984ee57e40b17f6759a5897148cba5 ./kintex7/site_type_PHASER_OUT_PHY.json`](./kintex7/site_type_PHASER_OUT_PHY.json)
* [`f8aefb394bd6cef6244a56a4376bf0a44ce368741dfbce8cf7f5df45a71c47a3 ./kintex7/site_type_PHASER_REF.json`](./kintex7/site_type_PHASER_REF.json)
* [`01733676f386e217548135ed297b2fa73e0d0d17003b84513708ed8508f447ce ./kintex7/site_type_PHY_CONTROL.json`](./kintex7/site_type_PHY_CONTROL.json)
* [`e314d184ac0bbe656ca4d34c33af80149b4d7dbe6798094de089462f78b52405 ./kintex7/site_type_PLLE2_ADV.json`](./kintex7/site_type_PLLE2_ADV.json)
* [`58897a08e0442222f117be75393c6b46360933abc71ff1de142ba7adcaabfa3f ./kintex7/site_type_PMV2.json`](./kintex7/site_type_PMV2.json)
* [`110126d521d4744019d75f9c0bdcef76851b2c8f003fed0d5dbb7f7806aadae7 ./kintex7/site_type_RAMB18E1.json`](./kintex7/site_type_RAMB18E1.json)
* [`1ab295693d283025d16966f5ed48515046fea1078529d48e0eab5eef732bcb40 ./kintex7/site_type_RAMBFIFO36E1.json`](./kintex7/site_type_RAMBFIFO36E1.json)
* [`586145c0b465d7ac945746193cf4f38ec5bb26bbc52997bce47d5fbdd9d0c241 ./kintex7/site_type_SLICEL.json`](./kintex7/site_type_SLICEL.json)
* [`201ecff6bb7d78c8597d467e55486fc00b2ad95a6a7dee0cd98346ab9e8c888a ./kintex7/site_type_SLICEM.json`](./kintex7/site_type_SLICEM.json)
* [`872bc95eb5f912fc95ca2ca18960b14b9cc20f00bf30b7227d0c6c9b0f3bbeb0 ./kintex7/site_type_STARTUP.json`](./kintex7/site_type_STARTUP.json)
* [`db8c88384575a7e0562692550bdba7a4089ea5fabe451bf58403d3a85af419a0 ./kintex7/site_type_TIEOFF.json`](./kintex7/site_type_TIEOFF.json)
* [`4d6130cb2604efae8ca5d628b95be2549083c16c639d335bdc906924e37ec28c ./kintex7/site_type_USR_ACCESS.json`](./kintex7/site_type_USR_ACCESS.json)
* [`dbf0ff3b27d1fac02572351765f1b17b3e950ed4e8fe95ac6bcd71012e4f7b2d ./kintex7/site_type_XADC.json`](./kintex7/site_type_XADC.json)
* [`eaea5154fc105272fef0c39faebac6089fb5a10bd9c4c6dea50332639f04380b ./kintex7/tileconn.json`](./kintex7/tileconn.json)
* [`eeef94852cdce206d5958d0d2e5754459cfb2e7c843c12871718bea8e202daa3 ./kintex7/tilegrid.json`](./kintex7/tilegrid.json)
* [`a93b4be2b2832d1a9240b892f6d8db469f3d9cf6229cc6856a197e854f4abc8a ./kintex7/tile_type_BRAM_INT_INTERFACE_L.json`](./kintex7/tile_type_BRAM_INT_INTERFACE_L.json)
* [`fff3e640e286158767fc484ec932d0ce7eba48c1168798c11c7779426a846004 ./kintex7/tile_type_BRAM_INT_INTERFACE_R.json`](./kintex7/tile_type_BRAM_INT_INTERFACE_R.json)
* [`fe1ba3b913bc91940d08dc034ef0c5ad7d530d15b5458c7240abedb4400c52ad ./kintex7/tile_type_BRAM_L.json`](./kintex7/tile_type_BRAM_L.json)
* [`0b3e0084e0ee328d9fc74180b3f10468d575ada3850117de77d6789bde11c3fa ./kintex7/tile_type_BRAM_R.json`](./kintex7/tile_type_BRAM_R.json)
* [`db6c15155f364bd395363fb230bf43119a0081e41d659b0afb01dc5144da723a ./kintex7/tile_type_BRKH_BRAM.json`](./kintex7/tile_type_BRKH_BRAM.json)
* [`9d3a3030a2e3b2cf1ac5325613d6f97121d92520573f5623f4bca7cc1f93f488 ./kintex7/tile_type_BRKH_B_TERM_INT.json`](./kintex7/tile_type_BRKH_B_TERM_INT.json)
* [`118df8447c839ff5b9e2325e328c0251d67f9bf5db209b7f2782f9235f240311 ./kintex7/tile_type_BRKH_CLB.json`](./kintex7/tile_type_BRKH_CLB.json)
* [`0d3e86aab90d3bb52dd77b187695d3cb3777e46336d1fc1725b6329b8902b626 ./kintex7/tile_type_BRKH_CLK.json`](./kintex7/tile_type_BRKH_CLK.json)
* [`7679aeafb655e2bd58deddc3ab9746ee00e801e4f6b3cd93e17d66f211beb288 ./kintex7/tile_type_BRKH_CMT.json`](./kintex7/tile_type_BRKH_CMT.json)
* [`5c19ea98b80ca36a2a91388352ebd37bba5b85e2580a5cb10ef1b9a31b26a009 ./kintex7/tile_type_BRKH_DSP_L.json`](./kintex7/tile_type_BRKH_DSP_L.json)
* [`15db89f4dc5243d4e315e8130937270919397031ec30ec764fde6400f9b5d651 ./kintex7/tile_type_BRKH_DSP_R.json`](./kintex7/tile_type_BRKH_DSP_R.json)
* [`856754623cc87f0058d073999e25faab904f7edef7beb0a818e60ab853fa5b97 ./kintex7/tile_type_BRKH_GTX.json`](./kintex7/tile_type_BRKH_GTX.json)
* [`f2e45380bacb76cfb51982ce6e561a9af21d8df0e51bbf0d1ab946e0372739e1 ./kintex7/tile_type_BRKH_INT.json`](./kintex7/tile_type_BRKH_INT.json)
* [`f03132d07804f511371569891bf51d6c14490ee9460f57728e179ee2a7be4cdc ./kintex7/tile_type_BRKH_TERM_INT.json`](./kintex7/tile_type_BRKH_TERM_INT.json)
* [`3c0cc073cc1c80424074ca96a1a87099e040512d279c313109b96146adf94c8e ./kintex7/tile_type_B_TERM_INT.json`](./kintex7/tile_type_B_TERM_INT.json)
* [`b4cf053f06f3965af2f05b74e43eff6bdf24daf8ee2cb61ddeeee70e71ed660d ./kintex7/tile_type_CFG_CENTER_BOT.json`](./kintex7/tile_type_CFG_CENTER_BOT.json)
* [`82468ad16be6809588902afecfb06ec15ec7408b6cd1e3b99fe14430a62e11a2 ./kintex7/tile_type_CFG_CENTER_MID.json`](./kintex7/tile_type_CFG_CENTER_MID.json)
* [`413970a4868c43567623a14b4093be69899de10ebba2f62fd06137660b35b6dc ./kintex7/tile_type_CFG_CENTER_TOP.json`](./kintex7/tile_type_CFG_CENTER_TOP.json)
* [`51e08a3158bfddccb5c43b0dc7ff6f55fe303df871795fdd921b8963e619e95c ./kintex7/tile_type_CLBLL_L.json`](./kintex7/tile_type_CLBLL_L.json)
* [`9b2e66795a517636d5af80c81ec7ac1c8189a553648a9b2d767c5ec3e9819508 ./kintex7/tile_type_CLBLL_R.json`](./kintex7/tile_type_CLBLL_R.json)
* [`0b0e0bb74eb6b8864a94663ec9adb7f14f29ebdffafb3088bbf794b51935a322 ./kintex7/tile_type_CLBLM_L.json`](./kintex7/tile_type_CLBLM_L.json)
* [`ec924ac530dbd8592880606da2244a55d19c05a14357ab8032aecc7ef2eb0fa9 ./kintex7/tile_type_CLBLM_R.json`](./kintex7/tile_type_CLBLM_R.json)
* [`656de9ce6a18a058c083d07bae3433fde5899680ac68165e9e8430023c2f123c ./kintex7/tile_type_CLK_BUFG_BOT_R.json`](./kintex7/tile_type_CLK_BUFG_BOT_R.json)
* [`6aa792786a1fbb38c20f1aceba3936775473d8dff5529f7aa41e8da38eee4c0c ./kintex7/tile_type_CLK_BUFG_REBUF.json`](./kintex7/tile_type_CLK_BUFG_REBUF.json)
* [`c478ac96f632d69db13f870eab1d86a84b3e47af5a2b4b6b93c3c71b3d75e87e ./kintex7/tile_type_CLK_BUFG_TOP_R.json`](./kintex7/tile_type_CLK_BUFG_TOP_R.json)
* [`d6df6130236178fdfecd77e7ab871dd7f5f5d91270aff446bbc6082b5d611f50 ./kintex7/tile_type_CLK_FEED.json`](./kintex7/tile_type_CLK_FEED.json)
* [`1a9f04a7268c7db635363e4c6d5885b3979cf9d7d3c67a202b3ac3af5c124122 ./kintex7/tile_type_CLK_HROW_BOT_R.json`](./kintex7/tile_type_CLK_HROW_BOT_R.json)
* [`b0b961602f0f9fdb17e2ca7566ef85543f0734b7e4e9822d4e5ce3763def1bdc ./kintex7/tile_type_CLK_HROW_TOP_R.json`](./kintex7/tile_type_CLK_HROW_TOP_R.json)
* [`54365a8bfc347ca228266b6a682e0ccb1a5c98283c90efc3b738b962134d62ba ./kintex7/tile_type_CLK_MTBF2.json`](./kintex7/tile_type_CLK_MTBF2.json)
* [`60f5de137907091563bc64aadc4caab115d6527c31525c6ede9148b4f9b5f3d9 ./kintex7/tile_type_CLK_PMV2.json`](./kintex7/tile_type_CLK_PMV2.json)
* [`392df005504cbc65b160a7eacf01d885617b0c2869269ba5de7b490c069993fe ./kintex7/tile_type_CLK_PMV2_SVT.json`](./kintex7/tile_type_CLK_PMV2_SVT.json)
* [`aeb291f8b0d6e930b1a9dfeddf444f78cf7b8a3e1b4bfd68695a610b4a56df15 ./kintex7/tile_type_CLK_PMVIOB.json`](./kintex7/tile_type_CLK_PMVIOB.json)
* [`2cf3b04cc58a0d9c9655d8a002ad789f15cc0da42ce797d616501af10ceaf3e5 ./kintex7/tile_type_CLK_PMV.json`](./kintex7/tile_type_CLK_PMV.json)
* [`3049d7d2fd6c902737f1a17661eea9fd8e195e7623e602737e5573bc226b659e ./kintex7/tile_type_CLK_TERM.json`](./kintex7/tile_type_CLK_TERM.json)
* [`f34c8817cd592fbd84bf5320aa2afe886e400219227e23106ab20bb14bf6b0e9 ./kintex7/tile_type_CMT_FIFO_L.json`](./kintex7/tile_type_CMT_FIFO_L.json)
* [`3f5c5c44013567f9162fecd20bc76a888f5426f363445c83a90e7765e7ac5328 ./kintex7/tile_type_CMT_FIFO_R.json`](./kintex7/tile_type_CMT_FIFO_R.json)
* [`ee092eb4fe6b8acdd0e145c57e0555390668dfe0b4fb4ecf72f1104a1f464380 ./kintex7/tile_type_CMT_PMV.json`](./kintex7/tile_type_CMT_PMV.json)
* [`f14e9d7dc485f0f7feba84cbc2824d2f6f49f78db009feaef3425a4bf818454a ./kintex7/tile_type_CMT_PMV_L.json`](./kintex7/tile_type_CMT_PMV_L.json)
* [`e7931a0f222780de2736402376667bfa06deaf5631af6e3ae7ecdc04ef4cf0e9 ./kintex7/tile_type_CMT_TOP_L_LOWER_B.json`](./kintex7/tile_type_CMT_TOP_L_LOWER_B.json)
* [`a6e0cf15801f96b7dbb09beb5c50d0468a971b615707990c9dc6f9b2606b9fcf ./kintex7/tile_type_CMT_TOP_L_LOWER_T.json`](./kintex7/tile_type_CMT_TOP_L_LOWER_T.json)
* [`be837955af15b1b057d389f90db066e7364a4aabc63174797157028d950a0736 ./kintex7/tile_type_CMT_TOP_L_UPPER_B.json`](./kintex7/tile_type_CMT_TOP_L_UPPER_B.json)
* [`601852861f50e91ec1398eeb464500f8364fea828630ce02e5feb3c2754eab1e ./kintex7/tile_type_CMT_TOP_L_UPPER_T.json`](./kintex7/tile_type_CMT_TOP_L_UPPER_T.json)
* [`41f0cdfdfe2a777484296d12f667fe87051c918264be5548cf1e8f8c0a82d6fa ./kintex7/tile_type_CMT_TOP_R_LOWER_B.json`](./kintex7/tile_type_CMT_TOP_R_LOWER_B.json)
* [`769bdd34e337f36851ea020d58e56fd4e3b574b82e64b165c9f9e97c3e7a1619 ./kintex7/tile_type_CMT_TOP_R_LOWER_T.json`](./kintex7/tile_type_CMT_TOP_R_LOWER_T.json)
* [`fabeef8ceadc3b73a5130c62a4ec27196d86bea851d9e4b65fab4a5c869ddfbb ./kintex7/tile_type_CMT_TOP_R_UPPER_B.json`](./kintex7/tile_type_CMT_TOP_R_UPPER_B.json)
* [`e91fbf80b93b718cf155474a3aa109323562c24e436fcd0d1ecfd49dae334c85 ./kintex7/tile_type_CMT_TOP_R_UPPER_T.json`](./kintex7/tile_type_CMT_TOP_R_UPPER_T.json)
* [`03a09a31d4f5cbacfcbc57cc3d7d02cb2cc1ff385fed3dce09e13656dbe78156 ./kintex7/tile_type_DSP_L.json`](./kintex7/tile_type_DSP_L.json)
* [`6a81b824a37477aa4aa885f05e03c730da5bce3175a693cea55e1c9ca3ad18d4 ./kintex7/tile_type_DSP_R.json`](./kintex7/tile_type_DSP_R.json)
* [`d04fd948a2dc32da998526ede6ccac34e621bf8e36bcc31169c33044b2d9b0d9 ./kintex7/tile_type_GTX_CHANNEL_0.json`](./kintex7/tile_type_GTX_CHANNEL_0.json)
* [`b91cd38187c42ff361ea0800a164f450b5ea391b6eccbfef40a49f279d63671c ./kintex7/tile_type_GTX_CHANNEL_1.json`](./kintex7/tile_type_GTX_CHANNEL_1.json)
* [`12e3a21b5755c12735f8de94a8d7b1007bdefff3d88e673a02987aa7cde40e5c ./kintex7/tile_type_GTX_CHANNEL_2.json`](./kintex7/tile_type_GTX_CHANNEL_2.json)
* [`e64e65fce02864e351975dffc0847c58dc6699cac2c7a883c6373eaf4cf30933 ./kintex7/tile_type_GTX_CHANNEL_3.json`](./kintex7/tile_type_GTX_CHANNEL_3.json)
* [`8a473573c5ec94768f3755b8f88a59de13e9af8fffcc6107d7515f38f6640aa0 ./kintex7/tile_type_GTX_COMMON.json`](./kintex7/tile_type_GTX_COMMON.json)
* [`cc2506b94140f6190f373e1e6f0c46793545b6a43a74f8b5a2a1a7ada4c9ec0e ./kintex7/tile_type_GTX_INT_INTERFACE.json`](./kintex7/tile_type_GTX_INT_INTERFACE.json)
* [`354ef04f0bdda1de5dcdcd33f5755a1d23ed12736f9130cf7be4b1177331ac42 ./kintex7/tile_type_HCLK_BRAM.json`](./kintex7/tile_type_HCLK_BRAM.json)
* [`df7c1fe5e634ef598e274709c416a89cbb7a466467ba8bb7aa2a06c92271f2ef ./kintex7/tile_type_HCLK_CLB.json`](./kintex7/tile_type_HCLK_CLB.json)
* [`28bf8be9e5b51f2125c8af8a9e4645494bc09265f212a19762dca8731934dd29 ./kintex7/tile_type_HCLK_CMT.json`](./kintex7/tile_type_HCLK_CMT.json)
* [`1a3eaf022b48825d6054418bf8c6eb9813fdfde0ed316d9ce2195559bb2c9b75 ./kintex7/tile_type_HCLK_CMT_L.json`](./kintex7/tile_type_HCLK_CMT_L.json)
* [`ba1573347a1e8aaf273177dd9a47ae0cbb460031944c4e9207aaeec06e6d6f3d ./kintex7/tile_type_HCLK_DSP_L.json`](./kintex7/tile_type_HCLK_DSP_L.json)
* [`1558e3a24f99161db174a0000aa7bf463ea2f658fdc0d5de95857c63e4781e76 ./kintex7/tile_type_HCLK_DSP_R.json`](./kintex7/tile_type_HCLK_DSP_R.json)
* [`981440f3c25fe99c89e59397d1f53ae2ea0ede7bf3b31ccd455a3f37cc1aa7df ./kintex7/tile_type_HCLK_FEEDTHRU_1.json`](./kintex7/tile_type_HCLK_FEEDTHRU_1.json)
* [`3114e5e086d22c789be17eab304f8cdc111c6a16815206ecabe587b47821d189 ./kintex7/tile_type_HCLK_FEEDTHRU_2.json`](./kintex7/tile_type_HCLK_FEEDTHRU_2.json)
* [`b41e34860cc61a3ddfe4237aca23aa6f076c91c8419e432bad2b8808a0e2f066 ./kintex7/tile_type_HCLK_FIFO_L.json`](./kintex7/tile_type_HCLK_FIFO_L.json)
* [`7ab3f91abd87e8fc978a8c565578f62a62ca9f9f3a0f91ca5fc1f12eee48e24d ./kintex7/tile_type_HCLK_GTX.json`](./kintex7/tile_type_HCLK_GTX.json)
* [`e9b15f998078da307163484c613e6428527269203566108aced10b9d10b5330c ./kintex7/tile_type_HCLK_INT_INTERFACE.json`](./kintex7/tile_type_HCLK_INT_INTERFACE.json)
* [`89ccb8895863d40efc4a2d2af8df687a12ddd32b77b81ace67263b1118a3597d ./kintex7/tile_type_HCLK_IOB.json`](./kintex7/tile_type_HCLK_IOB.json)
* [`6ea4fc281d2c2a2becc5ae9ac19a59b19d491bab36a16397e58327fae820350b ./kintex7/tile_type_HCLK_IOI3.json`](./kintex7/tile_type_HCLK_IOI3.json)
* [`04ea9ae2d99f532b1146ff7e3246c4b77d43b03ea82d52d9fb58931da2355601 ./kintex7/tile_type_HCLK_IOI.json`](./kintex7/tile_type_HCLK_IOI.json)
* [`06bf665ee2c3cedd70c74dc2a62681b5f1bb3b3068672389fafd11c6eef95b2e ./kintex7/tile_type_HCLK_L_BOT_UTURN.json`](./kintex7/tile_type_HCLK_L_BOT_UTURN.json)
* [`416fcad956b2082d8a17e57190f1470171f134397a4cdb23beccc35edcd58c50 ./kintex7/tile_type_HCLK_L.json`](./kintex7/tile_type_HCLK_L.json)
* [`fa5fe9cf004090046dc5a6829410efb4379a9670f0fdd01e7bb8a8c1bb01bff0 ./kintex7/tile_type_HCLK_R_BOT_UTURN.json`](./kintex7/tile_type_HCLK_R_BOT_UTURN.json)
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* [`b371b59e75bb9b18ba85b6ad43eaae3defe411a77c383c2c65780d8763c90f98 ./kintex7/tile_type_HCLK_TERM_GTX.json`](./kintex7/tile_type_HCLK_TERM_GTX.json)
* [`3713a04488775af071b9488eb191415e084b3c17e9a03ab38e514b61d822172e ./kintex7/tile_type_HCLK_TERM.json`](./kintex7/tile_type_HCLK_TERM.json)
* [`29f2633c9d8109d756ca8bafb3537d8bbfebb7f4999a25d41ed7176b9f2e8258 ./kintex7/tile_type_HCLK_VBRK.json`](./kintex7/tile_type_HCLK_VBRK.json)
* [`5c818e93dedf3f75062bca58782ac334a9c25bece6406766fb72c329ba7f67b7 ./kintex7/tile_type_HCLK_VFRAME.json`](./kintex7/tile_type_HCLK_VFRAME.json)
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* [`fc80af4e87d86b5b5554e1b44546440bfab85bc4ae1557ceed06d8209d098f38 ./kintex7/tile_type_INT_FEEDTHRU_2.json`](./kintex7/tile_type_INT_FEEDTHRU_2.json)
* [`2f388adb0b97739b0292e3aefb249346e48916d4c02816d2dd477ca66baaca38 ./kintex7/tile_type_INT_INTERFACE_L.json`](./kintex7/tile_type_INT_INTERFACE_L.json)
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* [`b1ada7c7e90afe1b4942897912f028b258e7157bbd9041f399b268fe256b270c ./kintex7/tile_type_INT_R.json`](./kintex7/tile_type_INT_R.json)
* [`1eb3c6e2ffed9dd7bf8c88db42e5ddb3834966d59935973be256dbe3081c26d8 ./kintex7/tile_type_IO_INT_INTERFACE_L.json`](./kintex7/tile_type_IO_INT_INTERFACE_L.json)
* [`c77d0a3cac3f62df502bf81e5b3ec9dd902872b9d642a711734f434259a3ca74 ./kintex7/tile_type_IO_INT_INTERFACE_R.json`](./kintex7/tile_type_IO_INT_INTERFACE_R.json)
* [`16a518f917b854c87eafdebe24261b758a868940de8a4629de650befa9f86da0 ./kintex7/tile_type_LIOB33.json`](./kintex7/tile_type_LIOB33.json)
* [`c095de913db4bddfcabbd5697a841500d344f83881f4d1beac75428cb25aad64 ./kintex7/tile_type_LIOB33_SING.json`](./kintex7/tile_type_LIOB33_SING.json)
* [`72855c141f9eaf7238ff243e223439eee18df1b1bfba4f8a686835f1542c880a ./kintex7/tile_type_LIOI3.json`](./kintex7/tile_type_LIOI3.json)
* [`1e6fad575e8b68ce44fea9b0509cc5d83ca0670cf97cebf4a29f983bee5ae49e ./kintex7/tile_type_LIOI3_SING.json`](./kintex7/tile_type_LIOI3_SING.json)
* [`f35fc20f3f65bf3f867cf477bcdd288e7270fda5d0204742d2f137fe08476f1d ./kintex7/tile_type_LIOI3_TBYTESRC.json`](./kintex7/tile_type_LIOI3_TBYTESRC.json)
* [`05cf5e8fda8975612f1eaf0a08c8f9c18b9719d471cdd382241d8788698e6297 ./kintex7/tile_type_LIOI3_TBYTETERM.json`](./kintex7/tile_type_LIOI3_TBYTETERM.json)
* [`e1c8778875bb256d12ed385b622bce95d86f5bd46c7aa5748f74f0854e39f2fd ./kintex7/tile_type_L_TERM_INT.json`](./kintex7/tile_type_L_TERM_INT.json)
* [`3ee96506f2b4554c95c04365ac76da9d9df49a0882c0bc51763968a95bd426ed ./kintex7/tile_type_MONITOR_BOT_FUJI2.json`](./kintex7/tile_type_MONITOR_BOT_FUJI2.json)
* [`7043cb553eec51674f1d2e34dcfdb7e2458f0412cf1103ad2d4369c3b9d21b20 ./kintex7/tile_type_MONITOR_MID_FUJI2.json`](./kintex7/tile_type_MONITOR_MID_FUJI2.json)
* [`a067e6134b9585d01b365b4ea89c523a10d491b18fee28db79846deca1541e73 ./kintex7/tile_type_MONITOR_TOP_FUJI2.json`](./kintex7/tile_type_MONITOR_TOP_FUJI2.json)
* [`2397779fbc09ce1abbb28d2d3b0dbd2c2d8ab733971455898b720ed41405943c ./kintex7/tile_type_NULL.json`](./kintex7/tile_type_NULL.json)
* [`cdde011fe6911e6bada3d8cb076a638fbcbe8daf3a3a1f312f6435a0393e742c ./kintex7/tile_type_PCIE_BOT.json`](./kintex7/tile_type_PCIE_BOT.json)
* [`f40a6d7b7146547db93e4de9bcde2079a2a2b2e4059741ae77365d684d777514 ./kintex7/tile_type_PCIE_INT_INTERFACE_L.json`](./kintex7/tile_type_PCIE_INT_INTERFACE_L.json)
* [`ace3f9b3eeea6b9ed9505bc4c9934731ee7c3ed5e18279ec1845564210ab9b44 ./kintex7/tile_type_PCIE_INT_INTERFACE_R.json`](./kintex7/tile_type_PCIE_INT_INTERFACE_R.json)
* [`12f4f10939cf94413223482516debe3c272717af213589426b58ca4bc9043df7 ./kintex7/tile_type_PCIE_NULL.json`](./kintex7/tile_type_PCIE_NULL.json)
* [`e3ef7cfe139e7d320b2e47fac82f33fc8dbbf9727a76ca093f35f4c85703ac58 ./kintex7/tile_type_PCIE_TOP.json`](./kintex7/tile_type_PCIE_TOP.json)
* [`fcf3b72e6b038ed65ef58fd4c1f0e7b3ec6d9c530a7b4d2e3d646db757c9adf2 ./kintex7/tile_type_RIOB18.json`](./kintex7/tile_type_RIOB18.json)
* [`af89547e9585767a881eea25331c1d2a18a9f37bbc1f9d69fe03c45a9a270bd7 ./kintex7/tile_type_RIOB18_SING.json`](./kintex7/tile_type_RIOB18_SING.json)
* [`d0850c3b1fb8c75b9e6bd2a0b61043d251956bc8553f614c4bb0bf02ee6aa23b ./kintex7/tile_type_RIOI.json`](./kintex7/tile_type_RIOI.json)
* [`2612c6eef42b6767ec3d06379ab74edd25203ab8a2920004b3c34892465b0217 ./kintex7/tile_type_RIOI_SING.json`](./kintex7/tile_type_RIOI_SING.json)
* [`7707013ce13e9ea1f6c2c24ad93877cab11fc92bd51e663fda6673777df3cdad ./kintex7/tile_type_RIOI_TBYTESRC.json`](./kintex7/tile_type_RIOI_TBYTESRC.json)
* [`1fec66d8e84dd2da267a0a2c64a482e2ecf263e023ffcaaffe1c72ebb8930a73 ./kintex7/tile_type_RIOI_TBYTETERM.json`](./kintex7/tile_type_RIOI_TBYTETERM.json)
* [`3f8ed6685fa00260c4c65b8401a4cf13aea24d833a634cc567aaeeeb1c29b23a ./kintex7/tile_type_R_TERM_INT_GTX.json`](./kintex7/tile_type_R_TERM_INT_GTX.json)
* [`50eb0be5594840accc6fbf8cd9f060d57b9a5e975e035157545dd86451563a36 ./kintex7/tile_type_R_TERM_INT.json`](./kintex7/tile_type_R_TERM_INT.json)
* [`6a66169978dc3250a90b949218a5f3d82ee68b2aac7868ad6f3aabe0ec7a8c05 ./kintex7/tile_type_TERM_CMT.json`](./kintex7/tile_type_TERM_CMT.json)
* [`861c90352175d3daab60219cd90a25ed429ea635b22eb06581c70625b8e606a7 ./kintex7/tile_type_T_TERM_INT.json`](./kintex7/tile_type_T_TERM_INT.json)
* [`2ce397e17c318c2fd95ebc20bb9c683e12d08ecaab5914f434e9e6ba80b108d8 ./kintex7/tile_type_VBRK_EXT.json`](./kintex7/tile_type_VBRK_EXT.json)
* [`05351758a94de46419680b6d8306ea0366afe7ba14bf0539726db96cdc76cf8d ./kintex7/tile_type_VBRK.json`](./kintex7/tile_type_VBRK.json)
* [`4b910b14d8ff3234d37be5adfc19808701ff336c943e35492414e8417a7d856c ./kintex7/tile_type_VFRAME.json`](./kintex7/tile_type_VFRAME.json)
* [`292b55e44a2c49d9a7fc961ba37761ee8a29e50c790ef9da5e8c0d1c6c142b2f ./kintex7/ppips_int_l.db`](./kintex7/ppips_int_l.db)
* [`60c352d2d6124ad3260ae0c3c151effa29aaad4c32fa2cee7787bfc43ca6aa89 ./kintex7/ppips_int_r.db`](./kintex7/ppips_int_r.db)
* [`63cab7c6cb50b9a86cd6de4ec02cfba93b99ac622684a1196b3d70adb1472fc1 ./kintex7/segbits_bram_l.block_ram.db`](./kintex7/segbits_bram_l.block_ram.db)
* [`4b616026c8d3cb1e4e61e5e5e5abdfa381e66ac6583cacc5262c69273ff813f0 ./kintex7/segbits_bram_l.db`](./kintex7/segbits_bram_l.db)
* [`6daa967b706d7fc5cdf597ed9f142df8f3003ded2fee3d622d484b21ceda2827 ./kintex7/segbits_bram_r.block_ram.db`](./kintex7/segbits_bram_r.block_ram.db)
* [`fb840f2f70f9203652d00f3b1dd5ea57e1b30d6ef49cb8c940b0f197b03ee5fe ./kintex7/segbits_bram_r.db`](./kintex7/segbits_bram_r.db)
* [`83c126d6bf0a40f5438026a1c8572b7f408a91011d89750315c72cf8e337fc9e ./kintex7/segbits_clbll_l.db`](./kintex7/segbits_clbll_l.db)
* [`78179d7f80769785b1d02c1b50994f6a801d3178a977205eb4376aeee680b160 ./kintex7/segbits_clbll_r.db`](./kintex7/segbits_clbll_r.db)
* [`b253e0c8547109c27087f829b5652d647ea1969d8fc460518ebefa1d32a48ae9 ./kintex7/segbits_clblm_l.db`](./kintex7/segbits_clblm_l.db)
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* [`1c2c7229781a4a1d51bbbdeea76238b10497c043aaadf2a76de783041a201878 ./kintex7/segbits_hclk_l.db`](./kintex7/segbits_hclk_l.db)
* [`51288ec0be63172fcb2a12a92853150c62a21e894c2d42a2586046c462bf57a9 ./kintex7/segbits_hclk_r.db`](./kintex7/segbits_hclk_r.db)
* [`23d2bec81339b3fcead640cba87c202edc0b5d9686a88abf586d41bdbf828569 ./kintex7/segbits_int_l.db`](./kintex7/segbits_int_l.db)
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* [`c4fe49753a5ba6b4abc688337d5df26f2101ccfca3dd4270ca77e39e5221bfe9 ./kintex7/settings.sh`](./kintex7/settings.sh)
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* [`a5a19be7b32a9e26182a2646cf8608e98e6ec4aaf285baea3ab039078788e109 ./kintex7/site_type_BUFR.json`](./kintex7/site_type_BUFR.json)
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* [`bcd387295f597629764677c85865ef34930e82d84999843163f6415ee83470d9 ./kintex7/site_type_FRAME_ECC.json`](./kintex7/site_type_FRAME_ECC.json)
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* [`f26fbc06575fa2d5abde06ec617af86bf386473dd97e6eff17c3929c87e889fb ./kintex7/site_type_IOB33S.json`](./kintex7/site_type_IOB33S.json)
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* [`dc96b19ee6e827360c59e845bbf9ea559ea881226a0344fd932fa691d53a099d ./kintex7/site_type_OLOGICE3.json`](./kintex7/site_type_OLOGICE3.json)
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* [`aeb8e6803ff63bb256644a65840ed39dcb64fccb3e01b44ae3479ae67f3341ac ./kintex7/site_type_PHASER_IN_PHY.json`](./kintex7/site_type_PHASER_IN_PHY.json)
* [`9d56de422cf14b2886d45d8b88a38ae159bd66630f98aea1acb1b1bd1321d52d ./kintex7/site_type_PHASER_OUT_PHY.json`](./kintex7/site_type_PHASER_OUT_PHY.json)
* [`eafe5543b8d36752a006772e9c1046331157c3f6fcaead642a1d93b6ec3c5caa ./kintex7/site_type_PHASER_REF.json`](./kintex7/site_type_PHASER_REF.json)
* [`684700d5ca81c587e4cb36b4e4832d09c295f2832c1fb6eadc8142b5d93451d3 ./kintex7/site_type_PHY_CONTROL.json`](./kintex7/site_type_PHY_CONTROL.json)
* [`d7d4341d7e1029cf59f70de76a59c627510c97a421964d1bb7d8e83bd918aa4f ./kintex7/site_type_PLLE2_ADV.json`](./kintex7/site_type_PLLE2_ADV.json)
* [`c01006fabc55d6b03265a3cc14576c9e28ccc37109331daef8cfdef3e726a029 ./kintex7/site_type_PMV2.json`](./kintex7/site_type_PMV2.json)
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* [`5237c206807877602106a66506a2a73bc345fca67189ca7873bbfc6d8b52be53 ./kintex7/site_type_SLICEL.json`](./kintex7/site_type_SLICEL.json)
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* [`bfd80f11db70c478290494ee936a172aac3ebd2351c9d82a0ebd10189a389c6f ./kintex7/site_type_STARTUP.json`](./kintex7/site_type_STARTUP.json)
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* [`f711f285e16aa11d4827ce8504e9413c8ccf87f9f86d108740738ae6cbb4f388 ./kintex7/site_type_XADC.json`](./kintex7/site_type_XADC.json)
* [`0bfdad62f04128ca4d469aa18b179cbd3bf78e40c6af50450c9ca85bfffd746f ./kintex7/tile_type_BRAM_INT_INTERFACE_L.json`](./kintex7/tile_type_BRAM_INT_INTERFACE_L.json)
* [`fd0b3b31118249e66193fa06633a58aa5d86820bed16d3f85497b886d2282845 ./kintex7/tile_type_BRAM_INT_INTERFACE_R.json`](./kintex7/tile_type_BRAM_INT_INTERFACE_R.json)
* [`eb70fc5b8f16c680ceb6fb8797305c44a7f300cddcb9e679273984f8001e9420 ./kintex7/tile_type_BRAM_L.json`](./kintex7/tile_type_BRAM_L.json)
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* [`6260182cedf2857372997d8b9a9b3d28504931d1c7ff5176d718dd44935354f0 ./kintex7/tile_type_CMT_TOP_R_LOWER_T.json`](./kintex7/tile_type_CMT_TOP_R_LOWER_T.json)
* [`c12d02118db07c8703fe07d9592cf8f1672389bd2bde3a82e67e41d961bbb171 ./kintex7/tile_type_CMT_TOP_R_UPPER_B.json`](./kintex7/tile_type_CMT_TOP_R_UPPER_B.json)
* [`816d810709c3f54a33774c6a9acefe472cac1e5748d306e692524007b699ee35 ./kintex7/tile_type_CMT_TOP_R_UPPER_T.json`](./kintex7/tile_type_CMT_TOP_R_UPPER_T.json)
* [`2911d44d3955c49dcad765b66aee65d1938224bb0a5cfe657b0061003cbaf154 ./kintex7/tile_type_DSP_L.json`](./kintex7/tile_type_DSP_L.json)
* [`06802112ab5ed24674380cf08a8c3287dfb3a1d939664362f29892807a91b69a ./kintex7/tile_type_DSP_R.json`](./kintex7/tile_type_DSP_R.json)
* [`61667549d4262e9cbda59fe2eb9a87a61594b0bf722f3ba8f0f85a4ff077c7cd ./kintex7/tile_type_GTX_CHANNEL_0.json`](./kintex7/tile_type_GTX_CHANNEL_0.json)
* [`aa472cce57a7ddfd06831483ee4d0b09d30b644ad8d45e0a4cb8e82e7950472b ./kintex7/tile_type_GTX_CHANNEL_1.json`](./kintex7/tile_type_GTX_CHANNEL_1.json)
* [`cae21c2a995cd8c8e6b0001bbb5641d113007f7e4b5ce3b9b62b48fe07f8874d ./kintex7/tile_type_GTX_CHANNEL_2.json`](./kintex7/tile_type_GTX_CHANNEL_2.json)
* [`e62f84821d99fd43f58b9a144eb48e013519824dfce6e1bb056f0f0a7c0b969b ./kintex7/tile_type_GTX_CHANNEL_3.json`](./kintex7/tile_type_GTX_CHANNEL_3.json)
* [`4f86506406294db9f5fe6fae8f7ebf22e762f0e10a985b1bbf7c8b1c91b0dcc0 ./kintex7/tile_type_GTX_COMMON.json`](./kintex7/tile_type_GTX_COMMON.json)
* [`b015248899232a2c9213742d7f44c597b75bb58e5f4edf03ef71119e003958d4 ./kintex7/tile_type_GTX_INT_INTERFACE.json`](./kintex7/tile_type_GTX_INT_INTERFACE.json)
* [`05eb17dc54b29fac95e4b2ac067139b528c1bc7f5cb78b672e6941a2966ec7bb ./kintex7/tile_type_HCLK_BRAM.json`](./kintex7/tile_type_HCLK_BRAM.json)
* [`307db3c561c03036e0460d24af8d435631bbacef7f81c0385f6179673d818d50 ./kintex7/tile_type_HCLK_CLB.json`](./kintex7/tile_type_HCLK_CLB.json)
* [`318c1785d2059191307e3e12efc326475b060106d048550bfd2a7a48381257d0 ./kintex7/tile_type_HCLK_CMT.json`](./kintex7/tile_type_HCLK_CMT.json)
* [`4af6db5c406dd683670c77fe2dbfcfd64b0d079e59e3082cfc4e578789cddf45 ./kintex7/tile_type_HCLK_CMT_L.json`](./kintex7/tile_type_HCLK_CMT_L.json)
* [`cbcd13d3b6a78888a73e22e1e33e56c80b5fcb23c4d1baf938b4b6daa02173f7 ./kintex7/tile_type_HCLK_DSP_L.json`](./kintex7/tile_type_HCLK_DSP_L.json)
* [`dacc707f9e2db1d6752f833cf0559536423baf915a848b3ff641373f4762793f ./kintex7/tile_type_HCLK_DSP_R.json`](./kintex7/tile_type_HCLK_DSP_R.json)
* [`c1d33fee3af7b2ba311bad50d6f8b771303ebd8241e617ec638b1fcb8d2c4ee0 ./kintex7/tile_type_HCLK_FEEDTHRU_1.json`](./kintex7/tile_type_HCLK_FEEDTHRU_1.json)
* [`0e991e5fc85e54835a7de8da8456ee1300d97d798fb12d16c521a9163500a20c ./kintex7/tile_type_HCLK_FEEDTHRU_2.json`](./kintex7/tile_type_HCLK_FEEDTHRU_2.json)
* [`1631fbdf6e3158d6e372508b55e32e3e638b270e0ca606359b4ad060f6337cea ./kintex7/tile_type_HCLK_FIFO_L.json`](./kintex7/tile_type_HCLK_FIFO_L.json)
* [`7897a72ad8df7a9561af0cd339d07b78fda2d8978771ca314edb158eb6bf21d5 ./kintex7/tile_type_HCLK_GTX.json`](./kintex7/tile_type_HCLK_GTX.json)
* [`6a66fa18fdad81ae738e61f650066415a2adc7d15b15ab87b5080faff3edb9e1 ./kintex7/tile_type_HCLK_INT_INTERFACE.json`](./kintex7/tile_type_HCLK_INT_INTERFACE.json)
* [`51fbaa9613664a08814f372c5791189ceb855720997334f55e52872cc6d4c46f ./kintex7/tile_type_HCLK_IOB.json`](./kintex7/tile_type_HCLK_IOB.json)
* [`a614c05f6190160ffe2178fe0a8bf52b351b429a2468217236b29e0c44344eaf ./kintex7/tile_type_HCLK_IOI.json`](./kintex7/tile_type_HCLK_IOI.json)
* [`e57958223bc67dcba0e52050d88164b60b2f25c689a6eed89718935b0c4c4557 ./kintex7/tile_type_HCLK_IOI3.json`](./kintex7/tile_type_HCLK_IOI3.json)
* [`2c39172c06f58c30f92d140c6c7c060777b1b3f397a23b9cf82a41a656da82ef ./kintex7/tile_type_HCLK_L.json`](./kintex7/tile_type_HCLK_L.json)
* [`4270980b733f54a17a34b5259579fd2e42d38efeeb42518967362c599def37c2 ./kintex7/tile_type_HCLK_L_BOT_UTURN.json`](./kintex7/tile_type_HCLK_L_BOT_UTURN.json)
* [`782d62d7a78ca8282570a945739057b1801795271764120ff4f20696a36e9354 ./kintex7/tile_type_HCLK_R.json`](./kintex7/tile_type_HCLK_R.json)
* [`0bc6c1727558cc3dfe8ee21ec2f2b03e6f0f362d3948b2afed0217e1fd1b2d32 ./kintex7/tile_type_HCLK_R_BOT_UTURN.json`](./kintex7/tile_type_HCLK_R_BOT_UTURN.json)
* [`5b459ee856bd5417b0c61831120d27cebb7f5c6ae4952470bdc6dc6bad6c5b49 ./kintex7/tile_type_HCLK_TERM.json`](./kintex7/tile_type_HCLK_TERM.json)
* [`ccc33563773bbe6157c016214acd36162575086bfa661e8fa53885a58dd2d43d ./kintex7/tile_type_HCLK_TERM_GTX.json`](./kintex7/tile_type_HCLK_TERM_GTX.json)
* [`e706c7cf142b8e806283d3cf030f89e30149bad7b2f156e739e2f41247922792 ./kintex7/tile_type_HCLK_VBRK.json`](./kintex7/tile_type_HCLK_VBRK.json)
* [`acabe2c19ef9286451b67f889608af10b57c4149be795c7b9e96c700e673741a ./kintex7/tile_type_HCLK_VFRAME.json`](./kintex7/tile_type_HCLK_VFRAME.json)
* [`fe9a6b9109c94abc0860142566f1d6c292b5313f2ebe641dbd3f4d41671d05a2 ./kintex7/tile_type_INT_FEEDTHRU_1.json`](./kintex7/tile_type_INT_FEEDTHRU_1.json)
* [`1ff618718c404f469eed1fc7499db1a7bcfa90bf152b317b07511d1e070d7622 ./kintex7/tile_type_INT_FEEDTHRU_2.json`](./kintex7/tile_type_INT_FEEDTHRU_2.json)
* [`08db2bc2bc634b16af1988b445a896ffdbe75e2275647657dd44dbc9e436ec9f ./kintex7/tile_type_INT_INTERFACE_L.json`](./kintex7/tile_type_INT_INTERFACE_L.json)
* [`3f04e660e8a477ae99b5349c70d4bb420ed61c823ead17915a2900cc2210ad46 ./kintex7/tile_type_INT_INTERFACE_R.json`](./kintex7/tile_type_INT_INTERFACE_R.json)
* [`cc47a410209b8beb6140d0216de2b298547116a90f4cd7cf9674785e838f4c36 ./kintex7/tile_type_INT_L.json`](./kintex7/tile_type_INT_L.json)
* [`784502f54f667eb147924b061bc62829588d0e43673f32fd9d45113b6f740457 ./kintex7/tile_type_INT_R.json`](./kintex7/tile_type_INT_R.json)
* [`ffedd570b50dfb9fdd8d1e5065da17d53319cda7e849848ec88d352c767e2d59 ./kintex7/tile_type_IO_INT_INTERFACE_L.json`](./kintex7/tile_type_IO_INT_INTERFACE_L.json)
* [`cf049a6c528634761c6067610f50110102caadc782a33b855f4059df8ed064d9 ./kintex7/tile_type_IO_INT_INTERFACE_R.json`](./kintex7/tile_type_IO_INT_INTERFACE_R.json)
* [`cef7db2efcd92f19a0775c1833e0dd23b3dcb4d016fa8516b7e69c4a658ac630 ./kintex7/tile_type_LIOB33.json`](./kintex7/tile_type_LIOB33.json)
* [`49276f934ed32b1ec0b2eac19b67178119fbc5674d022eec1de5be08b07c4e72 ./kintex7/tile_type_LIOB33_SING.json`](./kintex7/tile_type_LIOB33_SING.json)
* [`801140f147650d8b443e46fa51793181c264bc8d92c8767bb875ae838ae4a062 ./kintex7/tile_type_LIOI3.json`](./kintex7/tile_type_LIOI3.json)
* [`c2932bc581e8b38a7373f5a9a555263ce7aa9d96ad9c4e5675c599b11d86b67b ./kintex7/tile_type_LIOI3_SING.json`](./kintex7/tile_type_LIOI3_SING.json)
* [`b69c2ea84f06bfed085b2f50e1f4dd43033dd5f34ca19e67da42d6c80317cd23 ./kintex7/tile_type_LIOI3_TBYTESRC.json`](./kintex7/tile_type_LIOI3_TBYTESRC.json)
* [`44cf5e287a63932e7b6809f4fc3245ff380ae8ad24ed9b53b8cee45b719517b6 ./kintex7/tile_type_LIOI3_TBYTETERM.json`](./kintex7/tile_type_LIOI3_TBYTETERM.json)
* [`5c6ddebe6aef58fa126d2f1121f2c415737d513b90169c393dfcbe2655251716 ./kintex7/tile_type_L_TERM_INT.json`](./kintex7/tile_type_L_TERM_INT.json)
* [`492e354568a279eb9b4d45a38a8e99a7971d02dad9d7db9979a115ee775f7b57 ./kintex7/tile_type_MONITOR_BOT_FUJI2.json`](./kintex7/tile_type_MONITOR_BOT_FUJI2.json)
* [`ecd8853d71cb85a9234f41c12f81e22a91dc2623947c07c9ad5d6a07a1d4e9b7 ./kintex7/tile_type_MONITOR_MID_FUJI2.json`](./kintex7/tile_type_MONITOR_MID_FUJI2.json)
* [`687681f194bdd1c2642f07d0ef1e95fa1f4de557bc4ea3d098b8224e982eda69 ./kintex7/tile_type_MONITOR_TOP_FUJI2.json`](./kintex7/tile_type_MONITOR_TOP_FUJI2.json)
* [`880cdcd99af7ea01e4ee142860e0900c6c3503da3b3582837fedba1a2cafa852 ./kintex7/tile_type_NULL.json`](./kintex7/tile_type_NULL.json)
* [`a1553083f3d3f703f6fdc25b2e1b5b62e2a68d4371c4edcf3cb3aa8d8e99ec87 ./kintex7/tile_type_PCIE_BOT.json`](./kintex7/tile_type_PCIE_BOT.json)
* [`3e075fbce2e39f99504b7e799de6aa1146aafe32d545b0c7ba791d93751ac58b ./kintex7/tile_type_PCIE_INT_INTERFACE_L.json`](./kintex7/tile_type_PCIE_INT_INTERFACE_L.json)
* [`7640289b2a0635eba0172f8e37e452a53912620fe00572cf57fe4ac4ae0db2be ./kintex7/tile_type_PCIE_INT_INTERFACE_R.json`](./kintex7/tile_type_PCIE_INT_INTERFACE_R.json)
* [`944d9c69913b23cac150f0c80c14284d57fab43f69202a6cc63afaddce23221b ./kintex7/tile_type_PCIE_NULL.json`](./kintex7/tile_type_PCIE_NULL.json)
* [`dc29a2768d5aafea58e032f3d303e34e5e7dae896979ef2fc2fe70165b42cf3e ./kintex7/tile_type_PCIE_TOP.json`](./kintex7/tile_type_PCIE_TOP.json)
* [`0e43d927111f9707d0d2bde59253087eb358d93bed0ad3d45488d8025f45c453 ./kintex7/tile_type_RIOB18.json`](./kintex7/tile_type_RIOB18.json)
* [`143e828e00241ab782be5051c26bc83b78e87f82977e5c07d943778e4603f8f4 ./kintex7/tile_type_RIOB18_SING.json`](./kintex7/tile_type_RIOB18_SING.json)
* [`b6feb57ff8a4a680573e34cad591dd8806841c18fe6d10a13791f91c7ce947f8 ./kintex7/tile_type_RIOI.json`](./kintex7/tile_type_RIOI.json)
* [`f7782f69f88c344a504d2e8b48459cd0460835d9dcce13f229a84db8eed36b50 ./kintex7/tile_type_RIOI_SING.json`](./kintex7/tile_type_RIOI_SING.json)
* [`ceda94b5277ecf7224bcd4e1d323bb136245a547546d8b7479bee9957dfd1a5d ./kintex7/tile_type_RIOI_TBYTESRC.json`](./kintex7/tile_type_RIOI_TBYTESRC.json)
* [`3e40d2570c0019c986f4fd163cadc24f48d2557a7894af2af5994924f7a3158b ./kintex7/tile_type_RIOI_TBYTETERM.json`](./kintex7/tile_type_RIOI_TBYTETERM.json)
* [`16627ffc9c74acf89474ad03993367d2210f40d4ab07a8c71c98d9ad652f2ca8 ./kintex7/tile_type_R_TERM_INT.json`](./kintex7/tile_type_R_TERM_INT.json)
* [`fd664b568212b0479342de300f8efc07e8b521960fbb4b9abacb71336fca773b ./kintex7/tile_type_R_TERM_INT_GTX.json`](./kintex7/tile_type_R_TERM_INT_GTX.json)
* [`19503481fb531f7ddc5f92fdc7c97a817ce1cf550e128604041c771f2234b7fa ./kintex7/tile_type_TERM_CMT.json`](./kintex7/tile_type_TERM_CMT.json)
* [`f5ebbeee5575e5fbc1fb5d532f021e4ee8647de21b3874caac655d8c849a9ff3 ./kintex7/tile_type_T_TERM_INT.json`](./kintex7/tile_type_T_TERM_INT.json)
* [`dee783006fa5b5964d20457323cad59171a60397d730e9fe0840389587695727 ./kintex7/tile_type_VBRK.json`](./kintex7/tile_type_VBRK.json)
* [`04409fb1eb974ee5af7e8115bf16aacfd4bda61094c7c4644cc020762a45f6c8 ./kintex7/tile_type_VBRK_EXT.json`](./kintex7/tile_type_VBRK_EXT.json)
* [`004efcd7f9e172780ca7b8c379ec329bcfc52f86beaa1d997f41dbef7ac4a242 ./kintex7/tile_type_VFRAME.json`](./kintex7/tile_type_VFRAME.json)
* [`77985c4643b2984db517096deb4fc80ae992794089aea91c21b456d81fcbadd2 ./kintex7/tileconn.json`](./kintex7/tileconn.json)
* [`b870a0225ffe1b5b9729fbfea3925ad3c24ea7b9fa7ebc8665368f00a2743781 ./kintex7/tilegrid.json`](./kintex7/tilegrid.json)
* [`916a9b924454c10b835d561d80434461c5a9a2824bf85c3cdeeee5f0dedfcb24 ./kintex7/xc7k70tfbg676-2.json`](./kintex7/xc7k70tfbg676-2.json)
* [`44c1530cc9a184551c98face08bd4ab0a7ec3883623175a52da5c59fba9bfa38 ./kintex7/xc7k70tfbg676-2.yaml`](./kintex7/xc7k70tfbg676-2.yaml)
## Database for [zynq7](zynq7/)
### Settings
Created using following [settings/zynq7.sh (sha256: d956938bea24fcf8e8c7f71480116a9a668fb7be744e34a4e627b31a6b553f4b)](https://github.com/SymbiFlow/prjxray/blob/afe50c68c464c0cd4a3fa92b6a07c9abbe41682f/settings/zynq7.sh)
```shell
export XRAY_DATABASE="zynq7"
export XRAY_PART="xc7z010clg400-1"
export XRAY_ROI_FRAMES="0x00000000:0xffffffff"
# All CLB's in part, all BRAM's in part, all DSP's in part.
export XRAY_ROI_TILEGRID="SLICE_X0Y0:SLICE_X43Y99 RAMB18_X0Y0:RAMB18_X2Y39 RAMB36_X0Y0:RAMB36_X2Y19 DSP48_X0Y0:DSP48_X1Y39"
# These settings must remain in sync
export XRAY_ROI="SLICE_X00Y50:SLICE_X43Y99 RAMB18_X0Y20:RAMB18_X2Y39 RAMB36_X0Y10:RAMB36_X2Y19 IOB_X0Y50:IOB_X0Y99"
# Most of CMT X0Y2.
export XRAY_ROI_GRID_X1="0"
export XRAY_ROI_GRID_X2="118"
# Include VBRK / VTERM
export XRAY_ROI_GRID_Y1="0"
export XRAY_ROI_GRID_Y2="51"
export XRAY_PIN_00="L14"
export XRAY_PIN_01="L15"
export XRAY_PIN_02="M14"
export XRAY_PIN_03="M15"
export XRAY_PIN_04="K16"
export XRAY_PIN_05="J16"
export XRAY_PIN_06="J15"
source $(dirname ${BASH_SOURCE[0]})/../utils/environment.sh
init_db
```
### [Results](zynq7/)
Results have checksums;
* [`ee26e7dbf78c2a37118c49ce7edb5fa44afd51850a24824ba8b68e34366f0787 ./zynq7/settings.sh`](./zynq7/settings.sh)

2
artix7/mask_hclk_l.db
View File

@ -102,5 +102,3 @@ bit 05_28
bit 05_29
bit 05_30
bit 05_31
bit <0
bit candidates>

2
artix7/mask_hclk_r.db
View File

@ -102,5 +102,3 @@ bit 05_28
bit 05_29
bit 05_30
bit 05_31
bit <0
bit candidates>

240
artix7/ppips_clbll_l.db
View File

@ -1,146 +1,146 @@
CLBLL_L.CLBLL_L_AX.CLBLL_BYP0 always
CLBLL_L.CLBLL_LL_AX.CLBLL_BYP1 always
CLBLL_L.CLBLL_L_CX.CLBLL_BYP2 always
CLBLL_L.CLBLL_LL_CX.CLBLL_BYP3 always
CLBLL_L.CLBLL_LL_BX.CLBLL_BYP4 always
CLBLL_L.CLBLL_L_BX.CLBLL_BYP5 always
CLBLL_L.CLBLL_LL_DX.CLBLL_BYP6 always
CLBLL_L.CLBLL_L_DX.CLBLL_BYP7 always
CLBLL_L.CLBLL_L_CLK.CLBLL_CLK0 always
CLBLL_L.CLBLL_LL_CLK.CLBLL_CLK1 always
CLBLL_L.CLBLL_L_SR.CLBLL_CTRL0 always
CLBLL_L.CLBLL_LL_SR.CLBLL_CTRL1 always
CLBLL_L.CLBLL_L_CE.CLBLL_FAN6 always
CLBLL_L.CLBLL_LL_CE.CLBLL_FAN7 always
CLBLL_L.CLBLL_L_A3.CLBLL_IMUX0 always
CLBLL_L.CLBLL_L_A2.CLBLL_IMUX3 always
CLBLL_L.CLBLL_L_A6.CLBLL_IMUX5 always
CLBLL_L.CLBLL_L_A1.CLBLL_IMUX6 always
CLBLL_L.CLBLL_L_A5.CLBLL_IMUX9 always
CLBLL_L.CLBLL_L_A4.CLBLL_IMUX10 always
CLBLL_L.CLBLL_LL_A3.CLBLL_IMUX1 always
CLBLL_L.CLBLL_LL_A2.CLBLL_IMUX2 always
CLBLL_L.CLBLL_LL_A6.CLBLL_IMUX4 always
CLBLL_L.CLBLL_LL_A1.CLBLL_IMUX7 always
CLBLL_L.CLBLL_LL_A5.CLBLL_IMUX8 always
CLBLL_L.CLBLL_LL_A4.CLBLL_IMUX11 always
CLBLL_L.CLBLL_LL_B6.CLBLL_IMUX12 always
CLBLL_L.CLBLL_LL_B1.CLBLL_IMUX15 always
CLBLL_L.CLBLL_LL_B3.CLBLL_IMUX17 always
CLBLL_L.CLBLL_LL_B2.CLBLL_IMUX18 always
CLBLL_L.CLBLL_LL_B5.CLBLL_IMUX24 always
CLBLL_L.CLBLL_LL_B4.CLBLL_IMUX27 always
CLBLL_L.CLBLL_L_B6.CLBLL_IMUX13 always
CLBLL_L.CLBLL_L_B1.CLBLL_IMUX14 always
CLBLL_L.CLBLL_L_B3.CLBLL_IMUX16 always
CLBLL_L.CLBLL_L_B2.CLBLL_IMUX19 always
CLBLL_L.CLBLL_L_B5.CLBLL_IMUX25 always
CLBLL_L.CLBLL_L_B4.CLBLL_IMUX26 always
CLBLL_L.CLBLL_L_C2.CLBLL_IMUX20 always
CLBLL_L.CLBLL_L_C4.CLBLL_IMUX21 always
CLBLL_L.CLBLL_L_C3.CLBLL_IMUX23 always
CLBLL_L.CLBLL_L_C5.CLBLL_IMUX30 always
CLBLL_L.CLBLL_L_C1.CLBLL_IMUX33 always
CLBLL_L.CLBLL_L_C6.CLBLL_IMUX34 always
CLBLL_L.CLBLL_LL_C3.CLBLL_IMUX22 always
CLBLL_L.CLBLL_LL_C4.CLBLL_IMUX28 always
CLBLL_L.CLBLL_LL_C2.CLBLL_IMUX29 always
CLBLL_L.CLBLL_LL_C5.CLBLL_IMUX31 always
CLBLL_L.CLBLL_LL_C1.CLBLL_IMUX32 always
CLBLL_L.CLBLL_LL_C6.CLBLL_IMUX35 always
CLBLL_L.CLBLL_L_D2.CLBLL_IMUX36 always
CLBLL_L.CLBLL_L_D4.CLBLL_IMUX37 always
CLBLL_L.CLBLL_L_D3.CLBLL_IMUX39 always
CLBLL_L.CLBLL_L_D1.CLBLL_IMUX41 always
CLBLL_L.CLBLL_L_D6.CLBLL_IMUX42 always
CLBLL_L.CLBLL_L_D5.CLBLL_IMUX46 always
CLBLL_L.CLBLL_LL_D3.CLBLL_IMUX38 always
CLBLL_L.CLBLL_LL_D1.CLBLL_IMUX40 always
CLBLL_L.CLBLL_LL_D6.CLBLL_IMUX43 always
CLBLL_L.CLBLL_LL_D4.CLBLL_IMUX44 always
CLBLL_L.CLBLL_LL_D2.CLBLL_IMUX45 always
CLBLL_L.CLBLL_LL_D5.CLBLL_IMUX47 always
CLBLL_L.CLBLL_LOGIC_OUTS12.CLBLL_LL_A always
CLBLL_L.CLBLL_LL_AMUX.CLBLL_LL_A hint
CLBLL_L.CLBLL_LL_A.CLBLL_LL_A1 hint
CLBLL_L.CLBLL_LL_A.CLBLL_LL_A2 hint
CLBLL_L.CLBLL_LL_A.CLBLL_LL_A3 hint
CLBLL_L.CLBLL_LL_A.CLBLL_LL_A4 hint
CLBLL_L.CLBLL_LL_A.CLBLL_LL_A5 hint
CLBLL_L.CLBLL_LL_A.CLBLL_LL_A6 hint
CLBLL_L.CLBLL_LOGIC_OUTS20.CLBLL_LL_AMUX always
CLBLL_L.CLBLL_LOGIC_OUTS4.CLBLL_LL_AQ always
CLBLL_L.CLBLL_LOGIC_OUTS13.CLBLL_LL_B always
CLBLL_L.CLBLL_LL_BMUX.CLBLL_LL_B hint
CLBLL_L.CLBLL_LL_B.CLBLL_LL_B1 hint
CLBLL_L.CLBLL_LL_B.CLBLL_LL_B2 hint
CLBLL_L.CLBLL_LL_B.CLBLL_LL_B3 hint
CLBLL_L.CLBLL_LL_B.CLBLL_LL_B4 hint
CLBLL_L.CLBLL_LL_B.CLBLL_LL_B5 hint
CLBLL_L.CLBLL_LL_B.CLBLL_LL_B6 hint
CLBLL_L.CLBLL_LOGIC_OUTS21.CLBLL_LL_BMUX always
CLBLL_L.CLBLL_LOGIC_OUTS5.CLBLL_LL_BQ always
CLBLL_L.CLBLL_LOGIC_OUTS14.CLBLL_LL_C always
CLBLL_L.CLBLL_LL_CMUX.CLBLL_LL_C hint
CLBLL_L.CLBLL_LL_C.CLBLL_LL_C1 hint
CLBLL_L.CLBLL_LL_C.CLBLL_LL_C2 hint
CLBLL_L.CLBLL_LL_C.CLBLL_LL_C3 hint
CLBLL_L.CLBLL_LL_C.CLBLL_LL_C4 hint
CLBLL_L.CLBLL_LL_C.CLBLL_LL_C5 hint
CLBLL_L.CLBLL_LL_C.CLBLL_LL_C6 hint
CLBLL_L.CLBLL_LOGIC_OUTS22.CLBLL_LL_CMUX always
CLBLL_L.CLBLL_LL_COUT_N.CLBLL_LL_COUT always
CLBLL_L.CLBLL_LL_DMUX.CLBLL_LL_COUT hint
CLBLL_L.CLBLL_LOGIC_OUTS6.CLBLL_LL_CQ always
CLBLL_L.CLBLL_LOGIC_OUTS15.CLBLL_LL_D always
CLBLL_L.CLBLL_LL_DMUX.CLBLL_LL_D hint
CLBLL_L.CLBLL_LL_D.CLBLL_LL_D1 hint
CLBLL_L.CLBLL_LL_D.CLBLL_LL_D2 hint
CLBLL_L.CLBLL_LL_D.CLBLL_LL_D3 hint
CLBLL_L.CLBLL_LL_D.CLBLL_LL_D4 hint
CLBLL_L.CLBLL_LL_D.CLBLL_LL_D5 hint
CLBLL_L.CLBLL_LL_D.CLBLL_LL_D6 hint
CLBLL_L.CLBLL_LOGIC_OUTS23.CLBLL_LL_DMUX always
CLBLL_L.CLBLL_LOGIC_OUTS7.CLBLL_LL_DQ always
CLBLL_L.CLBLL_LOGIC_OUTS8.CLBLL_L_A always
CLBLL_L.CLBLL_L_AMUX.CLBLL_L_A hint
CLBLL_L.CLBLL_L_A.CLBLL_L_A1 hint
CLBLL_L.CLBLL_L_A.CLBLL_L_A2 hint
CLBLL_L.CLBLL_L_A.CLBLL_L_A3 hint
CLBLL_L.CLBLL_L_A.CLBLL_L_A4 hint
CLBLL_L.CLBLL_L_A.CLBLL_L_A5 hint
CLBLL_L.CLBLL_L_A.CLBLL_L_A6 hint
CLBLL_L.CLBLL_LOGIC_OUTS16.CLBLL_L_AMUX always
CLBLL_L.CLBLL_LOGIC_OUTS0.CLBLL_L_AQ always
CLBLL_L.CLBLL_LOGIC_OUTS9.CLBLL_L_B always
CLBLL_L.CLBLL_L_BMUX.CLBLL_L_B hint
CLBLL_L.CLBLL_L_AMUX.CLBLL_L_A hint
CLBLL_L.CLBLL_L_AX.CLBLL_BYP0 always
CLBLL_L.CLBLL_L_B.CLBLL_L_B1 hint
CLBLL_L.CLBLL_L_B.CLBLL_L_B2 hint
CLBLL_L.CLBLL_L_B.CLBLL_L_B3 hint
CLBLL_L.CLBLL_L_B.CLBLL_L_B4 hint
CLBLL_L.CLBLL_L_B.CLBLL_L_B5 hint
CLBLL_L.CLBLL_L_B.CLBLL_L_B6 hint
CLBLL_L.CLBLL_LOGIC_OUTS17.CLBLL_L_BMUX always
CLBLL_L.CLBLL_LOGIC_OUTS1.CLBLL_L_BQ always
CLBLL_L.CLBLL_LOGIC_OUTS10.CLBLL_L_C always
CLBLL_L.CLBLL_L_CMUX.CLBLL_L_C hint
CLBLL_L.CLBLL_L_BMUX.CLBLL_L_B hint
CLBLL_L.CLBLL_L_BX.CLBLL_BYP5 always
CLBLL_L.CLBLL_L_C.CLBLL_L_C1 hint
CLBLL_L.CLBLL_L_C.CLBLL_L_C2 hint
CLBLL_L.CLBLL_L_C.CLBLL_L_C3 hint
CLBLL_L.CLBLL_L_C.CLBLL_L_C4 hint
CLBLL_L.CLBLL_L_C.CLBLL_L_C5 hint
CLBLL_L.CLBLL_L_C.CLBLL_L_C6 hint
CLBLL_L.CLBLL_LOGIC_OUTS18.CLBLL_L_CMUX always
CLBLL_L.CLBLL_L_CE.CLBLL_FAN6 always
CLBLL_L.CLBLL_L_CLK.CLBLL_CLK0 always
CLBLL_L.CLBLL_L_CMUX.CLBLL_L_C hint
CLBLL_L.CLBLL_L_COUT_N.CLBLL_L_COUT always
CLBLL_L.CLBLL_L_DMUX.CLBLL_L_COUT hint
CLBLL_L.CLBLL_LOGIC_OUTS2.CLBLL_L_CQ always
CLBLL_L.CLBLL_LOGIC_OUTS11.CLBLL_L_D always
CLBLL_L.CLBLL_L_DMUX.CLBLL_L_D hint
CLBLL_L.CLBLL_L_CX.CLBLL_BYP2 always
CLBLL_L.CLBLL_L_D.CLBLL_L_D1 hint
CLBLL_L.CLBLL_L_D.CLBLL_L_D2 hint
CLBLL_L.CLBLL_L_D.CLBLL_L_D3 hint
CLBLL_L.CLBLL_L_D.CLBLL_L_D4 hint
CLBLL_L.CLBLL_L_D.CLBLL_L_D5 hint
CLBLL_L.CLBLL_L_D.CLBLL_L_D6 hint
CLBLL_L.CLBLL_LOGIC_OUTS19.CLBLL_L_DMUX always
CLBLL_L.CLBLL_L_DMUX.CLBLL_L_COUT hint
CLBLL_L.CLBLL_L_DMUX.CLBLL_L_D hint
CLBLL_L.CLBLL_L_DX.CLBLL_BYP7 always
CLBLL_L.CLBLL_L_SR.CLBLL_CTRL0 always
CLBLL_L.CLBLL_L_A1.CLBLL_IMUX6 always
CLBLL_L.CLBLL_L_A2.CLBLL_IMUX3 always
CLBLL_L.CLBLL_L_A3.CLBLL_IMUX0 always
CLBLL_L.CLBLL_L_A4.CLBLL_IMUX10 always
CLBLL_L.CLBLL_L_A5.CLBLL_IMUX9 always
CLBLL_L.CLBLL_L_A6.CLBLL_IMUX5 always
CLBLL_L.CLBLL_L_B1.CLBLL_IMUX14 always
CLBLL_L.CLBLL_L_B2.CLBLL_IMUX19 always
CLBLL_L.CLBLL_L_B3.CLBLL_IMUX16 always
CLBLL_L.CLBLL_L_B4.CLBLL_IMUX26 always
CLBLL_L.CLBLL_L_B5.CLBLL_IMUX25 always
CLBLL_L.CLBLL_L_B6.CLBLL_IMUX13 always
CLBLL_L.CLBLL_L_C1.CLBLL_IMUX33 always
CLBLL_L.CLBLL_L_C2.CLBLL_IMUX20 always
CLBLL_L.CLBLL_L_C3.CLBLL_IMUX23 always
CLBLL_L.CLBLL_L_C4.CLBLL_IMUX21 always
CLBLL_L.CLBLL_L_C5.CLBLL_IMUX30 always
CLBLL_L.CLBLL_L_C6.CLBLL_IMUX34 always
CLBLL_L.CLBLL_L_D1.CLBLL_IMUX41 always
CLBLL_L.CLBLL_L_D2.CLBLL_IMUX36 always
CLBLL_L.CLBLL_L_D3.CLBLL_IMUX39 always
CLBLL_L.CLBLL_L_D4.CLBLL_IMUX37 always
CLBLL_L.CLBLL_L_D5.CLBLL_IMUX46 always
CLBLL_L.CLBLL_L_D6.CLBLL_IMUX42 always
CLBLL_L.CLBLL_LL_A.CLBLL_LL_A1 hint
CLBLL_L.CLBLL_LL_A.CLBLL_LL_A2 hint
CLBLL_L.CLBLL_LL_A.CLBLL_LL_A3 hint
CLBLL_L.CLBLL_LL_A.CLBLL_LL_A4 hint
CLBLL_L.CLBLL_LL_A.CLBLL_LL_A5 hint
CLBLL_L.CLBLL_LL_A.CLBLL_LL_A6 hint
CLBLL_L.CLBLL_LL_AMUX.CLBLL_LL_A hint
CLBLL_L.CLBLL_LL_AX.CLBLL_BYP1 always
CLBLL_L.CLBLL_LL_B.CLBLL_LL_B1 hint
CLBLL_L.CLBLL_LL_B.CLBLL_LL_B2 hint
CLBLL_L.CLBLL_LL_B.CLBLL_LL_B3 hint
CLBLL_L.CLBLL_LL_B.CLBLL_LL_B4 hint
CLBLL_L.CLBLL_LL_B.CLBLL_LL_B5 hint
CLBLL_L.CLBLL_LL_B.CLBLL_LL_B6 hint
CLBLL_L.CLBLL_LL_BMUX.CLBLL_LL_B hint
CLBLL_L.CLBLL_LL_BX.CLBLL_BYP4 always
CLBLL_L.CLBLL_LL_C.CLBLL_LL_C1 hint
CLBLL_L.CLBLL_LL_C.CLBLL_LL_C2 hint
CLBLL_L.CLBLL_LL_C.CLBLL_LL_C3 hint
CLBLL_L.CLBLL_LL_C.CLBLL_LL_C4 hint
CLBLL_L.CLBLL_LL_C.CLBLL_LL_C5 hint
CLBLL_L.CLBLL_LL_C.CLBLL_LL_C6 hint
CLBLL_L.CLBLL_LL_CE.CLBLL_FAN7 always
CLBLL_L.CLBLL_LL_CLK.CLBLL_CLK1 always
CLBLL_L.CLBLL_LL_CMUX.CLBLL_LL_C hint
CLBLL_L.CLBLL_LL_COUT_N.CLBLL_LL_COUT always
CLBLL_L.CLBLL_LL_CX.CLBLL_BYP3 always
CLBLL_L.CLBLL_LL_D.CLBLL_LL_D1 hint
CLBLL_L.CLBLL_LL_D.CLBLL_LL_D2 hint
CLBLL_L.CLBLL_LL_D.CLBLL_LL_D3 hint
CLBLL_L.CLBLL_LL_D.CLBLL_LL_D4 hint
CLBLL_L.CLBLL_LL_D.CLBLL_LL_D5 hint
CLBLL_L.CLBLL_LL_D.CLBLL_LL_D6 hint
CLBLL_L.CLBLL_LL_DMUX.CLBLL_LL_COUT hint
CLBLL_L.CLBLL_LL_DMUX.CLBLL_LL_D hint
CLBLL_L.CLBLL_LL_DX.CLBLL_BYP6 always
CLBLL_L.CLBLL_LL_SR.CLBLL_CTRL1 always
CLBLL_L.CLBLL_LL_A1.CLBLL_IMUX7 always
CLBLL_L.CLBLL_LL_A2.CLBLL_IMUX2 always
CLBLL_L.CLBLL_LL_A3.CLBLL_IMUX1 always
CLBLL_L.CLBLL_LL_A4.CLBLL_IMUX11 always
CLBLL_L.CLBLL_LL_A5.CLBLL_IMUX8 always
CLBLL_L.CLBLL_LL_A6.CLBLL_IMUX4 always
CLBLL_L.CLBLL_LL_B1.CLBLL_IMUX15 always
CLBLL_L.CLBLL_LL_B2.CLBLL_IMUX18 always
CLBLL_L.CLBLL_LL_B3.CLBLL_IMUX17 always
CLBLL_L.CLBLL_LL_B4.CLBLL_IMUX27 always
CLBLL_L.CLBLL_LL_B5.CLBLL_IMUX24 always
CLBLL_L.CLBLL_LL_B6.CLBLL_IMUX12 always
CLBLL_L.CLBLL_LL_C1.CLBLL_IMUX32 always
CLBLL_L.CLBLL_LL_C2.CLBLL_IMUX29 always
CLBLL_L.CLBLL_LL_C3.CLBLL_IMUX22 always
CLBLL_L.CLBLL_LL_C4.CLBLL_IMUX28 always
CLBLL_L.CLBLL_LL_C5.CLBLL_IMUX31 always
CLBLL_L.CLBLL_LL_C6.CLBLL_IMUX35 always
CLBLL_L.CLBLL_LL_D1.CLBLL_IMUX40 always
CLBLL_L.CLBLL_LL_D2.CLBLL_IMUX45 always
CLBLL_L.CLBLL_LL_D3.CLBLL_IMUX38 always
CLBLL_L.CLBLL_LL_D4.CLBLL_IMUX44 always
CLBLL_L.CLBLL_LL_D5.CLBLL_IMUX47 always
CLBLL_L.CLBLL_LL_D6.CLBLL_IMUX43 always
CLBLL_L.CLBLL_LOGIC_OUTS0.CLBLL_L_AQ always
CLBLL_L.CLBLL_LOGIC_OUTS1.CLBLL_L_BQ always
CLBLL_L.CLBLL_LOGIC_OUTS2.CLBLL_L_CQ always
CLBLL_L.CLBLL_LOGIC_OUTS3.CLBLL_L_DQ always
CLBLL_L.CLBLL_LOGIC_OUTS4.CLBLL_LL_AQ always
CLBLL_L.CLBLL_LOGIC_OUTS5.CLBLL_LL_BQ always
CLBLL_L.CLBLL_LOGIC_OUTS6.CLBLL_LL_CQ always
CLBLL_L.CLBLL_LOGIC_OUTS7.CLBLL_LL_DQ always
CLBLL_L.CLBLL_LOGIC_OUTS8.CLBLL_L_A always
CLBLL_L.CLBLL_LOGIC_OUTS9.CLBLL_L_B always
CLBLL_L.CLBLL_LOGIC_OUTS10.CLBLL_L_C always
CLBLL_L.CLBLL_LOGIC_OUTS11.CLBLL_L_D always
CLBLL_L.CLBLL_LOGIC_OUTS12.CLBLL_LL_A always
CLBLL_L.CLBLL_LOGIC_OUTS13.CLBLL_LL_B always
CLBLL_L.CLBLL_LOGIC_OUTS14.CLBLL_LL_C always
CLBLL_L.CLBLL_LOGIC_OUTS15.CLBLL_LL_D always
CLBLL_L.CLBLL_LOGIC_OUTS16.CLBLL_L_AMUX always
CLBLL_L.CLBLL_LOGIC_OUTS17.CLBLL_L_BMUX always
CLBLL_L.CLBLL_LOGIC_OUTS18.CLBLL_L_CMUX always
CLBLL_L.CLBLL_LOGIC_OUTS19.CLBLL_L_DMUX always
CLBLL_L.CLBLL_LOGIC_OUTS20.CLBLL_LL_AMUX always
CLBLL_L.CLBLL_LOGIC_OUTS21.CLBLL_LL_BMUX always
CLBLL_L.CLBLL_LOGIC_OUTS22.CLBLL_LL_CMUX always
CLBLL_L.CLBLL_LOGIC_OUTS23.CLBLL_LL_DMUX always

240
artix7/ppips_clbll_r.db
View File

@ -1,146 +1,146 @@
CLBLL_R.CLBLL_L_AX.CLBLL_BYP0 always
CLBLL_R.CLBLL_LL_AX.CLBLL_BYP1 always
CLBLL_R.CLBLL_L_CX.CLBLL_BYP2 always
CLBLL_R.CLBLL_LL_CX.CLBLL_BYP3 always
CLBLL_R.CLBLL_LL_BX.CLBLL_BYP4 always
CLBLL_R.CLBLL_L_BX.CLBLL_BYP5 always
CLBLL_R.CLBLL_LL_DX.CLBLL_BYP6 always
CLBLL_R.CLBLL_L_DX.CLBLL_BYP7 always
CLBLL_R.CLBLL_L_CLK.CLBLL_CLK0 always
CLBLL_R.CLBLL_LL_CLK.CLBLL_CLK1 always
CLBLL_R.CLBLL_L_SR.CLBLL_CTRL0 always
CLBLL_R.CLBLL_LL_SR.CLBLL_CTRL1 always
CLBLL_R.CLBLL_L_CE.CLBLL_FAN6 always
CLBLL_R.CLBLL_LL_CE.CLBLL_FAN7 always
CLBLL_R.CLBLL_L_A3.CLBLL_IMUX0 always
CLBLL_R.CLBLL_L_A2.CLBLL_IMUX3 always
CLBLL_R.CLBLL_L_A6.CLBLL_IMUX5 always
CLBLL_R.CLBLL_L_A1.CLBLL_IMUX6 always
CLBLL_R.CLBLL_L_A5.CLBLL_IMUX9 always
CLBLL_R.CLBLL_L_A4.CLBLL_IMUX10 always
CLBLL_R.CLBLL_LL_A3.CLBLL_IMUX1 always
CLBLL_R.CLBLL_LL_A2.CLBLL_IMUX2 always
CLBLL_R.CLBLL_LL_A6.CLBLL_IMUX4 always
CLBLL_R.CLBLL_LL_A1.CLBLL_IMUX7 always
CLBLL_R.CLBLL_LL_A5.CLBLL_IMUX8 always
CLBLL_R.CLBLL_LL_A4.CLBLL_IMUX11 always
CLBLL_R.CLBLL_LL_B6.CLBLL_IMUX12 always
CLBLL_R.CLBLL_LL_B1.CLBLL_IMUX15 always
CLBLL_R.CLBLL_LL_B3.CLBLL_IMUX17 always
CLBLL_R.CLBLL_LL_B2.CLBLL_IMUX18 always
CLBLL_R.CLBLL_LL_B5.CLBLL_IMUX24 always
CLBLL_R.CLBLL_LL_B4.CLBLL_IMUX27 always
CLBLL_R.CLBLL_L_B6.CLBLL_IMUX13 always
CLBLL_R.CLBLL_L_B1.CLBLL_IMUX14 always
CLBLL_R.CLBLL_L_B3.CLBLL_IMUX16 always
CLBLL_R.CLBLL_L_B2.CLBLL_IMUX19 always
CLBLL_R.CLBLL_L_B5.CLBLL_IMUX25 always
CLBLL_R.CLBLL_L_B4.CLBLL_IMUX26 always
CLBLL_R.CLBLL_L_C2.CLBLL_IMUX20 always
CLBLL_R.CLBLL_L_C4.CLBLL_IMUX21 always
CLBLL_R.CLBLL_L_C3.CLBLL_IMUX23 always
CLBLL_R.CLBLL_L_C5.CLBLL_IMUX30 always
CLBLL_R.CLBLL_L_C1.CLBLL_IMUX33 always
CLBLL_R.CLBLL_L_C6.CLBLL_IMUX34 always
CLBLL_R.CLBLL_LL_C3.CLBLL_IMUX22 always
CLBLL_R.CLBLL_LL_C4.CLBLL_IMUX28 always
CLBLL_R.CLBLL_LL_C2.CLBLL_IMUX29 always
CLBLL_R.CLBLL_LL_C5.CLBLL_IMUX31 always
CLBLL_R.CLBLL_LL_C1.CLBLL_IMUX32 always
CLBLL_R.CLBLL_LL_C6.CLBLL_IMUX35 always
CLBLL_R.CLBLL_L_D2.CLBLL_IMUX36 always
CLBLL_R.CLBLL_L_D4.CLBLL_IMUX37 always
CLBLL_R.CLBLL_L_D3.CLBLL_IMUX39 always
CLBLL_R.CLBLL_L_D1.CLBLL_IMUX41 always
CLBLL_R.CLBLL_L_D6.CLBLL_IMUX42 always
CLBLL_R.CLBLL_L_D5.CLBLL_IMUX46 always
CLBLL_R.CLBLL_LL_D3.CLBLL_IMUX38 always
CLBLL_R.CLBLL_LL_D1.CLBLL_IMUX40 always
CLBLL_R.CLBLL_LL_D6.CLBLL_IMUX43 always
CLBLL_R.CLBLL_LL_D4.CLBLL_IMUX44 always
CLBLL_R.CLBLL_LL_D2.CLBLL_IMUX45 always
CLBLL_R.CLBLL_LL_D5.CLBLL_IMUX47 always
CLBLL_R.CLBLL_LOGIC_OUTS12.CLBLL_LL_A always
CLBLL_R.CLBLL_LL_AMUX.CLBLL_LL_A hint
CLBLL_R.CLBLL_LL_A.CLBLL_LL_A1 hint
CLBLL_R.CLBLL_LL_A.CLBLL_LL_A2 hint
CLBLL_R.CLBLL_LL_A.CLBLL_LL_A3 hint
CLBLL_R.CLBLL_LL_A.CLBLL_LL_A4 hint
CLBLL_R.CLBLL_LL_A.CLBLL_LL_A5 hint
CLBLL_R.CLBLL_LL_A.CLBLL_LL_A6 hint
CLBLL_R.CLBLL_LOGIC_OUTS20.CLBLL_LL_AMUX always
CLBLL_R.CLBLL_LOGIC_OUTS4.CLBLL_LL_AQ always
CLBLL_R.CLBLL_LOGIC_OUTS13.CLBLL_LL_B always
CLBLL_R.CLBLL_LL_BMUX.CLBLL_LL_B hint
CLBLL_R.CLBLL_LL_B.CLBLL_LL_B1 hint
CLBLL_R.CLBLL_LL_B.CLBLL_LL_B2 hint
CLBLL_R.CLBLL_LL_B.CLBLL_LL_B3 hint
CLBLL_R.CLBLL_LL_B.CLBLL_LL_B4 hint
CLBLL_R.CLBLL_LL_B.CLBLL_LL_B5 hint
CLBLL_R.CLBLL_LL_B.CLBLL_LL_B6 hint
CLBLL_R.CLBLL_LOGIC_OUTS21.CLBLL_LL_BMUX always
CLBLL_R.CLBLL_LOGIC_OUTS5.CLBLL_LL_BQ always
CLBLL_R.CLBLL_LOGIC_OUTS14.CLBLL_LL_C always
CLBLL_R.CLBLL_LL_CMUX.CLBLL_LL_C hint
CLBLL_R.CLBLL_LL_C.CLBLL_LL_C1 hint
CLBLL_R.CLBLL_LL_C.CLBLL_LL_C2 hint
CLBLL_R.CLBLL_LL_C.CLBLL_LL_C3 hint
CLBLL_R.CLBLL_LL_C.CLBLL_LL_C4 hint
CLBLL_R.CLBLL_LL_C.CLBLL_LL_C5 hint
CLBLL_R.CLBLL_LL_C.CLBLL_LL_C6 hint
CLBLL_R.CLBLL_LOGIC_OUTS22.CLBLL_LL_CMUX always
CLBLL_R.CLBLL_LL_COUT_N.CLBLL_LL_COUT always
CLBLL_R.CLBLL_LL_DMUX.CLBLL_LL_COUT hint
CLBLL_R.CLBLL_LOGIC_OUTS6.CLBLL_LL_CQ always
CLBLL_R.CLBLL_LOGIC_OUTS15.CLBLL_LL_D always
CLBLL_R.CLBLL_LL_DMUX.CLBLL_LL_D hint
CLBLL_R.CLBLL_LL_D.CLBLL_LL_D1 hint
CLBLL_R.CLBLL_LL_D.CLBLL_LL_D2 hint
CLBLL_R.CLBLL_LL_D.CLBLL_LL_D3 hint
CLBLL_R.CLBLL_LL_D.CLBLL_LL_D4 hint
CLBLL_R.CLBLL_LL_D.CLBLL_LL_D5 hint
CLBLL_R.CLBLL_LL_D.CLBLL_LL_D6 hint
CLBLL_R.CLBLL_LOGIC_OUTS23.CLBLL_LL_DMUX always
CLBLL_R.CLBLL_LOGIC_OUTS7.CLBLL_LL_DQ always
CLBLL_R.CLBLL_LOGIC_OUTS8.CLBLL_L_A always
CLBLL_R.CLBLL_L_AMUX.CLBLL_L_A hint
CLBLL_R.CLBLL_L_A.CLBLL_L_A1 hint
CLBLL_R.CLBLL_L_A.CLBLL_L_A2 hint
CLBLL_R.CLBLL_L_A.CLBLL_L_A3 hint
CLBLL_R.CLBLL_L_A.CLBLL_L_A4 hint
CLBLL_R.CLBLL_L_A.CLBLL_L_A5 hint
CLBLL_R.CLBLL_L_A.CLBLL_L_A6 hint
CLBLL_R.CLBLL_LOGIC_OUTS16.CLBLL_L_AMUX always
CLBLL_R.CLBLL_LOGIC_OUTS0.CLBLL_L_AQ always
CLBLL_R.CLBLL_LOGIC_OUTS9.CLBLL_L_B always
CLBLL_R.CLBLL_L_BMUX.CLBLL_L_B hint
CLBLL_R.CLBLL_L_AMUX.CLBLL_L_A hint
CLBLL_R.CLBLL_L_AX.CLBLL_BYP0 always
CLBLL_R.CLBLL_L_B.CLBLL_L_B1 hint
CLBLL_R.CLBLL_L_B.CLBLL_L_B2 hint
CLBLL_R.CLBLL_L_B.CLBLL_L_B3 hint
CLBLL_R.CLBLL_L_B.CLBLL_L_B4 hint
CLBLL_R.CLBLL_L_B.CLBLL_L_B5 hint
CLBLL_R.CLBLL_L_B.CLBLL_L_B6 hint
CLBLL_R.CLBLL_LOGIC_OUTS17.CLBLL_L_BMUX always
CLBLL_R.CLBLL_LOGIC_OUTS1.CLBLL_L_BQ always
CLBLL_R.CLBLL_LOGIC_OUTS10.CLBLL_L_C always
CLBLL_R.CLBLL_L_CMUX.CLBLL_L_C hint
CLBLL_R.CLBLL_L_BMUX.CLBLL_L_B hint
CLBLL_R.CLBLL_L_BX.CLBLL_BYP5 always
CLBLL_R.CLBLL_L_C.CLBLL_L_C1 hint
CLBLL_R.CLBLL_L_C.CLBLL_L_C2 hint
CLBLL_R.CLBLL_L_C.CLBLL_L_C3 hint
CLBLL_R.CLBLL_L_C.CLBLL_L_C4 hint
CLBLL_R.CLBLL_L_C.CLBLL_L_C5 hint
CLBLL_R.CLBLL_L_C.CLBLL_L_C6 hint
CLBLL_R.CLBLL_LOGIC_OUTS18.CLBLL_L_CMUX always
CLBLL_R.CLBLL_L_CE.CLBLL_FAN6 always
CLBLL_R.CLBLL_L_CLK.CLBLL_CLK0 always
CLBLL_R.CLBLL_L_CMUX.CLBLL_L_C hint
CLBLL_R.CLBLL_L_COUT_N.CLBLL_L_COUT always
CLBLL_R.CLBLL_L_DMUX.CLBLL_L_COUT hint
CLBLL_R.CLBLL_LOGIC_OUTS2.CLBLL_L_CQ always
CLBLL_R.CLBLL_LOGIC_OUTS11.CLBLL_L_D always
CLBLL_R.CLBLL_L_DMUX.CLBLL_L_D hint
CLBLL_R.CLBLL_L_CX.CLBLL_BYP2 always
CLBLL_R.CLBLL_L_D.CLBLL_L_D1 hint
CLBLL_R.CLBLL_L_D.CLBLL_L_D2 hint
CLBLL_R.CLBLL_L_D.CLBLL_L_D3 hint
CLBLL_R.CLBLL_L_D.CLBLL_L_D4 hint
CLBLL_R.CLBLL_L_D.CLBLL_L_D5 hint
CLBLL_R.CLBLL_L_D.CLBLL_L_D6 hint
CLBLL_R.CLBLL_LOGIC_OUTS19.CLBLL_L_DMUX always
CLBLL_R.CLBLL_L_DMUX.CLBLL_L_COUT hint
CLBLL_R.CLBLL_L_DMUX.CLBLL_L_D hint
CLBLL_R.CLBLL_L_DX.CLBLL_BYP7 always
CLBLL_R.CLBLL_L_SR.CLBLL_CTRL0 always
CLBLL_R.CLBLL_L_A1.CLBLL_IMUX6 always
CLBLL_R.CLBLL_L_A2.CLBLL_IMUX3 always
CLBLL_R.CLBLL_L_A3.CLBLL_IMUX0 always
CLBLL_R.CLBLL_L_A4.CLBLL_IMUX10 always
CLBLL_R.CLBLL_L_A5.CLBLL_IMUX9 always
CLBLL_R.CLBLL_L_A6.CLBLL_IMUX5 always
CLBLL_R.CLBLL_L_B1.CLBLL_IMUX14 always
CLBLL_R.CLBLL_L_B2.CLBLL_IMUX19 always
CLBLL_R.CLBLL_L_B3.CLBLL_IMUX16 always
CLBLL_R.CLBLL_L_B4.CLBLL_IMUX26 always
CLBLL_R.CLBLL_L_B5.CLBLL_IMUX25 always
CLBLL_R.CLBLL_L_B6.CLBLL_IMUX13 always
CLBLL_R.CLBLL_L_C1.CLBLL_IMUX33 always
CLBLL_R.CLBLL_L_C2.CLBLL_IMUX20 always
CLBLL_R.CLBLL_L_C3.CLBLL_IMUX23 always
CLBLL_R.CLBLL_L_C4.CLBLL_IMUX21 always
CLBLL_R.CLBLL_L_C5.CLBLL_IMUX30 always
CLBLL_R.CLBLL_L_C6.CLBLL_IMUX34 always
CLBLL_R.CLBLL_L_D1.CLBLL_IMUX41 always
CLBLL_R.CLBLL_L_D2.CLBLL_IMUX36 always
CLBLL_R.CLBLL_L_D3.CLBLL_IMUX39 always
CLBLL_R.CLBLL_L_D4.CLBLL_IMUX37 always
CLBLL_R.CLBLL_L_D5.CLBLL_IMUX46 always
CLBLL_R.CLBLL_L_D6.CLBLL_IMUX42 always
CLBLL_R.CLBLL_LL_A.CLBLL_LL_A1 hint
CLBLL_R.CLBLL_LL_A.CLBLL_LL_A2 hint
CLBLL_R.CLBLL_LL_A.CLBLL_LL_A3 hint
CLBLL_R.CLBLL_LL_A.CLBLL_LL_A4 hint
CLBLL_R.CLBLL_LL_A.CLBLL_LL_A5 hint
CLBLL_R.CLBLL_LL_A.CLBLL_LL_A6 hint
CLBLL_R.CLBLL_LL_AMUX.CLBLL_LL_A hint
CLBLL_R.CLBLL_LL_AX.CLBLL_BYP1 always
CLBLL_R.CLBLL_LL_B.CLBLL_LL_B1 hint
CLBLL_R.CLBLL_LL_B.CLBLL_LL_B2 hint
CLBLL_R.CLBLL_LL_B.CLBLL_LL_B3 hint
CLBLL_R.CLBLL_LL_B.CLBLL_LL_B4 hint
CLBLL_R.CLBLL_LL_B.CLBLL_LL_B5 hint
CLBLL_R.CLBLL_LL_B.CLBLL_LL_B6 hint
CLBLL_R.CLBLL_LL_BMUX.CLBLL_LL_B hint
CLBLL_R.CLBLL_LL_BX.CLBLL_BYP4 always
CLBLL_R.CLBLL_LL_C.CLBLL_LL_C1 hint
CLBLL_R.CLBLL_LL_C.CLBLL_LL_C2 hint
CLBLL_R.CLBLL_LL_C.CLBLL_LL_C3 hint
CLBLL_R.CLBLL_LL_C.CLBLL_LL_C4 hint
CLBLL_R.CLBLL_LL_C.CLBLL_LL_C5 hint
CLBLL_R.CLBLL_LL_C.CLBLL_LL_C6 hint
CLBLL_R.CLBLL_LL_CE.CLBLL_FAN7 always
CLBLL_R.CLBLL_LL_CLK.CLBLL_CLK1 always
CLBLL_R.CLBLL_LL_CMUX.CLBLL_LL_C hint
CLBLL_R.CLBLL_LL_COUT_N.CLBLL_LL_COUT always
CLBLL_R.CLBLL_LL_CX.CLBLL_BYP3 always
CLBLL_R.CLBLL_LL_D.CLBLL_LL_D1 hint
CLBLL_R.CLBLL_LL_D.CLBLL_LL_D2 hint
CLBLL_R.CLBLL_LL_D.CLBLL_LL_D3 hint
CLBLL_R.CLBLL_LL_D.CLBLL_LL_D4 hint
CLBLL_R.CLBLL_LL_D.CLBLL_LL_D5 hint
CLBLL_R.CLBLL_LL_D.CLBLL_LL_D6 hint
CLBLL_R.CLBLL_LL_DMUX.CLBLL_LL_COUT hint
CLBLL_R.CLBLL_LL_DMUX.CLBLL_LL_D hint
CLBLL_R.CLBLL_LL_DX.CLBLL_BYP6 always
CLBLL_R.CLBLL_LL_SR.CLBLL_CTRL1 always
CLBLL_R.CLBLL_LL_A1.CLBLL_IMUX7 always
CLBLL_R.CLBLL_LL_A2.CLBLL_IMUX2 always
CLBLL_R.CLBLL_LL_A3.CLBLL_IMUX1 always
CLBLL_R.CLBLL_LL_A4.CLBLL_IMUX11 always
CLBLL_R.CLBLL_LL_A5.CLBLL_IMUX8 always
CLBLL_R.CLBLL_LL_A6.CLBLL_IMUX4 always
CLBLL_R.CLBLL_LL_B1.CLBLL_IMUX15 always
CLBLL_R.CLBLL_LL_B2.CLBLL_IMUX18 always
CLBLL_R.CLBLL_LL_B3.CLBLL_IMUX17 always
CLBLL_R.CLBLL_LL_B4.CLBLL_IMUX27 always
CLBLL_R.CLBLL_LL_B5.CLBLL_IMUX24 always
CLBLL_R.CLBLL_LL_B6.CLBLL_IMUX12 always
CLBLL_R.CLBLL_LL_C1.CLBLL_IMUX32 always
CLBLL_R.CLBLL_LL_C2.CLBLL_IMUX29 always
CLBLL_R.CLBLL_LL_C3.CLBLL_IMUX22 always
CLBLL_R.CLBLL_LL_C4.CLBLL_IMUX28 always
CLBLL_R.CLBLL_LL_C5.CLBLL_IMUX31 always
CLBLL_R.CLBLL_LL_C6.CLBLL_IMUX35 always
CLBLL_R.CLBLL_LL_D1.CLBLL_IMUX40 always
CLBLL_R.CLBLL_LL_D2.CLBLL_IMUX45 always
CLBLL_R.CLBLL_LL_D3.CLBLL_IMUX38 always
CLBLL_R.CLBLL_LL_D4.CLBLL_IMUX44 always
CLBLL_R.CLBLL_LL_D5.CLBLL_IMUX47 always
CLBLL_R.CLBLL_LL_D6.CLBLL_IMUX43 always
CLBLL_R.CLBLL_LOGIC_OUTS0.CLBLL_L_AQ always
CLBLL_R.CLBLL_LOGIC_OUTS1.CLBLL_L_BQ always
CLBLL_R.CLBLL_LOGIC_OUTS2.CLBLL_L_CQ always
CLBLL_R.CLBLL_LOGIC_OUTS3.CLBLL_L_DQ always
CLBLL_R.CLBLL_LOGIC_OUTS4.CLBLL_LL_AQ always
CLBLL_R.CLBLL_LOGIC_OUTS5.CLBLL_LL_BQ always
CLBLL_R.CLBLL_LOGIC_OUTS6.CLBLL_LL_CQ always
CLBLL_R.CLBLL_LOGIC_OUTS7.CLBLL_LL_DQ always
CLBLL_R.CLBLL_LOGIC_OUTS8.CLBLL_L_A always
CLBLL_R.CLBLL_LOGIC_OUTS9.CLBLL_L_B always
CLBLL_R.CLBLL_LOGIC_OUTS10.CLBLL_L_C always
CLBLL_R.CLBLL_LOGIC_OUTS11.CLBLL_L_D always
CLBLL_R.CLBLL_LOGIC_OUTS12.CLBLL_LL_A always
CLBLL_R.CLBLL_LOGIC_OUTS13.CLBLL_LL_B always
CLBLL_R.CLBLL_LOGIC_OUTS14.CLBLL_LL_C always
CLBLL_R.CLBLL_LOGIC_OUTS15.CLBLL_LL_D always
CLBLL_R.CLBLL_LOGIC_OUTS16.CLBLL_L_AMUX always
CLBLL_R.CLBLL_LOGIC_OUTS17.CLBLL_L_BMUX always
CLBLL_R.CLBLL_LOGIC_OUTS18.CLBLL_L_CMUX always
CLBLL_R.CLBLL_LOGIC_OUTS19.CLBLL_L_DMUX always
CLBLL_R.CLBLL_LOGIC_OUTS20.CLBLL_LL_AMUX always
CLBLL_R.CLBLL_LOGIC_OUTS21.CLBLL_LL_BMUX always
CLBLL_R.CLBLL_LOGIC_OUTS22.CLBLL_LL_CMUX always
CLBLL_R.CLBLL_LOGIC_OUTS23.CLBLL_LL_DMUX always

198
artix7/ppips_clblm_l.db
View File

@ -1,151 +1,151 @@
CLBLM_L.CLBLM_L_AX.CLBLM_BYP0 always
CLBLM_L.CLBLM_M_AX.CLBLM_BYP1 always
CLBLM_L.CLBLM_L_CX.CLBLM_BYP2 always
CLBLM_L.CLBLM_M_CX.CLBLM_BYP3 always
CLBLM_L.CLBLM_M_BX.CLBLM_BYP4 always
CLBLM_L.CLBLM_L_BX.CLBLM_BYP5 always
CLBLM_L.CLBLM_M_DX.CLBLM_BYP6 always
CLBLM_L.CLBLM_L_DX.CLBLM_BYP7 always
CLBLM_L.CLBLM_L_CLK.CLBLM_CLK0 always
CLBLM_L.CLBLM_M_CLK.CLBLM_CLK1 always
CLBLM_L.CLBLM_L_SR.CLBLM_CTRL0 always
CLBLM_L.CLBLM_M_SR.CLBLM_CTRL1 always
CLBLM_L.CLBLM_M_AI.CLBLM_FAN0 always
CLBLM_L.CLBLM_M_BI.CLBLM_FAN2 always
CLBLM_L.CLBLM_M_DI.CLBLM_FAN3 always
CLBLM_L.CLBLM_M_WE.CLBLM_FAN4 always
CLBLM_L.CLBLM_M_CI.CLBLM_FAN5 always
CLBLM_L.CLBLM_L_CE.CLBLM_FAN6 always
CLBLM_L.CLBLM_M_CE.CLBLM_FAN7 always
CLBLM_L.CLBLM_L_A3.CLBLM_IMUX0 always
CLBLM_L.CLBLM_L_A2.CLBLM_IMUX3 always
CLBLM_L.CLBLM_L_A6.CLBLM_IMUX5 always
CLBLM_L.CLBLM_L_A1.CLBLM_IMUX6 always
CLBLM_L.CLBLM_L_A5.CLBLM_IMUX9 always
CLBLM_L.CLBLM_L_A4.CLBLM_IMUX10 always
CLBLM_L.CLBLM_M_A3.CLBLM_IMUX1 always
CLBLM_L.CLBLM_M_A2.CLBLM_IMUX2 always
CLBLM_L.CLBLM_M_A6.CLBLM_IMUX4 always
CLBLM_L.CLBLM_M_A1.CLBLM_IMUX7 always
CLBLM_L.CLBLM_M_A5.CLBLM_IMUX8 always
CLBLM_L.CLBLM_M_A4.CLBLM_IMUX11 always
CLBLM_L.CLBLM_M_B6.CLBLM_IMUX12 always
CLBLM_L.CLBLM_M_B1.CLBLM_IMUX15 always
CLBLM_L.CLBLM_M_B3.CLBLM_IMUX17 always
CLBLM_L.CLBLM_M_B2.CLBLM_IMUX18 always
CLBLM_L.CLBLM_M_B5.CLBLM_IMUX24 always
CLBLM_L.CLBLM_M_B4.CLBLM_IMUX27 always
CLBLM_L.CLBLM_L_B6.CLBLM_IMUX13 always
CLBLM_L.CLBLM_L_B1.CLBLM_IMUX14 always
CLBLM_L.CLBLM_L_B3.CLBLM_IMUX16 always
CLBLM_L.CLBLM_L_B2.CLBLM_IMUX19 always
CLBLM_L.CLBLM_L_B5.CLBLM_IMUX25 always
CLBLM_L.CLBLM_L_B4.CLBLM_IMUX26 always
CLBLM_L.CLBLM_L_C2.CLBLM_IMUX20 always
CLBLM_L.CLBLM_L_C4.CLBLM_IMUX21 always
CLBLM_L.CLBLM_L_C3.CLBLM_IMUX23 always
CLBLM_L.CLBLM_L_C5.CLBLM_IMUX30 always
CLBLM_L.CLBLM_L_C1.CLBLM_IMUX33 always
CLBLM_L.CLBLM_L_C6.CLBLM_IMUX34 always
CLBLM_L.CLBLM_M_C3.CLBLM_IMUX22 always
CLBLM_L.CLBLM_M_C4.CLBLM_IMUX28 always
CLBLM_L.CLBLM_M_C2.CLBLM_IMUX29 always
CLBLM_L.CLBLM_M_C5.CLBLM_IMUX31 always
CLBLM_L.CLBLM_M_C1.CLBLM_IMUX32 always
CLBLM_L.CLBLM_M_C6.CLBLM_IMUX35 always
CLBLM_L.CLBLM_L_D2.CLBLM_IMUX36 always
CLBLM_L.CLBLM_L_D4.CLBLM_IMUX37 always
CLBLM_L.CLBLM_L_D3.CLBLM_IMUX39 always
CLBLM_L.CLBLM_L_D1.CLBLM_IMUX41 always
CLBLM_L.CLBLM_L_D6.CLBLM_IMUX42 always
CLBLM_L.CLBLM_L_D5.CLBLM_IMUX46 always
CLBLM_L.CLBLM_M_D3.CLBLM_IMUX38 always
CLBLM_L.CLBLM_M_D1.CLBLM_IMUX40 always
CLBLM_L.CLBLM_M_D6.CLBLM_IMUX43 always
CLBLM_L.CLBLM_M_D4.CLBLM_IMUX44 always
CLBLM_L.CLBLM_M_D2.CLBLM_IMUX45 always
CLBLM_L.CLBLM_M_D5.CLBLM_IMUX47 always
CLBLM_L.CLBLM_LOGIC_OUTS8.CLBLM_L_A always
CLBLM_L.CLBLM_L_AMUX.CLBLM_L_A hint
CLBLM_L.CLBLM_L_A.CLBLM_L_A1 hint
CLBLM_L.CLBLM_L_A.CLBLM_L_A2 hint
CLBLM_L.CLBLM_L_A.CLBLM_L_A3 hint
CLBLM_L.CLBLM_L_A.CLBLM_L_A4 hint
CLBLM_L.CLBLM_L_A.CLBLM_L_A5 hint
CLBLM_L.CLBLM_L_A.CLBLM_L_A6 hint
CLBLM_L.CLBLM_LOGIC_OUTS16.CLBLM_L_AMUX always
CLBLM_L.CLBLM_LOGIC_OUTS0.CLBLM_L_AQ always
CLBLM_L.CLBLM_LOGIC_OUTS9.CLBLM_L_B always
CLBLM_L.CLBLM_L_BMUX.CLBLM_L_B hint
CLBLM_L.CLBLM_L_AMUX.CLBLM_L_A hint
CLBLM_L.CLBLM_L_AX.CLBLM_BYP0 always
CLBLM_L.CLBLM_L_B.CLBLM_L_B1 hint
CLBLM_L.CLBLM_L_B.CLBLM_L_B2 hint
CLBLM_L.CLBLM_L_B.CLBLM_L_B3 hint
CLBLM_L.CLBLM_L_B.CLBLM_L_B4 hint
CLBLM_L.CLBLM_L_B.CLBLM_L_B5 hint
CLBLM_L.CLBLM_L_B.CLBLM_L_B6 hint
CLBLM_L.CLBLM_LOGIC_OUTS17.CLBLM_L_BMUX always
CLBLM_L.CLBLM_LOGIC_OUTS1.CLBLM_L_BQ always
CLBLM_L.CLBLM_LOGIC_OUTS10.CLBLM_L_C always
CLBLM_L.CLBLM_L_CMUX.CLBLM_L_C hint
CLBLM_L.CLBLM_L_BMUX.CLBLM_L_B hint
CLBLM_L.CLBLM_L_BX.CLBLM_BYP5 always
CLBLM_L.CLBLM_L_C.CLBLM_L_C1 hint
CLBLM_L.CLBLM_L_C.CLBLM_L_C2 hint
CLBLM_L.CLBLM_L_C.CLBLM_L_C3 hint
CLBLM_L.CLBLM_L_C.CLBLM_L_C4 hint
CLBLM_L.CLBLM_L_C.CLBLM_L_C5 hint
CLBLM_L.CLBLM_L_C.CLBLM_L_C6 hint
CLBLM_L.CLBLM_LOGIC_OUTS18.CLBLM_L_CMUX always
CLBLM_L.CLBLM_L_CE.CLBLM_FAN6 always
CLBLM_L.CLBLM_L_CLK.CLBLM_CLK0 always
CLBLM_L.CLBLM_L_CMUX.CLBLM_L_C hint
CLBLM_L.CLBLM_L_COUT_N.CLBLM_L_COUT always
CLBLM_L.CLBLM_L_DMUX.CLBLM_L_COUT hint
CLBLM_L.CLBLM_LOGIC_OUTS2.CLBLM_L_CQ always
CLBLM_L.CLBLM_LOGIC_OUTS11.CLBLM_L_D always
CLBLM_L.CLBLM_L_DMUX.CLBLM_L_D hint
CLBLM_L.CLBLM_L_CX.CLBLM_BYP2 always
CLBLM_L.CLBLM_L_D.CLBLM_L_D1 hint
CLBLM_L.CLBLM_L_D.CLBLM_L_D2 hint
CLBLM_L.CLBLM_L_D.CLBLM_L_D3 hint
CLBLM_L.CLBLM_L_D.CLBLM_L_D4 hint
CLBLM_L.CLBLM_L_D.CLBLM_L_D5 hint
CLBLM_L.CLBLM_L_D.CLBLM_L_D6 hint
CLBLM_L.CLBLM_LOGIC_OUTS19.CLBLM_L_DMUX always
CLBLM_L.CLBLM_L_DMUX.CLBLM_L_COUT hint
CLBLM_L.CLBLM_L_DMUX.CLBLM_L_D hint
CLBLM_L.CLBLM_L_DX.CLBLM_BYP7 always
CLBLM_L.CLBLM_L_SR.CLBLM_CTRL0 always
CLBLM_L.CLBLM_L_A1.CLBLM_IMUX6 always
CLBLM_L.CLBLM_L_A2.CLBLM_IMUX3 always
CLBLM_L.CLBLM_L_A3.CLBLM_IMUX0 always
CLBLM_L.CLBLM_L_A4.CLBLM_IMUX10 always
CLBLM_L.CLBLM_L_A5.CLBLM_IMUX9 always
CLBLM_L.CLBLM_L_A6.CLBLM_IMUX5 always
CLBLM_L.CLBLM_L_B1.CLBLM_IMUX14 always
CLBLM_L.CLBLM_L_B2.CLBLM_IMUX19 always
CLBLM_L.CLBLM_L_B3.CLBLM_IMUX16 always
CLBLM_L.CLBLM_L_B4.CLBLM_IMUX26 always
CLBLM_L.CLBLM_L_B5.CLBLM_IMUX25 always
CLBLM_L.CLBLM_L_B6.CLBLM_IMUX13 always
CLBLM_L.CLBLM_L_C1.CLBLM_IMUX33 always
CLBLM_L.CLBLM_L_C2.CLBLM_IMUX20 always
CLBLM_L.CLBLM_L_C3.CLBLM_IMUX23 always
CLBLM_L.CLBLM_L_C4.CLBLM_IMUX21 always
CLBLM_L.CLBLM_L_C5.CLBLM_IMUX30 always
CLBLM_L.CLBLM_L_C6.CLBLM_IMUX34 always
CLBLM_L.CLBLM_L_D1.CLBLM_IMUX41 always
CLBLM_L.CLBLM_L_D2.CLBLM_IMUX36 always
CLBLM_L.CLBLM_L_D3.CLBLM_IMUX39 always
CLBLM_L.CLBLM_L_D4.CLBLM_IMUX37 always
CLBLM_L.CLBLM_L_D5.CLBLM_IMUX46 always
CLBLM_L.CLBLM_L_D6.CLBLM_IMUX42 always
CLBLM_L.CLBLM_LOGIC_OUTS0.CLBLM_L_AQ always
CLBLM_L.CLBLM_LOGIC_OUTS1.CLBLM_L_BQ always
CLBLM_L.CLBLM_LOGIC_OUTS2.CLBLM_L_CQ always
CLBLM_L.CLBLM_LOGIC_OUTS3.CLBLM_L_DQ always
CLBLM_L.CLBLM_LOGIC_OUTS4.CLBLM_M_AQ always
CLBLM_L.CLBLM_LOGIC_OUTS5.CLBLM_M_BQ always
CLBLM_L.CLBLM_LOGIC_OUTS6.CLBLM_M_CQ always
CLBLM_L.CLBLM_LOGIC_OUTS7.CLBLM_M_DQ always
CLBLM_L.CLBLM_LOGIC_OUTS8.CLBLM_L_A always
CLBLM_L.CLBLM_LOGIC_OUTS9.CLBLM_L_B always
CLBLM_L.CLBLM_LOGIC_OUTS10.CLBLM_L_C always
CLBLM_L.CLBLM_LOGIC_OUTS11.CLBLM_L_D always
CLBLM_L.CLBLM_LOGIC_OUTS12.CLBLM_M_A always
CLBLM_L.CLBLM_M_AMUX.CLBLM_M_A hint
CLBLM_L.CLBLM_LOGIC_OUTS13.CLBLM_M_B always
CLBLM_L.CLBLM_LOGIC_OUTS14.CLBLM_M_C always
CLBLM_L.CLBLM_LOGIC_OUTS15.CLBLM_M_D always
CLBLM_L.CLBLM_LOGIC_OUTS16.CLBLM_L_AMUX always
CLBLM_L.CLBLM_LOGIC_OUTS17.CLBLM_L_BMUX always
CLBLM_L.CLBLM_LOGIC_OUTS18.CLBLM_L_CMUX always
CLBLM_L.CLBLM_LOGIC_OUTS19.CLBLM_L_DMUX always
CLBLM_L.CLBLM_LOGIC_OUTS20.CLBLM_M_AMUX always
CLBLM_L.CLBLM_LOGIC_OUTS21.CLBLM_M_BMUX always
CLBLM_L.CLBLM_LOGIC_OUTS22.CLBLM_M_CMUX always
CLBLM_L.CLBLM_LOGIC_OUTS23.CLBLM_M_DMUX always
CLBLM_L.CLBLM_M_A.CLBLM_M_A1 hint
CLBLM_L.CLBLM_M_A.CLBLM_M_A2 hint
CLBLM_L.CLBLM_M_A.CLBLM_M_A3 hint
CLBLM_L.CLBLM_M_A.CLBLM_M_A4 hint
CLBLM_L.CLBLM_M_A.CLBLM_M_A5 hint
CLBLM_L.CLBLM_M_A.CLBLM_M_A6 hint
CLBLM_L.CLBLM_LOGIC_OUTS20.CLBLM_M_AMUX always
CLBLM_L.CLBLM_LOGIC_OUTS4.CLBLM_M_AQ always
CLBLM_L.CLBLM_LOGIC_OUTS13.CLBLM_M_B always
CLBLM_L.CLBLM_M_BMUX.CLBLM_M_B hint
CLBLM_L.CLBLM_M_AI.CLBLM_FAN0 always
CLBLM_L.CLBLM_M_AMUX.CLBLM_M_A hint
CLBLM_L.CLBLM_M_AX.CLBLM_BYP1 always
CLBLM_L.CLBLM_M_B.CLBLM_M_B1 hint
CLBLM_L.CLBLM_M_B.CLBLM_M_B2 hint
CLBLM_L.CLBLM_M_B.CLBLM_M_B3 hint
CLBLM_L.CLBLM_M_B.CLBLM_M_B4 hint
CLBLM_L.CLBLM_M_B.CLBLM_M_B5 hint
CLBLM_L.CLBLM_M_B.CLBLM_M_B6 hint
CLBLM_L.CLBLM_LOGIC_OUTS21.CLBLM_M_BMUX always
CLBLM_L.CLBLM_LOGIC_OUTS5.CLBLM_M_BQ always
CLBLM_L.CLBLM_LOGIC_OUTS14.CLBLM_M_C always
CLBLM_L.CLBLM_M_CMUX.CLBLM_M_C hint
CLBLM_L.CLBLM_M_BI.CLBLM_FAN2 always
CLBLM_L.CLBLM_M_BMUX.CLBLM_M_B hint
CLBLM_L.CLBLM_M_BX.CLBLM_BYP4 always
CLBLM_L.CLBLM_M_C.CLBLM_M_C1 hint
CLBLM_L.CLBLM_M_C.CLBLM_M_C2 hint
CLBLM_L.CLBLM_M_C.CLBLM_M_C3 hint
CLBLM_L.CLBLM_M_C.CLBLM_M_C4 hint
CLBLM_L.CLBLM_M_C.CLBLM_M_C5 hint
CLBLM_L.CLBLM_M_C.CLBLM_M_C6 hint
CLBLM_L.CLBLM_LOGIC_OUTS22.CLBLM_M_CMUX always
CLBLM_L.CLBLM_M_CE.CLBLM_FAN7 always
CLBLM_L.CLBLM_M_CI.CLBLM_FAN5 always
CLBLM_L.CLBLM_M_CLK.CLBLM_CLK1 always
CLBLM_L.CLBLM_M_CMUX.CLBLM_M_C hint
CLBLM_L.CLBLM_M_COUT_N.CLBLM_M_COUT always
CLBLM_L.CLBLM_M_DMUX.CLBLM_M_COUT hint
CLBLM_L.CLBLM_LOGIC_OUTS6.CLBLM_M_CQ always
CLBLM_L.CLBLM_LOGIC_OUTS15.CLBLM_M_D always
CLBLM_L.CLBLM_M_DMUX.CLBLM_M_D hint
CLBLM_L.CLBLM_M_CX.CLBLM_BYP3 always
CLBLM_L.CLBLM_M_D.CLBLM_M_D1 hint
CLBLM_L.CLBLM_M_D.CLBLM_M_D2 hint
CLBLM_L.CLBLM_M_D.CLBLM_M_D3 hint
CLBLM_L.CLBLM_M_D.CLBLM_M_D4 hint
CLBLM_L.CLBLM_M_D.CLBLM_M_D5 hint
CLBLM_L.CLBLM_M_D.CLBLM_M_D6 hint
CLBLM_L.CLBLM_LOGIC_OUTS23.CLBLM_M_DMUX always
CLBLM_L.CLBLM_LOGIC_OUTS7.CLBLM_M_DQ always
CLBLM_L.CLBLM_M_DI.CLBLM_FAN3 always
CLBLM_L.CLBLM_M_DMUX.CLBLM_M_COUT hint
CLBLM_L.CLBLM_M_DMUX.CLBLM_M_D hint
CLBLM_L.CLBLM_M_DX.CLBLM_BYP6 always
CLBLM_L.CLBLM_M_SR.CLBLM_CTRL1 always
CLBLM_L.CLBLM_M_WE.CLBLM_FAN4 always
CLBLM_L.CLBLM_M_A1.CLBLM_IMUX7 always
CLBLM_L.CLBLM_M_A2.CLBLM_IMUX2 always
CLBLM_L.CLBLM_M_A3.CLBLM_IMUX1 always
CLBLM_L.CLBLM_M_A4.CLBLM_IMUX11 always
CLBLM_L.CLBLM_M_A5.CLBLM_IMUX8 always
CLBLM_L.CLBLM_M_A6.CLBLM_IMUX4 always
CLBLM_L.CLBLM_M_B1.CLBLM_IMUX15 always
CLBLM_L.CLBLM_M_B2.CLBLM_IMUX18 always
CLBLM_L.CLBLM_M_B3.CLBLM_IMUX17 always
CLBLM_L.CLBLM_M_B4.CLBLM_IMUX27 always
CLBLM_L.CLBLM_M_B5.CLBLM_IMUX24 always
CLBLM_L.CLBLM_M_B6.CLBLM_IMUX12 always
CLBLM_L.CLBLM_M_C1.CLBLM_IMUX32 always
CLBLM_L.CLBLM_M_C2.CLBLM_IMUX29 always
CLBLM_L.CLBLM_M_C3.CLBLM_IMUX22 always
CLBLM_L.CLBLM_M_C4.CLBLM_IMUX28 always
CLBLM_L.CLBLM_M_C5.CLBLM_IMUX31 always
CLBLM_L.CLBLM_M_C6.CLBLM_IMUX35 always
CLBLM_L.CLBLM_M_D1.CLBLM_IMUX40 always
CLBLM_L.CLBLM_M_D2.CLBLM_IMUX45 always
CLBLM_L.CLBLM_M_D3.CLBLM_IMUX38 always
CLBLM_L.CLBLM_M_D4.CLBLM_IMUX44 always
CLBLM_L.CLBLM_M_D5.CLBLM_IMUX47 always
CLBLM_L.CLBLM_M_D6.CLBLM_IMUX43 always

198
artix7/ppips_clblm_r.db
View File

@ -1,151 +1,151 @@
CLBLM_R.CLBLM_L_AX.CLBLM_BYP0 always
CLBLM_R.CLBLM_M_AX.CLBLM_BYP1 always
CLBLM_R.CLBLM_L_CX.CLBLM_BYP2 always
CLBLM_R.CLBLM_M_CX.CLBLM_BYP3 always
CLBLM_R.CLBLM_M_BX.CLBLM_BYP4 always
CLBLM_R.CLBLM_L_BX.CLBLM_BYP5 always
CLBLM_R.CLBLM_M_DX.CLBLM_BYP6 always
CLBLM_R.CLBLM_L_DX.CLBLM_BYP7 always
CLBLM_R.CLBLM_L_CLK.CLBLM_CLK0 always
CLBLM_R.CLBLM_M_CLK.CLBLM_CLK1 always
CLBLM_R.CLBLM_L_SR.CLBLM_CTRL0 always
CLBLM_R.CLBLM_M_SR.CLBLM_CTRL1 always
CLBLM_R.CLBLM_M_AI.CLBLM_FAN0 always
CLBLM_R.CLBLM_M_BI.CLBLM_FAN2 always
CLBLM_R.CLBLM_M_DI.CLBLM_FAN3 always
CLBLM_R.CLBLM_M_WE.CLBLM_FAN4 always
CLBLM_R.CLBLM_M_CI.CLBLM_FAN5 always
CLBLM_R.CLBLM_L_CE.CLBLM_FAN6 always
CLBLM_R.CLBLM_M_CE.CLBLM_FAN7 always
CLBLM_R.CLBLM_L_A3.CLBLM_IMUX0 always
CLBLM_R.CLBLM_L_A2.CLBLM_IMUX3 always
CLBLM_R.CLBLM_L_A6.CLBLM_IMUX5 always
CLBLM_R.CLBLM_L_A1.CLBLM_IMUX6 always
CLBLM_R.CLBLM_L_A5.CLBLM_IMUX9 always
CLBLM_R.CLBLM_L_A4.CLBLM_IMUX10 always
CLBLM_R.CLBLM_M_A3.CLBLM_IMUX1 always
CLBLM_R.CLBLM_M_A2.CLBLM_IMUX2 always
CLBLM_R.CLBLM_M_A6.CLBLM_IMUX4 always
CLBLM_R.CLBLM_M_A1.CLBLM_IMUX7 always
CLBLM_R.CLBLM_M_A5.CLBLM_IMUX8 always
CLBLM_R.CLBLM_M_A4.CLBLM_IMUX11 always
CLBLM_R.CLBLM_M_B6.CLBLM_IMUX12 always
CLBLM_R.CLBLM_M_B1.CLBLM_IMUX15 always
CLBLM_R.CLBLM_M_B3.CLBLM_IMUX17 always
CLBLM_R.CLBLM_M_B2.CLBLM_IMUX18 always
CLBLM_R.CLBLM_M_B5.CLBLM_IMUX24 always
CLBLM_R.CLBLM_M_B4.CLBLM_IMUX27 always
CLBLM_R.CLBLM_L_B6.CLBLM_IMUX13 always
CLBLM_R.CLBLM_L_B1.CLBLM_IMUX14 always
CLBLM_R.CLBLM_L_B3.CLBLM_IMUX16 always
CLBLM_R.CLBLM_L_B2.CLBLM_IMUX19 always
CLBLM_R.CLBLM_L_B5.CLBLM_IMUX25 always
CLBLM_R.CLBLM_L_B4.CLBLM_IMUX26 always
CLBLM_R.CLBLM_L_C2.CLBLM_IMUX20 always
CLBLM_R.CLBLM_L_C4.CLBLM_IMUX21 always
CLBLM_R.CLBLM_L_C3.CLBLM_IMUX23 always
CLBLM_R.CLBLM_L_C5.CLBLM_IMUX30 always
CLBLM_R.CLBLM_L_C1.CLBLM_IMUX33 always
CLBLM_R.CLBLM_L_C6.CLBLM_IMUX34 always
CLBLM_R.CLBLM_M_C3.CLBLM_IMUX22 always
CLBLM_R.CLBLM_M_C4.CLBLM_IMUX28 always
CLBLM_R.CLBLM_M_C2.CLBLM_IMUX29 always
CLBLM_R.CLBLM_M_C5.CLBLM_IMUX31 always
CLBLM_R.CLBLM_M_C1.CLBLM_IMUX32 always
CLBLM_R.CLBLM_M_C6.CLBLM_IMUX35 always
CLBLM_R.CLBLM_L_D2.CLBLM_IMUX36 always
CLBLM_R.CLBLM_L_D4.CLBLM_IMUX37 always
CLBLM_R.CLBLM_L_D3.CLBLM_IMUX39 always
CLBLM_R.CLBLM_L_D1.CLBLM_IMUX41 always
CLBLM_R.CLBLM_L_D6.CLBLM_IMUX42 always
CLBLM_R.CLBLM_L_D5.CLBLM_IMUX46 always
CLBLM_R.CLBLM_M_D3.CLBLM_IMUX38 always
CLBLM_R.CLBLM_M_D1.CLBLM_IMUX40 always
CLBLM_R.CLBLM_M_D6.CLBLM_IMUX43 always
CLBLM_R.CLBLM_M_D4.CLBLM_IMUX44 always
CLBLM_R.CLBLM_M_D2.CLBLM_IMUX45 always
CLBLM_R.CLBLM_M_D5.CLBLM_IMUX47 always
CLBLM_R.CLBLM_LOGIC_OUTS8.CLBLM_L_A always
CLBLM_R.CLBLM_L_AMUX.CLBLM_L_A hint
CLBLM_R.CLBLM_L_A.CLBLM_L_A1 hint
CLBLM_R.CLBLM_L_A.CLBLM_L_A2 hint
CLBLM_R.CLBLM_L_A.CLBLM_L_A3 hint
CLBLM_R.CLBLM_L_A.CLBLM_L_A4 hint
CLBLM_R.CLBLM_L_A.CLBLM_L_A5 hint
CLBLM_R.CLBLM_L_A.CLBLM_L_A6 hint
CLBLM_R.CLBLM_LOGIC_OUTS16.CLBLM_L_AMUX always
CLBLM_R.CLBLM_LOGIC_OUTS0.CLBLM_L_AQ always
CLBLM_R.CLBLM_LOGIC_OUTS9.CLBLM_L_B always
CLBLM_R.CLBLM_L_BMUX.CLBLM_L_B hint
CLBLM_R.CLBLM_L_AMUX.CLBLM_L_A hint
CLBLM_R.CLBLM_L_AX.CLBLM_BYP0 always
CLBLM_R.CLBLM_L_B.CLBLM_L_B1 hint
CLBLM_R.CLBLM_L_B.CLBLM_L_B2 hint
CLBLM_R.CLBLM_L_B.CLBLM_L_B3 hint
CLBLM_R.CLBLM_L_B.CLBLM_L_B4 hint
CLBLM_R.CLBLM_L_B.CLBLM_L_B5 hint
CLBLM_R.CLBLM_L_B.CLBLM_L_B6 hint
CLBLM_R.CLBLM_LOGIC_OUTS17.CLBLM_L_BMUX always
CLBLM_R.CLBLM_LOGIC_OUTS1.CLBLM_L_BQ always
CLBLM_R.CLBLM_LOGIC_OUTS10.CLBLM_L_C always
CLBLM_R.CLBLM_L_CMUX.CLBLM_L_C hint
CLBLM_R.CLBLM_L_BMUX.CLBLM_L_B hint
CLBLM_R.CLBLM_L_BX.CLBLM_BYP5 always
CLBLM_R.CLBLM_L_C.CLBLM_L_C1 hint
CLBLM_R.CLBLM_L_C.CLBLM_L_C2 hint
CLBLM_R.CLBLM_L_C.CLBLM_L_C3 hint
CLBLM_R.CLBLM_L_C.CLBLM_L_C4 hint
CLBLM_R.CLBLM_L_C.CLBLM_L_C5 hint
CLBLM_R.CLBLM_L_C.CLBLM_L_C6 hint
CLBLM_R.CLBLM_LOGIC_OUTS18.CLBLM_L_CMUX always
CLBLM_R.CLBLM_L_CE.CLBLM_FAN6 always
CLBLM_R.CLBLM_L_CLK.CLBLM_CLK0 always
CLBLM_R.CLBLM_L_CMUX.CLBLM_L_C hint
CLBLM_R.CLBLM_L_COUT_N.CLBLM_L_COUT always
CLBLM_R.CLBLM_L_DMUX.CLBLM_L_COUT hint
CLBLM_R.CLBLM_LOGIC_OUTS2.CLBLM_L_CQ always
CLBLM_R.CLBLM_LOGIC_OUTS11.CLBLM_L_D always
CLBLM_R.CLBLM_L_DMUX.CLBLM_L_D hint
CLBLM_R.CLBLM_L_CX.CLBLM_BYP2 always
CLBLM_R.CLBLM_L_D.CLBLM_L_D1 hint
CLBLM_R.CLBLM_L_D.CLBLM_L_D2 hint
CLBLM_R.CLBLM_L_D.CLBLM_L_D3 hint
CLBLM_R.CLBLM_L_D.CLBLM_L_D4 hint
CLBLM_R.CLBLM_L_D.CLBLM_L_D5 hint
CLBLM_R.CLBLM_L_D.CLBLM_L_D6 hint
CLBLM_R.CLBLM_LOGIC_OUTS19.CLBLM_L_DMUX always
CLBLM_R.CLBLM_L_DMUX.CLBLM_L_COUT hint
CLBLM_R.CLBLM_L_DMUX.CLBLM_L_D hint
CLBLM_R.CLBLM_L_DX.CLBLM_BYP7 always
CLBLM_R.CLBLM_L_SR.CLBLM_CTRL0 always
CLBLM_R.CLBLM_L_A1.CLBLM_IMUX6 always
CLBLM_R.CLBLM_L_A2.CLBLM_IMUX3 always
CLBLM_R.CLBLM_L_A3.CLBLM_IMUX0 always
CLBLM_R.CLBLM_L_A4.CLBLM_IMUX10 always
CLBLM_R.CLBLM_L_A5.CLBLM_IMUX9 always
CLBLM_R.CLBLM_L_A6.CLBLM_IMUX5 always
CLBLM_R.CLBLM_L_B1.CLBLM_IMUX14 always
CLBLM_R.CLBLM_L_B2.CLBLM_IMUX19 always
CLBLM_R.CLBLM_L_B3.CLBLM_IMUX16 always
CLBLM_R.CLBLM_L_B4.CLBLM_IMUX26 always
CLBLM_R.CLBLM_L_B5.CLBLM_IMUX25 always
CLBLM_R.CLBLM_L_B6.CLBLM_IMUX13 always
CLBLM_R.CLBLM_L_C1.CLBLM_IMUX33 always
CLBLM_R.CLBLM_L_C2.CLBLM_IMUX20 always
CLBLM_R.CLBLM_L_C3.CLBLM_IMUX23 always
CLBLM_R.CLBLM_L_C4.CLBLM_IMUX21 always
CLBLM_R.CLBLM_L_C5.CLBLM_IMUX30 always
CLBLM_R.CLBLM_L_C6.CLBLM_IMUX34 always
CLBLM_R.CLBLM_L_D1.CLBLM_IMUX41 always
CLBLM_R.CLBLM_L_D2.CLBLM_IMUX36 always
CLBLM_R.CLBLM_L_D3.CLBLM_IMUX39 always
CLBLM_R.CLBLM_L_D4.CLBLM_IMUX37 always
CLBLM_R.CLBLM_L_D5.CLBLM_IMUX46 always
CLBLM_R.CLBLM_L_D6.CLBLM_IMUX42 always
CLBLM_R.CLBLM_LOGIC_OUTS0.CLBLM_L_AQ always
CLBLM_R.CLBLM_LOGIC_OUTS1.CLBLM_L_BQ always
CLBLM_R.CLBLM_LOGIC_OUTS2.CLBLM_L_CQ always
CLBLM_R.CLBLM_LOGIC_OUTS3.CLBLM_L_DQ always
CLBLM_R.CLBLM_LOGIC_OUTS4.CLBLM_M_AQ always
CLBLM_R.CLBLM_LOGIC_OUTS5.CLBLM_M_BQ always
CLBLM_R.CLBLM_LOGIC_OUTS6.CLBLM_M_CQ always
CLBLM_R.CLBLM_LOGIC_OUTS7.CLBLM_M_DQ always
CLBLM_R.CLBLM_LOGIC_OUTS8.CLBLM_L_A always
CLBLM_R.CLBLM_LOGIC_OUTS9.CLBLM_L_B always
CLBLM_R.CLBLM_LOGIC_OUTS10.CLBLM_L_C always
CLBLM_R.CLBLM_LOGIC_OUTS11.CLBLM_L_D always
CLBLM_R.CLBLM_LOGIC_OUTS12.CLBLM_M_A always
CLBLM_R.CLBLM_M_AMUX.CLBLM_M_A hint
CLBLM_R.CLBLM_LOGIC_OUTS13.CLBLM_M_B always
CLBLM_R.CLBLM_LOGIC_OUTS14.CLBLM_M_C always
CLBLM_R.CLBLM_LOGIC_OUTS15.CLBLM_M_D always
CLBLM_R.CLBLM_LOGIC_OUTS16.CLBLM_L_AMUX always
CLBLM_R.CLBLM_LOGIC_OUTS17.CLBLM_L_BMUX always
CLBLM_R.CLBLM_LOGIC_OUTS18.CLBLM_L_CMUX always
CLBLM_R.CLBLM_LOGIC_OUTS19.CLBLM_L_DMUX always
CLBLM_R.CLBLM_LOGIC_OUTS20.CLBLM_M_AMUX always
CLBLM_R.CLBLM_LOGIC_OUTS21.CLBLM_M_BMUX always
CLBLM_R.CLBLM_LOGIC_OUTS22.CLBLM_M_CMUX always
CLBLM_R.CLBLM_LOGIC_OUTS23.CLBLM_M_DMUX always
CLBLM_R.CLBLM_M_A.CLBLM_M_A1 hint
CLBLM_R.CLBLM_M_A.CLBLM_M_A2 hint
CLBLM_R.CLBLM_M_A.CLBLM_M_A3 hint
CLBLM_R.CLBLM_M_A.CLBLM_M_A4 hint
CLBLM_R.CLBLM_M_A.CLBLM_M_A5 hint
CLBLM_R.CLBLM_M_A.CLBLM_M_A6 hint
CLBLM_R.CLBLM_LOGIC_OUTS20.CLBLM_M_AMUX always
CLBLM_R.CLBLM_LOGIC_OUTS4.CLBLM_M_AQ always
CLBLM_R.CLBLM_LOGIC_OUTS13.CLBLM_M_B always
CLBLM_R.CLBLM_M_BMUX.CLBLM_M_B hint
CLBLM_R.CLBLM_M_AI.CLBLM_FAN0 always
CLBLM_R.CLBLM_M_AMUX.CLBLM_M_A hint
CLBLM_R.CLBLM_M_AX.CLBLM_BYP1 always
CLBLM_R.CLBLM_M_B.CLBLM_M_B1 hint
CLBLM_R.CLBLM_M_B.CLBLM_M_B2 hint
CLBLM_R.CLBLM_M_B.CLBLM_M_B3 hint
CLBLM_R.CLBLM_M_B.CLBLM_M_B4 hint
CLBLM_R.CLBLM_M_B.CLBLM_M_B5 hint
CLBLM_R.CLBLM_M_B.CLBLM_M_B6 hint
CLBLM_R.CLBLM_LOGIC_OUTS21.CLBLM_M_BMUX always
CLBLM_R.CLBLM_LOGIC_OUTS5.CLBLM_M_BQ always
CLBLM_R.CLBLM_LOGIC_OUTS14.CLBLM_M_C always
CLBLM_R.CLBLM_M_CMUX.CLBLM_M_C hint
CLBLM_R.CLBLM_M_BI.CLBLM_FAN2 always
CLBLM_R.CLBLM_M_BMUX.CLBLM_M_B hint
CLBLM_R.CLBLM_M_BX.CLBLM_BYP4 always
CLBLM_R.CLBLM_M_C.CLBLM_M_C1 hint
CLBLM_R.CLBLM_M_C.CLBLM_M_C2 hint
CLBLM_R.CLBLM_M_C.CLBLM_M_C3 hint
CLBLM_R.CLBLM_M_C.CLBLM_M_C4 hint
CLBLM_R.CLBLM_M_C.CLBLM_M_C5 hint
CLBLM_R.CLBLM_M_C.CLBLM_M_C6 hint
CLBLM_R.CLBLM_LOGIC_OUTS22.CLBLM_M_CMUX always
CLBLM_R.CLBLM_M_CE.CLBLM_FAN7 always
CLBLM_R.CLBLM_M_CI.CLBLM_FAN5 always
CLBLM_R.CLBLM_M_CLK.CLBLM_CLK1 always
CLBLM_R.CLBLM_M_CMUX.CLBLM_M_C hint
CLBLM_R.CLBLM_M_COUT_N.CLBLM_M_COUT always
CLBLM_R.CLBLM_M_DMUX.CLBLM_M_COUT hint
CLBLM_R.CLBLM_LOGIC_OUTS6.CLBLM_M_CQ always
CLBLM_R.CLBLM_LOGIC_OUTS15.CLBLM_M_D always
CLBLM_R.CLBLM_M_DMUX.CLBLM_M_D hint
CLBLM_R.CLBLM_M_CX.CLBLM_BYP3 always
CLBLM_R.CLBLM_M_D.CLBLM_M_D1 hint
CLBLM_R.CLBLM_M_D.CLBLM_M_D2 hint
CLBLM_R.CLBLM_M_D.CLBLM_M_D3 hint
CLBLM_R.CLBLM_M_D.CLBLM_M_D4 hint
CLBLM_R.CLBLM_M_D.CLBLM_M_D5 hint
CLBLM_R.CLBLM_M_D.CLBLM_M_D6 hint
CLBLM_R.CLBLM_LOGIC_OUTS23.CLBLM_M_DMUX always
CLBLM_R.CLBLM_LOGIC_OUTS7.CLBLM_M_DQ always
CLBLM_R.CLBLM_M_DI.CLBLM_FAN3 always
CLBLM_R.CLBLM_M_DMUX.CLBLM_M_COUT hint
CLBLM_R.CLBLM_M_DMUX.CLBLM_M_D hint
CLBLM_R.CLBLM_M_DX.CLBLM_BYP6 always
CLBLM_R.CLBLM_M_SR.CLBLM_CTRL1 always
CLBLM_R.CLBLM_M_WE.CLBLM_FAN4 always
CLBLM_R.CLBLM_M_A1.CLBLM_IMUX7 always
CLBLM_R.CLBLM_M_A2.CLBLM_IMUX2 always
CLBLM_R.CLBLM_M_A3.CLBLM_IMUX1 always
CLBLM_R.CLBLM_M_A4.CLBLM_IMUX11 always
CLBLM_R.CLBLM_M_A5.CLBLM_IMUX8 always
CLBLM_R.CLBLM_M_A6.CLBLM_IMUX4 always
CLBLM_R.CLBLM_M_B1.CLBLM_IMUX15 always
CLBLM_R.CLBLM_M_B2.CLBLM_IMUX18 always
CLBLM_R.CLBLM_M_B3.CLBLM_IMUX17 always
CLBLM_R.CLBLM_M_B4.CLBLM_IMUX27 always
CLBLM_R.CLBLM_M_B5.CLBLM_IMUX24 always
CLBLM_R.CLBLM_M_B6.CLBLM_IMUX12 always
CLBLM_R.CLBLM_M_C1.CLBLM_IMUX32 always
CLBLM_R.CLBLM_M_C2.CLBLM_IMUX29 always
CLBLM_R.CLBLM_M_C3.CLBLM_IMUX22 always
CLBLM_R.CLBLM_M_C4.CLBLM_IMUX28 always
CLBLM_R.CLBLM_M_C5.CLBLM_IMUX31 always
CLBLM_R.CLBLM_M_C6.CLBLM_IMUX35 always
CLBLM_R.CLBLM_M_D1.CLBLM_IMUX40 always
CLBLM_R.CLBLM_M_D2.CLBLM_IMUX45 always
CLBLM_R.CLBLM_M_D3.CLBLM_IMUX38 always
CLBLM_R.CLBLM_M_D4.CLBLM_IMUX44 always
CLBLM_R.CLBLM_M_D5.CLBLM_IMUX47 always
CLBLM_R.CLBLM_M_D6.CLBLM_IMUX43 always

16
artix7/ppips_int_l.db
View File

@ -30,15 +30,15 @@ INT_L.FAN_L4.FAN_ALT4 always
INT_L.FAN_L5.FAN_ALT5 always
INT_L.FAN_L6.FAN_ALT6 always
INT_L.FAN_L7.FAN_ALT7 always
INT_L.GCLK_L_B10_WEST.GCLK_L_B10 always
INT_L.GCLK_L_B10_EAST.GCLK_L_B10 always
INT_L.GCLK_L_B11_WEST.GCLK_L_B11 always
INT_L.GCLK_L_B11_EAST.GCLK_L_B11 always
INT_L.GCLK_L_B6_WEST.GCLK_L_B6 always
INT_L.GCLK_L_B6_EAST.GCLK_L_B6 always
INT_L.GCLK_L_B7_WEST.GCLK_L_B7 always
INT_L.GCLK_L_B6_WEST.GCLK_L_B6 always
INT_L.GCLK_L_B7_EAST.GCLK_L_B7 always
INT_L.GCLK_L_B8_WEST.GCLK_L_B8 always
INT_L.GCLK_L_B7_WEST.GCLK_L_B7 always
INT_L.GCLK_L_B8_EAST.GCLK_L_B8 always
INT_L.GCLK_L_B9_WEST.GCLK_L_B9 always
INT_L.GCLK_L_B8_WEST.GCLK_L_B8 always
INT_L.GCLK_L_B9_EAST.GCLK_L_B9 always
INT_L.GCLK_L_B9_WEST.GCLK_L_B9 always
INT_L.GCLK_L_B10_EAST.GCLK_L_B10 always
INT_L.GCLK_L_B10_WEST.GCLK_L_B10 always
INT_L.GCLK_L_B11_EAST.GCLK_L_B11 always
INT_L.GCLK_L_B11_WEST.GCLK_L_B11 always

32
artix7/ppips_int_r.db
View File

@ -6,14 +6,6 @@ INT_R.BYP_BOUNCE4.BYP_ALT4 always
INT_R.BYP_BOUNCE5.BYP_ALT5 always
INT_R.BYP_BOUNCE6.BYP_ALT6 always
INT_R.BYP_BOUNCE7.BYP_ALT7 always
INT_R.BYP0.BYP_ALT0 always
INT_R.BYP1.BYP_ALT1 always
INT_R.BYP2.BYP_ALT2 always
INT_R.BYP3.BYP_ALT3 always
INT_R.BYP4.BYP_ALT4 always
INT_R.BYP5.BYP_ALT5 always
INT_R.BYP6.BYP_ALT6 always
INT_R.BYP7.BYP_ALT7 always
INT_R.FAN_BOUNCE0.FAN_ALT0 always
INT_R.FAN_BOUNCE1.FAN_ALT1 always
INT_R.FAN_BOUNCE2.FAN_ALT2 always
@ -22,14 +14,6 @@ INT_R.FAN_BOUNCE4.FAN_ALT4 always
INT_R.FAN_BOUNCE5.FAN_ALT5 always
INT_R.FAN_BOUNCE6.FAN_ALT6 always
INT_R.FAN_BOUNCE7.FAN_ALT7 always
INT_R.FAN0.FAN_ALT0 always
INT_R.FAN1.FAN_ALT1 always
INT_R.FAN2.FAN_ALT2 always
INT_R.FAN3.FAN_ALT3 always
INT_R.FAN4.FAN_ALT4 always
INT_R.FAN5.FAN_ALT5 always
INT_R.FAN6.FAN_ALT6 always
INT_R.FAN7.FAN_ALT7 always
INT_R.GCLK_B0_EAST.GCLK_B0 always
INT_R.GCLK_B0_WEST.GCLK_B0 always
INT_R.GCLK_B1_EAST.GCLK_B1 always
@ -42,3 +26,19 @@ INT_R.GCLK_B4_EAST.GCLK_B4 always
INT_R.GCLK_B4_WEST.GCLK_B4 always
INT_R.GCLK_B5_EAST.GCLK_B5 always
INT_R.GCLK_B5_WEST.GCLK_B5 always
INT_R.BYP0.BYP_ALT0 always
INT_R.BYP1.BYP_ALT1 always
INT_R.BYP2.BYP_ALT2 always
INT_R.BYP3.BYP_ALT3 always
INT_R.BYP4.BYP_ALT4 always
INT_R.BYP5.BYP_ALT5 always
INT_R.BYP6.BYP_ALT6 always
INT_R.BYP7.BYP_ALT7 always
INT_R.FAN0.FAN_ALT0 always
INT_R.FAN1.FAN_ALT1 always
INT_R.FAN2.FAN_ALT2 always
INT_R.FAN3.FAN_ALT3 always
INT_R.FAN4.FAN_ALT4 always
INT_R.FAN5.FAN_ALT5 always
INT_R.FAN6.FAN_ALT6 always
INT_R.FAN7.FAN_ALT7 always

53728
artix7/segbits_bram_l.block_ram.db
View File

File diff suppressed because it is too large Load Diff

168
artix7/segbits_bram_l.db
View File

@ -1,12 +1,4 @@
BRAM_L.RAMB18_Y0.INIT_A[0] 27_73
BRAM_L.RAMB18_Y0.INIT_A[10] 27_129
BRAM_L.RAMB18_Y0.INIT_A[11] 27_113
BRAM_L.RAMB18_Y0.INIT_A[12] 27_97
BRAM_L.RAMB18_Y0.INIT_A[13] 27_81
BRAM_L.RAMB18_Y0.INIT_A[14] 27_49
BRAM_L.RAMB18_Y0.INIT_A[15] 27_33
BRAM_L.RAMB18_Y0.INIT_A[16] 27_17
BRAM_L.RAMB18_Y0.INIT_A[17] 27_01
BRAM_L.RAMB18_Y0.INIT_A[1] 27_65
BRAM_L.RAMB18_Y0.INIT_A[2] 27_137
BRAM_L.RAMB18_Y0.INIT_A[3] 27_121
@ -16,15 +8,15 @@ BRAM_L.RAMB18_Y0.INIT_A[6] 27_57
BRAM_L.RAMB18_Y0.INIT_A[7] 27_41
BRAM_L.RAMB18_Y0.INIT_A[8] 27_25
BRAM_L.RAMB18_Y0.INIT_A[9] 27_09
BRAM_L.RAMB18_Y0.INIT_A[10] 27_129
BRAM_L.RAMB18_Y0.INIT_A[11] 27_113
BRAM_L.RAMB18_Y0.INIT_A[12] 27_97
BRAM_L.RAMB18_Y0.INIT_A[13] 27_81
BRAM_L.RAMB18_Y0.INIT_A[14] 27_49
BRAM_L.RAMB18_Y0.INIT_A[15] 27_33
BRAM_L.RAMB18_Y0.INIT_A[16] 27_17
BRAM_L.RAMB18_Y0.INIT_A[17] 27_01
BRAM_L.RAMB18_Y0.INIT_B[0] 27_79
BRAM_L.RAMB18_Y0.INIT_B[10] 27_135
BRAM_L.RAMB18_Y0.INIT_B[11] 27_119
BRAM_L.RAMB18_Y0.INIT_B[12] 27_103
BRAM_L.RAMB18_Y0.INIT_B[13] 27_87
BRAM_L.RAMB18_Y0.INIT_B[14] 27_55
BRAM_L.RAMB18_Y0.INIT_B[15] 27_39
BRAM_L.RAMB18_Y0.INIT_B[16] 27_23
BRAM_L.RAMB18_Y0.INIT_B[17] 27_07
BRAM_L.RAMB18_Y0.INIT_B[1] 27_71
BRAM_L.RAMB18_Y0.INIT_B[2] 27_143
BRAM_L.RAMB18_Y0.INIT_B[3] 27_127
@ -34,23 +26,23 @@ BRAM_L.RAMB18_Y0.INIT_B[6] 27_63
BRAM_L.RAMB18_Y0.INIT_B[7] 27_47
BRAM_L.RAMB18_Y0.INIT_B[8] 27_31
BRAM_L.RAMB18_Y0.INIT_B[9] 27_15
BRAM_L.RAMB18_Y0.INIT_B[10] 27_135
BRAM_L.RAMB18_Y0.INIT_B[11] 27_119
BRAM_L.RAMB18_Y0.INIT_B[12] 27_103
BRAM_L.RAMB18_Y0.INIT_B[13] 27_87
BRAM_L.RAMB18_Y0.INIT_B[14] 27_55
BRAM_L.RAMB18_Y0.INIT_B[15] 27_39
BRAM_L.RAMB18_Y0.INIT_B[16] 27_23
BRAM_L.RAMB18_Y0.INIT_B[17] 27_07
BRAM_L.RAMB18_Y0.READ_WIDTH_A_2 27_35 !27_36 !27_37
BRAM_L.RAMB18_Y0.READ_WIDTH_A_4 !27_35 27_36 !27_37
BRAM_L.RAMB18_Y0.READ_WIDTH_A_9 27_35 27_36 !27_37
BRAM_L.RAMB18_Y0.READ_WIDTH_A_18 !27_35 !27_36 27_37
BRAM_L.RAMB18_Y0.READ_WIDTH_A_2 !27_36 !27_37 27_35
BRAM_L.RAMB18_Y0.READ_WIDTH_A_4 !27_35 !27_37 27_36
BRAM_L.RAMB18_Y0.READ_WIDTH_A_9 !27_37 27_35 27_36
BRAM_L.RAMB18_Y0.READ_WIDTH_B_2 27_43 !27_44 !27_45
BRAM_L.RAMB18_Y0.READ_WIDTH_B_4 !27_43 27_44 !27_45
BRAM_L.RAMB18_Y0.READ_WIDTH_B_9 27_43 27_44 !27_45
BRAM_L.RAMB18_Y0.READ_WIDTH_B_18 !27_43 !27_44 27_45
BRAM_L.RAMB18_Y0.READ_WIDTH_B_2 !27_44 !27_45 27_43
BRAM_L.RAMB18_Y0.READ_WIDTH_B_4 !27_43 !27_45 27_44
BRAM_L.RAMB18_Y0.READ_WIDTH_B_9 !27_45 27_43 27_44
BRAM_L.RAMB18_Y0.SRVAL_A[0] 27_74
BRAM_L.RAMB18_Y0.SRVAL_A[10] 27_130
BRAM_L.RAMB18_Y0.SRVAL_A[11] 27_114
BRAM_L.RAMB18_Y0.SRVAL_A[12] 27_98
BRAM_L.RAMB18_Y0.SRVAL_A[13] 27_82
BRAM_L.RAMB18_Y0.SRVAL_A[14] 27_50
BRAM_L.RAMB18_Y0.SRVAL_A[15] 27_34
BRAM_L.RAMB18_Y0.SRVAL_A[16] 27_18
BRAM_L.RAMB18_Y0.SRVAL_A[17] 27_02
BRAM_L.RAMB18_Y0.SRVAL_A[1] 27_66
BRAM_L.RAMB18_Y0.SRVAL_A[2] 27_138
BRAM_L.RAMB18_Y0.SRVAL_A[3] 27_122
@ -60,15 +52,15 @@ BRAM_L.RAMB18_Y0.SRVAL_A[6] 27_58
BRAM_L.RAMB18_Y0.SRVAL_A[7] 27_42
BRAM_L.RAMB18_Y0.SRVAL_A[8] 27_26
BRAM_L.RAMB18_Y0.SRVAL_A[9] 27_10
BRAM_L.RAMB18_Y0.SRVAL_A[10] 27_130
BRAM_L.RAMB18_Y0.SRVAL_A[11] 27_114
BRAM_L.RAMB18_Y0.SRVAL_A[12] 27_98
BRAM_L.RAMB18_Y0.SRVAL_A[13] 27_82
BRAM_L.RAMB18_Y0.SRVAL_A[14] 27_50
BRAM_L.RAMB18_Y0.SRVAL_A[15] 27_34
BRAM_L.RAMB18_Y0.SRVAL_A[16] 27_18
BRAM_L.RAMB18_Y0.SRVAL_A[17] 27_02
BRAM_L.RAMB18_Y0.SRVAL_B[0] 27_78
BRAM_L.RAMB18_Y0.SRVAL_B[10] 27_134
BRAM_L.RAMB18_Y0.SRVAL_B[11] 27_118
BRAM_L.RAMB18_Y0.SRVAL_B[12] 27_102
BRAM_L.RAMB18_Y0.SRVAL_B[13] 27_86
BRAM_L.RAMB18_Y0.SRVAL_B[14] 27_54
BRAM_L.RAMB18_Y0.SRVAL_B[15] 27_38
BRAM_L.RAMB18_Y0.SRVAL_B[16] 27_22
BRAM_L.RAMB18_Y0.SRVAL_B[17] 27_06
BRAM_L.RAMB18_Y0.SRVAL_B[1] 27_70
BRAM_L.RAMB18_Y0.SRVAL_B[2] 27_142
BRAM_L.RAMB18_Y0.SRVAL_B[3] 27_126
@ -78,18 +70,26 @@ BRAM_L.RAMB18_Y0.SRVAL_B[6] 27_62
BRAM_L.RAMB18_Y0.SRVAL_B[7] 27_46
BRAM_L.RAMB18_Y0.SRVAL_B[8] 27_30
BRAM_L.RAMB18_Y0.SRVAL_B[9] 27_14
BRAM_L.RAMB18_Y0.SRVAL_B[10] 27_134
BRAM_L.RAMB18_Y0.SRVAL_B[11] 27_118
BRAM_L.RAMB18_Y0.SRVAL_B[12] 27_102
BRAM_L.RAMB18_Y0.SRVAL_B[13] 27_86
BRAM_L.RAMB18_Y0.SRVAL_B[14] 27_54
BRAM_L.RAMB18_Y0.SRVAL_B[15] 27_38
BRAM_L.RAMB18_Y0.SRVAL_B[16] 27_22
BRAM_L.RAMB18_Y0.SRVAL_B[17] 27_06
BRAM_L.RAMB18_Y0.WRITE_MODE_A_NO_CHANGE 27_64
BRAM_L.RAMB18_Y0.WRITE_MODE_A_READ_FIRST 27_56
BRAM_L.RAMB18_Y0.WRITE_MODE_B_NO_CHANGE 27_68
BRAM_L.RAMB18_Y0.WRITE_MODE_B_READ_FIRST 27_67
BRAM_L.RAMB18_Y0.WRITE_WIDTH_A_2 27_51 !27_52 !27_53
BRAM_L.RAMB18_Y0.WRITE_WIDTH_A_4 !27_51 27_52 !27_53
BRAM_L.RAMB18_Y0.WRITE_WIDTH_A_9 27_51 27_52 !27_53
BRAM_L.RAMB18_Y0.WRITE_WIDTH_A_18 !27_51 !27_52 27_53
BRAM_L.RAMB18_Y0.WRITE_WIDTH_A_2 !27_52 !27_53 27_51
BRAM_L.RAMB18_Y0.WRITE_WIDTH_A_4 !27_51 !27_53 27_52
BRAM_L.RAMB18_Y0.WRITE_WIDTH_A_9 !27_53 27_51 27_52
BRAM_L.RAMB18_Y0.WRITE_WIDTH_B_2 27_59 !27_60 !27_61
BRAM_L.RAMB18_Y0.WRITE_WIDTH_B_4 !27_59 27_60 !27_61
BRAM_L.RAMB18_Y0.WRITE_WIDTH_B_9 27_59 27_60 !27_61
BRAM_L.RAMB18_Y0.WRITE_WIDTH_B_18 !27_59 !27_60 27_61
BRAM_L.RAMB18_Y0.WRITE_WIDTH_B_2 !27_60 !27_61 27_59
BRAM_L.RAMB18_Y0.WRITE_WIDTH_B_4 !27_59 !27_61 27_60
BRAM_L.RAMB18_Y0.WRITE_WIDTH_B_9 !27_61 27_59 27_60
BRAM_L.RAMB18_Y0.ZINV_CLKARDCLK 27_107
BRAM_L.RAMB18_Y0.ZINV_CLKBWRCLK 27_109
BRAM_L.RAMB18_Y0.ZINV_ENARDEN 27_112
@ -99,14 +99,6 @@ BRAM_L.RAMB18_Y0.ZINV_RSTRAMB 27_117
BRAM_L.RAMB18_Y0.ZINV_RSTREGARSTREG 27_120
BRAM_L.RAMB18_Y0.ZINV_RSTREGB 27_123
BRAM_L.RAMB18_Y1.INIT_A[0] 27_249
BRAM_L.RAMB18_Y1.INIT_A[10] 27_305
BRAM_L.RAMB18_Y1.INIT_A[11] 27_289
BRAM_L.RAMB18_Y1.INIT_A[12] 27_273
BRAM_L.RAMB18_Y1.INIT_A[13] 27_257
BRAM_L.RAMB18_Y1.INIT_A[14] 27_225
BRAM_L.RAMB18_Y1.INIT_A[15] 27_209
BRAM_L.RAMB18_Y1.INIT_A[16] 27_193
BRAM_L.RAMB18_Y1.INIT_A[17] 27_177
BRAM_L.RAMB18_Y1.INIT_A[1] 27_241
BRAM_L.RAMB18_Y1.INIT_A[2] 27_313
BRAM_L.RAMB18_Y1.INIT_A[3] 27_297
@ -116,15 +108,15 @@ BRAM_L.RAMB18_Y1.INIT_A[6] 27_233
BRAM_L.RAMB18_Y1.INIT_A[7] 27_217
BRAM_L.RAMB18_Y1.INIT_A[8] 27_201
BRAM_L.RAMB18_Y1.INIT_A[9] 27_185
BRAM_L.RAMB18_Y1.INIT_A[10] 27_305
BRAM_L.RAMB18_Y1.INIT_A[11] 27_289
BRAM_L.RAMB18_Y1.INIT_A[12] 27_273
BRAM_L.RAMB18_Y1.INIT_A[13] 27_257
BRAM_L.RAMB18_Y1.INIT_A[14] 27_225
BRAM_L.RAMB18_Y1.INIT_A[15] 27_209
BRAM_L.RAMB18_Y1.INIT_A[16] 27_193
BRAM_L.RAMB18_Y1.INIT_A[17] 27_177
BRAM_L.RAMB18_Y1.INIT_B[0] 27_255
BRAM_L.RAMB18_Y1.INIT_B[10] 27_311
BRAM_L.RAMB18_Y1.INIT_B[11] 27_295
BRAM_L.RAMB18_Y1.INIT_B[12] 27_279
BRAM_L.RAMB18_Y1.INIT_B[13] 27_263
BRAM_L.RAMB18_Y1.INIT_B[14] 27_231
BRAM_L.RAMB18_Y1.INIT_B[15] 27_215
BRAM_L.RAMB18_Y1.INIT_B[16] 27_199
BRAM_L.RAMB18_Y1.INIT_B[17] 27_183
BRAM_L.RAMB18_Y1.INIT_B[1] 27_247
BRAM_L.RAMB18_Y1.INIT_B[2] 27_319
BRAM_L.RAMB18_Y1.INIT_B[3] 27_303
@ -134,23 +126,23 @@ BRAM_L.RAMB18_Y1.INIT_B[6] 27_239
BRAM_L.RAMB18_Y1.INIT_B[7] 27_223
BRAM_L.RAMB18_Y1.INIT_B[8] 27_207
BRAM_L.RAMB18_Y1.INIT_B[9] 27_191
BRAM_L.RAMB18_Y1.READ_WIDTH_A_18 !27_284 !27_285 27_283
BRAM_L.RAMB18_Y1.INIT_B[10] 27_311
BRAM_L.RAMB18_Y1.INIT_B[11] 27_295
BRAM_L.RAMB18_Y1.INIT_B[12] 27_279
BRAM_L.RAMB18_Y1.INIT_B[13] 27_263
BRAM_L.RAMB18_Y1.INIT_B[14] 27_231
BRAM_L.RAMB18_Y1.INIT_B[15] 27_215
BRAM_L.RAMB18_Y1.INIT_B[16] 27_199
BRAM_L.RAMB18_Y1.INIT_B[17] 27_183
BRAM_L.RAMB18_Y1.READ_WIDTH_A_2 !27_283 !27_284 27_285
BRAM_L.RAMB18_Y1.READ_WIDTH_A_4 !27_283 !27_285 27_284
BRAM_L.RAMB18_Y1.READ_WIDTH_A_4 !27_283 27_284 !27_285
BRAM_L.RAMB18_Y1.READ_WIDTH_A_9 !27_283 27_284 27_285
BRAM_L.RAMB18_Y1.READ_WIDTH_B_18 !27_276 !27_277 27_275
BRAM_L.RAMB18_Y1.READ_WIDTH_A_18 27_283 !27_284 !27_285
BRAM_L.RAMB18_Y1.READ_WIDTH_B_2 !27_275 !27_276 27_277
BRAM_L.RAMB18_Y1.READ_WIDTH_B_4 !27_275 !27_277 27_276
BRAM_L.RAMB18_Y1.READ_WIDTH_B_4 !27_275 27_276 !27_277
BRAM_L.RAMB18_Y1.READ_WIDTH_B_9 !27_275 27_276 27_277
BRAM_L.RAMB18_Y1.READ_WIDTH_B_18 27_275 !27_276 !27_277
BRAM_L.RAMB18_Y1.SRVAL_A[0] 27_250
BRAM_L.RAMB18_Y1.SRVAL_A[10] 27_306
BRAM_L.RAMB18_Y1.SRVAL_A[11] 27_290
BRAM_L.RAMB18_Y1.SRVAL_A[12] 27_274
BRAM_L.RAMB18_Y1.SRVAL_A[13] 27_258
BRAM_L.RAMB18_Y1.SRVAL_A[14] 27_226
BRAM_L.RAMB18_Y1.SRVAL_A[15] 27_210
BRAM_L.RAMB18_Y1.SRVAL_A[16] 27_194
BRAM_L.RAMB18_Y1.SRVAL_A[17] 27_178
BRAM_L.RAMB18_Y1.SRVAL_A[1] 27_242
BRAM_L.RAMB18_Y1.SRVAL_A[2] 27_314
BRAM_L.RAMB18_Y1.SRVAL_A[3] 27_298
@ -160,15 +152,15 @@ BRAM_L.RAMB18_Y1.SRVAL_A[6] 27_234
BRAM_L.RAMB18_Y1.SRVAL_A[7] 27_218
BRAM_L.RAMB18_Y1.SRVAL_A[8] 27_202
BRAM_L.RAMB18_Y1.SRVAL_A[9] 27_186
BRAM_L.RAMB18_Y1.SRVAL_A[10] 27_306
BRAM_L.RAMB18_Y1.SRVAL_A[11] 27_290
BRAM_L.RAMB18_Y1.SRVAL_A[12] 27_274
BRAM_L.RAMB18_Y1.SRVAL_A[13] 27_258
BRAM_L.RAMB18_Y1.SRVAL_A[14] 27_226
BRAM_L.RAMB18_Y1.SRVAL_A[15] 27_210
BRAM_L.RAMB18_Y1.SRVAL_A[16] 27_194
BRAM_L.RAMB18_Y1.SRVAL_A[17] 27_178
BRAM_L.RAMB18_Y1.SRVAL_B[0] 27_254
BRAM_L.RAMB18_Y1.SRVAL_B[10] 27_310
BRAM_L.RAMB18_Y1.SRVAL_B[11] 27_294
BRAM_L.RAMB18_Y1.SRVAL_B[12] 27_278
BRAM_L.RAMB18_Y1.SRVAL_B[13] 27_262
BRAM_L.RAMB18_Y1.SRVAL_B[14] 27_230
BRAM_L.RAMB18_Y1.SRVAL_B[15] 27_214
BRAM_L.RAMB18_Y1.SRVAL_B[16] 27_198
BRAM_L.RAMB18_Y1.SRVAL_B[17] 27_182
BRAM_L.RAMB18_Y1.SRVAL_B[1] 27_246
BRAM_L.RAMB18_Y1.SRVAL_B[2] 27_318
BRAM_L.RAMB18_Y1.SRVAL_B[3] 27_302
@ -178,18 +170,26 @@ BRAM_L.RAMB18_Y1.SRVAL_B[6] 27_238
BRAM_L.RAMB18_Y1.SRVAL_B[7] 27_222
BRAM_L.RAMB18_Y1.SRVAL_B[8] 27_206
BRAM_L.RAMB18_Y1.SRVAL_B[9] 27_190
BRAM_L.RAMB18_Y1.SRVAL_B[10] 27_310
BRAM_L.RAMB18_Y1.SRVAL_B[11] 27_294
BRAM_L.RAMB18_Y1.SRVAL_B[12] 27_278
BRAM_L.RAMB18_Y1.SRVAL_B[13] 27_262
BRAM_L.RAMB18_Y1.SRVAL_B[14] 27_230
BRAM_L.RAMB18_Y1.SRVAL_B[15] 27_214
BRAM_L.RAMB18_Y1.SRVAL_B[16] 27_198
BRAM_L.RAMB18_Y1.SRVAL_B[17] 27_182
BRAM_L.RAMB18_Y1.WRITE_MODE_A_NO_CHANGE 27_256
BRAM_L.RAMB18_Y1.WRITE_MODE_A_READ_FIRST 27_264
BRAM_L.RAMB18_Y1.WRITE_MODE_B_NO_CHANGE 27_252
BRAM_L.RAMB18_Y1.WRITE_MODE_B_READ_FIRST 27_253
BRAM_L.RAMB18_Y1.WRITE_WIDTH_A_18 !27_268 !27_269 27_267
BRAM_L.RAMB18_Y1.WRITE_WIDTH_A_2 !27_267 !27_268 27_269
BRAM_L.RAMB18_Y1.WRITE_WIDTH_A_4 !27_267 !27_269 27_268
BRAM_L.RAMB18_Y1.WRITE_WIDTH_A_4 !27_267 27_268 !27_269
BRAM_L.RAMB18_Y1.WRITE_WIDTH_A_9 !27_267 27_268 27_269
BRAM_L.RAMB18_Y1.WRITE_WIDTH_B_18 !27_260 !27_261 27_259
BRAM_L.RAMB18_Y1.WRITE_WIDTH_A_18 27_267 !27_268 !27_269
BRAM_L.RAMB18_Y1.WRITE_WIDTH_B_2 !27_259 !27_260 27_261
BRAM_L.RAMB18_Y1.WRITE_WIDTH_B_4 !27_259 !27_261 27_260
BRAM_L.RAMB18_Y1.WRITE_WIDTH_B_4 !27_259 27_260 !27_261
BRAM_L.RAMB18_Y1.WRITE_WIDTH_B_9 !27_259 27_260 27_261
BRAM_L.RAMB18_Y1.WRITE_WIDTH_B_18 27_259 !27_260 !27_261
BRAM_L.RAMB18_Y1.ZINV_CLKARDCLK 27_213
BRAM_L.RAMB18_Y1.ZINV_CLKBWRCLK 27_211
BRAM_L.RAMB18_Y1.ZINV_ENARDEN 27_208

53728
artix7/segbits_bram_r.block_ram.db
View File

File diff suppressed because it is too large Load Diff

168
artix7/segbits_bram_r.db
View File

@ -1,12 +1,4 @@
BRAM_R.RAMB18_Y0.INIT_A[0] 27_73
BRAM_R.RAMB18_Y0.INIT_A[10] 27_129
BRAM_R.RAMB18_Y0.INIT_A[11] 27_113
BRAM_R.RAMB18_Y0.INIT_A[12] 27_97
BRAM_R.RAMB18_Y0.INIT_A[13] 27_81
BRAM_R.RAMB18_Y0.INIT_A[14] 27_49
BRAM_R.RAMB18_Y0.INIT_A[15] 27_33
BRAM_R.RAMB18_Y0.INIT_A[16] 27_17
BRAM_R.RAMB18_Y0.INIT_A[17] 27_01
BRAM_R.RAMB18_Y0.INIT_A[1] 27_65
BRAM_R.RAMB18_Y0.INIT_A[2] 27_137
BRAM_R.RAMB18_Y0.INIT_A[3] 27_121
@ -16,15 +8,15 @@ BRAM_R.RAMB18_Y0.INIT_A[6] 27_57
BRAM_R.RAMB18_Y0.INIT_A[7] 27_41
BRAM_R.RAMB18_Y0.INIT_A[8] 27_25
BRAM_R.RAMB18_Y0.INIT_A[9] 27_09
BRAM_R.RAMB18_Y0.INIT_A[10] 27_129
BRAM_R.RAMB18_Y0.INIT_A[11] 27_113
BRAM_R.RAMB18_Y0.INIT_A[12] 27_97
BRAM_R.RAMB18_Y0.INIT_A[13] 27_81
BRAM_R.RAMB18_Y0.INIT_A[14] 27_49
BRAM_R.RAMB18_Y0.INIT_A[15] 27_33
BRAM_R.RAMB18_Y0.INIT_A[16] 27_17
BRAM_R.RAMB18_Y0.INIT_A[17] 27_01
BRAM_R.RAMB18_Y0.INIT_B[0] 27_79
BRAM_R.RAMB18_Y0.INIT_B[10] 27_135
BRAM_R.RAMB18_Y0.INIT_B[11] 27_119
BRAM_R.RAMB18_Y0.INIT_B[12] 27_103
BRAM_R.RAMB18_Y0.INIT_B[13] 27_87
BRAM_R.RAMB18_Y0.INIT_B[14] 27_55
BRAM_R.RAMB18_Y0.INIT_B[15] 27_39
BRAM_R.RAMB18_Y0.INIT_B[16] 27_23
BRAM_R.RAMB18_Y0.INIT_B[17] 27_07
BRAM_R.RAMB18_Y0.INIT_B[1] 27_71
BRAM_R.RAMB18_Y0.INIT_B[2] 27_143
BRAM_R.RAMB18_Y0.INIT_B[3] 27_127
@ -34,23 +26,23 @@ BRAM_R.RAMB18_Y0.INIT_B[6] 27_63
BRAM_R.RAMB18_Y0.INIT_B[7] 27_47
BRAM_R.RAMB18_Y0.INIT_B[8] 27_31
BRAM_R.RAMB18_Y0.INIT_B[9] 27_15
BRAM_R.RAMB18_Y0.INIT_B[10] 27_135
BRAM_R.RAMB18_Y0.INIT_B[11] 27_119
BRAM_R.RAMB18_Y0.INIT_B[12] 27_103
BRAM_R.RAMB18_Y0.INIT_B[13] 27_87
BRAM_R.RAMB18_Y0.INIT_B[14] 27_55
BRAM_R.RAMB18_Y0.INIT_B[15] 27_39
BRAM_R.RAMB18_Y0.INIT_B[16] 27_23
BRAM_R.RAMB18_Y0.INIT_B[17] 27_07
BRAM_R.RAMB18_Y0.READ_WIDTH_A_2 27_35 !27_36 !27_37
BRAM_R.RAMB18_Y0.READ_WIDTH_A_4 !27_35 27_36 !27_37
BRAM_R.RAMB18_Y0.READ_WIDTH_A_9 27_35 27_36 !27_37
BRAM_R.RAMB18_Y0.READ_WIDTH_A_18 !27_35 !27_36 27_37
BRAM_R.RAMB18_Y0.READ_WIDTH_A_2 !27_36 !27_37 27_35
BRAM_R.RAMB18_Y0.READ_WIDTH_A_4 !27_35 !27_37 27_36
BRAM_R.RAMB18_Y0.READ_WIDTH_A_9 !27_37 27_35 27_36
BRAM_R.RAMB18_Y0.READ_WIDTH_B_2 27_43 !27_44 !27_45
BRAM_R.RAMB18_Y0.READ_WIDTH_B_4 !27_43 27_44 !27_45
BRAM_R.RAMB18_Y0.READ_WIDTH_B_9 27_43 27_44 !27_45
BRAM_R.RAMB18_Y0.READ_WIDTH_B_18 !27_43 !27_44 27_45
BRAM_R.RAMB18_Y0.READ_WIDTH_B_2 !27_44 !27_45 27_43
BRAM_R.RAMB18_Y0.READ_WIDTH_B_4 !27_43 !27_45 27_44
BRAM_R.RAMB18_Y0.READ_WIDTH_B_9 !27_45 27_43 27_44
BRAM_R.RAMB18_Y0.SRVAL_A[0] 27_74
BRAM_R.RAMB18_Y0.SRVAL_A[10] 27_130
BRAM_R.RAMB18_Y0.SRVAL_A[11] 27_114
BRAM_R.RAMB18_Y0.SRVAL_A[12] 27_98
BRAM_R.RAMB18_Y0.SRVAL_A[13] 27_82
BRAM_R.RAMB18_Y0.SRVAL_A[14] 27_50
BRAM_R.RAMB18_Y0.SRVAL_A[15] 27_34
BRAM_R.RAMB18_Y0.SRVAL_A[16] 27_18
BRAM_R.RAMB18_Y0.SRVAL_A[17] 27_02
BRAM_R.RAMB18_Y0.SRVAL_A[1] 27_66
BRAM_R.RAMB18_Y0.SRVAL_A[2] 27_138
BRAM_R.RAMB18_Y0.SRVAL_A[3] 27_122
@ -60,15 +52,15 @@ BRAM_R.RAMB18_Y0.SRVAL_A[6] 27_58
BRAM_R.RAMB18_Y0.SRVAL_A[7] 27_42
BRAM_R.RAMB18_Y0.SRVAL_A[8] 27_26
BRAM_R.RAMB18_Y0.SRVAL_A[9] 27_10
BRAM_R.RAMB18_Y0.SRVAL_A[10] 27_130
BRAM_R.RAMB18_Y0.SRVAL_A[11] 27_114
BRAM_R.RAMB18_Y0.SRVAL_A[12] 27_98
BRAM_R.RAMB18_Y0.SRVAL_A[13] 27_82
BRAM_R.RAMB18_Y0.SRVAL_A[14] 27_50
BRAM_R.RAMB18_Y0.SRVAL_A[15] 27_34
BRAM_R.RAMB18_Y0.SRVAL_A[16] 27_18
BRAM_R.RAMB18_Y0.SRVAL_A[17] 27_02
BRAM_R.RAMB18_Y0.SRVAL_B[0] 27_78
BRAM_R.RAMB18_Y0.SRVAL_B[10] 27_134
BRAM_R.RAMB18_Y0.SRVAL_B[11] 27_118
BRAM_R.RAMB18_Y0.SRVAL_B[12] 27_102
BRAM_R.RAMB18_Y0.SRVAL_B[13] 27_86
BRAM_R.RAMB18_Y0.SRVAL_B[14] 27_54
BRAM_R.RAMB18_Y0.SRVAL_B[15] 27_38
BRAM_R.RAMB18_Y0.SRVAL_B[16] 27_22
BRAM_R.RAMB18_Y0.SRVAL_B[17] 27_06
BRAM_R.RAMB18_Y0.SRVAL_B[1] 27_70
BRAM_R.RAMB18_Y0.SRVAL_B[2] 27_142
BRAM_R.RAMB18_Y0.SRVAL_B[3] 27_126
@ -78,18 +70,26 @@ BRAM_R.RAMB18_Y0.SRVAL_B[6] 27_62
BRAM_R.RAMB18_Y0.SRVAL_B[7] 27_46
BRAM_R.RAMB18_Y0.SRVAL_B[8] 27_30
BRAM_R.RAMB18_Y0.SRVAL_B[9] 27_14
BRAM_R.RAMB18_Y0.SRVAL_B[10] 27_134
BRAM_R.RAMB18_Y0.SRVAL_B[11] 27_118
BRAM_R.RAMB18_Y0.SRVAL_B[12] 27_102
BRAM_R.RAMB18_Y0.SRVAL_B[13] 27_86
BRAM_R.RAMB18_Y0.SRVAL_B[14] 27_54
BRAM_R.RAMB18_Y0.SRVAL_B[15] 27_38
BRAM_R.RAMB18_Y0.SRVAL_B[16] 27_22
BRAM_R.RAMB18_Y0.SRVAL_B[17] 27_06
BRAM_R.RAMB18_Y0.WRITE_MODE_A_NO_CHANGE 27_64
BRAM_R.RAMB18_Y0.WRITE_MODE_A_READ_FIRST 27_56
BRAM_R.RAMB18_Y0.WRITE_MODE_B_NO_CHANGE 27_68
BRAM_R.RAMB18_Y0.WRITE_MODE_B_READ_FIRST 27_67
BRAM_R.RAMB18_Y0.WRITE_WIDTH_A_2 27_51 !27_52 !27_53
BRAM_R.RAMB18_Y0.WRITE_WIDTH_A_4 !27_51 27_52 !27_53
BRAM_R.RAMB18_Y0.WRITE_WIDTH_A_9 27_51 27_52 !27_53
BRAM_R.RAMB18_Y0.WRITE_WIDTH_A_18 !27_51 !27_52 27_53
BRAM_R.RAMB18_Y0.WRITE_WIDTH_A_2 !27_52 !27_53 27_51
BRAM_R.RAMB18_Y0.WRITE_WIDTH_A_4 !27_51 !27_53 27_52
BRAM_R.RAMB18_Y0.WRITE_WIDTH_A_9 !27_53 27_51 27_52
BRAM_R.RAMB18_Y0.WRITE_WIDTH_B_2 27_59 !27_60 !27_61
BRAM_R.RAMB18_Y0.WRITE_WIDTH_B_4 !27_59 27_60 !27_61
BRAM_R.RAMB18_Y0.WRITE_WIDTH_B_9 27_59 27_60 !27_61
BRAM_R.RAMB18_Y0.WRITE_WIDTH_B_18 !27_59 !27_60 27_61
BRAM_R.RAMB18_Y0.WRITE_WIDTH_B_2 !27_60 !27_61 27_59
BRAM_R.RAMB18_Y0.WRITE_WIDTH_B_4 !27_59 !27_61 27_60
BRAM_R.RAMB18_Y0.WRITE_WIDTH_B_9 !27_61 27_59 27_60
BRAM_R.RAMB18_Y0.ZINV_CLKARDCLK 27_107
BRAM_R.RAMB18_Y0.ZINV_CLKBWRCLK 27_109
BRAM_R.RAMB18_Y0.ZINV_ENARDEN 27_112
@ -99,14 +99,6 @@ BRAM_R.RAMB18_Y0.ZINV_RSTRAMB 27_117
BRAM_R.RAMB18_Y0.ZINV_RSTREGARSTREG 27_120
BRAM_R.RAMB18_Y0.ZINV_RSTREGB 27_123
BRAM_R.RAMB18_Y1.INIT_A[0] 27_249
BRAM_R.RAMB18_Y1.INIT_A[10] 27_305
BRAM_R.RAMB18_Y1.INIT_A[11] 27_289
BRAM_R.RAMB18_Y1.INIT_A[12] 27_273
BRAM_R.RAMB18_Y1.INIT_A[13] 27_257
BRAM_R.RAMB18_Y1.INIT_A[14] 27_225
BRAM_R.RAMB18_Y1.INIT_A[15] 27_209
BRAM_R.RAMB18_Y1.INIT_A[16] 27_193
BRAM_R.RAMB18_Y1.INIT_A[17] 27_177
BRAM_R.RAMB18_Y1.INIT_A[1] 27_241
BRAM_R.RAMB18_Y1.INIT_A[2] 27_313
BRAM_R.RAMB18_Y1.INIT_A[3] 27_297
@ -116,15 +108,15 @@ BRAM_R.RAMB18_Y1.INIT_A[6] 27_233
BRAM_R.RAMB18_Y1.INIT_A[7] 27_217
BRAM_R.RAMB18_Y1.INIT_A[8] 27_201
BRAM_R.RAMB18_Y1.INIT_A[9] 27_185
BRAM_R.RAMB18_Y1.INIT_A[10] 27_305
BRAM_R.RAMB18_Y1.INIT_A[11] 27_289
BRAM_R.RAMB18_Y1.INIT_A[12] 27_273
BRAM_R.RAMB18_Y1.INIT_A[13] 27_257
BRAM_R.RAMB18_Y1.INIT_A[14] 27_225
BRAM_R.RAMB18_Y1.INIT_A[15] 27_209
BRAM_R.RAMB18_Y1.INIT_A[16] 27_193
BRAM_R.RAMB18_Y1.INIT_A[17] 27_177
BRAM_R.RAMB18_Y1.INIT_B[0] 27_255
BRAM_R.RAMB18_Y1.INIT_B[10] 27_311
BRAM_R.RAMB18_Y1.INIT_B[11] 27_295
BRAM_R.RAMB18_Y1.INIT_B[12] 27_279
BRAM_R.RAMB18_Y1.INIT_B[13] 27_263
BRAM_R.RAMB18_Y1.INIT_B[14] 27_231
BRAM_R.RAMB18_Y1.INIT_B[15] 27_215
BRAM_R.RAMB18_Y1.INIT_B[16] 27_199
BRAM_R.RAMB18_Y1.INIT_B[17] 27_183
BRAM_R.RAMB18_Y1.INIT_B[1] 27_247
BRAM_R.RAMB18_Y1.INIT_B[2] 27_319
BRAM_R.RAMB18_Y1.INIT_B[3] 27_303
@ -134,23 +126,23 @@ BRAM_R.RAMB18_Y1.INIT_B[6] 27_239
BRAM_R.RAMB18_Y1.INIT_B[7] 27_223
BRAM_R.RAMB18_Y1.INIT_B[8] 27_207
BRAM_R.RAMB18_Y1.INIT_B[9] 27_191
BRAM_R.RAMB18_Y1.READ_WIDTH_A_18 !27_284 !27_285 27_283
BRAM_R.RAMB18_Y1.INIT_B[10] 27_311
BRAM_R.RAMB18_Y1.INIT_B[11] 27_295
BRAM_R.RAMB18_Y1.INIT_B[12] 27_279
BRAM_R.RAMB18_Y1.INIT_B[13] 27_263
BRAM_R.RAMB18_Y1.INIT_B[14] 27_231
BRAM_R.RAMB18_Y1.INIT_B[15] 27_215
BRAM_R.RAMB18_Y1.INIT_B[16] 27_199
BRAM_R.RAMB18_Y1.INIT_B[17] 27_183
BRAM_R.RAMB18_Y1.READ_WIDTH_A_2 !27_283 !27_284 27_285
BRAM_R.RAMB18_Y1.READ_WIDTH_A_4 !27_283 !27_285 27_284
BRAM_R.RAMB18_Y1.READ_WIDTH_A_4 !27_283 27_284 !27_285
BRAM_R.RAMB18_Y1.READ_WIDTH_A_9 !27_283 27_284 27_285
BRAM_R.RAMB18_Y1.READ_WIDTH_B_18 !27_276 !27_277 27_275
BRAM_R.RAMB18_Y1.READ_WIDTH_A_18 27_283 !27_284 !27_285
BRAM_R.RAMB18_Y1.READ_WIDTH_B_2 !27_275 !27_276 27_277
BRAM_R.RAMB18_Y1.READ_WIDTH_B_4 !27_275 !27_277 27_276
BRAM_R.RAMB18_Y1.READ_WIDTH_B_4 !27_275 27_276 !27_277
BRAM_R.RAMB18_Y1.READ_WIDTH_B_9 !27_275 27_276 27_277
BRAM_R.RAMB18_Y1.READ_WIDTH_B_18 27_275 !27_276 !27_277
BRAM_R.RAMB18_Y1.SRVAL_A[0] 27_250
BRAM_R.RAMB18_Y1.SRVAL_A[10] 27_306
BRAM_R.RAMB18_Y1.SRVAL_A[11] 27_290
BRAM_R.RAMB18_Y1.SRVAL_A[12] 27_274
BRAM_R.RAMB18_Y1.SRVAL_A[13] 27_258
BRAM_R.RAMB18_Y1.SRVAL_A[14] 27_226
BRAM_R.RAMB18_Y1.SRVAL_A[15] 27_210
BRAM_R.RAMB18_Y1.SRVAL_A[16] 27_194
BRAM_R.RAMB18_Y1.SRVAL_A[17] 27_178
BRAM_R.RAMB18_Y1.SRVAL_A[1] 27_242
BRAM_R.RAMB18_Y1.SRVAL_A[2] 27_314
BRAM_R.RAMB18_Y1.SRVAL_A[3] 27_298
@ -160,15 +152,15 @@ BRAM_R.RAMB18_Y1.SRVAL_A[6] 27_234
BRAM_R.RAMB18_Y1.SRVAL_A[7] 27_218
BRAM_R.RAMB18_Y1.SRVAL_A[8] 27_202
BRAM_R.RAMB18_Y1.SRVAL_A[9] 27_186
BRAM_R.RAMB18_Y1.SRVAL_A[10] 27_306
BRAM_R.RAMB18_Y1.SRVAL_A[11] 27_290
BRAM_R.RAMB18_Y1.SRVAL_A[12] 27_274
BRAM_R.RAMB18_Y1.SRVAL_A[13] 27_258
BRAM_R.RAMB18_Y1.SRVAL_A[14] 27_226
BRAM_R.RAMB18_Y1.SRVAL_A[15] 27_210
BRAM_R.RAMB18_Y1.SRVAL_A[16] 27_194
BRAM_R.RAMB18_Y1.SRVAL_A[17] 27_178
BRAM_R.RAMB18_Y1.SRVAL_B[0] 27_254
BRAM_R.RAMB18_Y1.SRVAL_B[10] 27_310
BRAM_R.RAMB18_Y1.SRVAL_B[11] 27_294
BRAM_R.RAMB18_Y1.SRVAL_B[12] 27_278
BRAM_R.RAMB18_Y1.SRVAL_B[13] 27_262
BRAM_R.RAMB18_Y1.SRVAL_B[14] 27_230
BRAM_R.RAMB18_Y1.SRVAL_B[15] 27_214
BRAM_R.RAMB18_Y1.SRVAL_B[16] 27_198
BRAM_R.RAMB18_Y1.SRVAL_B[17] 27_182
BRAM_R.RAMB18_Y1.SRVAL_B[1] 27_246
BRAM_R.RAMB18_Y1.SRVAL_B[2] 27_318
BRAM_R.RAMB18_Y1.SRVAL_B[3] 27_302
@ -178,18 +170,26 @@ BRAM_R.RAMB18_Y1.SRVAL_B[6] 27_238
BRAM_R.RAMB18_Y1.SRVAL_B[7] 27_222
BRAM_R.RAMB18_Y1.SRVAL_B[8] 27_206
BRAM_R.RAMB18_Y1.SRVAL_B[9] 27_190
BRAM_R.RAMB18_Y1.SRVAL_B[10] 27_310
BRAM_R.RAMB18_Y1.SRVAL_B[11] 27_294
BRAM_R.RAMB18_Y1.SRVAL_B[12] 27_278
BRAM_R.RAMB18_Y1.SRVAL_B[13] 27_262
BRAM_R.RAMB18_Y1.SRVAL_B[14] 27_230
BRAM_R.RAMB18_Y1.SRVAL_B[15] 27_214
BRAM_R.RAMB18_Y1.SRVAL_B[16] 27_198
BRAM_R.RAMB18_Y1.SRVAL_B[17] 27_182
BRAM_R.RAMB18_Y1.WRITE_MODE_A_NO_CHANGE 27_256
BRAM_R.RAMB18_Y1.WRITE_MODE_A_READ_FIRST 27_264
BRAM_R.RAMB18_Y1.WRITE_MODE_B_NO_CHANGE 27_252
BRAM_R.RAMB18_Y1.WRITE_MODE_B_READ_FIRST 27_253
BRAM_R.RAMB18_Y1.WRITE_WIDTH_A_18 !27_268 !27_269 27_267
BRAM_R.RAMB18_Y1.WRITE_WIDTH_A_2 !27_267 !27_268 27_269
BRAM_R.RAMB18_Y1.WRITE_WIDTH_A_4 !27_267 !27_269 27_268
BRAM_R.RAMB18_Y1.WRITE_WIDTH_A_4 !27_267 27_268 !27_269
BRAM_R.RAMB18_Y1.WRITE_WIDTH_A_9 !27_267 27_268 27_269
BRAM_R.RAMB18_Y1.WRITE_WIDTH_B_18 !27_260 !27_261 27_259
BRAM_R.RAMB18_Y1.WRITE_WIDTH_A_18 27_267 !27_268 !27_269
BRAM_R.RAMB18_Y1.WRITE_WIDTH_B_2 !27_259 !27_260 27_261
BRAM_R.RAMB18_Y1.WRITE_WIDTH_B_4 !27_259 !27_261 27_260
BRAM_R.RAMB18_Y1.WRITE_WIDTH_B_4 !27_259 27_260 !27_261
BRAM_R.RAMB18_Y1.WRITE_WIDTH_B_9 !27_259 27_260 27_261
BRAM_R.RAMB18_Y1.WRITE_WIDTH_B_18 27_259 !27_260 !27_261
BRAM_R.RAMB18_Y1.ZINV_CLKARDCLK 27_213
BRAM_R.RAMB18_Y1.ZINV_CLKBWRCLK 27_211
BRAM_R.RAMB18_Y1.ZINV_ENARDEN 27_208

174
artix7/segbits_clbll_l.db
View File

@ -4,12 +4,12 @@ CLBLL_L.SLICEL_X0.A5FFMUX.IN_A 30_09
CLBLL_L.SLICEL_X0.A5FFMUX.IN_B 30_10
CLBLL_L.SLICEL_X0.AFF.ZINI 31_03
CLBLL_L.SLICEL_X0.AFF.ZRST 30_12
CLBLL_L.SLICEL_X0.AFFMUX.AX !30_00 !30_02 !30_03 30_01
CLBLL_L.SLICEL_X0.AFFMUX.CY !30_01 !30_03 30_00 30_02
CLBLL_L.SLICEL_X0.AFFMUX.F7 !30_02 !30_03 30_00 30_01
CLBLL_L.SLICEL_X0.AFFMUX.O5 !30_01 !30_02 30_00 30_03
CLBLL_L.SLICEL_X0.AFFMUX.AX !30_00 30_01 !30_02 !30_03
CLBLL_L.SLICEL_X0.AFFMUX.CY 30_00 !30_01 30_02 !30_03
CLBLL_L.SLICEL_X0.AFFMUX.XOR !30_00 !30_01 30_02 !30_03
CLBLL_L.SLICEL_X0.AFFMUX.F7 30_00 30_01 !30_02 !30_03
CLBLL_L.SLICEL_X0.AFFMUX.O5 30_00 !30_01 !30_02 30_03
CLBLL_L.SLICEL_X0.AFFMUX.O6 !30_00 !30_01 !30_02 30_03
CLBLL_L.SLICEL_X0.AFFMUX.XOR !30_00 !30_01 !30_03 30_02
CLBLL_L.SLICEL_X0.ALUT.INIT[00] 32_15
CLBLL_L.SLICEL_X0.ALUT.INIT[01] 33_15
CLBLL_L.SLICEL_X0.ALUT.INIT[02] 32_14
@ -75,24 +75,24 @@ CLBLL_L.SLICEL_X0.ALUT.INIT[61] 34_01
CLBLL_L.SLICEL_X0.ALUT.INIT[62] 35_00
CLBLL_L.SLICEL_X0.ALUT.INIT[63] 34_00
CLBLL_L.SLICEL_X0.ALUT.RAM 31_16
CLBLL_L.SLICEL_X0.AOUTMUX.A5Q !30_06 !30_08 !30_11 30_07
CLBLL_L.SLICEL_X0.AOUTMUX.CY !30_07 !30_11 30_06 30_08
CLBLL_L.SLICEL_X0.AOUTMUX.F7 !30_08 !30_11 30_06 30_07
CLBLL_L.SLICEL_X0.AOUTMUX.O5 !30_07 !30_08 30_06 30_11
CLBLL_L.SLICEL_X0.AOUTMUX.A5Q !30_06 30_07 !30_08 !30_11
CLBLL_L.SLICEL_X0.AOUTMUX.CY 30_06 !30_07 30_08 !30_11
CLBLL_L.SLICEL_X0.AOUTMUX.XOR !30_06 !30_07 30_08 !30_11
CLBLL_L.SLICEL_X0.AOUTMUX.F7 30_06 30_07 !30_08 !30_11
CLBLL_L.SLICEL_X0.AOUTMUX.O5 30_06 !30_07 !30_08 30_11
CLBLL_L.SLICEL_X0.AOUTMUX.O6 !30_06 !30_07 !30_08 30_11
CLBLL_L.SLICEL_X0.AOUTMUX.XOR !30_06 !30_07 !30_11 30_08
CLBLL_L.SLICEL_X0.B5FF.ZINI 31_22
CLBLL_L.SLICEL_X0.B5FF.ZRST 01_19
CLBLL_L.SLICEL_X0.B5FFMUX.IN_A 30_19
CLBLL_L.SLICEL_X0.B5FFMUX.IN_B 30_18
CLBLL_L.SLICEL_X0.BFF.ZINI 31_28
CLBLL_L.SLICEL_X0.BFF.ZRST 30_30
CLBLL_L.SLICEL_X0.BFFMUX.BX !30_24 !30_25 !30_27 30_26
CLBLL_L.SLICEL_X0.BFFMUX.CY !30_24 !30_26 30_25 30_27
CLBLL_L.SLICEL_X0.BFFMUX.BX !30_24 !30_25 30_26 !30_27
CLBLL_L.SLICEL_X0.BFFMUX.CY !30_24 30_25 !30_26 30_27
CLBLL_L.SLICEL_X0.BFFMUX.XOR !30_24 30_25 !30_26 !30_27
CLBLL_L.SLICEL_X0.BFFMUX.F8 !30_24 !30_25 30_26 30_27
CLBLL_L.SLICEL_X0.BFFMUX.O5 !30_25 !30_26 30_24 30_27
CLBLL_L.SLICEL_X0.BFFMUX.O6 !30_25 !30_26 !30_27 30_24
CLBLL_L.SLICEL_X0.BFFMUX.XOR !30_24 !30_26 !30_27 30_25
CLBLL_L.SLICEL_X0.BFFMUX.O5 30_24 !30_25 !30_26 30_27
CLBLL_L.SLICEL_X0.BFFMUX.O6 30_24 !30_25 !30_26 !30_27
CLBLL_L.SLICEL_X0.BLUT.INIT[00] 32_31
CLBLL_L.SLICEL_X0.BLUT.INIT[01] 33_31
CLBLL_L.SLICEL_X0.BLUT.INIT[02] 32_30
@ -159,28 +159,24 @@ CLBLL_L.SLICEL_X0.BLUT.INIT[62] 35_16
CLBLL_L.SLICEL_X0.BLUT.INIT[63] 34_16
CLBLL_L.SLICEL_X0.BLUT.RAM 31_17
CLBLL_L.SLICEL_X0.BOUTMUX.B5Q !30_20 !30_21 !30_22 30_23
CLBLL_L.SLICEL_X0.BOUTMUX.CY !30_20 !30_23 30_21 30_22
CLBLL_L.SLICEL_X0.BOUTMUX.CY !30_20 30_21 30_22 !30_23
CLBLL_L.SLICEL_X0.BOUTMUX.XOR !30_20 30_21 !30_22 !30_23
CLBLL_L.SLICEL_X0.BOUTMUX.F8 !30_20 !30_21 30_22 30_23
CLBLL_L.SLICEL_X0.BOUTMUX.O5 !30_21 !30_23 30_20 30_22
CLBLL_L.SLICEL_X0.BOUTMUX.O6 !30_21 !30_22 !30_23 30_20
CLBLL_L.SLICEL_X0.BOUTMUX.XOR !30_20 !30_22 !30_23 30_21
CLBLL_L.SLICEL_X0.BOUTMUX.O5 30_20 !30_21 30_22 !30_23
CLBLL_L.SLICEL_X0.BOUTMUX.O6 30_20 !30_21 !30_22 !30_23
CLBLL_L.SLICEL_X0.C5FF.ZINI 31_41
CLBLL_L.SLICEL_X0.C5FF.ZRST 01_47
CLBLL_L.SLICEL_X0.C5FFMUX.IN_A 31_45
CLBLL_L.SLICEL_X0.C5FFMUX.IN_B 30_39
CLBLL_L.SLICEL_X0.CARRY4.ACY0 30_15
CLBLL_L.SLICEL_X0.CARRY4.BCY0 01_15
CLBLL_L.SLICEL_X0.CARRY4.CCY0 30_48
CLBLL_L.SLICEL_X0.CARRY4.DCY0 30_49
CLBLL_L.SLICEL_X0.CEUSEDMUX 01_39
CLBLL_L.SLICEL_X0.CFF.ZINI 31_33
CLBLL_L.SLICEL_X0.CFF.ZRST 30_33
CLBLL_L.SLICEL_X0.CFFMUX.CX !30_35 !30_37 !30_38 30_36
CLBLL_L.SLICEL_X0.CFFMUX.CY !30_36 !30_38 30_35 30_37
CLBLL_L.SLICEL_X0.CFFMUX.F7 !30_37 !30_38 30_35 30_36
CLBLL_L.SLICEL_X0.CFFMUX.O5 !30_36 !30_37 30_35 30_38
CLBLL_L.SLICEL_X0.CFFMUX.CX !30_35 30_36 !30_37 !30_38
CLBLL_L.SLICEL_X0.CFFMUX.CY 30_35 !30_36 30_37 !30_38
CLBLL_L.SLICEL_X0.CFFMUX.XOR !30_35 !30_36 30_37 !30_38
CLBLL_L.SLICEL_X0.CFFMUX.F7 30_35 30_36 !30_37 !30_38
CLBLL_L.SLICEL_X0.CFFMUX.O5 30_35 !30_36 !30_37 30_38
CLBLL_L.SLICEL_X0.CFFMUX.O6 !30_35 !30_36 !30_37 30_38
CLBLL_L.SLICEL_X0.CFFMUX.XOR !30_35 !30_36 !30_38 30_37
CLBLL_L.SLICEL_X0.CLKINV 01_51
CLBLL_L.SLICEL_X0.CLUT.INIT[00] 32_47
CLBLL_L.SLICEL_X0.CLUT.INIT[01] 33_47
@ -247,23 +243,23 @@ CLBLL_L.SLICEL_X0.CLUT.INIT[61] 34_33
CLBLL_L.SLICEL_X0.CLUT.INIT[62] 35_32
CLBLL_L.SLICEL_X0.CLUT.INIT[63] 34_32
CLBLL_L.SLICEL_X0.CLUT.RAM 31_46
CLBLL_L.SLICEL_X0.COUTMUX.C5Q !30_40 !30_44 !30_45 30_43
CLBLL_L.SLICEL_X0.COUTMUX.CY !30_43 !30_45 30_40 30_44
CLBLL_L.SLICEL_X0.COUTMUX.F7 !30_44 !30_45 30_40 30_43
CLBLL_L.SLICEL_X0.COUTMUX.O5 !30_43 !30_44 30_40 30_45
CLBLL_L.SLICEL_X0.COUTMUX.C5Q !30_40 30_43 !30_44 !30_45
CLBLL_L.SLICEL_X0.COUTMUX.CY 30_40 !30_43 30_44 !30_45
CLBLL_L.SLICEL_X0.COUTMUX.XOR !30_40 !30_43 30_44 !30_45
CLBLL_L.SLICEL_X0.COUTMUX.F7 30_40 30_43 !30_44 !30_45
CLBLL_L.SLICEL_X0.COUTMUX.O5 30_40 !30_43 !30_44 30_45
CLBLL_L.SLICEL_X0.COUTMUX.O6 !30_40 !30_43 !30_44 30_45
CLBLL_L.SLICEL_X0.COUTMUX.XOR !30_40 !30_43 !30_45 30_44
CLBLL_L.SLICEL_X0.D5FF.ZINI 31_51
CLBLL_L.SLICEL_X0.D5FF.ZRST 01_55
CLBLL_L.SLICEL_X0.D5FFMUX.IN_A 30_55
CLBLL_L.SLICEL_X0.D5FFMUX.IN_B 30_54
CLBLL_L.SLICEL_X0.DFF.ZINI 31_58
CLBLL_L.SLICEL_X0.DFF.ZRST 30_50
CLBLL_L.SLICEL_X0.DFFMUX.CY !30_59 !30_61 30_60 30_62
CLBLL_L.SLICEL_X0.DFFMUX.DX !30_59 !30_60 !30_62 30_61
CLBLL_L.SLICEL_X0.DFFMUX.O5 !30_60 !30_61 30_59 30_62
CLBLL_L.SLICEL_X0.DFFMUX.O6 !30_60 !30_61 !30_62 30_59
CLBLL_L.SLICEL_X0.DFFMUX.XOR !30_59 !30_61 !30_62 30_60
CLBLL_L.SLICEL_X0.DFFMUX.CY !30_59 30_60 !30_61 30_62
CLBLL_L.SLICEL_X0.DFFMUX.DX !30_59 !30_60 30_61 !30_62
CLBLL_L.SLICEL_X0.DFFMUX.XOR !30_59 30_60 !30_61 !30_62
CLBLL_L.SLICEL_X0.DFFMUX.O5 30_59 !30_60 !30_61 30_62
CLBLL_L.SLICEL_X0.DFFMUX.O6 30_59 !30_60 !30_61 !30_62
CLBLL_L.SLICEL_X0.DLUT.INIT[00] 32_63
CLBLL_L.SLICEL_X0.DLUT.INIT[01] 33_63
CLBLL_L.SLICEL_X0.DLUT.INIT[02] 32_62
@ -331,29 +327,33 @@ CLBLL_L.SLICEL_X0.DLUT.INIT[63] 34_48
CLBLL_L.SLICEL_X0.DLUT.RAM 31_47
CLBLL_L.SLICEL_X0.DLUT.SMALL 01_59
CLBLL_L.SLICEL_X0.DLUT.SRL 30_47
CLBLL_L.SLICEL_X0.DOUTMUX.CY !30_56 !30_57 30_51 30_52
CLBLL_L.SLICEL_X0.DOUTMUX.CY 30_51 30_52 !30_56 !30_57
CLBLL_L.SLICEL_X0.DOUTMUX.D5Q !30_51 !30_52 !30_56 30_57
CLBLL_L.SLICEL_X0.DOUTMUX.O5 !30_51 !30_57 30_52 30_56
CLBLL_L.SLICEL_X0.DOUTMUX.O6 !30_51 !30_52 !30_57 30_56
CLBLL_L.SLICEL_X0.DOUTMUX.XOR !30_52 !30_56 !30_57 30_51
CLBLL_L.SLICEL_X0.DOUTMUX.XOR 30_51 !30_52 !30_56 !30_57
CLBLL_L.SLICEL_X0.DOUTMUX.O5 !30_51 30_52 30_56 !30_57
CLBLL_L.SLICEL_X0.DOUTMUX.O6 !30_51 !30_52 30_56 !30_57
CLBLL_L.SLICEL_X0.FFSYNC 00_48
CLBLL_L.SLICEL_X0.LATCH 30_32
CLBLL_L.SLICEL_X0.PRECYINIT.1 !30_13 !30_14 00_12
CLBLL_L.SLICEL_X0.PRECYINIT.1 00_12 !30_13 !30_14
CLBLL_L.SLICEL_X0.PRECYINIT.AX !00_12 !30_13 30_14
CLBLL_L.SLICEL_X0.PRECYINIT.CIN !00_12 !30_14 30_13
CLBLL_L.SLICEL_X0.PRECYINIT.CIN !00_12 30_13 !30_14
CLBLL_L.SLICEL_X0.SRUSEDMUX 01_35
CLBLL_L.SLICEL_X0.CARRY4.ACY0 30_15
CLBLL_L.SLICEL_X0.CARRY4.BCY0 01_15
CLBLL_L.SLICEL_X0.CARRY4.CCY0 30_48
CLBLL_L.SLICEL_X0.CARRY4.DCY0 30_49
CLBLL_L.SLICEL_X1.A5FF.ZINI 31_05
CLBLL_L.SLICEL_X1.A5FF.ZRST 01_03
CLBLL_L.SLICEL_X1.A5FFMUX.IN_A 31_08
CLBLL_L.SLICEL_X1.A5FFMUX.IN_B 31_11
CLBLL_L.SLICEL_X1.AFF.ZINI 31_04
CLBLL_L.SLICEL_X1.AFF.ZRST 31_15
CLBLL_L.SLICEL_X1.AFFMUX.AX !30_04 !31_00 !31_02 31_01
CLBLL_L.SLICEL_X1.AFFMUX.CY !30_04 !31_01 31_00 31_02
CLBLL_L.SLICEL_X1.AFFMUX.F7 !30_04 !31_02 31_00 31_01
CLBLL_L.SLICEL_X1.AFFMUX.O5 !31_01 !31_02 30_04 31_00
CLBLL_L.SLICEL_X1.AFFMUX.O6 !31_00 !31_01 !31_02 30_04
CLBLL_L.SLICEL_X1.AFFMUX.AX !30_04 !31_00 31_01 !31_02
CLBLL_L.SLICEL_X1.AFFMUX.CY !30_04 31_00 !31_01 31_02
CLBLL_L.SLICEL_X1.AFFMUX.XOR !30_04 !31_00 !31_01 31_02
CLBLL_L.SLICEL_X1.AFFMUX.F7 !30_04 31_00 31_01 !31_02
CLBLL_L.SLICEL_X1.AFFMUX.O5 30_04 31_00 !31_01 !31_02
CLBLL_L.SLICEL_X1.AFFMUX.O6 30_04 !31_00 !31_01 !31_02
CLBLL_L.SLICEL_X1.ALUT.INIT[00] 26_15
CLBLL_L.SLICEL_X1.ALUT.INIT[01] 27_15
CLBLL_L.SLICEL_X1.ALUT.INIT[02] 26_14
@ -418,12 +418,12 @@ CLBLL_L.SLICEL_X1.ALUT.INIT[60] 29_01
CLBLL_L.SLICEL_X1.ALUT.INIT[61] 28_01
CLBLL_L.SLICEL_X1.ALUT.INIT[62] 29_00
CLBLL_L.SLICEL_X1.ALUT.INIT[63] 28_00
CLBLL_L.SLICEL_X1.AOUTMUX.A5Q !31_07 !31_09 !31_10 30_05
CLBLL_L.SLICEL_X1.AOUTMUX.CY !30_05 !31_09 31_07 31_10
CLBLL_L.SLICEL_X1.AOUTMUX.F7 !31_07 !31_09 30_05 31_10
CLBLL_L.SLICEL_X1.AOUTMUX.A5Q 30_05 !31_07 !31_09 !31_10
CLBLL_L.SLICEL_X1.AOUTMUX.CY !30_05 31_07 !31_09 31_10
CLBLL_L.SLICEL_X1.AOUTMUX.XOR !30_05 31_07 !31_09 !31_10
CLBLL_L.SLICEL_X1.AOUTMUX.F7 30_05 !31_07 !31_09 31_10
CLBLL_L.SLICEL_X1.AOUTMUX.O5 !30_05 !31_07 31_09 31_10
CLBLL_L.SLICEL_X1.AOUTMUX.O6 !30_05 !31_07 !31_10 31_09
CLBLL_L.SLICEL_X1.AOUTMUX.XOR !30_05 !31_09 !31_10 31_07
CLBLL_L.SLICEL_X1.AOUTMUX.O6 !30_05 !31_07 31_09 !31_10
CLBLL_L.SLICEL_X1.B5FF.ZINI 31_23
CLBLL_L.SLICEL_X1.B5FF.ZRST 00_16
CLBLL_L.SLICEL_X1.B5FFMUX.IN_A 31_19
@ -431,11 +431,11 @@ CLBLL_L.SLICEL_X1.B5FFMUX.IN_B 31_18
CLBLL_L.SLICEL_X1.BFF.ZINI 31_29
CLBLL_L.SLICEL_X1.BFF.ZRST 31_30
CLBLL_L.SLICEL_X1.BFFMUX.BX !31_24 !31_25 !31_26 31_27
CLBLL_L.SLICEL_X1.BFFMUX.CY !31_24 !31_27 31_25 31_26
CLBLL_L.SLICEL_X1.BFFMUX.F8 !31_24 !31_26 31_25 31_27
CLBLL_L.SLICEL_X1.BFFMUX.O5 !31_26 !31_27 31_24 31_25
CLBLL_L.SLICEL_X1.BFFMUX.O6 !31_25 !31_26 !31_27 31_24
CLBLL_L.SLICEL_X1.BFFMUX.XOR !31_24 !31_25 !31_27 31_26
CLBLL_L.SLICEL_X1.BFFMUX.CY !31_24 31_25 31_26 !31_27
CLBLL_L.SLICEL_X1.BFFMUX.XOR !31_24 !31_25 31_26 !31_27
CLBLL_L.SLICEL_X1.BFFMUX.F8 !31_24 31_25 !31_26 31_27
CLBLL_L.SLICEL_X1.BFFMUX.O5 31_24 31_25 !31_26 !31_27
CLBLL_L.SLICEL_X1.BFFMUX.O6 31_24 !31_25 !31_26 !31_27
CLBLL_L.SLICEL_X1.BLUT.INIT[00] 26_31
CLBLL_L.SLICEL_X1.BLUT.INIT[01] 27_31
CLBLL_L.SLICEL_X1.BLUT.INIT[02] 26_30
@ -500,29 +500,25 @@ CLBLL_L.SLICEL_X1.BLUT.INIT[60] 29_17
CLBLL_L.SLICEL_X1.BLUT.INIT[61] 28_17
CLBLL_L.SLICEL_X1.BLUT.INIT[62] 29_16
CLBLL_L.SLICEL_X1.BLUT.INIT[63] 28_16
CLBLL_L.SLICEL_X1.BOUTMUX.B5Q !30_28 !31_20 !31_21 30_29
CLBLL_L.SLICEL_X1.BOUTMUX.CY !30_29 !31_20 30_28 31_21
CLBLL_L.SLICEL_X1.BOUTMUX.F8 !30_28 !31_20 30_29 31_21
CLBLL_L.SLICEL_X1.BOUTMUX.B5Q !30_28 30_29 !31_20 !31_21
CLBLL_L.SLICEL_X1.BOUTMUX.CY 30_28 !30_29 !31_20 31_21
CLBLL_L.SLICEL_X1.BOUTMUX.XOR 30_28 !30_29 !31_20 !31_21
CLBLL_L.SLICEL_X1.BOUTMUX.F8 !30_28 30_29 !31_20 31_21
CLBLL_L.SLICEL_X1.BOUTMUX.O5 !30_28 !30_29 31_20 31_21
CLBLL_L.SLICEL_X1.BOUTMUX.O6 !30_28 !30_29 !31_21 31_20
CLBLL_L.SLICEL_X1.BOUTMUX.XOR !30_29 !31_20 !31_21 30_28
CLBLL_L.SLICEL_X1.BOUTMUX.O6 !30_28 !30_29 31_20 !31_21
CLBLL_L.SLICEL_X1.C5FF.ZINI 31_42
CLBLL_L.SLICEL_X1.C5FF.ZRST 00_44
CLBLL_L.SLICEL_X1.C5FFMUX.IN_A 31_44
CLBLL_L.SLICEL_X1.C5FFMUX.IN_B 31_39
CLBLL_L.SLICEL_X1.CARRY4.ACY0 31_14
CLBLL_L.SLICEL_X1.CARRY4.BCY0 00_08
CLBLL_L.SLICEL_X1.CARRY4.CCY0 31_48
CLBLL_L.SLICEL_X1.CARRY4.DCY0 31_49
CLBLL_L.SLICEL_X1.CEUSEDMUX 00_36
CLBLL_L.SLICEL_X1.CFF.ZINI 31_34
CLBLL_L.SLICEL_X1.CFF.ZRST 30_34
CLBLL_L.SLICEL_X1.CFFMUX.CX !31_35 !31_36 !31_37 31_38
CLBLL_L.SLICEL_X1.CFFMUX.CY !31_36 !31_38 31_35 31_37
CLBLL_L.SLICEL_X1.CFFMUX.F7 !31_36 !31_37 31_35 31_38
CLBLL_L.SLICEL_X1.CFFMUX.O5 !31_37 !31_38 31_35 31_36
CLBLL_L.SLICEL_X1.CFFMUX.O6 !31_35 !31_37 !31_38 31_36
CLBLL_L.SLICEL_X1.CFFMUX.XOR !31_35 !31_36 !31_38 31_37
CLBLL_L.SLICEL_X1.CFFMUX.CY 31_35 !31_36 31_37 !31_38
CLBLL_L.SLICEL_X1.CFFMUX.XOR !31_35 !31_36 31_37 !31_38
CLBLL_L.SLICEL_X1.CFFMUX.F7 31_35 !31_36 !31_37 31_38
CLBLL_L.SLICEL_X1.CFFMUX.O5 31_35 31_36 !31_37 !31_38
CLBLL_L.SLICEL_X1.CFFMUX.O6 !31_35 31_36 !31_37 !31_38
CLBLL_L.SLICEL_X1.CLKINV 00_52
CLBLL_L.SLICEL_X1.CLUT.INIT[00] 26_47
CLBLL_L.SLICEL_X1.CLUT.INIT[01] 27_47
@ -588,23 +584,23 @@ CLBLL_L.SLICEL_X1.CLUT.INIT[60] 29_33
CLBLL_L.SLICEL_X1.CLUT.INIT[61] 28_33
CLBLL_L.SLICEL_X1.CLUT.INIT[62] 29_32
CLBLL_L.SLICEL_X1.CLUT.INIT[63] 28_32
CLBLL_L.SLICEL_X1.COUTMUX.C5Q !30_42 !31_40 !31_43 30_41
CLBLL_L.SLICEL_X1.COUTMUX.CY !30_41 !31_43 30_42 31_40
CLBLL_L.SLICEL_X1.COUTMUX.F7 !30_42 !31_43 30_41 31_40
CLBLL_L.SLICEL_X1.COUTMUX.C5Q 30_41 !30_42 !31_40 !31_43
CLBLL_L.SLICEL_X1.COUTMUX.CY !30_41 30_42 31_40 !31_43
CLBLL_L.SLICEL_X1.COUTMUX.XOR !30_41 30_42 !31_40 !31_43
CLBLL_L.SLICEL_X1.COUTMUX.F7 30_41 !30_42 31_40 !31_43
CLBLL_L.SLICEL_X1.COUTMUX.O5 !30_41 !30_42 31_40 31_43
CLBLL_L.SLICEL_X1.COUTMUX.O6 !30_41 !30_42 !31_40 31_43
CLBLL_L.SLICEL_X1.COUTMUX.XOR !30_41 !31_40 !31_43 30_42
CLBLL_L.SLICEL_X1.D5FF.ZINI 31_52
CLBLL_L.SLICEL_X1.D5FF.ZRST 00_56
CLBLL_L.SLICEL_X1.D5FFMUX.IN_A 31_55
CLBLL_L.SLICEL_X1.D5FFMUX.IN_B 31_54
CLBLL_L.SLICEL_X1.DFF.ZINI 31_59
CLBLL_L.SLICEL_X1.DFF.ZRST 31_50
CLBLL_L.SLICEL_X1.DFFMUX.CY !31_60 !31_61 30_58 31_62
CLBLL_L.SLICEL_X1.DFFMUX.DX !30_58 !31_60 !31_62 31_61
CLBLL_L.SLICEL_X1.DFFMUX.O5 !31_61 !31_62 30_58 31_60
CLBLL_L.SLICEL_X1.DFFMUX.O6 !30_58 !31_61 !31_62 31_60
CLBLL_L.SLICEL_X1.DFFMUX.CY 30_58 !31_60 !31_61 31_62
CLBLL_L.SLICEL_X1.DFFMUX.DX !30_58 !31_60 31_61 !31_62
CLBLL_L.SLICEL_X1.DFFMUX.XOR !30_58 !31_60 !31_61 31_62
CLBLL_L.SLICEL_X1.DFFMUX.O5 30_58 31_60 !31_61 !31_62
CLBLL_L.SLICEL_X1.DFFMUX.O6 !30_58 31_60 !31_61 !31_62
CLBLL_L.SLICEL_X1.DLUT.INIT[00] 26_63
CLBLL_L.SLICEL_X1.DLUT.INIT[01] 27_63
CLBLL_L.SLICEL_X1.DLUT.INIT[02] 26_62
@ -669,14 +665,18 @@ CLBLL_L.SLICEL_X1.DLUT.INIT[60] 29_49
CLBLL_L.SLICEL_X1.DLUT.INIT[61] 28_49
CLBLL_L.SLICEL_X1.DLUT.INIT[62] 29_48
CLBLL_L.SLICEL_X1.DLUT.INIT[63] 28_48
CLBLL_L.SLICEL_X1.DOUTMUX.CY !31_53 !31_56 30_53 31_57
CLBLL_L.SLICEL_X1.DOUTMUX.D5Q !30_53 !31_56 !31_57 31_53
CLBLL_L.SLICEL_X1.DOUTMUX.CY 30_53 !31_53 !31_56 31_57
CLBLL_L.SLICEL_X1.DOUTMUX.D5Q !30_53 31_53 !31_56 !31_57
CLBLL_L.SLICEL_X1.DOUTMUX.XOR 30_53 !31_53 !31_56 !31_57
CLBLL_L.SLICEL_X1.DOUTMUX.O5 !30_53 !31_53 31_56 31_57
CLBLL_L.SLICEL_X1.DOUTMUX.O6 !30_53 !31_53 !31_57 31_56
CLBLL_L.SLICEL_X1.DOUTMUX.XOR !31_53 !31_56 !31_57 30_53
CLBLL_L.SLICEL_X1.DOUTMUX.O6 !30_53 !31_53 31_56 !31_57
CLBLL_L.SLICEL_X1.FFSYNC 01_31
CLBLL_L.SLICEL_X1.LATCH 31_32
CLBLL_L.SLICEL_X1.PRECYINIT.1 !31_12 !31_13 01_11
CLBLL_L.SLICEL_X1.PRECYINIT.1 01_11 !31_12 !31_13
CLBLL_L.SLICEL_X1.PRECYINIT.AX !01_11 !31_12 31_13
CLBLL_L.SLICEL_X1.PRECYINIT.CIN !01_11 !31_13 31_12
CLBLL_L.SLICEL_X1.PRECYINIT.CIN !01_11 31_12 !31_13
CLBLL_L.SLICEL_X1.SRUSEDMUX 00_32
CLBLL_L.SLICEL_X1.CARRY4.ACY0 31_14
CLBLL_L.SLICEL_X1.CARRY4.BCY0 00_08
CLBLL_L.SLICEL_X1.CARRY4.CCY0 31_48
CLBLL_L.SLICEL_X1.CARRY4.DCY0 31_49

174
artix7/segbits_clbll_r.db
View File

@ -4,12 +4,12 @@ CLBLL_R.SLICEL_X0.A5FFMUX.IN_A 30_09
CLBLL_R.SLICEL_X0.A5FFMUX.IN_B 30_10
CLBLL_R.SLICEL_X0.AFF.ZINI 31_03
CLBLL_R.SLICEL_X0.AFF.ZRST 30_12
CLBLL_R.SLICEL_X0.AFFMUX.AX !30_00 !30_02 !30_03 30_01
CLBLL_R.SLICEL_X0.AFFMUX.CY !30_01 !30_03 30_00 30_02
CLBLL_R.SLICEL_X0.AFFMUX.F7 !30_02 !30_03 30_00 30_01
CLBLL_R.SLICEL_X0.AFFMUX.O5 !30_01 !30_02 30_00 30_03
CLBLL_R.SLICEL_X0.AFFMUX.AX !30_00 30_01 !30_02 !30_03
CLBLL_R.SLICEL_X0.AFFMUX.CY 30_00 !30_01 30_02 !30_03
CLBLL_R.SLICEL_X0.AFFMUX.XOR !30_00 !30_01 30_02 !30_03
CLBLL_R.SLICEL_X0.AFFMUX.F7 30_00 30_01 !30_02 !30_03
CLBLL_R.SLICEL_X0.AFFMUX.O5 30_00 !30_01 !30_02 30_03
CLBLL_R.SLICEL_X0.AFFMUX.O6 !30_00 !30_01 !30_02 30_03
CLBLL_R.SLICEL_X0.AFFMUX.XOR !30_00 !30_01 !30_03 30_02
CLBLL_R.SLICEL_X0.ALUT.INIT[00] 32_15
CLBLL_R.SLICEL_X0.ALUT.INIT[01] 33_15
CLBLL_R.SLICEL_X0.ALUT.INIT[02] 32_14
@ -75,24 +75,24 @@ CLBLL_R.SLICEL_X0.ALUT.INIT[61] 34_01
CLBLL_R.SLICEL_X0.ALUT.INIT[62] 35_00
CLBLL_R.SLICEL_X0.ALUT.INIT[63] 34_00
CLBLL_R.SLICEL_X0.ALUT.RAM 31_16
CLBLL_R.SLICEL_X0.AOUTMUX.A5Q !30_06 !30_08 !30_11 30_07
CLBLL_R.SLICEL_X0.AOUTMUX.CY !30_07 !30_11 30_06 30_08
CLBLL_R.SLICEL_X0.AOUTMUX.F7 !30_08 !30_11 30_06 30_07
CLBLL_R.SLICEL_X0.AOUTMUX.O5 !30_07 !30_08 30_06 30_11
CLBLL_R.SLICEL_X0.AOUTMUX.A5Q !30_06 30_07 !30_08 !30_11
CLBLL_R.SLICEL_X0.AOUTMUX.CY 30_06 !30_07 30_08 !30_11
CLBLL_R.SLICEL_X0.AOUTMUX.XOR !30_06 !30_07 30_08 !30_11
CLBLL_R.SLICEL_X0.AOUTMUX.F7 30_06 30_07 !30_08 !30_11
CLBLL_R.SLICEL_X0.AOUTMUX.O5 30_06 !30_07 !30_08 30_11
CLBLL_R.SLICEL_X0.AOUTMUX.O6 !30_06 !30_07 !30_08 30_11
CLBLL_R.SLICEL_X0.AOUTMUX.XOR !30_06 !30_07 !30_11 30_08
CLBLL_R.SLICEL_X0.B5FF.ZINI 31_22
CLBLL_R.SLICEL_X0.B5FF.ZRST 01_19
CLBLL_R.SLICEL_X0.B5FFMUX.IN_A 30_19
CLBLL_R.SLICEL_X0.B5FFMUX.IN_B 30_18
CLBLL_R.SLICEL_X0.BFF.ZINI 31_28
CLBLL_R.SLICEL_X0.BFF.ZRST 30_30
CLBLL_R.SLICEL_X0.BFFMUX.BX !30_24 !30_25 !30_27 30_26
CLBLL_R.SLICEL_X0.BFFMUX.CY !30_24 !30_26 30_25 30_27
CLBLL_R.SLICEL_X0.BFFMUX.BX !30_24 !30_25 30_26 !30_27
CLBLL_R.SLICEL_X0.BFFMUX.CY !30_24 30_25 !30_26 30_27
CLBLL_R.SLICEL_X0.BFFMUX.XOR !30_24 30_25 !30_26 !30_27
CLBLL_R.SLICEL_X0.BFFMUX.F8 !30_24 !30_25 30_26 30_27
CLBLL_R.SLICEL_X0.BFFMUX.O5 !30_25 !30_26 30_24 30_27
CLBLL_R.SLICEL_X0.BFFMUX.O6 !30_25 !30_26 !30_27 30_24
CLBLL_R.SLICEL_X0.BFFMUX.XOR !30_24 !30_26 !30_27 30_25
CLBLL_R.SLICEL_X0.BFFMUX.O5 30_24 !30_25 !30_26 30_27
CLBLL_R.SLICEL_X0.BFFMUX.O6 30_24 !30_25 !30_26 !30_27
CLBLL_R.SLICEL_X0.BLUT.INIT[00] 32_31
CLBLL_R.SLICEL_X0.BLUT.INIT[01] 33_31
CLBLL_R.SLICEL_X0.BLUT.INIT[02] 32_30
@ -159,28 +159,24 @@ CLBLL_R.SLICEL_X0.BLUT.INIT[62] 35_16
CLBLL_R.SLICEL_X0.BLUT.INIT[63] 34_16
CLBLL_R.SLICEL_X0.BLUT.RAM 31_17
CLBLL_R.SLICEL_X0.BOUTMUX.B5Q !30_20 !30_21 !30_22 30_23
CLBLL_R.SLICEL_X0.BOUTMUX.CY !30_20 !30_23 30_21 30_22
CLBLL_R.SLICEL_X0.BOUTMUX.CY !30_20 30_21 30_22 !30_23
CLBLL_R.SLICEL_X0.BOUTMUX.XOR !30_20 30_21 !30_22 !30_23
CLBLL_R.SLICEL_X0.BOUTMUX.F8 !30_20 !30_21 30_22 30_23
CLBLL_R.SLICEL_X0.BOUTMUX.O5 !30_21 !30_23 30_20 30_22
CLBLL_R.SLICEL_X0.BOUTMUX.O6 !30_21 !30_22 !30_23 30_20
CLBLL_R.SLICEL_X0.BOUTMUX.XOR !30_20 !30_22 !30_23 30_21
CLBLL_R.SLICEL_X0.BOUTMUX.O5 30_20 !30_21 30_22 !30_23
CLBLL_R.SLICEL_X0.BOUTMUX.O6 30_20 !30_21 !30_22 !30_23
CLBLL_R.SLICEL_X0.C5FF.ZINI 31_41
CLBLL_R.SLICEL_X0.C5FF.ZRST 01_47
CLBLL_R.SLICEL_X0.C5FFMUX.IN_A 31_45
CLBLL_R.SLICEL_X0.C5FFMUX.IN_B 30_39
CLBLL_R.SLICEL_X0.CARRY4.ACY0 30_15
CLBLL_R.SLICEL_X0.CARRY4.BCY0 01_15
CLBLL_R.SLICEL_X0.CARRY4.CCY0 30_48
CLBLL_R.SLICEL_X0.CARRY4.DCY0 30_49
CLBLL_R.SLICEL_X0.CEUSEDMUX 01_39
CLBLL_R.SLICEL_X0.CFF.ZINI 31_33
CLBLL_R.SLICEL_X0.CFF.ZRST 30_33
CLBLL_R.SLICEL_X0.CFFMUX.CX !30_35 !30_37 !30_38 30_36
CLBLL_R.SLICEL_X0.CFFMUX.CY !30_36 !30_38 30_35 30_37
CLBLL_R.SLICEL_X0.CFFMUX.F7 !30_37 !30_38 30_35 30_36
CLBLL_R.SLICEL_X0.CFFMUX.O5 !30_36 !30_37 30_35 30_38
CLBLL_R.SLICEL_X0.CFFMUX.CX !30_35 30_36 !30_37 !30_38
CLBLL_R.SLICEL_X0.CFFMUX.CY 30_35 !30_36 30_37 !30_38
CLBLL_R.SLICEL_X0.CFFMUX.XOR !30_35 !30_36 30_37 !30_38
CLBLL_R.SLICEL_X0.CFFMUX.F7 30_35 30_36 !30_37 !30_38
CLBLL_R.SLICEL_X0.CFFMUX.O5 30_35 !30_36 !30_37 30_38
CLBLL_R.SLICEL_X0.CFFMUX.O6 !30_35 !30_36 !30_37 30_38
CLBLL_R.SLICEL_X0.CFFMUX.XOR !30_35 !30_36 !30_38 30_37
CLBLL_R.SLICEL_X0.CLKINV 01_51
CLBLL_R.SLICEL_X0.CLUT.INIT[00] 32_47
CLBLL_R.SLICEL_X0.CLUT.INIT[01] 33_47
@ -247,23 +243,23 @@ CLBLL_R.SLICEL_X0.CLUT.INIT[61] 34_33
CLBLL_R.SLICEL_X0.CLUT.INIT[62] 35_32
CLBLL_R.SLICEL_X0.CLUT.INIT[63] 34_32
CLBLL_R.SLICEL_X0.CLUT.RAM 31_46
CLBLL_R.SLICEL_X0.COUTMUX.C5Q !30_40 !30_44 !30_45 30_43
CLBLL_R.SLICEL_X0.COUTMUX.CY !30_43 !30_45 30_40 30_44
CLBLL_R.SLICEL_X0.COUTMUX.F7 !30_44 !30_45 30_40 30_43
CLBLL_R.SLICEL_X0.COUTMUX.O5 !30_43 !30_44 30_40 30_45
CLBLL_R.SLICEL_X0.COUTMUX.C5Q !30_40 30_43 !30_44 !30_45
CLBLL_R.SLICEL_X0.COUTMUX.CY 30_40 !30_43 30_44 !30_45
CLBLL_R.SLICEL_X0.COUTMUX.XOR !30_40 !30_43 30_44 !30_45
CLBLL_R.SLICEL_X0.COUTMUX.F7 30_40 30_43 !30_44 !30_45
CLBLL_R.SLICEL_X0.COUTMUX.O5 30_40 !30_43 !30_44 30_45
CLBLL_R.SLICEL_X0.COUTMUX.O6 !30_40 !30_43 !30_44 30_45
CLBLL_R.SLICEL_X0.COUTMUX.XOR !30_40 !30_43 !30_45 30_44
CLBLL_R.SLICEL_X0.D5FF.ZINI 31_51
CLBLL_R.SLICEL_X0.D5FF.ZRST 01_55
CLBLL_R.SLICEL_X0.D5FFMUX.IN_A 30_55
CLBLL_R.SLICEL_X0.D5FFMUX.IN_B 30_54
CLBLL_R.SLICEL_X0.DFF.ZINI 31_58
CLBLL_R.SLICEL_X0.DFF.ZRST 30_50
CLBLL_R.SLICEL_X0.DFFMUX.CY !30_59 !30_61 30_60 30_62
CLBLL_R.SLICEL_X0.DFFMUX.DX !30_59 !30_60 !30_62 30_61
CLBLL_R.SLICEL_X0.DFFMUX.O5 !30_60 !30_61 30_59 30_62
CLBLL_R.SLICEL_X0.DFFMUX.O6 !30_60 !30_61 !30_62 30_59
CLBLL_R.SLICEL_X0.DFFMUX.XOR !30_59 !30_61 !30_62 30_60
CLBLL_R.SLICEL_X0.DFFMUX.CY !30_59 30_60 !30_61 30_62
CLBLL_R.SLICEL_X0.DFFMUX.DX !30_59 !30_60 30_61 !30_62
CLBLL_R.SLICEL_X0.DFFMUX.XOR !30_59 30_60 !30_61 !30_62
CLBLL_R.SLICEL_X0.DFFMUX.O5 30_59 !30_60 !30_61 30_62
CLBLL_R.SLICEL_X0.DFFMUX.O6 30_59 !30_60 !30_61 !30_62
CLBLL_R.SLICEL_X0.DLUT.INIT[00] 32_63
CLBLL_R.SLICEL_X0.DLUT.INIT[01] 33_63
CLBLL_R.SLICEL_X0.DLUT.INIT[02] 32_62
@ -331,29 +327,33 @@ CLBLL_R.SLICEL_X0.DLUT.INIT[63] 34_48
CLBLL_R.SLICEL_X0.DLUT.RAM 31_47
CLBLL_R.SLICEL_X0.DLUT.SMALL 01_59
CLBLL_R.SLICEL_X0.DLUT.SRL 30_47
CLBLL_R.SLICEL_X0.DOUTMUX.CY !30_56 !30_57 30_51 30_52
CLBLL_R.SLICEL_X0.DOUTMUX.CY 30_51 30_52 !30_56 !30_57
CLBLL_R.SLICEL_X0.DOUTMUX.D5Q !30_51 !30_52 !30_56 30_57
CLBLL_R.SLICEL_X0.DOUTMUX.O5 !30_51 !30_57 30_52 30_56
CLBLL_R.SLICEL_X0.DOUTMUX.O6 !30_51 !30_52 !30_57 30_56
CLBLL_R.SLICEL_X0.DOUTMUX.XOR !30_52 !30_56 !30_57 30_51
CLBLL_R.SLICEL_X0.DOUTMUX.XOR 30_51 !30_52 !30_56 !30_57
CLBLL_R.SLICEL_X0.DOUTMUX.O5 !30_51 30_52 30_56 !30_57
CLBLL_R.SLICEL_X0.DOUTMUX.O6 !30_51 !30_52 30_56 !30_57
CLBLL_R.SLICEL_X0.FFSYNC 00_48
CLBLL_R.SLICEL_X0.LATCH 30_32
CLBLL_R.SLICEL_X0.PRECYINIT.1 !30_13 !30_14 00_12
CLBLL_R.SLICEL_X0.PRECYINIT.1 00_12 !30_13 !30_14
CLBLL_R.SLICEL_X0.PRECYINIT.AX !00_12 !30_13 30_14
CLBLL_R.SLICEL_X0.PRECYINIT.CIN !00_12 !30_14 30_13
CLBLL_R.SLICEL_X0.PRECYINIT.CIN !00_12 30_13 !30_14
CLBLL_R.SLICEL_X0.SRUSEDMUX 01_35
CLBLL_R.SLICEL_X0.CARRY4.ACY0 30_15
CLBLL_R.SLICEL_X0.CARRY4.BCY0 01_15
CLBLL_R.SLICEL_X0.CARRY4.CCY0 30_48
CLBLL_R.SLICEL_X0.CARRY4.DCY0 30_49
CLBLL_R.SLICEL_X1.A5FF.ZINI 31_05
CLBLL_R.SLICEL_X1.A5FF.ZRST 01_03
CLBLL_R.SLICEL_X1.A5FFMUX.IN_A 31_08
CLBLL_R.SLICEL_X1.A5FFMUX.IN_B 31_11
CLBLL_R.SLICEL_X1.AFF.ZINI 31_04
CLBLL_R.SLICEL_X1.AFF.ZRST 31_15
CLBLL_R.SLICEL_X1.AFFMUX.AX !30_04 !31_00 !31_02 31_01
CLBLL_R.SLICEL_X1.AFFMUX.CY !30_04 !31_01 31_00 31_02
CLBLL_R.SLICEL_X1.AFFMUX.F7 !30_04 !31_02 31_00 31_01
CLBLL_R.SLICEL_X1.AFFMUX.O5 !31_01 !31_02 30_04 31_00
CLBLL_R.SLICEL_X1.AFFMUX.O6 !31_00 !31_01 !31_02 30_04
CLBLL_R.SLICEL_X1.AFFMUX.AX !30_04 !31_00 31_01 !31_02
CLBLL_R.SLICEL_X1.AFFMUX.CY !30_04 31_00 !31_01 31_02
CLBLL_R.SLICEL_X1.AFFMUX.XOR !30_04 !31_00 !31_01 31_02
CLBLL_R.SLICEL_X1.AFFMUX.F7 !30_04 31_00 31_01 !31_02
CLBLL_R.SLICEL_X1.AFFMUX.O5 30_04 31_00 !31_01 !31_02
CLBLL_R.SLICEL_X1.AFFMUX.O6 30_04 !31_00 !31_01 !31_02
CLBLL_R.SLICEL_X1.ALUT.INIT[00] 26_15
CLBLL_R.SLICEL_X1.ALUT.INIT[01] 27_15
CLBLL_R.SLICEL_X1.ALUT.INIT[02] 26_14
@ -418,12 +418,12 @@ CLBLL_R.SLICEL_X1.ALUT.INIT[60] 29_01
CLBLL_R.SLICEL_X1.ALUT.INIT[61] 28_01
CLBLL_R.SLICEL_X1.ALUT.INIT[62] 29_00
CLBLL_R.SLICEL_X1.ALUT.INIT[63] 28_00
CLBLL_R.SLICEL_X1.AOUTMUX.A5Q !31_07 !31_09 !31_10 30_05
CLBLL_R.SLICEL_X1.AOUTMUX.CY !30_05 !31_09 31_07 31_10
CLBLL_R.SLICEL_X1.AOUTMUX.F7 !31_07 !31_09 30_05 31_10
CLBLL_R.SLICEL_X1.AOUTMUX.A5Q 30_05 !31_07 !31_09 !31_10
CLBLL_R.SLICEL_X1.AOUTMUX.CY !30_05 31_07 !31_09 31_10
CLBLL_R.SLICEL_X1.AOUTMUX.XOR !30_05 31_07 !31_09 !31_10
CLBLL_R.SLICEL_X1.AOUTMUX.F7 30_05 !31_07 !31_09 31_10
CLBLL_R.SLICEL_X1.AOUTMUX.O5 !30_05 !31_07 31_09 31_10
CLBLL_R.SLICEL_X1.AOUTMUX.O6 !30_05 !31_07 !31_10 31_09
CLBLL_R.SLICEL_X1.AOUTMUX.XOR !30_05 !31_09 !31_10 31_07
CLBLL_R.SLICEL_X1.AOUTMUX.O6 !30_05 !31_07 31_09 !31_10
CLBLL_R.SLICEL_X1.B5FF.ZINI 31_23
CLBLL_R.SLICEL_X1.B5FF.ZRST 00_16
CLBLL_R.SLICEL_X1.B5FFMUX.IN_A 31_19
@ -431,11 +431,11 @@ CLBLL_R.SLICEL_X1.B5FFMUX.IN_B 31_18
CLBLL_R.SLICEL_X1.BFF.ZINI 31_29
CLBLL_R.SLICEL_X1.BFF.ZRST 31_30
CLBLL_R.SLICEL_X1.BFFMUX.BX !31_24 !31_25 !31_26 31_27
CLBLL_R.SLICEL_X1.BFFMUX.CY !31_24 !31_27 31_25 31_26
CLBLL_R.SLICEL_X1.BFFMUX.F8 !31_24 !31_26 31_25 31_27
CLBLL_R.SLICEL_X1.BFFMUX.O5 !31_26 !31_27 31_24 31_25
CLBLL_R.SLICEL_X1.BFFMUX.O6 !31_25 !31_26 !31_27 31_24
CLBLL_R.SLICEL_X1.BFFMUX.XOR !31_24 !31_25 !31_27 31_26
CLBLL_R.SLICEL_X1.BFFMUX.CY !31_24 31_25 31_26 !31_27
CLBLL_R.SLICEL_X1.BFFMUX.XOR !31_24 !31_25 31_26 !31_27
CLBLL_R.SLICEL_X1.BFFMUX.F8 !31_24 31_25 !31_26 31_27
CLBLL_R.SLICEL_X1.BFFMUX.O5 31_24 31_25 !31_26 !31_27
CLBLL_R.SLICEL_X1.BFFMUX.O6 31_24 !31_25 !31_26 !31_27
CLBLL_R.SLICEL_X1.BLUT.INIT[00] 26_31
CLBLL_R.SLICEL_X1.BLUT.INIT[01] 27_31
CLBLL_R.SLICEL_X1.BLUT.INIT[02] 26_30
@ -500,29 +500,25 @@ CLBLL_R.SLICEL_X1.BLUT.INIT[60] 29_17
CLBLL_R.SLICEL_X1.BLUT.INIT[61] 28_17
CLBLL_R.SLICEL_X1.BLUT.INIT[62] 29_16
CLBLL_R.SLICEL_X1.BLUT.INIT[63] 28_16
CLBLL_R.SLICEL_X1.BOUTMUX.B5Q !30_28 !31_20 !31_21 30_29
CLBLL_R.SLICEL_X1.BOUTMUX.CY !30_29 !31_20 30_28 31_21
CLBLL_R.SLICEL_X1.BOUTMUX.F8 !30_28 !31_20 30_29 31_21
CLBLL_R.SLICEL_X1.BOUTMUX.B5Q !30_28 30_29 !31_20 !31_21
CLBLL_R.SLICEL_X1.BOUTMUX.CY 30_28 !30_29 !31_20 31_21
CLBLL_R.SLICEL_X1.BOUTMUX.XOR 30_28 !30_29 !31_20 !31_21
CLBLL_R.SLICEL_X1.BOUTMUX.F8 !30_28 30_29 !31_20 31_21
CLBLL_R.SLICEL_X1.BOUTMUX.O5 !30_28 !30_29 31_20 31_21
CLBLL_R.SLICEL_X1.BOUTMUX.O6 !30_28 !30_29 !31_21 31_20
CLBLL_R.SLICEL_X1.BOUTMUX.XOR !30_29 !31_20 !31_21 30_28
CLBLL_R.SLICEL_X1.BOUTMUX.O6 !30_28 !30_29 31_20 !31_21
CLBLL_R.SLICEL_X1.C5FF.ZINI 31_42
CLBLL_R.SLICEL_X1.C5FF.ZRST 00_44
CLBLL_R.SLICEL_X1.C5FFMUX.IN_A 31_44
CLBLL_R.SLICEL_X1.C5FFMUX.IN_B 31_39
CLBLL_R.SLICEL_X1.CARRY4.ACY0 31_14
CLBLL_R.SLICEL_X1.CARRY4.BCY0 00_08
CLBLL_R.SLICEL_X1.CARRY4.CCY0 31_48
CLBLL_R.SLICEL_X1.CARRY4.DCY0 31_49
CLBLL_R.SLICEL_X1.CEUSEDMUX 00_36
CLBLL_R.SLICEL_X1.CFF.ZINI 31_34
CLBLL_R.SLICEL_X1.CFF.ZRST 30_34
CLBLL_R.SLICEL_X1.CFFMUX.CX !31_35 !31_36 !31_37 31_38
CLBLL_R.SLICEL_X1.CFFMUX.CY !31_36 !31_38 31_35 31_37
CLBLL_R.SLICEL_X1.CFFMUX.F7 !31_36 !31_37 31_35 31_38
CLBLL_R.SLICEL_X1.CFFMUX.O5 !31_37 !31_38 31_35 31_36
CLBLL_R.SLICEL_X1.CFFMUX.O6 !31_35 !31_37 !31_38 31_36
CLBLL_R.SLICEL_X1.CFFMUX.XOR !31_35 !31_36 !31_38 31_37
CLBLL_R.SLICEL_X1.CFFMUX.CY 31_35 !31_36 31_37 !31_38
CLBLL_R.SLICEL_X1.CFFMUX.XOR !31_35 !31_36 31_37 !31_38
CLBLL_R.SLICEL_X1.CFFMUX.F7 31_35 !31_36 !31_37 31_38
CLBLL_R.SLICEL_X1.CFFMUX.O5 31_35 31_36 !31_37 !31_38
CLBLL_R.SLICEL_X1.CFFMUX.O6 !31_35 31_36 !31_37 !31_38
CLBLL_R.SLICEL_X1.CLKINV 00_52
CLBLL_R.SLICEL_X1.CLUT.INIT[00] 26_47
CLBLL_R.SLICEL_X1.CLUT.INIT[01] 27_47
@ -588,23 +584,23 @@ CLBLL_R.SLICEL_X1.CLUT.INIT[60] 29_33
CLBLL_R.SLICEL_X1.CLUT.INIT[61] 28_33
CLBLL_R.SLICEL_X1.CLUT.INIT[62] 29_32
CLBLL_R.SLICEL_X1.CLUT.INIT[63] 28_32
CLBLL_R.SLICEL_X1.COUTMUX.C5Q !30_42 !31_40 !31_43 30_41
CLBLL_R.SLICEL_X1.COUTMUX.CY !30_41 !31_43 30_42 31_40
CLBLL_R.SLICEL_X1.COUTMUX.F7 !30_42 !31_43 30_41 31_40
CLBLL_R.SLICEL_X1.COUTMUX.C5Q 30_41 !30_42 !31_40 !31_43
CLBLL_R.SLICEL_X1.COUTMUX.CY !30_41 30_42 31_40 !31_43
CLBLL_R.SLICEL_X1.COUTMUX.XOR !30_41 30_42 !31_40 !31_43
CLBLL_R.SLICEL_X1.COUTMUX.F7 30_41 !30_42 31_40 !31_43
CLBLL_R.SLICEL_X1.COUTMUX.O5 !30_41 !30_42 31_40 31_43
CLBLL_R.SLICEL_X1.COUTMUX.O6 !30_41 !30_42 !31_40 31_43
CLBLL_R.SLICEL_X1.COUTMUX.XOR !30_41 !31_40 !31_43 30_42
CLBLL_R.SLICEL_X1.D5FF.ZINI 31_52
CLBLL_R.SLICEL_X1.D5FF.ZRST 00_56
CLBLL_R.SLICEL_X1.D5FFMUX.IN_A 31_55
CLBLL_R.SLICEL_X1.D5FFMUX.IN_B 31_54
CLBLL_R.SLICEL_X1.DFF.ZINI 31_59
CLBLL_R.SLICEL_X1.DFF.ZRST 31_50
CLBLL_R.SLICEL_X1.DFFMUX.CY !31_60 !31_61 30_58 31_62
CLBLL_R.SLICEL_X1.DFFMUX.DX !30_58 !31_60 !31_62 31_61
CLBLL_R.SLICEL_X1.DFFMUX.O5 !31_61 !31_62 30_58 31_60
CLBLL_R.SLICEL_X1.DFFMUX.O6 !30_58 !31_61 !31_62 31_60
CLBLL_R.SLICEL_X1.DFFMUX.CY 30_58 !31_60 !31_61 31_62
CLBLL_R.SLICEL_X1.DFFMUX.DX !30_58 !31_60 31_61 !31_62
CLBLL_R.SLICEL_X1.DFFMUX.XOR !30_58 !31_60 !31_61 31_62
CLBLL_R.SLICEL_X1.DFFMUX.O5 30_58 31_60 !31_61 !31_62
CLBLL_R.SLICEL_X1.DFFMUX.O6 !30_58 31_60 !31_61 !31_62
CLBLL_R.SLICEL_X1.DLUT.INIT[00] 26_63
CLBLL_R.SLICEL_X1.DLUT.INIT[01] 27_63
CLBLL_R.SLICEL_X1.DLUT.INIT[02] 26_62
@ -669,14 +665,18 @@ CLBLL_R.SLICEL_X1.DLUT.INIT[60] 29_49
CLBLL_R.SLICEL_X1.DLUT.INIT[61] 28_49
CLBLL_R.SLICEL_X1.DLUT.INIT[62] 29_48
CLBLL_R.SLICEL_X1.DLUT.INIT[63] 28_48
CLBLL_R.SLICEL_X1.DOUTMUX.CY !31_53 !31_56 30_53 31_57
CLBLL_R.SLICEL_X1.DOUTMUX.D5Q !30_53 !31_56 !31_57 31_53
CLBLL_R.SLICEL_X1.DOUTMUX.CY 30_53 !31_53 !31_56 31_57
CLBLL_R.SLICEL_X1.DOUTMUX.D5Q !30_53 31_53 !31_56 !31_57
CLBLL_R.SLICEL_X1.DOUTMUX.XOR 30_53 !31_53 !31_56 !31_57
CLBLL_R.SLICEL_X1.DOUTMUX.O5 !30_53 !31_53 31_56 31_57
CLBLL_R.SLICEL_X1.DOUTMUX.O6 !30_53 !31_53 !31_57 31_56
CLBLL_R.SLICEL_X1.DOUTMUX.XOR !31_53 !31_56 !31_57 30_53
CLBLL_R.SLICEL_X1.DOUTMUX.O6 !30_53 !31_53 31_56 !31_57
CLBLL_R.SLICEL_X1.FFSYNC 01_31
CLBLL_R.SLICEL_X1.LATCH 31_32
CLBLL_R.SLICEL_X1.PRECYINIT.1 !31_12 !31_13 01_11
CLBLL_R.SLICEL_X1.PRECYINIT.1 01_11 !31_12 !31_13
CLBLL_R.SLICEL_X1.PRECYINIT.AX !01_11 !31_12 31_13
CLBLL_R.SLICEL_X1.PRECYINIT.CIN !01_11 !31_13 31_12
CLBLL_R.SLICEL_X1.PRECYINIT.CIN !01_11 31_12 !31_13
CLBLL_R.SLICEL_X1.SRUSEDMUX 00_32
CLBLL_R.SLICEL_X1.CARRY4.ACY0 31_14
CLBLL_R.SLICEL_X1.CARRY4.BCY0 00_08
CLBLL_R.SLICEL_X1.CARRY4.CCY0 31_48
CLBLL_R.SLICEL_X1.CARRY4.DCY0 31_49

174
artix7/segbits_clblm_l.db
View File

@ -4,12 +4,12 @@ CLBLM_L.SLICEL_X1.A5FFMUX.IN_A 31_08
CLBLM_L.SLICEL_X1.A5FFMUX.IN_B 31_11
CLBLM_L.SLICEL_X1.AFF.ZINI 31_04
CLBLM_L.SLICEL_X1.AFF.ZRST 31_15
CLBLM_L.SLICEL_X1.AFFMUX.AX !30_04 !31_00 !31_02 31_01
CLBLM_L.SLICEL_X1.AFFMUX.CY !30_04 !31_01 31_00 31_02
CLBLM_L.SLICEL_X1.AFFMUX.F7 !30_04 !31_02 31_00 31_01
CLBLM_L.SLICEL_X1.AFFMUX.O5 !31_01 !31_02 30_04 31_00
CLBLM_L.SLICEL_X1.AFFMUX.O6 !31_00 !31_01 !31_02 30_04
CLBLM_L.SLICEL_X1.AFFMUX.AX !30_04 !31_00 31_01 !31_02
CLBLM_L.SLICEL_X1.AFFMUX.CY !30_04 31_00 !31_01 31_02
CLBLM_L.SLICEL_X1.AFFMUX.XOR !30_04 !31_00 !31_01 31_02
CLBLM_L.SLICEL_X1.AFFMUX.F7 !30_04 31_00 31_01 !31_02
CLBLM_L.SLICEL_X1.AFFMUX.O5 30_04 31_00 !31_01 !31_02
CLBLM_L.SLICEL_X1.AFFMUX.O6 30_04 !31_00 !31_01 !31_02
CLBLM_L.SLICEL_X1.ALUT.INIT[00] 26_15
CLBLM_L.SLICEL_X1.ALUT.INIT[01] 27_15
CLBLM_L.SLICEL_X1.ALUT.INIT[02] 26_14
@ -74,12 +74,12 @@ CLBLM_L.SLICEL_X1.ALUT.INIT[60] 29_01
CLBLM_L.SLICEL_X1.ALUT.INIT[61] 28_01
CLBLM_L.SLICEL_X1.ALUT.INIT[62] 29_00
CLBLM_L.SLICEL_X1.ALUT.INIT[63] 28_00
CLBLM_L.SLICEL_X1.AOUTMUX.A5Q !31_07 !31_09 !31_10 30_05
CLBLM_L.SLICEL_X1.AOUTMUX.CY !30_05 !31_09 31_07 31_10
CLBLM_L.SLICEL_X1.AOUTMUX.F7 !31_07 !31_09 30_05 31_10
CLBLM_L.SLICEL_X1.AOUTMUX.A5Q 30_05 !31_07 !31_09 !31_10
CLBLM_L.SLICEL_X1.AOUTMUX.CY !30_05 31_07 !31_09 31_10
CLBLM_L.SLICEL_X1.AOUTMUX.XOR !30_05 31_07 !31_09 !31_10
CLBLM_L.SLICEL_X1.AOUTMUX.F7 30_05 !31_07 !31_09 31_10
CLBLM_L.SLICEL_X1.AOUTMUX.O5 !30_05 !31_07 31_09 31_10
CLBLM_L.SLICEL_X1.AOUTMUX.O6 !30_05 !31_07 !31_10 31_09
CLBLM_L.SLICEL_X1.AOUTMUX.XOR !30_05 !31_09 !31_10 31_07
CLBLM_L.SLICEL_X1.AOUTMUX.O6 !30_05 !31_07 31_09 !31_10
CLBLM_L.SLICEL_X1.B5FF.ZINI 31_23
CLBLM_L.SLICEL_X1.B5FF.ZRST 00_16
CLBLM_L.SLICEL_X1.B5FFMUX.IN_A 31_19
@ -87,11 +87,11 @@ CLBLM_L.SLICEL_X1.B5FFMUX.IN_B 31_18
CLBLM_L.SLICEL_X1.BFF.ZINI 31_29
CLBLM_L.SLICEL_X1.BFF.ZRST 31_30
CLBLM_L.SLICEL_X1.BFFMUX.BX !31_24 !31_25 !31_26 31_27
CLBLM_L.SLICEL_X1.BFFMUX.CY !31_24 !31_27 31_25 31_26
CLBLM_L.SLICEL_X1.BFFMUX.F8 !31_24 !31_26 31_25 31_27
CLBLM_L.SLICEL_X1.BFFMUX.O5 !31_26 !31_27 31_24 31_25
CLBLM_L.SLICEL_X1.BFFMUX.O6 !31_25 !31_26 !31_27 31_24
CLBLM_L.SLICEL_X1.BFFMUX.XOR !31_24 !31_25 !31_27 31_26
CLBLM_L.SLICEL_X1.BFFMUX.CY !31_24 31_25 31_26 !31_27
CLBLM_L.SLICEL_X1.BFFMUX.XOR !31_24 !31_25 31_26 !31_27
CLBLM_L.SLICEL_X1.BFFMUX.F8 !31_24 31_25 !31_26 31_27
CLBLM_L.SLICEL_X1.BFFMUX.O5 31_24 31_25 !31_26 !31_27
CLBLM_L.SLICEL_X1.BFFMUX.O6 31_24 !31_25 !31_26 !31_27
CLBLM_L.SLICEL_X1.BLUT.INIT[00] 26_31
CLBLM_L.SLICEL_X1.BLUT.INIT[01] 27_31
CLBLM_L.SLICEL_X1.BLUT.INIT[02] 26_30
@ -156,29 +156,25 @@ CLBLM_L.SLICEL_X1.BLUT.INIT[60] 29_17
CLBLM_L.SLICEL_X1.BLUT.INIT[61] 28_17
CLBLM_L.SLICEL_X1.BLUT.INIT[62] 29_16
CLBLM_L.SLICEL_X1.BLUT.INIT[63] 28_16
CLBLM_L.SLICEL_X1.BOUTMUX.B5Q !30_28 !31_20 !31_21 30_29
CLBLM_L.SLICEL_X1.BOUTMUX.CY !30_29 !31_20 30_28 31_21
CLBLM_L.SLICEL_X1.BOUTMUX.F8 !30_28 !31_20 30_29 31_21
CLBLM_L.SLICEL_X1.BOUTMUX.B5Q !30_28 30_29 !31_20 !31_21
CLBLM_L.SLICEL_X1.BOUTMUX.CY 30_28 !30_29 !31_20 31_21
CLBLM_L.SLICEL_X1.BOUTMUX.XOR 30_28 !30_29 !31_20 !31_21
CLBLM_L.SLICEL_X1.BOUTMUX.F8 !30_28 30_29 !31_20 31_21
CLBLM_L.SLICEL_X1.BOUTMUX.O5 !30_28 !30_29 31_20 31_21
CLBLM_L.SLICEL_X1.BOUTMUX.O6 !30_28 !30_29 !31_21 31_20
CLBLM_L.SLICEL_X1.BOUTMUX.XOR !30_29 !31_20 !31_21 30_28
CLBLM_L.SLICEL_X1.BOUTMUX.O6 !30_28 !30_29 31_20 !31_21
CLBLM_L.SLICEL_X1.C5FF.ZINI 31_42
CLBLM_L.SLICEL_X1.C5FF.ZRST 00_44
CLBLM_L.SLICEL_X1.C5FFMUX.IN_A 31_44
CLBLM_L.SLICEL_X1.C5FFMUX.IN_B 31_39
CLBLM_L.SLICEL_X1.CARRY4.ACY0 31_14
CLBLM_L.SLICEL_X1.CARRY4.BCY0 00_08
CLBLM_L.SLICEL_X1.CARRY4.CCY0 31_48
CLBLM_L.SLICEL_X1.CARRY4.DCY0 31_49
CLBLM_L.SLICEL_X1.CEUSEDMUX 00_36
CLBLM_L.SLICEL_X1.CFF.ZINI 31_34
CLBLM_L.SLICEL_X1.CFF.ZRST 30_34
CLBLM_L.SLICEL_X1.CFFMUX.CX !31_35 !31_36 !31_37 31_38
CLBLM_L.SLICEL_X1.CFFMUX.CY !31_36 !31_38 31_35 31_37
CLBLM_L.SLICEL_X1.CFFMUX.F7 !31_36 !31_37 31_35 31_38
CLBLM_L.SLICEL_X1.CFFMUX.O5 !31_37 !31_38 31_35 31_36
CLBLM_L.SLICEL_X1.CFFMUX.O6 !31_35 !31_37 !31_38 31_36
CLBLM_L.SLICEL_X1.CFFMUX.XOR !31_35 !31_36 !31_38 31_37
CLBLM_L.SLICEL_X1.CFFMUX.CY 31_35 !31_36 31_37 !31_38
CLBLM_L.SLICEL_X1.CFFMUX.XOR !31_35 !31_36 31_37 !31_38
CLBLM_L.SLICEL_X1.CFFMUX.F7 31_35 !31_36 !31_37 31_38
CLBLM_L.SLICEL_X1.CFFMUX.O5 31_35 31_36 !31_37 !31_38
CLBLM_L.SLICEL_X1.CFFMUX.O6 !31_35 31_36 !31_37 !31_38
CLBLM_L.SLICEL_X1.CLKINV 00_52
CLBLM_L.SLICEL_X1.CLUT.INIT[00] 26_47
CLBLM_L.SLICEL_X1.CLUT.INIT[01] 27_47
@ -244,23 +240,23 @@ CLBLM_L.SLICEL_X1.CLUT.INIT[60] 29_33
CLBLM_L.SLICEL_X1.CLUT.INIT[61] 28_33
CLBLM_L.SLICEL_X1.CLUT.INIT[62] 29_32
CLBLM_L.SLICEL_X1.CLUT.INIT[63] 28_32
CLBLM_L.SLICEL_X1.COUTMUX.C5Q !30_42 !31_40 !31_43 30_41
CLBLM_L.SLICEL_X1.COUTMUX.CY !30_41 !31_43 30_42 31_40
CLBLM_L.SLICEL_X1.COUTMUX.F7 !30_42 !31_43 30_41 31_40
CLBLM_L.SLICEL_X1.COUTMUX.C5Q 30_41 !30_42 !31_40 !31_43
CLBLM_L.SLICEL_X1.COUTMUX.CY !30_41 30_42 31_40 !31_43
CLBLM_L.SLICEL_X1.COUTMUX.XOR !30_41 30_42 !31_40 !31_43
CLBLM_L.SLICEL_X1.COUTMUX.F7 30_41 !30_42 31_40 !31_43
CLBLM_L.SLICEL_X1.COUTMUX.O5 !30_41 !30_42 31_40 31_43
CLBLM_L.SLICEL_X1.COUTMUX.O6 !30_41 !30_42 !31_40 31_43
CLBLM_L.SLICEL_X1.COUTMUX.XOR !30_41 !31_40 !31_43 30_42
CLBLM_L.SLICEL_X1.D5FF.ZINI 31_52
CLBLM_L.SLICEL_X1.D5FF.ZRST 00_56
CLBLM_L.SLICEL_X1.D5FFMUX.IN_A 31_55
CLBLM_L.SLICEL_X1.D5FFMUX.IN_B 31_54
CLBLM_L.SLICEL_X1.DFF.ZINI 31_59
CLBLM_L.SLICEL_X1.DFF.ZRST 31_50
CLBLM_L.SLICEL_X1.DFFMUX.CY !31_60 !31_61 30_58 31_62
CLBLM_L.SLICEL_X1.DFFMUX.DX !30_58 !31_60 !31_62 31_61
CLBLM_L.SLICEL_X1.DFFMUX.O5 !31_61 !31_62 30_58 31_60
CLBLM_L.SLICEL_X1.DFFMUX.O6 !30_58 !31_61 !31_62 31_60
CLBLM_L.SLICEL_X1.DFFMUX.CY 30_58 !31_60 !31_61 31_62
CLBLM_L.SLICEL_X1.DFFMUX.DX !30_58 !31_60 31_61 !31_62
CLBLM_L.SLICEL_X1.DFFMUX.XOR !30_58 !31_60 !31_61 31_62
CLBLM_L.SLICEL_X1.DFFMUX.O5 30_58 31_60 !31_61 !31_62
CLBLM_L.SLICEL_X1.DFFMUX.O6 !30_58 31_60 !31_61 !31_62
CLBLM_L.SLICEL_X1.DLUT.INIT[00] 26_63
CLBLM_L.SLICEL_X1.DLUT.INIT[01] 27_63
CLBLM_L.SLICEL_X1.DLUT.INIT[02] 26_62
@ -325,29 +321,33 @@ CLBLM_L.SLICEL_X1.DLUT.INIT[60] 29_49
CLBLM_L.SLICEL_X1.DLUT.INIT[61] 28_49
CLBLM_L.SLICEL_X1.DLUT.INIT[62] 29_48
CLBLM_L.SLICEL_X1.DLUT.INIT[63] 28_48
CLBLM_L.SLICEL_X1.DOUTMUX.CY !31_53 !31_56 30_53 31_57
CLBLM_L.SLICEL_X1.DOUTMUX.D5Q !30_53 !31_56 !31_57 31_53
CLBLM_L.SLICEL_X1.DOUTMUX.CY 30_53 !31_53 !31_56 31_57
CLBLM_L.SLICEL_X1.DOUTMUX.D5Q !30_53 31_53 !31_56 !31_57
CLBLM_L.SLICEL_X1.DOUTMUX.XOR 30_53 !31_53 !31_56 !31_57
CLBLM_L.SLICEL_X1.DOUTMUX.O5 !30_53 !31_53 31_56 31_57
CLBLM_L.SLICEL_X1.DOUTMUX.O6 !30_53 !31_53 !31_57 31_56
CLBLM_L.SLICEL_X1.DOUTMUX.XOR !31_53 !31_56 !31_57 30_53
CLBLM_L.SLICEL_X1.DOUTMUX.O6 !30_53 !31_53 31_56 !31_57
CLBLM_L.SLICEL_X1.FFSYNC 01_31
CLBLM_L.SLICEL_X1.LATCH 31_32
CLBLM_L.SLICEL_X1.PRECYINIT.1 !31_12 !31_13 01_11
CLBLM_L.SLICEL_X1.PRECYINIT.1 01_11 !31_12 !31_13
CLBLM_L.SLICEL_X1.PRECYINIT.AX !01_11 !31_12 31_13
CLBLM_L.SLICEL_X1.PRECYINIT.CIN !01_11 !31_13 31_12
CLBLM_L.SLICEL_X1.PRECYINIT.CIN !01_11 31_12 !31_13
CLBLM_L.SLICEL_X1.SRUSEDMUX 00_32
CLBLM_L.SLICEL_X1.CARRY4.ACY0 31_14
CLBLM_L.SLICEL_X1.CARRY4.BCY0 00_08
CLBLM_L.SLICEL_X1.CARRY4.CCY0 31_48
CLBLM_L.SLICEL_X1.CARRY4.DCY0 31_49
CLBLM_L.SLICEM_X0.A5FF.ZINI 31_06
CLBLM_L.SLICEM_X0.A5FF.ZRST 01_07
CLBLM_L.SLICEM_X0.A5FFMUX.IN_A 30_09
CLBLM_L.SLICEM_X0.A5FFMUX.IN_B 30_10
CLBLM_L.SLICEM_X0.AFF.ZINI 31_03
CLBLM_L.SLICEM_X0.AFF.ZRST 30_12
CLBLM_L.SLICEM_X0.AFFMUX.AX !30_00 !30_02 !30_03 30_01
CLBLM_L.SLICEM_X0.AFFMUX.CY !30_01 !30_03 30_00 30_02
CLBLM_L.SLICEM_X0.AFFMUX.F7 !30_02 !30_03 30_00 30_01
CLBLM_L.SLICEM_X0.AFFMUX.O5 !30_01 !30_02 30_00 30_03
CLBLM_L.SLICEM_X0.AFFMUX.AX !30_00 30_01 !30_02 !30_03
CLBLM_L.SLICEM_X0.AFFMUX.CY 30_00 !30_01 30_02 !30_03
CLBLM_L.SLICEM_X0.AFFMUX.XOR !30_00 !30_01 30_02 !30_03
CLBLM_L.SLICEM_X0.AFFMUX.F7 30_00 30_01 !30_02 !30_03
CLBLM_L.SLICEM_X0.AFFMUX.O5 30_00 !30_01 !30_02 30_03
CLBLM_L.SLICEM_X0.AFFMUX.O6 !30_00 !30_01 !30_02 30_03
CLBLM_L.SLICEM_X0.AFFMUX.XOR !30_00 !30_01 !30_03 30_02
CLBLM_L.SLICEM_X0.ALUT.DI1MUX.AI 00_00
CLBLM_L.SLICEM_X0.ALUT.INIT[00] 34_15
CLBLM_L.SLICEM_X0.ALUT.INIT[01] 35_15
@ -416,24 +416,24 @@ CLBLM_L.SLICEM_X0.ALUT.INIT[63] 33_00
CLBLM_L.SLICEM_X0.ALUT.RAM 31_16
CLBLM_L.SLICEM_X0.ALUT.SMALL 00_04
CLBLM_L.SLICEM_X0.ALUT.SRL 30_16
CLBLM_L.SLICEM_X0.AOUTMUX.A5Q !30_06 !30_08 !30_11 30_07
CLBLM_L.SLICEM_X0.AOUTMUX.CY !30_07 !30_11 30_06 30_08
CLBLM_L.SLICEM_X0.AOUTMUX.F7 !30_08 !30_11 30_06 30_07
CLBLM_L.SLICEM_X0.AOUTMUX.O5 !30_07 !30_08 30_06 30_11
CLBLM_L.SLICEM_X0.AOUTMUX.A5Q !30_06 30_07 !30_08 !30_11
CLBLM_L.SLICEM_X0.AOUTMUX.CY 30_06 !30_07 30_08 !30_11
CLBLM_L.SLICEM_X0.AOUTMUX.XOR !30_06 !30_07 30_08 !30_11
CLBLM_L.SLICEM_X0.AOUTMUX.F7 30_06 30_07 !30_08 !30_11
CLBLM_L.SLICEM_X0.AOUTMUX.O5 30_06 !30_07 !30_08 30_11
CLBLM_L.SLICEM_X0.AOUTMUX.O6 !30_06 !30_07 !30_08 30_11
CLBLM_L.SLICEM_X0.AOUTMUX.XOR !30_06 !30_07 !30_11 30_08
CLBLM_L.SLICEM_X0.B5FF.ZINI 31_22
CLBLM_L.SLICEM_X0.B5FF.ZRST 01_19
CLBLM_L.SLICEM_X0.B5FFMUX.IN_A 30_19
CLBLM_L.SLICEM_X0.B5FFMUX.IN_B 30_18
CLBLM_L.SLICEM_X0.BFF.ZINI 31_28
CLBLM_L.SLICEM_X0.BFF.ZRST 30_30
CLBLM_L.SLICEM_X0.BFFMUX.BX !30_24 !30_25 !30_27 30_26
CLBLM_L.SLICEM_X0.BFFMUX.CY !30_24 !30_26 30_25 30_27
CLBLM_L.SLICEM_X0.BFFMUX.BX !30_24 !30_25 30_26 !30_27
CLBLM_L.SLICEM_X0.BFFMUX.CY !30_24 30_25 !30_26 30_27
CLBLM_L.SLICEM_X0.BFFMUX.XOR !30_24 30_25 !30_26 !30_27
CLBLM_L.SLICEM_X0.BFFMUX.F8 !30_24 !30_25 30_26 30_27
CLBLM_L.SLICEM_X0.BFFMUX.O5 !30_25 !30_26 30_24 30_27
CLBLM_L.SLICEM_X0.BFFMUX.O6 !30_25 !30_26 !30_27 30_24
CLBLM_L.SLICEM_X0.BFFMUX.XOR !30_24 !30_26 !30_27 30_25
CLBLM_L.SLICEM_X0.BFFMUX.O5 30_24 !30_25 !30_26 30_27
CLBLM_L.SLICEM_X0.BFFMUX.O6 30_24 !30_25 !30_26 !30_27
CLBLM_L.SLICEM_X0.BLUT.DI1MUX.BI 00_20
CLBLM_L.SLICEM_X0.BLUT.INIT[00] 34_31
CLBLM_L.SLICEM_X0.BLUT.INIT[01] 35_31
@ -503,28 +503,24 @@ CLBLM_L.SLICEM_X0.BLUT.RAM 31_17
CLBLM_L.SLICEM_X0.BLUT.SMALL 00_24
CLBLM_L.SLICEM_X0.BLUT.SRL 30_17
CLBLM_L.SLICEM_X0.BOUTMUX.B5Q !30_20 !30_21 !30_22 30_23
CLBLM_L.SLICEM_X0.BOUTMUX.CY !30_20 !30_23 30_21 30_22
CLBLM_L.SLICEM_X0.BOUTMUX.CY !30_20 30_21 30_22 !30_23
CLBLM_L.SLICEM_X0.BOUTMUX.XOR !30_20 30_21 !30_22 !30_23
CLBLM_L.SLICEM_X0.BOUTMUX.F8 !30_20 !30_21 30_22 30_23
CLBLM_L.SLICEM_X0.BOUTMUX.O5 !30_21 !30_23 30_20 30_22
CLBLM_L.SLICEM_X0.BOUTMUX.O6 !30_21 !30_22 !30_23 30_20
CLBLM_L.SLICEM_X0.BOUTMUX.XOR !30_20 !30_22 !30_23 30_21
CLBLM_L.SLICEM_X0.BOUTMUX.O5 30_20 !30_21 30_22 !30_23
CLBLM_L.SLICEM_X0.BOUTMUX.O6 30_20 !30_21 !30_22 !30_23
CLBLM_L.SLICEM_X0.C5FF.ZINI 31_41
CLBLM_L.SLICEM_X0.C5FF.ZRST 01_47
CLBLM_L.SLICEM_X0.C5FFMUX.IN_A 31_45
CLBLM_L.SLICEM_X0.C5FFMUX.IN_B 30_39
CLBLM_L.SLICEM_X0.CARRY4.ACY0 30_15
CLBLM_L.SLICEM_X0.CARRY4.BCY0 01_15
CLBLM_L.SLICEM_X0.CARRY4.CCY0 30_48
CLBLM_L.SLICEM_X0.CARRY4.DCY0 30_49
CLBLM_L.SLICEM_X0.CEUSEDMUX 01_39
CLBLM_L.SLICEM_X0.CFF.ZINI 31_33
CLBLM_L.SLICEM_X0.CFF.ZRST 30_33
CLBLM_L.SLICEM_X0.CFFMUX.CX !30_35 !30_37 !30_38 30_36
CLBLM_L.SLICEM_X0.CFFMUX.CY !30_36 !30_38 30_35 30_37
CLBLM_L.SLICEM_X0.CFFMUX.F7 !30_37 !30_38 30_35 30_36
CLBLM_L.SLICEM_X0.CFFMUX.O5 !30_36 !30_37 30_35 30_38
CLBLM_L.SLICEM_X0.CFFMUX.CX !30_35 30_36 !30_37 !30_38
CLBLM_L.SLICEM_X0.CFFMUX.CY 30_35 !30_36 30_37 !30_38
CLBLM_L.SLICEM_X0.CFFMUX.XOR !30_35 !30_36 30_37 !30_38
CLBLM_L.SLICEM_X0.CFFMUX.F7 30_35 30_36 !30_37 !30_38
CLBLM_L.SLICEM_X0.CFFMUX.O5 30_35 !30_36 !30_37 30_38
CLBLM_L.SLICEM_X0.CFFMUX.O6 !30_35 !30_36 !30_37 30_38
CLBLM_L.SLICEM_X0.CFFMUX.XOR !30_35 !30_36 !30_38 30_37
CLBLM_L.SLICEM_X0.CLKINV 01_51
CLBLM_L.SLICEM_X0.CLUT.DI1MUX.CI 01_43
CLBLM_L.SLICEM_X0.CLUT.INIT[00] 34_47
@ -594,23 +590,23 @@ CLBLM_L.SLICEM_X0.CLUT.INIT[63] 33_32
CLBLM_L.SLICEM_X0.CLUT.RAM 31_46
CLBLM_L.SLICEM_X0.CLUT.SMALL 00_28
CLBLM_L.SLICEM_X0.CLUT.SRL 30_46
CLBLM_L.SLICEM_X0.COUTMUX.C5Q !30_40 !30_44 !30_45 30_43
CLBLM_L.SLICEM_X0.COUTMUX.CY !30_43 !30_45 30_40 30_44
CLBLM_L.SLICEM_X0.COUTMUX.F7 !30_44 !30_45 30_40 30_43
CLBLM_L.SLICEM_X0.COUTMUX.O5 !30_43 !30_44 30_40 30_45
CLBLM_L.SLICEM_X0.COUTMUX.C5Q !30_40 30_43 !30_44 !30_45
CLBLM_L.SLICEM_X0.COUTMUX.CY 30_40 !30_43 30_44 !30_45
CLBLM_L.SLICEM_X0.COUTMUX.XOR !30_40 !30_43 30_44 !30_45
CLBLM_L.SLICEM_X0.COUTMUX.F7 30_40 30_43 !30_44 !30_45
CLBLM_L.SLICEM_X0.COUTMUX.O5 30_40 !30_43 !30_44 30_45
CLBLM_L.SLICEM_X0.COUTMUX.O6 !30_40 !30_43 !30_44 30_45
CLBLM_L.SLICEM_X0.COUTMUX.XOR !30_40 !30_43 !30_45 30_44
CLBLM_L.SLICEM_X0.D5FF.ZINI 31_51
CLBLM_L.SLICEM_X0.D5FF.ZRST 01_55
CLBLM_L.SLICEM_X0.D5FFMUX.IN_A 30_55
CLBLM_L.SLICEM_X0.D5FFMUX.IN_B 30_54
CLBLM_L.SLICEM_X0.DFF.ZINI 31_58
CLBLM_L.SLICEM_X0.DFF.ZRST 30_50
CLBLM_L.SLICEM_X0.DFFMUX.CY !30_59 !30_61 30_60 30_62
CLBLM_L.SLICEM_X0.DFFMUX.DX !30_59 !30_60 !30_62 30_61
CLBLM_L.SLICEM_X0.DFFMUX.O5 !30_60 !30_61 30_59 30_62
CLBLM_L.SLICEM_X0.DFFMUX.O6 !30_60 !30_61 !30_62 30_59
CLBLM_L.SLICEM_X0.DFFMUX.XOR !30_59 !30_61 !30_62 30_60
CLBLM_L.SLICEM_X0.DFFMUX.CY !30_59 30_60 !30_61 30_62
CLBLM_L.SLICEM_X0.DFFMUX.DX !30_59 !30_60 30_61 !30_62
CLBLM_L.SLICEM_X0.DFFMUX.XOR !30_59 30_60 !30_61 !30_62
CLBLM_L.SLICEM_X0.DFFMUX.O5 30_59 !30_60 !30_61 30_62
CLBLM_L.SLICEM_X0.DFFMUX.O6 30_59 !30_60 !30_61 !30_62
CLBLM_L.SLICEM_X0.DLUT.INIT[00] 34_63
CLBLM_L.SLICEM_X0.DLUT.INIT[01] 35_63
CLBLM_L.SLICEM_X0.DLUT.INIT[02] 34_62
@ -678,17 +674,21 @@ CLBLM_L.SLICEM_X0.DLUT.INIT[63] 33_48
CLBLM_L.SLICEM_X0.DLUT.RAM 31_47
CLBLM_L.SLICEM_X0.DLUT.SMALL 01_59
CLBLM_L.SLICEM_X0.DLUT.SRL 30_47
CLBLM_L.SLICEM_X0.DOUTMUX.CY !30_56 !30_57 30_51 30_52
CLBLM_L.SLICEM_X0.DOUTMUX.CY 30_51 30_52 !30_56 !30_57
CLBLM_L.SLICEM_X0.DOUTMUX.D5Q !30_51 !30_52 !30_56 30_57
CLBLM_L.SLICEM_X0.DOUTMUX.O5 !30_51 !30_57 30_52 30_56
CLBLM_L.SLICEM_X0.DOUTMUX.O6 !30_51 !30_52 !30_57 30_56
CLBLM_L.SLICEM_X0.DOUTMUX.XOR !30_52 !30_56 !30_57 30_51
CLBLM_L.SLICEM_X0.DOUTMUX.XOR 30_51 !30_52 !30_56 !30_57
CLBLM_L.SLICEM_X0.DOUTMUX.O5 !30_51 30_52 30_56 !30_57
CLBLM_L.SLICEM_X0.DOUTMUX.O6 !30_51 !30_52 30_56 !30_57
CLBLM_L.SLICEM_X0.FFSYNC 00_48
CLBLM_L.SLICEM_X0.LATCH 30_32
CLBLM_L.SLICEM_X0.PRECYINIT.1 !30_13 !30_14 00_12
CLBLM_L.SLICEM_X0.PRECYINIT.1 00_12 !30_13 !30_14
CLBLM_L.SLICEM_X0.PRECYINIT.AX !00_12 !30_13 30_14
CLBLM_L.SLICEM_X0.PRECYINIT.CIN !00_12 !30_14 30_13
CLBLM_L.SLICEM_X0.PRECYINIT.CIN !00_12 30_13 !30_14
CLBLM_L.SLICEM_X0.SRUSEDMUX 01_35
CLBLM_L.SLICEM_X0.WA7USED 00_40
CLBLM_L.SLICEM_X0.WA8USED 01_27
CLBLM_L.SLICEM_X0.WEMUX.CE 01_23
CLBLM_L.SLICEM_X0.CARRY4.ACY0 30_15
CLBLM_L.SLICEM_X0.CARRY4.BCY0 01_15
CLBLM_L.SLICEM_X0.CARRY4.CCY0 30_48
CLBLM_L.SLICEM_X0.CARRY4.DCY0 30_49

174
artix7/segbits_clblm_r.db
View File

@ -4,12 +4,12 @@ CLBLM_R.SLICEL_X1.A5FFMUX.IN_A 31_08
CLBLM_R.SLICEL_X1.A5FFMUX.IN_B 31_11
CLBLM_R.SLICEL_X1.AFF.ZINI 31_04
CLBLM_R.SLICEL_X1.AFF.ZRST 31_15
CLBLM_R.SLICEL_X1.AFFMUX.AX !30_04 !31_00 !31_02 31_01
CLBLM_R.SLICEL_X1.AFFMUX.CY !30_04 !31_01 31_00 31_02
CLBLM_R.SLICEL_X1.AFFMUX.F7 !30_04 !31_02 31_00 31_01
CLBLM_R.SLICEL_X1.AFFMUX.O5 !31_01 !31_02 30_04 31_00
CLBLM_R.SLICEL_X1.AFFMUX.O6 !31_00 !31_01 !31_02 30_04
CLBLM_R.SLICEL_X1.AFFMUX.AX !30_04 !31_00 31_01 !31_02
CLBLM_R.SLICEL_X1.AFFMUX.CY !30_04 31_00 !31_01 31_02
CLBLM_R.SLICEL_X1.AFFMUX.XOR !30_04 !31_00 !31_01 31_02
CLBLM_R.SLICEL_X1.AFFMUX.F7 !30_04 31_00 31_01 !31_02
CLBLM_R.SLICEL_X1.AFFMUX.O5 30_04 31_00 !31_01 !31_02
CLBLM_R.SLICEL_X1.AFFMUX.O6 30_04 !31_00 !31_01 !31_02
CLBLM_R.SLICEL_X1.ALUT.INIT[00] 26_15
CLBLM_R.SLICEL_X1.ALUT.INIT[01] 27_15
CLBLM_R.SLICEL_X1.ALUT.INIT[02] 26_14
@ -74,12 +74,12 @@ CLBLM_R.SLICEL_X1.ALUT.INIT[60] 29_01
CLBLM_R.SLICEL_X1.ALUT.INIT[61] 28_01
CLBLM_R.SLICEL_X1.ALUT.INIT[62] 29_00
CLBLM_R.SLICEL_X1.ALUT.INIT[63] 28_00
CLBLM_R.SLICEL_X1.AOUTMUX.A5Q !31_07 !31_09 !31_10 30_05
CLBLM_R.SLICEL_X1.AOUTMUX.CY !30_05 !31_09 31_07 31_10
CLBLM_R.SLICEL_X1.AOUTMUX.F7 !31_07 !31_09 30_05 31_10
CLBLM_R.SLICEL_X1.AOUTMUX.A5Q 30_05 !31_07 !31_09 !31_10
CLBLM_R.SLICEL_X1.AOUTMUX.CY !30_05 31_07 !31_09 31_10
CLBLM_R.SLICEL_X1.AOUTMUX.XOR !30_05 31_07 !31_09 !31_10
CLBLM_R.SLICEL_X1.AOUTMUX.F7 30_05 !31_07 !31_09 31_10
CLBLM_R.SLICEL_X1.AOUTMUX.O5 !30_05 !31_07 31_09 31_10
CLBLM_R.SLICEL_X1.AOUTMUX.O6 !30_05 !31_07 !31_10 31_09
CLBLM_R.SLICEL_X1.AOUTMUX.XOR !30_05 !31_09 !31_10 31_07
CLBLM_R.SLICEL_X1.AOUTMUX.O6 !30_05 !31_07 31_09 !31_10
CLBLM_R.SLICEL_X1.B5FF.ZINI 31_23
CLBLM_R.SLICEL_X1.B5FF.ZRST 00_16
CLBLM_R.SLICEL_X1.B5FFMUX.IN_A 31_19
@ -87,11 +87,11 @@ CLBLM_R.SLICEL_X1.B5FFMUX.IN_B 31_18
CLBLM_R.SLICEL_X1.BFF.ZINI 31_29
CLBLM_R.SLICEL_X1.BFF.ZRST 31_30
CLBLM_R.SLICEL_X1.BFFMUX.BX !31_24 !31_25 !31_26 31_27
CLBLM_R.SLICEL_X1.BFFMUX.CY !31_24 !31_27 31_25 31_26
CLBLM_R.SLICEL_X1.BFFMUX.F8 !31_24 !31_26 31_25 31_27
CLBLM_R.SLICEL_X1.BFFMUX.O5 !31_26 !31_27 31_24 31_25
CLBLM_R.SLICEL_X1.BFFMUX.O6 !31_25 !31_26 !31_27 31_24
CLBLM_R.SLICEL_X1.BFFMUX.XOR !31_24 !31_25 !31_27 31_26
CLBLM_R.SLICEL_X1.BFFMUX.CY !31_24 31_25 31_26 !31_27
CLBLM_R.SLICEL_X1.BFFMUX.XOR !31_24 !31_25 31_26 !31_27
CLBLM_R.SLICEL_X1.BFFMUX.F8 !31_24 31_25 !31_26 31_27
CLBLM_R.SLICEL_X1.BFFMUX.O5 31_24 31_25 !31_26 !31_27
CLBLM_R.SLICEL_X1.BFFMUX.O6 31_24 !31_25 !31_26 !31_27
CLBLM_R.SLICEL_X1.BLUT.INIT[00] 26_31
CLBLM_R.SLICEL_X1.BLUT.INIT[01] 27_31
CLBLM_R.SLICEL_X1.BLUT.INIT[02] 26_30
@ -156,29 +156,25 @@ CLBLM_R.SLICEL_X1.BLUT.INIT[60] 29_17
CLBLM_R.SLICEL_X1.BLUT.INIT[61] 28_17
CLBLM_R.SLICEL_X1.BLUT.INIT[62] 29_16
CLBLM_R.SLICEL_X1.BLUT.INIT[63] 28_16
CLBLM_R.SLICEL_X1.BOUTMUX.B5Q !30_28 !31_20 !31_21 30_29
CLBLM_R.SLICEL_X1.BOUTMUX.CY !30_29 !31_20 30_28 31_21
CLBLM_R.SLICEL_X1.BOUTMUX.F8 !30_28 !31_20 30_29 31_21
CLBLM_R.SLICEL_X1.BOUTMUX.B5Q !30_28 30_29 !31_20 !31_21
CLBLM_R.SLICEL_X1.BOUTMUX.CY 30_28 !30_29 !31_20 31_21
CLBLM_R.SLICEL_X1.BOUTMUX.XOR 30_28 !30_29 !31_20 !31_21
CLBLM_R.SLICEL_X1.BOUTMUX.F8 !30_28 30_29 !31_20 31_21
CLBLM_R.SLICEL_X1.BOUTMUX.O5 !30_28 !30_29 31_20 31_21
CLBLM_R.SLICEL_X1.BOUTMUX.O6 !30_28 !30_29 !31_21 31_20
CLBLM_R.SLICEL_X1.BOUTMUX.XOR !30_29 !31_20 !31_21 30_28
CLBLM_R.SLICEL_X1.BOUTMUX.O6 !30_28 !30_29 31_20 !31_21
CLBLM_R.SLICEL_X1.C5FF.ZINI 31_42
CLBLM_R.SLICEL_X1.C5FF.ZRST 00_44
CLBLM_R.SLICEL_X1.C5FFMUX.IN_A 31_44
CLBLM_R.SLICEL_X1.C5FFMUX.IN_B 31_39
CLBLM_R.SLICEL_X1.CARRY4.ACY0 31_14
CLBLM_R.SLICEL_X1.CARRY4.BCY0 00_08
CLBLM_R.SLICEL_X1.CARRY4.CCY0 31_48
CLBLM_R.SLICEL_X1.CARRY4.DCY0 31_49
CLBLM_R.SLICEL_X1.CEUSEDMUX 00_36
CLBLM_R.SLICEL_X1.CFF.ZINI 31_34
CLBLM_R.SLICEL_X1.CFF.ZRST 30_34
CLBLM_R.SLICEL_X1.CFFMUX.CX !31_35 !31_36 !31_37 31_38
CLBLM_R.SLICEL_X1.CFFMUX.CY !31_36 !31_38 31_35 31_37
CLBLM_R.SLICEL_X1.CFFMUX.F7 !31_36 !31_37 31_35 31_38
CLBLM_R.SLICEL_X1.CFFMUX.O5 !31_37 !31_38 31_35 31_36
CLBLM_R.SLICEL_X1.CFFMUX.O6 !31_35 !31_37 !31_38 31_36
CLBLM_R.SLICEL_X1.CFFMUX.XOR !31_35 !31_36 !31_38 31_37
CLBLM_R.SLICEL_X1.CFFMUX.CY 31_35 !31_36 31_37 !31_38
CLBLM_R.SLICEL_X1.CFFMUX.XOR !31_35 !31_36 31_37 !31_38
CLBLM_R.SLICEL_X1.CFFMUX.F7 31_35 !31_36 !31_37 31_38
CLBLM_R.SLICEL_X1.CFFMUX.O5 31_35 31_36 !31_37 !31_38
CLBLM_R.SLICEL_X1.CFFMUX.O6 !31_35 31_36 !31_37 !31_38
CLBLM_R.SLICEL_X1.CLKINV 00_52
CLBLM_R.SLICEL_X1.CLUT.INIT[00] 26_47
CLBLM_R.SLICEL_X1.CLUT.INIT[01] 27_47
@ -244,23 +240,23 @@ CLBLM_R.SLICEL_X1.CLUT.INIT[60] 29_33
CLBLM_R.SLICEL_X1.CLUT.INIT[61] 28_33
CLBLM_R.SLICEL_X1.CLUT.INIT[62] 29_32
CLBLM_R.SLICEL_X1.CLUT.INIT[63] 28_32
CLBLM_R.SLICEL_X1.COUTMUX.C5Q !30_42 !31_40 !31_43 30_41
CLBLM_R.SLICEL_X1.COUTMUX.CY !30_41 !31_43 30_42 31_40
CLBLM_R.SLICEL_X1.COUTMUX.F7 !30_42 !31_43 30_41 31_40
CLBLM_R.SLICEL_X1.COUTMUX.C5Q 30_41 !30_42 !31_40 !31_43
CLBLM_R.SLICEL_X1.COUTMUX.CY !30_41 30_42 31_40 !31_43
CLBLM_R.SLICEL_X1.COUTMUX.XOR !30_41 30_42 !31_40 !31_43
CLBLM_R.SLICEL_X1.COUTMUX.F7 30_41 !30_42 31_40 !31_43
CLBLM_R.SLICEL_X1.COUTMUX.O5 !30_41 !30_42 31_40 31_43
CLBLM_R.SLICEL_X1.COUTMUX.O6 !30_41 !30_42 !31_40 31_43
CLBLM_R.SLICEL_X1.COUTMUX.XOR !30_41 !31_40 !31_43 30_42
CLBLM_R.SLICEL_X1.D5FF.ZINI 31_52
CLBLM_R.SLICEL_X1.D5FF.ZRST 00_56
CLBLM_R.SLICEL_X1.D5FFMUX.IN_A 31_55
CLBLM_R.SLICEL_X1.D5FFMUX.IN_B 31_54
CLBLM_R.SLICEL_X1.DFF.ZINI 31_59
CLBLM_R.SLICEL_X1.DFF.ZRST 31_50
CLBLM_R.SLICEL_X1.DFFMUX.CY !31_60 !31_61 30_58 31_62
CLBLM_R.SLICEL_X1.DFFMUX.DX !30_58 !31_60 !31_62 31_61
CLBLM_R.SLICEL_X1.DFFMUX.O5 !31_61 !31_62 30_58 31_60
CLBLM_R.SLICEL_X1.DFFMUX.O6 !30_58 !31_61 !31_62 31_60
CLBLM_R.SLICEL_X1.DFFMUX.CY 30_58 !31_60 !31_61 31_62
CLBLM_R.SLICEL_X1.DFFMUX.DX !30_58 !31_60 31_61 !31_62
CLBLM_R.SLICEL_X1.DFFMUX.XOR !30_58 !31_60 !31_61 31_62
CLBLM_R.SLICEL_X1.DFFMUX.O5 30_58 31_60 !31_61 !31_62
CLBLM_R.SLICEL_X1.DFFMUX.O6 !30_58 31_60 !31_61 !31_62
CLBLM_R.SLICEL_X1.DLUT.INIT[00] 26_63
CLBLM_R.SLICEL_X1.DLUT.INIT[01] 27_63
CLBLM_R.SLICEL_X1.DLUT.INIT[02] 26_62
@ -325,29 +321,33 @@ CLBLM_R.SLICEL_X1.DLUT.INIT[60] 29_49
CLBLM_R.SLICEL_X1.DLUT.INIT[61] 28_49
CLBLM_R.SLICEL_X1.DLUT.INIT[62] 29_48
CLBLM_R.SLICEL_X1.DLUT.INIT[63] 28_48
CLBLM_R.SLICEL_X1.DOUTMUX.CY !31_53 !31_56 30_53 31_57
CLBLM_R.SLICEL_X1.DOUTMUX.D5Q !30_53 !31_56 !31_57 31_53
CLBLM_R.SLICEL_X1.DOUTMUX.CY 30_53 !31_53 !31_56 31_57
CLBLM_R.SLICEL_X1.DOUTMUX.D5Q !30_53 31_53 !31_56 !31_57
CLBLM_R.SLICEL_X1.DOUTMUX.XOR 30_53 !31_53 !31_56 !31_57
CLBLM_R.SLICEL_X1.DOUTMUX.O5 !30_53 !31_53 31_56 31_57
CLBLM_R.SLICEL_X1.DOUTMUX.O6 !30_53 !31_53 !31_57 31_56
CLBLM_R.SLICEL_X1.DOUTMUX.XOR !31_53 !31_56 !31_57 30_53
CLBLM_R.SLICEL_X1.DOUTMUX.O6 !30_53 !31_53 31_56 !31_57
CLBLM_R.SLICEL_X1.FFSYNC 01_31
CLBLM_R.SLICEL_X1.LATCH 31_32
CLBLM_R.SLICEL_X1.PRECYINIT.1 !31_12 !31_13 01_11
CLBLM_R.SLICEL_X1.PRECYINIT.1 01_11 !31_12 !31_13
CLBLM_R.SLICEL_X1.PRECYINIT.AX !01_11 !31_12 31_13
CLBLM_R.SLICEL_X1.PRECYINIT.CIN !01_11 !31_13 31_12
CLBLM_R.SLICEL_X1.PRECYINIT.CIN !01_11 31_12 !31_13
CLBLM_R.SLICEL_X1.SRUSEDMUX 00_32
CLBLM_R.SLICEL_X1.CARRY4.ACY0 31_14
CLBLM_R.SLICEL_X1.CARRY4.BCY0 00_08
CLBLM_R.SLICEL_X1.CARRY4.CCY0 31_48
CLBLM_R.SLICEL_X1.CARRY4.DCY0 31_49
CLBLM_R.SLICEM_X0.A5FF.ZINI 31_06
CLBLM_R.SLICEM_X0.A5FF.ZRST 01_07
CLBLM_R.SLICEM_X0.A5FFMUX.IN_A 30_09
CLBLM_R.SLICEM_X0.A5FFMUX.IN_B 30_10
CLBLM_R.SLICEM_X0.AFF.ZINI 31_03
CLBLM_R.SLICEM_X0.AFF.ZRST 30_12
CLBLM_R.SLICEM_X0.AFFMUX.AX !30_00 !30_02 !30_03 30_01
CLBLM_R.SLICEM_X0.AFFMUX.CY !30_01 !30_03 30_00 30_02
CLBLM_R.SLICEM_X0.AFFMUX.F7 !30_02 !30_03 30_00 30_01
CLBLM_R.SLICEM_X0.AFFMUX.O5 !30_01 !30_02 30_00 30_03
CLBLM_R.SLICEM_X0.AFFMUX.AX !30_00 30_01 !30_02 !30_03
CLBLM_R.SLICEM_X0.AFFMUX.CY 30_00 !30_01 30_02 !30_03
CLBLM_R.SLICEM_X0.AFFMUX.XOR !30_00 !30_01 30_02 !30_03
CLBLM_R.SLICEM_X0.AFFMUX.F7 30_00 30_01 !30_02 !30_03
CLBLM_R.SLICEM_X0.AFFMUX.O5 30_00 !30_01 !30_02 30_03
CLBLM_R.SLICEM_X0.AFFMUX.O6 !30_00 !30_01 !30_02 30_03
CLBLM_R.SLICEM_X0.AFFMUX.XOR !30_00 !30_01 !30_03 30_02
CLBLM_R.SLICEM_X0.ALUT.DI1MUX.AI 00_00
CLBLM_R.SLICEM_X0.ALUT.INIT[00] 34_15
CLBLM_R.SLICEM_X0.ALUT.INIT[01] 35_15
@ -416,24 +416,24 @@ CLBLM_R.SLICEM_X0.ALUT.INIT[63] 33_00
CLBLM_R.SLICEM_X0.ALUT.RAM 31_16
CLBLM_R.SLICEM_X0.ALUT.SMALL 00_04
CLBLM_R.SLICEM_X0.ALUT.SRL 30_16
CLBLM_R.SLICEM_X0.AOUTMUX.A5Q !30_06 !30_08 !30_11 30_07
CLBLM_R.SLICEM_X0.AOUTMUX.CY !30_07 !30_11 30_06 30_08
CLBLM_R.SLICEM_X0.AOUTMUX.F7 !30_08 !30_11 30_06 30_07
CLBLM_R.SLICEM_X0.AOUTMUX.O5 !30_07 !30_08 30_06 30_11
CLBLM_R.SLICEM_X0.AOUTMUX.A5Q !30_06 30_07 !30_08 !30_11
CLBLM_R.SLICEM_X0.AOUTMUX.CY 30_06 !30_07 30_08 !30_11
CLBLM_R.SLICEM_X0.AOUTMUX.XOR !30_06 !30_07 30_08 !30_11
CLBLM_R.SLICEM_X0.AOUTMUX.F7 30_06 30_07 !30_08 !30_11
CLBLM_R.SLICEM_X0.AOUTMUX.O5 30_06 !30_07 !30_08 30_11
CLBLM_R.SLICEM_X0.AOUTMUX.O6 !30_06 !30_07 !30_08 30_11
CLBLM_R.SLICEM_X0.AOUTMUX.XOR !30_06 !30_07 !30_11 30_08
CLBLM_R.SLICEM_X0.B5FF.ZINI 31_22
CLBLM_R.SLICEM_X0.B5FF.ZRST 01_19
CLBLM_R.SLICEM_X0.B5FFMUX.IN_A 30_19
CLBLM_R.SLICEM_X0.B5FFMUX.IN_B 30_18
CLBLM_R.SLICEM_X0.BFF.ZINI 31_28
CLBLM_R.SLICEM_X0.BFF.ZRST 30_30
CLBLM_R.SLICEM_X0.BFFMUX.BX !30_24 !30_25 !30_27 30_26
CLBLM_R.SLICEM_X0.BFFMUX.CY !30_24 !30_26 30_25 30_27
CLBLM_R.SLICEM_X0.BFFMUX.BX !30_24 !30_25 30_26 !30_27
CLBLM_R.SLICEM_X0.BFFMUX.CY !30_24 30_25 !30_26 30_27
CLBLM_R.SLICEM_X0.BFFMUX.XOR !30_24 30_25 !30_26 !30_27
CLBLM_R.SLICEM_X0.BFFMUX.F8 !30_24 !30_25 30_26 30_27
CLBLM_R.SLICEM_X0.BFFMUX.O5 !30_25 !30_26 30_24 30_27
CLBLM_R.SLICEM_X0.BFFMUX.O6 !30_25 !30_26 !30_27 30_24
CLBLM_R.SLICEM_X0.BFFMUX.XOR !30_24 !30_26 !30_27 30_25
CLBLM_R.SLICEM_X0.BFFMUX.O5 30_24 !30_25 !30_26 30_27
CLBLM_R.SLICEM_X0.BFFMUX.O6 30_24 !30_25 !30_26 !30_27
CLBLM_R.SLICEM_X0.BLUT.DI1MUX.BI 00_20
CLBLM_R.SLICEM_X0.BLUT.INIT[00] 34_31
CLBLM_R.SLICEM_X0.BLUT.INIT[01] 35_31
@ -503,28 +503,24 @@ CLBLM_R.SLICEM_X0.BLUT.RAM 31_17
CLBLM_R.SLICEM_X0.BLUT.SMALL 00_24
CLBLM_R.SLICEM_X0.BLUT.SRL 30_17
CLBLM_R.SLICEM_X0.BOUTMUX.B5Q !30_20 !30_21 !30_22 30_23
CLBLM_R.SLICEM_X0.BOUTMUX.CY !30_20 !30_23 30_21 30_22
CLBLM_R.SLICEM_X0.BOUTMUX.CY !30_20 30_21 30_22 !30_23
CLBLM_R.SLICEM_X0.BOUTMUX.XOR !30_20 30_21 !30_22 !30_23
CLBLM_R.SLICEM_X0.BOUTMUX.F8 !30_20 !30_21 30_22 30_23
CLBLM_R.SLICEM_X0.BOUTMUX.O5 !30_21 !30_23 30_20 30_22
CLBLM_R.SLICEM_X0.BOUTMUX.O6 !30_21 !30_22 !30_23 30_20
CLBLM_R.SLICEM_X0.BOUTMUX.XOR !30_20 !30_22 !30_23 30_21
CLBLM_R.SLICEM_X0.BOUTMUX.O5 30_20 !30_21 30_22 !30_23
CLBLM_R.SLICEM_X0.BOUTMUX.O6 30_20 !30_21 !30_22 !30_23
CLBLM_R.SLICEM_X0.C5FF.ZINI 31_41
CLBLM_R.SLICEM_X0.C5FF.ZRST 01_47
CLBLM_R.SLICEM_X0.C5FFMUX.IN_A 31_45
CLBLM_R.SLICEM_X0.C5FFMUX.IN_B 30_39
CLBLM_R.SLICEM_X0.CARRY4.ACY0 30_15
CLBLM_R.SLICEM_X0.CARRY4.BCY0 01_15
CLBLM_R.SLICEM_X0.CARRY4.CCY0 30_48
CLBLM_R.SLICEM_X0.CARRY4.DCY0 30_49
CLBLM_R.SLICEM_X0.CEUSEDMUX 01_39
CLBLM_R.SLICEM_X0.CFF.ZINI 31_33
CLBLM_R.SLICEM_X0.CFF.ZRST 30_33
CLBLM_R.SLICEM_X0.CFFMUX.CX !30_35 !30_37 !30_38 30_36
CLBLM_R.SLICEM_X0.CFFMUX.CY !30_36 !30_38 30_35 30_37
CLBLM_R.SLICEM_X0.CFFMUX.F7 !30_37 !30_38 30_35 30_36
CLBLM_R.SLICEM_X0.CFFMUX.O5 !30_36 !30_37 30_35 30_38
CLBLM_R.SLICEM_X0.CFFMUX.CX !30_35 30_36 !30_37 !30_38
CLBLM_R.SLICEM_X0.CFFMUX.CY 30_35 !30_36 30_37 !30_38
CLBLM_R.SLICEM_X0.CFFMUX.XOR !30_35 !30_36 30_37 !30_38
CLBLM_R.SLICEM_X0.CFFMUX.F7 30_35 30_36 !30_37 !30_38
CLBLM_R.SLICEM_X0.CFFMUX.O5 30_35 !30_36 !30_37 30_38
CLBLM_R.SLICEM_X0.CFFMUX.O6 !30_35 !30_36 !30_37 30_38
CLBLM_R.SLICEM_X0.CFFMUX.XOR !30_35 !30_36 !30_38 30_37
CLBLM_R.SLICEM_X0.CLKINV 01_51
CLBLM_R.SLICEM_X0.CLUT.DI1MUX.CI 01_43
CLBLM_R.SLICEM_X0.CLUT.INIT[00] 34_47
@ -594,23 +590,23 @@ CLBLM_R.SLICEM_X0.CLUT.INIT[63] 33_32
CLBLM_R.SLICEM_X0.CLUT.RAM 31_46
CLBLM_R.SLICEM_X0.CLUT.SMALL 00_28
CLBLM_R.SLICEM_X0.CLUT.SRL 30_46
CLBLM_R.SLICEM_X0.COUTMUX.C5Q !30_40 !30_44 !30_45 30_43
CLBLM_R.SLICEM_X0.COUTMUX.CY !30_43 !30_45 30_40 30_44
CLBLM_R.SLICEM_X0.COUTMUX.F7 !30_44 !30_45 30_40 30_43
CLBLM_R.SLICEM_X0.COUTMUX.O5 !30_43 !30_44 30_40 30_45
CLBLM_R.SLICEM_X0.COUTMUX.C5Q !30_40 30_43 !30_44 !30_45
CLBLM_R.SLICEM_X0.COUTMUX.CY 30_40 !30_43 30_44 !30_45
CLBLM_R.SLICEM_X0.COUTMUX.XOR !30_40 !30_43 30_44 !30_45
CLBLM_R.SLICEM_X0.COUTMUX.F7 30_40 30_43 !30_44 !30_45
CLBLM_R.SLICEM_X0.COUTMUX.O5 30_40 !30_43 !30_44 30_45
CLBLM_R.SLICEM_X0.COUTMUX.O6 !30_40 !30_43 !30_44 30_45
CLBLM_R.SLICEM_X0.COUTMUX.XOR !30_40 !30_43 !30_45 30_44
CLBLM_R.SLICEM_X0.D5FF.ZINI 31_51
CLBLM_R.SLICEM_X0.D5FF.ZRST 01_55
CLBLM_R.SLICEM_X0.D5FFMUX.IN_A 30_55
CLBLM_R.SLICEM_X0.D5FFMUX.IN_B 30_54
CLBLM_R.SLICEM_X0.DFF.ZINI 31_58
CLBLM_R.SLICEM_X0.DFF.ZRST 30_50
CLBLM_R.SLICEM_X0.DFFMUX.CY !30_59 !30_61 30_60 30_62
CLBLM_R.SLICEM_X0.DFFMUX.DX !30_59 !30_60 !30_62 30_61
CLBLM_R.SLICEM_X0.DFFMUX.O5 !30_60 !30_61 30_59 30_62
CLBLM_R.SLICEM_X0.DFFMUX.O6 !30_60 !30_61 !30_62 30_59
CLBLM_R.SLICEM_X0.DFFMUX.XOR !30_59 !30_61 !30_62 30_60
CLBLM_R.SLICEM_X0.DFFMUX.CY !30_59 30_60 !30_61 30_62
CLBLM_R.SLICEM_X0.DFFMUX.DX !30_59 !30_60 30_61 !30_62
CLBLM_R.SLICEM_X0.DFFMUX.XOR !30_59 30_60 !30_61 !30_62
CLBLM_R.SLICEM_X0.DFFMUX.O5 30_59 !30_60 !30_61 30_62
CLBLM_R.SLICEM_X0.DFFMUX.O6 30_59 !30_60 !30_61 !30_62
CLBLM_R.SLICEM_X0.DLUT.INIT[00] 34_63
CLBLM_R.SLICEM_X0.DLUT.INIT[01] 35_63
CLBLM_R.SLICEM_X0.DLUT.INIT[02] 34_62
@ -678,17 +674,21 @@ CLBLM_R.SLICEM_X0.DLUT.INIT[63] 33_48
CLBLM_R.SLICEM_X0.DLUT.RAM 31_47
CLBLM_R.SLICEM_X0.DLUT.SMALL 01_59
CLBLM_R.SLICEM_X0.DLUT.SRL 30_47
CLBLM_R.SLICEM_X0.DOUTMUX.CY !30_56 !30_57 30_51 30_52
CLBLM_R.SLICEM_X0.DOUTMUX.CY 30_51 30_52 !30_56 !30_57
CLBLM_R.SLICEM_X0.DOUTMUX.D5Q !30_51 !30_52 !30_56 30_57
CLBLM_R.SLICEM_X0.DOUTMUX.O5 !30_51 !30_57 30_52 30_56
CLBLM_R.SLICEM_X0.DOUTMUX.O6 !30_51 !30_52 !30_57 30_56
CLBLM_R.SLICEM_X0.DOUTMUX.XOR !30_52 !30_56 !30_57 30_51
CLBLM_R.SLICEM_X0.DOUTMUX.XOR 30_51 !30_52 !30_56 !30_57
CLBLM_R.SLICEM_X0.DOUTMUX.O5 !30_51 30_52 30_56 !30_57
CLBLM_R.SLICEM_X0.DOUTMUX.O6 !30_51 !30_52 30_56 !30_57
CLBLM_R.SLICEM_X0.FFSYNC 00_48
CLBLM_R.SLICEM_X0.LATCH 30_32
CLBLM_R.SLICEM_X0.PRECYINIT.1 !30_13 !30_14 00_12
CLBLM_R.SLICEM_X0.PRECYINIT.1 00_12 !30_13 !30_14
CLBLM_R.SLICEM_X0.PRECYINIT.AX !00_12 !30_13 30_14
CLBLM_R.SLICEM_X0.PRECYINIT.CIN !00_12 !30_14 30_13
CLBLM_R.SLICEM_X0.PRECYINIT.CIN !00_12 30_13 !30_14
CLBLM_R.SLICEM_X0.SRUSEDMUX 01_35
CLBLM_R.SLICEM_X0.WA7USED 00_40
CLBLM_R.SLICEM_X0.WA8USED 01_27
CLBLM_R.SLICEM_X0.WEMUX.CE 01_23
CLBLM_R.SLICEM_X0.CARRY4.ACY0 30_15
CLBLM_R.SLICEM_X0.CARRY4.BCY0 01_15
CLBLM_R.SLICEM_X0.CARRY4.CCY0 30_48
CLBLM_R.SLICEM_X0.CARRY4.DCY0 30_49

196
artix7/segbits_hclk_l.db
View File

@ -1,15 +1,7 @@
HCLK_L.ENABLE_BUFFER.HCLK_CK_BUFHCLK10 00_22
HCLK_L.ENABLE_BUFFER.HCLK_CK_BUFHCLK11 01_22
HCLK_L.ENABLE_BUFFER.HCLK_CK_BUFHCLK8 00_14
HCLK_L.ENABLE_BUFFER.HCLK_CK_BUFHCLK9 01_19
HCLK_L.HCLK_LEAF_CLK_B_BOTL0.HCLK_CK_BUFHCLK10 01_15 04_15
HCLK_L.HCLK_LEAF_CLK_B_BOTL0.HCLK_CK_BUFHCLK11 01_15 03_15
HCLK_L.HCLK_LEAF_CLK_B_BOTL0.HCLK_CK_BUFHCLK8 01_15 04_14
HCLK_L.HCLK_LEAF_CLK_B_BOTL0.HCLK_CK_BUFHCLK9 01_15 03_14
HCLK_L.HCLK_LEAF_CLK_B_BOTL0.HCLK_CK_BUFRCLK0 00_16 04_14
HCLK_L.HCLK_LEAF_CLK_B_BOTL0.HCLK_CK_BUFRCLK1 00_16 03_14
HCLK_L.HCLK_LEAF_CLK_B_BOTL0.HCLK_CK_BUFRCLK2 00_16 04_15
HCLK_L.HCLK_LEAF_CLK_B_BOTL0.HCLK_CK_BUFRCLK3 00_16 03_15
HCLK_L.ENABLE_BUFFER.HCLK_CK_BUFHCLK10 00_22
HCLK_L.ENABLE_BUFFER.HCLK_CK_BUFHCLK11 01_22
HCLK_L.HCLK_LEAF_CLK_B_BOTL0.HCLK_CK_OUTIN_L0 01_14 04_14
HCLK_L.HCLK_LEAF_CLK_B_BOTL0.HCLK_CK_OUTIN_L1 01_14 03_14
HCLK_L.HCLK_LEAF_CLK_B_BOTL0.HCLK_CK_OUTIN_L2 01_14 04_15
@ -18,14 +10,14 @@ HCLK_L.HCLK_LEAF_CLK_B_BOTL0.HCLK_CK_OUTIN_L4 00_15 04_14
HCLK_L.HCLK_LEAF_CLK_B_BOTL0.HCLK_CK_OUTIN_L5 00_15 03_14
HCLK_L.HCLK_LEAF_CLK_B_BOTL0.HCLK_CK_OUTIN_L6 00_15 04_15
HCLK_L.HCLK_LEAF_CLK_B_BOTL0.HCLK_CK_OUTIN_L7 00_15 03_15
HCLK_L.HCLK_LEAF_CLK_B_BOTL1.HCLK_CK_BUFHCLK10 02_15 04_16
HCLK_L.HCLK_LEAF_CLK_B_BOTL1.HCLK_CK_BUFHCLK11 04_16 05_15
HCLK_L.HCLK_LEAF_CLK_B_BOTL1.HCLK_CK_BUFHCLK8 02_14 04_16
HCLK_L.HCLK_LEAF_CLK_B_BOTL1.HCLK_CK_BUFHCLK9 04_16 05_14
HCLK_L.HCLK_LEAF_CLK_B_BOTL1.HCLK_CK_BUFRCLK0 02_14 02_16
HCLK_L.HCLK_LEAF_CLK_B_BOTL1.HCLK_CK_BUFRCLK1 02_16 05_14
HCLK_L.HCLK_LEAF_CLK_B_BOTL1.HCLK_CK_BUFRCLK2 02_15 02_16
HCLK_L.HCLK_LEAF_CLK_B_BOTL1.HCLK_CK_BUFRCLK3 02_16 05_15
HCLK_L.HCLK_LEAF_CLK_B_BOTL0.HCLK_CK_BUFHCLK8 01_15 04_14
HCLK_L.HCLK_LEAF_CLK_B_BOTL0.HCLK_CK_BUFHCLK9 01_15 03_14
HCLK_L.HCLK_LEAF_CLK_B_BOTL0.HCLK_CK_BUFHCLK10 01_15 04_15
HCLK_L.HCLK_LEAF_CLK_B_BOTL0.HCLK_CK_BUFHCLK11 01_15 03_15
HCLK_L.HCLK_LEAF_CLK_B_BOTL0.HCLK_CK_BUFRCLK0 00_16 04_14
HCLK_L.HCLK_LEAF_CLK_B_BOTL0.HCLK_CK_BUFRCLK1 00_16 03_14
HCLK_L.HCLK_LEAF_CLK_B_BOTL0.HCLK_CK_BUFRCLK2 00_16 04_15
HCLK_L.HCLK_LEAF_CLK_B_BOTL0.HCLK_CK_BUFRCLK3 00_16 03_15
HCLK_L.HCLK_LEAF_CLK_B_BOTL1.HCLK_CK_OUTIN_L0 02_14 03_16
HCLK_L.HCLK_LEAF_CLK_B_BOTL1.HCLK_CK_OUTIN_L1 03_16 05_14
HCLK_L.HCLK_LEAF_CLK_B_BOTL1.HCLK_CK_OUTIN_L2 02_15 03_16
@ -34,14 +26,14 @@ HCLK_L.HCLK_LEAF_CLK_B_BOTL1.HCLK_CK_OUTIN_L4 02_14 05_16
HCLK_L.HCLK_LEAF_CLK_B_BOTL1.HCLK_CK_OUTIN_L5 05_14 05_16
HCLK_L.HCLK_LEAF_CLK_B_BOTL1.HCLK_CK_OUTIN_L6 02_15 05_16
HCLK_L.HCLK_LEAF_CLK_B_BOTL1.HCLK_CK_OUTIN_L7 05_15 05_16
HCLK_L.HCLK_LEAF_CLK_B_BOTL2.HCLK_CK_BUFHCLK10 00_17 05_18
HCLK_L.HCLK_LEAF_CLK_B_BOTL2.HCLK_CK_BUFHCLK11 00_17 02_18
HCLK_L.HCLK_LEAF_CLK_B_BOTL2.HCLK_CK_BUFHCLK8 00_17 05_19
HCLK_L.HCLK_LEAF_CLK_B_BOTL2.HCLK_CK_BUFHCLK9 00_17 02_19
HCLK_L.HCLK_LEAF_CLK_B_BOTL2.HCLK_CK_BUFRCLK0 01_16 05_19
HCLK_L.HCLK_LEAF_CLK_B_BOTL2.HCLK_CK_BUFRCLK1 01_16 02_19
HCLK_L.HCLK_LEAF_CLK_B_BOTL2.HCLK_CK_BUFRCLK2 01_16 05_18
HCLK_L.HCLK_LEAF_CLK_B_BOTL2.HCLK_CK_BUFRCLK3 01_16 02_18
HCLK_L.HCLK_LEAF_CLK_B_BOTL1.HCLK_CK_BUFHCLK8 02_14 04_16
HCLK_L.HCLK_LEAF_CLK_B_BOTL1.HCLK_CK_BUFHCLK9 04_16 05_14
HCLK_L.HCLK_LEAF_CLK_B_BOTL1.HCLK_CK_BUFHCLK10 02_15 04_16
HCLK_L.HCLK_LEAF_CLK_B_BOTL1.HCLK_CK_BUFHCLK11 04_16 05_15
HCLK_L.HCLK_LEAF_CLK_B_BOTL1.HCLK_CK_BUFRCLK0 02_14 02_16
HCLK_L.HCLK_LEAF_CLK_B_BOTL1.HCLK_CK_BUFRCLK1 02_16 05_14
HCLK_L.HCLK_LEAF_CLK_B_BOTL1.HCLK_CK_BUFRCLK2 02_15 02_16
HCLK_L.HCLK_LEAF_CLK_B_BOTL1.HCLK_CK_BUFRCLK3 02_16 05_15
HCLK_L.HCLK_LEAF_CLK_B_BOTL2.HCLK_CK_OUTIN_L0 00_18 05_19
HCLK_L.HCLK_LEAF_CLK_B_BOTL2.HCLK_CK_OUTIN_L1 00_18 02_19
HCLK_L.HCLK_LEAF_CLK_B_BOTL2.HCLK_CK_OUTIN_L2 00_18 05_18
@ -50,14 +42,14 @@ HCLK_L.HCLK_LEAF_CLK_B_BOTL2.HCLK_CK_OUTIN_L4 01_17 05_19
HCLK_L.HCLK_LEAF_CLK_B_BOTL2.HCLK_CK_OUTIN_L5 01_17 02_19
HCLK_L.HCLK_LEAF_CLK_B_BOTL2.HCLK_CK_OUTIN_L6 01_17 05_18
HCLK_L.HCLK_LEAF_CLK_B_BOTL2.HCLK_CK_OUTIN_L7 01_17 02_18
HCLK_L.HCLK_LEAF_CLK_B_BOTL3.HCLK_CK_BUFHCLK10 03_18 05_17
HCLK_L.HCLK_LEAF_CLK_B_BOTL3.HCLK_CK_BUFHCLK11 04_18 05_17
HCLK_L.HCLK_LEAF_CLK_B_BOTL3.HCLK_CK_BUFHCLK8 03_19 05_17
HCLK_L.HCLK_LEAF_CLK_B_BOTL3.HCLK_CK_BUFHCLK9 04_19 05_17
HCLK_L.HCLK_LEAF_CLK_B_BOTL3.HCLK_CK_BUFRCLK0 03_17 03_19
HCLK_L.HCLK_LEAF_CLK_B_BOTL3.HCLK_CK_BUFRCLK1 03_17 04_19
HCLK_L.HCLK_LEAF_CLK_B_BOTL3.HCLK_CK_BUFRCLK2 03_17 03_18
HCLK_L.HCLK_LEAF_CLK_B_BOTL3.HCLK_CK_BUFRCLK3 03_17 04_18
HCLK_L.HCLK_LEAF_CLK_B_BOTL2.HCLK_CK_BUFHCLK8 00_17 05_19
HCLK_L.HCLK_LEAF_CLK_B_BOTL2.HCLK_CK_BUFHCLK9 00_17 02_19
HCLK_L.HCLK_LEAF_CLK_B_BOTL2.HCLK_CK_BUFHCLK10 00_17 05_18
HCLK_L.HCLK_LEAF_CLK_B_BOTL2.HCLK_CK_BUFHCLK11 00_17 02_18
HCLK_L.HCLK_LEAF_CLK_B_BOTL2.HCLK_CK_BUFRCLK0 01_16 05_19
HCLK_L.HCLK_LEAF_CLK_B_BOTL2.HCLK_CK_BUFRCLK1 01_16 02_19
HCLK_L.HCLK_LEAF_CLK_B_BOTL2.HCLK_CK_BUFRCLK2 01_16 05_18
HCLK_L.HCLK_LEAF_CLK_B_BOTL2.HCLK_CK_BUFRCLK3 01_16 02_18
HCLK_L.HCLK_LEAF_CLK_B_BOTL3.HCLK_CK_OUTIN_L0 02_17 03_19
HCLK_L.HCLK_LEAF_CLK_B_BOTL3.HCLK_CK_OUTIN_L1 02_17 04_19
HCLK_L.HCLK_LEAF_CLK_B_BOTL3.HCLK_CK_OUTIN_L2 02_17 03_18
@ -66,14 +58,14 @@ HCLK_L.HCLK_LEAF_CLK_B_BOTL3.HCLK_CK_OUTIN_L4 03_19 04_17
HCLK_L.HCLK_LEAF_CLK_B_BOTL3.HCLK_CK_OUTIN_L5 04_17 04_19
HCLK_L.HCLK_LEAF_CLK_B_BOTL3.HCLK_CK_OUTIN_L6 03_18 04_17
HCLK_L.HCLK_LEAF_CLK_B_BOTL3.HCLK_CK_OUTIN_L7 04_17 04_18
HCLK_L.HCLK_LEAF_CLK_B_BOTL4.HCLK_CK_BUFHCLK10 00_21 04_21
HCLK_L.HCLK_LEAF_CLK_B_BOTL4.HCLK_CK_BUFHCLK11 00_21 03_21
HCLK_L.HCLK_LEAF_CLK_B_BOTL4.HCLK_CK_BUFHCLK8 00_21 04_20
HCLK_L.HCLK_LEAF_CLK_B_BOTL4.HCLK_CK_BUFHCLK9 00_21 03_20
HCLK_L.HCLK_LEAF_CLK_B_BOTL4.HCLK_CK_BUFRCLK0 01_21 04_20
HCLK_L.HCLK_LEAF_CLK_B_BOTL4.HCLK_CK_BUFRCLK1 01_21 03_20
HCLK_L.HCLK_LEAF_CLK_B_BOTL4.HCLK_CK_BUFRCLK2 01_21 04_21
HCLK_L.HCLK_LEAF_CLK_B_BOTL4.HCLK_CK_BUFRCLK3 01_21 03_21
HCLK_L.HCLK_LEAF_CLK_B_BOTL3.HCLK_CK_BUFHCLK8 03_19 05_17
HCLK_L.HCLK_LEAF_CLK_B_BOTL3.HCLK_CK_BUFHCLK9 04_19 05_17
HCLK_L.HCLK_LEAF_CLK_B_BOTL3.HCLK_CK_BUFHCLK10 03_18 05_17
HCLK_L.HCLK_LEAF_CLK_B_BOTL3.HCLK_CK_BUFHCLK11 04_18 05_17
HCLK_L.HCLK_LEAF_CLK_B_BOTL3.HCLK_CK_BUFRCLK0 03_17 03_19
HCLK_L.HCLK_LEAF_CLK_B_BOTL3.HCLK_CK_BUFRCLK1 03_17 04_19
HCLK_L.HCLK_LEAF_CLK_B_BOTL3.HCLK_CK_BUFRCLK2 03_17 03_18
HCLK_L.HCLK_LEAF_CLK_B_BOTL3.HCLK_CK_BUFRCLK3 03_17 04_18
HCLK_L.HCLK_LEAF_CLK_B_BOTL4.HCLK_CK_OUTIN_L0 00_20 04_20
HCLK_L.HCLK_LEAF_CLK_B_BOTL4.HCLK_CK_OUTIN_L1 00_20 03_20
HCLK_L.HCLK_LEAF_CLK_B_BOTL4.HCLK_CK_OUTIN_L2 00_20 04_21
@ -82,14 +74,14 @@ HCLK_L.HCLK_LEAF_CLK_B_BOTL4.HCLK_CK_OUTIN_L4 01_20 04_20
HCLK_L.HCLK_LEAF_CLK_B_BOTL4.HCLK_CK_OUTIN_L5 01_20 03_20
HCLK_L.HCLK_LEAF_CLK_B_BOTL4.HCLK_CK_OUTIN_L6 01_20 04_21
HCLK_L.HCLK_LEAF_CLK_B_BOTL4.HCLK_CK_OUTIN_L7 01_20 03_21
HCLK_L.HCLK_LEAF_CLK_B_BOTL5.HCLK_CK_BUFHCLK10 02_21 04_22
HCLK_L.HCLK_LEAF_CLK_B_BOTL5.HCLK_CK_BUFHCLK11 04_22 05_21
HCLK_L.HCLK_LEAF_CLK_B_BOTL5.HCLK_CK_BUFHCLK8 02_20 04_22
HCLK_L.HCLK_LEAF_CLK_B_BOTL5.HCLK_CK_BUFHCLK9 04_22 05_20
HCLK_L.HCLK_LEAF_CLK_B_BOTL5.HCLK_CK_BUFRCLK0 02_20 02_22
HCLK_L.HCLK_LEAF_CLK_B_BOTL5.HCLK_CK_BUFRCLK1 02_22 05_20
HCLK_L.HCLK_LEAF_CLK_B_BOTL5.HCLK_CK_BUFRCLK2 02_21 02_22
HCLK_L.HCLK_LEAF_CLK_B_BOTL5.HCLK_CK_BUFRCLK3 02_22 05_21
HCLK_L.HCLK_LEAF_CLK_B_BOTL4.HCLK_CK_BUFHCLK8 00_21 04_20
HCLK_L.HCLK_LEAF_CLK_B_BOTL4.HCLK_CK_BUFHCLK9 00_21 03_20
HCLK_L.HCLK_LEAF_CLK_B_BOTL4.HCLK_CK_BUFHCLK10 00_21 04_21
HCLK_L.HCLK_LEAF_CLK_B_BOTL4.HCLK_CK_BUFHCLK11 00_21 03_21
HCLK_L.HCLK_LEAF_CLK_B_BOTL4.HCLK_CK_BUFRCLK0 01_21 04_20
HCLK_L.HCLK_LEAF_CLK_B_BOTL4.HCLK_CK_BUFRCLK1 01_21 03_20
HCLK_L.HCLK_LEAF_CLK_B_BOTL4.HCLK_CK_BUFRCLK2 01_21 04_21
HCLK_L.HCLK_LEAF_CLK_B_BOTL4.HCLK_CK_BUFRCLK3 01_21 03_21
HCLK_L.HCLK_LEAF_CLK_B_BOTL5.HCLK_CK_OUTIN_L0 02_20 03_22
HCLK_L.HCLK_LEAF_CLK_B_BOTL5.HCLK_CK_OUTIN_L1 03_22 05_20
HCLK_L.HCLK_LEAF_CLK_B_BOTL5.HCLK_CK_OUTIN_L2 02_21 03_22
@ -98,14 +90,14 @@ HCLK_L.HCLK_LEAF_CLK_B_BOTL5.HCLK_CK_OUTIN_L4 02_20 05_22
HCLK_L.HCLK_LEAF_CLK_B_BOTL5.HCLK_CK_OUTIN_L5 05_20 05_22
HCLK_L.HCLK_LEAF_CLK_B_BOTL5.HCLK_CK_OUTIN_L6 02_21 05_22
HCLK_L.HCLK_LEAF_CLK_B_BOTL5.HCLK_CK_OUTIN_L7 05_21 05_22
HCLK_L.HCLK_LEAF_CLK_B_TOPL0.HCLK_CK_BUFHCLK10 01_29 05_30
HCLK_L.HCLK_LEAF_CLK_B_TOPL0.HCLK_CK_BUFHCLK11 01_29 02_30
HCLK_L.HCLK_LEAF_CLK_B_TOPL0.HCLK_CK_BUFHCLK8 01_29 05_31
HCLK_L.HCLK_LEAF_CLK_B_TOPL0.HCLK_CK_BUFHCLK9 01_29 02_31
HCLK_L.HCLK_LEAF_CLK_B_TOPL0.HCLK_CK_BUFRCLK0 00_29 05_31
HCLK_L.HCLK_LEAF_CLK_B_TOPL0.HCLK_CK_BUFRCLK1 00_29 02_31
HCLK_L.HCLK_LEAF_CLK_B_TOPL0.HCLK_CK_BUFRCLK2 00_29 05_30
HCLK_L.HCLK_LEAF_CLK_B_TOPL0.HCLK_CK_BUFRCLK3 00_29 02_30
HCLK_L.HCLK_LEAF_CLK_B_BOTL5.HCLK_CK_BUFHCLK8 02_20 04_22
HCLK_L.HCLK_LEAF_CLK_B_BOTL5.HCLK_CK_BUFHCLK9 04_22 05_20
HCLK_L.HCLK_LEAF_CLK_B_BOTL5.HCLK_CK_BUFHCLK10 02_21 04_22
HCLK_L.HCLK_LEAF_CLK_B_BOTL5.HCLK_CK_BUFHCLK11 04_22 05_21
HCLK_L.HCLK_LEAF_CLK_B_BOTL5.HCLK_CK_BUFRCLK0 02_20 02_22
HCLK_L.HCLK_LEAF_CLK_B_BOTL5.HCLK_CK_BUFRCLK1 02_22 05_20
HCLK_L.HCLK_LEAF_CLK_B_BOTL5.HCLK_CK_BUFRCLK2 02_21 02_22
HCLK_L.HCLK_LEAF_CLK_B_BOTL5.HCLK_CK_BUFRCLK3 02_22 05_21
HCLK_L.HCLK_LEAF_CLK_B_TOPL0.HCLK_CK_OUTIN_L0 01_30 05_31
HCLK_L.HCLK_LEAF_CLK_B_TOPL0.HCLK_CK_OUTIN_L1 01_30 02_31
HCLK_L.HCLK_LEAF_CLK_B_TOPL0.HCLK_CK_OUTIN_L2 01_30 05_30
@ -114,14 +106,14 @@ HCLK_L.HCLK_LEAF_CLK_B_TOPL0.HCLK_CK_OUTIN_L4 00_30 05_31
HCLK_L.HCLK_LEAF_CLK_B_TOPL0.HCLK_CK_OUTIN_L5 00_30 02_31
HCLK_L.HCLK_LEAF_CLK_B_TOPL0.HCLK_CK_OUTIN_L6 00_30 05_30
HCLK_L.HCLK_LEAF_CLK_B_TOPL0.HCLK_CK_OUTIN_L7 00_30 02_30
HCLK_L.HCLK_LEAF_CLK_B_TOPL1.HCLK_CK_BUFHCLK10 03_30 05_29
HCLK_L.HCLK_LEAF_CLK_B_TOPL1.HCLK_CK_BUFHCLK11 04_30 05_29
HCLK_L.HCLK_LEAF_CLK_B_TOPL1.HCLK_CK_BUFHCLK8 03_31 05_29
HCLK_L.HCLK_LEAF_CLK_B_TOPL1.HCLK_CK_BUFHCLK9 04_31 05_29
HCLK_L.HCLK_LEAF_CLK_B_TOPL1.HCLK_CK_BUFRCLK0 03_29 03_31
HCLK_L.HCLK_LEAF_CLK_B_TOPL1.HCLK_CK_BUFRCLK1 03_29 04_31
HCLK_L.HCLK_LEAF_CLK_B_TOPL1.HCLK_CK_BUFRCLK2 03_29 03_30
HCLK_L.HCLK_LEAF_CLK_B_TOPL1.HCLK_CK_BUFRCLK3 03_29 04_30
HCLK_L.HCLK_LEAF_CLK_B_TOPL0.HCLK_CK_BUFHCLK8 01_29 05_31
HCLK_L.HCLK_LEAF_CLK_B_TOPL0.HCLK_CK_BUFHCLK9 01_29 02_31
HCLK_L.HCLK_LEAF_CLK_B_TOPL0.HCLK_CK_BUFHCLK10 01_29 05_30
HCLK_L.HCLK_LEAF_CLK_B_TOPL0.HCLK_CK_BUFHCLK11 01_29 02_30
HCLK_L.HCLK_LEAF_CLK_B_TOPL0.HCLK_CK_BUFRCLK0 00_29 05_31
HCLK_L.HCLK_LEAF_CLK_B_TOPL0.HCLK_CK_BUFRCLK1 00_29 02_31
HCLK_L.HCLK_LEAF_CLK_B_TOPL0.HCLK_CK_BUFRCLK2 00_29 05_30
HCLK_L.HCLK_LEAF_CLK_B_TOPL0.HCLK_CK_BUFRCLK3 00_29 02_30
HCLK_L.HCLK_LEAF_CLK_B_TOPL1.HCLK_CK_OUTIN_L0 02_29 03_31
HCLK_L.HCLK_LEAF_CLK_B_TOPL1.HCLK_CK_OUTIN_L1 02_29 04_31
HCLK_L.HCLK_LEAF_CLK_B_TOPL1.HCLK_CK_OUTIN_L2 02_29 03_30
@ -130,14 +122,14 @@ HCLK_L.HCLK_LEAF_CLK_B_TOPL1.HCLK_CK_OUTIN_L4 03_31 04_29
HCLK_L.HCLK_LEAF_CLK_B_TOPL1.HCLK_CK_OUTIN_L5 04_29 04_31
HCLK_L.HCLK_LEAF_CLK_B_TOPL1.HCLK_CK_OUTIN_L6 03_30 04_29
HCLK_L.HCLK_LEAF_CLK_B_TOPL1.HCLK_CK_OUTIN_L7 04_29 04_30
HCLK_L.HCLK_LEAF_CLK_B_TOPL2.HCLK_CK_BUFHCLK10 00_28 04_27
HCLK_L.HCLK_LEAF_CLK_B_TOPL2.HCLK_CK_BUFHCLK11 00_28 03_27
HCLK_L.HCLK_LEAF_CLK_B_TOPL2.HCLK_CK_BUFHCLK8 00_28 04_26
HCLK_L.HCLK_LEAF_CLK_B_TOPL2.HCLK_CK_BUFHCLK9 00_28 03_26
HCLK_L.HCLK_LEAF_CLK_B_TOPL2.HCLK_CK_BUFRCLK0 01_28 04_26
HCLK_L.HCLK_LEAF_CLK_B_TOPL2.HCLK_CK_BUFRCLK1 01_28 03_26
HCLK_L.HCLK_LEAF_CLK_B_TOPL2.HCLK_CK_BUFRCLK2 01_28 04_27
HCLK_L.HCLK_LEAF_CLK_B_TOPL2.HCLK_CK_BUFRCLK3 01_28 03_27
HCLK_L.HCLK_LEAF_CLK_B_TOPL1.HCLK_CK_BUFHCLK8 03_31 05_29
HCLK_L.HCLK_LEAF_CLK_B_TOPL1.HCLK_CK_BUFHCLK9 04_31 05_29
HCLK_L.HCLK_LEAF_CLK_B_TOPL1.HCLK_CK_BUFHCLK10 03_30 05_29
HCLK_L.HCLK_LEAF_CLK_B_TOPL1.HCLK_CK_BUFHCLK11 04_30 05_29
HCLK_L.HCLK_LEAF_CLK_B_TOPL1.HCLK_CK_BUFRCLK0 03_29 03_31
HCLK_L.HCLK_LEAF_CLK_B_TOPL1.HCLK_CK_BUFRCLK1 03_29 04_31
HCLK_L.HCLK_LEAF_CLK_B_TOPL1.HCLK_CK_BUFRCLK2 03_29 03_30
HCLK_L.HCLK_LEAF_CLK_B_TOPL1.HCLK_CK_BUFRCLK3 03_29 04_30
HCLK_L.HCLK_LEAF_CLK_B_TOPL2.HCLK_CK_OUTIN_L0 00_26 04_26
HCLK_L.HCLK_LEAF_CLK_B_TOPL2.HCLK_CK_OUTIN_L1 00_26 03_26
HCLK_L.HCLK_LEAF_CLK_B_TOPL2.HCLK_CK_OUTIN_L2 00_26 04_27
@ -146,14 +138,14 @@ HCLK_L.HCLK_LEAF_CLK_B_TOPL2.HCLK_CK_OUTIN_L4 01_26 04_26
HCLK_L.HCLK_LEAF_CLK_B_TOPL2.HCLK_CK_OUTIN_L5 01_26 03_26
HCLK_L.HCLK_LEAF_CLK_B_TOPL2.HCLK_CK_OUTIN_L6 01_26 04_27
HCLK_L.HCLK_LEAF_CLK_B_TOPL2.HCLK_CK_OUTIN_L7 01_26 03_27
HCLK_L.HCLK_LEAF_CLK_B_TOPL3.HCLK_CK_BUFHCLK10 02_27 04_28
HCLK_L.HCLK_LEAF_CLK_B_TOPL3.HCLK_CK_BUFHCLK11 04_28 05_27
HCLK_L.HCLK_LEAF_CLK_B_TOPL3.HCLK_CK_BUFHCLK8 02_26 04_28
HCLK_L.HCLK_LEAF_CLK_B_TOPL3.HCLK_CK_BUFHCLK9 04_28 05_26
HCLK_L.HCLK_LEAF_CLK_B_TOPL3.HCLK_CK_BUFRCLK0 02_26 02_28
HCLK_L.HCLK_LEAF_CLK_B_TOPL3.HCLK_CK_BUFRCLK1 02_28 05_26
HCLK_L.HCLK_LEAF_CLK_B_TOPL3.HCLK_CK_BUFRCLK2 02_27 02_28
HCLK_L.HCLK_LEAF_CLK_B_TOPL3.HCLK_CK_BUFRCLK3 02_28 05_27
HCLK_L.HCLK_LEAF_CLK_B_TOPL2.HCLK_CK_BUFHCLK8 00_28 04_26
HCLK_L.HCLK_LEAF_CLK_B_TOPL2.HCLK_CK_BUFHCLK9 00_28 03_26
HCLK_L.HCLK_LEAF_CLK_B_TOPL2.HCLK_CK_BUFHCLK10 00_28 04_27
HCLK_L.HCLK_LEAF_CLK_B_TOPL2.HCLK_CK_BUFHCLK11 00_28 03_27
HCLK_L.HCLK_LEAF_CLK_B_TOPL2.HCLK_CK_BUFRCLK0 01_28 04_26
HCLK_L.HCLK_LEAF_CLK_B_TOPL2.HCLK_CK_BUFRCLK1 01_28 03_26
HCLK_L.HCLK_LEAF_CLK_B_TOPL2.HCLK_CK_BUFRCLK2 01_28 04_27
HCLK_L.HCLK_LEAF_CLK_B_TOPL2.HCLK_CK_BUFRCLK3 01_28 03_27
HCLK_L.HCLK_LEAF_CLK_B_TOPL3.HCLK_CK_OUTIN_L0 02_26 03_28
HCLK_L.HCLK_LEAF_CLK_B_TOPL3.HCLK_CK_OUTIN_L1 03_28 05_26
HCLK_L.HCLK_LEAF_CLK_B_TOPL3.HCLK_CK_OUTIN_L2 02_27 03_28
@ -162,14 +154,14 @@ HCLK_L.HCLK_LEAF_CLK_B_TOPL3.HCLK_CK_OUTIN_L4 02_26 05_28
HCLK_L.HCLK_LEAF_CLK_B_TOPL3.HCLK_CK_OUTIN_L5 05_26 05_28
HCLK_L.HCLK_LEAF_CLK_B_TOPL3.HCLK_CK_OUTIN_L6 02_27 05_28
HCLK_L.HCLK_LEAF_CLK_B_TOPL3.HCLK_CK_OUTIN_L7 05_27 05_28
HCLK_L.HCLK_LEAF_CLK_B_TOPL4.HCLK_CK_BUFHCLK10 01_24 05_24
HCLK_L.HCLK_LEAF_CLK_B_TOPL4.HCLK_CK_BUFHCLK11 01_24 02_24
HCLK_L.HCLK_LEAF_CLK_B_TOPL4.HCLK_CK_BUFHCLK8 01_24 05_25
HCLK_L.HCLK_LEAF_CLK_B_TOPL4.HCLK_CK_BUFHCLK9 01_24 02_25
HCLK_L.HCLK_LEAF_CLK_B_TOPL4.HCLK_CK_BUFRCLK0 00_24 05_25
HCLK_L.HCLK_LEAF_CLK_B_TOPL4.HCLK_CK_BUFRCLK1 00_24 02_25
HCLK_L.HCLK_LEAF_CLK_B_TOPL4.HCLK_CK_BUFRCLK2 00_24 05_24
HCLK_L.HCLK_LEAF_CLK_B_TOPL4.HCLK_CK_BUFRCLK3 00_24 02_24
HCLK_L.HCLK_LEAF_CLK_B_TOPL3.HCLK_CK_BUFHCLK8 02_26 04_28
HCLK_L.HCLK_LEAF_CLK_B_TOPL3.HCLK_CK_BUFHCLK9 04_28 05_26
HCLK_L.HCLK_LEAF_CLK_B_TOPL3.HCLK_CK_BUFHCLK10 02_27 04_28
HCLK_L.HCLK_LEAF_CLK_B_TOPL3.HCLK_CK_BUFHCLK11 04_28 05_27
HCLK_L.HCLK_LEAF_CLK_B_TOPL3.HCLK_CK_BUFRCLK0 02_26 02_28
HCLK_L.HCLK_LEAF_CLK_B_TOPL3.HCLK_CK_BUFRCLK1 02_28 05_26
HCLK_L.HCLK_LEAF_CLK_B_TOPL3.HCLK_CK_BUFRCLK2 02_27 02_28
HCLK_L.HCLK_LEAF_CLK_B_TOPL3.HCLK_CK_BUFRCLK3 02_28 05_27
HCLK_L.HCLK_LEAF_CLK_B_TOPL4.HCLK_CK_OUTIN_L0 01_25 05_25
HCLK_L.HCLK_LEAF_CLK_B_TOPL4.HCLK_CK_OUTIN_L1 01_25 02_25
HCLK_L.HCLK_LEAF_CLK_B_TOPL4.HCLK_CK_OUTIN_L2 01_25 05_24
@ -178,14 +170,14 @@ HCLK_L.HCLK_LEAF_CLK_B_TOPL4.HCLK_CK_OUTIN_L4 00_25 05_25
HCLK_L.HCLK_LEAF_CLK_B_TOPL4.HCLK_CK_OUTIN_L5 00_25 02_25
HCLK_L.HCLK_LEAF_CLK_B_TOPL4.HCLK_CK_OUTIN_L6 00_25 05_24
HCLK_L.HCLK_LEAF_CLK_B_TOPL4.HCLK_CK_OUTIN_L7 00_25 02_24
HCLK_L.HCLK_LEAF_CLK_B_TOPL5.HCLK_CK_BUFHCLK10 03_24 05_23
HCLK_L.HCLK_LEAF_CLK_B_TOPL5.HCLK_CK_BUFHCLK11 04_24 05_23
HCLK_L.HCLK_LEAF_CLK_B_TOPL5.HCLK_CK_BUFHCLK8 03_25 05_23
HCLK_L.HCLK_LEAF_CLK_B_TOPL5.HCLK_CK_BUFHCLK9 04_25 05_23
HCLK_L.HCLK_LEAF_CLK_B_TOPL5.HCLK_CK_BUFRCLK0 03_23 03_25
HCLK_L.HCLK_LEAF_CLK_B_TOPL5.HCLK_CK_BUFRCLK1 03_23 04_25
HCLK_L.HCLK_LEAF_CLK_B_TOPL5.HCLK_CK_BUFRCLK2 03_23 03_24
HCLK_L.HCLK_LEAF_CLK_B_TOPL5.HCLK_CK_BUFRCLK3 03_23 04_24
HCLK_L.HCLK_LEAF_CLK_B_TOPL4.HCLK_CK_BUFHCLK8 01_24 05_25
HCLK_L.HCLK_LEAF_CLK_B_TOPL4.HCLK_CK_BUFHCLK9 01_24 02_25
HCLK_L.HCLK_LEAF_CLK_B_TOPL4.HCLK_CK_BUFHCLK10 01_24 05_24
HCLK_L.HCLK_LEAF_CLK_B_TOPL4.HCLK_CK_BUFHCLK11 01_24 02_24
HCLK_L.HCLK_LEAF_CLK_B_TOPL4.HCLK_CK_BUFRCLK0 00_24 05_25
HCLK_L.HCLK_LEAF_CLK_B_TOPL4.HCLK_CK_BUFRCLK1 00_24 02_25
HCLK_L.HCLK_LEAF_CLK_B_TOPL4.HCLK_CK_BUFRCLK2 00_24 05_24
HCLK_L.HCLK_LEAF_CLK_B_TOPL4.HCLK_CK_BUFRCLK3 00_24 02_24
HCLK_L.HCLK_LEAF_CLK_B_TOPL5.HCLK_CK_OUTIN_L0 02_23 03_25
HCLK_L.HCLK_LEAF_CLK_B_TOPL5.HCLK_CK_OUTIN_L1 02_23 04_25
HCLK_L.HCLK_LEAF_CLK_B_TOPL5.HCLK_CK_OUTIN_L2 02_23 03_24
@ -194,3 +186,11 @@ HCLK_L.HCLK_LEAF_CLK_B_TOPL5.HCLK_CK_OUTIN_L4 03_25 04_23
HCLK_L.HCLK_LEAF_CLK_B_TOPL5.HCLK_CK_OUTIN_L5 04_23 04_25
HCLK_L.HCLK_LEAF_CLK_B_TOPL5.HCLK_CK_OUTIN_L6 03_24 04_23
HCLK_L.HCLK_LEAF_CLK_B_TOPL5.HCLK_CK_OUTIN_L7 04_23 04_24
HCLK_L.HCLK_LEAF_CLK_B_TOPL5.HCLK_CK_BUFHCLK8 03_25 05_23
HCLK_L.HCLK_LEAF_CLK_B_TOPL5.HCLK_CK_BUFHCLK9 04_25 05_23
HCLK_L.HCLK_LEAF_CLK_B_TOPL5.HCLK_CK_BUFHCLK10 03_24 05_23
HCLK_L.HCLK_LEAF_CLK_B_TOPL5.HCLK_CK_BUFHCLK11 04_24 05_23
HCLK_L.HCLK_LEAF_CLK_B_TOPL5.HCLK_CK_BUFRCLK0 03_23 03_25
HCLK_L.HCLK_LEAF_CLK_B_TOPL5.HCLK_CK_BUFRCLK1 03_23 04_25
HCLK_L.HCLK_LEAF_CLK_B_TOPL5.HCLK_CK_BUFRCLK2 03_23 03_24
HCLK_L.HCLK_LEAF_CLK_B_TOPL5.HCLK_CK_BUFRCLK3 03_23 04_24

192
artix7/segbits_hclk_r.db
View File

@ -6,14 +6,6 @@ HCLK_R.ENABLE_BUFFER.HCLK_CK_BUFHCLK4 00_23
HCLK_R.ENABLE_BUFFER.HCLK_CK_BUFHCLK5 01_23
HCLK_R.ENABLE_BUFFER.HCLK_CK_BUFHCLK6 00_31
HCLK_R.ENABLE_BUFFER.HCLK_CK_BUFHCLK7 01_31
HCLK_R.HCLK_LEAF_CLK_B_BOT0.HCLK_CK_BUFHCLK0 01_14 04_14
HCLK_R.HCLK_LEAF_CLK_B_BOT0.HCLK_CK_BUFHCLK1 01_14 03_14
HCLK_R.HCLK_LEAF_CLK_B_BOT0.HCLK_CK_BUFHCLK2 01_14 04_15
HCLK_R.HCLK_LEAF_CLK_B_BOT0.HCLK_CK_BUFHCLK3 01_14 03_15
HCLK_R.HCLK_LEAF_CLK_B_BOT0.HCLK_CK_BUFHCLK4 00_15 04_14
HCLK_R.HCLK_LEAF_CLK_B_BOT0.HCLK_CK_BUFHCLK5 00_15 03_14
HCLK_R.HCLK_LEAF_CLK_B_BOT0.HCLK_CK_BUFHCLK6 00_15 04_15
HCLK_R.HCLK_LEAF_CLK_B_BOT0.HCLK_CK_BUFHCLK7 00_15 03_15
HCLK_R.HCLK_LEAF_CLK_B_BOT0.HCLK_CK_OUTIN_R0 00_16 04_14
HCLK_R.HCLK_LEAF_CLK_B_BOT0.HCLK_CK_OUTIN_R1 00_16 03_14
HCLK_R.HCLK_LEAF_CLK_B_BOT0.HCLK_CK_OUTIN_R2 00_16 04_15
@ -22,14 +14,14 @@ HCLK_R.HCLK_LEAF_CLK_B_BOT0.HCLK_CK_OUTIN_R4 01_15 04_14
HCLK_R.HCLK_LEAF_CLK_B_BOT0.HCLK_CK_OUTIN_R5 01_15 03_14
HCLK_R.HCLK_LEAF_CLK_B_BOT0.HCLK_CK_OUTIN_R6 01_15 04_15
HCLK_R.HCLK_LEAF_CLK_B_BOT0.HCLK_CK_OUTIN_R7 01_15 03_15
HCLK_R.HCLK_LEAF_CLK_B_BOT1.HCLK_CK_BUFHCLK0 02_14 03_16
HCLK_R.HCLK_LEAF_CLK_B_BOT1.HCLK_CK_BUFHCLK1 03_16 05_14
HCLK_R.HCLK_LEAF_CLK_B_BOT1.HCLK_CK_BUFHCLK2 02_15 03_16
HCLK_R.HCLK_LEAF_CLK_B_BOT1.HCLK_CK_BUFHCLK3 03_16 05_15
HCLK_R.HCLK_LEAF_CLK_B_BOT1.HCLK_CK_BUFHCLK4 02_14 05_16
HCLK_R.HCLK_LEAF_CLK_B_BOT1.HCLK_CK_BUFHCLK5 05_14 05_16
HCLK_R.HCLK_LEAF_CLK_B_BOT1.HCLK_CK_BUFHCLK6 02_15 05_16
HCLK_R.HCLK_LEAF_CLK_B_BOT1.HCLK_CK_BUFHCLK7 05_15 05_16
HCLK_R.HCLK_LEAF_CLK_B_BOT0.HCLK_CK_BUFHCLK0 01_14 04_14
HCLK_R.HCLK_LEAF_CLK_B_BOT0.HCLK_CK_BUFHCLK1 01_14 03_14
HCLK_R.HCLK_LEAF_CLK_B_BOT0.HCLK_CK_BUFHCLK2 01_14 04_15
HCLK_R.HCLK_LEAF_CLK_B_BOT0.HCLK_CK_BUFHCLK3 01_14 03_15
HCLK_R.HCLK_LEAF_CLK_B_BOT0.HCLK_CK_BUFHCLK4 00_15 04_14
HCLK_R.HCLK_LEAF_CLK_B_BOT0.HCLK_CK_BUFHCLK5 00_15 03_14
HCLK_R.HCLK_LEAF_CLK_B_BOT0.HCLK_CK_BUFHCLK6 00_15 04_15
HCLK_R.HCLK_LEAF_CLK_B_BOT0.HCLK_CK_BUFHCLK7 00_15 03_15
HCLK_R.HCLK_LEAF_CLK_B_BOT1.HCLK_CK_OUTIN_R0 02_14 02_16
HCLK_R.HCLK_LEAF_CLK_B_BOT1.HCLK_CK_OUTIN_R1 02_16 05_14
HCLK_R.HCLK_LEAF_CLK_B_BOT1.HCLK_CK_OUTIN_R2 02_15 02_16
@ -38,14 +30,14 @@ HCLK_R.HCLK_LEAF_CLK_B_BOT1.HCLK_CK_OUTIN_R4 02_14 04_16
HCLK_R.HCLK_LEAF_CLK_B_BOT1.HCLK_CK_OUTIN_R5 04_16 05_14
HCLK_R.HCLK_LEAF_CLK_B_BOT1.HCLK_CK_OUTIN_R6 02_15 04_16
HCLK_R.HCLK_LEAF_CLK_B_BOT1.HCLK_CK_OUTIN_R7 04_16 05_15
HCLK_R.HCLK_LEAF_CLK_B_BOT2.HCLK_CK_BUFHCLK0 00_18 05_19
HCLK_R.HCLK_LEAF_CLK_B_BOT2.HCLK_CK_BUFHCLK1 00_18 02_19
HCLK_R.HCLK_LEAF_CLK_B_BOT2.HCLK_CK_BUFHCLK2 00_18 05_18
HCLK_R.HCLK_LEAF_CLK_B_BOT2.HCLK_CK_BUFHCLK3 00_18 02_18
HCLK_R.HCLK_LEAF_CLK_B_BOT2.HCLK_CK_BUFHCLK4 01_17 05_19
HCLK_R.HCLK_LEAF_CLK_B_BOT2.HCLK_CK_BUFHCLK5 01_17 02_19
HCLK_R.HCLK_LEAF_CLK_B_BOT2.HCLK_CK_BUFHCLK6 01_17 05_18
HCLK_R.HCLK_LEAF_CLK_B_BOT2.HCLK_CK_BUFHCLK7 01_17 02_18
HCLK_R.HCLK_LEAF_CLK_B_BOT1.HCLK_CK_BUFHCLK0 02_14 03_16
HCLK_R.HCLK_LEAF_CLK_B_BOT1.HCLK_CK_BUFHCLK1 03_16 05_14
HCLK_R.HCLK_LEAF_CLK_B_BOT1.HCLK_CK_BUFHCLK2 02_15 03_16
HCLK_R.HCLK_LEAF_CLK_B_BOT1.HCLK_CK_BUFHCLK3 03_16 05_15
HCLK_R.HCLK_LEAF_CLK_B_BOT1.HCLK_CK_BUFHCLK4 02_14 05_16
HCLK_R.HCLK_LEAF_CLK_B_BOT1.HCLK_CK_BUFHCLK5 05_14 05_16
HCLK_R.HCLK_LEAF_CLK_B_BOT1.HCLK_CK_BUFHCLK6 02_15 05_16
HCLK_R.HCLK_LEAF_CLK_B_BOT1.HCLK_CK_BUFHCLK7 05_15 05_16
HCLK_R.HCLK_LEAF_CLK_B_BOT2.HCLK_CK_OUTIN_R0 01_16 05_19
HCLK_R.HCLK_LEAF_CLK_B_BOT2.HCLK_CK_OUTIN_R1 01_16 02_19
HCLK_R.HCLK_LEAF_CLK_B_BOT2.HCLK_CK_OUTIN_R2 01_16 05_18
@ -54,14 +46,14 @@ HCLK_R.HCLK_LEAF_CLK_B_BOT2.HCLK_CK_OUTIN_R4 00_17 05_19
HCLK_R.HCLK_LEAF_CLK_B_BOT2.HCLK_CK_OUTIN_R5 00_17 02_19
HCLK_R.HCLK_LEAF_CLK_B_BOT2.HCLK_CK_OUTIN_R6 00_17 05_18
HCLK_R.HCLK_LEAF_CLK_B_BOT2.HCLK_CK_OUTIN_R7 00_17 02_18
HCLK_R.HCLK_LEAF_CLK_B_BOT3.HCLK_CK_BUFHCLK0 02_17 03_19
HCLK_R.HCLK_LEAF_CLK_B_BOT3.HCLK_CK_BUFHCLK1 02_17 04_19
HCLK_R.HCLK_LEAF_CLK_B_BOT3.HCLK_CK_BUFHCLK2 02_17 03_18
HCLK_R.HCLK_LEAF_CLK_B_BOT3.HCLK_CK_BUFHCLK3 02_17 04_18
HCLK_R.HCLK_LEAF_CLK_B_BOT3.HCLK_CK_BUFHCLK4 03_19 04_17
HCLK_R.HCLK_LEAF_CLK_B_BOT3.HCLK_CK_BUFHCLK5 04_17 04_19
HCLK_R.HCLK_LEAF_CLK_B_BOT3.HCLK_CK_BUFHCLK6 03_18 04_17
HCLK_R.HCLK_LEAF_CLK_B_BOT3.HCLK_CK_BUFHCLK7 04_17 04_18
HCLK_R.HCLK_LEAF_CLK_B_BOT2.HCLK_CK_BUFHCLK0 00_18 05_19
HCLK_R.HCLK_LEAF_CLK_B_BOT2.HCLK_CK_BUFHCLK1 00_18 02_19
HCLK_R.HCLK_LEAF_CLK_B_BOT2.HCLK_CK_BUFHCLK2 00_18 05_18
HCLK_R.HCLK_LEAF_CLK_B_BOT2.HCLK_CK_BUFHCLK3 00_18 02_18
HCLK_R.HCLK_LEAF_CLK_B_BOT2.HCLK_CK_BUFHCLK4 01_17 05_19
HCLK_R.HCLK_LEAF_CLK_B_BOT2.HCLK_CK_BUFHCLK5 01_17 02_19
HCLK_R.HCLK_LEAF_CLK_B_BOT2.HCLK_CK_BUFHCLK6 01_17 05_18
HCLK_R.HCLK_LEAF_CLK_B_BOT2.HCLK_CK_BUFHCLK7 01_17 02_18
HCLK_R.HCLK_LEAF_CLK_B_BOT3.HCLK_CK_OUTIN_R0 03_17 03_19
HCLK_R.HCLK_LEAF_CLK_B_BOT3.HCLK_CK_OUTIN_R1 03_17 04_19
HCLK_R.HCLK_LEAF_CLK_B_BOT3.HCLK_CK_OUTIN_R2 03_17 03_18
@ -70,14 +62,14 @@ HCLK_R.HCLK_LEAF_CLK_B_BOT3.HCLK_CK_OUTIN_R4 03_19 05_17
HCLK_R.HCLK_LEAF_CLK_B_BOT3.HCLK_CK_OUTIN_R5 04_19 05_17
HCLK_R.HCLK_LEAF_CLK_B_BOT3.HCLK_CK_OUTIN_R6 03_18 05_17
HCLK_R.HCLK_LEAF_CLK_B_BOT3.HCLK_CK_OUTIN_R7 04_18 05_17
HCLK_R.HCLK_LEAF_CLK_B_BOT4.HCLK_CK_BUFHCLK0 00_20 04_20
HCLK_R.HCLK_LEAF_CLK_B_BOT4.HCLK_CK_BUFHCLK1 00_20 03_20
HCLK_R.HCLK_LEAF_CLK_B_BOT4.HCLK_CK_BUFHCLK2 00_20 04_21
HCLK_R.HCLK_LEAF_CLK_B_BOT4.HCLK_CK_BUFHCLK3 00_20 03_21
HCLK_R.HCLK_LEAF_CLK_B_BOT4.HCLK_CK_BUFHCLK4 01_20 04_20
HCLK_R.HCLK_LEAF_CLK_B_BOT4.HCLK_CK_BUFHCLK5 01_20 03_20
HCLK_R.HCLK_LEAF_CLK_B_BOT4.HCLK_CK_BUFHCLK6 01_20 04_21
HCLK_R.HCLK_LEAF_CLK_B_BOT4.HCLK_CK_BUFHCLK7 01_20 03_21
HCLK_R.HCLK_LEAF_CLK_B_BOT3.HCLK_CK_BUFHCLK0 02_17 03_19
HCLK_R.HCLK_LEAF_CLK_B_BOT3.HCLK_CK_BUFHCLK1 02_17 04_19
HCLK_R.HCLK_LEAF_CLK_B_BOT3.HCLK_CK_BUFHCLK2 02_17 03_18
HCLK_R.HCLK_LEAF_CLK_B_BOT3.HCLK_CK_BUFHCLK3 02_17 04_18
HCLK_R.HCLK_LEAF_CLK_B_BOT3.HCLK_CK_BUFHCLK4 03_19 04_17
HCLK_R.HCLK_LEAF_CLK_B_BOT3.HCLK_CK_BUFHCLK5 04_17 04_19
HCLK_R.HCLK_LEAF_CLK_B_BOT3.HCLK_CK_BUFHCLK6 03_18 04_17
HCLK_R.HCLK_LEAF_CLK_B_BOT3.HCLK_CK_BUFHCLK7 04_17 04_18
HCLK_R.HCLK_LEAF_CLK_B_BOT4.HCLK_CK_OUTIN_R0 01_21 04_20
HCLK_R.HCLK_LEAF_CLK_B_BOT4.HCLK_CK_OUTIN_R1 01_21 03_20
HCLK_R.HCLK_LEAF_CLK_B_BOT4.HCLK_CK_OUTIN_R2 01_21 04_21
@ -86,14 +78,14 @@ HCLK_R.HCLK_LEAF_CLK_B_BOT4.HCLK_CK_OUTIN_R4 00_21 04_20
HCLK_R.HCLK_LEAF_CLK_B_BOT4.HCLK_CK_OUTIN_R5 00_21 03_20
HCLK_R.HCLK_LEAF_CLK_B_BOT4.HCLK_CK_OUTIN_R6 00_21 04_21
HCLK_R.HCLK_LEAF_CLK_B_BOT4.HCLK_CK_OUTIN_R7 00_21 03_21
HCLK_R.HCLK_LEAF_CLK_B_BOT5.HCLK_CK_BUFHCLK0 02_20 03_22
HCLK_R.HCLK_LEAF_CLK_B_BOT5.HCLK_CK_BUFHCLK1 03_22 05_20
HCLK_R.HCLK_LEAF_CLK_B_BOT5.HCLK_CK_BUFHCLK2 02_21 03_22
HCLK_R.HCLK_LEAF_CLK_B_BOT5.HCLK_CK_BUFHCLK3 03_22 05_21
HCLK_R.HCLK_LEAF_CLK_B_BOT5.HCLK_CK_BUFHCLK4 02_20 05_22
HCLK_R.HCLK_LEAF_CLK_B_BOT5.HCLK_CK_BUFHCLK5 05_20 05_22
HCLK_R.HCLK_LEAF_CLK_B_BOT5.HCLK_CK_BUFHCLK6 02_21 05_22
HCLK_R.HCLK_LEAF_CLK_B_BOT5.HCLK_CK_BUFHCLK7 05_21 05_22
HCLK_R.HCLK_LEAF_CLK_B_BOT4.HCLK_CK_BUFHCLK0 00_20 04_20
HCLK_R.HCLK_LEAF_CLK_B_BOT4.HCLK_CK_BUFHCLK1 00_20 03_20
HCLK_R.HCLK_LEAF_CLK_B_BOT4.HCLK_CK_BUFHCLK2 00_20 04_21
HCLK_R.HCLK_LEAF_CLK_B_BOT4.HCLK_CK_BUFHCLK3 00_20 03_21
HCLK_R.HCLK_LEAF_CLK_B_BOT4.HCLK_CK_BUFHCLK4 01_20 04_20
HCLK_R.HCLK_LEAF_CLK_B_BOT4.HCLK_CK_BUFHCLK5 01_20 03_20
HCLK_R.HCLK_LEAF_CLK_B_BOT4.HCLK_CK_BUFHCLK6 01_20 04_21
HCLK_R.HCLK_LEAF_CLK_B_BOT4.HCLK_CK_BUFHCLK7 01_20 03_21
HCLK_R.HCLK_LEAF_CLK_B_BOT5.HCLK_CK_OUTIN_R0 02_20 02_22
HCLK_R.HCLK_LEAF_CLK_B_BOT5.HCLK_CK_OUTIN_R1 02_22 05_20
HCLK_R.HCLK_LEAF_CLK_B_BOT5.HCLK_CK_OUTIN_R2 02_21 02_22
@ -102,14 +94,14 @@ HCLK_R.HCLK_LEAF_CLK_B_BOT5.HCLK_CK_OUTIN_R4 02_20 04_22
HCLK_R.HCLK_LEAF_CLK_B_BOT5.HCLK_CK_OUTIN_R5 04_22 05_20
HCLK_R.HCLK_LEAF_CLK_B_BOT5.HCLK_CK_OUTIN_R6 02_21 04_22
HCLK_R.HCLK_LEAF_CLK_B_BOT5.HCLK_CK_OUTIN_R7 04_22 05_21
HCLK_R.HCLK_LEAF_CLK_B_TOP0.HCLK_CK_BUFHCLK0 01_30 05_31
HCLK_R.HCLK_LEAF_CLK_B_TOP0.HCLK_CK_BUFHCLK1 01_30 02_31
HCLK_R.HCLK_LEAF_CLK_B_TOP0.HCLK_CK_BUFHCLK2 01_30 05_30
HCLK_R.HCLK_LEAF_CLK_B_TOP0.HCLK_CK_BUFHCLK3 01_30 02_30
HCLK_R.HCLK_LEAF_CLK_B_TOP0.HCLK_CK_BUFHCLK4 00_30 05_31
HCLK_R.HCLK_LEAF_CLK_B_TOP0.HCLK_CK_BUFHCLK5 00_30 02_31
HCLK_R.HCLK_LEAF_CLK_B_TOP0.HCLK_CK_BUFHCLK6 00_30 05_30
HCLK_R.HCLK_LEAF_CLK_B_TOP0.HCLK_CK_BUFHCLK7 00_30 02_30
HCLK_R.HCLK_LEAF_CLK_B_BOT5.HCLK_CK_BUFHCLK0 02_20 03_22
HCLK_R.HCLK_LEAF_CLK_B_BOT5.HCLK_CK_BUFHCLK1 03_22 05_20
HCLK_R.HCLK_LEAF_CLK_B_BOT5.HCLK_CK_BUFHCLK2 02_21 03_22
HCLK_R.HCLK_LEAF_CLK_B_BOT5.HCLK_CK_BUFHCLK3 03_22 05_21
HCLK_R.HCLK_LEAF_CLK_B_BOT5.HCLK_CK_BUFHCLK4 02_20 05_22
HCLK_R.HCLK_LEAF_CLK_B_BOT5.HCLK_CK_BUFHCLK5 05_20 05_22
HCLK_R.HCLK_LEAF_CLK_B_BOT5.HCLK_CK_BUFHCLK6 02_21 05_22
HCLK_R.HCLK_LEAF_CLK_B_BOT5.HCLK_CK_BUFHCLK7 05_21 05_22
HCLK_R.HCLK_LEAF_CLK_B_TOP0.HCLK_CK_OUTIN_R0 00_29 05_31
HCLK_R.HCLK_LEAF_CLK_B_TOP0.HCLK_CK_OUTIN_R1 00_29 02_31
HCLK_R.HCLK_LEAF_CLK_B_TOP0.HCLK_CK_OUTIN_R2 00_29 05_30
@ -118,14 +110,14 @@ HCLK_R.HCLK_LEAF_CLK_B_TOP0.HCLK_CK_OUTIN_R4 01_29 05_31
HCLK_R.HCLK_LEAF_CLK_B_TOP0.HCLK_CK_OUTIN_R5 01_29 02_31
HCLK_R.HCLK_LEAF_CLK_B_TOP0.HCLK_CK_OUTIN_R6 01_29 05_30
HCLK_R.HCLK_LEAF_CLK_B_TOP0.HCLK_CK_OUTIN_R7 01_29 02_30
HCLK_R.HCLK_LEAF_CLK_B_TOP1.HCLK_CK_BUFHCLK0 02_29 03_31
HCLK_R.HCLK_LEAF_CLK_B_TOP1.HCLK_CK_BUFHCLK1 02_29 04_31
HCLK_R.HCLK_LEAF_CLK_B_TOP1.HCLK_CK_BUFHCLK2 02_29 03_30
HCLK_R.HCLK_LEAF_CLK_B_TOP1.HCLK_CK_BUFHCLK3 02_29 04_30
HCLK_R.HCLK_LEAF_CLK_B_TOP1.HCLK_CK_BUFHCLK4 03_31 04_29
HCLK_R.HCLK_LEAF_CLK_B_TOP1.HCLK_CK_BUFHCLK5 04_29 04_31
HCLK_R.HCLK_LEAF_CLK_B_TOP1.HCLK_CK_BUFHCLK6 03_30 04_29
HCLK_R.HCLK_LEAF_CLK_B_TOP1.HCLK_CK_BUFHCLK7 04_29 04_30
HCLK_R.HCLK_LEAF_CLK_B_TOP0.HCLK_CK_BUFHCLK0 01_30 05_31
HCLK_R.HCLK_LEAF_CLK_B_TOP0.HCLK_CK_BUFHCLK1 01_30 02_31
HCLK_R.HCLK_LEAF_CLK_B_TOP0.HCLK_CK_BUFHCLK2 01_30 05_30
HCLK_R.HCLK_LEAF_CLK_B_TOP0.HCLK_CK_BUFHCLK3 01_30 02_30
HCLK_R.HCLK_LEAF_CLK_B_TOP0.HCLK_CK_BUFHCLK4 00_30 05_31
HCLK_R.HCLK_LEAF_CLK_B_TOP0.HCLK_CK_BUFHCLK5 00_30 02_31
HCLK_R.HCLK_LEAF_CLK_B_TOP0.HCLK_CK_BUFHCLK6 00_30 05_30
HCLK_R.HCLK_LEAF_CLK_B_TOP0.HCLK_CK_BUFHCLK7 00_30 02_30
HCLK_R.HCLK_LEAF_CLK_B_TOP1.HCLK_CK_OUTIN_R0 03_29 03_31
HCLK_R.HCLK_LEAF_CLK_B_TOP1.HCLK_CK_OUTIN_R1 03_29 04_31
HCLK_R.HCLK_LEAF_CLK_B_TOP1.HCLK_CK_OUTIN_R2 03_29 03_30
@ -134,14 +126,14 @@ HCLK_R.HCLK_LEAF_CLK_B_TOP1.HCLK_CK_OUTIN_R4 03_31 05_29
HCLK_R.HCLK_LEAF_CLK_B_TOP1.HCLK_CK_OUTIN_R5 04_31 05_29
HCLK_R.HCLK_LEAF_CLK_B_TOP1.HCLK_CK_OUTIN_R6 03_30 05_29
HCLK_R.HCLK_LEAF_CLK_B_TOP1.HCLK_CK_OUTIN_R7 04_30 05_29
HCLK_R.HCLK_LEAF_CLK_B_TOP2.HCLK_CK_BUFHCLK0 00_26 04_26
HCLK_R.HCLK_LEAF_CLK_B_TOP2.HCLK_CK_BUFHCLK1 00_26 03_26
HCLK_R.HCLK_LEAF_CLK_B_TOP2.HCLK_CK_BUFHCLK2 00_26 04_27
HCLK_R.HCLK_LEAF_CLK_B_TOP2.HCLK_CK_BUFHCLK3 00_26 03_27
HCLK_R.HCLK_LEAF_CLK_B_TOP2.HCLK_CK_BUFHCLK4 01_26 04_26
HCLK_R.HCLK_LEAF_CLK_B_TOP2.HCLK_CK_BUFHCLK5 01_26 03_26
HCLK_R.HCLK_LEAF_CLK_B_TOP2.HCLK_CK_BUFHCLK6 01_26 04_27
HCLK_R.HCLK_LEAF_CLK_B_TOP2.HCLK_CK_BUFHCLK7 01_26 03_27
HCLK_R.HCLK_LEAF_CLK_B_TOP1.HCLK_CK_BUFHCLK0 02_29 03_31
HCLK_R.HCLK_LEAF_CLK_B_TOP1.HCLK_CK_BUFHCLK1 02_29 04_31
HCLK_R.HCLK_LEAF_CLK_B_TOP1.HCLK_CK_BUFHCLK2 02_29 03_30
HCLK_R.HCLK_LEAF_CLK_B_TOP1.HCLK_CK_BUFHCLK3 02_29 04_30
HCLK_R.HCLK_LEAF_CLK_B_TOP1.HCLK_CK_BUFHCLK4 03_31 04_29
HCLK_R.HCLK_LEAF_CLK_B_TOP1.HCLK_CK_BUFHCLK5 04_29 04_31
HCLK_R.HCLK_LEAF_CLK_B_TOP1.HCLK_CK_BUFHCLK6 03_30 04_29
HCLK_R.HCLK_LEAF_CLK_B_TOP1.HCLK_CK_BUFHCLK7 04_29 04_30
HCLK_R.HCLK_LEAF_CLK_B_TOP2.HCLK_CK_OUTIN_R0 01_28 04_26
HCLK_R.HCLK_LEAF_CLK_B_TOP2.HCLK_CK_OUTIN_R1 01_28 03_26
HCLK_R.HCLK_LEAF_CLK_B_TOP2.HCLK_CK_OUTIN_R2 01_28 04_27
@ -150,14 +142,14 @@ HCLK_R.HCLK_LEAF_CLK_B_TOP2.HCLK_CK_OUTIN_R4 00_28 04_26
HCLK_R.HCLK_LEAF_CLK_B_TOP2.HCLK_CK_OUTIN_R5 00_28 03_26
HCLK_R.HCLK_LEAF_CLK_B_TOP2.HCLK_CK_OUTIN_R6 00_28 04_27
HCLK_R.HCLK_LEAF_CLK_B_TOP2.HCLK_CK_OUTIN_R7 00_28 03_27
HCLK_R.HCLK_LEAF_CLK_B_TOP3.HCLK_CK_BUFHCLK0 02_26 03_28
HCLK_R.HCLK_LEAF_CLK_B_TOP3.HCLK_CK_BUFHCLK1 03_28 05_26
HCLK_R.HCLK_LEAF_CLK_B_TOP3.HCLK_CK_BUFHCLK2 02_27 03_28
HCLK_R.HCLK_LEAF_CLK_B_TOP3.HCLK_CK_BUFHCLK3 03_28 05_27
HCLK_R.HCLK_LEAF_CLK_B_TOP3.HCLK_CK_BUFHCLK4 02_26 05_28
HCLK_R.HCLK_LEAF_CLK_B_TOP3.HCLK_CK_BUFHCLK5 05_26 05_28
HCLK_R.HCLK_LEAF_CLK_B_TOP3.HCLK_CK_BUFHCLK6 02_27 05_28
HCLK_R.HCLK_LEAF_CLK_B_TOP3.HCLK_CK_BUFHCLK7 05_27 05_28
HCLK_R.HCLK_LEAF_CLK_B_TOP2.HCLK_CK_BUFHCLK0 00_26 04_26
HCLK_R.HCLK_LEAF_CLK_B_TOP2.HCLK_CK_BUFHCLK1 00_26 03_26
HCLK_R.HCLK_LEAF_CLK_B_TOP2.HCLK_CK_BUFHCLK2 00_26 04_27
HCLK_R.HCLK_LEAF_CLK_B_TOP2.HCLK_CK_BUFHCLK3 00_26 03_27
HCLK_R.HCLK_LEAF_CLK_B_TOP2.HCLK_CK_BUFHCLK4 01_26 04_26
HCLK_R.HCLK_LEAF_CLK_B_TOP2.HCLK_CK_BUFHCLK5 01_26 03_26
HCLK_R.HCLK_LEAF_CLK_B_TOP2.HCLK_CK_BUFHCLK6 01_26 04_27
HCLK_R.HCLK_LEAF_CLK_B_TOP2.HCLK_CK_BUFHCLK7 01_26 03_27
HCLK_R.HCLK_LEAF_CLK_B_TOP3.HCLK_CK_OUTIN_R0 02_26 02_28
HCLK_R.HCLK_LEAF_CLK_B_TOP3.HCLK_CK_OUTIN_R1 02_28 05_26
HCLK_R.HCLK_LEAF_CLK_B_TOP3.HCLK_CK_OUTIN_R2 02_27 02_28
@ -166,14 +158,14 @@ HCLK_R.HCLK_LEAF_CLK_B_TOP3.HCLK_CK_OUTIN_R4 02_26 04_28
HCLK_R.HCLK_LEAF_CLK_B_TOP3.HCLK_CK_OUTIN_R5 04_28 05_26
HCLK_R.HCLK_LEAF_CLK_B_TOP3.HCLK_CK_OUTIN_R6 02_27 04_28
HCLK_R.HCLK_LEAF_CLK_B_TOP3.HCLK_CK_OUTIN_R7 04_28 05_27
HCLK_R.HCLK_LEAF_CLK_B_TOP4.HCLK_CK_BUFHCLK0 01_25 05_25
HCLK_R.HCLK_LEAF_CLK_B_TOP4.HCLK_CK_BUFHCLK1 01_25 02_25
HCLK_R.HCLK_LEAF_CLK_B_TOP4.HCLK_CK_BUFHCLK2 01_25 05_24
HCLK_R.HCLK_LEAF_CLK_B_TOP4.HCLK_CK_BUFHCLK3 01_25 02_24
HCLK_R.HCLK_LEAF_CLK_B_TOP4.HCLK_CK_BUFHCLK4 00_25 05_25
HCLK_R.HCLK_LEAF_CLK_B_TOP4.HCLK_CK_BUFHCLK5 00_25 02_25
HCLK_R.HCLK_LEAF_CLK_B_TOP4.HCLK_CK_BUFHCLK6 00_25 05_24
HCLK_R.HCLK_LEAF_CLK_B_TOP4.HCLK_CK_BUFHCLK7 00_25 02_24
HCLK_R.HCLK_LEAF_CLK_B_TOP3.HCLK_CK_BUFHCLK0 02_26 03_28
HCLK_R.HCLK_LEAF_CLK_B_TOP3.HCLK_CK_BUFHCLK1 03_28 05_26
HCLK_R.HCLK_LEAF_CLK_B_TOP3.HCLK_CK_BUFHCLK2 02_27 03_28
HCLK_R.HCLK_LEAF_CLK_B_TOP3.HCLK_CK_BUFHCLK3 03_28 05_27
HCLK_R.HCLK_LEAF_CLK_B_TOP3.HCLK_CK_BUFHCLK4 02_26 05_28
HCLK_R.HCLK_LEAF_CLK_B_TOP3.HCLK_CK_BUFHCLK5 05_26 05_28
HCLK_R.HCLK_LEAF_CLK_B_TOP3.HCLK_CK_BUFHCLK6 02_27 05_28
HCLK_R.HCLK_LEAF_CLK_B_TOP3.HCLK_CK_BUFHCLK7 05_27 05_28
HCLK_R.HCLK_LEAF_CLK_B_TOP4.HCLK_CK_OUTIN_R0 00_24 05_25
HCLK_R.HCLK_LEAF_CLK_B_TOP4.HCLK_CK_OUTIN_R1 00_24 02_25
HCLK_R.HCLK_LEAF_CLK_B_TOP4.HCLK_CK_OUTIN_R2 00_24 05_24
@ -182,14 +174,14 @@ HCLK_R.HCLK_LEAF_CLK_B_TOP4.HCLK_CK_OUTIN_R4 01_24 05_25
HCLK_R.HCLK_LEAF_CLK_B_TOP4.HCLK_CK_OUTIN_R5 01_24 02_25
HCLK_R.HCLK_LEAF_CLK_B_TOP4.HCLK_CK_OUTIN_R6 01_24 05_24
HCLK_R.HCLK_LEAF_CLK_B_TOP4.HCLK_CK_OUTIN_R7 01_24 02_24
HCLK_R.HCLK_LEAF_CLK_B_TOP5.HCLK_CK_BUFHCLK0 02_23 03_25
HCLK_R.HCLK_LEAF_CLK_B_TOP5.HCLK_CK_BUFHCLK1 02_23 04_25
HCLK_R.HCLK_LEAF_CLK_B_TOP5.HCLK_CK_BUFHCLK2 02_23 03_24
HCLK_R.HCLK_LEAF_CLK_B_TOP5.HCLK_CK_BUFHCLK3 02_23 04_24
HCLK_R.HCLK_LEAF_CLK_B_TOP5.HCLK_CK_BUFHCLK4 03_25 04_23
HCLK_R.HCLK_LEAF_CLK_B_TOP5.HCLK_CK_BUFHCLK5 04_23 04_25
HCLK_R.HCLK_LEAF_CLK_B_TOP5.HCLK_CK_BUFHCLK6 03_24 04_23
HCLK_R.HCLK_LEAF_CLK_B_TOP5.HCLK_CK_BUFHCLK7 04_23 04_24
HCLK_R.HCLK_LEAF_CLK_B_TOP4.HCLK_CK_BUFHCLK0 01_25 05_25
HCLK_R.HCLK_LEAF_CLK_B_TOP4.HCLK_CK_BUFHCLK1 01_25 02_25
HCLK_R.HCLK_LEAF_CLK_B_TOP4.HCLK_CK_BUFHCLK2 01_25 05_24
HCLK_R.HCLK_LEAF_CLK_B_TOP4.HCLK_CK_BUFHCLK3 01_25 02_24
HCLK_R.HCLK_LEAF_CLK_B_TOP4.HCLK_CK_BUFHCLK4 00_25 05_25
HCLK_R.HCLK_LEAF_CLK_B_TOP4.HCLK_CK_BUFHCLK5 00_25 02_25
HCLK_R.HCLK_LEAF_CLK_B_TOP4.HCLK_CK_BUFHCLK6 00_25 05_24
HCLK_R.HCLK_LEAF_CLK_B_TOP4.HCLK_CK_BUFHCLK7 00_25 02_24
HCLK_R.HCLK_LEAF_CLK_B_TOP5.HCLK_CK_OUTIN_R0 03_23 03_25
HCLK_R.HCLK_LEAF_CLK_B_TOP5.HCLK_CK_OUTIN_R1 03_23 04_25
HCLK_R.HCLK_LEAF_CLK_B_TOP5.HCLK_CK_OUTIN_R2 03_23 03_24
@ -198,3 +190,11 @@ HCLK_R.HCLK_LEAF_CLK_B_TOP5.HCLK_CK_OUTIN_R4 03_25 05_23
HCLK_R.HCLK_LEAF_CLK_B_TOP5.HCLK_CK_OUTIN_R5 04_25 05_23
HCLK_R.HCLK_LEAF_CLK_B_TOP5.HCLK_CK_OUTIN_R6 03_24 05_23
HCLK_R.HCLK_LEAF_CLK_B_TOP5.HCLK_CK_OUTIN_R7 04_24 05_23
HCLK_R.HCLK_LEAF_CLK_B_TOP5.HCLK_CK_BUFHCLK0 02_23 03_25
HCLK_R.HCLK_LEAF_CLK_B_TOP5.HCLK_CK_BUFHCLK1 02_23 04_25
HCLK_R.HCLK_LEAF_CLK_B_TOP5.HCLK_CK_BUFHCLK2 02_23 03_24
HCLK_R.HCLK_LEAF_CLK_B_TOP5.HCLK_CK_BUFHCLK3 02_23 04_24
HCLK_R.HCLK_LEAF_CLK_B_TOP5.HCLK_CK_BUFHCLK4 03_25 04_23
HCLK_R.HCLK_LEAF_CLK_B_TOP5.HCLK_CK_BUFHCLK5 04_23 04_25
HCLK_R.HCLK_LEAF_CLK_B_TOP5.HCLK_CK_BUFHCLK6 03_24 04_23
HCLK_R.HCLK_LEAF_CLK_B_TOP5.HCLK_CK_BUFHCLK7 04_23 04_24

4794
artix7/segbits_int_l.db
View File

File diff suppressed because it is too large Load Diff

4352
artix7/segbits_int_r.db
View File

File diff suppressed because it is too large Load Diff

26
artix7/settings.sh
View File

@ -1,25 +1 @@
export XRAY_DATABASE="artix7"
export XRAY_PART="xc7a50tfgg484-1"
export XRAY_ROI_FRAMES="0x00000000:0xffffffff"
# All CLB's in part, all BRAM's in part, all DSP's in part.
export XRAY_ROI_TILEGRID="SLICE_X0Y0:SLICE_X65Y99 SLICE_X0Y100:SLICE_X57Y149 RAMB18_X0Y0:RAMB18_X1Y59 RAMB36_X0Y0:RAMB36_X1Y29 RAMB18_X2Y0:RAMB18_X2Y39 RAMB36_X2Y0:RAMB36_X2Y19 DSP48_X0Y0:DSP48_X1Y59"
# These settings must remain in sync
export XRAY_ROI="SLICE_X0Y100:SLICE_X35Y149 RAMB18_X0Y40:RAMB18_X0Y59 RAMB36_X0Y20:RAMB36_X0Y29 DSP48_X0Y40:DSP48_X0Y59"
# Most of CMT X0Y2.
export XRAY_ROI_GRID_X1="9"
export XRAY_ROI_GRID_X2="58"
# Include VBRK / VTERM
export XRAY_ROI_GRID_Y1="0"
export XRAY_ROI_GRID_Y2="52"
export XRAY_PIN_00="E22"
export XRAY_PIN_01="D22"
export XRAY_PIN_02="E21"
export XRAY_PIN_03="D21"
export XRAY_PIN_04="G21"
export XRAY_PIN_05="G22"
export XRAY_PIN_06="F21"
source $(dirname ${BASH_SOURCE[0]})/../../utils/environment.sh
source $(dirname ${BASH_SOURCE[0]})/../../settings/artix7.sh

2
artix7/site_type_BSCAN.json
View File

@ -36,4 +36,4 @@
},
"site_pips": {},
"type": "BSCAN"
}
}

2
artix7/site_type_BUFGCTRL.json
View File

@ -79,4 +79,4 @@
}
},
"type": "BUFGCTRL"
}
}

2
artix7/site_type_BUFHCE.json
View File

@ -21,4 +21,4 @@
}
},
"type": "BUFHCE"
}
}

2
artix7/site_type_BUFIO.json
View File

@ -9,4 +9,4 @@
},
"site_pips": {},
"type": "BUFIO"
}
}

2
artix7/site_type_BUFMRCE.json
View File

@ -21,4 +21,4 @@
}
},
"type": "BUFMRCE"
}
}

2
artix7/site_type_BUFR.json
View File

@ -15,4 +15,4 @@
},
"site_pips": {},
"type": "BUFR"
}
}

2
artix7/site_type_CAPTURE.json
View File

@ -9,4 +9,4 @@
},
"site_pips": {},
"type": "CAPTURE"
}
}

2
artix7/site_type_DCIRESET.json
View File

@ -9,4 +9,4 @@
},
"site_pips": {},
"type": "DCIRESET"
}
}

2
artix7/site_type_DNA_PORT.json
View File

@ -18,4 +18,4 @@
},
"site_pips": {},
"type": "DNA_PORT"
}
}

2
artix7/site_type_DSP48E1.json
View File

@ -1399,4 +1399,4 @@
}
},
"type": "DSP48E1"
}
}

2
artix7/site_type_EFUSE_USR.json
View File

@ -99,4 +99,4 @@
},
"site_pips": {},
"type": "EFUSE_USR"
}
}

2
artix7/site_type_FIFO18E1.json
View File

@ -534,4 +534,4 @@
}
},
"type": "FIFO18E1"
}
}

2
artix7/site_type_FRAME_ECC.json
View File

@ -168,4 +168,4 @@
},
"site_pips": {},
"type": "FRAME_ECC"
}
}

2
artix7/site_type_GTPE2_CHANNEL.json
View File

@ -1871,4 +1871,4 @@
}
},
"type": "GTPE2_CHANNEL"
}
}

2
artix7/site_type_GTPE2_COMMON.json
View File

@ -539,4 +539,4 @@
}
},
"type": "GTPE2_COMMON"
}
}

2
artix7/site_type_IBUFDS_GTE2.json
View File

@ -30,4 +30,4 @@
}
},
"type": "IBUFDS_GTE2"
}
}

2
artix7/site_type_ICAP.json
View File

@ -204,4 +204,4 @@
},
"site_pips": {},
"type": "ICAP"
}
}

2
artix7/site_type_IDELAYCTRL.json
View File

@ -24,4 +24,4 @@
},
"site_pips": {},
"type": "IDELAYCTRL"
}
}

2
artix7/site_type_IDELAYE2.json
View File

@ -97,4 +97,4 @@
}
},
"type": "IDELAYE2"
}
}

2
artix7/site_type_ILOGICE3.json
View File

@ -205,4 +205,4 @@
}
},
"type": "ILOGICE3"
}
}

2
artix7/site_type_IN_FIFO.json
View File

@ -450,4 +450,4 @@
},
"site_pips": {},
"type": "IN_FIFO"
}
}

2
artix7/site_type_IOB33.json
View File

@ -91,4 +91,4 @@
}
},
"type": "IOB33"
}
}

2
artix7/site_type_IOB33M.json
View File

@ -103,4 +103,4 @@
}
},
"type": "IOB33M"
}
}

2
artix7/site_type_IOB33S.json
View File

@ -111,4 +111,4 @@
}
},
"type": "IOB33S"
}
}

2
artix7/site_type_IPAD.json
View File

@ -6,4 +6,4 @@
},
"site_pips": {},
"type": "IPAD"
}
}

2
artix7/site_type_MMCME2_ADV.json
View File

@ -542,4 +542,4 @@
}
},
"type": "MMCME2_ADV"
}
}

2
artix7/site_type_OLOGICE3.json
View File

@ -207,4 +207,4 @@
}
},
"type": "OLOGICE3"
}
}

2
artix7/site_type_OPAD.json
View File

@ -6,4 +6,4 @@
},
"site_pips": {},
"type": "OPAD"
}
}

2
artix7/site_type_OUT_FIFO.json
View File

@ -450,4 +450,4 @@
},
"site_pips": {},
"type": "OUT_FIFO"
}
}

2
artix7/site_type_PCIE_2_1.json
View File

@ -6750,4 +6750,4 @@
},
"site_pips": {},
"type": "PCIE_2_1"
}
}

2
artix7/site_type_PHASER_IN_PHY.json
View File

@ -288,4 +288,4 @@
}
},
"type": "PHASER_IN_PHY"
}
}

2
artix7/site_type_PHASER_OUT_PHY.json
View File

@ -243,4 +243,4 @@
}
},
"type": "PHASER_OUT_PHY"
}
}

2
artix7/site_type_PHASER_REF.json
View File

@ -86,4 +86,4 @@
}
},
"type": "PHASER_REF"
}
}

2
artix7/site_type_PHY_CONTROL.json
View File

@ -315,4 +315,4 @@
},
"site_pips": {},
"type": "PHY_CONTROL"
}
}

2
artix7/site_type_PLLE2_ADV.json
View File

@ -490,4 +490,4 @@
}
},
"type": "PLLE2_ADV"
}
}

2
artix7/site_type_PMV2.json
View File

@ -24,4 +24,4 @@
},
"site_pips": {},
"type": "PMV2"
}
}

2
artix7/site_type_RAMB18E1.json
View File

@ -558,4 +558,4 @@
}
},
"type": "RAMB18E1"
}
}

2
artix7/site_type_RAMBFIFO36E1.json
View File

@ -1232,4 +1232,4 @@
}
},
"type": "RAMBFIFO36E1"
}
}

2
artix7/site_type_SLICEL.json
View File

@ -691,4 +691,4 @@
}
},
"type": "SLICEL"
}
}

2
artix7/site_type_SLICEM.json
View File

@ -766,4 +766,4 @@
}
},
"type": "SLICEM"
}
}

2
artix7/site_type_STARTUP.json
View File

@ -42,4 +42,4 @@
},
"site_pips": {},
"type": "STARTUP"
}
}

2
artix7/site_type_TIEOFF.json
View File

@ -9,4 +9,4 @@
},
"site_pips": {},
"type": "TIEOFF"
}
}

2
artix7/site_type_USR_ACCESS.json
View File

@ -105,4 +105,4 @@
},
"site_pips": {},
"type": "USR_ACCESS"
}
}

2
artix7/site_type_XADC.json
View File

@ -680,4 +680,4 @@
}
},
"type": "XADC"
}
}

2
artix7/tile_type_BRAM_INT_INTERFACE_L.json
View File

@ -473,4 +473,4 @@
"INT_INTERFACE_WW4END3",
"L_INT_INTER_DQS_IOTOPHASER"
]
}
}

2
artix7/tile_type_BRAM_INT_INTERFACE_R.json
View File

@ -473,4 +473,4 @@
"INT_INTERFACE_WW4END3",
"L_INT_INTER_DQS_IOTOPHASER"
]
}
}

2
artix7/tile_type_BRAM_L.json
View File

@ -9831,4 +9831,4 @@
"BRAM_WW4END3_3",
"BRAM_WW4END3_4"
]
}
}

2
artix7/tile_type_BRAM_R.json
View File

@ -9831,4 +9831,4 @@
"BRAM_WW4END3_3",
"BRAM_WW4END3_4"
]
}
}

2
artix7/tile_type_BRKH_BRAM.json
View File

@ -68,4 +68,4 @@
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU8",
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU9"
]
}
}

2
artix7/tile_type_BRKH_B_TERM_INT.json
View File

@ -122,4 +122,4 @@
"B_TERM_UTURN_INT_WR1BEG0",
"B_TERM_UTURN_INT_WR1END0"
]
}
}

2
artix7/tile_type_BRKH_CLB.json
View File

@ -8,4 +8,4 @@
"BRKH_CLB_COUT1_L",
"BRKH_CLB_COUT1_R"
]
}
}

2
artix7/tile_type_BRKH_CLK.json
View File

@ -132,4 +132,4 @@
"BRKH_CLK_R_CK_GCLK8",
"BRKH_CLK_R_CK_GCLK9"
]
}
}

2
artix7/tile_type_BRKH_CMT.json
View File

@ -13,4 +13,4 @@
"BRKH_CMT_PHASEREF_BELOW1",
"BRKH_CMT_PHYCTRL_SYNC_BB"
]
}
}

2
artix7/tile_type_BRKH_DSP_L.json
View File

@ -102,4 +102,4 @@
"BRKH_DSP_PCIN8",
"BRKH_DSP_PCIN9"
]
}
}

2
artix7/tile_type_BRKH_DSP_R.json
View File

@ -102,4 +102,4 @@
"BRKH_DSP_PCIN8",
"BRKH_DSP_PCIN9"
]
}
}

2
artix7/tile_type_BRKH_GTX.json
View File

@ -101,4 +101,4 @@
"BRKH_GTX_SOUTHREFCLK1_LOWER",
"BRKH_GTX_SOUTHREFCLK1_UPPER"
]
}
}

2
artix7/tile_type_BRKH_INT.json
View File

@ -364,4 +364,4 @@
"BRKH_INT_WW2END3",
"BRKH_INT_WW4END_S0_0"
]
}
}

2
artix7/tile_type_BRKH_TERM_INT.json
View File

@ -121,4 +121,4 @@
"T_TERM_UTURN_INT_WR1BEG_S0",
"T_TERM_UTURN_INT_WR1END_S1_0"
]
}
}

2
artix7/tile_type_B_TERM_INT.json
View File

@ -122,4 +122,4 @@
"B_TERM_UTURN_INT_WR1BEG0",
"B_TERM_UTURN_INT_WR1END0"
]
}
}

2
artix7/tile_type_CFG_CENTER_BOT.json
View File

@ -4510,4 +4510,4 @@
"CFG_CENTER_WW4END3_8",
"CFG_CENTER_WW4END3_9"
]
}
}

2
artix7/tile_type_CFG_CENTER_MID.json
View File

@ -7184,4 +7184,4 @@
"CFG_CENTER_WW4END3_8",
"CFG_CENTER_WW4END3_9"
]
}
}

2
artix7/tile_type_CFG_CENTER_TOP.json
View File

@ -2587,4 +2587,4 @@
"CFG_CENTER_WW4END3_8",
"CFG_CENTER_WW4END3_9"
]
}
}

2
artix7/tile_type_CLBLL_L.json
View File

@ -1446,4 +1446,4 @@
"CLBLL_WW4END2",
"CLBLL_WW4END3"
]
}
}

2
artix7/tile_type_CLBLL_R.json
View File

@ -1446,4 +1446,4 @@
"CLBLL_WW4END2",
"CLBLL_WW4END3"
]
}
}

2
artix7/tile_type_CLBLM_L.json
View File

@ -1491,4 +1491,4 @@
"CLBLM_WW4END2",
"CLBLM_WW4END3"
]
}
}

2
artix7/tile_type_CLBLM_R.json
View File

@ -1491,4 +1491,4 @@
"CLBLM_WW4END2",
"CLBLM_WW4END3"
]
}
}

2
artix7/tile_type_CLK_BUFG_BOT_R.json
View File

@ -3566,4 +3566,4 @@
"CLK_HROW_WW4END3_2",
"CLK_HROW_WW4END3_3"
]
}
}

2
artix7/tile_type_CLK_BUFG_REBUF.json
View File

@ -1185,4 +1185,4 @@
"GCLK9_8_UP_TEST_RING_IN",
"GCLK9_8_UP_TEST_RING_OUT"
]
}
}

2
artix7/tile_type_CLK_BUFG_TOP_R.json
View File

@ -3566,4 +3566,4 @@
"CLK_HROW_WW4END3_2",
"CLK_HROW_WW4END3_3"
]
}
}

2
artix7/tile_type_CLK_FEED.json
View File

@ -258,4 +258,4 @@
"CLK_FEED_WW4END2",
"CLK_FEED_WW4END3"
]
}
}

2
artix7/tile_type_CLK_HROW_BOT_R.json
View File

@ -22378,4 +22378,4 @@
"CLK_HROW_WW4END3_6",
"CLK_HROW_WW4END3_7"
]
}
}

2
artix7/tile_type_CLK_HROW_TOP_R.json
View File

@ -22378,4 +22378,4 @@
"CLK_HROW_WW4END3_6",
"CLK_HROW_WW4END3_7"
]
}
}

2
artix7/tile_type_CLK_MTBF2.json
View File

@ -362,4 +362,4 @@
"CLK_PMV_LOGIC_OUTS8_0",
"CLK_PMV_LOGIC_OUTS9_0"
]
}
}

2
artix7/tile_type_CLK_PMV.json
View File

@ -1668,4 +1668,4 @@
"CLK_PMV_WW4END3_5",
"CLK_PMV_WW4END3_6"
]
}
}

2
artix7/tile_type_CLK_PMV2.json
View File

@ -374,4 +374,4 @@
"CLK_PMV_LOGIC_OUTS8_0",
"CLK_PMV_LOGIC_OUTS9_0"
]
}
}

2
artix7/tile_type_CLK_PMV2_SVT.json
View File

@ -357,4 +357,4 @@
"CLK_PMV_LOGIC_OUTS8_0",
"CLK_PMV_LOGIC_OUTS9_0"
]
}
}

2
artix7/tile_type_CLK_PMVIOB.json
View File

@ -356,4 +356,4 @@
"CLK_PMV_LOGIC_OUTS8_0",
"CLK_PMV_LOGIC_OUTS9_0"
]
}
}

2
artix7/tile_type_CLK_TERM.json
View File

@ -68,4 +68,4 @@
"CLK_TERM_R_GCLK8",
"CLK_TERM_R_GCLK9"
]
}
}

Some files were not shown because too many files have changed in this diff Show More