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Merge pull request #3 from litghost/fixup_database 

Fix up database
This commit is contained in:
Tim Ansell 2019-01-11 17:47:09 -08:00 committed by GitHub
parent aa178c3e2f a47c01d9ac
commit 79aea5dea1
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
10 changed files with 3004 additions and 59 deletions
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artix7/harness/basys3/swbut/design.bit
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artix7/harness/basys3/swbut/design.dcp
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artix7/harness/basys3/swbut/design.json
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artix7/harness/basys3/swbut/design.txt
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@ -1,18 +1,36 @@
name node pin wire
clk CLK_HROW_TOP_R_X60Y130/CLK_HROW_CK_BUFHCLK_L0 W5 HCLK_VBRK_X34Y130/HCLK_VBRK_CK_BUFHCLK0
din[0] INT_R_X9Y102/NE2BEG3 V17 VBRK_X29Y108/VBRK_NE2A3
din[1] INT_R_X9Y105/NE2BEG3 V16 VBRK_X29Y111/VBRK_NE2A3
din[2] INT_R_X9Y108/NE2BEG3 W16 VBRK_X29Y114/VBRK_NE2A3
din[3] INT_R_X9Y111/NE2BEG3 W17 VBRK_X29Y117/VBRK_NE2A3
din[4] INT_R_X9Y114/NE2BEG3 W15 VBRK_X29Y120/VBRK_NE2A3
din[5] INT_R_X9Y117/NE2BEG3 V15 VBRK_X29Y123/VBRK_NE2A3
din[6] INT_R_X9Y120/NE2BEG3 W14 VBRK_X29Y126/VBRK_NE2A3
din[7] INT_R_X9Y123/NE2BEG3 W13 VBRK_X29Y129/VBRK_NE2A3
dout[0] INT_L_X10Y125/SW6BEG0 U16 VBRK_X29Y131/VBRK_SW4A0
dout[1] INT_L_X10Y128/SW6BEG0 E19 VBRK_X29Y134/VBRK_SW4A0
dout[2] INT_L_X10Y131/SW6BEG0 U19 VBRK_X29Y137/VBRK_SW4A0
dout[3] INT_L_X10Y134/SW6BEG0 V19 VBRK_X29Y140/VBRK_SW4A0
dout[4] INT_L_X10Y137/SW6BEG0 W18 VBRK_X29Y143/VBRK_SW4A0
dout[5] INT_L_X10Y140/SW6BEG0 U15 VBRK_X29Y146/VBRK_SW4A0
dout[6] INT_L_X10Y143/SW6BEG0 U14 VBRK_X29Y149/VBRK_SW4A0
dout[7] INT_L_X10Y146/SW6BEG0 V14 VBRK_X29Y152/VBRK_SW4A0
din[0] INT_L_X0Y102/EE2BEG2 V17 VBRK_X9Y107/VBRK_EE2A2
din[1] INT_L_X0Y104/EE2BEG2 V16 VBRK_X9Y109/VBRK_EE2A2
din[2] INT_L_X0Y106/EE2BEG2 W16 VBRK_X9Y111/VBRK_EE2A2
din[3] INT_L_X0Y108/EE2BEG2 W17 VBRK_X9Y113/VBRK_EE2A2
din[4] INT_L_X0Y110/EE2BEG2 W15 VBRK_X9Y115/VBRK_EE2A2
din[5] INT_L_X0Y112/EE2BEG2 V15 VBRK_X9Y117/VBRK_EE2A2
din[6] INT_L_X0Y114/EE2BEG2 W14 VBRK_X9Y119/VBRK_EE2A2
din[7] INT_L_X0Y116/EE2BEG2 W13 VBRK_X9Y121/VBRK_EE2A2
din[8] INT_R_X25Y126/WW2BEG1 V2 VBRK_X61Y132/VBRK_WW2END1
din[9] INT_R_X25Y128/WW2BEG1 T3 VBRK_X61Y134/VBRK_WW2END1
din[10] INT_R_X25Y130/WW2BEG1 T2 VBRK_X61Y136/VBRK_WW2END1
din[11] INT_R_X25Y132/WW2BEG1 R3 VBRK_X61Y138/VBRK_WW2END1
din[12] INT_R_X25Y134/WW2BEG1 W2 VBRK_X61Y140/VBRK_WW2END1
din[13] INT_R_X25Y136/WW2BEG1 U1 VBRK_X61Y142/VBRK_WW2END1
din[14] INT_R_X25Y138/WW2BEG1 T1 VBRK_X61Y144/VBRK_WW2END1
din[15] INT_R_X25Y140/WW2BEG1 R2 VBRK_X61Y146/VBRK_WW2END1
din[16] INT_L_X0Y118/EE2BEG2 B18 VBRK_X9Y123/VBRK_EE2A2
dout[0] INT_L_X2Y115/SW6BEG0 U16 VBRK_X9Y120/VBRK_SW4A0
dout[1] INT_L_X2Y117/SW6BEG0 E19 VBRK_X9Y122/VBRK_SW4A0
dout[2] INT_L_X2Y119/SW6BEG0 U19 VBRK_X9Y124/VBRK_SW4A0
dout[3] INT_L_X2Y121/SW6BEG0 V19 VBRK_X9Y126/VBRK_SW4A0
dout[4] INT_L_X2Y123/SW6BEG0 W18 VBRK_X9Y128/VBRK_SW4A0
dout[5] INT_L_X2Y125/SW6BEG0 U15 VBRK_X9Y131/VBRK_SW4A0
dout[6] INT_L_X2Y127/SW6BEG0 U14 VBRK_X9Y133/VBRK_SW4A0
dout[7] INT_L_X2Y129/SW6BEG0 V14 VBRK_X9Y135/VBRK_SW4A0
dout[8] INT_L_X2Y131/SW6BEG0 V13 VBRK_X9Y137/VBRK_SW4A0
dout[9] INT_R_X23Y115/LH12 V3 VBRK_X61Y120/VBRK_LH12
dout[10] INT_R_X23Y117/LH12 W3 VBRK_X61Y122/VBRK_LH12
dout[11] INT_R_X23Y119/LH12 U3 VBRK_X61Y124/VBRK_LH12
dout[12] INT_R_X23Y121/LH12 P3 VBRK_X61Y126/VBRK_LH12
dout[13] INT_R_X23Y123/LH12 N3 VBRK_X61Y128/VBRK_LH12
dout[14] INT_R_X23Y125/LH12 P1 VBRK_X61Y131/VBRK_LH12
dout[15] INT_R_X23Y127/LH12 L1 VBRK_X61Y133/VBRK_LH12
dout[16] INT_L_X2Y133/SW6BEG0 A18 VBRK_X9Y139/VBRK_SW4A0

2
artix7/segbits_clbll_l.db
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@ -510,7 +510,7 @@ CLBLL_L.SLICEL_X1.C5FF.ZINI 31_42
CLBLL_L.SLICEL_X1.C5FF.ZRST 00_44
CLBLL_L.SLICEL_X1.C5FFMUX.IN_A 31_44
CLBLL_L.SLICEL_X1.C5FFMUX.IN_B 31_39
CLBLL_L.SLICEL_X1.CARRY4.ACY0 31_01 31_04 31_14 31_15
CLBLL_L.SLICEL_X1.CARRY4.ACY0 31_14
CLBLL_L.SLICEL_X1.CARRY4.BCY0 00_08
CLBLL_L.SLICEL_X1.CARRY4.CCY0 31_48
CLBLL_L.SLICEL_X1.CARRY4.DCY0 31_49

2
artix7/segbits_clbll_r.db
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@ -510,7 +510,7 @@ CLBLL_R.SLICEL_X1.C5FF.ZINI 31_42
CLBLL_R.SLICEL_X1.C5FF.ZRST 00_44
CLBLL_R.SLICEL_X1.C5FFMUX.IN_A 31_44
CLBLL_R.SLICEL_X1.C5FFMUX.IN_B 31_39
CLBLL_R.SLICEL_X1.CARRY4.ACY0 31_01 31_04 31_14 31_15
CLBLL_R.SLICEL_X1.CARRY4.ACY0 31_14
CLBLL_R.SLICEL_X1.CARRY4.BCY0 00_08
CLBLL_R.SLICEL_X1.CARRY4.CCY0 31_48
CLBLL_R.SLICEL_X1.CARRY4.DCY0 31_49

2
artix7/segbits_clblm_l.db
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@ -166,7 +166,7 @@ CLBLM_L.SLICEL_X1.C5FF.ZINI 31_42
CLBLM_L.SLICEL_X1.C5FF.ZRST 00_44
CLBLM_L.SLICEL_X1.C5FFMUX.IN_A 31_44
CLBLM_L.SLICEL_X1.C5FFMUX.IN_B 31_39
CLBLM_L.SLICEL_X1.CARRY4.ACY0 31_01 31_04 31_14 31_15
CLBLM_L.SLICEL_X1.CARRY4.ACY0 31_14
CLBLM_L.SLICEL_X1.CARRY4.BCY0 00_08
CLBLM_L.SLICEL_X1.CARRY4.CCY0 31_48
CLBLM_L.SLICEL_X1.CARRY4.DCY0 31_49

2
artix7/segbits_clblm_r.db
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@ -166,7 +166,7 @@ CLBLM_R.SLICEL_X1.C5FF.ZINI 31_42
CLBLM_R.SLICEL_X1.C5FF.ZRST 00_44
CLBLM_R.SLICEL_X1.C5FFMUX.IN_A 31_44
CLBLM_R.SLICEL_X1.C5FFMUX.IN_B 31_39
CLBLM_R.SLICEL_X1.CARRY4.ACY0 31_01 31_04 31_14 31_15
CLBLM_R.SLICEL_X1.CARRY4.ACY0 31_14
CLBLM_R.SLICEL_X1.CARRY4.BCY0 00_08
CLBLM_R.SLICEL_X1.CARRY4.CCY0 31_48
CLBLM_R.SLICEL_X1.CARRY4.DCY0 31_49

2
artix7/segbits_int_l.db
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@ -19,7 +19,6 @@ INT_L.BYP_ALT0.SL1END0 !23_07 19_06 22_07 24_07 25_07
INT_L.BYP_ALT0.SR1END_N3_3 !22_07 18_06 23_07 24_07 25_07
INT_L.BYP_ALT0.SS2END0 !22_07 !23_07 !25_07 16_07 24_07
INT_L.BYP_ALT0.SW2END0 !22_07 !23_07 !24_07 16_07 25_07
INT_L.BYP_ALT0.VCC_WIRE 31_02 31_26 31_37 31_62
INT_L.BYP_ALT0.WL1END0 !23_07 17_07 22_07 24_07 25_07
INT_L.BYP_ALT0.WR1END0 !22_07 16_07 23_07 24_07 25_07
INT_L.BYP_ALT0.WW2END_N0_3 !22_07 !23_07 !25_07 17_07 24_07
@ -44,7 +43,6 @@ INT_L.BYP_ALT1.SL1END0 !23_15 19_14 22_15 24_15 25_15
INT_L.BYP_ALT1.SR1BEG_S0 !22_15 18_14 23_15 24_15 25_15
INT_L.BYP_ALT1.SS2END0 !22_15 !23_15 !25_15 19_14 24_15
INT_L.BYP_ALT1.SW2END0 !22_15 !23_15 !24_15 19_14 25_15
INT_L.BYP_ALT1.VCC_WIRE 30_02 30_25 30_37 30_60
INT_L.BYP_ALT1.WL1END0 !23_15 16_15 22_15 24_15 25_15
INT_L.BYP_ALT1.WR1END1 !22_15 17_15 23_15 24_15 25_15
INT_L.BYP_ALT1.WW2END0 !22_15 !23_15 !25_15 18_14 24_15

2
artix7/segbits_int_r.db
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@ -19,7 +19,6 @@ INT_R.BYP_ALT0.SL1END0 !23_07 19_06 22_07 24_07 25_07
INT_R.BYP_ALT0.SR1END_N3_3 !22_07 18_06 23_07 24_07 25_07
INT_R.BYP_ALT0.SS2END0 !22_07 !23_07 !25_07 16_07 24_07
INT_R.BYP_ALT0.SW2END0 !22_07 !23_07 !24_07 16_07 25_07
INT_R.BYP_ALT0.VCC_WIRE 31_02 31_26 31_37 31_62
INT_R.BYP_ALT0.WL1END0 !23_07 17_07 22_07 24_07 25_07
INT_R.BYP_ALT0.WR1END0 !22_07 16_07 23_07 24_07 25_07
INT_R.BYP_ALT0.WW2END_N0_3 !22_07 !23_07 !25_07 17_07 24_07
@ -44,7 +43,6 @@ INT_R.BYP_ALT1.SL1END0 !23_15 19_14 22_15 24_15 25_15
INT_R.BYP_ALT1.SR1BEG_S0 !22_15 18_14 23_15 24_15 25_15
INT_R.BYP_ALT1.SS2END0 !22_15 !23_15 !25_15 19_14 24_15
INT_R.BYP_ALT1.SW2END0 !22_15 !23_15 !24_15 19_14 25_15
INT_R.BYP_ALT1.VCC_WIRE 30_02 30_25 30_37 30_60
INT_R.BYP_ALT1.WL1END0 !23_15 16_15 22_15 24_15 25_15
INT_R.BYP_ALT1.WR1END1 !22_15 17_15 23_15 24_15 25_15
INT_R.BYP_ALT1.WW2END0 !22_15 !23_15 !25_15 18_14 24_15