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prjxray-db
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Updating Kintex DB based on "Merge pull request #275 from mcmasterg/rempips". 

See [Info File](Info.md) for details.

Signed-off-by: Tim 'mithro' Ansell <me@mith.ro>
This commit is contained in:
Tim 'mithro' Ansell 2018-12-06 21:23:53 +00:00
parent 04e855b7ce
commit 9fdc601ebf
44 changed files with 529402 additions and 519392 deletions
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69
Info.md
View File

@ -298,14 +298,17 @@ Results have checksums;
### Settings
Created using following [settings.sh (sha256: 555d484e8c10c35897ac446eb7a1bbebf0606c56dcd19caa9c8d916bb77cad64)](https://github.com/SymbiFlow/prjxray/blob/b43bf3539f51ed8a755ae245682cd660ca23d813/database/kintex7/settings.sh)
Created using following [settings.sh (sha256: 63265e0520e5cc4aa92f47568fe01fdfd80c95fe76bb0a7fc3aefb3e1933ff45)](https://github.com/SymbiFlow/prjxray/blob/afe50c68c464c0cd4a3fa92b6a07c9abbe41682f/database/kintex7/settings.sh)
```shell
export XRAY_DATABASE="kintex7"
export XRAY_PART="xc7k70tfbg676-2"
export XRAY_ROI_FRAMES="0x00000000:0xffffffff"
export XRAY_ROI="SLICE_X0Y50:SLICE_X19Y99 DSP48_X0Y20:DSP48_X0Y39 RAMB18_X0Y20:RAMB18_X0Y39 RAMB36_X0Y10:RAMB36_X0Y19"
# FIXME: make entire part
export XRAY_ROI_TILEGRID="SLICE_X0Y50:SLICE_X19Y99 DSP48_X0Y20:DSP48_X0Y39 RAMB18_X0Y20:RAMB18_X0Y39 RAMB36_X0Y10:RAMB36_X0Y19"
# These settings must remain in sync
export XRAY_ROI="SLICE_X0Y50:SLICE_X19Y99 DSP48_X0Y20:DSP48_X0Y39 RAMB18_X0Y20:RAMB18_X0Y39 RAMB36_X0Y10:RAMB36_X0Y19"
# Part of CMT X0Y1
export XRAY_ROI_GRID_X1="9"
export XRAY_ROI_GRID_X2="38"
@ -330,36 +333,12 @@ source $(dirname ${BASH_SOURCE[0]})/../../utils/environment.sh
Results have checksums;
* [`d154b5fc62e0ae17091b880050a7302f4f75fed1008967eb88e2c1e3f13f4792 ./kintex7/element_counts.csv`](./kintex7/element_counts.csv)
* [`6f6dd0ba33fdd78d87f8591adbff5aad2d3653a1b1fa03d77079ce64a7c1f175 ./kintex7/mask_bram0_l.db`](./kintex7/mask_bram0_l.db)
* [`9d12bc3be758587479874bff531ad702f429a963518d7bc5b2b3c0400ded4c6a ./kintex7/mask_bram0_r.db`](./kintex7/mask_bram0_r.db)
* [`6f6dd0ba33fdd78d87f8591adbff5aad2d3653a1b1fa03d77079ce64a7c1f175 ./kintex7/mask_bram1_l.db`](./kintex7/mask_bram1_l.db)
* [`9d12bc3be758587479874bff531ad702f429a963518d7bc5b2b3c0400ded4c6a ./kintex7/mask_bram1_r.db`](./kintex7/mask_bram1_r.db)
* [`6f6dd0ba33fdd78d87f8591adbff5aad2d3653a1b1fa03d77079ce64a7c1f175 ./kintex7/mask_bram2_l.db`](./kintex7/mask_bram2_l.db)
* [`9d12bc3be758587479874bff531ad702f429a963518d7bc5b2b3c0400ded4c6a ./kintex7/mask_bram2_r.db`](./kintex7/mask_bram2_r.db)
* [`6f6dd0ba33fdd78d87f8591adbff5aad2d3653a1b1fa03d77079ce64a7c1f175 ./kintex7/mask_bram3_l.db`](./kintex7/mask_bram3_l.db)
* [`9d12bc3be758587479874bff531ad702f429a963518d7bc5b2b3c0400ded4c6a ./kintex7/mask_bram3_r.db`](./kintex7/mask_bram3_r.db)
* [`6f6dd0ba33fdd78d87f8591adbff5aad2d3653a1b1fa03d77079ce64a7c1f175 ./kintex7/mask_bram4_l.db`](./kintex7/mask_bram4_l.db)
* [`9d12bc3be758587479874bff531ad702f429a963518d7bc5b2b3c0400ded4c6a ./kintex7/mask_bram4_r.db`](./kintex7/mask_bram4_r.db)
* [`5d8e00a868cba3369bf2d5696d6871695967cb2a42f6464cb366dcef5d7d48e7 ./kintex7/mask_bram_l.db`](./kintex7/mask_bram_l.db)
* [`5d8e00a868cba3369bf2d5696d6871695967cb2a42f6464cb366dcef5d7d48e7 ./kintex7/mask_bram_r.db`](./kintex7/mask_bram_r.db)
* [`5c274320294201935a3edccb43eca8e347ca1f0acded71ec388c794877d4b55b ./kintex7/mask_clbll_l.db`](./kintex7/mask_clbll_l.db)
* [`5c274320294201935a3edccb43eca8e347ca1f0acded71ec388c794877d4b55b ./kintex7/mask_clbll_r.db`](./kintex7/mask_clbll_r.db)
* [`5c274320294201935a3edccb43eca8e347ca1f0acded71ec388c794877d4b55b ./kintex7/mask_clblm_l.db`](./kintex7/mask_clblm_l.db)
* [`5c274320294201935a3edccb43eca8e347ca1f0acded71ec388c794877d4b55b ./kintex7/mask_clblm_r.db`](./kintex7/mask_clblm_r.db)
* [`6f6dd0ba33fdd78d87f8591adbff5aad2d3653a1b1fa03d77079ce64a7c1f175 ./kintex7/mask_dsp0_l.db`](./kintex7/mask_dsp0_l.db)
* [`9d12bc3be758587479874bff531ad702f429a963518d7bc5b2b3c0400ded4c6a ./kintex7/mask_dsp0_r.db`](./kintex7/mask_dsp0_r.db)
* [`6f6dd0ba33fdd78d87f8591adbff5aad2d3653a1b1fa03d77079ce64a7c1f175 ./kintex7/mask_dsp1_l.db`](./kintex7/mask_dsp1_l.db)
* [`9d12bc3be758587479874bff531ad702f429a963518d7bc5b2b3c0400ded4c6a ./kintex7/mask_dsp1_r.db`](./kintex7/mask_dsp1_r.db)
* [`6f6dd0ba33fdd78d87f8591adbff5aad2d3653a1b1fa03d77079ce64a7c1f175 ./kintex7/mask_dsp2_l.db`](./kintex7/mask_dsp2_l.db)
* [`9d12bc3be758587479874bff531ad702f429a963518d7bc5b2b3c0400ded4c6a ./kintex7/mask_dsp2_r.db`](./kintex7/mask_dsp2_r.db)
* [`6f6dd0ba33fdd78d87f8591adbff5aad2d3653a1b1fa03d77079ce64a7c1f175 ./kintex7/mask_dsp3_l.db`](./kintex7/mask_dsp3_l.db)
* [`9d12bc3be758587479874bff531ad702f429a963518d7bc5b2b3c0400ded4c6a ./kintex7/mask_dsp3_r.db`](./kintex7/mask_dsp3_r.db)
* [`6f6dd0ba33fdd78d87f8591adbff5aad2d3653a1b1fa03d77079ce64a7c1f175 ./kintex7/mask_dsp4_l.db`](./kintex7/mask_dsp4_l.db)
* [`9d12bc3be758587479874bff531ad702f429a963518d7bc5b2b3c0400ded4c6a ./kintex7/mask_dsp4_r.db`](./kintex7/mask_dsp4_r.db)
* [`76a9286b89fa91babd4ab8b59156b12a7024130d66f9f08da290797d00a115e6 ./kintex7/mask_dsp_l.db`](./kintex7/mask_dsp_l.db)
* [`76a9286b89fa91babd4ab8b59156b12a7024130d66f9f08da290797d00a115e6 ./kintex7/mask_dsp_r.db`](./kintex7/mask_dsp_r.db)
* [`76d1e0bd4b7ad492cf3fe8698b2b5f46f7dcc5fe446984e5dccae373c63edafd ./kintex7/mask_hclk_l.db`](./kintex7/mask_hclk_l.db)
* [`76d1e0bd4b7ad492cf3fe8698b2b5f46f7dcc5fe446984e5dccae373c63edafd ./kintex7/mask_hclk_r.db`](./kintex7/mask_hclk_r.db)
* [`2f2a37cca066562d79b6a7ecc89ff750c30db2cb355c0665379b356c7c8d41bd ./kintex7/mask_clbll_l.db`](./kintex7/mask_clbll_l.db)
* [`48d52092f62239a82141b89539c690a405a54822ba04d0e284d9ffd300811d8c ./kintex7/mask_clbll_r.db`](./kintex7/mask_clbll_r.db)
* [`2f2a37cca066562d79b6a7ecc89ff750c30db2cb355c0665379b356c7c8d41bd ./kintex7/mask_clblm_l.db`](./kintex7/mask_clblm_l.db)
* [`48d52092f62239a82141b89539c690a405a54822ba04d0e284d9ffd300811d8c ./kintex7/mask_clblm_r.db`](./kintex7/mask_clblm_r.db)
* [`c5aabee9a52c0eb671d569264639b6903e85e76e50ce57af8b7033062e81c2f5 ./kintex7/mask_hclk_l.db`](./kintex7/mask_hclk_l.db)
* [`c5aabee9a52c0eb671d569264639b6903e85e76e50ce57af8b7033062e81c2f5 ./kintex7/mask_hclk_r.db`](./kintex7/mask_hclk_r.db)
* [`6baea72435613b87334f95cfe2b1ab36da4d57ada20b71a7dd870715b3e430c4 ./kintex7/ppips_clbll_l.db`](./kintex7/ppips_clbll_l.db)
* [`3955d590e8ee64c843bb80f911a08781c1bac63e71b577436ae1f44195a88e22 ./kintex7/ppips_clbll_r.db`](./kintex7/ppips_clbll_r.db)
* [`29f175153821dc13989eb580676ff0007e108d911275a74e7ebe45e819c14eaf ./kintex7/ppips_clblm_l.db`](./kintex7/ppips_clblm_l.db)
@ -368,19 +347,19 @@ Results have checksums;
* [`81e0696179a33bdf8d2279a53b406911a403d50224355e9ad29eccee01a70305 ./kintex7/ppips_hclk_r.db`](./kintex7/ppips_hclk_r.db)
* [`be617c15d1ec311b6249791414bbd69380fe90b476353cbb2fc2a7cb06f5029d ./kintex7/ppips_int_l.db`](./kintex7/ppips_int_l.db)
* [`a1423859c97a82dcfb114644f50b991db4ca7e0996e6d1ae4d2c97bfdfcb723d ./kintex7/ppips_int_r.db`](./kintex7/ppips_int_r.db)
* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./kintex7/segbits_bram_l.block_ram.db`](./kintex7/segbits_bram_l.block_ram.db)
* [`b3011b6a49b05f1f0a40b499537d0f3eb208a51b87d6d97811911df50d4ad2d2 ./kintex7/segbits_bram_l.db`](./kintex7/segbits_bram_l.db)
* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./kintex7/segbits_bram_r.block_ram.db`](./kintex7/segbits_bram_r.block_ram.db)
* [`ac4e1c029ed8e623985ca2665e7aa1fae57aa2b33defb5f8cfa17d34d160e4b1 ./kintex7/segbits_bram_r.db`](./kintex7/segbits_bram_r.db)
* [`7591abf4d35e031e0d35cb8fdfe77c2b7d0f2840625c105977108e08451857f4 ./kintex7/segbits_clbll_l.db`](./kintex7/segbits_clbll_l.db)
* [`9a23ca5a568841b282c0207ed4cfe70925b0d5c4bbf232e5ee5697123082078c ./kintex7/segbits_clbll_r.db`](./kintex7/segbits_clbll_r.db)
* [`10f499474dc8b6c4b051291d70aedadfb9902219079553eefbbc64dabfd78a06 ./kintex7/segbits_clblm_l.db`](./kintex7/segbits_clblm_l.db)
* [`4c3a3a92b4bb860098596ce8d4a6fd869aff59705dc5d5049ce97ee70f6d39ac ./kintex7/segbits_clblm_r.db`](./kintex7/segbits_clblm_r.db)
* [`7966925d50ebf5296f273ac64d03614ce0f452209bc0a4bde2e3d30f2fbd9a53 ./kintex7/segbits_bram_l.block_ram.db`](./kintex7/segbits_bram_l.block_ram.db)
* [`aaa1d706495108244ce39af259fe7a0b636f3e5e0d911e2bce23f904d8816f1a ./kintex7/segbits_bram_l.db`](./kintex7/segbits_bram_l.db)
* [`7b958779367cfa8ab94fc1358241bf2704f0f165eb7809653d527ecef77bb6b1 ./kintex7/segbits_bram_r.block_ram.db`](./kintex7/segbits_bram_r.block_ram.db)
* [`c5335d22c23e0ef7dc23d66388d9586fef598680d429f96d4308a21a345edc22 ./kintex7/segbits_bram_r.db`](./kintex7/segbits_bram_r.db)
* [`6ebf61394acdcf59009aa7f43248d87aaabde0bd13db4e64d180d6efeb32e4f9 ./kintex7/segbits_clbll_l.db`](./kintex7/segbits_clbll_l.db)
* [`f9165aded2d9ee5b60cda1bf043e38fd70f984f190cdf8f52aff7118ac07575d ./kintex7/segbits_clbll_r.db`](./kintex7/segbits_clbll_r.db)
* [`b2cb977a0bbdcbe3aab6b7bc162776799a2b9ada25b4f937b57073a906e8d167 ./kintex7/segbits_clblm_l.db`](./kintex7/segbits_clblm_l.db)
* [`6ed746de31fb69b018835239edcf191945982e9b705711e4b174031838b3bc90 ./kintex7/segbits_clblm_r.db`](./kintex7/segbits_clblm_r.db)
* [`df496c4d335fac0c379497ff0a75ba4f5c5c25bcce79f9c7a72d5f08066310db ./kintex7/segbits_hclk_l.db`](./kintex7/segbits_hclk_l.db)
* [`5e22f758a04eab3185b2453c9994aa2fa48f50ca8a6b49bf82e8fc4351f23a5c ./kintex7/segbits_hclk_r.db`](./kintex7/segbits_hclk_r.db)
* [`51b25643ef3b8a7a90181ad61199cd70ac8c5baa18ee1aacd2e81ff50ccdbfcf ./kintex7/segbits_int_l.db`](./kintex7/segbits_int_l.db)
* [`05d1165f911881b3600b01f86cad9a6618c8b0dadb7014def3145f9254fd0c45 ./kintex7/segbits_int_r.db`](./kintex7/segbits_int_r.db)
* [`555d484e8c10c35897ac446eb7a1bbebf0606c56dcd19caa9c8d916bb77cad64 ./kintex7/settings.sh`](./kintex7/settings.sh)
* [`e1628ab6bdb2e040f019041a57101eff46a46b7d9010c5662b28570fddc26463 ./kintex7/segbits_int_l.db`](./kintex7/segbits_int_l.db)
* [`9f72ee9d65e9b05274b85cf1ef47bbb7438eb127925f11b23733736e25e2fec8 ./kintex7/segbits_int_r.db`](./kintex7/segbits_int_r.db)
* [`63265e0520e5cc4aa92f47568fe01fdfd80c95fe76bb0a7fc3aefb3e1933ff45 ./kintex7/settings.sh`](./kintex7/settings.sh)
* [`6a998dd55a7aa4ab33db25db7b5167d57f3d708713baf1fca394dc2940f12007 ./kintex7/site_type_BSCAN.json`](./kintex7/site_type_BSCAN.json)
* [`7f59ea08fa5dbf9ce84ea26f03f13cd02683fce9cdd98621e501e422bf09d165 ./kintex7/site_type_BUFGCTRL.json`](./kintex7/site_type_BUFGCTRL.json)
* [`2d6c78790d74503f0810356de3a765b380b319f09a41593bc8cbe8979defd1f7 ./kintex7/site_type_BUFHCE.json`](./kintex7/site_type_BUFHCE.json)
@ -432,8 +411,8 @@ Results have checksums;
* [`db8c88384575a7e0562692550bdba7a4089ea5fabe451bf58403d3a85af419a0 ./kintex7/site_type_TIEOFF.json`](./kintex7/site_type_TIEOFF.json)
* [`4d6130cb2604efae8ca5d628b95be2549083c16c639d335bdc906924e37ec28c ./kintex7/site_type_USR_ACCESS.json`](./kintex7/site_type_USR_ACCESS.json)
* [`dbf0ff3b27d1fac02572351765f1b17b3e950ed4e8fe95ac6bcd71012e4f7b2d ./kintex7/site_type_XADC.json`](./kintex7/site_type_XADC.json)
* [`7f9142831f091d653501a1179b597502fa831e744b5392bab6a8bdd8f7827f50 ./kintex7/tileconn.json`](./kintex7/tileconn.json)
* [`2ccb101556ecee8ad729fbdd2dcbca296beb0cddc1755f649de3255cbaa51b2f ./kintex7/tilegrid.json`](./kintex7/tilegrid.json)
* [`46f7c8b9fcb943f16d55e233c5ac3c31089e55b1ccb89b8c38c18cb068af6111 ./kintex7/tileconn.json`](./kintex7/tileconn.json)
* [`eeef94852cdce206d5958d0d2e5754459cfb2e7c843c12871718bea8e202daa3 ./kintex7/tilegrid.json`](./kintex7/tilegrid.json)
* [`a93b4be2b2832d1a9240b892f6d8db469f3d9cf6229cc6856a197e854f4abc8a ./kintex7/tile_type_BRAM_INT_INTERFACE_L.json`](./kintex7/tile_type_BRAM_INT_INTERFACE_L.json)
* [`fff3e640e286158767fc484ec932d0ce7eba48c1168798c11c7779426a846004 ./kintex7/tile_type_BRAM_INT_INTERFACE_R.json`](./kintex7/tile_type_BRAM_INT_INTERFACE_R.json)
* [`fe1ba3b913bc91940d08dc034ef0c5ad7d530d15b5458c7240abedb4400c52ad ./kintex7/tile_type_BRAM_L.json`](./kintex7/tile_type_BRAM_L.json)

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@ -11,24 +11,17 @@ bit 00_09
bit 00_10
bit 00_11
bit 00_12
bit 00_13
bit 00_14
bit 00_15
bit 00_16
bit 00_17
bit 00_18
bit 00_19
bit 00_20
bit 00_21
bit 00_22
bit 00_23
bit 00_24
bit 00_25
bit 00_26
bit 00_27
bit 00_28
bit 00_29
bit 00_30
bit 00_32
bit 00_33
bit 00_34
@ -37,7 +30,6 @@ bit 00_36
bit 00_37
bit 00_38
bit 00_39
bit 00_40
bit 00_41
bit 00_42
bit 00_43
@ -46,20 +38,11 @@ bit 00_45
bit 00_46
bit 00_47
bit 00_48
bit 00_49
bit 00_50
bit 00_51
bit 00_52
bit 00_53
bit 00_54
bit 00_55
bit 00_56
bit 00_57
bit 00_58
bit 00_59
bit 00_61
bit 00_62
bit 00_63
bit 01_00
bit 01_01
bit 01_02
@ -72,23 +55,15 @@ bit 01_08
bit 01_09
bit 01_10
bit 01_11
bit 01_12
bit 01_13
bit 01_14
bit 01_15
bit 01_16
bit 01_17
bit 01_18
bit 01_19
bit 01_20
bit 01_21
bit 01_22
bit 01_23
bit 01_24
bit 01_25
bit 01_26
bit 01_27
bit 01_28
bit 01_29
bit 01_31
bit 01_32
@ -108,19 +83,11 @@ bit 01_45
bit 01_46
bit 01_47
bit 01_48
bit 01_49
bit 01_50
bit 01_51
bit 01_52
bit 01_53
bit 01_54
bit 01_55
bit 01_56
bit 01_57
bit 01_58
bit 01_59
bit 01_60
bit 01_61
bit 01_62
bit 02_01
bit 02_02
@ -1898,8 +1865,6 @@ bit 30_12
bit 30_13
bit 30_14
bit 30_15
bit 30_16
bit 30_17
bit 30_18
bit 30_19
bit 30_20
@ -1913,7 +1878,6 @@ bit 30_27
bit 30_28
bit 30_29
bit 30_30
bit 30_32
bit 30_33
bit 30_34
bit 30_35
@ -1927,8 +1891,6 @@ bit 30_42
bit 30_43
bit 30_44
bit 30_45
bit 30_46
bit 30_47
bit 30_48
bit 30_49
bit 30_50
@ -1975,7 +1937,6 @@ bit 31_27
bit 31_28
bit 31_29
bit 31_30
bit 31_32
bit 31_33
bit 31_34
bit 31_35

40
kintex7/mask_clbll_r.db
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@ -11,24 +11,17 @@ bit 00_09
bit 00_10
bit 00_11
bit 00_12
bit 00_13
bit 00_14
bit 00_15
bit 00_16
bit 00_17
bit 00_18
bit 00_19
bit 00_20
bit 00_21
bit 00_22
bit 00_23
bit 00_24
bit 00_25
bit 00_26
bit 00_27
bit 00_28
bit 00_29
bit 00_30
bit 00_32
bit 00_33
bit 00_34
@ -37,7 +30,6 @@ bit 00_36
bit 00_37
bit 00_38
bit 00_39
bit 00_40
bit 00_41
bit 00_42
bit 00_43
@ -46,20 +38,11 @@ bit 00_45
bit 00_46
bit 00_47
bit 00_48
bit 00_49
bit 00_50
bit 00_51
bit 00_52
bit 00_53
bit 00_54
bit 00_55
bit 00_56
bit 00_57
bit 00_58
bit 00_59
bit 00_61
bit 00_62
bit 00_63
bit 01_00
bit 01_01
bit 01_02
@ -72,23 +55,15 @@ bit 01_08
bit 01_09
bit 01_10
bit 01_11
bit 01_12
bit 01_13
bit 01_14
bit 01_15
bit 01_16
bit 01_17
bit 01_18
bit 01_19
bit 01_20
bit 01_21
bit 01_22
bit 01_23
bit 01_24
bit 01_25
bit 01_26
bit 01_27
bit 01_28
bit 01_29
bit 01_31
bit 01_32
@ -104,24 +79,15 @@ bit 01_41
bit 01_42
bit 01_43
bit 01_44
bit 01_45
bit 01_46
bit 01_47
bit 01_48
bit 01_49
bit 01_50
bit 01_51
bit 01_52
bit 01_53
bit 01_54
bit 01_55
bit 01_56
bit 01_57
bit 01_58
bit 01_59
bit 01_60
bit 01_61
bit 01_62
bit 02_01
bit 02_02
bit 02_03
@ -1898,8 +1864,6 @@ bit 30_12
bit 30_13
bit 30_14
bit 30_15
bit 30_16
bit 30_17
bit 30_18
bit 30_19
bit 30_20
@ -1913,7 +1877,6 @@ bit 30_27
bit 30_28
bit 30_29
bit 30_30
bit 30_32
bit 30_33
bit 30_34
bit 30_35
@ -1927,8 +1890,6 @@ bit 30_42
bit 30_43
bit 30_44
bit 30_45
bit 30_46
bit 30_47
bit 30_48
bit 30_49
bit 30_50
@ -1975,7 +1936,6 @@ bit 31_27
bit 31_28
bit 31_29
bit 31_30
bit 31_32
bit 31_33
bit 31_34
bit 31_35

39
kintex7/mask_clblm_l.db
View File

@ -11,24 +11,17 @@ bit 00_09
bit 00_10
bit 00_11
bit 00_12
bit 00_13
bit 00_14
bit 00_15
bit 00_16
bit 00_17
bit 00_18
bit 00_19
bit 00_20
bit 00_21
bit 00_22
bit 00_23
bit 00_24
bit 00_25
bit 00_26
bit 00_27
bit 00_28
bit 00_29
bit 00_30
bit 00_32
bit 00_33
bit 00_34
@ -37,7 +30,6 @@ bit 00_36
bit 00_37
bit 00_38
bit 00_39
bit 00_40
bit 00_41
bit 00_42
bit 00_43
@ -46,20 +38,11 @@ bit 00_45
bit 00_46
bit 00_47
bit 00_48
bit 00_49
bit 00_50
bit 00_51
bit 00_52
bit 00_53
bit 00_54
bit 00_55
bit 00_56
bit 00_57
bit 00_58
bit 00_59
bit 00_61
bit 00_62
bit 00_63
bit 01_00
bit 01_01
bit 01_02
@ -72,23 +55,15 @@ bit 01_08
bit 01_09
bit 01_10
bit 01_11
bit 01_12
bit 01_13
bit 01_14
bit 01_15
bit 01_16
bit 01_17
bit 01_18
bit 01_19
bit 01_20
bit 01_21
bit 01_22
bit 01_23
bit 01_24
bit 01_25
bit 01_26
bit 01_27
bit 01_28
bit 01_29
bit 01_31
bit 01_32
@ -108,19 +83,11 @@ bit 01_45
bit 01_46
bit 01_47
bit 01_48
bit 01_49
bit 01_50
bit 01_51
bit 01_52
bit 01_53
bit 01_54
bit 01_55
bit 01_56
bit 01_57
bit 01_58
bit 01_59
bit 01_60
bit 01_61
bit 01_62
bit 02_01
bit 02_02
@ -1898,8 +1865,6 @@ bit 30_12
bit 30_13
bit 30_14
bit 30_15
bit 30_16
bit 30_17
bit 30_18
bit 30_19
bit 30_20
@ -1913,7 +1878,6 @@ bit 30_27
bit 30_28
bit 30_29
bit 30_30
bit 30_32
bit 30_33
bit 30_34
bit 30_35
@ -1927,8 +1891,6 @@ bit 30_42
bit 30_43
bit 30_44
bit 30_45
bit 30_46
bit 30_47
bit 30_48
bit 30_49
bit 30_50
@ -1975,7 +1937,6 @@ bit 31_27
bit 31_28
bit 31_29
bit 31_30
bit 31_32
bit 31_33
bit 31_34
bit 31_35

40
kintex7/mask_clblm_r.db
View File

@ -11,24 +11,17 @@ bit 00_09
bit 00_10
bit 00_11
bit 00_12
bit 00_13
bit 00_14
bit 00_15
bit 00_16
bit 00_17
bit 00_18
bit 00_19
bit 00_20
bit 00_21
bit 00_22
bit 00_23
bit 00_24
bit 00_25
bit 00_26
bit 00_27
bit 00_28
bit 00_29
bit 00_30
bit 00_32
bit 00_33
bit 00_34
@ -37,7 +30,6 @@ bit 00_36
bit 00_37
bit 00_38
bit 00_39
bit 00_40
bit 00_41
bit 00_42
bit 00_43
@ -46,20 +38,11 @@ bit 00_45
bit 00_46
bit 00_47
bit 00_48
bit 00_49
bit 00_50
bit 00_51
bit 00_52
bit 00_53
bit 00_54
bit 00_55
bit 00_56
bit 00_57
bit 00_58
bit 00_59
bit 00_61
bit 00_62
bit 00_63
bit 01_00
bit 01_01
bit 01_02
@ -72,23 +55,15 @@ bit 01_08
bit 01_09
bit 01_10
bit 01_11
bit 01_12
bit 01_13
bit 01_14
bit 01_15
bit 01_16
bit 01_17
bit 01_18
bit 01_19
bit 01_20
bit 01_21
bit 01_22
bit 01_23
bit 01_24
bit 01_25
bit 01_26
bit 01_27
bit 01_28
bit 01_29
bit 01_31
bit 01_32
@ -104,24 +79,15 @@ bit 01_41
bit 01_42
bit 01_43
bit 01_44
bit 01_45
bit 01_46
bit 01_47
bit 01_48
bit 01_49
bit 01_50
bit 01_51
bit 01_52
bit 01_53
bit 01_54
bit 01_55
bit 01_56
bit 01_57
bit 01_58
bit 01_59
bit 01_60
bit 01_61
bit 01_62
bit 02_01
bit 02_02
bit 02_03
@ -1898,8 +1864,6 @@ bit 30_12
bit 30_13
bit 30_14
bit 30_15
bit 30_16
bit 30_17
bit 30_18
bit 30_19
bit 30_20
@ -1913,7 +1877,6 @@ bit 30_27
bit 30_28
bit 30_29
bit 30_30
bit 30_32
bit 30_33
bit 30_34
bit 30_35
@ -1927,8 +1890,6 @@ bit 30_42
bit 30_43
bit 30_44
bit 30_45
bit 30_46
bit 30_47
bit 30_48
bit 30_49
bit 30_50
@ -1975,7 +1936,6 @@ bit 31_27
bit 31_28
bit 31_29
bit 31_30
bit 31_32
bit 31_33
bit 31_34
bit 31_35

1556
kintex7/mask_dsp0_l.db
View File

File diff suppressed because it is too large Load Diff

1557
kintex7/mask_dsp0_r.db
View File

File diff suppressed because it is too large Load Diff

1556
kintex7/mask_dsp1_l.db
View File

File diff suppressed because it is too large Load Diff

1557
kintex7/mask_dsp1_r.db
View File

File diff suppressed because it is too large Load Diff

1556
kintex7/mask_dsp2_l.db
View File

File diff suppressed because it is too large Load Diff

1557
kintex7/mask_dsp2_r.db
View File

File diff suppressed because it is too large Load Diff

1556
kintex7/mask_dsp3_l.db
View File

File diff suppressed because it is too large Load Diff

1557
kintex7/mask_dsp3_r.db
View File

File diff suppressed because it is too large Load Diff

1556
kintex7/mask_dsp4_l.db
View File

File diff suppressed because it is too large Load Diff

1557
kintex7/mask_dsp4_r.db
View File

File diff suppressed because it is too large Load Diff

8030
kintex7/mask_dsp_l.db
View File

File diff suppressed because it is too large Load Diff

8030
kintex7/mask_dsp_r.db
View File

File diff suppressed because it is too large Load Diff

2
kintex7/mask_hclk_l.db
View File

@ -102,3 +102,5 @@ bit 05_28
bit 05_29
bit 05_30
bit 05_31
bit <0
bit candidates>

2
kintex7/mask_hclk_r.db
View File

@ -102,3 +102,5 @@ bit 05_28
bit 05_29
bit 05_30
bit 05_31
bit <0
bit candidates>

36864
kintex7/segbits_bram_l.block_ram.db
View File

File diff suppressed because it is too large Load Diff

72
kintex7/segbits_bram_l.db
View File

@ -2,12 +2,12 @@ BRAM_L.RAMB18_Y0.INIT_A[0] 27_73
BRAM_L.RAMB18_Y0.INIT_A[10] 27_129
BRAM_L.RAMB18_Y0.INIT_A[11] 27_113
BRAM_L.RAMB18_Y0.INIT_A[12] 27_97
BRAM_L.RAMB18_Y0.INIT_A[1] 27_65
BRAM_L.RAMB18_Y0.INIT_A[13] 27_81
BRAM_L.RAMB18_Y0.INIT_A[14] 27_49
BRAM_L.RAMB18_Y0.INIT_A[15] 27_33
BRAM_L.RAMB18_Y0.INIT_A[16] 27_17
BRAM_L.RAMB18_Y0.INIT_A[17] 27_01
BRAM_L.RAMB18_Y0.INIT_A[1] 27_65
BRAM_L.RAMB18_Y0.INIT_A[2] 27_137
BRAM_L.RAMB18_Y0.INIT_A[3] 27_121
BRAM_L.RAMB18_Y0.INIT_A[4] 27_105
@ -20,12 +20,12 @@ BRAM_L.RAMB18_Y0.INIT_B[0] 27_79
BRAM_L.RAMB18_Y0.INIT_B[10] 27_135
BRAM_L.RAMB18_Y0.INIT_B[11] 27_119
BRAM_L.RAMB18_Y0.INIT_B[12] 27_103
BRAM_L.RAMB18_Y0.INIT_B[1] 27_71
BRAM_L.RAMB18_Y0.INIT_B[13] 27_87
BRAM_L.RAMB18_Y0.INIT_B[14] 27_55
BRAM_L.RAMB18_Y0.INIT_B[15] 27_39
BRAM_L.RAMB18_Y0.INIT_B[16] 27_23
BRAM_L.RAMB18_Y0.INIT_B[17] 27_07
BRAM_L.RAMB18_Y0.INIT_B[1] 27_71
BRAM_L.RAMB18_Y0.INIT_B[2] 27_143
BRAM_L.RAMB18_Y0.INIT_B[3] 27_127
BRAM_L.RAMB18_Y0.INIT_B[4] 27_111
@ -34,22 +34,24 @@ BRAM_L.RAMB18_Y0.INIT_B[6] 27_63
BRAM_L.RAMB18_Y0.INIT_B[7] 27_47
BRAM_L.RAMB18_Y0.INIT_B[8] 27_31
BRAM_L.RAMB18_Y0.INIT_B[9] 27_15
BRAM_L.RAMB18_Y0.READ_WIDTH_A_B0 27_35
BRAM_L.RAMB18_Y0.READ_WIDTH_A_B1 27_36
BRAM_L.RAMB18_Y0.READ_WIDTH_A_B2 27_37
BRAM_L.RAMB18_Y0.READ_WIDTH_B_B0 27_43
BRAM_L.RAMB18_Y0.READ_WIDTH_B_B1 27_44
BRAM_L.RAMB18_Y0.READ_WIDTH_B_B2 27_45
BRAM_L.RAMB18_Y0.READ_WIDTH_A_18 !27_35 !27_36 27_37
BRAM_L.RAMB18_Y0.READ_WIDTH_A_2 !27_36 !27_37 27_35
BRAM_L.RAMB18_Y0.READ_WIDTH_A_4 !27_35 !27_37 27_36
BRAM_L.RAMB18_Y0.READ_WIDTH_A_9 !27_37 27_35 27_36
BRAM_L.RAMB18_Y0.READ_WIDTH_B_18 !27_43 !27_44 27_45
BRAM_L.RAMB18_Y0.READ_WIDTH_B_2 !27_44 !27_45 27_43
BRAM_L.RAMB18_Y0.READ_WIDTH_B_4 !27_43 !27_45 27_44
BRAM_L.RAMB18_Y0.READ_WIDTH_B_9 !27_45 27_43 27_44
BRAM_L.RAMB18_Y0.SRVAL_A[0] 27_74
BRAM_L.RAMB18_Y0.SRVAL_A[10] 27_130
BRAM_L.RAMB18_Y0.SRVAL_A[11] 27_114
BRAM_L.RAMB18_Y0.SRVAL_A[12] 27_98
BRAM_L.RAMB18_Y0.SRVAL_A[1] 27_66
BRAM_L.RAMB18_Y0.SRVAL_A[13] 27_82
BRAM_L.RAMB18_Y0.SRVAL_A[14] 27_50
BRAM_L.RAMB18_Y0.SRVAL_A[15] 27_34
BRAM_L.RAMB18_Y0.SRVAL_A[16] 27_18
BRAM_L.RAMB18_Y0.SRVAL_A[17] 27_02
BRAM_L.RAMB18_Y0.SRVAL_A[1] 27_66
BRAM_L.RAMB18_Y0.SRVAL_A[2] 27_138
BRAM_L.RAMB18_Y0.SRVAL_A[3] 27_122
BRAM_L.RAMB18_Y0.SRVAL_A[4] 27_106
@ -62,12 +64,12 @@ BRAM_L.RAMB18_Y0.SRVAL_B[0] 27_78
BRAM_L.RAMB18_Y0.SRVAL_B[10] 27_134
BRAM_L.RAMB18_Y0.SRVAL_B[11] 27_118
BRAM_L.RAMB18_Y0.SRVAL_B[12] 27_102
BRAM_L.RAMB18_Y0.SRVAL_B[1] 27_70
BRAM_L.RAMB18_Y0.SRVAL_B[13] 27_86
BRAM_L.RAMB18_Y0.SRVAL_B[14] 27_54
BRAM_L.RAMB18_Y0.SRVAL_B[15] 27_38
BRAM_L.RAMB18_Y0.SRVAL_B[16] 27_22
BRAM_L.RAMB18_Y0.SRVAL_B[17] 27_06
BRAM_L.RAMB18_Y0.SRVAL_B[1] 27_70
BRAM_L.RAMB18_Y0.SRVAL_B[2] 27_142
BRAM_L.RAMB18_Y0.SRVAL_B[3] 27_126
BRAM_L.RAMB18_Y0.SRVAL_B[4] 27_110
@ -80,12 +82,14 @@ BRAM_L.RAMB18_Y0.WRITE_MODE_A_NO_CHANGE 27_64
BRAM_L.RAMB18_Y0.WRITE_MODE_A_READ_FIRST 27_56
BRAM_L.RAMB18_Y0.WRITE_MODE_B_NO_CHANGE 27_68
BRAM_L.RAMB18_Y0.WRITE_MODE_B_READ_FIRST 27_67
BRAM_L.RAMB18_Y0.WRITE_WIDTH_A_B0 27_51
BRAM_L.RAMB18_Y0.WRITE_WIDTH_A_B1 27_52
BRAM_L.RAMB18_Y0.WRITE_WIDTH_A_B2 27_53
BRAM_L.RAMB18_Y0.WRITE_WIDTH_B_B0 27_59
BRAM_L.RAMB18_Y0.WRITE_WIDTH_B_B1 27_60
BRAM_L.RAMB18_Y0.WRITE_WIDTH_B_B2 27_61
BRAM_L.RAMB18_Y0.WRITE_WIDTH_A_18 !27_51 !27_52 27_53
BRAM_L.RAMB18_Y0.WRITE_WIDTH_A_2 !27_52 !27_53 27_51
BRAM_L.RAMB18_Y0.WRITE_WIDTH_A_4 !27_51 !27_53 27_52
BRAM_L.RAMB18_Y0.WRITE_WIDTH_A_9 !27_53 27_51 27_52
BRAM_L.RAMB18_Y0.WRITE_WIDTH_B_18 !27_59 !27_60 27_61
BRAM_L.RAMB18_Y0.WRITE_WIDTH_B_2 !27_60 !27_61 27_59
BRAM_L.RAMB18_Y0.WRITE_WIDTH_B_4 !27_59 !27_61 27_60
BRAM_L.RAMB18_Y0.WRITE_WIDTH_B_9 !27_61 27_59 27_60
BRAM_L.RAMB18_Y0.ZINV_CLKARDCLK 27_107
BRAM_L.RAMB18_Y0.ZINV_CLKBWRCLK 27_109
BRAM_L.RAMB18_Y0.ZINV_ENARDEN 27_112
@ -98,12 +102,12 @@ BRAM_L.RAMB18_Y1.INIT_A[0] 27_249
BRAM_L.RAMB18_Y1.INIT_A[10] 27_305
BRAM_L.RAMB18_Y1.INIT_A[11] 27_289
BRAM_L.RAMB18_Y1.INIT_A[12] 27_273
BRAM_L.RAMB18_Y1.INIT_A[1] 27_241
BRAM_L.RAMB18_Y1.INIT_A[13] 27_257
BRAM_L.RAMB18_Y1.INIT_A[14] 27_225
BRAM_L.RAMB18_Y1.INIT_A[15] 27_209
BRAM_L.RAMB18_Y1.INIT_A[16] 27_193
BRAM_L.RAMB18_Y1.INIT_A[17] 27_177
BRAM_L.RAMB18_Y1.INIT_A[1] 27_241
BRAM_L.RAMB18_Y1.INIT_A[2] 27_313
BRAM_L.RAMB18_Y1.INIT_A[3] 27_297
BRAM_L.RAMB18_Y1.INIT_A[4] 27_281
@ -116,12 +120,12 @@ BRAM_L.RAMB18_Y1.INIT_B[0] 27_255
BRAM_L.RAMB18_Y1.INIT_B[10] 27_311
BRAM_L.RAMB18_Y1.INIT_B[11] 27_295
BRAM_L.RAMB18_Y1.INIT_B[12] 27_279
BRAM_L.RAMB18_Y1.INIT_B[1] 27_247
BRAM_L.RAMB18_Y1.INIT_B[13] 27_263
BRAM_L.RAMB18_Y1.INIT_B[14] 27_231
BRAM_L.RAMB18_Y1.INIT_B[15] 27_215
BRAM_L.RAMB18_Y1.INIT_B[16] 27_199
BRAM_L.RAMB18_Y1.INIT_B[17] 27_183
BRAM_L.RAMB18_Y1.INIT_B[1] 27_247
BRAM_L.RAMB18_Y1.INIT_B[2] 27_319
BRAM_L.RAMB18_Y1.INIT_B[3] 27_303
BRAM_L.RAMB18_Y1.INIT_B[4] 27_287
@ -130,22 +134,24 @@ BRAM_L.RAMB18_Y1.INIT_B[6] 27_239
BRAM_L.RAMB18_Y1.INIT_B[7] 27_223
BRAM_L.RAMB18_Y1.INIT_B[8] 27_207
BRAM_L.RAMB18_Y1.INIT_B[9] 27_191
BRAM_L.RAMB18_Y1.READ_WIDTH_A_B0 27_285
BRAM_L.RAMB18_Y1.READ_WIDTH_A_B1 27_284
BRAM_L.RAMB18_Y1.READ_WIDTH_A_B2 27_283
BRAM_L.RAMB18_Y1.READ_WIDTH_B_B0 27_277
BRAM_L.RAMB18_Y1.READ_WIDTH_B_B1 27_276
BRAM_L.RAMB18_Y1.READ_WIDTH_B_B2 27_275
BRAM_L.RAMB18_Y1.READ_WIDTH_A_18 !27_284 !27_285 27_283
BRAM_L.RAMB18_Y1.READ_WIDTH_A_2 !27_283 !27_284 27_285
BRAM_L.RAMB18_Y1.READ_WIDTH_A_4 !27_283 !27_285 27_284
BRAM_L.RAMB18_Y1.READ_WIDTH_A_9 !27_283 27_284 27_285
BRAM_L.RAMB18_Y1.READ_WIDTH_B_18 !27_276 !27_277 27_275
BRAM_L.RAMB18_Y1.READ_WIDTH_B_2 !27_275 !27_276 27_277
BRAM_L.RAMB18_Y1.READ_WIDTH_B_4 !27_275 !27_277 27_276
BRAM_L.RAMB18_Y1.READ_WIDTH_B_9 !27_275 27_276 27_277
BRAM_L.RAMB18_Y1.SRVAL_A[0] 27_250
BRAM_L.RAMB18_Y1.SRVAL_A[10] 27_306
BRAM_L.RAMB18_Y1.SRVAL_A[11] 27_290
BRAM_L.RAMB18_Y1.SRVAL_A[12] 27_274
BRAM_L.RAMB18_Y1.SRVAL_A[1] 27_242
BRAM_L.RAMB18_Y1.SRVAL_A[13] 27_258
BRAM_L.RAMB18_Y1.SRVAL_A[14] 27_226
BRAM_L.RAMB18_Y1.SRVAL_A[15] 27_210
BRAM_L.RAMB18_Y1.SRVAL_A[16] 27_194
BRAM_L.RAMB18_Y1.SRVAL_A[17] 27_178
BRAM_L.RAMB18_Y1.SRVAL_A[1] 27_242
BRAM_L.RAMB18_Y1.SRVAL_A[2] 27_314
BRAM_L.RAMB18_Y1.SRVAL_A[3] 27_298
BRAM_L.RAMB18_Y1.SRVAL_A[4] 27_282
@ -158,12 +164,12 @@ BRAM_L.RAMB18_Y1.SRVAL_B[0] 27_254
BRAM_L.RAMB18_Y1.SRVAL_B[10] 27_310
BRAM_L.RAMB18_Y1.SRVAL_B[11] 27_294
BRAM_L.RAMB18_Y1.SRVAL_B[12] 27_278
BRAM_L.RAMB18_Y1.SRVAL_B[1] 27_246
BRAM_L.RAMB18_Y1.SRVAL_B[13] 27_262
BRAM_L.RAMB18_Y1.SRVAL_B[14] 27_230
BRAM_L.RAMB18_Y1.SRVAL_B[15] 27_214
BRAM_L.RAMB18_Y1.SRVAL_B[16] 27_198
BRAM_L.RAMB18_Y1.SRVAL_B[17] 27_182
BRAM_L.RAMB18_Y1.SRVAL_B[1] 27_246
BRAM_L.RAMB18_Y1.SRVAL_B[2] 27_318
BRAM_L.RAMB18_Y1.SRVAL_B[3] 27_302
BRAM_L.RAMB18_Y1.SRVAL_B[4] 27_286
@ -176,12 +182,14 @@ BRAM_L.RAMB18_Y1.WRITE_MODE_A_NO_CHANGE 27_256
BRAM_L.RAMB18_Y1.WRITE_MODE_A_READ_FIRST 27_264
BRAM_L.RAMB18_Y1.WRITE_MODE_B_NO_CHANGE 27_252
BRAM_L.RAMB18_Y1.WRITE_MODE_B_READ_FIRST 27_253
BRAM_L.RAMB18_Y1.WRITE_WIDTH_A_B0 27_269
BRAM_L.RAMB18_Y1.WRITE_WIDTH_A_B1 27_268
BRAM_L.RAMB18_Y1.WRITE_WIDTH_A_B2 27_267
BRAM_L.RAMB18_Y1.WRITE_WIDTH_B_B0 27_261
BRAM_L.RAMB18_Y1.WRITE_WIDTH_B_B1 27_260
BRAM_L.RAMB18_Y1.WRITE_WIDTH_B_B2 27_259
BRAM_L.RAMB18_Y1.WRITE_WIDTH_A_18 !27_268 !27_269 27_267
BRAM_L.RAMB18_Y1.WRITE_WIDTH_A_2 !27_267 !27_268 27_269
BRAM_L.RAMB18_Y1.WRITE_WIDTH_A_4 !27_267 !27_269 27_268
BRAM_L.RAMB18_Y1.WRITE_WIDTH_A_9 !27_267 27_268 27_269
BRAM_L.RAMB18_Y1.WRITE_WIDTH_B_18 !27_260 !27_261 27_259
BRAM_L.RAMB18_Y1.WRITE_WIDTH_B_2 !27_259 !27_260 27_261
BRAM_L.RAMB18_Y1.WRITE_WIDTH_B_4 !27_259 !27_261 27_260
BRAM_L.RAMB18_Y1.WRITE_WIDTH_B_9 !27_259 27_260 27_261
BRAM_L.RAMB18_Y1.ZINV_CLKARDCLK 27_213
BRAM_L.RAMB18_Y1.ZINV_CLKBWRCLK 27_211
BRAM_L.RAMB18_Y1.ZINV_ENARDEN 27_208

36864
kintex7/segbits_bram_r.block_ram.db
View File

File diff suppressed because it is too large Load Diff

72
kintex7/segbits_bram_r.db
View File

@ -2,12 +2,12 @@ BRAM_R.RAMB18_Y0.INIT_A[0] 27_73
BRAM_R.RAMB18_Y0.INIT_A[10] 27_129
BRAM_R.RAMB18_Y0.INIT_A[11] 27_113
BRAM_R.RAMB18_Y0.INIT_A[12] 27_97
BRAM_R.RAMB18_Y0.INIT_A[1] 27_65
BRAM_R.RAMB18_Y0.INIT_A[13] 27_81
BRAM_R.RAMB18_Y0.INIT_A[14] 27_49
BRAM_R.RAMB18_Y0.INIT_A[15] 27_33
BRAM_R.RAMB18_Y0.INIT_A[16] 27_17
BRAM_R.RAMB18_Y0.INIT_A[17] 27_01
BRAM_R.RAMB18_Y0.INIT_A[1] 27_65
BRAM_R.RAMB18_Y0.INIT_A[2] 27_137
BRAM_R.RAMB18_Y0.INIT_A[3] 27_121
BRAM_R.RAMB18_Y0.INIT_A[4] 27_105
@ -20,12 +20,12 @@ BRAM_R.RAMB18_Y0.INIT_B[0] 27_79
BRAM_R.RAMB18_Y0.INIT_B[10] 27_135
BRAM_R.RAMB18_Y0.INIT_B[11] 27_119
BRAM_R.RAMB18_Y0.INIT_B[12] 27_103
BRAM_R.RAMB18_Y0.INIT_B[1] 27_71
BRAM_R.RAMB18_Y0.INIT_B[13] 27_87
BRAM_R.RAMB18_Y0.INIT_B[14] 27_55
BRAM_R.RAMB18_Y0.INIT_B[15] 27_39
BRAM_R.RAMB18_Y0.INIT_B[16] 27_23
BRAM_R.RAMB18_Y0.INIT_B[17] 27_07
BRAM_R.RAMB18_Y0.INIT_B[1] 27_71
BRAM_R.RAMB18_Y0.INIT_B[2] 27_143
BRAM_R.RAMB18_Y0.INIT_B[3] 27_127
BRAM_R.RAMB18_Y0.INIT_B[4] 27_111
@ -34,22 +34,24 @@ BRAM_R.RAMB18_Y0.INIT_B[6] 27_63
BRAM_R.RAMB18_Y0.INIT_B[7] 27_47
BRAM_R.RAMB18_Y0.INIT_B[8] 27_31
BRAM_R.RAMB18_Y0.INIT_B[9] 27_15
BRAM_R.RAMB18_Y0.READ_WIDTH_A_B0 27_35
BRAM_R.RAMB18_Y0.READ_WIDTH_A_B1 27_36
BRAM_R.RAMB18_Y0.READ_WIDTH_A_B2 27_37
BRAM_R.RAMB18_Y0.READ_WIDTH_B_B0 27_43
BRAM_R.RAMB18_Y0.READ_WIDTH_B_B1 27_44
BRAM_R.RAMB18_Y0.READ_WIDTH_B_B2 27_45
BRAM_R.RAMB18_Y0.READ_WIDTH_A_18 !27_35 !27_36 27_37
BRAM_R.RAMB18_Y0.READ_WIDTH_A_2 !27_36 !27_37 27_35
BRAM_R.RAMB18_Y0.READ_WIDTH_A_4 !27_35 !27_37 27_36
BRAM_R.RAMB18_Y0.READ_WIDTH_A_9 !27_37 27_35 27_36
BRAM_R.RAMB18_Y0.READ_WIDTH_B_18 !27_43 !27_44 27_45
BRAM_R.RAMB18_Y0.READ_WIDTH_B_2 !27_44 !27_45 27_43
BRAM_R.RAMB18_Y0.READ_WIDTH_B_4 !27_43 !27_45 27_44
BRAM_R.RAMB18_Y0.READ_WIDTH_B_9 !27_45 27_43 27_44
BRAM_R.RAMB18_Y0.SRVAL_A[0] 27_74
BRAM_R.RAMB18_Y0.SRVAL_A[10] 27_130
BRAM_R.RAMB18_Y0.SRVAL_A[11] 27_114
BRAM_R.RAMB18_Y0.SRVAL_A[12] 27_98
BRAM_R.RAMB18_Y0.SRVAL_A[1] 27_66
BRAM_R.RAMB18_Y0.SRVAL_A[13] 27_82
BRAM_R.RAMB18_Y0.SRVAL_A[14] 27_50
BRAM_R.RAMB18_Y0.SRVAL_A[15] 27_34
BRAM_R.RAMB18_Y0.SRVAL_A[16] 27_18
BRAM_R.RAMB18_Y0.SRVAL_A[17] 27_02
BRAM_R.RAMB18_Y0.SRVAL_A[1] 27_66
BRAM_R.RAMB18_Y0.SRVAL_A[2] 27_138
BRAM_R.RAMB18_Y0.SRVAL_A[3] 27_122
BRAM_R.RAMB18_Y0.SRVAL_A[4] 27_106
@ -62,12 +64,12 @@ BRAM_R.RAMB18_Y0.SRVAL_B[0] 27_78
BRAM_R.RAMB18_Y0.SRVAL_B[10] 27_134
BRAM_R.RAMB18_Y0.SRVAL_B[11] 27_118
BRAM_R.RAMB18_Y0.SRVAL_B[12] 27_102
BRAM_R.RAMB18_Y0.SRVAL_B[1] 27_70
BRAM_R.RAMB18_Y0.SRVAL_B[13] 27_86
BRAM_R.RAMB18_Y0.SRVAL_B[14] 27_54
BRAM_R.RAMB18_Y0.SRVAL_B[15] 27_38
BRAM_R.RAMB18_Y0.SRVAL_B[16] 27_22
BRAM_R.RAMB18_Y0.SRVAL_B[17] 27_06
BRAM_R.RAMB18_Y0.SRVAL_B[1] 27_70
BRAM_R.RAMB18_Y0.SRVAL_B[2] 27_142
BRAM_R.RAMB18_Y0.SRVAL_B[3] 27_126
BRAM_R.RAMB18_Y0.SRVAL_B[4] 27_110
@ -80,12 +82,14 @@ BRAM_R.RAMB18_Y0.WRITE_MODE_A_NO_CHANGE 27_64
BRAM_R.RAMB18_Y0.WRITE_MODE_A_READ_FIRST 27_56
BRAM_R.RAMB18_Y0.WRITE_MODE_B_NO_CHANGE 27_68
BRAM_R.RAMB18_Y0.WRITE_MODE_B_READ_FIRST 27_67
BRAM_R.RAMB18_Y0.WRITE_WIDTH_A_B0 27_51
BRAM_R.RAMB18_Y0.WRITE_WIDTH_A_B1 27_52
BRAM_R.RAMB18_Y0.WRITE_WIDTH_A_B2 27_53
BRAM_R.RAMB18_Y0.WRITE_WIDTH_B_B0 27_59
BRAM_R.RAMB18_Y0.WRITE_WIDTH_B_B1 27_60
BRAM_R.RAMB18_Y0.WRITE_WIDTH_B_B2 27_61
BRAM_R.RAMB18_Y0.WRITE_WIDTH_A_18 !27_51 !27_52 27_53
BRAM_R.RAMB18_Y0.WRITE_WIDTH_A_2 !27_52 !27_53 27_51
BRAM_R.RAMB18_Y0.WRITE_WIDTH_A_4 !27_51 !27_53 27_52
BRAM_R.RAMB18_Y0.WRITE_WIDTH_A_9 !27_53 27_51 27_52
BRAM_R.RAMB18_Y0.WRITE_WIDTH_B_18 !27_59 !27_60 27_61
BRAM_R.RAMB18_Y0.WRITE_WIDTH_B_2 !27_60 !27_61 27_59
BRAM_R.RAMB18_Y0.WRITE_WIDTH_B_4 !27_59 !27_61 27_60
BRAM_R.RAMB18_Y0.WRITE_WIDTH_B_9 !27_61 27_59 27_60
BRAM_R.RAMB18_Y0.ZINV_CLKARDCLK 27_107
BRAM_R.RAMB18_Y0.ZINV_CLKBWRCLK 27_109
BRAM_R.RAMB18_Y0.ZINV_ENARDEN 27_112
@ -98,12 +102,12 @@ BRAM_R.RAMB18_Y1.INIT_A[0] 27_249
BRAM_R.RAMB18_Y1.INIT_A[10] 27_305
BRAM_R.RAMB18_Y1.INIT_A[11] 27_289
BRAM_R.RAMB18_Y1.INIT_A[12] 27_273
BRAM_R.RAMB18_Y1.INIT_A[1] 27_241
BRAM_R.RAMB18_Y1.INIT_A[13] 27_257
BRAM_R.RAMB18_Y1.INIT_A[14] 27_225
BRAM_R.RAMB18_Y1.INIT_A[15] 27_209
BRAM_R.RAMB18_Y1.INIT_A[16] 27_193
BRAM_R.RAMB18_Y1.INIT_A[17] 27_177
BRAM_R.RAMB18_Y1.INIT_A[1] 27_241
BRAM_R.RAMB18_Y1.INIT_A[2] 27_313
BRAM_R.RAMB18_Y1.INIT_A[3] 27_297
BRAM_R.RAMB18_Y1.INIT_A[4] 27_281
@ -116,12 +120,12 @@ BRAM_R.RAMB18_Y1.INIT_B[0] 27_255
BRAM_R.RAMB18_Y1.INIT_B[10] 27_311
BRAM_R.RAMB18_Y1.INIT_B[11] 27_295
BRAM_R.RAMB18_Y1.INIT_B[12] 27_279
BRAM_R.RAMB18_Y1.INIT_B[1] 27_247
BRAM_R.RAMB18_Y1.INIT_B[13] 27_263
BRAM_R.RAMB18_Y1.INIT_B[14] 27_231
BRAM_R.RAMB18_Y1.INIT_B[15] 27_215
BRAM_R.RAMB18_Y1.INIT_B[16] 27_199
BRAM_R.RAMB18_Y1.INIT_B[17] 27_183
BRAM_R.RAMB18_Y1.INIT_B[1] 27_247
BRAM_R.RAMB18_Y1.INIT_B[2] 27_319
BRAM_R.RAMB18_Y1.INIT_B[3] 27_303
BRAM_R.RAMB18_Y1.INIT_B[4] 27_287
@ -130,22 +134,24 @@ BRAM_R.RAMB18_Y1.INIT_B[6] 27_239
BRAM_R.RAMB18_Y1.INIT_B[7] 27_223
BRAM_R.RAMB18_Y1.INIT_B[8] 27_207
BRAM_R.RAMB18_Y1.INIT_B[9] 27_191
BRAM_R.RAMB18_Y1.READ_WIDTH_A_B0 27_285
BRAM_R.RAMB18_Y1.READ_WIDTH_A_B1 27_284
BRAM_R.RAMB18_Y1.READ_WIDTH_A_B2 27_283
BRAM_R.RAMB18_Y1.READ_WIDTH_B_B0 27_277
BRAM_R.RAMB18_Y1.READ_WIDTH_B_B1 27_276
BRAM_R.RAMB18_Y1.READ_WIDTH_B_B2 27_275
BRAM_R.RAMB18_Y1.READ_WIDTH_A_18 !27_284 !27_285 27_283
BRAM_R.RAMB18_Y1.READ_WIDTH_A_2 !27_283 !27_284 27_285
BRAM_R.RAMB18_Y1.READ_WIDTH_A_4 !27_283 !27_285 27_284
BRAM_R.RAMB18_Y1.READ_WIDTH_A_9 !27_283 27_284 27_285
BRAM_R.RAMB18_Y1.READ_WIDTH_B_18 !27_276 !27_277 27_275
BRAM_R.RAMB18_Y1.READ_WIDTH_B_2 !27_275 !27_276 27_277
BRAM_R.RAMB18_Y1.READ_WIDTH_B_4 !27_275 !27_277 27_276
BRAM_R.RAMB18_Y1.READ_WIDTH_B_9 !27_275 27_276 27_277
BRAM_R.RAMB18_Y1.SRVAL_A[0] 27_250
BRAM_R.RAMB18_Y1.SRVAL_A[10] 27_306
BRAM_R.RAMB18_Y1.SRVAL_A[11] 27_290
BRAM_R.RAMB18_Y1.SRVAL_A[12] 27_274
BRAM_R.RAMB18_Y1.SRVAL_A[1] 27_242
BRAM_R.RAMB18_Y1.SRVAL_A[13] 27_258
BRAM_R.RAMB18_Y1.SRVAL_A[14] 27_226
BRAM_R.RAMB18_Y1.SRVAL_A[15] 27_210
BRAM_R.RAMB18_Y1.SRVAL_A[16] 27_194
BRAM_R.RAMB18_Y1.SRVAL_A[17] 27_178
BRAM_R.RAMB18_Y1.SRVAL_A[1] 27_242
BRAM_R.RAMB18_Y1.SRVAL_A[2] 27_314
BRAM_R.RAMB18_Y1.SRVAL_A[3] 27_298
BRAM_R.RAMB18_Y1.SRVAL_A[4] 27_282
@ -158,12 +164,12 @@ BRAM_R.RAMB18_Y1.SRVAL_B[0] 27_254
BRAM_R.RAMB18_Y1.SRVAL_B[10] 27_310
BRAM_R.RAMB18_Y1.SRVAL_B[11] 27_294
BRAM_R.RAMB18_Y1.SRVAL_B[12] 27_278
BRAM_R.RAMB18_Y1.SRVAL_B[1] 27_246
BRAM_R.RAMB18_Y1.SRVAL_B[13] 27_262
BRAM_R.RAMB18_Y1.SRVAL_B[14] 27_230
BRAM_R.RAMB18_Y1.SRVAL_B[15] 27_214
BRAM_R.RAMB18_Y1.SRVAL_B[16] 27_198
BRAM_R.RAMB18_Y1.SRVAL_B[17] 27_182
BRAM_R.RAMB18_Y1.SRVAL_B[1] 27_246
BRAM_R.RAMB18_Y1.SRVAL_B[2] 27_318
BRAM_R.RAMB18_Y1.SRVAL_B[3] 27_302
BRAM_R.RAMB18_Y1.SRVAL_B[4] 27_286
@ -176,12 +182,14 @@ BRAM_R.RAMB18_Y1.WRITE_MODE_A_NO_CHANGE 27_256
BRAM_R.RAMB18_Y1.WRITE_MODE_A_READ_FIRST 27_264
BRAM_R.RAMB18_Y1.WRITE_MODE_B_NO_CHANGE 27_252
BRAM_R.RAMB18_Y1.WRITE_MODE_B_READ_FIRST 27_253
BRAM_R.RAMB18_Y1.WRITE_WIDTH_A_B0 27_269
BRAM_R.RAMB18_Y1.WRITE_WIDTH_A_B1 27_268
BRAM_R.RAMB18_Y1.WRITE_WIDTH_A_B2 27_267
BRAM_R.RAMB18_Y1.WRITE_WIDTH_B_B0 27_261
BRAM_R.RAMB18_Y1.WRITE_WIDTH_B_B1 27_260
BRAM_R.RAMB18_Y1.WRITE_WIDTH_B_B2 27_259
BRAM_R.RAMB18_Y1.WRITE_WIDTH_A_18 !27_268 !27_269 27_267
BRAM_R.RAMB18_Y1.WRITE_WIDTH_A_2 !27_267 !27_268 27_269
BRAM_R.RAMB18_Y1.WRITE_WIDTH_A_4 !27_267 !27_269 27_268
BRAM_R.RAMB18_Y1.WRITE_WIDTH_A_9 !27_267 27_268 27_269
BRAM_R.RAMB18_Y1.WRITE_WIDTH_B_18 !27_260 !27_261 27_259
BRAM_R.RAMB18_Y1.WRITE_WIDTH_B_2 !27_259 !27_260 27_261
BRAM_R.RAMB18_Y1.WRITE_WIDTH_B_4 !27_259 !27_261 27_260
BRAM_R.RAMB18_Y1.WRITE_WIDTH_B_9 !27_259 27_260 27_261
BRAM_R.RAMB18_Y1.ZINV_CLKARDCLK 27_213
BRAM_R.RAMB18_Y1.ZINV_CLKBWRCLK 27_211
BRAM_R.RAMB18_Y1.ZINV_ENARDEN 27_208

36
kintex7/segbits_clbll_l.db
View File

@ -81,6 +81,7 @@ CLBLL_L.SLICEL_X0.AOUTMUX.A5Q !30_06 !30_08 !30_11 30_07
CLBLL_L.SLICEL_X0.AOUTMUX.CY !30_07 !30_11 30_06 30_08
CLBLL_L.SLICEL_X0.AOUTMUX.F7 !30_08 !30_11 30_06 30_07
CLBLL_L.SLICEL_X0.AOUTMUX.O5 !30_07 !30_08 30_06 30_11
CLBLL_L.SLICEL_X0.AOUTMUX.O6 !30_06 !30_07 !30_08 30_11
CLBLL_L.SLICEL_X0.AOUTMUX.XOR !30_06 !30_07 !30_11 30_08
CLBLL_L.SLICEL_X0.B5FF.ZINI 31_22
CLBLL_L.SLICEL_X0.B5FF.ZRST 01_19
@ -165,16 +166,14 @@ CLBLL_L.SLICEL_X0.BOUTMUX.B5Q !30_20 !30_21 !30_22 30_23
CLBLL_L.SLICEL_X0.BOUTMUX.CY !30_20 !30_23 30_21 30_22
CLBLL_L.SLICEL_X0.BOUTMUX.F8 !30_20 !30_21 30_22 30_23
CLBLL_L.SLICEL_X0.BOUTMUX.O5 !30_21 !30_23 30_20 30_22
CLBLL_L.SLICEL_X0.BOUTMUX.O6 !30_21 !30_22 !30_23 30_20
CLBLL_L.SLICEL_X0.BOUTMUX.XOR !30_20 !30_22 !30_23 30_21
CLBLL_L.SLICEL_X0.C5FF.ZINI 31_41
CLBLL_L.SLICEL_X0.C5FF.ZRST 01_47
CLBLL_L.SLICEL_X0.C5FFMUX.IN_A 31_45
CLBLL_L.SLICEL_X0.C5FFMUX.IN_B 30_39
CLBLL_L.SLICEL_X0.CARRY4.ACY0 !30_00 !30_02 !30_03 30_01 30_12 30_15 31_03
CLBLL_L.SLICEL_X0.CARRY4.ACY0 30_15
CLBLL_L.SLICEL_X0.CARRY4.BCY0 !30_24 !30_25 !30_27 01_15 30_26 30_30 31_28
CLBLL_L.SLICEL_X0.CARRY4.ACY0 30_01 30_12 30_15 31_03
CLBLL_L.SLICEL_X0.CARRY4.BCY0 01_15
CLBLL_L.SLICEL_X0.CARRY4.CCY0 !30_35 !30_37 !30_38 30_33 30_36 30_48 31_33
CLBLL_L.SLICEL_X0.CARRY4.CCY0 30_48
CLBLL_L.SLICEL_X0.CARRY4.DCY0 30_49
CLBLL_L.SLICEL_X0.CEUSEDMUX 01_39
@ -258,11 +257,12 @@ CLBLL_L.SLICEL_X0.COUTMUX.C5Q !30_40 !30_44 !30_45 30_43
CLBLL_L.SLICEL_X0.COUTMUX.CY !30_43 !30_45 30_40 30_44
CLBLL_L.SLICEL_X0.COUTMUX.F7 !30_44 !30_45 30_40 30_43
CLBLL_L.SLICEL_X0.COUTMUX.O5 !30_43 !30_44 30_40 30_45
CLBLL_L.SLICEL_X0.COUTMUX.O6 !30_40 !30_43 !30_44 30_45
CLBLL_L.SLICEL_X0.COUTMUX.XOR !30_40 !30_43 !30_45 30_44
CLBLL_L.SLICEL_X0.D5FF.ZINI 31_51
CLBLL_L.SLICEL_X0.D5FF.ZRST 01_55
CLBLL_L.SLICEL_X0.D5FFMUX.IN_A 30_55
CLBLL_L.SLICEL_X0.D5FFMUX.IN_B 30_54
CLBLL_L.SLICEL_X0.D5FFMUX.IN_B 21_55 25_55 30_54
CLBLL_L.SLICEL_X0.DFF.ZINI 31_58
CLBLL_L.SLICEL_X0.DFF.ZRST 30_50
CLBLL_L.SLICEL_X0.DFFMUX.CY !30_59 !30_61 30_60 30_62
@ -340,12 +340,13 @@ CLBLL_L.SLICEL_X0.DLUT.SRL 30_47
CLBLL_L.SLICEL_X0.DOUTMUX.CY !30_56 !30_57 30_51 30_52
CLBLL_L.SLICEL_X0.DOUTMUX.D5Q !30_51 !30_52 !30_56 30_57
CLBLL_L.SLICEL_X0.DOUTMUX.O5 !30_51 !30_57 30_52 30_56
CLBLL_L.SLICEL_X0.DOUTMUX.O6 !30_51 !30_52 !30_57 30_56
CLBLL_L.SLICEL_X0.DOUTMUX.XOR !30_52 !30_56 !30_57 30_51
CLBLL_L.SLICEL_X0.FFSYNC 00_48
CLBLL_L.SLICEL_X0.LATCH 30_32
CLBLL_L.SLICEL_X0.PRECYINIT.1 00_12
CLBLL_L.SLICEL_X0.PRECYINIT.AX 30_14
CLBLL_L.SLICEL_X0.PRECYINIT.CIN 30_13
CLBLL_L.SLICEL_X0.PRECYINIT.1 !30_13 !30_14 00_12
CLBLL_L.SLICEL_X0.PRECYINIT.AX !00_12 !30_13 30_14
CLBLL_L.SLICEL_X0.PRECYINIT.CIN !00_12 !30_14 30_13
CLBLL_L.SLICEL_X0.SRUSEDMUX 01_35
CLBLL_L.SLICEL_X0.WA7USED 00_40
CLBLL_L.SLICEL_X0.WA8USED 01_27
@ -430,6 +431,7 @@ CLBLL_L.SLICEL_X1.AOUTMUX.A5Q !31_07 !31_09 !31_10 30_05
CLBLL_L.SLICEL_X1.AOUTMUX.CY !30_05 !31_09 31_07 31_10
CLBLL_L.SLICEL_X1.AOUTMUX.F7 !31_07 !31_09 30_05 31_10
CLBLL_L.SLICEL_X1.AOUTMUX.O5 !30_05 !31_07 31_09 31_10
CLBLL_L.SLICEL_X1.AOUTMUX.O6 !30_05 !31_07 !31_10 31_09
CLBLL_L.SLICEL_X1.AOUTMUX.XOR !30_05 !31_09 !31_10 31_07
CLBLL_L.SLICEL_X1.B5FF.ZINI 31_23
CLBLL_L.SLICEL_X1.B5FF.ZRST 00_16
@ -511,16 +513,14 @@ CLBLL_L.SLICEL_X1.BOUTMUX.B5Q !30_28 !31_20 !31_21 30_29
CLBLL_L.SLICEL_X1.BOUTMUX.CY !30_29 !31_20 30_28 31_21
CLBLL_L.SLICEL_X1.BOUTMUX.F8 !30_28 !31_20 30_29 31_21
CLBLL_L.SLICEL_X1.BOUTMUX.O5 !30_28 !30_29 31_20 31_21
CLBLL_L.SLICEL_X1.BOUTMUX.O6 !30_28 !30_29 !31_21 31_20
CLBLL_L.SLICEL_X1.BOUTMUX.XOR !30_29 !31_20 !31_21 30_28
CLBLL_L.SLICEL_X1.C5FF.ZINI 31_42
CLBLL_L.SLICEL_X1.C5FF.ZRST 00_44
CLBLL_L.SLICEL_X1.C5FFMUX.IN_A 31_44
CLBLL_L.SLICEL_X1.C5FFMUX.IN_B 31_39
CLBLL_L.SLICEL_X1.CARRY4.ACY0 !30_04 !31_00 !31_02 31_01 31_04 31_14 31_15
CLBLL_L.SLICEL_X1.CARRY4.ACY0 31_14
CLBLL_L.SLICEL_X1.CARRY4.BCY0 !31_24 !31_25 !31_26 00_08 31_27 31_29 31_30
CLBLL_L.SLICEL_X1.CARRY4.BCY0 00_08
CLBLL_L.SLICEL_X1.CARRY4.CCY0 !31_35 !31_36 !31_37 30_34 31_34 31_38 31_48
CLBLL_L.SLICEL_X1.CARRY4.ACY0 31_01 31_04 31_14 31_15
CLBLL_L.SLICEL_X1.CARRY4.BCY0 00_08 31_27 31_29 31_30
CLBLL_L.SLICEL_X1.CARRY4.CCY0 31_48
CLBLL_L.SLICEL_X1.CARRY4.DCY0 31_49
CLBLL_L.SLICEL_X1.CEUSEDMUX 00_36
@ -601,11 +601,12 @@ CLBLL_L.SLICEL_X1.COUTMUX.C5Q !30_42 !31_40 !31_43 30_41
CLBLL_L.SLICEL_X1.COUTMUX.CY !30_41 !31_43 30_42 31_40
CLBLL_L.SLICEL_X1.COUTMUX.F7 !30_42 !31_43 30_41 31_40
CLBLL_L.SLICEL_X1.COUTMUX.O5 !30_41 !30_42 31_40 31_43
CLBLL_L.SLICEL_X1.COUTMUX.O6 !30_41 !30_42 !31_40 31_43
CLBLL_L.SLICEL_X1.COUTMUX.XOR !30_41 !31_40 !31_43 30_42
CLBLL_L.SLICEL_X1.D5FF.ZINI 31_52
CLBLL_L.SLICEL_X1.D5FF.ZRST 00_56
CLBLL_L.SLICEL_X1.D5FFMUX.IN_A 31_55
CLBLL_L.SLICEL_X1.D5FFMUX.IN_B 31_54
CLBLL_L.SLICEL_X1.D5FFMUX.IN_B 25_63 31_54
CLBLL_L.SLICEL_X1.DFF.ZINI 31_59
CLBLL_L.SLICEL_X1.DFF.ZRST 31_50
CLBLL_L.SLICEL_X1.DFFMUX.CY !31_60 !31_61 30_58 31_62
@ -680,10 +681,11 @@ CLBLL_L.SLICEL_X1.DLUT.INIT[63] 28_48
CLBLL_L.SLICEL_X1.DOUTMUX.CY !31_53 !31_56 30_53 31_57
CLBLL_L.SLICEL_X1.DOUTMUX.D5Q !30_53 !31_56 !31_57 31_53
CLBLL_L.SLICEL_X1.DOUTMUX.O5 !30_53 !31_53 31_56 31_57
CLBLL_L.SLICEL_X1.DOUTMUX.O6 !30_53 !31_53 !31_57 31_56
CLBLL_L.SLICEL_X1.DOUTMUX.XOR !31_53 !31_56 !31_57 30_53
CLBLL_L.SLICEL_X1.FFSYNC 01_31
CLBLL_L.SLICEL_X1.LATCH 31_32
CLBLL_L.SLICEL_X1.PRECYINIT.1 01_11
CLBLL_L.SLICEL_X1.PRECYINIT.AX 31_13
CLBLL_L.SLICEL_X1.PRECYINIT.CIN 31_12
CLBLL_L.SLICEL_X1.PRECYINIT.1 !31_12 !31_13 01_11
CLBLL_L.SLICEL_X1.PRECYINIT.AX !01_11 !31_12 31_13
CLBLL_L.SLICEL_X1.PRECYINIT.CIN !01_11 !31_13 31_12
CLBLL_L.SLICEL_X1.SRUSEDMUX 00_32

36
kintex7/segbits_clbll_r.db
View File

@ -81,6 +81,7 @@ CLBLL_R.SLICEL_X0.AOUTMUX.A5Q !30_06 !30_08 !30_11 30_07
CLBLL_R.SLICEL_X0.AOUTMUX.CY !30_07 !30_11 30_06 30_08
CLBLL_R.SLICEL_X0.AOUTMUX.F7 !30_08 !30_11 30_06 30_07
CLBLL_R.SLICEL_X0.AOUTMUX.O5 !30_07 !30_08 30_06 30_11
CLBLL_R.SLICEL_X0.AOUTMUX.O6 !30_06 !30_07 !30_08 30_11
CLBLL_R.SLICEL_X0.AOUTMUX.XOR !30_06 !30_07 !30_11 30_08
CLBLL_R.SLICEL_X0.B5FF.ZINI 31_22
CLBLL_R.SLICEL_X0.B5FF.ZRST 01_19
@ -165,16 +166,14 @@ CLBLL_R.SLICEL_X0.BOUTMUX.B5Q !30_20 !30_21 !30_22 30_23
CLBLL_R.SLICEL_X0.BOUTMUX.CY !30_20 !30_23 30_21 30_22
CLBLL_R.SLICEL_X0.BOUTMUX.F8 !30_20 !30_21 30_22 30_23
CLBLL_R.SLICEL_X0.BOUTMUX.O5 !30_21 !30_23 30_20 30_22
CLBLL_R.SLICEL_X0.BOUTMUX.O6 !30_21 !30_22 !30_23 30_20
CLBLL_R.SLICEL_X0.BOUTMUX.XOR !30_20 !30_22 !30_23 30_21
CLBLL_R.SLICEL_X0.C5FF.ZINI 31_41
CLBLL_R.SLICEL_X0.C5FF.ZRST 01_47
CLBLL_R.SLICEL_X0.C5FFMUX.IN_A 31_45
CLBLL_R.SLICEL_X0.C5FFMUX.IN_B 30_39
CLBLL_R.SLICEL_X0.CARRY4.ACY0 !30_00 !30_02 !30_03 30_01 30_12 30_15 31_03
CLBLL_R.SLICEL_X0.CARRY4.ACY0 30_15
CLBLL_R.SLICEL_X0.CARRY4.BCY0 !30_24 !30_25 !30_27 01_15 30_26 30_30 31_28
CLBLL_R.SLICEL_X0.CARRY4.ACY0 30_01 30_12 30_15 31_03
CLBLL_R.SLICEL_X0.CARRY4.BCY0 01_15
CLBLL_R.SLICEL_X0.CARRY4.CCY0 !30_35 !30_37 !30_38 30_33 30_36 30_48 31_33
CLBLL_R.SLICEL_X0.CARRY4.CCY0 30_48
CLBLL_R.SLICEL_X0.CARRY4.DCY0 30_49
CLBLL_R.SLICEL_X0.CEUSEDMUX 01_39
@ -258,11 +257,12 @@ CLBLL_R.SLICEL_X0.COUTMUX.C5Q !30_40 !30_44 !30_45 30_43
CLBLL_R.SLICEL_X0.COUTMUX.CY !30_43 !30_45 30_40 30_44
CLBLL_R.SLICEL_X0.COUTMUX.F7 !30_44 !30_45 30_40 30_43
CLBLL_R.SLICEL_X0.COUTMUX.O5 !30_43 !30_44 30_40 30_45
CLBLL_R.SLICEL_X0.COUTMUX.O6 !30_40 !30_43 !30_44 30_45
CLBLL_R.SLICEL_X0.COUTMUX.XOR !30_40 !30_43 !30_45 30_44
CLBLL_R.SLICEL_X0.D5FF.ZINI 31_51
CLBLL_R.SLICEL_X0.D5FF.ZRST 01_55
CLBLL_R.SLICEL_X0.D5FFMUX.IN_A 30_55
CLBLL_R.SLICEL_X0.D5FFMUX.IN_B 30_54
CLBLL_R.SLICEL_X0.D5FFMUX.IN_B 21_55 25_55 30_54
CLBLL_R.SLICEL_X0.DFF.ZINI 31_58
CLBLL_R.SLICEL_X0.DFF.ZRST 30_50
CLBLL_R.SLICEL_X0.DFFMUX.CY !30_59 !30_61 30_60 30_62
@ -340,12 +340,13 @@ CLBLL_R.SLICEL_X0.DLUT.SRL 30_47
CLBLL_R.SLICEL_X0.DOUTMUX.CY !30_56 !30_57 30_51 30_52
CLBLL_R.SLICEL_X0.DOUTMUX.D5Q !30_51 !30_52 !30_56 30_57
CLBLL_R.SLICEL_X0.DOUTMUX.O5 !30_51 !30_57 30_52 30_56
CLBLL_R.SLICEL_X0.DOUTMUX.O6 !30_51 !30_52 !30_57 30_56
CLBLL_R.SLICEL_X0.DOUTMUX.XOR !30_52 !30_56 !30_57 30_51
CLBLL_R.SLICEL_X0.FFSYNC 00_48
CLBLL_R.SLICEL_X0.LATCH 30_32
CLBLL_R.SLICEL_X0.PRECYINIT.1 00_12
CLBLL_R.SLICEL_X0.PRECYINIT.AX 30_14
CLBLL_R.SLICEL_X0.PRECYINIT.CIN 30_13
CLBLL_R.SLICEL_X0.PRECYINIT.1 !30_13 !30_14 00_12
CLBLL_R.SLICEL_X0.PRECYINIT.AX !00_12 !30_13 30_14
CLBLL_R.SLICEL_X0.PRECYINIT.CIN !00_12 !30_14 30_13
CLBLL_R.SLICEL_X0.SRUSEDMUX 01_35
CLBLL_R.SLICEL_X0.WA7USED 00_40
CLBLL_R.SLICEL_X0.WA8USED 01_27
@ -430,6 +431,7 @@ CLBLL_R.SLICEL_X1.AOUTMUX.A5Q !31_07 !31_09 !31_10 30_05
CLBLL_R.SLICEL_X1.AOUTMUX.CY !30_05 !31_09 31_07 31_10
CLBLL_R.SLICEL_X1.AOUTMUX.F7 !31_07 !31_09 30_05 31_10
CLBLL_R.SLICEL_X1.AOUTMUX.O5 !30_05 !31_07 31_09 31_10
CLBLL_R.SLICEL_X1.AOUTMUX.O6 !30_05 !31_07 !31_10 31_09
CLBLL_R.SLICEL_X1.AOUTMUX.XOR !30_05 !31_09 !31_10 31_07
CLBLL_R.SLICEL_X1.B5FF.ZINI 31_23
CLBLL_R.SLICEL_X1.B5FF.ZRST 00_16
@ -511,16 +513,14 @@ CLBLL_R.SLICEL_X1.BOUTMUX.B5Q !30_28 !31_20 !31_21 30_29
CLBLL_R.SLICEL_X1.BOUTMUX.CY !30_29 !31_20 30_28 31_21
CLBLL_R.SLICEL_X1.BOUTMUX.F8 !30_28 !31_20 30_29 31_21
CLBLL_R.SLICEL_X1.BOUTMUX.O5 !30_28 !30_29 31_20 31_21
CLBLL_R.SLICEL_X1.BOUTMUX.O6 !30_28 !30_29 !31_21 31_20
CLBLL_R.SLICEL_X1.BOUTMUX.XOR !30_29 !31_20 !31_21 30_28
CLBLL_R.SLICEL_X1.C5FF.ZINI 31_42
CLBLL_R.SLICEL_X1.C5FF.ZRST 00_44
CLBLL_R.SLICEL_X1.C5FFMUX.IN_A 31_44
CLBLL_R.SLICEL_X1.C5FFMUX.IN_B 31_39
CLBLL_R.SLICEL_X1.CARRY4.ACY0 !30_04 !31_00 !31_02 31_01 31_04 31_14 31_15
CLBLL_R.SLICEL_X1.CARRY4.ACY0 31_14
CLBLL_R.SLICEL_X1.CARRY4.BCY0 !31_24 !31_25 !31_26 00_08 31_27 31_29 31_30
CLBLL_R.SLICEL_X1.CARRY4.BCY0 00_08
CLBLL_R.SLICEL_X1.CARRY4.CCY0 !31_35 !31_36 !31_37 30_34 31_34 31_38 31_48
CLBLL_R.SLICEL_X1.CARRY4.ACY0 31_01 31_04 31_14 31_15
CLBLL_R.SLICEL_X1.CARRY4.BCY0 00_08 31_27 31_29 31_30
CLBLL_R.SLICEL_X1.CARRY4.CCY0 31_48
CLBLL_R.SLICEL_X1.CARRY4.DCY0 31_49
CLBLL_R.SLICEL_X1.CEUSEDMUX 00_36
@ -601,11 +601,12 @@ CLBLL_R.SLICEL_X1.COUTMUX.C5Q !30_42 !31_40 !31_43 30_41
CLBLL_R.SLICEL_X1.COUTMUX.CY !30_41 !31_43 30_42 31_40
CLBLL_R.SLICEL_X1.COUTMUX.F7 !30_42 !31_43 30_41 31_40
CLBLL_R.SLICEL_X1.COUTMUX.O5 !30_41 !30_42 31_40 31_43
CLBLL_R.SLICEL_X1.COUTMUX.O6 !30_41 !30_42 !31_40 31_43
CLBLL_R.SLICEL_X1.COUTMUX.XOR !30_41 !31_40 !31_43 30_42
CLBLL_R.SLICEL_X1.D5FF.ZINI 31_52
CLBLL_R.SLICEL_X1.D5FF.ZRST 00_56
CLBLL_R.SLICEL_X1.D5FFMUX.IN_A 31_55
CLBLL_R.SLICEL_X1.D5FFMUX.IN_B 31_54
CLBLL_R.SLICEL_X1.D5FFMUX.IN_B 25_63 31_54
CLBLL_R.SLICEL_X1.DFF.ZINI 31_59
CLBLL_R.SLICEL_X1.DFF.ZRST 31_50
CLBLL_R.SLICEL_X1.DFFMUX.CY !31_60 !31_61 30_58 31_62
@ -680,10 +681,11 @@ CLBLL_R.SLICEL_X1.DLUT.INIT[63] 28_48
CLBLL_R.SLICEL_X1.DOUTMUX.CY !31_53 !31_56 30_53 31_57
CLBLL_R.SLICEL_X1.DOUTMUX.D5Q !30_53 !31_56 !31_57 31_53
CLBLL_R.SLICEL_X1.DOUTMUX.O5 !30_53 !31_53 31_56 31_57
CLBLL_R.SLICEL_X1.DOUTMUX.O6 !30_53 !31_53 !31_57 31_56
CLBLL_R.SLICEL_X1.DOUTMUX.XOR !31_53 !31_56 !31_57 30_53
CLBLL_R.SLICEL_X1.FFSYNC 01_31
CLBLL_R.SLICEL_X1.LATCH 31_32
CLBLL_R.SLICEL_X1.PRECYINIT.1 01_11
CLBLL_R.SLICEL_X1.PRECYINIT.AX 31_13
CLBLL_R.SLICEL_X1.PRECYINIT.CIN 31_12
CLBLL_R.SLICEL_X1.PRECYINIT.1 !31_12 !31_13 01_11
CLBLL_R.SLICEL_X1.PRECYINIT.AX !01_11 !31_12 31_13
CLBLL_R.SLICEL_X1.PRECYINIT.CIN !01_11 !31_13 31_12
CLBLL_R.SLICEL_X1.SRUSEDMUX 00_32

39
kintex7/segbits_clblm_l.db
View File

@ -78,6 +78,7 @@ CLBLM_L.SLICEL_X1.AOUTMUX.A5Q !31_07 !31_09 !31_10 30_05
CLBLM_L.SLICEL_X1.AOUTMUX.CY !30_05 !31_09 31_07 31_10
CLBLM_L.SLICEL_X1.AOUTMUX.F7 !31_07 !31_09 30_05 31_10
CLBLM_L.SLICEL_X1.AOUTMUX.O5 !30_05 !31_07 31_09 31_10
CLBLM_L.SLICEL_X1.AOUTMUX.O6 !30_05 !31_07 !31_10 31_09
CLBLM_L.SLICEL_X1.AOUTMUX.XOR !30_05 !31_09 !31_10 31_07
CLBLM_L.SLICEL_X1.B5FF.ZINI 31_23
CLBLM_L.SLICEL_X1.B5FF.ZRST 00_16
@ -159,16 +160,14 @@ CLBLM_L.SLICEL_X1.BOUTMUX.B5Q !30_28 !31_20 !31_21 30_29
CLBLM_L.SLICEL_X1.BOUTMUX.CY !30_29 !31_20 30_28 31_21
CLBLM_L.SLICEL_X1.BOUTMUX.F8 !30_28 !31_20 30_29 31_21
CLBLM_L.SLICEL_X1.BOUTMUX.O5 !30_28 !30_29 31_20 31_21
CLBLM_L.SLICEL_X1.BOUTMUX.O6 !30_28 !30_29 !31_21 31_20
CLBLM_L.SLICEL_X1.BOUTMUX.XOR !30_29 !31_20 !31_21 30_28
CLBLM_L.SLICEL_X1.C5FF.ZINI 31_42
CLBLM_L.SLICEL_X1.C5FF.ZRST 00_44
CLBLM_L.SLICEL_X1.C5FFMUX.IN_A 31_44
CLBLM_L.SLICEL_X1.C5FFMUX.IN_B 31_39
CLBLM_L.SLICEL_X1.CARRY4.ACY0 !30_04 !31_00 !31_02 31_01 31_04 31_14 31_15
CLBLM_L.SLICEL_X1.CARRY4.ACY0 31_14
CLBLM_L.SLICEL_X1.CARRY4.BCY0 !31_24 !31_25 !31_26 00_08 31_27 31_29 31_30
CLBLM_L.SLICEL_X1.CARRY4.BCY0 00_08
CLBLM_L.SLICEL_X1.CARRY4.CCY0 !31_35 !31_36 !31_37 30_34 31_34 31_38 31_48
CLBLM_L.SLICEL_X1.CARRY4.ACY0 31_01 31_04 31_14 31_15
CLBLM_L.SLICEL_X1.CARRY4.BCY0 00_08 31_27 31_29 31_30
CLBLM_L.SLICEL_X1.CARRY4.CCY0 31_48
CLBLM_L.SLICEL_X1.CARRY4.DCY0 31_49
CLBLM_L.SLICEL_X1.CEUSEDMUX 00_36
@ -249,11 +248,12 @@ CLBLM_L.SLICEL_X1.COUTMUX.C5Q !30_42 !31_40 !31_43 30_41
CLBLM_L.SLICEL_X1.COUTMUX.CY !30_41 !31_43 30_42 31_40
CLBLM_L.SLICEL_X1.COUTMUX.F7 !30_42 !31_43 30_41 31_40
CLBLM_L.SLICEL_X1.COUTMUX.O5 !30_41 !30_42 31_40 31_43
CLBLM_L.SLICEL_X1.COUTMUX.O6 !30_41 !30_42 !31_40 31_43
CLBLM_L.SLICEL_X1.COUTMUX.XOR !30_41 !31_40 !31_43 30_42
CLBLM_L.SLICEL_X1.D5FF.ZINI 31_52
CLBLM_L.SLICEL_X1.D5FF.ZRST 00_56
CLBLM_L.SLICEL_X1.D5FFMUX.IN_A 31_55
CLBLM_L.SLICEL_X1.D5FFMUX.IN_B 31_54
CLBLM_L.SLICEL_X1.D5FFMUX.IN_B 25_63 31_54
CLBLM_L.SLICEL_X1.DFF.ZINI 31_59
CLBLM_L.SLICEL_X1.DFF.ZRST 31_50
CLBLM_L.SLICEL_X1.DFFMUX.CY !31_60 !31_61 30_58 31_62
@ -328,18 +328,18 @@ CLBLM_L.SLICEL_X1.DLUT.INIT[63] 28_48
CLBLM_L.SLICEL_X1.DOUTMUX.CY !31_53 !31_56 30_53 31_57
CLBLM_L.SLICEL_X1.DOUTMUX.D5Q !30_53 !31_56 !31_57 31_53
CLBLM_L.SLICEL_X1.DOUTMUX.O5 !30_53 !31_53 31_56 31_57
CLBLM_L.SLICEL_X1.DOUTMUX.O6 !30_53 !31_53 !31_57 31_56
CLBLM_L.SLICEL_X1.DOUTMUX.XOR !31_53 !31_56 !31_57 30_53
CLBLM_L.SLICEL_X1.FFSYNC 01_31
CLBLM_L.SLICEL_X1.LATCH 31_32
CLBLM_L.SLICEL_X1.PRECYINIT.1 01_11
CLBLM_L.SLICEL_X1.PRECYINIT.AX 31_13
CLBLM_L.SLICEL_X1.PRECYINIT.CIN 31_12
CLBLM_L.SLICEL_X1.PRECYINIT.1 !31_12 !31_13 01_11
CLBLM_L.SLICEL_X1.PRECYINIT.AX !01_11 !31_12 31_13
CLBLM_L.SLICEL_X1.PRECYINIT.CIN !01_11 !31_13 31_12
CLBLM_L.SLICEL_X1.SRUSEDMUX 00_32
CLBLM_L.SLICEM_X0.A5FF.ZINI 31_06
CLBLM_L.SLICEM_X0.A5FF.ZRST 01_07
CLBLM_L.SLICEM_X0.A5FFMUX.IN_A 30_09
CLBLM_L.SLICEM_X0.A5FFMUX.IN_B 30_10
CLBLM_L.SLICEM_X0.ADI1MUX.AI !22_00 !23_00 !24_00 00_00 25_00
CLBLM_L.SLICEM_X0.AFF.ZINI 31_03
CLBLM_L.SLICEM_X0.AFF.ZRST 30_12
CLBLM_L.SLICEM_X0.AFFMUX.AX !30_00 !30_02 !30_03 30_01
@ -420,12 +420,12 @@ CLBLM_L.SLICEM_X0.AOUTMUX.A5Q !30_06 !30_08 !30_11 30_07
CLBLM_L.SLICEM_X0.AOUTMUX.CY !30_07 !30_11 30_06 30_08
CLBLM_L.SLICEM_X0.AOUTMUX.F7 !30_08 !30_11 30_06 30_07
CLBLM_L.SLICEM_X0.AOUTMUX.O5 !30_07 !30_08 30_06 30_11
CLBLM_L.SLICEM_X0.AOUTMUX.O6 !30_06 !30_07 !30_08 30_11
CLBLM_L.SLICEM_X0.AOUTMUX.XOR !30_06 !30_07 !30_11 30_08
CLBLM_L.SLICEM_X0.B5FF.ZINI 31_22
CLBLM_L.SLICEM_X0.B5FF.ZRST 01_19
CLBLM_L.SLICEM_X0.B5FFMUX.IN_A 30_19
CLBLM_L.SLICEM_X0.B5FFMUX.IN_B 30_18
CLBLM_L.SLICEM_X0.BDI1MUX.BI 00_20
CLBLM_L.SLICEM_X0.BFF.ZINI 31_28
CLBLM_L.SLICEM_X0.BFF.ZRST 30_30
CLBLM_L.SLICEM_X0.BFFMUX.BX !30_24 !30_25 !30_27 30_26
@ -506,19 +506,16 @@ CLBLM_L.SLICEM_X0.BOUTMUX.B5Q !30_20 !30_21 !30_22 30_23
CLBLM_L.SLICEM_X0.BOUTMUX.CY !30_20 !30_23 30_21 30_22
CLBLM_L.SLICEM_X0.BOUTMUX.F8 !30_20 !30_21 30_22 30_23
CLBLM_L.SLICEM_X0.BOUTMUX.O5 !30_21 !30_23 30_20 30_22
CLBLM_L.SLICEM_X0.BOUTMUX.O6 !30_21 !30_22 !30_23 30_20
CLBLM_L.SLICEM_X0.BOUTMUX.XOR !30_20 !30_22 !30_23 30_21
CLBLM_L.SLICEM_X0.C5FF.ZINI 31_41
CLBLM_L.SLICEM_X0.C5FF.ZRST 01_47
CLBLM_L.SLICEM_X0.C5FFMUX.IN_A 31_45
CLBLM_L.SLICEM_X0.C5FFMUX.IN_B 30_39
CLBLM_L.SLICEM_X0.CARRY4.ACY0 !30_00 !30_02 !30_03 30_01 30_12 30_15 31_03
CLBLM_L.SLICEM_X0.CARRY4.ACY0 30_15
CLBLM_L.SLICEM_X0.CARRY4.BCY0 !30_24 !30_25 !30_27 01_15 30_26 30_30 31_28
CLBLM_L.SLICEM_X0.CARRY4.ACY0 30_01 30_12 30_15 31_03
CLBLM_L.SLICEM_X0.CARRY4.BCY0 01_15
CLBLM_L.SLICEM_X0.CARRY4.CCY0 !30_35 !30_37 !30_38 30_33 30_36 30_48 31_33
CLBLM_L.SLICEM_X0.CARRY4.CCY0 30_48
CLBLM_L.SLICEM_X0.CARRY4.DCY0 30_49
CLBLM_L.SLICEM_X0.CDI1MUX.CI 01_43
CLBLM_L.SLICEM_X0.CEUSEDMUX 01_39
CLBLM_L.SLICEM_X0.CFF.ZINI 31_33
CLBLM_L.SLICEM_X0.CFF.ZRST 30_33
@ -601,11 +598,12 @@ CLBLM_L.SLICEM_X0.COUTMUX.C5Q !30_40 !30_44 !30_45 30_43
CLBLM_L.SLICEM_X0.COUTMUX.CY !30_43 !30_45 30_40 30_44
CLBLM_L.SLICEM_X0.COUTMUX.F7 !30_44 !30_45 30_40 30_43
CLBLM_L.SLICEM_X0.COUTMUX.O5 !30_43 !30_44 30_40 30_45
CLBLM_L.SLICEM_X0.COUTMUX.O6 !30_40 !30_43 !30_44 30_45
CLBLM_L.SLICEM_X0.COUTMUX.XOR !30_40 !30_43 !30_45 30_44
CLBLM_L.SLICEM_X0.D5FF.ZINI 31_51
CLBLM_L.SLICEM_X0.D5FF.ZRST 01_55
CLBLM_L.SLICEM_X0.D5FFMUX.IN_A 30_55
CLBLM_L.SLICEM_X0.D5FFMUX.IN_B 30_54
CLBLM_L.SLICEM_X0.D5FFMUX.IN_B 21_55 25_55 30_54
CLBLM_L.SLICEM_X0.DFF.ZINI 31_58
CLBLM_L.SLICEM_X0.DFF.ZRST 30_50
CLBLM_L.SLICEM_X0.DFFMUX.CY !30_59 !30_61 30_60 30_62
@ -683,12 +681,13 @@ CLBLM_L.SLICEM_X0.DLUT.SRL 30_47
CLBLM_L.SLICEM_X0.DOUTMUX.CY !30_56 !30_57 30_51 30_52
CLBLM_L.SLICEM_X0.DOUTMUX.D5Q !30_51 !30_52 !30_56 30_57
CLBLM_L.SLICEM_X0.DOUTMUX.O5 !30_51 !30_57 30_52 30_56
CLBLM_L.SLICEM_X0.DOUTMUX.O6 !30_51 !30_52 !30_57 30_56
CLBLM_L.SLICEM_X0.DOUTMUX.XOR !30_52 !30_56 !30_57 30_51
CLBLM_L.SLICEM_X0.FFSYNC 00_48
CLBLM_L.SLICEM_X0.LATCH 30_32
CLBLM_L.SLICEM_X0.PRECYINIT.1 00_12
CLBLM_L.SLICEM_X0.PRECYINIT.AX 30_14
CLBLM_L.SLICEM_X0.PRECYINIT.CIN 30_13
CLBLM_L.SLICEM_X0.PRECYINIT.1 !30_13 !30_14 00_12
CLBLM_L.SLICEM_X0.PRECYINIT.AX !00_12 !30_13 30_14
CLBLM_L.SLICEM_X0.PRECYINIT.CIN !00_12 !30_14 30_13
CLBLM_L.SLICEM_X0.SRUSEDMUX 01_35
CLBLM_L.SLICEM_X0.WA7USED 00_40
CLBLM_L.SLICEM_X0.WA8USED 01_27

39
kintex7/segbits_clblm_r.db
View File

@ -78,6 +78,7 @@ CLBLM_R.SLICEL_X1.AOUTMUX.A5Q !31_07 !31_09 !31_10 30_05
CLBLM_R.SLICEL_X1.AOUTMUX.CY !30_05 !31_09 31_07 31_10
CLBLM_R.SLICEL_X1.AOUTMUX.F7 !31_07 !31_09 30_05 31_10
CLBLM_R.SLICEL_X1.AOUTMUX.O5 !30_05 !31_07 31_09 31_10
CLBLM_R.SLICEL_X1.AOUTMUX.O6 !30_05 !31_07 !31_10 31_09
CLBLM_R.SLICEL_X1.AOUTMUX.XOR !30_05 !31_09 !31_10 31_07
CLBLM_R.SLICEL_X1.B5FF.ZINI 31_23
CLBLM_R.SLICEL_X1.B5FF.ZRST 00_16
@ -159,16 +160,14 @@ CLBLM_R.SLICEL_X1.BOUTMUX.B5Q !30_28 !31_20 !31_21 30_29
CLBLM_R.SLICEL_X1.BOUTMUX.CY !30_29 !31_20 30_28 31_21
CLBLM_R.SLICEL_X1.BOUTMUX.F8 !30_28 !31_20 30_29 31_21
CLBLM_R.SLICEL_X1.BOUTMUX.O5 !30_28 !30_29 31_20 31_21
CLBLM_R.SLICEL_X1.BOUTMUX.O6 !30_28 !30_29 !31_21 31_20
CLBLM_R.SLICEL_X1.BOUTMUX.XOR !30_29 !31_20 !31_21 30_28
CLBLM_R.SLICEL_X1.C5FF.ZINI 31_42
CLBLM_R.SLICEL_X1.C5FF.ZRST 00_44
CLBLM_R.SLICEL_X1.C5FFMUX.IN_A 31_44
CLBLM_R.SLICEL_X1.C5FFMUX.IN_B 31_39
CLBLM_R.SLICEL_X1.CARRY4.ACY0 !30_04 !31_00 !31_02 31_01 31_04 31_14 31_15
CLBLM_R.SLICEL_X1.CARRY4.ACY0 31_14
CLBLM_R.SLICEL_X1.CARRY4.BCY0 !31_24 !31_25 !31_26 00_08 31_27 31_29 31_30
CLBLM_R.SLICEL_X1.CARRY4.BCY0 00_08
CLBLM_R.SLICEL_X1.CARRY4.CCY0 !31_35 !31_36 !31_37 30_34 31_34 31_38 31_48
CLBLM_R.SLICEL_X1.CARRY4.ACY0 31_01 31_04 31_14 31_15
CLBLM_R.SLICEL_X1.CARRY4.BCY0 00_08 31_27 31_29 31_30
CLBLM_R.SLICEL_X1.CARRY4.CCY0 31_48
CLBLM_R.SLICEL_X1.CARRY4.DCY0 31_49
CLBLM_R.SLICEL_X1.CEUSEDMUX 00_36
@ -249,11 +248,12 @@ CLBLM_R.SLICEL_X1.COUTMUX.C5Q !30_42 !31_40 !31_43 30_41
CLBLM_R.SLICEL_X1.COUTMUX.CY !30_41 !31_43 30_42 31_40
CLBLM_R.SLICEL_X1.COUTMUX.F7 !30_42 !31_43 30_41 31_40
CLBLM_R.SLICEL_X1.COUTMUX.O5 !30_41 !30_42 31_40 31_43
CLBLM_R.SLICEL_X1.COUTMUX.O6 !30_41 !30_42 !31_40 31_43
CLBLM_R.SLICEL_X1.COUTMUX.XOR !30_41 !31_40 !31_43 30_42
CLBLM_R.SLICEL_X1.D5FF.ZINI 31_52
CLBLM_R.SLICEL_X1.D5FF.ZRST 00_56
CLBLM_R.SLICEL_X1.D5FFMUX.IN_A 31_55
CLBLM_R.SLICEL_X1.D5FFMUX.IN_B 31_54
CLBLM_R.SLICEL_X1.D5FFMUX.IN_B 25_63 31_54
CLBLM_R.SLICEL_X1.DFF.ZINI 31_59
CLBLM_R.SLICEL_X1.DFF.ZRST 31_50
CLBLM_R.SLICEL_X1.DFFMUX.CY !31_60 !31_61 30_58 31_62
@ -328,18 +328,18 @@ CLBLM_R.SLICEL_X1.DLUT.INIT[63] 28_48
CLBLM_R.SLICEL_X1.DOUTMUX.CY !31_53 !31_56 30_53 31_57
CLBLM_R.SLICEL_X1.DOUTMUX.D5Q !30_53 !31_56 !31_57 31_53
CLBLM_R.SLICEL_X1.DOUTMUX.O5 !30_53 !31_53 31_56 31_57
CLBLM_R.SLICEL_X1.DOUTMUX.O6 !30_53 !31_53 !31_57 31_56
CLBLM_R.SLICEL_X1.DOUTMUX.XOR !31_53 !31_56 !31_57 30_53
CLBLM_R.SLICEL_X1.FFSYNC 01_31
CLBLM_R.SLICEL_X1.LATCH 31_32
CLBLM_R.SLICEL_X1.PRECYINIT.1 01_11
CLBLM_R.SLICEL_X1.PRECYINIT.AX 31_13
CLBLM_R.SLICEL_X1.PRECYINIT.CIN 31_12
CLBLM_R.SLICEL_X1.PRECYINIT.1 !31_12 !31_13 01_11
CLBLM_R.SLICEL_X1.PRECYINIT.AX !01_11 !31_12 31_13
CLBLM_R.SLICEL_X1.PRECYINIT.CIN !01_11 !31_13 31_12
CLBLM_R.SLICEL_X1.SRUSEDMUX 00_32
CLBLM_R.SLICEM_X0.A5FF.ZINI 31_06
CLBLM_R.SLICEM_X0.A5FF.ZRST 01_07
CLBLM_R.SLICEM_X0.A5FFMUX.IN_A 30_09
CLBLM_R.SLICEM_X0.A5FFMUX.IN_B 30_10
CLBLM_R.SLICEM_X0.ADI1MUX.AI !22_00 !23_00 !24_00 00_00 25_00
CLBLM_R.SLICEM_X0.AFF.ZINI 31_03
CLBLM_R.SLICEM_X0.AFF.ZRST 30_12
CLBLM_R.SLICEM_X0.AFFMUX.AX !30_00 !30_02 !30_03 30_01
@ -420,12 +420,12 @@ CLBLM_R.SLICEM_X0.AOUTMUX.A5Q !30_06 !30_08 !30_11 30_07
CLBLM_R.SLICEM_X0.AOUTMUX.CY !30_07 !30_11 30_06 30_08
CLBLM_R.SLICEM_X0.AOUTMUX.F7 !30_08 !30_11 30_06 30_07
CLBLM_R.SLICEM_X0.AOUTMUX.O5 !30_07 !30_08 30_06 30_11
CLBLM_R.SLICEM_X0.AOUTMUX.O6 !30_06 !30_07 !30_08 30_11
CLBLM_R.SLICEM_X0.AOUTMUX.XOR !30_06 !30_07 !30_11 30_08
CLBLM_R.SLICEM_X0.B5FF.ZINI 31_22
CLBLM_R.SLICEM_X0.B5FF.ZRST 01_19
CLBLM_R.SLICEM_X0.B5FFMUX.IN_A 30_19
CLBLM_R.SLICEM_X0.B5FFMUX.IN_B 30_18
CLBLM_R.SLICEM_X0.BDI1MUX.BI 00_20
CLBLM_R.SLICEM_X0.BFF.ZINI 31_28
CLBLM_R.SLICEM_X0.BFF.ZRST 30_30
CLBLM_R.SLICEM_X0.BFFMUX.BX !30_24 !30_25 !30_27 30_26
@ -506,19 +506,16 @@ CLBLM_R.SLICEM_X0.BOUTMUX.B5Q !30_20 !30_21 !30_22 30_23
CLBLM_R.SLICEM_X0.BOUTMUX.CY !30_20 !30_23 30_21 30_22
CLBLM_R.SLICEM_X0.BOUTMUX.F8 !30_20 !30_21 30_22 30_23
CLBLM_R.SLICEM_X0.BOUTMUX.O5 !30_21 !30_23 30_20 30_22
CLBLM_R.SLICEM_X0.BOUTMUX.O6 !30_21 !30_22 !30_23 30_20
CLBLM_R.SLICEM_X0.BOUTMUX.XOR !30_20 !30_22 !30_23 30_21
CLBLM_R.SLICEM_X0.C5FF.ZINI 31_41
CLBLM_R.SLICEM_X0.C5FF.ZRST 01_47
CLBLM_R.SLICEM_X0.C5FFMUX.IN_A 31_45
CLBLM_R.SLICEM_X0.C5FFMUX.IN_B 30_39
CLBLM_R.SLICEM_X0.CARRY4.ACY0 !30_00 !30_02 !30_03 30_01 30_12 30_15 31_03
CLBLM_R.SLICEM_X0.CARRY4.ACY0 30_15
CLBLM_R.SLICEM_X0.CARRY4.BCY0 !30_24 !30_25 !30_27 01_15 30_26 30_30 31_28
CLBLM_R.SLICEM_X0.CARRY4.ACY0 30_01 30_12 30_15 31_03
CLBLM_R.SLICEM_X0.CARRY4.BCY0 01_15
CLBLM_R.SLICEM_X0.CARRY4.CCY0 !30_35 !30_37 !30_38 30_33 30_36 30_48 31_33
CLBLM_R.SLICEM_X0.CARRY4.CCY0 30_48
CLBLM_R.SLICEM_X0.CARRY4.DCY0 30_49
CLBLM_R.SLICEM_X0.CDI1MUX.CI 01_43
CLBLM_R.SLICEM_X0.CEUSEDMUX 01_39
CLBLM_R.SLICEM_X0.CFF.ZINI 31_33
CLBLM_R.SLICEM_X0.CFF.ZRST 30_33
@ -601,11 +598,12 @@ CLBLM_R.SLICEM_X0.COUTMUX.C5Q !30_40 !30_44 !30_45 30_43
CLBLM_R.SLICEM_X0.COUTMUX.CY !30_43 !30_45 30_40 30_44
CLBLM_R.SLICEM_X0.COUTMUX.F7 !30_44 !30_45 30_40 30_43
CLBLM_R.SLICEM_X0.COUTMUX.O5 !30_43 !30_44 30_40 30_45
CLBLM_R.SLICEM_X0.COUTMUX.O6 !30_40 !30_43 !30_44 30_45
CLBLM_R.SLICEM_X0.COUTMUX.XOR !30_40 !30_43 !30_45 30_44
CLBLM_R.SLICEM_X0.D5FF.ZINI 31_51
CLBLM_R.SLICEM_X0.D5FF.ZRST 01_55
CLBLM_R.SLICEM_X0.D5FFMUX.IN_A 30_55
CLBLM_R.SLICEM_X0.D5FFMUX.IN_B 30_54
CLBLM_R.SLICEM_X0.D5FFMUX.IN_B 21_55 25_55 30_54
CLBLM_R.SLICEM_X0.DFF.ZINI 31_58
CLBLM_R.SLICEM_X0.DFF.ZRST 30_50
CLBLM_R.SLICEM_X0.DFFMUX.CY !30_59 !30_61 30_60 30_62
@ -683,12 +681,13 @@ CLBLM_R.SLICEM_X0.DLUT.SRL 30_47
CLBLM_R.SLICEM_X0.DOUTMUX.CY !30_56 !30_57 30_51 30_52
CLBLM_R.SLICEM_X0.DOUTMUX.D5Q !30_51 !30_52 !30_56 30_57
CLBLM_R.SLICEM_X0.DOUTMUX.O5 !30_51 !30_57 30_52 30_56
CLBLM_R.SLICEM_X0.DOUTMUX.O6 !30_51 !30_52 !30_57 30_56
CLBLM_R.SLICEM_X0.DOUTMUX.XOR !30_52 !30_56 !30_57 30_51
CLBLM_R.SLICEM_X0.FFSYNC 00_48
CLBLM_R.SLICEM_X0.LATCH 30_32
CLBLM_R.SLICEM_X0.PRECYINIT.1 00_12
CLBLM_R.SLICEM_X0.PRECYINIT.AX 30_14
CLBLM_R.SLICEM_X0.PRECYINIT.CIN 30_13
CLBLM_R.SLICEM_X0.PRECYINIT.1 !30_13 !30_14 00_12
CLBLM_R.SLICEM_X0.PRECYINIT.AX !00_12 !30_13 30_14
CLBLM_R.SLICEM_X0.PRECYINIT.CIN !00_12 !30_14 30_13
CLBLM_R.SLICEM_X0.SRUSEDMUX 01_35
CLBLM_R.SLICEM_X0.WA7USED 00_40
CLBLM_R.SLICEM_X0.WA8USED 01_27

14
kintex7/segbits_int_l.db
View File

@ -19,7 +19,7 @@ INT_L.BYP_ALT0.SL1END0 !23_07 19_06 22_07 24_07 25_07
INT_L.BYP_ALT0.SR1END_N3_3 !22_07 18_06 23_07 24_07 25_07
INT_L.BYP_ALT0.SS2END0 !22_07 !23_07 !25_07 16_07 24_07
INT_L.BYP_ALT0.SW2END0 !22_07 !23_07 !24_07 16_07 25_07
INT_L.BYP_ALT0.VCC_WIRE !30_04 !30_58 !31_00 !31_01 !31_24 !31_25 !31_27 !31_35 !31_36 !31_38 !31_60 !31_61 31_02 31_26 31_37 31_62
INT_L.BYP_ALT0.VCC_WIRE 31_02 31_26 31_37 31_62
INT_L.BYP_ALT0.WL1END0 !23_07 17_07 22_07 24_07 25_07
INT_L.BYP_ALT0.WR1END0 !22_07 16_07 23_07 24_07 25_07
INT_L.BYP_ALT0.WW2END_N0_3 !22_07 !23_07 !25_07 17_07 24_07
@ -44,7 +44,7 @@ INT_L.BYP_ALT1.SL1END0 !23_15 19_14 22_15 24_15 25_15
INT_L.BYP_ALT1.SR1BEG_S0 !22_15 18_14 23_15 24_15 25_15
INT_L.BYP_ALT1.SS2END0 !22_15 !23_15 !25_15 19_14 24_15
INT_L.BYP_ALT1.SW2END0 !22_15 !23_15 !24_15 19_14 25_15
INT_L.BYP_ALT1.VCC_WIRE !30_00 !30_01 !30_03 !30_24 !30_26 !30_27 !30_35 !30_36 !30_38 !30_59 !30_61 !30_62 30_02 30_25 30_37 30_60
INT_L.BYP_ALT1.VCC_WIRE 30_02 30_25 30_37 30_60
INT_L.BYP_ALT1.WL1END0 !23_15 16_15 22_15 24_15 25_15
INT_L.BYP_ALT1.WR1END1 !22_15 17_15 23_15 24_15 25_15
INT_L.BYP_ALT1.WW2END0 !22_15 !23_15 !25_15 18_14 24_15
@ -607,7 +607,7 @@ INT_L.FAN_ALT1.EL1END3 !22_48 17_48 23_48 24_48 25_48
INT_L.FAN_ALT1.ER1END2 !23_48 16_48 22_48 24_48 25_48
INT_L.FAN_ALT1.FAN_BOUNCE3 !22_48 20_48 23_48 24_48 25_48
INT_L.FAN_ALT1.FAN_BOUNCE_S3_4 !23_48 20_48 22_48 24_48 25_48
INT_L.FAN_ALT1.GFAN1 !00_18 !00_19 !01_13 !22_48 !23_48 !24_48 00_14 00_17 21_48 25_48
INT_L.FAN_ALT1.GFAN1 00_14 00_17 21_48 25_48
INT_L.FAN_ALT1.LOGIC_OUTS_L11 !22_48 21_48 23_48 24_48 25_48
INT_L.FAN_ALT1.LOGIC_OUTS_L17 !22_48 !23_48 !25_48 21_48 24_48
INT_L.FAN_ALT1.LOGIC_OUTS_L7 !23_48 21_48 22_48 24_48 25_48
@ -655,7 +655,7 @@ INT_L.FAN_ALT3.EL1END3 !22_56 16_56 23_56 24_56 25_56
INT_L.FAN_ALT3.ER1END3 !23_56 17_56 22_56 24_56 25_56
INT_L.FAN_ALT3.FAN_BOUNCE_S3_0 !22_56 20_56 23_56 24_56 25_56
INT_L.FAN_ALT3.FAN_BOUNCE_S3_2 !23_56 20_56 22_56 24_56 25_56
INT_L.FAN_ALT3.GFAN1 !22_56 !23_56 !24_56 21_56 25_56
INT_L.FAN_ALT3.GFAN1 00_14 00_17 21_56 25_56
INT_L.FAN_ALT3.LOGIC_OUTS_L15 !22_56 21_56 23_56 24_56 25_56
INT_L.FAN_ALT3.LOGIC_OUTS_L21 !22_56 !23_56 !25_56 21_56 24_56
INT_L.FAN_ALT3.LOGIC_OUTS_L3 !23_56 21_56 22_56 24_56 25_56
@ -672,7 +672,7 @@ INT_L.FAN_ALT3.SW2END3 !22_56 !23_56 !25_56 18_57 24_56
INT_L.FAN_ALT3.WL1END3 !22_56 17_56 23_56 24_56 25_56
INT_L.FAN_ALT3.WR1END3 !23_56 16_56 22_56 24_56 25_56
INT_L.FAN_ALT3.WW2END3 !22_56 !23_56 !24_56 19_57 25_56
INT_L.FAN_ALT4.BYP_BOUNCE_N3_3 !22_08 !23_08 !24_08 20_08 25_08
INT_L.FAN_ALT4.BYP_BOUNCE_N3_3 20_08 25_08
INT_L.FAN_ALT4.BYP_BOUNCE_N3_7 !22_08 !23_08 !25_08 20_08 24_08
INT_L.FAN_ALT4.EE2END0 !22_08 !23_08 !24_08 16_08 25_08
INT_L.FAN_ALT4.EL1END0 !22_08 16_08 23_08 24_08 25_08
@ -703,7 +703,7 @@ INT_L.FAN_ALT5.EL1END2 !22_40 16_40 23_40 24_40 25_40
INT_L.FAN_ALT5.ER1END2 !23_40 17_40 22_40 24_40 25_40
INT_L.FAN_ALT5.FAN_BOUNCE1 !22_40 20_40 23_40 24_40 25_40
INT_L.FAN_ALT5.FAN_BOUNCE_S3_0 !23_40 20_40 22_40 24_40 25_40
INT_L.FAN_ALT5.GFAN1 !00_18 !00_19 !01_13 !22_40 !23_40 !24_40 00_14 00_17 21_40 25_40
INT_L.FAN_ALT5.GFAN1 21_40 25_40
INT_L.FAN_ALT5.LOGIC_OUTS_L10 !22_40 21_40 23_40 24_40 25_40
INT_L.FAN_ALT5.LOGIC_OUTS_L16 !22_40 !23_40 !25_40 21_40 24_40
INT_L.FAN_ALT5.LOGIC_OUTS_L6 !23_40 21_40 22_40 24_40 25_40
@ -2026,7 +2026,7 @@ INT_L.LV_L0.WR1END0 00_02 00_07
INT_L.LV_L0.WW4END0 00_05 00_07
INT_L.LV_L18.ER1END0 00_03 00_06
INT_L.LV_L18.LH0 00_01 01_02
INT_L.LV_L18.LH12 01_02
INT_L.LV_L18.LH12 01_02 01_08
INT_L.LV_L18.LH6 00_06 01_02
INT_L.LV_L18.LV_L0 01_00 01_01
INT_L.LV_L18.NN6END0 00_03 01_00

14
kintex7/segbits_int_r.db
View File

@ -19,7 +19,7 @@ INT_R.BYP_ALT0.SL1END0 !23_07 19_06 22_07 24_07 25_07
INT_R.BYP_ALT0.SR1END_N3_3 !22_07 18_06 23_07 24_07 25_07
INT_R.BYP_ALT0.SS2END0 !22_07 !23_07 !25_07 16_07 24_07
INT_R.BYP_ALT0.SW2END0 !22_07 !23_07 !24_07 16_07 25_07
INT_R.BYP_ALT0.VCC_WIRE !30_04 !30_58 !31_00 !31_01 !31_24 !31_25 !31_27 !31_35 !31_36 !31_38 !31_60 !31_61 31_02 31_26 31_37 31_62
INT_R.BYP_ALT0.VCC_WIRE 31_02 31_26 31_37 31_62
INT_R.BYP_ALT0.WL1END0 !23_07 17_07 22_07 24_07 25_07
INT_R.BYP_ALT0.WR1END0 !22_07 16_07 23_07 24_07 25_07
INT_R.BYP_ALT0.WW2END_N0_3 !22_07 !23_07 !25_07 17_07 24_07
@ -44,7 +44,7 @@ INT_R.BYP_ALT1.SL1END0 !23_15 19_14 22_15 24_15 25_15
INT_R.BYP_ALT1.SR1BEG_S0 !22_15 18_14 23_15 24_15 25_15
INT_R.BYP_ALT1.SS2END0 !22_15 !23_15 !25_15 19_14 24_15
INT_R.BYP_ALT1.SW2END0 !22_15 !23_15 !24_15 19_14 25_15
INT_R.BYP_ALT1.VCC_WIRE !30_00 !30_01 !30_03 !30_24 !30_26 !30_27 !30_35 !30_36 !30_38 !30_59 !30_61 !30_62 30_02 30_25 30_37 30_60
INT_R.BYP_ALT1.VCC_WIRE 30_02 30_25 30_37 30_60
INT_R.BYP_ALT1.WL1END0 !23_15 16_15 22_15 24_15 25_15
INT_R.BYP_ALT1.WR1END1 !22_15 17_15 23_15 24_15 25_15
INT_R.BYP_ALT1.WW2END0 !22_15 !23_15 !25_15 18_14 24_15
@ -607,7 +607,7 @@ INT_R.FAN_ALT1.EL1END3 !22_48 17_48 23_48 24_48 25_48
INT_R.FAN_ALT1.ER1END2 !23_48 16_48 22_48 24_48 25_48
INT_R.FAN_ALT1.FAN_BOUNCE3 !22_48 20_48 23_48 24_48 25_48
INT_R.FAN_ALT1.FAN_BOUNCE_S3_4 !23_48 20_48 22_48 24_48 25_48
INT_R.FAN_ALT1.GFAN1 !00_18 !00_19 !01_13 !22_48 !23_48 !24_48 00_14 00_17 21_48 25_48
INT_R.FAN_ALT1.GFAN1 00_14 00_17 21_48 25_48
INT_R.FAN_ALT1.LOGIC_OUTS11 !22_48 21_48 23_48 24_48 25_48
INT_R.FAN_ALT1.LOGIC_OUTS17 !22_48 !23_48 !25_48 21_48 24_48
INT_R.FAN_ALT1.LOGIC_OUTS7 !23_48 21_48 22_48 24_48 25_48
@ -655,7 +655,7 @@ INT_R.FAN_ALT3.EL1END3 !22_56 16_56 23_56 24_56 25_56
INT_R.FAN_ALT3.ER1END3 !23_56 17_56 22_56 24_56 25_56
INT_R.FAN_ALT3.FAN_BOUNCE_S3_0 !22_56 20_56 23_56 24_56 25_56
INT_R.FAN_ALT3.FAN_BOUNCE_S3_2 !23_56 20_56 22_56 24_56 25_56
INT_R.FAN_ALT3.GFAN1 !22_56 !23_56 !24_56 21_56 25_56
INT_R.FAN_ALT3.GFAN1 00_14 00_17 21_56 25_56
INT_R.FAN_ALT3.LOGIC_OUTS15 !22_56 21_56 23_56 24_56 25_56
INT_R.FAN_ALT3.LOGIC_OUTS21 !22_56 !23_56 !25_56 21_56 24_56
INT_R.FAN_ALT3.LOGIC_OUTS3 !23_56 21_56 22_56 24_56 25_56
@ -672,7 +672,7 @@ INT_R.FAN_ALT3.SW2END3 !22_56 !23_56 !25_56 18_57 24_56
INT_R.FAN_ALT3.WL1END3 !22_56 17_56 23_56 24_56 25_56
INT_R.FAN_ALT3.WR1END3 !23_56 16_56 22_56 24_56 25_56
INT_R.FAN_ALT3.WW2END3 !22_56 !23_56 !24_56 19_57 25_56
INT_R.FAN_ALT4.BYP_BOUNCE_N3_3 !22_08 !23_08 !24_08 20_08 25_08
INT_R.FAN_ALT4.BYP_BOUNCE_N3_3 20_08 25_08
INT_R.FAN_ALT4.BYP_BOUNCE_N3_7 !22_08 !23_08 !25_08 20_08 24_08
INT_R.FAN_ALT4.EE2END0 !22_08 !23_08 !24_08 16_08 25_08
INT_R.FAN_ALT4.EL1END0 !22_08 16_08 23_08 24_08 25_08
@ -696,14 +696,14 @@ INT_R.FAN_ALT4.SW2END0 !22_08 !23_08 !25_08 18_09 24_08
INT_R.FAN_ALT4.WL1END0 !22_08 17_08 23_08 24_08 25_08
INT_R.FAN_ALT4.WR1END0 !23_08 16_08 22_08 24_08 25_08
INT_R.FAN_ALT4.WW2END0 !22_08 !23_08 !24_08 19_09 25_08
INT_R.FAN_ALT5.BYP_BOUNCE1 !22_40 !23_40 !25_40 20_40 24_40
INT_R.FAN_ALT5.BYP_BOUNCE1 20_40 24_40
INT_R.FAN_ALT5.BYP_BOUNCE5 !22_40 !23_40 !24_40 20_40 25_40
INT_R.FAN_ALT5.EE2END2 !22_40 !23_40 !24_40 16_40 25_40
INT_R.FAN_ALT5.EL1END2 !22_40 16_40 23_40 24_40 25_40
INT_R.FAN_ALT5.ER1END2 !23_40 17_40 22_40 24_40 25_40
INT_R.FAN_ALT5.FAN_BOUNCE1 !22_40 20_40 23_40 24_40 25_40
INT_R.FAN_ALT5.FAN_BOUNCE_S3_0 !23_40 20_40 22_40 24_40 25_40
INT_R.FAN_ALT5.GFAN1 !22_40 !23_40 !24_40 21_40 25_40
INT_R.FAN_ALT5.GFAN1 00_14 00_17 21_40 25_40
INT_R.FAN_ALT5.LOGIC_OUTS10 !22_40 21_40 23_40 24_40 25_40
INT_R.FAN_ALT5.LOGIC_OUTS16 !22_40 !23_40 !25_40 21_40 24_40
INT_R.FAN_ALT5.LOGIC_OUTS6 !23_40 21_40 22_40 24_40 25_40

5
kintex7/settings.sh
View File

@ -2,8 +2,11 @@ export XRAY_DATABASE="kintex7"
export XRAY_PART="xc7k70tfbg676-2"
export XRAY_ROI_FRAMES="0x00000000:0xffffffff"
export XRAY_ROI="SLICE_X0Y50:SLICE_X19Y99 DSP48_X0Y20:DSP48_X0Y39 RAMB18_X0Y20:RAMB18_X0Y39 RAMB36_X0Y10:RAMB36_X0Y19"
# FIXME: make entire part
export XRAY_ROI_TILEGRID="SLICE_X0Y50:SLICE_X19Y99 DSP48_X0Y20:DSP48_X0Y39 RAMB18_X0Y20:RAMB18_X0Y39 RAMB36_X0Y10:RAMB36_X0Y19"
# These settings must remain in sync
export XRAY_ROI="SLICE_X0Y50:SLICE_X19Y99 DSP48_X0Y20:DSP48_X0Y39 RAMB18_X0Y20:RAMB18_X0Y39 RAMB36_X0Y10:RAMB36_X0Y19"
# Part of CMT X0Y1
export XRAY_ROI_GRID_X1="9"
export XRAY_ROI_GRID_X2="38"

910804
kintex7/tileconn.json
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File diff suppressed because it is too large Load Diff

70
kintex7/tilegrid.json
View File

@ -7321,6 +7321,13 @@
},
"BRAM_L_X6Y50": {
"bits": {
"BLOCK_RAM": {
"baseaddr": "0x00C00000",
"frames": 128,
"height": 10,
"offset": 0,
"words": 10
},
"CLB_IO_CLK": {
"baseaddr": "0x00400300",
"frames": 28,
@ -7342,6 +7349,13 @@
},
"BRAM_L_X6Y55": {
"bits": {
"BLOCK_RAM": {
"baseaddr": "0x00C00000",
"frames": 128,
"height": 10,
"offset": 10,
"words": 10
},
"CLB_IO_CLK": {
"baseaddr": "0x00400300",
"frames": 28,
@ -7363,6 +7377,13 @@
},
"BRAM_L_X6Y60": {
"bits": {
"BLOCK_RAM": {
"baseaddr": "0x00C00000",
"frames": 128,
"height": 10,
"offset": 20,
"words": 10
},
"CLB_IO_CLK": {
"baseaddr": "0x00400300",
"frames": 28,
@ -7384,6 +7405,13 @@
},
"BRAM_L_X6Y65": {
"bits": {
"BLOCK_RAM": {
"baseaddr": "0x00C00000",
"frames": 128,
"height": 10,
"offset": 30,
"words": 10
},
"CLB_IO_CLK": {
"baseaddr": "0x00400300",
"frames": 28,
@ -7405,6 +7433,13 @@
},
"BRAM_L_X6Y70": {
"bits": {
"BLOCK_RAM": {
"baseaddr": "0x00C00000",
"frames": 128,
"height": 10,
"offset": 40,
"words": 10
},
"CLB_IO_CLK": {
"baseaddr": "0x00400300",
"frames": 28,
@ -7426,6 +7461,13 @@
},
"BRAM_L_X6Y75": {
"bits": {
"BLOCK_RAM": {
"baseaddr": "0x00C00000",
"frames": 128,
"height": 10,
"offset": 51,
"words": 10
},
"CLB_IO_CLK": {
"baseaddr": "0x00400300",
"frames": 28,
@ -7447,6 +7489,13 @@
},
"BRAM_L_X6Y80": {
"bits": {
"BLOCK_RAM": {
"baseaddr": "0x00C00000",
"frames": 128,
"height": 10,
"offset": 61,
"words": 10
},
"CLB_IO_CLK": {
"baseaddr": "0x00400300",
"frames": 28,
@ -7468,6 +7517,13 @@
},
"BRAM_L_X6Y85": {
"bits": {
"BLOCK_RAM": {
"baseaddr": "0x00C00000",
"frames": 128,
"height": 10,
"offset": 71,
"words": 10
},
"CLB_IO_CLK": {
"baseaddr": "0x00400300",
"frames": 28,
@ -7489,6 +7545,13 @@
},
"BRAM_L_X6Y90": {
"bits": {
"BLOCK_RAM": {
"baseaddr": "0x00C00000",
"frames": 128,
"height": 10,
"offset": 81,
"words": 10
},
"CLB_IO_CLK": {
"baseaddr": "0x00400300",
"frames": 28,
@ -7510,6 +7573,13 @@
},
"BRAM_L_X6Y95": {
"bits": {
"BLOCK_RAM": {
"baseaddr": "0x00C00000",
"frames": 128,
"height": 10,
"offset": 91,
"words": 10
},
"CLB_IO_CLK": {
"baseaddr": "0x00400300",
"frames": 28,