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prjxray-db
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Updating Artix DB based on "Merge pull request #275 from mcmasterg/rempips". 

See [Info File](Info.md) for details.

Signed-off-by: Tim 'mithro' Ansell <me@mith.ro>
This commit is contained in:
Tim 'mithro' Ansell 2018-12-06 21:23:53 +00:00
parent a620b9bef9
commit 04e855b7ce
26 changed files with 523996 additions and 482844 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

66
Info.md
View File

@ -37,35 +37,37 @@ These files are released under the very permissive [CC0 1.0 Universal](COPYING).
# Details
Last updated on Fri Dec 7 01:01:06 UTC 2018 (2018-12-07T01:01:06+00:00).
Last updated on Fri Dec 7 01:03:27 UTC 2018 (2018-12-07T01:03:27+00:00).
Created using [Project X-Ray](https://github.com/SymbiFlow/prjxray) version [v0.0-984-gb43bf35](https://github.com/SymbiFlow/prjxray/commit/b43bf3539f51ed8a755ae245682cd660ca23d813).
Created using [Project X-Ray](https://github.com/SymbiFlow/prjxray) version [v0.0-1084-gafe50c6](https://github.com/SymbiFlow/prjxray/commit/afe50c68c464c0cd4a3fa92b6a07c9abbe41682f).
Latest commit was;
```
commit b43bf3539f51ed8a755ae245682cd660ca23d813
Merge: b5d691c e2e236e
Author: Tim Ansell <me@mith.ro>
Date: Tue Nov 6 15:11:29 2018 -0800
commit afe50c68c464c0cd4a3fa92b6a07c9abbe41682f
Merge: 8385636 5c82555
Author: John McMaster <18452276+mcmasterg@users.noreply.github.com>
Date: Wed Nov 28 14:28:03 2018 -0800
Merge pull request #229 from mcmasterg/k7_bits
Merge pull request #275 from mcmasterg/rempips
k7: use all bitstream bits, format settings.sh alike
Rempips
```
## Database for [artix7](artix7/)
### Settings
Created using following [settings.sh (sha256: d77b40f729b66962f0197a5e31b43860326401b6116ac36e727411319adac0f2)](https://github.com/SymbiFlow/prjxray/blob/b43bf3539f51ed8a755ae245682cd660ca23d813/database/artix7/settings.sh)
Created using following [settings.sh (sha256: 5e7fd99c466d50e7074f812737417596ed2dd985a8f084bdb803ff06543d9b7f)](https://github.com/SymbiFlow/prjxray/blob/afe50c68c464c0cd4a3fa92b6a07c9abbe41682f/database/artix7/settings.sh)
```shell
export XRAY_DATABASE="artix7"
export XRAY_PART="xc7a50tfgg484-1"
export XRAY_ROI_FRAMES="0x00000000:0xffffffff"
# All CLB's in part, all BRAM's in part, all DSP's in part.
export XRAY_ROI="SLICE_X0Y0:SLICE_X65Y99 SLICE_X0Y100:SLICE_X57Y149 RAMB18_X0Y0:RAMB18_X1Y59 RAMB36_X0Y0:RAMB36_X1Y29 RAMB18_X2Y0:RAMB18_X2Y39 RAMB36_X2Y0:RAMB36_X2Y19 DSP48_X0Y0:DSP48_X1Y59"
export XRAY_ROI_TILEGRID="SLICE_X0Y0:SLICE_X65Y99 SLICE_X0Y100:SLICE_X57Y149 RAMB18_X0Y0:RAMB18_X1Y59 RAMB36_X0Y0:RAMB36_X1Y29 RAMB18_X2Y0:RAMB18_X2Y39 RAMB36_X2Y0:RAMB36_X2Y19 DSP48_X0Y0:DSP48_X1Y59"
# These settings must remain in sync
export XRAY_ROI="SLICE_X0Y100:SLICE_X35Y149 RAMB18_X0Y40:RAMB18_X0Y59 RAMB36_X0Y20:RAMB36_X0Y29 DSP48_X0Y40:DSP48_X0Y59"
# Most of CMT X0Y2.
export XRAY_ROI_GRID_X1="9"
export XRAY_ROI_GRID_X2="58"
@ -103,16 +105,12 @@ Results have checksums;
* [`65cbe9fc850652b79386575b9d9f7bb157757b27d49a40fc5297cff3f22084df ./artix7/harness/basys3/swbut/design.json`](./artix7/harness/basys3/swbut/design.json)
* [`cd4000b96378f736d31686b381ebd4349898b3b8bd09606223c7ca48cb1a5aba ./artix7/harness/basys3/swbut/design.txt`](./artix7/harness/basys3/swbut/design.txt)
* [`4c0a815ab8943181331f7aa9ac77655a0a640d9a409a602e4f24f8feb5f905e9 ./artix7/harness/README.md`](./artix7/harness/README.md)
* [`1c863520307fac805e9dec67ed91eabf663e7cf873b3da16e581cefa771ed9c4 ./artix7/mask_bram_l.db`](./artix7/mask_bram_l.db)
* [`9b0ecfed6b65de55c9975d59c92512f3f67ed5cc07106d027eb63edaffe53fca ./artix7/mask_bram_r.db`](./artix7/mask_bram_r.db)
* [`5c274320294201935a3edccb43eca8e347ca1f0acded71ec388c794877d4b55b ./artix7/mask_clbll_l.db`](./artix7/mask_clbll_l.db)
* [`5c274320294201935a3edccb43eca8e347ca1f0acded71ec388c794877d4b55b ./artix7/mask_clbll_r.db`](./artix7/mask_clbll_r.db)
* [`5c274320294201935a3edccb43eca8e347ca1f0acded71ec388c794877d4b55b ./artix7/mask_clblm_l.db`](./artix7/mask_clblm_l.db)
* [`5c274320294201935a3edccb43eca8e347ca1f0acded71ec388c794877d4b55b ./artix7/mask_clblm_r.db`](./artix7/mask_clblm_r.db)
* [`ad8008e2e4dfd461e421b15f236cd1862e501e5679ad292ede421122373e224f ./artix7/mask_dsp_l.db`](./artix7/mask_dsp_l.db)
* [`169a5dc2a069653f17dad854fff1895e3981bcd703109304f719d7f1b3a02ab1 ./artix7/mask_dsp_r.db`](./artix7/mask_dsp_r.db)
* [`76d1e0bd4b7ad492cf3fe8698b2b5f46f7dcc5fe446984e5dccae373c63edafd ./artix7/mask_hclk_l.db`](./artix7/mask_hclk_l.db)
* [`76d1e0bd4b7ad492cf3fe8698b2b5f46f7dcc5fe446984e5dccae373c63edafd ./artix7/mask_hclk_r.db`](./artix7/mask_hclk_r.db)
* [`5acfc8680a96dfe832cbcf70e55d98617323e8f37405d3dca7bcfda9b31aef17 ./artix7/mask_clbll_l.db`](./artix7/mask_clbll_l.db)
* [`615472574699aeeb8471224558ce13e18f14c3e65e3b5a2ecc862ee6d3e89211 ./artix7/mask_clbll_r.db`](./artix7/mask_clbll_r.db)
* [`5acfc8680a96dfe832cbcf70e55d98617323e8f37405d3dca7bcfda9b31aef17 ./artix7/mask_clblm_l.db`](./artix7/mask_clblm_l.db)
* [`615472574699aeeb8471224558ce13e18f14c3e65e3b5a2ecc862ee6d3e89211 ./artix7/mask_clblm_r.db`](./artix7/mask_clblm_r.db)
* [`c5aabee9a52c0eb671d569264639b6903e85e76e50ce57af8b7033062e81c2f5 ./artix7/mask_hclk_l.db`](./artix7/mask_hclk_l.db)
* [`c5aabee9a52c0eb671d569264639b6903e85e76e50ce57af8b7033062e81c2f5 ./artix7/mask_hclk_r.db`](./artix7/mask_hclk_r.db)
* [`6baea72435613b87334f95cfe2b1ab36da4d57ada20b71a7dd870715b3e430c4 ./artix7/ppips_clbll_l.db`](./artix7/ppips_clbll_l.db)
* [`3955d590e8ee64c843bb80f911a08781c1bac63e71b577436ae1f44195a88e22 ./artix7/ppips_clbll_r.db`](./artix7/ppips_clbll_r.db)
* [`29f175153821dc13989eb580676ff0007e108d911275a74e7ebe45e819c14eaf ./artix7/ppips_clblm_l.db`](./artix7/ppips_clblm_l.db)
@ -121,19 +119,19 @@ Results have checksums;
* [`81e0696179a33bdf8d2279a53b406911a403d50224355e9ad29eccee01a70305 ./artix7/ppips_hclk_r.db`](./artix7/ppips_hclk_r.db)
* [`be617c15d1ec311b6249791414bbd69380fe90b476353cbb2fc2a7cb06f5029d ./artix7/ppips_int_l.db`](./artix7/ppips_int_l.db)
* [`a1423859c97a82dcfb114644f50b991db4ca7e0996e6d1ae4d2c97bfdfcb723d ./artix7/ppips_int_r.db`](./artix7/ppips_int_r.db)
* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./artix7/segbits_bram_l.block_ram.db`](./artix7/segbits_bram_l.block_ram.db)
* [`b3011b6a49b05f1f0a40b499537d0f3eb208a51b87d6d97811911df50d4ad2d2 ./artix7/segbits_bram_l.db`](./artix7/segbits_bram_l.db)
* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./artix7/segbits_bram_r.block_ram.db`](./artix7/segbits_bram_r.block_ram.db)
* [`ac4e1c029ed8e623985ca2665e7aa1fae57aa2b33defb5f8cfa17d34d160e4b1 ./artix7/segbits_bram_r.db`](./artix7/segbits_bram_r.db)
* [`280eb9f102fe5fb64a657088b277d08bb0600c90507a17567bf44b544b6cf2ac ./artix7/segbits_clbll_l.db`](./artix7/segbits_clbll_l.db)
* [`28a4160e4ce09f2a3d015b913d4f0a320ff8e47088fdada9622fcdf8c4b523e6 ./artix7/segbits_clbll_r.db`](./artix7/segbits_clbll_r.db)
* [`de134d4d2a9e1e2aed74bffaea198d886d12e7e906152d58cc777db65d58e2d2 ./artix7/segbits_clblm_l.db`](./artix7/segbits_clblm_l.db)
* [`b1e17491351b2f402df2415ef0908d8ff4e84fa645180c2c9931843c479d8e45 ./artix7/segbits_clblm_r.db`](./artix7/segbits_clblm_r.db)
* [`20f7bf469951b04a56e5e140b6327470750b08960643353384b35baf85eb9117 ./artix7/segbits_hclk_l.db`](./artix7/segbits_hclk_l.db)
* [`7966925d50ebf5296f273ac64d03614ce0f452209bc0a4bde2e3d30f2fbd9a53 ./artix7/segbits_bram_l.block_ram.db`](./artix7/segbits_bram_l.block_ram.db)
* [`aaa1d706495108244ce39af259fe7a0b636f3e5e0d911e2bce23f904d8816f1a ./artix7/segbits_bram_l.db`](./artix7/segbits_bram_l.db)
* [`7b958779367cfa8ab94fc1358241bf2704f0f165eb7809653d527ecef77bb6b1 ./artix7/segbits_bram_r.block_ram.db`](./artix7/segbits_bram_r.block_ram.db)
* [`c5335d22c23e0ef7dc23d66388d9586fef598680d429f96d4308a21a345edc22 ./artix7/segbits_bram_r.db`](./artix7/segbits_bram_r.db)
* [`0cc8dc983fe854bc534c9239dd3b0ffa2dda77f9805a315f9defeaf42c255618 ./artix7/segbits_clbll_l.db`](./artix7/segbits_clbll_l.db)
* [`cd85f9175e2fc0e379c05e01c21ec21dc6bc76733e03cffe47af7fa6bc4d5c37 ./artix7/segbits_clbll_r.db`](./artix7/segbits_clbll_r.db)
* [`564092247d7162afb3ad01a8a2cf1dbe7f198cbee3be0d113afedb67ef4c96ec ./artix7/segbits_clblm_l.db`](./artix7/segbits_clblm_l.db)
* [`f15a683170fdb706c9b53af9029a5a81c7e0efbd8b45f84145f8cbddf6065d86 ./artix7/segbits_clblm_r.db`](./artix7/segbits_clblm_r.db)
* [`df496c4d335fac0c379497ff0a75ba4f5c5c25bcce79f9c7a72d5f08066310db ./artix7/segbits_hclk_l.db`](./artix7/segbits_hclk_l.db)
* [`5e22f758a04eab3185b2453c9994aa2fa48f50ca8a6b49bf82e8fc4351f23a5c ./artix7/segbits_hclk_r.db`](./artix7/segbits_hclk_r.db)
* [`90d9243f3210a3ac7feb0d5c4434d62bd74ebf5edc75b95a9eae22540d462d3f ./artix7/segbits_int_l.db`](./artix7/segbits_int_l.db)
* [`13bc58bf4a42029adf4f9b06ffd7c9436e2294bf4fdc16cdaa70505c28a2a7b7 ./artix7/segbits_int_r.db`](./artix7/segbits_int_r.db)
* [`d77b40f729b66962f0197a5e31b43860326401b6116ac36e727411319adac0f2 ./artix7/settings.sh`](./artix7/settings.sh)
* [`582158a8db52f7e08b4d0f20d4e2f9efcaa56bd836f06e1e8b0de3dbb909d698 ./artix7/segbits_int_l.db`](./artix7/segbits_int_l.db)
* [`c95a67762d97d31140eb9f251fb52d97674912633990438495bf8c37793eea06 ./artix7/segbits_int_r.db`](./artix7/segbits_int_r.db)
* [`5e7fd99c466d50e7074f812737417596ed2dd985a8f084bdb803ff06543d9b7f ./artix7/settings.sh`](./artix7/settings.sh)
* [`6a998dd55a7aa4ab33db25db7b5167d57f3d708713baf1fca394dc2940f12007 ./artix7/site_type_BSCAN.json`](./artix7/site_type_BSCAN.json)
* [`7f59ea08fa5dbf9ce84ea26f03f13cd02683fce9cdd98621e501e422bf09d165 ./artix7/site_type_BUFGCTRL.json`](./artix7/site_type_BUFGCTRL.json)
* [`2d6c78790d74503f0810356de3a765b380b319f09a41593bc8cbe8979defd1f7 ./artix7/site_type_BUFHCE.json`](./artix7/site_type_BUFHCE.json)
@ -178,8 +176,8 @@ Results have checksums;
* [`db8c88384575a7e0562692550bdba7a4089ea5fabe451bf58403d3a85af419a0 ./artix7/site_type_TIEOFF.json`](./artix7/site_type_TIEOFF.json)
* [`4d6130cb2604efae8ca5d628b95be2549083c16c639d335bdc906924e37ec28c ./artix7/site_type_USR_ACCESS.json`](./artix7/site_type_USR_ACCESS.json)
* [`dbf0ff3b27d1fac02572351765f1b17b3e950ed4e8fe95ac6bcd71012e4f7b2d ./artix7/site_type_XADC.json`](./artix7/site_type_XADC.json)
* [`2af71373b90795d9db335d93f255391c9f11abc72a1dfd96b9d964bf254290d3 ./artix7/tileconn.json`](./artix7/tileconn.json)
* [`455829274901658159f9f06f8021b34a19e8fe891991a4c3ea137a8d5646e998 ./artix7/tilegrid.json`](./artix7/tilegrid.json)
* [`6ae28ffd57cb4c4f7a731e0ea8e37173f079db2cfe275f05b526ba261db5d234 ./artix7/tileconn.json`](./artix7/tileconn.json)
* [`3dcf45da1b1f6d0b0f4867c6cabd17366a383652f09b6838e3f906a4b5d1a677 ./artix7/tilegrid.json`](./artix7/tilegrid.json)
* [`a93b4be2b2832d1a9240b892f6d8db469f3d9cf6229cc6856a197e854f4abc8a ./artix7/tile_type_BRAM_INT_INTERFACE_L.json`](./artix7/tile_type_BRAM_INT_INTERFACE_L.json)
* [`fff3e640e286158767fc484ec932d0ce7eba48c1168798c11c7779426a846004 ./artix7/tile_type_BRAM_INT_INTERFACE_R.json`](./artix7/tile_type_BRAM_INT_INTERFACE_R.json)
* [`ea83df939d85f211eebf41d40d8ee9c5b7f1d6c493c5f4b842cbf3b6d9b9b186 ./artix7/tile_type_BRAM_L.json`](./artix7/tile_type_BRAM_L.json)

3
Makefile Normal file
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@ -0,0 +1,3 @@
clean:
rm -f $$(ls */* |grep -v settings.sh)

8232
artix7/mask_bram_l.db
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File diff suppressed because it is too large Load Diff

8237
artix7/mask_bram_r.db
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File diff suppressed because it is too large Load Diff

28
artix7/mask_clbll_l.db
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@ -11,24 +11,17 @@ bit 00_09
bit 00_10
bit 00_11
bit 00_12
bit 00_13
bit 00_14
bit 00_15
bit 00_16
bit 00_17
bit 00_18
bit 00_19
bit 00_20
bit 00_21
bit 00_22
bit 00_23
bit 00_24
bit 00_25
bit 00_26
bit 00_27
bit 00_28
bit 00_29
bit 00_30
bit 00_32
bit 00_33
bit 00_34
@ -37,7 +30,6 @@ bit 00_36
bit 00_37
bit 00_38
bit 00_39
bit 00_40
bit 00_41
bit 00_42
bit 00_43
@ -46,12 +38,8 @@ bit 00_45
bit 00_46
bit 00_47
bit 00_48
bit 00_49
bit 00_50
bit 00_51
bit 00_52
bit 00_53
bit 00_54
bit 00_55
bit 00_56
bit 00_57
@ -72,23 +60,15 @@ bit 01_08
bit 01_09
bit 01_10
bit 01_11
bit 01_12
bit 01_13
bit 01_14
bit 01_15
bit 01_16
bit 01_17
bit 01_18
bit 01_19
bit 01_20
bit 01_21
bit 01_22
bit 01_23
bit 01_24
bit 01_25
bit 01_26
bit 01_27
bit 01_28
bit 01_29
bit 01_31
bit 01_32
@ -108,9 +88,7 @@ bit 01_45
bit 01_46
bit 01_47
bit 01_48
bit 01_49
bit 01_50
bit 01_51
bit 01_52
bit 01_53
bit 01_54
@ -1898,8 +1876,6 @@ bit 30_12
bit 30_13
bit 30_14
bit 30_15
bit 30_16
bit 30_17
bit 30_18
bit 30_19
bit 30_20
@ -1913,7 +1889,6 @@ bit 30_27
bit 30_28
bit 30_29
bit 30_30
bit 30_32
bit 30_33
bit 30_34
bit 30_35
@ -1927,8 +1902,6 @@ bit 30_42
bit 30_43
bit 30_44
bit 30_45
bit 30_46
bit 30_47
bit 30_48
bit 30_49
bit 30_50
@ -1975,7 +1948,6 @@ bit 31_27
bit 31_28
bit 31_29
bit 31_30
bit 31_32
bit 31_33
bit 31_34
bit 31_35

27
artix7/mask_clbll_r.db
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@ -11,24 +11,17 @@ bit 00_09
bit 00_10
bit 00_11
bit 00_12
bit 00_13
bit 00_14
bit 00_15
bit 00_16
bit 00_17
bit 00_18
bit 00_19
bit 00_20
bit 00_21
bit 00_22
bit 00_23
bit 00_24
bit 00_25
bit 00_26
bit 00_27
bit 00_28
bit 00_29
bit 00_30
bit 00_32
bit 00_33
bit 00_34
@ -37,7 +30,6 @@ bit 00_36
bit 00_37
bit 00_38
bit 00_39
bit 00_40
bit 00_41
bit 00_42
bit 00_43
@ -48,10 +40,7 @@ bit 00_47
bit 00_48
bit 00_49
bit 00_50
bit 00_51
bit 00_52
bit 00_53
bit 00_54
bit 00_55
bit 00_56
bit 00_57
@ -72,23 +61,15 @@ bit 01_08
bit 01_09
bit 01_10
bit 01_11
bit 01_12
bit 01_13
bit 01_14
bit 01_15
bit 01_16
bit 01_17
bit 01_18
bit 01_19
bit 01_20
bit 01_21
bit 01_22
bit 01_23
bit 01_24
bit 01_25
bit 01_26
bit 01_27
bit 01_28
bit 01_29
bit 01_31
bit 01_32
@ -108,9 +89,7 @@ bit 01_45
bit 01_46
bit 01_47
bit 01_48
bit 01_49
bit 01_50
bit 01_51
bit 01_52
bit 01_53
bit 01_54
@ -1898,8 +1877,6 @@ bit 30_12
bit 30_13
bit 30_14
bit 30_15
bit 30_16
bit 30_17
bit 30_18
bit 30_19
bit 30_20
@ -1913,7 +1890,6 @@ bit 30_27
bit 30_28
bit 30_29
bit 30_30
bit 30_32
bit 30_33
bit 30_34
bit 30_35
@ -1927,8 +1903,6 @@ bit 30_42
bit 30_43
bit 30_44
bit 30_45
bit 30_46
bit 30_47
bit 30_48
bit 30_49
bit 30_50
@ -1975,7 +1949,6 @@ bit 31_27
bit 31_28
bit 31_29
bit 31_30
bit 31_32
bit 31_33
bit 31_34
bit 31_35

28
artix7/mask_clblm_l.db
View File

@ -11,24 +11,17 @@ bit 00_09
bit 00_10
bit 00_11
bit 00_12
bit 00_13
bit 00_14
bit 00_15
bit 00_16
bit 00_17
bit 00_18
bit 00_19
bit 00_20
bit 00_21
bit 00_22
bit 00_23
bit 00_24
bit 00_25
bit 00_26
bit 00_27
bit 00_28
bit 00_29
bit 00_30
bit 00_32
bit 00_33
bit 00_34
@ -37,7 +30,6 @@ bit 00_36
bit 00_37
bit 00_38
bit 00_39
bit 00_40
bit 00_41
bit 00_42
bit 00_43
@ -46,12 +38,8 @@ bit 00_45
bit 00_46
bit 00_47
bit 00_48
bit 00_49
bit 00_50
bit 00_51
bit 00_52
bit 00_53
bit 00_54
bit 00_55
bit 00_56
bit 00_57
@ -72,23 +60,15 @@ bit 01_08
bit 01_09
bit 01_10
bit 01_11
bit 01_12
bit 01_13
bit 01_14
bit 01_15
bit 01_16
bit 01_17
bit 01_18
bit 01_19
bit 01_20
bit 01_21
bit 01_22
bit 01_23
bit 01_24
bit 01_25
bit 01_26
bit 01_27
bit 01_28
bit 01_29
bit 01_31
bit 01_32
@ -108,9 +88,7 @@ bit 01_45
bit 01_46
bit 01_47
bit 01_48
bit 01_49
bit 01_50
bit 01_51
bit 01_52
bit 01_53
bit 01_54
@ -1898,8 +1876,6 @@ bit 30_12
bit 30_13
bit 30_14
bit 30_15
bit 30_16
bit 30_17
bit 30_18
bit 30_19
bit 30_20
@ -1913,7 +1889,6 @@ bit 30_27
bit 30_28
bit 30_29
bit 30_30
bit 30_32
bit 30_33
bit 30_34
bit 30_35
@ -1927,8 +1902,6 @@ bit 30_42
bit 30_43
bit 30_44
bit 30_45
bit 30_46
bit 30_47
bit 30_48
bit 30_49
bit 30_50
@ -1975,7 +1948,6 @@ bit 31_27
bit 31_28
bit 31_29
bit 31_30
bit 31_32
bit 31_33
bit 31_34
bit 31_35

27
artix7/mask_clblm_r.db
View File

@ -11,24 +11,17 @@ bit 00_09
bit 00_10
bit 00_11
bit 00_12
bit 00_13
bit 00_14
bit 00_15
bit 00_16
bit 00_17
bit 00_18
bit 00_19
bit 00_20
bit 00_21
bit 00_22
bit 00_23
bit 00_24
bit 00_25
bit 00_26
bit 00_27
bit 00_28
bit 00_29
bit 00_30
bit 00_32
bit 00_33
bit 00_34
@ -37,7 +30,6 @@ bit 00_36
bit 00_37
bit 00_38
bit 00_39
bit 00_40
bit 00_41
bit 00_42
bit 00_43
@ -48,10 +40,7 @@ bit 00_47
bit 00_48
bit 00_49
bit 00_50
bit 00_51
bit 00_52
bit 00_53
bit 00_54
bit 00_55
bit 00_56
bit 00_57
@ -72,23 +61,15 @@ bit 01_08
bit 01_09
bit 01_10
bit 01_11
bit 01_12
bit 01_13
bit 01_14
bit 01_15
bit 01_16
bit 01_17
bit 01_18
bit 01_19
bit 01_20
bit 01_21
bit 01_22
bit 01_23
bit 01_24
bit 01_25
bit 01_26
bit 01_27
bit 01_28
bit 01_29
bit 01_31
bit 01_32
@ -108,9 +89,7 @@ bit 01_45
bit 01_46
bit 01_47
bit 01_48
bit 01_49
bit 01_50
bit 01_51
bit 01_52
bit 01_53
bit 01_54
@ -1898,8 +1877,6 @@ bit 30_12
bit 30_13
bit 30_14
bit 30_15
bit 30_16
bit 30_17
bit 30_18
bit 30_19
bit 30_20
@ -1913,7 +1890,6 @@ bit 30_27
bit 30_28
bit 30_29
bit 30_30
bit 30_32
bit 30_33
bit 30_34
bit 30_35
@ -1927,8 +1903,6 @@ bit 30_42
bit 30_43
bit 30_44
bit 30_45
bit 30_46
bit 30_47
bit 30_48
bit 30_49
bit 30_50
@ -1975,7 +1949,6 @@ bit 31_27
bit 31_28
bit 31_29
bit 31_30
bit 31_32
bit 31_33
bit 31_34
bit 31_35

8040
artix7/mask_dsp_l.db
View File

File diff suppressed because it is too large Load Diff

8045
artix7/mask_dsp_r.db
View File

File diff suppressed because it is too large Load Diff

2
artix7/mask_hclk_l.db
View File

@ -102,3 +102,5 @@ bit 05_28
bit 05_29
bit 05_30
bit 05_31
bit <0
bit candidates>

2
artix7/mask_hclk_r.db
View File

@ -102,3 +102,5 @@ bit 05_28
bit 05_29
bit 05_30
bit 05_31
bit <0
bit candidates>

36864
artix7/segbits_bram_l.block_ram.db
View File

File diff suppressed because it is too large Load Diff

72
artix7/segbits_bram_l.db
View File

@ -2,12 +2,12 @@ BRAM_L.RAMB18_Y0.INIT_A[0] 27_73
BRAM_L.RAMB18_Y0.INIT_A[10] 27_129
BRAM_L.RAMB18_Y0.INIT_A[11] 27_113
BRAM_L.RAMB18_Y0.INIT_A[12] 27_97
BRAM_L.RAMB18_Y0.INIT_A[1] 27_65
BRAM_L.RAMB18_Y0.INIT_A[13] 27_81
BRAM_L.RAMB18_Y0.INIT_A[14] 27_49
BRAM_L.RAMB18_Y0.INIT_A[15] 27_33
BRAM_L.RAMB18_Y0.INIT_A[16] 27_17
BRAM_L.RAMB18_Y0.INIT_A[17] 27_01
BRAM_L.RAMB18_Y0.INIT_A[1] 27_65
BRAM_L.RAMB18_Y0.INIT_A[2] 27_137
BRAM_L.RAMB18_Y0.INIT_A[3] 27_121
BRAM_L.RAMB18_Y0.INIT_A[4] 27_105
@ -20,12 +20,12 @@ BRAM_L.RAMB18_Y0.INIT_B[0] 27_79
BRAM_L.RAMB18_Y0.INIT_B[10] 27_135
BRAM_L.RAMB18_Y0.INIT_B[11] 27_119
BRAM_L.RAMB18_Y0.INIT_B[12] 27_103
BRAM_L.RAMB18_Y0.INIT_B[1] 27_71
BRAM_L.RAMB18_Y0.INIT_B[13] 27_87
BRAM_L.RAMB18_Y0.INIT_B[14] 27_55
BRAM_L.RAMB18_Y0.INIT_B[15] 27_39
BRAM_L.RAMB18_Y0.INIT_B[16] 27_23
BRAM_L.RAMB18_Y0.INIT_B[17] 27_07
BRAM_L.RAMB18_Y0.INIT_B[1] 27_71
BRAM_L.RAMB18_Y0.INIT_B[2] 27_143
BRAM_L.RAMB18_Y0.INIT_B[3] 27_127
BRAM_L.RAMB18_Y0.INIT_B[4] 27_111
@ -34,22 +34,24 @@ BRAM_L.RAMB18_Y0.INIT_B[6] 27_63
BRAM_L.RAMB18_Y0.INIT_B[7] 27_47
BRAM_L.RAMB18_Y0.INIT_B[8] 27_31
BRAM_L.RAMB18_Y0.INIT_B[9] 27_15
BRAM_L.RAMB18_Y0.READ_WIDTH_A_B0 27_35
BRAM_L.RAMB18_Y0.READ_WIDTH_A_B1 27_36
BRAM_L.RAMB18_Y0.READ_WIDTH_A_B2 27_37
BRAM_L.RAMB18_Y0.READ_WIDTH_B_B0 27_43
BRAM_L.RAMB18_Y0.READ_WIDTH_B_B1 27_44
BRAM_L.RAMB18_Y0.READ_WIDTH_B_B2 27_45
BRAM_L.RAMB18_Y0.READ_WIDTH_A_18 !27_35 !27_36 27_37
BRAM_L.RAMB18_Y0.READ_WIDTH_A_2 !27_36 !27_37 27_35
BRAM_L.RAMB18_Y0.READ_WIDTH_A_4 !27_35 !27_37 27_36
BRAM_L.RAMB18_Y0.READ_WIDTH_A_9 !27_37 27_35 27_36
BRAM_L.RAMB18_Y0.READ_WIDTH_B_18 !27_43 !27_44 27_45
BRAM_L.RAMB18_Y0.READ_WIDTH_B_2 !27_44 !27_45 27_43
BRAM_L.RAMB18_Y0.READ_WIDTH_B_4 !27_43 !27_45 27_44
BRAM_L.RAMB18_Y0.READ_WIDTH_B_9 !27_45 27_43 27_44
BRAM_L.RAMB18_Y0.SRVAL_A[0] 27_74
BRAM_L.RAMB18_Y0.SRVAL_A[10] 27_130
BRAM_L.RAMB18_Y0.SRVAL_A[11] 27_114
BRAM_L.RAMB18_Y0.SRVAL_A[12] 27_98
BRAM_L.RAMB18_Y0.SRVAL_A[1] 27_66
BRAM_L.RAMB18_Y0.SRVAL_A[13] 27_82
BRAM_L.RAMB18_Y0.SRVAL_A[14] 27_50
BRAM_L.RAMB18_Y0.SRVAL_A[15] 27_34
BRAM_L.RAMB18_Y0.SRVAL_A[16] 27_18
BRAM_L.RAMB18_Y0.SRVAL_A[17] 27_02
BRAM_L.RAMB18_Y0.SRVAL_A[1] 27_66
BRAM_L.RAMB18_Y0.SRVAL_A[2] 27_138
BRAM_L.RAMB18_Y0.SRVAL_A[3] 27_122
BRAM_L.RAMB18_Y0.SRVAL_A[4] 27_106
@ -62,12 +64,12 @@ BRAM_L.RAMB18_Y0.SRVAL_B[0] 27_78
BRAM_L.RAMB18_Y0.SRVAL_B[10] 27_134
BRAM_L.RAMB18_Y0.SRVAL_B[11] 27_118
BRAM_L.RAMB18_Y0.SRVAL_B[12] 27_102
BRAM_L.RAMB18_Y0.SRVAL_B[1] 27_70
BRAM_L.RAMB18_Y0.SRVAL_B[13] 27_86
BRAM_L.RAMB18_Y0.SRVAL_B[14] 27_54
BRAM_L.RAMB18_Y0.SRVAL_B[15] 27_38
BRAM_L.RAMB18_Y0.SRVAL_B[16] 27_22
BRAM_L.RAMB18_Y0.SRVAL_B[17] 27_06
BRAM_L.RAMB18_Y0.SRVAL_B[1] 27_70
BRAM_L.RAMB18_Y0.SRVAL_B[2] 27_142
BRAM_L.RAMB18_Y0.SRVAL_B[3] 27_126
BRAM_L.RAMB18_Y0.SRVAL_B[4] 27_110
@ -80,12 +82,14 @@ BRAM_L.RAMB18_Y0.WRITE_MODE_A_NO_CHANGE 27_64
BRAM_L.RAMB18_Y0.WRITE_MODE_A_READ_FIRST 27_56
BRAM_L.RAMB18_Y0.WRITE_MODE_B_NO_CHANGE 27_68
BRAM_L.RAMB18_Y0.WRITE_MODE_B_READ_FIRST 27_67
BRAM_L.RAMB18_Y0.WRITE_WIDTH_A_B0 27_51
BRAM_L.RAMB18_Y0.WRITE_WIDTH_A_B1 27_52
BRAM_L.RAMB18_Y0.WRITE_WIDTH_A_B2 27_53
BRAM_L.RAMB18_Y0.WRITE_WIDTH_B_B0 27_59
BRAM_L.RAMB18_Y0.WRITE_WIDTH_B_B1 27_60
BRAM_L.RAMB18_Y0.WRITE_WIDTH_B_B2 27_61
BRAM_L.RAMB18_Y0.WRITE_WIDTH_A_18 !27_51 !27_52 27_53
BRAM_L.RAMB18_Y0.WRITE_WIDTH_A_2 !27_52 !27_53 27_51
BRAM_L.RAMB18_Y0.WRITE_WIDTH_A_4 !27_51 !27_53 27_52
BRAM_L.RAMB18_Y0.WRITE_WIDTH_A_9 !27_53 27_51 27_52
BRAM_L.RAMB18_Y0.WRITE_WIDTH_B_18 !27_59 !27_60 27_61
BRAM_L.RAMB18_Y0.WRITE_WIDTH_B_2 !27_60 !27_61 27_59
BRAM_L.RAMB18_Y0.WRITE_WIDTH_B_4 !27_59 !27_61 27_60
BRAM_L.RAMB18_Y0.WRITE_WIDTH_B_9 !27_61 27_59 27_60
BRAM_L.RAMB18_Y0.ZINV_CLKARDCLK 27_107
BRAM_L.RAMB18_Y0.ZINV_CLKBWRCLK 27_109
BRAM_L.RAMB18_Y0.ZINV_ENARDEN 27_112
@ -98,12 +102,12 @@ BRAM_L.RAMB18_Y1.INIT_A[0] 27_249
BRAM_L.RAMB18_Y1.INIT_A[10] 27_305
BRAM_L.RAMB18_Y1.INIT_A[11] 27_289
BRAM_L.RAMB18_Y1.INIT_A[12] 27_273
BRAM_L.RAMB18_Y1.INIT_A[1] 27_241
BRAM_L.RAMB18_Y1.INIT_A[13] 27_257
BRAM_L.RAMB18_Y1.INIT_A[14] 27_225
BRAM_L.RAMB18_Y1.INIT_A[15] 27_209
BRAM_L.RAMB18_Y1.INIT_A[16] 27_193
BRAM_L.RAMB18_Y1.INIT_A[17] 27_177
BRAM_L.RAMB18_Y1.INIT_A[1] 27_241
BRAM_L.RAMB18_Y1.INIT_A[2] 27_313
BRAM_L.RAMB18_Y1.INIT_A[3] 27_297
BRAM_L.RAMB18_Y1.INIT_A[4] 27_281
@ -116,12 +120,12 @@ BRAM_L.RAMB18_Y1.INIT_B[0] 27_255
BRAM_L.RAMB18_Y1.INIT_B[10] 27_311
BRAM_L.RAMB18_Y1.INIT_B[11] 27_295
BRAM_L.RAMB18_Y1.INIT_B[12] 27_279
BRAM_L.RAMB18_Y1.INIT_B[1] 27_247
BRAM_L.RAMB18_Y1.INIT_B[13] 27_263
BRAM_L.RAMB18_Y1.INIT_B[14] 27_231
BRAM_L.RAMB18_Y1.INIT_B[15] 27_215
BRAM_L.RAMB18_Y1.INIT_B[16] 27_199
BRAM_L.RAMB18_Y1.INIT_B[17] 27_183
BRAM_L.RAMB18_Y1.INIT_B[1] 27_247
BRAM_L.RAMB18_Y1.INIT_B[2] 27_319
BRAM_L.RAMB18_Y1.INIT_B[3] 27_303
BRAM_L.RAMB18_Y1.INIT_B[4] 27_287
@ -130,22 +134,24 @@ BRAM_L.RAMB18_Y1.INIT_B[6] 27_239
BRAM_L.RAMB18_Y1.INIT_B[7] 27_223
BRAM_L.RAMB18_Y1.INIT_B[8] 27_207
BRAM_L.RAMB18_Y1.INIT_B[9] 27_191
BRAM_L.RAMB18_Y1.READ_WIDTH_A_B0 27_285
BRAM_L.RAMB18_Y1.READ_WIDTH_A_B1 27_284
BRAM_L.RAMB18_Y1.READ_WIDTH_A_B2 27_283
BRAM_L.RAMB18_Y1.READ_WIDTH_B_B0 27_277
BRAM_L.RAMB18_Y1.READ_WIDTH_B_B1 27_276
BRAM_L.RAMB18_Y1.READ_WIDTH_B_B2 27_275
BRAM_L.RAMB18_Y1.READ_WIDTH_A_18 !27_284 !27_285 27_283
BRAM_L.RAMB18_Y1.READ_WIDTH_A_2 !27_283 !27_284 27_285
BRAM_L.RAMB18_Y1.READ_WIDTH_A_4 !27_283 !27_285 27_284
BRAM_L.RAMB18_Y1.READ_WIDTH_A_9 !27_283 27_284 27_285
BRAM_L.RAMB18_Y1.READ_WIDTH_B_18 !27_276 !27_277 27_275
BRAM_L.RAMB18_Y1.READ_WIDTH_B_2 !27_275 !27_276 27_277
BRAM_L.RAMB18_Y1.READ_WIDTH_B_4 !27_275 !27_277 27_276
BRAM_L.RAMB18_Y1.READ_WIDTH_B_9 !27_275 27_276 27_277
BRAM_L.RAMB18_Y1.SRVAL_A[0] 27_250
BRAM_L.RAMB18_Y1.SRVAL_A[10] 27_306
BRAM_L.RAMB18_Y1.SRVAL_A[11] 27_290
BRAM_L.RAMB18_Y1.SRVAL_A[12] 27_274
BRAM_L.RAMB18_Y1.SRVAL_A[1] 27_242
BRAM_L.RAMB18_Y1.SRVAL_A[13] 27_258
BRAM_L.RAMB18_Y1.SRVAL_A[14] 27_226
BRAM_L.RAMB18_Y1.SRVAL_A[15] 27_210
BRAM_L.RAMB18_Y1.SRVAL_A[16] 27_194
BRAM_L.RAMB18_Y1.SRVAL_A[17] 27_178
BRAM_L.RAMB18_Y1.SRVAL_A[1] 27_242
BRAM_L.RAMB18_Y1.SRVAL_A[2] 27_314
BRAM_L.RAMB18_Y1.SRVAL_A[3] 27_298
BRAM_L.RAMB18_Y1.SRVAL_A[4] 27_282
@ -158,12 +164,12 @@ BRAM_L.RAMB18_Y1.SRVAL_B[0] 27_254
BRAM_L.RAMB18_Y1.SRVAL_B[10] 27_310
BRAM_L.RAMB18_Y1.SRVAL_B[11] 27_294
BRAM_L.RAMB18_Y1.SRVAL_B[12] 27_278
BRAM_L.RAMB18_Y1.SRVAL_B[1] 27_246
BRAM_L.RAMB18_Y1.SRVAL_B[13] 27_262
BRAM_L.RAMB18_Y1.SRVAL_B[14] 27_230
BRAM_L.RAMB18_Y1.SRVAL_B[15] 27_214
BRAM_L.RAMB18_Y1.SRVAL_B[16] 27_198
BRAM_L.RAMB18_Y1.SRVAL_B[17] 27_182
BRAM_L.RAMB18_Y1.SRVAL_B[1] 27_246
BRAM_L.RAMB18_Y1.SRVAL_B[2] 27_318
BRAM_L.RAMB18_Y1.SRVAL_B[3] 27_302
BRAM_L.RAMB18_Y1.SRVAL_B[4] 27_286
@ -176,12 +182,14 @@ BRAM_L.RAMB18_Y1.WRITE_MODE_A_NO_CHANGE 27_256
BRAM_L.RAMB18_Y1.WRITE_MODE_A_READ_FIRST 27_264
BRAM_L.RAMB18_Y1.WRITE_MODE_B_NO_CHANGE 27_252
BRAM_L.RAMB18_Y1.WRITE_MODE_B_READ_FIRST 27_253
BRAM_L.RAMB18_Y1.WRITE_WIDTH_A_B0 27_269
BRAM_L.RAMB18_Y1.WRITE_WIDTH_A_B1 27_268
BRAM_L.RAMB18_Y1.WRITE_WIDTH_A_B2 27_267
BRAM_L.RAMB18_Y1.WRITE_WIDTH_B_B0 27_261
BRAM_L.RAMB18_Y1.WRITE_WIDTH_B_B1 27_260
BRAM_L.RAMB18_Y1.WRITE_WIDTH_B_B2 27_259
BRAM_L.RAMB18_Y1.WRITE_WIDTH_A_18 !27_268 !27_269 27_267
BRAM_L.RAMB18_Y1.WRITE_WIDTH_A_2 !27_267 !27_268 27_269
BRAM_L.RAMB18_Y1.WRITE_WIDTH_A_4 !27_267 !27_269 27_268
BRAM_L.RAMB18_Y1.WRITE_WIDTH_A_9 !27_267 27_268 27_269
BRAM_L.RAMB18_Y1.WRITE_WIDTH_B_18 !27_260 !27_261 27_259
BRAM_L.RAMB18_Y1.WRITE_WIDTH_B_2 !27_259 !27_260 27_261
BRAM_L.RAMB18_Y1.WRITE_WIDTH_B_4 !27_259 !27_261 27_260
BRAM_L.RAMB18_Y1.WRITE_WIDTH_B_9 !27_259 27_260 27_261
BRAM_L.RAMB18_Y1.ZINV_CLKARDCLK 27_213
BRAM_L.RAMB18_Y1.ZINV_CLKBWRCLK 27_211
BRAM_L.RAMB18_Y1.ZINV_ENARDEN 27_208

36864
artix7/segbits_bram_r.block_ram.db
View File

File diff suppressed because it is too large Load Diff

72
artix7/segbits_bram_r.db
View File

@ -2,12 +2,12 @@ BRAM_R.RAMB18_Y0.INIT_A[0] 27_73
BRAM_R.RAMB18_Y0.INIT_A[10] 27_129
BRAM_R.RAMB18_Y0.INIT_A[11] 27_113
BRAM_R.RAMB18_Y0.INIT_A[12] 27_97
BRAM_R.RAMB18_Y0.INIT_A[1] 27_65
BRAM_R.RAMB18_Y0.INIT_A[13] 27_81
BRAM_R.RAMB18_Y0.INIT_A[14] 27_49
BRAM_R.RAMB18_Y0.INIT_A[15] 27_33
BRAM_R.RAMB18_Y0.INIT_A[16] 27_17
BRAM_R.RAMB18_Y0.INIT_A[17] 27_01
BRAM_R.RAMB18_Y0.INIT_A[1] 27_65
BRAM_R.RAMB18_Y0.INIT_A[2] 27_137
BRAM_R.RAMB18_Y0.INIT_A[3] 27_121
BRAM_R.RAMB18_Y0.INIT_A[4] 27_105
@ -20,12 +20,12 @@ BRAM_R.RAMB18_Y0.INIT_B[0] 27_79
BRAM_R.RAMB18_Y0.INIT_B[10] 27_135
BRAM_R.RAMB18_Y0.INIT_B[11] 27_119
BRAM_R.RAMB18_Y0.INIT_B[12] 27_103
BRAM_R.RAMB18_Y0.INIT_B[1] 27_71
BRAM_R.RAMB18_Y0.INIT_B[13] 27_87
BRAM_R.RAMB18_Y0.INIT_B[14] 27_55
BRAM_R.RAMB18_Y0.INIT_B[15] 27_39
BRAM_R.RAMB18_Y0.INIT_B[16] 27_23
BRAM_R.RAMB18_Y0.INIT_B[17] 27_07
BRAM_R.RAMB18_Y0.INIT_B[1] 27_71
BRAM_R.RAMB18_Y0.INIT_B[2] 27_143
BRAM_R.RAMB18_Y0.INIT_B[3] 27_127
BRAM_R.RAMB18_Y0.INIT_B[4] 27_111
@ -34,22 +34,24 @@ BRAM_R.RAMB18_Y0.INIT_B[6] 27_63
BRAM_R.RAMB18_Y0.INIT_B[7] 27_47
BRAM_R.RAMB18_Y0.INIT_B[8] 27_31
BRAM_R.RAMB18_Y0.INIT_B[9] 27_15
BRAM_R.RAMB18_Y0.READ_WIDTH_A_B0 27_35
BRAM_R.RAMB18_Y0.READ_WIDTH_A_B1 27_36
BRAM_R.RAMB18_Y0.READ_WIDTH_A_B2 27_37
BRAM_R.RAMB18_Y0.READ_WIDTH_B_B0 27_43
BRAM_R.RAMB18_Y0.READ_WIDTH_B_B1 27_44
BRAM_R.RAMB18_Y0.READ_WIDTH_B_B2 27_45
BRAM_R.RAMB18_Y0.READ_WIDTH_A_18 !27_35 !27_36 27_37
BRAM_R.RAMB18_Y0.READ_WIDTH_A_2 !27_36 !27_37 27_35
BRAM_R.RAMB18_Y0.READ_WIDTH_A_4 !27_35 !27_37 27_36
BRAM_R.RAMB18_Y0.READ_WIDTH_A_9 !27_37 27_35 27_36
BRAM_R.RAMB18_Y0.READ_WIDTH_B_18 !27_43 !27_44 27_45
BRAM_R.RAMB18_Y0.READ_WIDTH_B_2 !27_44 !27_45 27_43
BRAM_R.RAMB18_Y0.READ_WIDTH_B_4 !27_43 !27_45 27_44
BRAM_R.RAMB18_Y0.READ_WIDTH_B_9 !27_45 27_43 27_44
BRAM_R.RAMB18_Y0.SRVAL_A[0] 27_74
BRAM_R.RAMB18_Y0.SRVAL_A[10] 27_130
BRAM_R.RAMB18_Y0.SRVAL_A[11] 27_114
BRAM_R.RAMB18_Y0.SRVAL_A[12] 27_98
BRAM_R.RAMB18_Y0.SRVAL_A[1] 27_66
BRAM_R.RAMB18_Y0.SRVAL_A[13] 27_82
BRAM_R.RAMB18_Y0.SRVAL_A[14] 27_50
BRAM_R.RAMB18_Y0.SRVAL_A[15] 27_34
BRAM_R.RAMB18_Y0.SRVAL_A[16] 27_18
BRAM_R.RAMB18_Y0.SRVAL_A[17] 27_02
BRAM_R.RAMB18_Y0.SRVAL_A[1] 27_66
BRAM_R.RAMB18_Y0.SRVAL_A[2] 27_138
BRAM_R.RAMB18_Y0.SRVAL_A[3] 27_122
BRAM_R.RAMB18_Y0.SRVAL_A[4] 27_106
@ -62,12 +64,12 @@ BRAM_R.RAMB18_Y0.SRVAL_B[0] 27_78
BRAM_R.RAMB18_Y0.SRVAL_B[10] 27_134
BRAM_R.RAMB18_Y0.SRVAL_B[11] 27_118
BRAM_R.RAMB18_Y0.SRVAL_B[12] 27_102
BRAM_R.RAMB18_Y0.SRVAL_B[1] 27_70
BRAM_R.RAMB18_Y0.SRVAL_B[13] 27_86
BRAM_R.RAMB18_Y0.SRVAL_B[14] 27_54
BRAM_R.RAMB18_Y0.SRVAL_B[15] 27_38
BRAM_R.RAMB18_Y0.SRVAL_B[16] 27_22
BRAM_R.RAMB18_Y0.SRVAL_B[17] 27_06
BRAM_R.RAMB18_Y0.SRVAL_B[1] 27_70
BRAM_R.RAMB18_Y0.SRVAL_B[2] 27_142
BRAM_R.RAMB18_Y0.SRVAL_B[3] 27_126
BRAM_R.RAMB18_Y0.SRVAL_B[4] 27_110
@ -80,12 +82,14 @@ BRAM_R.RAMB18_Y0.WRITE_MODE_A_NO_CHANGE 27_64
BRAM_R.RAMB18_Y0.WRITE_MODE_A_READ_FIRST 27_56
BRAM_R.RAMB18_Y0.WRITE_MODE_B_NO_CHANGE 27_68
BRAM_R.RAMB18_Y0.WRITE_MODE_B_READ_FIRST 27_67
BRAM_R.RAMB18_Y0.WRITE_WIDTH_A_B0 27_51
BRAM_R.RAMB18_Y0.WRITE_WIDTH_A_B1 27_52
BRAM_R.RAMB18_Y0.WRITE_WIDTH_A_B2 27_53
BRAM_R.RAMB18_Y0.WRITE_WIDTH_B_B0 27_59
BRAM_R.RAMB18_Y0.WRITE_WIDTH_B_B1 27_60
BRAM_R.RAMB18_Y0.WRITE_WIDTH_B_B2 27_61
BRAM_R.RAMB18_Y0.WRITE_WIDTH_A_18 !27_51 !27_52 27_53
BRAM_R.RAMB18_Y0.WRITE_WIDTH_A_2 !27_52 !27_53 27_51
BRAM_R.RAMB18_Y0.WRITE_WIDTH_A_4 !27_51 !27_53 27_52
BRAM_R.RAMB18_Y0.WRITE_WIDTH_A_9 !27_53 27_51 27_52
BRAM_R.RAMB18_Y0.WRITE_WIDTH_B_18 !27_59 !27_60 27_61
BRAM_R.RAMB18_Y0.WRITE_WIDTH_B_2 !27_60 !27_61 27_59
BRAM_R.RAMB18_Y0.WRITE_WIDTH_B_4 !27_59 !27_61 27_60
BRAM_R.RAMB18_Y0.WRITE_WIDTH_B_9 !27_61 27_59 27_60
BRAM_R.RAMB18_Y0.ZINV_CLKARDCLK 27_107
BRAM_R.RAMB18_Y0.ZINV_CLKBWRCLK 27_109
BRAM_R.RAMB18_Y0.ZINV_ENARDEN 27_112
@ -98,12 +102,12 @@ BRAM_R.RAMB18_Y1.INIT_A[0] 27_249
BRAM_R.RAMB18_Y1.INIT_A[10] 27_305
BRAM_R.RAMB18_Y1.INIT_A[11] 27_289
BRAM_R.RAMB18_Y1.INIT_A[12] 27_273
BRAM_R.RAMB18_Y1.INIT_A[1] 27_241
BRAM_R.RAMB18_Y1.INIT_A[13] 27_257
BRAM_R.RAMB18_Y1.INIT_A[14] 27_225
BRAM_R.RAMB18_Y1.INIT_A[15] 27_209
BRAM_R.RAMB18_Y1.INIT_A[16] 27_193
BRAM_R.RAMB18_Y1.INIT_A[17] 27_177
BRAM_R.RAMB18_Y1.INIT_A[1] 27_241
BRAM_R.RAMB18_Y1.INIT_A[2] 27_313
BRAM_R.RAMB18_Y1.INIT_A[3] 27_297
BRAM_R.RAMB18_Y1.INIT_A[4] 27_281
@ -116,12 +120,12 @@ BRAM_R.RAMB18_Y1.INIT_B[0] 27_255
BRAM_R.RAMB18_Y1.INIT_B[10] 27_311
BRAM_R.RAMB18_Y1.INIT_B[11] 27_295
BRAM_R.RAMB18_Y1.INIT_B[12] 27_279
BRAM_R.RAMB18_Y1.INIT_B[1] 27_247
BRAM_R.RAMB18_Y1.INIT_B[13] 27_263
BRAM_R.RAMB18_Y1.INIT_B[14] 27_231
BRAM_R.RAMB18_Y1.INIT_B[15] 27_215
BRAM_R.RAMB18_Y1.INIT_B[16] 27_199
BRAM_R.RAMB18_Y1.INIT_B[17] 27_183
BRAM_R.RAMB18_Y1.INIT_B[1] 27_247
BRAM_R.RAMB18_Y1.INIT_B[2] 27_319
BRAM_R.RAMB18_Y1.INIT_B[3] 27_303
BRAM_R.RAMB18_Y1.INIT_B[4] 27_287
@ -130,22 +134,24 @@ BRAM_R.RAMB18_Y1.INIT_B[6] 27_239
BRAM_R.RAMB18_Y1.INIT_B[7] 27_223
BRAM_R.RAMB18_Y1.INIT_B[8] 27_207
BRAM_R.RAMB18_Y1.INIT_B[9] 27_191
BRAM_R.RAMB18_Y1.READ_WIDTH_A_B0 27_285
BRAM_R.RAMB18_Y1.READ_WIDTH_A_B1 27_284
BRAM_R.RAMB18_Y1.READ_WIDTH_A_B2 27_283
BRAM_R.RAMB18_Y1.READ_WIDTH_B_B0 27_277
BRAM_R.RAMB18_Y1.READ_WIDTH_B_B1 27_276
BRAM_R.RAMB18_Y1.READ_WIDTH_B_B2 27_275
BRAM_R.RAMB18_Y1.READ_WIDTH_A_18 !27_284 !27_285 27_283
BRAM_R.RAMB18_Y1.READ_WIDTH_A_2 !27_283 !27_284 27_285
BRAM_R.RAMB18_Y1.READ_WIDTH_A_4 !27_283 !27_285 27_284
BRAM_R.RAMB18_Y1.READ_WIDTH_A_9 !27_283 27_284 27_285
BRAM_R.RAMB18_Y1.READ_WIDTH_B_18 !27_276 !27_277 27_275
BRAM_R.RAMB18_Y1.READ_WIDTH_B_2 !27_275 !27_276 27_277
BRAM_R.RAMB18_Y1.READ_WIDTH_B_4 !27_275 !27_277 27_276
BRAM_R.RAMB18_Y1.READ_WIDTH_B_9 !27_275 27_276 27_277
BRAM_R.RAMB18_Y1.SRVAL_A[0] 27_250
BRAM_R.RAMB18_Y1.SRVAL_A[10] 27_306
BRAM_R.RAMB18_Y1.SRVAL_A[11] 27_290
BRAM_R.RAMB18_Y1.SRVAL_A[12] 27_274
BRAM_R.RAMB18_Y1.SRVAL_A[1] 27_242
BRAM_R.RAMB18_Y1.SRVAL_A[13] 27_258
BRAM_R.RAMB18_Y1.SRVAL_A[14] 27_226
BRAM_R.RAMB18_Y1.SRVAL_A[15] 27_210
BRAM_R.RAMB18_Y1.SRVAL_A[16] 27_194
BRAM_R.RAMB18_Y1.SRVAL_A[17] 27_178
BRAM_R.RAMB18_Y1.SRVAL_A[1] 27_242
BRAM_R.RAMB18_Y1.SRVAL_A[2] 27_314
BRAM_R.RAMB18_Y1.SRVAL_A[3] 27_298
BRAM_R.RAMB18_Y1.SRVAL_A[4] 27_282
@ -158,12 +164,12 @@ BRAM_R.RAMB18_Y1.SRVAL_B[0] 27_254
BRAM_R.RAMB18_Y1.SRVAL_B[10] 27_310
BRAM_R.RAMB18_Y1.SRVAL_B[11] 27_294
BRAM_R.RAMB18_Y1.SRVAL_B[12] 27_278
BRAM_R.RAMB18_Y1.SRVAL_B[1] 27_246
BRAM_R.RAMB18_Y1.SRVAL_B[13] 27_262
BRAM_R.RAMB18_Y1.SRVAL_B[14] 27_230
BRAM_R.RAMB18_Y1.SRVAL_B[15] 27_214
BRAM_R.RAMB18_Y1.SRVAL_B[16] 27_198
BRAM_R.RAMB18_Y1.SRVAL_B[17] 27_182
BRAM_R.RAMB18_Y1.SRVAL_B[1] 27_246
BRAM_R.RAMB18_Y1.SRVAL_B[2] 27_318
BRAM_R.RAMB18_Y1.SRVAL_B[3] 27_302
BRAM_R.RAMB18_Y1.SRVAL_B[4] 27_286
@ -176,12 +182,14 @@ BRAM_R.RAMB18_Y1.WRITE_MODE_A_NO_CHANGE 27_256
BRAM_R.RAMB18_Y1.WRITE_MODE_A_READ_FIRST 27_264
BRAM_R.RAMB18_Y1.WRITE_MODE_B_NO_CHANGE 27_252
BRAM_R.RAMB18_Y1.WRITE_MODE_B_READ_FIRST 27_253
BRAM_R.RAMB18_Y1.WRITE_WIDTH_A_B0 27_269
BRAM_R.RAMB18_Y1.WRITE_WIDTH_A_B1 27_268
BRAM_R.RAMB18_Y1.WRITE_WIDTH_A_B2 27_267
BRAM_R.RAMB18_Y1.WRITE_WIDTH_B_B0 27_261
BRAM_R.RAMB18_Y1.WRITE_WIDTH_B_B1 27_260
BRAM_R.RAMB18_Y1.WRITE_WIDTH_B_B2 27_259
BRAM_R.RAMB18_Y1.WRITE_WIDTH_A_18 !27_268 !27_269 27_267
BRAM_R.RAMB18_Y1.WRITE_WIDTH_A_2 !27_267 !27_268 27_269
BRAM_R.RAMB18_Y1.WRITE_WIDTH_A_4 !27_267 !27_269 27_268
BRAM_R.RAMB18_Y1.WRITE_WIDTH_A_9 !27_267 27_268 27_269
BRAM_R.RAMB18_Y1.WRITE_WIDTH_B_18 !27_260 !27_261 27_259
BRAM_R.RAMB18_Y1.WRITE_WIDTH_B_2 !27_259 !27_260 27_261
BRAM_R.RAMB18_Y1.WRITE_WIDTH_B_4 !27_259 !27_261 27_260
BRAM_R.RAMB18_Y1.WRITE_WIDTH_B_9 !27_259 27_260 27_261
BRAM_R.RAMB18_Y1.ZINV_CLKARDCLK 27_213
BRAM_R.RAMB18_Y1.ZINV_CLKBWRCLK 27_211
BRAM_R.RAMB18_Y1.ZINV_ENARDEN 27_208

145
artix7/segbits_clbll_l.db
View File

@ -1,16 +1,7 @@
CLBLL_L.SLICEL_X0.A5FF.MUX.A 30_09
CLBLL_L.SLICEL_X0.A5FF.MUX.B 30_10
CLBLL_L.SLICEL_X0.A5FF.ZINI 31_06
CLBLL_L.SLICEL_X0.A5FF.ZRST 01_07
CLBLL_L.SLICEL_X0.A5FFMUX.IN_A 30_09
CLBLL_L.SLICEL_X0.A5FFMUX.IN_B 30_10
CLBLL_L.SLICEL_X0.ADI1MUX.AI 00_00
CLBLL_L.SLICEL_X0.AFF.DMUX.AX !30_00 !30_02 !30_03 30_01
CLBLL_L.SLICEL_X0.AFF.DMUX.CY !30_01 !30_03 30_00 30_02
CLBLL_L.SLICEL_X0.AFF.DMUX.F7 !30_02 !30_03 30_00 30_01
CLBLL_L.SLICEL_X0.AFF.DMUX.O5 !30_01 !30_02 30_00 30_03
CLBLL_L.SLICEL_X0.AFF.DMUX.O6 !30_00 !30_01 !30_02 30_03
CLBLL_L.SLICEL_X0.AFF.DMUX.XOR !30_00 !30_01 !30_03 30_02
CLBLL_L.SLICEL_X0.AFF.ZINI 31_03
CLBLL_L.SLICEL_X0.AFF.ZRST 30_12
CLBLL_L.SLICEL_X0.AFFMUX.AX !30_00 !30_02 !30_03 30_01
@ -84,32 +75,16 @@ CLBLL_L.SLICEL_X0.ALUT.INIT[61] 34_01
CLBLL_L.SLICEL_X0.ALUT.INIT[62] 35_00
CLBLL_L.SLICEL_X0.ALUT.INIT[63] 34_00
CLBLL_L.SLICEL_X0.ALUT.RAM 31_16
CLBLL_L.SLICEL_X0.ALUT.SMALL 00_04
CLBLL_L.SLICEL_X0.ALUT.SRL 30_16
CLBLL_L.SLICEL_X0.AMUX.A5Q !30_06 !30_08 !30_11 30_07
CLBLL_L.SLICEL_X0.AMUX.CY !30_07 !30_11 30_06 30_08
CLBLL_L.SLICEL_X0.AMUX.F7 !30_08 !30_11 30_06 30_07
CLBLL_L.SLICEL_X0.AMUX.O5 !30_07 !30_08 30_06 30_11
CLBLL_L.SLICEL_X0.AMUX.O6 !30_06 !30_07 !30_08 30_11
CLBLL_L.SLICEL_X0.AMUX.XOR !30_06 !30_07 !30_11 30_08
CLBLL_L.SLICEL_X0.AOUTMUX.A5Q !30_06 !30_08 !30_11 30_07
CLBLL_L.SLICEL_X0.AOUTMUX.CY !30_07 !30_11 30_06 30_08
CLBLL_L.SLICEL_X0.AOUTMUX.F7 !30_08 !30_11 30_06 30_07
CLBLL_L.SLICEL_X0.AOUTMUX.O5 !30_07 !30_08 30_06 30_11
CLBLL_L.SLICEL_X0.AOUTMUX.O6 !30_06 !30_07 !30_08 30_11
CLBLL_L.SLICEL_X0.AOUTMUX.XOR !30_06 !30_07 !30_11 30_08
CLBLL_L.SLICEL_X0.B5FF.MUX.A 30_19
CLBLL_L.SLICEL_X0.B5FF.MUX.B 30_18
CLBLL_L.SLICEL_X0.B5FF.ZINI 31_22
CLBLL_L.SLICEL_X0.B5FF.ZRST 01_19
CLBLL_L.SLICEL_X0.B5FFMUX.IN_A 30_19
CLBLL_L.SLICEL_X0.B5FFMUX.IN_B 30_18
CLBLL_L.SLICEL_X0.BDI1MUX.BI 00_20
CLBLL_L.SLICEL_X0.BFF.DMUX.BX !30_24 !30_25 !30_27 30_26
CLBLL_L.SLICEL_X0.BFF.DMUX.CY !30_24 !30_26 30_25 30_27
CLBLL_L.SLICEL_X0.BFF.DMUX.F8 !30_24 !30_25 30_26 30_27
CLBLL_L.SLICEL_X0.BFF.DMUX.O5 !30_25 !30_26 30_24 30_27
CLBLL_L.SLICEL_X0.BFF.DMUX.O6 !30_25 !30_26 !30_27 30_24
CLBLL_L.SLICEL_X0.BFF.DMUX.XOR !30_24 !30_26 !30_27 30_25
CLBLL_L.SLICEL_X0.BFF.ZINI 31_28
CLBLL_L.SLICEL_X0.BFF.ZRST 30_30
CLBLL_L.SLICEL_X0.BFFMUX.BX !30_24 !30_25 !30_27 30_26
@ -183,38 +158,21 @@ CLBLL_L.SLICEL_X0.BLUT.INIT[61] 34_17
CLBLL_L.SLICEL_X0.BLUT.INIT[62] 35_16
CLBLL_L.SLICEL_X0.BLUT.INIT[63] 34_16
CLBLL_L.SLICEL_X0.BLUT.RAM 31_17
CLBLL_L.SLICEL_X0.BLUT.SMALL 00_24
CLBLL_L.SLICEL_X0.BLUT.SRL 30_17
CLBLL_L.SLICEL_X0.BMUX.B5Q !30_20 !30_21 !30_22 30_23
CLBLL_L.SLICEL_X0.BMUX.CY !30_20 !30_23 30_21 30_22
CLBLL_L.SLICEL_X0.BMUX.F8 !30_20 !30_21 30_22 30_23
CLBLL_L.SLICEL_X0.BMUX.O5 !30_21 !30_23 30_20 30_22
CLBLL_L.SLICEL_X0.BMUX.O6 !30_21 !30_22 !30_23 30_20
CLBLL_L.SLICEL_X0.BMUX.XOR !30_20 !30_22 !30_23 30_21
CLBLL_L.SLICEL_X0.BOUTMUX.B5Q !30_20 !30_21 !30_22 30_23
CLBLL_L.SLICEL_X0.BOUTMUX.CY !30_20 !30_23 30_21 30_22
CLBLL_L.SLICEL_X0.BOUTMUX.F8 !30_20 !30_21 30_22 30_23
CLBLL_L.SLICEL_X0.BOUTMUX.O5 !30_21 !30_23 30_20 30_22
CLBLL_L.SLICEL_X0.BOUTMUX.O6 !30_21 !30_22 !30_23 30_20
CLBLL_L.SLICEL_X0.BOUTMUX.XOR !30_20 !30_22 !30_23 30_21
CLBLL_L.SLICEL_X0.C5FF.MUX.A 31_45
CLBLL_L.SLICEL_X0.C5FF.MUX.B 30_39
CLBLL_L.SLICEL_X0.C5FF.ZINI 31_41
CLBLL_L.SLICEL_X0.C5FF.ZRST 01_47
CLBLL_L.SLICEL_X0.C5FFMUX.IN_A 31_45
CLBLL_L.SLICEL_X0.C5FFMUX.IN_B 30_39
CLBLL_L.SLICEL_X0.CARRY4.ACY0 !30_00 !30_02 !30_03 30_01 30_12 30_15 31_03
CLBLL_L.SLICEL_X0.CARRY4.ACY0 30_15
CLBLL_L.SLICEL_X0.CARRY4.BCY0 01_15
CLBLL_L.SLICEL_X0.CARRY4.CCY0 30_48
CLBLL_L.SLICEL_X0.CARRY4.DCY0 30_49
CLBLL_L.SLICEL_X0.CDI1MUX.CI 01_43
CLBLL_L.SLICEL_X0.CEUSEDMUX 01_39
CLBLL_L.SLICEL_X0.CFF.DMUX.CX !30_35 !30_37 !30_38 30_36
CLBLL_L.SLICEL_X0.CFF.DMUX.CY !30_36 !30_38 30_35 30_37
CLBLL_L.SLICEL_X0.CFF.DMUX.F7 !30_37 !30_38 30_35 30_36
CLBLL_L.SLICEL_X0.CFF.DMUX.O5 !30_36 !30_37 30_35 30_38
CLBLL_L.SLICEL_X0.CFF.DMUX.O6 !30_35 !30_36 !30_37 30_38
CLBLL_L.SLICEL_X0.CFF.DMUX.XOR !30_35 !30_36 !30_38 30_37
CLBLL_L.SLICEL_X0.CFF.ZINI 31_33
CLBLL_L.SLICEL_X0.CFF.ZRST 30_33
CLBLL_L.SLICEL_X0.CFFMUX.CX !30_35 !30_37 !30_38 30_36
@ -289,31 +247,16 @@ CLBLL_L.SLICEL_X0.CLUT.INIT[61] 34_33
CLBLL_L.SLICEL_X0.CLUT.INIT[62] 35_32
CLBLL_L.SLICEL_X0.CLUT.INIT[63] 34_32
CLBLL_L.SLICEL_X0.CLUT.RAM 31_46
CLBLL_L.SLICEL_X0.CLUT.SMALL 00_28
CLBLL_L.SLICEL_X0.CLUT.SRL 30_46
CLBLL_L.SLICEL_X0.CMUX.C5Q !30_40 !30_44 !30_45 30_43
CLBLL_L.SLICEL_X0.CMUX.CY !30_43 !30_45 30_40 30_44
CLBLL_L.SLICEL_X0.CMUX.F7 !30_44 !30_45 30_40 30_43
CLBLL_L.SLICEL_X0.CMUX.O5 !30_43 !30_44 30_40 30_45
CLBLL_L.SLICEL_X0.CMUX.O6 !30_40 !30_43 !30_44 30_45
CLBLL_L.SLICEL_X0.CMUX.XOR !30_40 !30_43 !30_45 30_44
CLBLL_L.SLICEL_X0.COUTMUX.C5Q !30_40 !30_44 !30_45 30_43
CLBLL_L.SLICEL_X0.COUTMUX.CY !30_43 !30_45 30_40 30_44
CLBLL_L.SLICEL_X0.COUTMUX.F7 !30_44 !30_45 30_40 30_43
CLBLL_L.SLICEL_X0.COUTMUX.O5 !30_43 !30_44 30_40 30_45
CLBLL_L.SLICEL_X0.COUTMUX.O6 !30_40 !30_43 !30_44 30_45
CLBLL_L.SLICEL_X0.COUTMUX.XOR !30_40 !30_43 !30_45 30_44
CLBLL_L.SLICEL_X0.D5FF.MUX.A 30_55
CLBLL_L.SLICEL_X0.D5FF.MUX.B 30_54
CLBLL_L.SLICEL_X0.D5FF.ZINI 31_51
CLBLL_L.SLICEL_X0.D5FF.ZRST 01_55
CLBLL_L.SLICEL_X0.D5FFMUX.IN_A 30_55
CLBLL_L.SLICEL_X0.D5FFMUX.IN_B !22_55 !23_55 !24_55 25_55 30_54
CLBLL_L.SLICEL_X0.D5FFMUX.IN_B 30_54
CLBLL_L.SLICEL_X0.DFF.DMUX.CY !30_59 !30_61 30_60 30_62
CLBLL_L.SLICEL_X0.DFF.DMUX.DX !30_59 !30_60 !30_62 30_61
CLBLL_L.SLICEL_X0.DFF.DMUX.O5 !30_60 !30_61 30_59 30_62
CLBLL_L.SLICEL_X0.DFF.DMUX.O6 !30_60 !30_61 !30_62 30_59
CLBLL_L.SLICEL_X0.DFF.DMUX.XOR !30_59 !30_61 !30_62 30_60
CLBLL_L.SLICEL_X0.DFF.ZINI 31_58
CLBLL_L.SLICEL_X0.DFF.ZRST 30_50
CLBLL_L.SLICEL_X0.DFFMUX.CY !30_59 !30_61 30_60 30_62
@ -388,36 +331,24 @@ CLBLL_L.SLICEL_X0.DLUT.INIT[63] 34_48
CLBLL_L.SLICEL_X0.DLUT.RAM 31_47
CLBLL_L.SLICEL_X0.DLUT.SMALL 01_59
CLBLL_L.SLICEL_X0.DLUT.SRL 30_47
CLBLL_L.SLICEL_X0.DMUX.CY !30_56 !30_57 30_51 30_52
CLBLL_L.SLICEL_X0.DMUX.D5Q !30_51 !30_52 !30_56 30_57
CLBLL_L.SLICEL_X0.DMUX.O5 !30_51 !30_57 30_52 30_56
CLBLL_L.SLICEL_X0.DMUX.O6 !30_51 !30_52 !30_57 30_56
CLBLL_L.SLICEL_X0.DMUX.XOR !30_52 !30_56 !30_57 30_51
CLBLL_L.SLICEL_X0.DOUTMUX.CY !30_56 !30_57 30_51 30_52
CLBLL_L.SLICEL_X0.DOUTMUX.D5Q !30_51 !30_52 !30_56 30_57
CLBLL_L.SLICEL_X0.DOUTMUX.O5 !30_51 !30_57 30_52 30_56
CLBLL_L.SLICEL_X0.DOUTMUX.O6 !30_51 !30_52 !30_57 30_56
CLBLL_L.SLICEL_X0.DOUTMUX.XOR !30_52 !30_56 !30_57 30_51
CLBLL_L.SLICEL_X0.FFSYNC 00_48
CLBLL_L.SLICEL_X0.LATCH 30_32
CLBLL_L.SLICEL_X0.PRECYINIT.1 00_12
CLBLL_L.SLICEL_X0.PRECYINIT.AX 30_14
CLBLL_L.SLICEL_X0.PRECYINIT.CIN 30_13
CLBLL_L.SLICEL_X0.PRECYINIT.1 !30_13 !30_14 00_12
CLBLL_L.SLICEL_X0.PRECYINIT.AX !00_12 !30_13 30_14
CLBLL_L.SLICEL_X0.PRECYINIT.CIN !00_12 !30_14 30_13
CLBLL_L.SLICEL_X0.SRUSEDMUX 01_35
CLBLL_L.SLICEL_X0.WA7USED 00_40
CLBLL_L.SLICEL_X0.WA8USED 01_27
CLBLL_L.SLICEL_X0.WEMUX.CE 01_23
CLBLL_L.SLICEL_X1.A5FF.MUX.A 31_08
CLBLL_L.SLICEL_X1.A5FF.MUX.B 31_11
CLBLL_L.SLICEL_X0.WEMUX.CE 01_23 24_62 26_32 26_36
CLBLL_L.SLICEL_X1.A5FF.ZINI 31_05
CLBLL_L.SLICEL_X1.A5FF.ZRST 01_03
CLBLL_L.SLICEL_X1.A5FFMUX.IN_A 31_08
CLBLL_L.SLICEL_X1.A5FFMUX.IN_B 31_11
CLBLL_L.SLICEL_X1.AFF.DMUX.AX !30_04 !31_00 !31_02 31_01
CLBLL_L.SLICEL_X1.AFF.DMUX.CY !30_04 !31_01 31_00 31_02
CLBLL_L.SLICEL_X1.AFF.DMUX.F7 !30_04 !31_02 31_00 31_01
CLBLL_L.SLICEL_X1.AFF.DMUX.O5 !31_01 !31_02 30_04 31_00
CLBLL_L.SLICEL_X1.AFF.DMUX.O6 !31_00 !31_01 !31_02 30_04
CLBLL_L.SLICEL_X1.AFF.DMUX.XOR !30_04 !31_00 !31_01 31_02
CLBLL_L.SLICEL_X1.AFF.ZINI 31_04
CLBLL_L.SLICEL_X1.AFF.ZRST 31_15
CLBLL_L.SLICEL_X1.AFFMUX.AX !30_04 !31_00 !31_02 31_01
@ -490,29 +421,16 @@ CLBLL_L.SLICEL_X1.ALUT.INIT[60] 29_01
CLBLL_L.SLICEL_X1.ALUT.INIT[61] 28_01
CLBLL_L.SLICEL_X1.ALUT.INIT[62] 29_00
CLBLL_L.SLICEL_X1.ALUT.INIT[63] 28_00
CLBLL_L.SLICEL_X1.AMUX.A5Q !31_07 !31_09 !31_10 30_05
CLBLL_L.SLICEL_X1.AMUX.CY !30_05 !31_09 31_07 31_10
CLBLL_L.SLICEL_X1.AMUX.F7 !31_07 !31_09 30_05 31_10
CLBLL_L.SLICEL_X1.AMUX.O5 !30_05 !31_07 31_09 31_10
CLBLL_L.SLICEL_X1.AMUX.O6 !30_05 !31_07 !31_10 31_09
CLBLL_L.SLICEL_X1.AMUX.XOR !30_05 !31_09 !31_10 31_07
CLBLL_L.SLICEL_X1.AOUTMUX.A5Q !31_07 !31_09 !31_10 30_05
CLBLL_L.SLICEL_X1.AOUTMUX.CY !30_05 !31_09 31_07 31_10
CLBLL_L.SLICEL_X1.AOUTMUX.F7 !31_07 !31_09 30_05 31_10
CLBLL_L.SLICEL_X1.AOUTMUX.O5 !30_05 !31_07 31_09 31_10
CLBLL_L.SLICEL_X1.AOUTMUX.O6 !30_05 !31_07 !31_10 31_09
CLBLL_L.SLICEL_X1.AOUTMUX.XOR !30_05 !31_09 !31_10 31_07
CLBLL_L.SLICEL_X1.B5FF.MUX.A 31_19
CLBLL_L.SLICEL_X1.B5FF.MUX.B 31_18
CLBLL_L.SLICEL_X1.B5FF.ZINI 31_23
CLBLL_L.SLICEL_X1.B5FF.ZRST 00_16
CLBLL_L.SLICEL_X1.B5FFMUX.IN_A 31_19
CLBLL_L.SLICEL_X1.B5FFMUX.IN_B 31_18
CLBLL_L.SLICEL_X1.BFF.DMUX.BX !31_24 !31_25 !31_26 31_27
CLBLL_L.SLICEL_X1.BFF.DMUX.CY !31_24 !31_27 31_25 31_26
CLBLL_L.SLICEL_X1.BFF.DMUX.F8 !31_24 !31_26 31_25 31_27
CLBLL_L.SLICEL_X1.BFF.DMUX.O5 !31_26 !31_27 31_24 31_25
CLBLL_L.SLICEL_X1.BFF.DMUX.O6 !31_25 !31_26 !31_27 31_24
CLBLL_L.SLICEL_X1.BFF.DMUX.XOR !31_24 !31_25 !31_27 31_26
CLBLL_L.SLICEL_X1.BFF.ZINI 31_29
CLBLL_L.SLICEL_X1.BFF.ZRST 31_30
CLBLL_L.SLICEL_X1.BFFMUX.BX !31_24 !31_25 !31_26 31_27
@ -585,35 +503,21 @@ CLBLL_L.SLICEL_X1.BLUT.INIT[60] 29_17
CLBLL_L.SLICEL_X1.BLUT.INIT[61] 28_17
CLBLL_L.SLICEL_X1.BLUT.INIT[62] 29_16
CLBLL_L.SLICEL_X1.BLUT.INIT[63] 28_16
CLBLL_L.SLICEL_X1.BMUX.B5Q !30_28 !31_20 !31_21 30_29
CLBLL_L.SLICEL_X1.BMUX.CY !30_29 !31_20 30_28 31_21
CLBLL_L.SLICEL_X1.BMUX.F8 !30_28 !31_20 30_29 31_21
CLBLL_L.SLICEL_X1.BMUX.O5 !30_28 !30_29 31_20 31_21
CLBLL_L.SLICEL_X1.BMUX.O6 !30_28 !30_29 !31_21 31_20
CLBLL_L.SLICEL_X1.BMUX.XOR !30_29 !31_20 !31_21 30_28
CLBLL_L.SLICEL_X1.BOUTMUX.B5Q !30_28 !31_20 !31_21 30_29
CLBLL_L.SLICEL_X1.BOUTMUX.CY !30_29 !31_20 30_28 31_21
CLBLL_L.SLICEL_X1.BOUTMUX.F8 !30_28 !31_20 30_29 31_21
CLBLL_L.SLICEL_X1.BOUTMUX.O5 !30_28 !30_29 31_20 31_21
CLBLL_L.SLICEL_X1.BOUTMUX.O6 !30_28 !30_29 !31_21 31_20
CLBLL_L.SLICEL_X1.BOUTMUX.XOR !30_29 !31_20 !31_21 30_28
CLBLL_L.SLICEL_X1.C5FF.MUX.A 31_44
CLBLL_L.SLICEL_X1.C5FF.MUX.B 31_39
CLBLL_L.SLICEL_X1.C5FF.ZINI 31_42
CLBLL_L.SLICEL_X1.C5FF.ZRST 00_44
CLBLL_L.SLICEL_X1.C5FFMUX.IN_A 31_44
CLBLL_L.SLICEL_X1.C5FFMUX.IN_B 31_39
CLBLL_L.SLICEL_X1.CARRY4.ACY0 31_14
CLBLL_L.SLICEL_X1.CARRY4.BCY0 !31_24 !31_25 !31_26 00_08 31_27 31_29 31_30
CLBLL_L.SLICEL_X1.CARRY4.ACY0 31_01 31_04 31_14 31_15
CLBLL_L.SLICEL_X1.CARRY4.BCY0 00_08
CLBLL_L.SLICEL_X1.CARRY4.CCY0 31_48
CLBLL_L.SLICEL_X1.CARRY4.DCY0 31_49
CLBLL_L.SLICEL_X1.CEUSEDMUX 00_36
CLBLL_L.SLICEL_X1.CFF.DMUX.CX !31_35 !31_36 !31_37 31_38
CLBLL_L.SLICEL_X1.CFF.DMUX.CY !31_36 !31_38 31_35 31_37
CLBLL_L.SLICEL_X1.CFF.DMUX.F7 !31_36 !31_37 31_35 31_38
CLBLL_L.SLICEL_X1.CFF.DMUX.O5 !31_37 !31_38 31_35 31_36
CLBLL_L.SLICEL_X1.CFF.DMUX.O6 !31_35 !31_37 !31_38 31_36
CLBLL_L.SLICEL_X1.CFF.DMUX.XOR !31_35 !31_36 !31_38 31_37
CLBLL_L.SLICEL_X1.CFF.ZINI 31_34
CLBLL_L.SLICEL_X1.CFF.ZRST 30_34
CLBLL_L.SLICEL_X1.CFFMUX.CX !31_35 !31_36 !31_37 31_38
@ -687,29 +591,16 @@ CLBLL_L.SLICEL_X1.CLUT.INIT[60] 29_33
CLBLL_L.SLICEL_X1.CLUT.INIT[61] 28_33
CLBLL_L.SLICEL_X1.CLUT.INIT[62] 29_32
CLBLL_L.SLICEL_X1.CLUT.INIT[63] 28_32
CLBLL_L.SLICEL_X1.CMUX.C5Q !30_42 !31_40 !31_43 30_41
CLBLL_L.SLICEL_X1.CMUX.CY !30_41 !31_43 30_42 31_40
CLBLL_L.SLICEL_X1.CMUX.F7 !30_42 !31_43 30_41 31_40
CLBLL_L.SLICEL_X1.CMUX.O5 !30_41 !30_42 31_40 31_43
CLBLL_L.SLICEL_X1.CMUX.O6 !30_41 !30_42 !31_40 31_43
CLBLL_L.SLICEL_X1.CMUX.XOR !30_41 !31_40 !31_43 30_42
CLBLL_L.SLICEL_X1.COUTMUX.C5Q !30_42 !31_40 !31_43 30_41
CLBLL_L.SLICEL_X1.COUTMUX.CY !30_41 !31_43 30_42 31_40
CLBLL_L.SLICEL_X1.COUTMUX.F7 !30_42 !31_43 30_41 31_40
CLBLL_L.SLICEL_X1.COUTMUX.O5 !30_41 !30_42 31_40 31_43
CLBLL_L.SLICEL_X1.COUTMUX.O6 !30_41 !30_42 !31_40 31_43
CLBLL_L.SLICEL_X1.COUTMUX.XOR !30_41 !31_40 !31_43 30_42
CLBLL_L.SLICEL_X1.D5FF.MUX.A 31_55
CLBLL_L.SLICEL_X1.D5FF.MUX.B 31_54
CLBLL_L.SLICEL_X1.D5FF.ZINI 31_52
CLBLL_L.SLICEL_X1.D5FF.ZRST 00_56
CLBLL_L.SLICEL_X1.D5FFMUX.IN_A 31_55
CLBLL_L.SLICEL_X1.D5FFMUX.IN_B !22_63 !23_63 !24_63 25_63 31_54
CLBLL_L.SLICEL_X1.D5FFMUX.IN_B 31_54
CLBLL_L.SLICEL_X1.DFF.DMUX.CY !31_60 !31_61 30_58 31_62
CLBLL_L.SLICEL_X1.DFF.DMUX.DX !30_58 !31_60 !31_62 31_61
CLBLL_L.SLICEL_X1.DFF.DMUX.O5 !31_61 !31_62 30_58 31_60
CLBLL_L.SLICEL_X1.DFF.DMUX.O6 !30_58 !31_61 !31_62 31_60
CLBLL_L.SLICEL_X1.DFF.DMUX.XOR !30_58 !31_60 !31_61 31_62
CLBLL_L.SLICEL_X1.DFF.ZINI 31_59
CLBLL_L.SLICEL_X1.DFF.ZRST 31_50
CLBLL_L.SLICEL_X1.DFFMUX.CY !31_60 !31_61 30_58 31_62
@ -781,18 +672,14 @@ CLBLL_L.SLICEL_X1.DLUT.INIT[60] 29_49
CLBLL_L.SLICEL_X1.DLUT.INIT[61] 28_49
CLBLL_L.SLICEL_X1.DLUT.INIT[62] 29_48
CLBLL_L.SLICEL_X1.DLUT.INIT[63] 28_48
CLBLL_L.SLICEL_X1.DMUX.CY !31_53 !31_56 30_53 31_57
CLBLL_L.SLICEL_X1.DMUX.D5Q !30_53 !31_56 !31_57 31_53
CLBLL_L.SLICEL_X1.DMUX.O5 !30_53 !31_53 31_56 31_57
CLBLL_L.SLICEL_X1.DMUX.O6 !30_53 !31_53 !31_57 31_56
CLBLL_L.SLICEL_X1.DMUX.XOR !31_53 !31_56 !31_57 30_53
CLBLL_L.SLICEL_X1.DOUTMUX.CY !31_53 !31_56 30_53 31_57
CLBLL_L.SLICEL_X1.DOUTMUX.D5Q !30_53 !31_56 !31_57 31_53
CLBLL_L.SLICEL_X1.DOUTMUX.O5 !30_53 !31_53 31_56 31_57
CLBLL_L.SLICEL_X1.DOUTMUX.O6 !30_53 !31_53 !31_57 31_56
CLBLL_L.SLICEL_X1.DOUTMUX.XOR !31_53 !31_56 !31_57 30_53
CLBLL_L.SLICEL_X1.FFSYNC 01_31
CLBLL_L.SLICEL_X1.LATCH 31_32
CLBLL_L.SLICEL_X1.PRECYINIT.1 01_11
CLBLL_L.SLICEL_X1.PRECYINIT.AX 31_13
CLBLL_L.SLICEL_X1.PRECYINIT.CIN 31_12
CLBLL_L.SLICEL_X1.PRECYINIT.1 !31_12 !31_13 01_11
CLBLL_L.SLICEL_X1.PRECYINIT.AX !01_11 !31_12 31_13
CLBLL_L.SLICEL_X1.PRECYINIT.CIN !01_11 !31_13 31_12
CLBLL_L.SLICEL_X1.SRUSEDMUX 00_32

145
artix7/segbits_clbll_r.db
View File

@ -1,16 +1,7 @@
CLBLL_R.SLICEL_X0.A5FF.MUX.A 30_09
CLBLL_R.SLICEL_X0.A5FF.MUX.B 30_10
CLBLL_R.SLICEL_X0.A5FF.ZINI 31_06
CLBLL_R.SLICEL_X0.A5FF.ZRST 01_07
CLBLL_R.SLICEL_X0.A5FFMUX.IN_A 30_09
CLBLL_R.SLICEL_X0.A5FFMUX.IN_B 30_10
CLBLL_R.SLICEL_X0.ADI1MUX.AI 00_00
CLBLL_R.SLICEL_X0.AFF.DMUX.AX !30_00 !30_02 !30_03 30_01
CLBLL_R.SLICEL_X0.AFF.DMUX.CY !30_01 !30_03 30_00 30_02
CLBLL_R.SLICEL_X0.AFF.DMUX.F7 !30_02 !30_03 30_00 30_01
CLBLL_R.SLICEL_X0.AFF.DMUX.O5 !30_01 !30_02 30_00 30_03
CLBLL_R.SLICEL_X0.AFF.DMUX.O6 !30_00 !30_01 !30_02 30_03
CLBLL_R.SLICEL_X0.AFF.DMUX.XOR !30_00 !30_01 !30_03 30_02
CLBLL_R.SLICEL_X0.AFF.ZINI 31_03
CLBLL_R.SLICEL_X0.AFF.ZRST 30_12
CLBLL_R.SLICEL_X0.AFFMUX.AX !30_00 !30_02 !30_03 30_01
@ -84,32 +75,16 @@ CLBLL_R.SLICEL_X0.ALUT.INIT[61] 34_01
CLBLL_R.SLICEL_X0.ALUT.INIT[62] 35_00
CLBLL_R.SLICEL_X0.ALUT.INIT[63] 34_00
CLBLL_R.SLICEL_X0.ALUT.RAM 31_16
CLBLL_R.SLICEL_X0.ALUT.SMALL 00_04
CLBLL_R.SLICEL_X0.ALUT.SRL 30_16
CLBLL_R.SLICEL_X0.AMUX.A5Q !30_06 !30_08 !30_11 30_07
CLBLL_R.SLICEL_X0.AMUX.CY !30_07 !30_11 30_06 30_08
CLBLL_R.SLICEL_X0.AMUX.F7 !30_08 !30_11 30_06 30_07
CLBLL_R.SLICEL_X0.AMUX.O5 !30_07 !30_08 30_06 30_11
CLBLL_R.SLICEL_X0.AMUX.O6 !30_06 !30_07 !30_08 30_11
CLBLL_R.SLICEL_X0.AMUX.XOR !30_06 !30_07 !30_11 30_08
CLBLL_R.SLICEL_X0.AOUTMUX.A5Q !30_06 !30_08 !30_11 30_07
CLBLL_R.SLICEL_X0.AOUTMUX.CY !30_07 !30_11 30_06 30_08
CLBLL_R.SLICEL_X0.AOUTMUX.F7 !30_08 !30_11 30_06 30_07
CLBLL_R.SLICEL_X0.AOUTMUX.O5 !30_07 !30_08 30_06 30_11
CLBLL_R.SLICEL_X0.AOUTMUX.O6 !30_06 !30_07 !30_08 30_11
CLBLL_R.SLICEL_X0.AOUTMUX.XOR !30_06 !30_07 !30_11 30_08
CLBLL_R.SLICEL_X0.B5FF.MUX.A 30_19
CLBLL_R.SLICEL_X0.B5FF.MUX.B 30_18
CLBLL_R.SLICEL_X0.B5FF.ZINI 31_22
CLBLL_R.SLICEL_X0.B5FF.ZRST 01_19
CLBLL_R.SLICEL_X0.B5FFMUX.IN_A 30_19
CLBLL_R.SLICEL_X0.B5FFMUX.IN_B 30_18
CLBLL_R.SLICEL_X0.BDI1MUX.BI 00_20
CLBLL_R.SLICEL_X0.BFF.DMUX.BX !30_24 !30_25 !30_27 30_26
CLBLL_R.SLICEL_X0.BFF.DMUX.CY !30_24 !30_26 30_25 30_27
CLBLL_R.SLICEL_X0.BFF.DMUX.F8 !30_24 !30_25 30_26 30_27
CLBLL_R.SLICEL_X0.BFF.DMUX.O5 !30_25 !30_26 30_24 30_27
CLBLL_R.SLICEL_X0.BFF.DMUX.O6 !30_25 !30_26 !30_27 30_24
CLBLL_R.SLICEL_X0.BFF.DMUX.XOR !30_24 !30_26 !30_27 30_25
CLBLL_R.SLICEL_X0.BFF.ZINI 31_28
CLBLL_R.SLICEL_X0.BFF.ZRST 30_30
CLBLL_R.SLICEL_X0.BFFMUX.BX !30_24 !30_25 !30_27 30_26
@ -183,38 +158,21 @@ CLBLL_R.SLICEL_X0.BLUT.INIT[61] 34_17
CLBLL_R.SLICEL_X0.BLUT.INIT[62] 35_16
CLBLL_R.SLICEL_X0.BLUT.INIT[63] 34_16
CLBLL_R.SLICEL_X0.BLUT.RAM 31_17
CLBLL_R.SLICEL_X0.BLUT.SMALL 00_24
CLBLL_R.SLICEL_X0.BLUT.SRL 30_17
CLBLL_R.SLICEL_X0.BMUX.B5Q !30_20 !30_21 !30_22 30_23
CLBLL_R.SLICEL_X0.BMUX.CY !30_20 !30_23 30_21 30_22
CLBLL_R.SLICEL_X0.BMUX.F8 !30_20 !30_21 30_22 30_23
CLBLL_R.SLICEL_X0.BMUX.O5 !30_21 !30_23 30_20 30_22
CLBLL_R.SLICEL_X0.BMUX.O6 !30_21 !30_22 !30_23 30_20
CLBLL_R.SLICEL_X0.BMUX.XOR !30_20 !30_22 !30_23 30_21
CLBLL_R.SLICEL_X0.BOUTMUX.B5Q !30_20 !30_21 !30_22 30_23
CLBLL_R.SLICEL_X0.BOUTMUX.CY !30_20 !30_23 30_21 30_22
CLBLL_R.SLICEL_X0.BOUTMUX.F8 !30_20 !30_21 30_22 30_23
CLBLL_R.SLICEL_X0.BOUTMUX.O5 !30_21 !30_23 30_20 30_22
CLBLL_R.SLICEL_X0.BOUTMUX.O6 !30_21 !30_22 !30_23 30_20
CLBLL_R.SLICEL_X0.BOUTMUX.XOR !30_20 !30_22 !30_23 30_21
CLBLL_R.SLICEL_X0.C5FF.MUX.A 31_45
CLBLL_R.SLICEL_X0.C5FF.MUX.B 30_39
CLBLL_R.SLICEL_X0.C5FF.ZINI 31_41
CLBLL_R.SLICEL_X0.C5FF.ZRST 01_47
CLBLL_R.SLICEL_X0.C5FFMUX.IN_A 31_45
CLBLL_R.SLICEL_X0.C5FFMUX.IN_B 30_39
CLBLL_R.SLICEL_X0.CARRY4.ACY0 !30_00 !30_02 !30_03 30_01 30_12 30_15 31_03
CLBLL_R.SLICEL_X0.CARRY4.ACY0 30_15
CLBLL_R.SLICEL_X0.CARRY4.BCY0 01_15
CLBLL_R.SLICEL_X0.CARRY4.CCY0 30_48
CLBLL_R.SLICEL_X0.CARRY4.DCY0 30_49
CLBLL_R.SLICEL_X0.CDI1MUX.CI 01_43
CLBLL_R.SLICEL_X0.CEUSEDMUX 01_39
CLBLL_R.SLICEL_X0.CFF.DMUX.CX !30_35 !30_37 !30_38 30_36
CLBLL_R.SLICEL_X0.CFF.DMUX.CY !30_36 !30_38 30_35 30_37
CLBLL_R.SLICEL_X0.CFF.DMUX.F7 !30_37 !30_38 30_35 30_36
CLBLL_R.SLICEL_X0.CFF.DMUX.O5 !30_36 !30_37 30_35 30_38
CLBLL_R.SLICEL_X0.CFF.DMUX.O6 !30_35 !30_36 !30_37 30_38
CLBLL_R.SLICEL_X0.CFF.DMUX.XOR !30_35 !30_36 !30_38 30_37
CLBLL_R.SLICEL_X0.CFF.ZINI 31_33
CLBLL_R.SLICEL_X0.CFF.ZRST 30_33
CLBLL_R.SLICEL_X0.CFFMUX.CX !30_35 !30_37 !30_38 30_36
@ -289,31 +247,16 @@ CLBLL_R.SLICEL_X0.CLUT.INIT[61] 34_33
CLBLL_R.SLICEL_X0.CLUT.INIT[62] 35_32
CLBLL_R.SLICEL_X0.CLUT.INIT[63] 34_32
CLBLL_R.SLICEL_X0.CLUT.RAM 31_46
CLBLL_R.SLICEL_X0.CLUT.SMALL 00_28
CLBLL_R.SLICEL_X0.CLUT.SRL 30_46
CLBLL_R.SLICEL_X0.CMUX.C5Q !30_40 !30_44 !30_45 30_43
CLBLL_R.SLICEL_X0.CMUX.CY !30_43 !30_45 30_40 30_44
CLBLL_R.SLICEL_X0.CMUX.F7 !30_44 !30_45 30_40 30_43
CLBLL_R.SLICEL_X0.CMUX.O5 !30_43 !30_44 30_40 30_45
CLBLL_R.SLICEL_X0.CMUX.O6 !30_40 !30_43 !30_44 30_45
CLBLL_R.SLICEL_X0.CMUX.XOR !30_40 !30_43 !30_45 30_44
CLBLL_R.SLICEL_X0.COUTMUX.C5Q !30_40 !30_44 !30_45 30_43
CLBLL_R.SLICEL_X0.COUTMUX.CY !30_43 !30_45 30_40 30_44
CLBLL_R.SLICEL_X0.COUTMUX.F7 !30_44 !30_45 30_40 30_43
CLBLL_R.SLICEL_X0.COUTMUX.O5 !30_43 !30_44 30_40 30_45
CLBLL_R.SLICEL_X0.COUTMUX.O6 !30_40 !30_43 !30_44 30_45
CLBLL_R.SLICEL_X0.COUTMUX.XOR !30_40 !30_43 !30_45 30_44
CLBLL_R.SLICEL_X0.D5FF.MUX.A 30_55
CLBLL_R.SLICEL_X0.D5FF.MUX.B 30_54
CLBLL_R.SLICEL_X0.D5FF.ZINI 31_51
CLBLL_R.SLICEL_X0.D5FF.ZRST 01_55
CLBLL_R.SLICEL_X0.D5FFMUX.IN_A 30_55
CLBLL_R.SLICEL_X0.D5FFMUX.IN_B !22_55 !23_55 !24_55 25_55 30_54
CLBLL_R.SLICEL_X0.D5FFMUX.IN_B 30_54
CLBLL_R.SLICEL_X0.DFF.DMUX.CY !30_59 !30_61 30_60 30_62
CLBLL_R.SLICEL_X0.DFF.DMUX.DX !30_59 !30_60 !30_62 30_61
CLBLL_R.SLICEL_X0.DFF.DMUX.O5 !30_60 !30_61 30_59 30_62
CLBLL_R.SLICEL_X0.DFF.DMUX.O6 !30_60 !30_61 !30_62 30_59
CLBLL_R.SLICEL_X0.DFF.DMUX.XOR !30_59 !30_61 !30_62 30_60
CLBLL_R.SLICEL_X0.DFF.ZINI 31_58
CLBLL_R.SLICEL_X0.DFF.ZRST 30_50
CLBLL_R.SLICEL_X0.DFFMUX.CY !30_59 !30_61 30_60 30_62
@ -388,36 +331,24 @@ CLBLL_R.SLICEL_X0.DLUT.INIT[63] 34_48
CLBLL_R.SLICEL_X0.DLUT.RAM 31_47
CLBLL_R.SLICEL_X0.DLUT.SMALL 01_59
CLBLL_R.SLICEL_X0.DLUT.SRL 30_47
CLBLL_R.SLICEL_X0.DMUX.CY !30_56 !30_57 30_51 30_52
CLBLL_R.SLICEL_X0.DMUX.D5Q !30_51 !30_52 !30_56 30_57
CLBLL_R.SLICEL_X0.DMUX.O5 !30_51 !30_57 30_52 30_56
CLBLL_R.SLICEL_X0.DMUX.O6 !30_51 !30_52 !30_57 30_56
CLBLL_R.SLICEL_X0.DMUX.XOR !30_52 !30_56 !30_57 30_51
CLBLL_R.SLICEL_X0.DOUTMUX.CY !30_56 !30_57 30_51 30_52
CLBLL_R.SLICEL_X0.DOUTMUX.D5Q !30_51 !30_52 !30_56 30_57
CLBLL_R.SLICEL_X0.DOUTMUX.O5 !30_51 !30_57 30_52 30_56
CLBLL_R.SLICEL_X0.DOUTMUX.O6 !30_51 !30_52 !30_57 30_56
CLBLL_R.SLICEL_X0.DOUTMUX.XOR !30_52 !30_56 !30_57 30_51
CLBLL_R.SLICEL_X0.FFSYNC 00_48
CLBLL_R.SLICEL_X0.LATCH 30_32
CLBLL_R.SLICEL_X0.PRECYINIT.1 00_12
CLBLL_R.SLICEL_X0.PRECYINIT.AX 30_14
CLBLL_R.SLICEL_X0.PRECYINIT.CIN 30_13
CLBLL_R.SLICEL_X0.PRECYINIT.1 !30_13 !30_14 00_12
CLBLL_R.SLICEL_X0.PRECYINIT.AX !00_12 !30_13 30_14
CLBLL_R.SLICEL_X0.PRECYINIT.CIN !00_12 !30_14 30_13
CLBLL_R.SLICEL_X0.SRUSEDMUX 01_35
CLBLL_R.SLICEL_X0.WA7USED 00_40
CLBLL_R.SLICEL_X0.WA8USED 01_27
CLBLL_R.SLICEL_X0.WEMUX.CE 01_23
CLBLL_R.SLICEL_X1.A5FF.MUX.A 31_08
CLBLL_R.SLICEL_X1.A5FF.MUX.B 31_11
CLBLL_R.SLICEL_X0.WEMUX.CE 01_23 24_62 26_32 26_36
CLBLL_R.SLICEL_X1.A5FF.ZINI 31_05
CLBLL_R.SLICEL_X1.A5FF.ZRST 01_03
CLBLL_R.SLICEL_X1.A5FFMUX.IN_A 31_08
CLBLL_R.SLICEL_X1.A5FFMUX.IN_B 31_11
CLBLL_R.SLICEL_X1.AFF.DMUX.AX !30_04 !31_00 !31_02 31_01
CLBLL_R.SLICEL_X1.AFF.DMUX.CY !30_04 !31_01 31_00 31_02
CLBLL_R.SLICEL_X1.AFF.DMUX.F7 !30_04 !31_02 31_00 31_01
CLBLL_R.SLICEL_X1.AFF.DMUX.O5 !31_01 !31_02 30_04 31_00
CLBLL_R.SLICEL_X1.AFF.DMUX.O6 !31_00 !31_01 !31_02 30_04
CLBLL_R.SLICEL_X1.AFF.DMUX.XOR !30_04 !31_00 !31_01 31_02
CLBLL_R.SLICEL_X1.AFF.ZINI 31_04
CLBLL_R.SLICEL_X1.AFF.ZRST 31_15
CLBLL_R.SLICEL_X1.AFFMUX.AX !30_04 !31_00 !31_02 31_01
@ -490,29 +421,16 @@ CLBLL_R.SLICEL_X1.ALUT.INIT[60] 29_01
CLBLL_R.SLICEL_X1.ALUT.INIT[61] 28_01
CLBLL_R.SLICEL_X1.ALUT.INIT[62] 29_00
CLBLL_R.SLICEL_X1.ALUT.INIT[63] 28_00
CLBLL_R.SLICEL_X1.AMUX.A5Q !31_07 !31_09 !31_10 30_05
CLBLL_R.SLICEL_X1.AMUX.CY !30_05 !31_09 31_07 31_10
CLBLL_R.SLICEL_X1.AMUX.F7 !31_07 !31_09 30_05 31_10
CLBLL_R.SLICEL_X1.AMUX.O5 !30_05 !31_07 31_09 31_10
CLBLL_R.SLICEL_X1.AMUX.O6 !30_05 !31_07 !31_10 31_09
CLBLL_R.SLICEL_X1.AMUX.XOR !30_05 !31_09 !31_10 31_07
CLBLL_R.SLICEL_X1.AOUTMUX.A5Q !31_07 !31_09 !31_10 30_05
CLBLL_R.SLICEL_X1.AOUTMUX.CY !30_05 !31_09 31_07 31_10
CLBLL_R.SLICEL_X1.AOUTMUX.F7 !31_07 !31_09 30_05 31_10
CLBLL_R.SLICEL_X1.AOUTMUX.O5 !30_05 !31_07 31_09 31_10
CLBLL_R.SLICEL_X1.AOUTMUX.O6 !30_05 !31_07 !31_10 31_09
CLBLL_R.SLICEL_X1.AOUTMUX.XOR !30_05 !31_09 !31_10 31_07
CLBLL_R.SLICEL_X1.B5FF.MUX.A 31_19
CLBLL_R.SLICEL_X1.B5FF.MUX.B 31_18
CLBLL_R.SLICEL_X1.B5FF.ZINI 31_23
CLBLL_R.SLICEL_X1.B5FF.ZRST 00_16
CLBLL_R.SLICEL_X1.B5FFMUX.IN_A 31_19
CLBLL_R.SLICEL_X1.B5FFMUX.IN_B 31_18
CLBLL_R.SLICEL_X1.BFF.DMUX.BX !31_24 !31_25 !31_26 31_27
CLBLL_R.SLICEL_X1.BFF.DMUX.CY !31_24 !31_27 31_25 31_26
CLBLL_R.SLICEL_X1.BFF.DMUX.F8 !31_24 !31_26 31_25 31_27
CLBLL_R.SLICEL_X1.BFF.DMUX.O5 !31_26 !31_27 31_24 31_25
CLBLL_R.SLICEL_X1.BFF.DMUX.O6 !31_25 !31_26 !31_27 31_24
CLBLL_R.SLICEL_X1.BFF.DMUX.XOR !31_24 !31_25 !31_27 31_26
CLBLL_R.SLICEL_X1.BFF.ZINI 31_29
CLBLL_R.SLICEL_X1.BFF.ZRST 31_30
CLBLL_R.SLICEL_X1.BFFMUX.BX !31_24 !31_25 !31_26 31_27
@ -585,35 +503,21 @@ CLBLL_R.SLICEL_X1.BLUT.INIT[60] 29_17
CLBLL_R.SLICEL_X1.BLUT.INIT[61] 28_17
CLBLL_R.SLICEL_X1.BLUT.INIT[62] 29_16
CLBLL_R.SLICEL_X1.BLUT.INIT[63] 28_16
CLBLL_R.SLICEL_X1.BMUX.B5Q !30_28 !31_20 !31_21 30_29
CLBLL_R.SLICEL_X1.BMUX.CY !30_29 !31_20 30_28 31_21
CLBLL_R.SLICEL_X1.BMUX.F8 !30_28 !31_20 30_29 31_21
CLBLL_R.SLICEL_X1.BMUX.O5 !30_28 !30_29 31_20 31_21
CLBLL_R.SLICEL_X1.BMUX.O6 !30_28 !30_29 !31_21 31_20
CLBLL_R.SLICEL_X1.BMUX.XOR !30_29 !31_20 !31_21 30_28
CLBLL_R.SLICEL_X1.BOUTMUX.B5Q !30_28 !31_20 !31_21 30_29
CLBLL_R.SLICEL_X1.BOUTMUX.CY !30_29 !31_20 30_28 31_21
CLBLL_R.SLICEL_X1.BOUTMUX.F8 !30_28 !31_20 30_29 31_21
CLBLL_R.SLICEL_X1.BOUTMUX.O5 !30_28 !30_29 31_20 31_21
CLBLL_R.SLICEL_X1.BOUTMUX.O6 !30_28 !30_29 !31_21 31_20
CLBLL_R.SLICEL_X1.BOUTMUX.XOR !30_29 !31_20 !31_21 30_28
CLBLL_R.SLICEL_X1.C5FF.MUX.A 31_44
CLBLL_R.SLICEL_X1.C5FF.MUX.B 31_39
CLBLL_R.SLICEL_X1.C5FF.ZINI 31_42
CLBLL_R.SLICEL_X1.C5FF.ZRST 00_44
CLBLL_R.SLICEL_X1.C5FFMUX.IN_A 31_44
CLBLL_R.SLICEL_X1.C5FFMUX.IN_B 31_39
CLBLL_R.SLICEL_X1.CARRY4.ACY0 31_14
CLBLL_R.SLICEL_X1.CARRY4.BCY0 !31_24 !31_25 !31_26 00_08 31_27 31_29 31_30
CLBLL_R.SLICEL_X1.CARRY4.ACY0 31_01 31_04 31_14 31_15
CLBLL_R.SLICEL_X1.CARRY4.BCY0 00_08
CLBLL_R.SLICEL_X1.CARRY4.CCY0 31_48
CLBLL_R.SLICEL_X1.CARRY4.DCY0 31_49
CLBLL_R.SLICEL_X1.CEUSEDMUX 00_36
CLBLL_R.SLICEL_X1.CFF.DMUX.CX !31_35 !31_36 !31_37 31_38
CLBLL_R.SLICEL_X1.CFF.DMUX.CY !31_36 !31_38 31_35 31_37
CLBLL_R.SLICEL_X1.CFF.DMUX.F7 !31_36 !31_37 31_35 31_38
CLBLL_R.SLICEL_X1.CFF.DMUX.O5 !31_37 !31_38 31_35 31_36
CLBLL_R.SLICEL_X1.CFF.DMUX.O6 !31_35 !31_37 !31_38 31_36
CLBLL_R.SLICEL_X1.CFF.DMUX.XOR !31_35 !31_36 !31_38 31_37
CLBLL_R.SLICEL_X1.CFF.ZINI 31_34
CLBLL_R.SLICEL_X1.CFF.ZRST 30_34
CLBLL_R.SLICEL_X1.CFFMUX.CX !31_35 !31_36 !31_37 31_38
@ -687,29 +591,16 @@ CLBLL_R.SLICEL_X1.CLUT.INIT[60] 29_33
CLBLL_R.SLICEL_X1.CLUT.INIT[61] 28_33
CLBLL_R.SLICEL_X1.CLUT.INIT[62] 29_32
CLBLL_R.SLICEL_X1.CLUT.INIT[63] 28_32
CLBLL_R.SLICEL_X1.CMUX.C5Q !30_42 !31_40 !31_43 30_41
CLBLL_R.SLICEL_X1.CMUX.CY !30_41 !31_43 30_42 31_40
CLBLL_R.SLICEL_X1.CMUX.F7 !30_42 !31_43 30_41 31_40
CLBLL_R.SLICEL_X1.CMUX.O5 !30_41 !30_42 31_40 31_43
CLBLL_R.SLICEL_X1.CMUX.O6 !30_41 !30_42 !31_40 31_43
CLBLL_R.SLICEL_X1.CMUX.XOR !30_41 !31_40 !31_43 30_42
CLBLL_R.SLICEL_X1.COUTMUX.C5Q !30_42 !31_40 !31_43 30_41
CLBLL_R.SLICEL_X1.COUTMUX.CY !30_41 !31_43 30_42 31_40
CLBLL_R.SLICEL_X1.COUTMUX.F7 !30_42 !31_43 30_41 31_40
CLBLL_R.SLICEL_X1.COUTMUX.O5 !30_41 !30_42 31_40 31_43
CLBLL_R.SLICEL_X1.COUTMUX.O6 !30_41 !30_42 !31_40 31_43
CLBLL_R.SLICEL_X1.COUTMUX.XOR !30_41 !31_40 !31_43 30_42
CLBLL_R.SLICEL_X1.D5FF.MUX.A 31_55
CLBLL_R.SLICEL_X1.D5FF.MUX.B 31_54
CLBLL_R.SLICEL_X1.D5FF.ZINI 31_52
CLBLL_R.SLICEL_X1.D5FF.ZRST 00_56
CLBLL_R.SLICEL_X1.D5FFMUX.IN_A 31_55
CLBLL_R.SLICEL_X1.D5FFMUX.IN_B !22_63 !23_63 !24_63 25_63 31_54
CLBLL_R.SLICEL_X1.D5FFMUX.IN_B 31_54
CLBLL_R.SLICEL_X1.DFF.DMUX.CY !31_60 !31_61 30_58 31_62
CLBLL_R.SLICEL_X1.DFF.DMUX.DX !30_58 !31_60 !31_62 31_61
CLBLL_R.SLICEL_X1.DFF.DMUX.O5 !31_61 !31_62 30_58 31_60
CLBLL_R.SLICEL_X1.DFF.DMUX.O6 !30_58 !31_61 !31_62 31_60
CLBLL_R.SLICEL_X1.DFF.DMUX.XOR !30_58 !31_60 !31_61 31_62
CLBLL_R.SLICEL_X1.DFF.ZINI 31_59
CLBLL_R.SLICEL_X1.DFF.ZRST 31_50
CLBLL_R.SLICEL_X1.DFFMUX.CY !31_60 !31_61 30_58 31_62
@ -781,18 +672,14 @@ CLBLL_R.SLICEL_X1.DLUT.INIT[60] 29_49
CLBLL_R.SLICEL_X1.DLUT.INIT[61] 28_49
CLBLL_R.SLICEL_X1.DLUT.INIT[62] 29_48
CLBLL_R.SLICEL_X1.DLUT.INIT[63] 28_48
CLBLL_R.SLICEL_X1.DMUX.CY !31_53 !31_56 30_53 31_57
CLBLL_R.SLICEL_X1.DMUX.D5Q !30_53 !31_56 !31_57 31_53
CLBLL_R.SLICEL_X1.DMUX.O5 !30_53 !31_53 31_56 31_57
CLBLL_R.SLICEL_X1.DMUX.O6 !30_53 !31_53 !31_57 31_56
CLBLL_R.SLICEL_X1.DMUX.XOR !31_53 !31_56 !31_57 30_53
CLBLL_R.SLICEL_X1.DOUTMUX.CY !31_53 !31_56 30_53 31_57
CLBLL_R.SLICEL_X1.DOUTMUX.D5Q !30_53 !31_56 !31_57 31_53
CLBLL_R.SLICEL_X1.DOUTMUX.O5 !30_53 !31_53 31_56 31_57
CLBLL_R.SLICEL_X1.DOUTMUX.O6 !30_53 !31_53 !31_57 31_56
CLBLL_R.SLICEL_X1.DOUTMUX.XOR !31_53 !31_56 !31_57 30_53
CLBLL_R.SLICEL_X1.FFSYNC 01_31
CLBLL_R.SLICEL_X1.LATCH 31_32
CLBLL_R.SLICEL_X1.PRECYINIT.1 01_11
CLBLL_R.SLICEL_X1.PRECYINIT.AX 31_13
CLBLL_R.SLICEL_X1.PRECYINIT.CIN 31_12
CLBLL_R.SLICEL_X1.PRECYINIT.1 !31_12 !31_13 01_11
CLBLL_R.SLICEL_X1.PRECYINIT.AX !01_11 !31_12 31_13
CLBLL_R.SLICEL_X1.PRECYINIT.CIN !01_11 !31_13 31_12
CLBLL_R.SLICEL_X1.SRUSEDMUX 00_32

145
artix7/segbits_clblm_l.db
View File

@ -1,15 +1,7 @@
CLBLM_L.SLICEL_X1.A5FF.MUX.A 31_08
CLBLM_L.SLICEL_X1.A5FF.MUX.B 31_11
CLBLM_L.SLICEL_X1.A5FF.ZINI 31_05
CLBLM_L.SLICEL_X1.A5FF.ZRST 01_03
CLBLM_L.SLICEL_X1.A5FFMUX.IN_A 31_08
CLBLM_L.SLICEL_X1.A5FFMUX.IN_B 31_11
CLBLM_L.SLICEL_X1.AFF.DMUX.AX !30_04 !31_00 !31_02 31_01
CLBLM_L.SLICEL_X1.AFF.DMUX.CY !30_04 !31_01 31_00 31_02
CLBLM_L.SLICEL_X1.AFF.DMUX.F7 !30_04 !31_02 31_00 31_01
CLBLM_L.SLICEL_X1.AFF.DMUX.O5 !31_01 !31_02 30_04 31_00
CLBLM_L.SLICEL_X1.AFF.DMUX.O6 !31_00 !31_01 !31_02 30_04
CLBLM_L.SLICEL_X1.AFF.DMUX.XOR !30_04 !31_00 !31_01 31_02
CLBLM_L.SLICEL_X1.AFF.ZINI 31_04
CLBLM_L.SLICEL_X1.AFF.ZRST 31_15
CLBLM_L.SLICEL_X1.AFFMUX.AX !30_04 !31_00 !31_02 31_01
@ -82,29 +74,16 @@ CLBLM_L.SLICEL_X1.ALUT.INIT[60] 29_01
CLBLM_L.SLICEL_X1.ALUT.INIT[61] 28_01
CLBLM_L.SLICEL_X1.ALUT.INIT[62] 29_00
CLBLM_L.SLICEL_X1.ALUT.INIT[63] 28_00
CLBLM_L.SLICEL_X1.AMUX.A5Q !31_07 !31_09 !31_10 30_05
CLBLM_L.SLICEL_X1.AMUX.CY !30_05 !31_09 31_07 31_10
CLBLM_L.SLICEL_X1.AMUX.F7 !31_07 !31_09 30_05 31_10
CLBLM_L.SLICEL_X1.AMUX.O5 !30_05 !31_07 31_09 31_10
CLBLM_L.SLICEL_X1.AMUX.O6 !30_05 !31_07 !31_10 31_09
CLBLM_L.SLICEL_X1.AMUX.XOR !30_05 !31_09 !31_10 31_07
CLBLM_L.SLICEL_X1.AOUTMUX.A5Q !31_07 !31_09 !31_10 30_05
CLBLM_L.SLICEL_X1.AOUTMUX.CY !30_05 !31_09 31_07 31_10
CLBLM_L.SLICEL_X1.AOUTMUX.F7 !31_07 !31_09 30_05 31_10
CLBLM_L.SLICEL_X1.AOUTMUX.O5 !30_05 !31_07 31_09 31_10
CLBLM_L.SLICEL_X1.AOUTMUX.O6 !30_05 !31_07 !31_10 31_09
CLBLM_L.SLICEL_X1.AOUTMUX.XOR !30_05 !31_09 !31_10 31_07
CLBLM_L.SLICEL_X1.B5FF.MUX.A 31_19
CLBLM_L.SLICEL_X1.B5FF.MUX.B 31_18
CLBLM_L.SLICEL_X1.B5FF.ZINI 31_23
CLBLM_L.SLICEL_X1.B5FF.ZRST 00_16
CLBLM_L.SLICEL_X1.B5FFMUX.IN_A 31_19
CLBLM_L.SLICEL_X1.B5FFMUX.IN_B 31_18
CLBLM_L.SLICEL_X1.BFF.DMUX.BX !31_24 !31_25 !31_26 31_27
CLBLM_L.SLICEL_X1.BFF.DMUX.CY !31_24 !31_27 31_25 31_26
CLBLM_L.SLICEL_X1.BFF.DMUX.F8 !31_24 !31_26 31_25 31_27
CLBLM_L.SLICEL_X1.BFF.DMUX.O5 !31_26 !31_27 31_24 31_25
CLBLM_L.SLICEL_X1.BFF.DMUX.O6 !31_25 !31_26 !31_27 31_24
CLBLM_L.SLICEL_X1.BFF.DMUX.XOR !31_24 !31_25 !31_27 31_26
CLBLM_L.SLICEL_X1.BFF.ZINI 31_29
CLBLM_L.SLICEL_X1.BFF.ZRST 31_30
CLBLM_L.SLICEL_X1.BFFMUX.BX !31_24 !31_25 !31_26 31_27
@ -177,35 +156,21 @@ CLBLM_L.SLICEL_X1.BLUT.INIT[60] 29_17
CLBLM_L.SLICEL_X1.BLUT.INIT[61] 28_17
CLBLM_L.SLICEL_X1.BLUT.INIT[62] 29_16
CLBLM_L.SLICEL_X1.BLUT.INIT[63] 28_16
CLBLM_L.SLICEL_X1.BMUX.B5Q !30_28 !31_20 !31_21 30_29
CLBLM_L.SLICEL_X1.BMUX.CY !30_29 !31_20 30_28 31_21
CLBLM_L.SLICEL_X1.BMUX.F8 !30_28 !31_20 30_29 31_21
CLBLM_L.SLICEL_X1.BMUX.O5 !30_28 !30_29 31_20 31_21
CLBLM_L.SLICEL_X1.BMUX.O6 !30_28 !30_29 !31_21 31_20
CLBLM_L.SLICEL_X1.BMUX.XOR !30_29 !31_20 !31_21 30_28
CLBLM_L.SLICEL_X1.BOUTMUX.B5Q !30_28 !31_20 !31_21 30_29
CLBLM_L.SLICEL_X1.BOUTMUX.CY !30_29 !31_20 30_28 31_21
CLBLM_L.SLICEL_X1.BOUTMUX.F8 !30_28 !31_20 30_29 31_21
CLBLM_L.SLICEL_X1.BOUTMUX.O5 !30_28 !30_29 31_20 31_21
CLBLM_L.SLICEL_X1.BOUTMUX.O6 !30_28 !30_29 !31_21 31_20
CLBLM_L.SLICEL_X1.BOUTMUX.XOR !30_29 !31_20 !31_21 30_28
CLBLM_L.SLICEL_X1.C5FF.MUX.A 31_44
CLBLM_L.SLICEL_X1.C5FF.MUX.B 31_39
CLBLM_L.SLICEL_X1.C5FF.ZINI 31_42
CLBLM_L.SLICEL_X1.C5FF.ZRST 00_44
CLBLM_L.SLICEL_X1.C5FFMUX.IN_A 31_44
CLBLM_L.SLICEL_X1.C5FFMUX.IN_B 31_39
CLBLM_L.SLICEL_X1.CARRY4.ACY0 31_14
CLBLM_L.SLICEL_X1.CARRY4.BCY0 !31_24 !31_25 !31_26 00_08 31_27 31_29 31_30
CLBLM_L.SLICEL_X1.CARRY4.ACY0 31_01 31_04 31_14 31_15
CLBLM_L.SLICEL_X1.CARRY4.BCY0 00_08
CLBLM_L.SLICEL_X1.CARRY4.CCY0 31_48
CLBLM_L.SLICEL_X1.CARRY4.DCY0 31_49
CLBLM_L.SLICEL_X1.CEUSEDMUX 00_36
CLBLM_L.SLICEL_X1.CFF.DMUX.CX !31_35 !31_36 !31_37 31_38
CLBLM_L.SLICEL_X1.CFF.DMUX.CY !31_36 !31_38 31_35 31_37
CLBLM_L.SLICEL_X1.CFF.DMUX.F7 !31_36 !31_37 31_35 31_38
CLBLM_L.SLICEL_X1.CFF.DMUX.O5 !31_37 !31_38 31_35 31_36
CLBLM_L.SLICEL_X1.CFF.DMUX.O6 !31_35 !31_37 !31_38 31_36
CLBLM_L.SLICEL_X1.CFF.DMUX.XOR !31_35 !31_36 !31_38 31_37
CLBLM_L.SLICEL_X1.CFF.ZINI 31_34
CLBLM_L.SLICEL_X1.CFF.ZRST 30_34
CLBLM_L.SLICEL_X1.CFFMUX.CX !31_35 !31_36 !31_37 31_38
@ -279,29 +244,16 @@ CLBLM_L.SLICEL_X1.CLUT.INIT[60] 29_33
CLBLM_L.SLICEL_X1.CLUT.INIT[61] 28_33
CLBLM_L.SLICEL_X1.CLUT.INIT[62] 29_32
CLBLM_L.SLICEL_X1.CLUT.INIT[63] 28_32
CLBLM_L.SLICEL_X1.CMUX.C5Q !30_42 !31_40 !31_43 30_41
CLBLM_L.SLICEL_X1.CMUX.CY !30_41 !31_43 30_42 31_40
CLBLM_L.SLICEL_X1.CMUX.F7 !30_42 !31_43 30_41 31_40
CLBLM_L.SLICEL_X1.CMUX.O5 !30_41 !30_42 31_40 31_43
CLBLM_L.SLICEL_X1.CMUX.O6 !30_41 !30_42 !31_40 31_43
CLBLM_L.SLICEL_X1.CMUX.XOR !30_41 !31_40 !31_43 30_42
CLBLM_L.SLICEL_X1.COUTMUX.C5Q !30_42 !31_40 !31_43 30_41
CLBLM_L.SLICEL_X1.COUTMUX.CY !30_41 !31_43 30_42 31_40
CLBLM_L.SLICEL_X1.COUTMUX.F7 !30_42 !31_43 30_41 31_40
CLBLM_L.SLICEL_X1.COUTMUX.O5 !30_41 !30_42 31_40 31_43
CLBLM_L.SLICEL_X1.COUTMUX.O6 !30_41 !30_42 !31_40 31_43
CLBLM_L.SLICEL_X1.COUTMUX.XOR !30_41 !31_40 !31_43 30_42
CLBLM_L.SLICEL_X1.D5FF.MUX.A 31_55
CLBLM_L.SLICEL_X1.D5FF.MUX.B 31_54
CLBLM_L.SLICEL_X1.D5FF.ZINI 31_52
CLBLM_L.SLICEL_X1.D5FF.ZRST 00_56
CLBLM_L.SLICEL_X1.D5FFMUX.IN_A 31_55
CLBLM_L.SLICEL_X1.D5FFMUX.IN_B !22_63 !23_63 !24_63 25_63 31_54
CLBLM_L.SLICEL_X1.D5FFMUX.IN_B 31_54
CLBLM_L.SLICEL_X1.DFF.DMUX.CY !31_60 !31_61 30_58 31_62
CLBLM_L.SLICEL_X1.DFF.DMUX.DX !30_58 !31_60 !31_62 31_61
CLBLM_L.SLICEL_X1.DFF.DMUX.O5 !31_61 !31_62 30_58 31_60
CLBLM_L.SLICEL_X1.DFF.DMUX.O6 !30_58 !31_61 !31_62 31_60
CLBLM_L.SLICEL_X1.DFF.DMUX.XOR !30_58 !31_60 !31_61 31_62
CLBLM_L.SLICEL_X1.DFF.ZINI 31_59
CLBLM_L.SLICEL_X1.DFF.ZRST 31_50
CLBLM_L.SLICEL_X1.DFFMUX.CY !31_60 !31_61 30_58 31_62
@ -373,34 +325,21 @@ CLBLM_L.SLICEL_X1.DLUT.INIT[60] 29_49
CLBLM_L.SLICEL_X1.DLUT.INIT[61] 28_49
CLBLM_L.SLICEL_X1.DLUT.INIT[62] 29_48
CLBLM_L.SLICEL_X1.DLUT.INIT[63] 28_48
CLBLM_L.SLICEL_X1.DMUX.CY !31_53 !31_56 30_53 31_57
CLBLM_L.SLICEL_X1.DMUX.D5Q !30_53 !31_56 !31_57 31_53
CLBLM_L.SLICEL_X1.DMUX.O5 !30_53 !31_53 31_56 31_57
CLBLM_L.SLICEL_X1.DMUX.O6 !30_53 !31_53 !31_57 31_56
CLBLM_L.SLICEL_X1.DMUX.XOR !31_53 !31_56 !31_57 30_53
CLBLM_L.SLICEL_X1.DOUTMUX.CY !31_53 !31_56 30_53 31_57
CLBLM_L.SLICEL_X1.DOUTMUX.D5Q !30_53 !31_56 !31_57 31_53
CLBLM_L.SLICEL_X1.DOUTMUX.O5 !30_53 !31_53 31_56 31_57
CLBLM_L.SLICEL_X1.DOUTMUX.O6 !30_53 !31_53 !31_57 31_56
CLBLM_L.SLICEL_X1.DOUTMUX.XOR !31_53 !31_56 !31_57 30_53
CLBLM_L.SLICEL_X1.FFSYNC 01_31
CLBLM_L.SLICEL_X1.LATCH 31_32
CLBLM_L.SLICEL_X1.PRECYINIT.1 01_11
CLBLM_L.SLICEL_X1.PRECYINIT.AX 31_13
CLBLM_L.SLICEL_X1.PRECYINIT.CIN 31_12
CLBLM_L.SLICEL_X1.PRECYINIT.1 !31_12 !31_13 01_11
CLBLM_L.SLICEL_X1.PRECYINIT.AX !01_11 !31_12 31_13
CLBLM_L.SLICEL_X1.PRECYINIT.CIN !01_11 !31_13 31_12
CLBLM_L.SLICEL_X1.SRUSEDMUX 00_32
CLBLM_L.SLICEM_X0.A5FF.MUX.A 30_09
CLBLM_L.SLICEM_X0.A5FF.MUX.B 30_10
CLBLM_L.SLICEM_X0.A5FF.ZINI 31_06
CLBLM_L.SLICEM_X0.A5FF.ZRST 01_07
CLBLM_L.SLICEM_X0.A5FFMUX.IN_A 30_09
CLBLM_L.SLICEM_X0.A5FFMUX.IN_B 30_10
CLBLM_L.SLICEM_X0.ADI1MUX.AI 00_00
CLBLM_L.SLICEM_X0.AFF.DMUX.AX !30_00 !30_02 !30_03 30_01
CLBLM_L.SLICEM_X0.AFF.DMUX.CY !30_01 !30_03 30_00 30_02
CLBLM_L.SLICEM_X0.AFF.DMUX.F7 !30_02 !30_03 30_00 30_01
CLBLM_L.SLICEM_X0.AFF.DMUX.O5 !30_01 !30_02 30_00 30_03
CLBLM_L.SLICEM_X0.AFF.DMUX.O6 !30_00 !30_01 !30_02 30_03
CLBLM_L.SLICEM_X0.AFF.DMUX.XOR !30_00 !30_01 !30_03 30_02
CLBLM_L.SLICEM_X0.AFF.ZINI 31_03
CLBLM_L.SLICEM_X0.AFF.ZRST 30_12
CLBLM_L.SLICEM_X0.AFFMUX.AX !30_00 !30_02 !30_03 30_01
@ -475,32 +414,16 @@ CLBLM_L.SLICEM_X0.ALUT.INIT[61] 33_01
CLBLM_L.SLICEM_X0.ALUT.INIT[62] 32_00
CLBLM_L.SLICEM_X0.ALUT.INIT[63] 33_00
CLBLM_L.SLICEM_X0.ALUT.RAM 31_16
CLBLM_L.SLICEM_X0.ALUT.SMALL 00_04
CLBLM_L.SLICEM_X0.ALUT.SRL 30_16
CLBLM_L.SLICEM_X0.AMUX.A5Q !30_06 !30_08 !30_11 30_07
CLBLM_L.SLICEM_X0.AMUX.CY !30_07 !30_11 30_06 30_08
CLBLM_L.SLICEM_X0.AMUX.F7 !30_08 !30_11 30_06 30_07
CLBLM_L.SLICEM_X0.AMUX.O5 !30_07 !30_08 30_06 30_11
CLBLM_L.SLICEM_X0.AMUX.O6 !30_06 !30_07 !30_08 30_11
CLBLM_L.SLICEM_X0.AMUX.XOR !30_06 !30_07 !30_11 30_08
CLBLM_L.SLICEM_X0.AOUTMUX.A5Q !30_06 !30_08 !30_11 30_07
CLBLM_L.SLICEM_X0.AOUTMUX.CY !30_07 !30_11 30_06 30_08
CLBLM_L.SLICEM_X0.AOUTMUX.F7 !30_08 !30_11 30_06 30_07
CLBLM_L.SLICEM_X0.AOUTMUX.O5 !30_07 !30_08 30_06 30_11
CLBLM_L.SLICEM_X0.AOUTMUX.O6 !30_06 !30_07 !30_08 30_11
CLBLM_L.SLICEM_X0.AOUTMUX.XOR !30_06 !30_07 !30_11 30_08
CLBLM_L.SLICEM_X0.B5FF.MUX.A 30_19
CLBLM_L.SLICEM_X0.B5FF.MUX.B 30_18
CLBLM_L.SLICEM_X0.B5FF.ZINI 31_22
CLBLM_L.SLICEM_X0.B5FF.ZRST 01_19
CLBLM_L.SLICEM_X0.B5FFMUX.IN_A 30_19
CLBLM_L.SLICEM_X0.B5FFMUX.IN_B 30_18
CLBLM_L.SLICEM_X0.BDI1MUX.BI 00_20
CLBLM_L.SLICEM_X0.BFF.DMUX.BX !30_24 !30_25 !30_27 30_26
CLBLM_L.SLICEM_X0.BFF.DMUX.CY !30_24 !30_26 30_25 30_27
CLBLM_L.SLICEM_X0.BFF.DMUX.F8 !30_24 !30_25 30_26 30_27
CLBLM_L.SLICEM_X0.BFF.DMUX.O5 !30_25 !30_26 30_24 30_27
CLBLM_L.SLICEM_X0.BFF.DMUX.O6 !30_25 !30_26 !30_27 30_24
CLBLM_L.SLICEM_X0.BFF.DMUX.XOR !30_24 !30_26 !30_27 30_25
CLBLM_L.SLICEM_X0.BFF.ZINI 31_28
CLBLM_L.SLICEM_X0.BFF.ZRST 30_30
CLBLM_L.SLICEM_X0.BFFMUX.BX !30_24 !30_25 !30_27 30_26
@ -575,38 +498,21 @@ CLBLM_L.SLICEM_X0.BLUT.INIT[61] 33_17
CLBLM_L.SLICEM_X0.BLUT.INIT[62] 32_16
CLBLM_L.SLICEM_X0.BLUT.INIT[63] 33_16
CLBLM_L.SLICEM_X0.BLUT.RAM 31_17
CLBLM_L.SLICEM_X0.BLUT.SMALL 00_24
CLBLM_L.SLICEM_X0.BLUT.SRL 30_17
CLBLM_L.SLICEM_X0.BMUX.B5Q !30_20 !30_21 !30_22 30_23
CLBLM_L.SLICEM_X0.BMUX.CY !30_20 !30_23 30_21 30_22
CLBLM_L.SLICEM_X0.BMUX.F8 !30_20 !30_21 30_22 30_23
CLBLM_L.SLICEM_X0.BMUX.O5 !30_21 !30_23 30_20 30_22
CLBLM_L.SLICEM_X0.BMUX.O6 !30_21 !30_22 !30_23 30_20
CLBLM_L.SLICEM_X0.BMUX.XOR !30_20 !30_22 !30_23 30_21
CLBLM_L.SLICEM_X0.BOUTMUX.B5Q !30_20 !30_21 !30_22 30_23
CLBLM_L.SLICEM_X0.BOUTMUX.CY !30_20 !30_23 30_21 30_22
CLBLM_L.SLICEM_X0.BOUTMUX.F8 !30_20 !30_21 30_22 30_23
CLBLM_L.SLICEM_X0.BOUTMUX.O5 !30_21 !30_23 30_20 30_22
CLBLM_L.SLICEM_X0.BOUTMUX.O6 !30_21 !30_22 !30_23 30_20
CLBLM_L.SLICEM_X0.BOUTMUX.XOR !30_20 !30_22 !30_23 30_21
CLBLM_L.SLICEM_X0.C5FF.MUX.A 31_45
CLBLM_L.SLICEM_X0.C5FF.MUX.B 30_39
CLBLM_L.SLICEM_X0.C5FF.ZINI 31_41
CLBLM_L.SLICEM_X0.C5FF.ZRST 01_47
CLBLM_L.SLICEM_X0.C5FFMUX.IN_A 31_45
CLBLM_L.SLICEM_X0.C5FFMUX.IN_B 30_39
CLBLM_L.SLICEM_X0.CARRY4.ACY0 !30_00 !30_02 !30_03 30_01 30_12 30_15 31_03
CLBLM_L.SLICEM_X0.CARRY4.ACY0 30_15
CLBLM_L.SLICEM_X0.CARRY4.BCY0 01_15
CLBLM_L.SLICEM_X0.CARRY4.CCY0 30_48
CLBLM_L.SLICEM_X0.CARRY4.DCY0 30_49
CLBLM_L.SLICEM_X0.CDI1MUX.CI 01_43
CLBLM_L.SLICEM_X0.CEUSEDMUX 01_39
CLBLM_L.SLICEM_X0.CFF.DMUX.CX !30_35 !30_37 !30_38 30_36
CLBLM_L.SLICEM_X0.CFF.DMUX.CY !30_36 !30_38 30_35 30_37
CLBLM_L.SLICEM_X0.CFF.DMUX.F7 !30_37 !30_38 30_35 30_36
CLBLM_L.SLICEM_X0.CFF.DMUX.O5 !30_36 !30_37 30_35 30_38
CLBLM_L.SLICEM_X0.CFF.DMUX.O6 !30_35 !30_36 !30_37 30_38
CLBLM_L.SLICEM_X0.CFF.DMUX.XOR !30_35 !30_36 !30_38 30_37
CLBLM_L.SLICEM_X0.CFF.ZINI 31_33
CLBLM_L.SLICEM_X0.CFF.ZRST 30_33
CLBLM_L.SLICEM_X0.CFFMUX.CX !30_35 !30_37 !30_38 30_36
@ -682,31 +588,16 @@ CLBLM_L.SLICEM_X0.CLUT.INIT[61] 33_33
CLBLM_L.SLICEM_X0.CLUT.INIT[62] 32_32
CLBLM_L.SLICEM_X0.CLUT.INIT[63] 33_32
CLBLM_L.SLICEM_X0.CLUT.RAM 31_46
CLBLM_L.SLICEM_X0.CLUT.SMALL 00_28
CLBLM_L.SLICEM_X0.CLUT.SRL 30_46
CLBLM_L.SLICEM_X0.CMUX.C5Q !30_40 !30_44 !30_45 30_43
CLBLM_L.SLICEM_X0.CMUX.CY !30_43 !30_45 30_40 30_44
CLBLM_L.SLICEM_X0.CMUX.F7 !30_44 !30_45 30_40 30_43
CLBLM_L.SLICEM_X0.CMUX.O5 !30_43 !30_44 30_40 30_45
CLBLM_L.SLICEM_X0.CMUX.O6 !30_40 !30_43 !30_44 30_45
CLBLM_L.SLICEM_X0.CMUX.XOR !30_40 !30_43 !30_45 30_44
CLBLM_L.SLICEM_X0.COUTMUX.C5Q !30_40 !30_44 !30_45 30_43
CLBLM_L.SLICEM_X0.COUTMUX.CY !30_43 !30_45 30_40 30_44
CLBLM_L.SLICEM_X0.COUTMUX.F7 !30_44 !30_45 30_40 30_43
CLBLM_L.SLICEM_X0.COUTMUX.O5 !30_43 !30_44 30_40 30_45
CLBLM_L.SLICEM_X0.COUTMUX.O6 !30_40 !30_43 !30_44 30_45
CLBLM_L.SLICEM_X0.COUTMUX.XOR !30_40 !30_43 !30_45 30_44
CLBLM_L.SLICEM_X0.D5FF.MUX.A 30_55
CLBLM_L.SLICEM_X0.D5FF.MUX.B 30_54
CLBLM_L.SLICEM_X0.D5FF.ZINI 31_51
CLBLM_L.SLICEM_X0.D5FF.ZRST 01_55
CLBLM_L.SLICEM_X0.D5FFMUX.IN_A 30_55
CLBLM_L.SLICEM_X0.D5FFMUX.IN_B !22_55 !23_55 !24_55 25_55 30_54
CLBLM_L.SLICEM_X0.D5FFMUX.IN_B 30_54
CLBLM_L.SLICEM_X0.DFF.DMUX.CY !30_59 !30_61 30_60 30_62
CLBLM_L.SLICEM_X0.DFF.DMUX.DX !30_59 !30_60 !30_62 30_61
CLBLM_L.SLICEM_X0.DFF.DMUX.O5 !30_60 !30_61 30_59 30_62
CLBLM_L.SLICEM_X0.DFF.DMUX.O6 !30_60 !30_61 !30_62 30_59
CLBLM_L.SLICEM_X0.DFF.DMUX.XOR !30_59 !30_61 !30_62 30_60
CLBLM_L.SLICEM_X0.DFF.ZINI 31_58
CLBLM_L.SLICEM_X0.DFF.ZRST 30_50
CLBLM_L.SLICEM_X0.DFFMUX.CY !30_59 !30_61 30_60 30_62
@ -781,21 +672,17 @@ CLBLM_L.SLICEM_X0.DLUT.INIT[63] 33_48
CLBLM_L.SLICEM_X0.DLUT.RAM 31_47
CLBLM_L.SLICEM_X0.DLUT.SMALL 01_59
CLBLM_L.SLICEM_X0.DLUT.SRL 30_47
CLBLM_L.SLICEM_X0.DMUX.CY !30_56 !30_57 30_51 30_52
CLBLM_L.SLICEM_X0.DMUX.D5Q !30_51 !30_52 !30_56 30_57
CLBLM_L.SLICEM_X0.DMUX.O5 !30_51 !30_57 30_52 30_56
CLBLM_L.SLICEM_X0.DMUX.O6 !30_51 !30_52 !30_57 30_56
CLBLM_L.SLICEM_X0.DMUX.XOR !30_52 !30_56 !30_57 30_51
CLBLM_L.SLICEM_X0.DOUTMUX.CY !30_56 !30_57 30_51 30_52
CLBLM_L.SLICEM_X0.DOUTMUX.D5Q !30_51 !30_52 !30_56 30_57
CLBLM_L.SLICEM_X0.DOUTMUX.O5 !30_51 !30_57 30_52 30_56
CLBLM_L.SLICEM_X0.DOUTMUX.O6 !30_51 !30_52 !30_57 30_56
CLBLM_L.SLICEM_X0.DOUTMUX.XOR !30_52 !30_56 !30_57 30_51
CLBLM_L.SLICEM_X0.FFSYNC 00_48
CLBLM_L.SLICEM_X0.LATCH 30_32
CLBLM_L.SLICEM_X0.PRECYINIT.1 00_12
CLBLM_L.SLICEM_X0.PRECYINIT.AX 30_14
CLBLM_L.SLICEM_X0.PRECYINIT.CIN 30_13
CLBLM_L.SLICEM_X0.PRECYINIT.1 !30_13 !30_14 00_12
CLBLM_L.SLICEM_X0.PRECYINIT.AX !00_12 !30_13 30_14
CLBLM_L.SLICEM_X0.PRECYINIT.CIN !00_12 !30_14 30_13
CLBLM_L.SLICEM_X0.SRUSEDMUX 01_35
CLBLM_L.SLICEM_X0.WA7USED 00_40
CLBLM_L.SLICEM_X0.WA8USED 01_27
CLBLM_L.SLICEM_X0.WEMUX.CE 01_23
CLBLM_L.SLICEM_X0.WEMUX.CE 01_23 24_62 26_32 26_36

145
artix7/segbits_clblm_r.db
View File

@ -1,15 +1,7 @@
CLBLM_R.SLICEL_X1.A5FF.MUX.A 31_08
CLBLM_R.SLICEL_X1.A5FF.MUX.B 31_11
CLBLM_R.SLICEL_X1.A5FF.ZINI 31_05
CLBLM_R.SLICEL_X1.A5FF.ZRST 01_03
CLBLM_R.SLICEL_X1.A5FFMUX.IN_A 31_08
CLBLM_R.SLICEL_X1.A5FFMUX.IN_B 31_11
CLBLM_R.SLICEL_X1.AFF.DMUX.AX !30_04 !31_00 !31_02 31_01
CLBLM_R.SLICEL_X1.AFF.DMUX.CY !30_04 !31_01 31_00 31_02
CLBLM_R.SLICEL_X1.AFF.DMUX.F7 !30_04 !31_02 31_00 31_01
CLBLM_R.SLICEL_X1.AFF.DMUX.O5 !31_01 !31_02 30_04 31_00
CLBLM_R.SLICEL_X1.AFF.DMUX.O6 !31_00 !31_01 !31_02 30_04
CLBLM_R.SLICEL_X1.AFF.DMUX.XOR !30_04 !31_00 !31_01 31_02
CLBLM_R.SLICEL_X1.AFF.ZINI 31_04
CLBLM_R.SLICEL_X1.AFF.ZRST 31_15
CLBLM_R.SLICEL_X1.AFFMUX.AX !30_04 !31_00 !31_02 31_01
@ -82,29 +74,16 @@ CLBLM_R.SLICEL_X1.ALUT.INIT[60] 29_01
CLBLM_R.SLICEL_X1.ALUT.INIT[61] 28_01
CLBLM_R.SLICEL_X1.ALUT.INIT[62] 29_00
CLBLM_R.SLICEL_X1.ALUT.INIT[63] 28_00
CLBLM_R.SLICEL_X1.AMUX.A5Q !31_07 !31_09 !31_10 30_05
CLBLM_R.SLICEL_X1.AMUX.CY !30_05 !31_09 31_07 31_10
CLBLM_R.SLICEL_X1.AMUX.F7 !31_07 !31_09 30_05 31_10
CLBLM_R.SLICEL_X1.AMUX.O5 !30_05 !31_07 31_09 31_10
CLBLM_R.SLICEL_X1.AMUX.O6 !30_05 !31_07 !31_10 31_09
CLBLM_R.SLICEL_X1.AMUX.XOR !30_05 !31_09 !31_10 31_07
CLBLM_R.SLICEL_X1.AOUTMUX.A5Q !31_07 !31_09 !31_10 30_05
CLBLM_R.SLICEL_X1.AOUTMUX.CY !30_05 !31_09 31_07 31_10
CLBLM_R.SLICEL_X1.AOUTMUX.F7 !31_07 !31_09 30_05 31_10
CLBLM_R.SLICEL_X1.AOUTMUX.O5 !30_05 !31_07 31_09 31_10
CLBLM_R.SLICEL_X1.AOUTMUX.O6 !30_05 !31_07 !31_10 31_09
CLBLM_R.SLICEL_X1.AOUTMUX.XOR !30_05 !31_09 !31_10 31_07
CLBLM_R.SLICEL_X1.B5FF.MUX.A 31_19
CLBLM_R.SLICEL_X1.B5FF.MUX.B 31_18
CLBLM_R.SLICEL_X1.B5FF.ZINI 31_23
CLBLM_R.SLICEL_X1.B5FF.ZRST 00_16
CLBLM_R.SLICEL_X1.B5FFMUX.IN_A 31_19
CLBLM_R.SLICEL_X1.B5FFMUX.IN_B 31_18
CLBLM_R.SLICEL_X1.BFF.DMUX.BX !31_24 !31_25 !31_26 31_27
CLBLM_R.SLICEL_X1.BFF.DMUX.CY !31_24 !31_27 31_25 31_26
CLBLM_R.SLICEL_X1.BFF.DMUX.F8 !31_24 !31_26 31_25 31_27
CLBLM_R.SLICEL_X1.BFF.DMUX.O5 !31_26 !31_27 31_24 31_25
CLBLM_R.SLICEL_X1.BFF.DMUX.O6 !31_25 !31_26 !31_27 31_24
CLBLM_R.SLICEL_X1.BFF.DMUX.XOR !31_24 !31_25 !31_27 31_26
CLBLM_R.SLICEL_X1.BFF.ZINI 31_29
CLBLM_R.SLICEL_X1.BFF.ZRST 31_30
CLBLM_R.SLICEL_X1.BFFMUX.BX !31_24 !31_25 !31_26 31_27
@ -177,35 +156,21 @@ CLBLM_R.SLICEL_X1.BLUT.INIT[60] 29_17
CLBLM_R.SLICEL_X1.BLUT.INIT[61] 28_17
CLBLM_R.SLICEL_X1.BLUT.INIT[62] 29_16
CLBLM_R.SLICEL_X1.BLUT.INIT[63] 28_16
CLBLM_R.SLICEL_X1.BMUX.B5Q !30_28 !31_20 !31_21 30_29
CLBLM_R.SLICEL_X1.BMUX.CY !30_29 !31_20 30_28 31_21
CLBLM_R.SLICEL_X1.BMUX.F8 !30_28 !31_20 30_29 31_21
CLBLM_R.SLICEL_X1.BMUX.O5 !30_28 !30_29 31_20 31_21
CLBLM_R.SLICEL_X1.BMUX.O6 !30_28 !30_29 !31_21 31_20
CLBLM_R.SLICEL_X1.BMUX.XOR !30_29 !31_20 !31_21 30_28
CLBLM_R.SLICEL_X1.BOUTMUX.B5Q !30_28 !31_20 !31_21 30_29
CLBLM_R.SLICEL_X1.BOUTMUX.CY !30_29 !31_20 30_28 31_21
CLBLM_R.SLICEL_X1.BOUTMUX.F8 !30_28 !31_20 30_29 31_21
CLBLM_R.SLICEL_X1.BOUTMUX.O5 !30_28 !30_29 31_20 31_21
CLBLM_R.SLICEL_X1.BOUTMUX.O6 !30_28 !30_29 !31_21 31_20
CLBLM_R.SLICEL_X1.BOUTMUX.XOR !30_29 !31_20 !31_21 30_28
CLBLM_R.SLICEL_X1.C5FF.MUX.A 31_44
CLBLM_R.SLICEL_X1.C5FF.MUX.B 31_39
CLBLM_R.SLICEL_X1.C5FF.ZINI 31_42
CLBLM_R.SLICEL_X1.C5FF.ZRST 00_44
CLBLM_R.SLICEL_X1.C5FFMUX.IN_A 31_44
CLBLM_R.SLICEL_X1.C5FFMUX.IN_B 31_39
CLBLM_R.SLICEL_X1.CARRY4.ACY0 31_14
CLBLM_R.SLICEL_X1.CARRY4.BCY0 !31_24 !31_25 !31_26 00_08 31_27 31_29 31_30
CLBLM_R.SLICEL_X1.CARRY4.ACY0 31_01 31_04 31_14 31_15
CLBLM_R.SLICEL_X1.CARRY4.BCY0 00_08
CLBLM_R.SLICEL_X1.CARRY4.CCY0 31_48
CLBLM_R.SLICEL_X1.CARRY4.DCY0 31_49
CLBLM_R.SLICEL_X1.CEUSEDMUX 00_36
CLBLM_R.SLICEL_X1.CFF.DMUX.CX !31_35 !31_36 !31_37 31_38
CLBLM_R.SLICEL_X1.CFF.DMUX.CY !31_36 !31_38 31_35 31_37
CLBLM_R.SLICEL_X1.CFF.DMUX.F7 !31_36 !31_37 31_35 31_38
CLBLM_R.SLICEL_X1.CFF.DMUX.O5 !31_37 !31_38 31_35 31_36
CLBLM_R.SLICEL_X1.CFF.DMUX.O6 !31_35 !31_37 !31_38 31_36
CLBLM_R.SLICEL_X1.CFF.DMUX.XOR !31_35 !31_36 !31_38 31_37
CLBLM_R.SLICEL_X1.CFF.ZINI 31_34
CLBLM_R.SLICEL_X1.CFF.ZRST 30_34
CLBLM_R.SLICEL_X1.CFFMUX.CX !31_35 !31_36 !31_37 31_38
@ -279,29 +244,16 @@ CLBLM_R.SLICEL_X1.CLUT.INIT[60] 29_33
CLBLM_R.SLICEL_X1.CLUT.INIT[61] 28_33
CLBLM_R.SLICEL_X1.CLUT.INIT[62] 29_32
CLBLM_R.SLICEL_X1.CLUT.INIT[63] 28_32
CLBLM_R.SLICEL_X1.CMUX.C5Q !30_42 !31_40 !31_43 30_41
CLBLM_R.SLICEL_X1.CMUX.CY !30_41 !31_43 30_42 31_40
CLBLM_R.SLICEL_X1.CMUX.F7 !30_42 !31_43 30_41 31_40
CLBLM_R.SLICEL_X1.CMUX.O5 !30_41 !30_42 31_40 31_43
CLBLM_R.SLICEL_X1.CMUX.O6 !30_41 !30_42 !31_40 31_43
CLBLM_R.SLICEL_X1.CMUX.XOR !30_41 !31_40 !31_43 30_42
CLBLM_R.SLICEL_X1.COUTMUX.C5Q !30_42 !31_40 !31_43 30_41
CLBLM_R.SLICEL_X1.COUTMUX.CY !30_41 !31_43 30_42 31_40
CLBLM_R.SLICEL_X1.COUTMUX.F7 !30_42 !31_43 30_41 31_40
CLBLM_R.SLICEL_X1.COUTMUX.O5 !30_41 !30_42 31_40 31_43
CLBLM_R.SLICEL_X1.COUTMUX.O6 !30_41 !30_42 !31_40 31_43
CLBLM_R.SLICEL_X1.COUTMUX.XOR !30_41 !31_40 !31_43 30_42
CLBLM_R.SLICEL_X1.D5FF.MUX.A 31_55
CLBLM_R.SLICEL_X1.D5FF.MUX.B 31_54
CLBLM_R.SLICEL_X1.D5FF.ZINI 31_52
CLBLM_R.SLICEL_X1.D5FF.ZRST 00_56
CLBLM_R.SLICEL_X1.D5FFMUX.IN_A 31_55
CLBLM_R.SLICEL_X1.D5FFMUX.IN_B !22_63 !23_63 !24_63 25_63 31_54
CLBLM_R.SLICEL_X1.D5FFMUX.IN_B 31_54
CLBLM_R.SLICEL_X1.DFF.DMUX.CY !31_60 !31_61 30_58 31_62
CLBLM_R.SLICEL_X1.DFF.DMUX.DX !30_58 !31_60 !31_62 31_61
CLBLM_R.SLICEL_X1.DFF.DMUX.O5 !31_61 !31_62 30_58 31_60
CLBLM_R.SLICEL_X1.DFF.DMUX.O6 !30_58 !31_61 !31_62 31_60
CLBLM_R.SLICEL_X1.DFF.DMUX.XOR !30_58 !31_60 !31_61 31_62
CLBLM_R.SLICEL_X1.DFF.ZINI 31_59
CLBLM_R.SLICEL_X1.DFF.ZRST 31_50
CLBLM_R.SLICEL_X1.DFFMUX.CY !31_60 !31_61 30_58 31_62
@ -373,34 +325,21 @@ CLBLM_R.SLICEL_X1.DLUT.INIT[60] 29_49
CLBLM_R.SLICEL_X1.DLUT.INIT[61] 28_49
CLBLM_R.SLICEL_X1.DLUT.INIT[62] 29_48
CLBLM_R.SLICEL_X1.DLUT.INIT[63] 28_48
CLBLM_R.SLICEL_X1.DMUX.CY !31_53 !31_56 30_53 31_57
CLBLM_R.SLICEL_X1.DMUX.D5Q !30_53 !31_56 !31_57 31_53
CLBLM_R.SLICEL_X1.DMUX.O5 !30_53 !31_53 31_56 31_57
CLBLM_R.SLICEL_X1.DMUX.O6 !30_53 !31_53 !31_57 31_56
CLBLM_R.SLICEL_X1.DMUX.XOR !31_53 !31_56 !31_57 30_53
CLBLM_R.SLICEL_X1.DOUTMUX.CY !31_53 !31_56 30_53 31_57
CLBLM_R.SLICEL_X1.DOUTMUX.D5Q !30_53 !31_56 !31_57 31_53
CLBLM_R.SLICEL_X1.DOUTMUX.O5 !30_53 !31_53 31_56 31_57
CLBLM_R.SLICEL_X1.DOUTMUX.O6 !30_53 !31_53 !31_57 31_56
CLBLM_R.SLICEL_X1.DOUTMUX.XOR !31_53 !31_56 !31_57 30_53
CLBLM_R.SLICEL_X1.FFSYNC 01_31
CLBLM_R.SLICEL_X1.LATCH 31_32
CLBLM_R.SLICEL_X1.PRECYINIT.1 01_11
CLBLM_R.SLICEL_X1.PRECYINIT.AX 31_13
CLBLM_R.SLICEL_X1.PRECYINIT.CIN 31_12
CLBLM_R.SLICEL_X1.PRECYINIT.1 !31_12 !31_13 01_11
CLBLM_R.SLICEL_X1.PRECYINIT.AX !01_11 !31_12 31_13
CLBLM_R.SLICEL_X1.PRECYINIT.CIN !01_11 !31_13 31_12
CLBLM_R.SLICEL_X1.SRUSEDMUX 00_32
CLBLM_R.SLICEM_X0.A5FF.MUX.A 30_09
CLBLM_R.SLICEM_X0.A5FF.MUX.B 30_10
CLBLM_R.SLICEM_X0.A5FF.ZINI 31_06
CLBLM_R.SLICEM_X0.A5FF.ZRST 01_07
CLBLM_R.SLICEM_X0.A5FFMUX.IN_A 30_09
CLBLM_R.SLICEM_X0.A5FFMUX.IN_B 30_10
CLBLM_R.SLICEM_X0.ADI1MUX.AI 00_00
CLBLM_R.SLICEM_X0.AFF.DMUX.AX !30_00 !30_02 !30_03 30_01
CLBLM_R.SLICEM_X0.AFF.DMUX.CY !30_01 !30_03 30_00 30_02
CLBLM_R.SLICEM_X0.AFF.DMUX.F7 !30_02 !30_03 30_00 30_01
CLBLM_R.SLICEM_X0.AFF.DMUX.O5 !30_01 !30_02 30_00 30_03
CLBLM_R.SLICEM_X0.AFF.DMUX.O6 !30_00 !30_01 !30_02 30_03
CLBLM_R.SLICEM_X0.AFF.DMUX.XOR !30_00 !30_01 !30_03 30_02
CLBLM_R.SLICEM_X0.AFF.ZINI 31_03
CLBLM_R.SLICEM_X0.AFF.ZRST 30_12
CLBLM_R.SLICEM_X0.AFFMUX.AX !30_00 !30_02 !30_03 30_01
@ -475,32 +414,16 @@ CLBLM_R.SLICEM_X0.ALUT.INIT[61] 33_01
CLBLM_R.SLICEM_X0.ALUT.INIT[62] 32_00
CLBLM_R.SLICEM_X0.ALUT.INIT[63] 33_00
CLBLM_R.SLICEM_X0.ALUT.RAM 31_16
CLBLM_R.SLICEM_X0.ALUT.SMALL 00_04
CLBLM_R.SLICEM_X0.ALUT.SRL 30_16
CLBLM_R.SLICEM_X0.AMUX.A5Q !30_06 !30_08 !30_11 30_07
CLBLM_R.SLICEM_X0.AMUX.CY !30_07 !30_11 30_06 30_08
CLBLM_R.SLICEM_X0.AMUX.F7 !30_08 !30_11 30_06 30_07
CLBLM_R.SLICEM_X0.AMUX.O5 !30_07 !30_08 30_06 30_11
CLBLM_R.SLICEM_X0.AMUX.O6 !30_06 !30_07 !30_08 30_11
CLBLM_R.SLICEM_X0.AMUX.XOR !30_06 !30_07 !30_11 30_08
CLBLM_R.SLICEM_X0.AOUTMUX.A5Q !30_06 !30_08 !30_11 30_07
CLBLM_R.SLICEM_X0.AOUTMUX.CY !30_07 !30_11 30_06 30_08
CLBLM_R.SLICEM_X0.AOUTMUX.F7 !30_08 !30_11 30_06 30_07
CLBLM_R.SLICEM_X0.AOUTMUX.O5 !30_07 !30_08 30_06 30_11
CLBLM_R.SLICEM_X0.AOUTMUX.O6 !30_06 !30_07 !30_08 30_11
CLBLM_R.SLICEM_X0.AOUTMUX.XOR !30_06 !30_07 !30_11 30_08
CLBLM_R.SLICEM_X0.B5FF.MUX.A 30_19
CLBLM_R.SLICEM_X0.B5FF.MUX.B 30_18
CLBLM_R.SLICEM_X0.B5FF.ZINI 31_22
CLBLM_R.SLICEM_X0.B5FF.ZRST 01_19
CLBLM_R.SLICEM_X0.B5FFMUX.IN_A 30_19
CLBLM_R.SLICEM_X0.B5FFMUX.IN_B 30_18
CLBLM_R.SLICEM_X0.BDI1MUX.BI 00_20
CLBLM_R.SLICEM_X0.BFF.DMUX.BX !30_24 !30_25 !30_27 30_26
CLBLM_R.SLICEM_X0.BFF.DMUX.CY !30_24 !30_26 30_25 30_27
CLBLM_R.SLICEM_X0.BFF.DMUX.F8 !30_24 !30_25 30_26 30_27
CLBLM_R.SLICEM_X0.BFF.DMUX.O5 !30_25 !30_26 30_24 30_27
CLBLM_R.SLICEM_X0.BFF.DMUX.O6 !30_25 !30_26 !30_27 30_24
CLBLM_R.SLICEM_X0.BFF.DMUX.XOR !30_24 !30_26 !30_27 30_25
CLBLM_R.SLICEM_X0.BFF.ZINI 31_28
CLBLM_R.SLICEM_X0.BFF.ZRST 30_30
CLBLM_R.SLICEM_X0.BFFMUX.BX !30_24 !30_25 !30_27 30_26
@ -575,38 +498,21 @@ CLBLM_R.SLICEM_X0.BLUT.INIT[61] 33_17
CLBLM_R.SLICEM_X0.BLUT.INIT[62] 32_16
CLBLM_R.SLICEM_X0.BLUT.INIT[63] 33_16
CLBLM_R.SLICEM_X0.BLUT.RAM 31_17
CLBLM_R.SLICEM_X0.BLUT.SMALL 00_24
CLBLM_R.SLICEM_X0.BLUT.SRL 30_17
CLBLM_R.SLICEM_X0.BMUX.B5Q !30_20 !30_21 !30_22 30_23
CLBLM_R.SLICEM_X0.BMUX.CY !30_20 !30_23 30_21 30_22
CLBLM_R.SLICEM_X0.BMUX.F8 !30_20 !30_21 30_22 30_23
CLBLM_R.SLICEM_X0.BMUX.O5 !30_21 !30_23 30_20 30_22
CLBLM_R.SLICEM_X0.BMUX.O6 !30_21 !30_22 !30_23 30_20
CLBLM_R.SLICEM_X0.BMUX.XOR !30_20 !30_22 !30_23 30_21
CLBLM_R.SLICEM_X0.BOUTMUX.B5Q !30_20 !30_21 !30_22 30_23
CLBLM_R.SLICEM_X0.BOUTMUX.CY !30_20 !30_23 30_21 30_22
CLBLM_R.SLICEM_X0.BOUTMUX.F8 !30_20 !30_21 30_22 30_23
CLBLM_R.SLICEM_X0.BOUTMUX.O5 !30_21 !30_23 30_20 30_22
CLBLM_R.SLICEM_X0.BOUTMUX.O6 !30_21 !30_22 !30_23 30_20
CLBLM_R.SLICEM_X0.BOUTMUX.XOR !30_20 !30_22 !30_23 30_21
CLBLM_R.SLICEM_X0.C5FF.MUX.A 31_45
CLBLM_R.SLICEM_X0.C5FF.MUX.B 30_39
CLBLM_R.SLICEM_X0.C5FF.ZINI 31_41
CLBLM_R.SLICEM_X0.C5FF.ZRST 01_47
CLBLM_R.SLICEM_X0.C5FFMUX.IN_A 31_45
CLBLM_R.SLICEM_X0.C5FFMUX.IN_B 30_39
CLBLM_R.SLICEM_X0.CARRY4.ACY0 !30_00 !30_02 !30_03 30_01 30_12 30_15 31_03
CLBLM_R.SLICEM_X0.CARRY4.ACY0 30_15
CLBLM_R.SLICEM_X0.CARRY4.BCY0 01_15
CLBLM_R.SLICEM_X0.CARRY4.CCY0 30_48
CLBLM_R.SLICEM_X0.CARRY4.DCY0 30_49
CLBLM_R.SLICEM_X0.CDI1MUX.CI 01_43
CLBLM_R.SLICEM_X0.CEUSEDMUX 01_39
CLBLM_R.SLICEM_X0.CFF.DMUX.CX !30_35 !30_37 !30_38 30_36
CLBLM_R.SLICEM_X0.CFF.DMUX.CY !30_36 !30_38 30_35 30_37
CLBLM_R.SLICEM_X0.CFF.DMUX.F7 !30_37 !30_38 30_35 30_36
CLBLM_R.SLICEM_X0.CFF.DMUX.O5 !30_36 !30_37 30_35 30_38
CLBLM_R.SLICEM_X0.CFF.DMUX.O6 !30_35 !30_36 !30_37 30_38
CLBLM_R.SLICEM_X0.CFF.DMUX.XOR !30_35 !30_36 !30_38 30_37
CLBLM_R.SLICEM_X0.CFF.ZINI 31_33
CLBLM_R.SLICEM_X0.CFF.ZRST 30_33
CLBLM_R.SLICEM_X0.CFFMUX.CX !30_35 !30_37 !30_38 30_36
@ -682,31 +588,16 @@ CLBLM_R.SLICEM_X0.CLUT.INIT[61] 33_33
CLBLM_R.SLICEM_X0.CLUT.INIT[62] 32_32
CLBLM_R.SLICEM_X0.CLUT.INIT[63] 33_32
CLBLM_R.SLICEM_X0.CLUT.RAM 31_46
CLBLM_R.SLICEM_X0.CLUT.SMALL 00_28
CLBLM_R.SLICEM_X0.CLUT.SRL 30_46
CLBLM_R.SLICEM_X0.CMUX.C5Q !30_40 !30_44 !30_45 30_43
CLBLM_R.SLICEM_X0.CMUX.CY !30_43 !30_45 30_40 30_44
CLBLM_R.SLICEM_X0.CMUX.F7 !30_44 !30_45 30_40 30_43
CLBLM_R.SLICEM_X0.CMUX.O5 !30_43 !30_44 30_40 30_45
CLBLM_R.SLICEM_X0.CMUX.O6 !30_40 !30_43 !30_44 30_45
CLBLM_R.SLICEM_X0.CMUX.XOR !30_40 !30_43 !30_45 30_44
CLBLM_R.SLICEM_X0.COUTMUX.C5Q !30_40 !30_44 !30_45 30_43
CLBLM_R.SLICEM_X0.COUTMUX.CY !30_43 !30_45 30_40 30_44
CLBLM_R.SLICEM_X0.COUTMUX.F7 !30_44 !30_45 30_40 30_43
CLBLM_R.SLICEM_X0.COUTMUX.O5 !30_43 !30_44 30_40 30_45
CLBLM_R.SLICEM_X0.COUTMUX.O6 !30_40 !30_43 !30_44 30_45
CLBLM_R.SLICEM_X0.COUTMUX.XOR !30_40 !30_43 !30_45 30_44
CLBLM_R.SLICEM_X0.D5FF.MUX.A 30_55
CLBLM_R.SLICEM_X0.D5FF.MUX.B 30_54
CLBLM_R.SLICEM_X0.D5FF.ZINI 31_51
CLBLM_R.SLICEM_X0.D5FF.ZRST 01_55
CLBLM_R.SLICEM_X0.D5FFMUX.IN_A 30_55
CLBLM_R.SLICEM_X0.D5FFMUX.IN_B !22_55 !23_55 !24_55 25_55 30_54
CLBLM_R.SLICEM_X0.D5FFMUX.IN_B 30_54
CLBLM_R.SLICEM_X0.DFF.DMUX.CY !30_59 !30_61 30_60 30_62
CLBLM_R.SLICEM_X0.DFF.DMUX.DX !30_59 !30_60 !30_62 30_61
CLBLM_R.SLICEM_X0.DFF.DMUX.O5 !30_60 !30_61 30_59 30_62
CLBLM_R.SLICEM_X0.DFF.DMUX.O6 !30_60 !30_61 !30_62 30_59
CLBLM_R.SLICEM_X0.DFF.DMUX.XOR !30_59 !30_61 !30_62 30_60
CLBLM_R.SLICEM_X0.DFF.ZINI 31_58
CLBLM_R.SLICEM_X0.DFF.ZRST 30_50
CLBLM_R.SLICEM_X0.DFFMUX.CY !30_59 !30_61 30_60 30_62
@ -781,21 +672,17 @@ CLBLM_R.SLICEM_X0.DLUT.INIT[63] 33_48
CLBLM_R.SLICEM_X0.DLUT.RAM 31_47
CLBLM_R.SLICEM_X0.DLUT.SMALL 01_59
CLBLM_R.SLICEM_X0.DLUT.SRL 30_47
CLBLM_R.SLICEM_X0.DMUX.CY !30_56 !30_57 30_51 30_52
CLBLM_R.SLICEM_X0.DMUX.D5Q !30_51 !30_52 !30_56 30_57
CLBLM_R.SLICEM_X0.DMUX.O5 !30_51 !30_57 30_52 30_56
CLBLM_R.SLICEM_X0.DMUX.O6 !30_51 !30_52 !30_57 30_56
CLBLM_R.SLICEM_X0.DMUX.XOR !30_52 !30_56 !30_57 30_51
CLBLM_R.SLICEM_X0.DOUTMUX.CY !30_56 !30_57 30_51 30_52
CLBLM_R.SLICEM_X0.DOUTMUX.D5Q !30_51 !30_52 !30_56 30_57
CLBLM_R.SLICEM_X0.DOUTMUX.O5 !30_51 !30_57 30_52 30_56
CLBLM_R.SLICEM_X0.DOUTMUX.O6 !30_51 !30_52 !30_57 30_56
CLBLM_R.SLICEM_X0.DOUTMUX.XOR !30_52 !30_56 !30_57 30_51
CLBLM_R.SLICEM_X0.FFSYNC 00_48
CLBLM_R.SLICEM_X0.LATCH 30_32
CLBLM_R.SLICEM_X0.PRECYINIT.1 00_12
CLBLM_R.SLICEM_X0.PRECYINIT.AX 30_14
CLBLM_R.SLICEM_X0.PRECYINIT.CIN 30_13
CLBLM_R.SLICEM_X0.PRECYINIT.1 !30_13 !30_14 00_12
CLBLM_R.SLICEM_X0.PRECYINIT.AX !00_12 !30_13 30_14
CLBLM_R.SLICEM_X0.PRECYINIT.CIN !00_12 !30_14 30_13
CLBLM_R.SLICEM_X0.SRUSEDMUX 01_35
CLBLM_R.SLICEM_X0.WA7USED 00_40
CLBLM_R.SLICEM_X0.WA8USED 01_27
CLBLM_R.SLICEM_X0.WEMUX.CE 01_23
CLBLM_R.SLICEM_X0.WEMUX.CE 01_23 24_62 26_32 26_36

4
artix7/segbits_hclk_l.db
View File

@ -2,10 +2,6 @@ HCLK_L.ENABLE_BUFFER.HCLK_CK_BUFHCLK10 00_22
HCLK_L.ENABLE_BUFFER.HCLK_CK_BUFHCLK11 01_22
HCLK_L.ENABLE_BUFFER.HCLK_CK_BUFHCLK8 00_14
HCLK_L.ENABLE_BUFFER.HCLK_CK_BUFHCLK9 01_19
HCLK_L.ENABLE_BUFFER.HCLK_CK_BUFRCLK0 00_23
HCLK_L.ENABLE_BUFFER.HCLK_CK_BUFRCLK1 01_23
HCLK_L.ENABLE_BUFFER.HCLK_CK_BUFRCLK2 00_31
HCLK_L.ENABLE_BUFFER.HCLK_CK_BUFRCLK3 01_31
HCLK_L.HCLK_LEAF_CLK_B_BOTL0.HCLK_CK_BUFHCLK10 01_15 04_15
HCLK_L.HCLK_LEAF_CLK_B_BOTL0.HCLK_CK_BUFHCLK11 01_15 03_15
HCLK_L.HCLK_LEAF_CLK_B_BOTL0.HCLK_CK_BUFHCLK8 01_15 04_14

16
artix7/segbits_int_l.db
View File

@ -19,7 +19,7 @@ INT_L.BYP_ALT0.SL1END0 !23_07 19_06 22_07 24_07 25_07
INT_L.BYP_ALT0.SR1END_N3_3 !22_07 18_06 23_07 24_07 25_07
INT_L.BYP_ALT0.SS2END0 !22_07 !23_07 !25_07 16_07 24_07
INT_L.BYP_ALT0.SW2END0 !22_07 !23_07 !24_07 16_07 25_07
INT_L.BYP_ALT0.VCC_WIRE !30_04 !30_58 !31_00 !31_01 !31_24 !31_25 !31_27 !31_35 !31_36 !31_38 !31_60 !31_61 31_02 31_26 31_37 31_62
INT_L.BYP_ALT0.VCC_WIRE 31_02 31_26 31_37 31_62
INT_L.BYP_ALT0.WL1END0 !23_07 17_07 22_07 24_07 25_07
INT_L.BYP_ALT0.WR1END0 !22_07 16_07 23_07 24_07 25_07
INT_L.BYP_ALT0.WW2END_N0_3 !22_07 !23_07 !25_07 17_07 24_07
@ -44,7 +44,7 @@ INT_L.BYP_ALT1.SL1END0 !23_15 19_14 22_15 24_15 25_15
INT_L.BYP_ALT1.SR1BEG_S0 !22_15 18_14 23_15 24_15 25_15
INT_L.BYP_ALT1.SS2END0 !22_15 !23_15 !25_15 19_14 24_15
INT_L.BYP_ALT1.SW2END0 !22_15 !23_15 !24_15 19_14 25_15
INT_L.BYP_ALT1.VCC_WIRE !30_00 !30_01 !30_03 !30_24 !30_26 !30_27 !30_35 !30_36 !30_38 !30_59 !30_61 !30_62 30_02 30_25 30_37 30_60
INT_L.BYP_ALT1.VCC_WIRE 30_02 30_25 30_37 30_60
INT_L.BYP_ALT1.WL1END0 !23_15 16_15 22_15 24_15 25_15
INT_L.BYP_ALT1.WR1END1 !22_15 17_15 23_15 24_15 25_15
INT_L.BYP_ALT1.WW2END0 !22_15 !23_15 !25_15 18_14 24_15
@ -607,7 +607,7 @@ INT_L.FAN_ALT1.EL1END3 !22_48 17_48 23_48 24_48 25_48
INT_L.FAN_ALT1.ER1END2 !23_48 16_48 22_48 24_48 25_48
INT_L.FAN_ALT1.FAN_BOUNCE3 !22_48 20_48 23_48 24_48 25_48
INT_L.FAN_ALT1.FAN_BOUNCE_S3_4 !23_48 20_48 22_48 24_48 25_48
INT_L.FAN_ALT1.GFAN1 !22_48 !23_48 !24_48 21_48 25_48
INT_L.FAN_ALT1.GFAN1 00_14 00_17 21_48 25_48
INT_L.FAN_ALT1.LOGIC_OUTS_L11 !22_48 21_48 23_48 24_48 25_48
INT_L.FAN_ALT1.LOGIC_OUTS_L17 !22_48 !23_48 !25_48 21_48 24_48
INT_L.FAN_ALT1.LOGIC_OUTS_L7 !23_48 21_48 22_48 24_48 25_48
@ -672,7 +672,7 @@ INT_L.FAN_ALT3.SW2END3 !22_56 !23_56 !25_56 18_57 24_56
INT_L.FAN_ALT3.WL1END3 !22_56 17_56 23_56 24_56 25_56
INT_L.FAN_ALT3.WR1END3 !23_56 16_56 22_56 24_56 25_56
INT_L.FAN_ALT3.WW2END3 !22_56 !23_56 !24_56 19_57 25_56
INT_L.FAN_ALT4.BYP_BOUNCE_N3_3 !22_08 !23_08 !24_08 20_08 25_08
INT_L.FAN_ALT4.BYP_BOUNCE_N3_3 20_08 25_08
INT_L.FAN_ALT4.BYP_BOUNCE_N3_7 !22_08 !23_08 !25_08 20_08 24_08
INT_L.FAN_ALT4.EE2END0 !22_08 !23_08 !24_08 16_08 25_08
INT_L.FAN_ALT4.EL1END0 !22_08 16_08 23_08 24_08 25_08
@ -696,14 +696,14 @@ INT_L.FAN_ALT4.SW2END0 !22_08 !23_08 !25_08 18_09 24_08
INT_L.FAN_ALT4.WL1END0 !22_08 17_08 23_08 24_08 25_08
INT_L.FAN_ALT4.WR1END0 !23_08 16_08 22_08 24_08 25_08
INT_L.FAN_ALT4.WW2END0 !22_08 !23_08 !24_08 19_09 25_08
INT_L.FAN_ALT5.BYP_BOUNCE1 !22_40 !23_40 !25_40 20_40 24_40
INT_L.FAN_ALT5.BYP_BOUNCE1 20_40 24_40
INT_L.FAN_ALT5.BYP_BOUNCE5 !22_40 !23_40 !24_40 20_40 25_40
INT_L.FAN_ALT5.EE2END2 !22_40 !23_40 !24_40 16_40 25_40
INT_L.FAN_ALT5.EL1END2 !22_40 16_40 23_40 24_40 25_40
INT_L.FAN_ALT5.ER1END2 !23_40 17_40 22_40 24_40 25_40
INT_L.FAN_ALT5.FAN_BOUNCE1 !22_40 20_40 23_40 24_40 25_40
INT_L.FAN_ALT5.FAN_BOUNCE_S3_0 !23_40 20_40 22_40 24_40 25_40
INT_L.FAN_ALT5.GFAN1 !22_40 !23_40 !24_40 21_40 25_40
INT_L.FAN_ALT5.GFAN1 00_14 00_17 21_40 25_40
INT_L.FAN_ALT5.LOGIC_OUTS_L10 !22_40 21_40 23_40 24_40 25_40
INT_L.FAN_ALT5.LOGIC_OUTS_L16 !22_40 !23_40 !25_40 21_40 24_40
INT_L.FAN_ALT5.LOGIC_OUTS_L6 !23_40 21_40 22_40 24_40 25_40
@ -727,7 +727,6 @@ INT_L.FAN_ALT6.EL1END1 !22_24 16_24 23_24 24_24 25_24
INT_L.FAN_ALT6.ER1END1 !23_24 17_24 22_24 24_24 25_24
INT_L.FAN_ALT6.FAN_BOUNCE1 !22_24 20_24 23_24 24_24 25_24
INT_L.FAN_ALT6.FAN_BOUNCE7 !23_24 20_24 22_24 24_24 25_24
INT_L.FAN_ALT6.GFAN0 !22_24 !23_24 !24_24 00_36 21_24 25_24
INT_L.FAN_ALT6.GFAN0 !22_24 !23_24 !24_24 21_24 25_24
INT_L.FAN_ALT6.LOGIC_OUTS_L1 !23_24 21_24 22_24 24_24 25_24
INT_L.FAN_ALT6.LOGIC_OUTS_L13 !22_24 21_24 23_24 24_24 25_24
@ -752,7 +751,6 @@ INT_L.FAN_ALT7.EL1END2 !22_32 17_32 23_32 24_32 25_32
INT_L.FAN_ALT7.ER1END1 !23_32 16_32 22_32 24_32 25_32
INT_L.FAN_ALT7.FAN_BOUNCE3 !22_32 20_32 23_32 24_32 25_32
INT_L.FAN_ALT7.FAN_BOUNCE5 !23_32 20_32 22_32 24_32 25_32
INT_L.FAN_ALT7.GFAN1 !22_32 !23_32 !24_32 01_39 21_32 25_32
INT_L.FAN_ALT7.GFAN1 !22_32 !23_32 !24_32 21_32 25_32
INT_L.FAN_ALT7.LOGIC_OUTS_L14 !22_32 21_32 23_32 24_32 25_32
INT_L.FAN_ALT7.LOGIC_OUTS_L2 !23_32 21_32 22_32 24_32 25_32
@ -2028,7 +2026,7 @@ INT_L.LV_L0.WR1END0 00_02 00_07
INT_L.LV_L0.WW4END0 00_05 00_07
INT_L.LV_L18.ER1END0 00_03 00_06
INT_L.LV_L18.LH0 00_01 01_02
INT_L.LV_L18.LH12 01_02 01_08
INT_L.LV_L18.LH12 01_08
INT_L.LV_L18.LH6 00_06 01_02
INT_L.LV_L18.LV_L0 01_00 01_01
INT_L.LV_L18.NN6END0 00_03 01_00

16
artix7/segbits_int_r.db
View File

@ -19,7 +19,7 @@ INT_R.BYP_ALT0.SL1END0 !23_07 19_06 22_07 24_07 25_07
INT_R.BYP_ALT0.SR1END_N3_3 !22_07 18_06 23_07 24_07 25_07
INT_R.BYP_ALT0.SS2END0 !22_07 !23_07 !25_07 16_07 24_07
INT_R.BYP_ALT0.SW2END0 !22_07 !23_07 !24_07 16_07 25_07
INT_R.BYP_ALT0.VCC_WIRE !30_04 !30_58 !31_00 !31_01 !31_24 !31_25 !31_27 !31_35 !31_36 !31_38 !31_60 !31_61 31_02 31_26 31_37 31_62
INT_R.BYP_ALT0.VCC_WIRE 31_02 31_26 31_37 31_62
INT_R.BYP_ALT0.WL1END0 !23_07 17_07 22_07 24_07 25_07
INT_R.BYP_ALT0.WR1END0 !22_07 16_07 23_07 24_07 25_07
INT_R.BYP_ALT0.WW2END_N0_3 !22_07 !23_07 !25_07 17_07 24_07
@ -44,7 +44,7 @@ INT_R.BYP_ALT1.SL1END0 !23_15 19_14 22_15 24_15 25_15
INT_R.BYP_ALT1.SR1BEG_S0 !22_15 18_14 23_15 24_15 25_15
INT_R.BYP_ALT1.SS2END0 !22_15 !23_15 !25_15 19_14 24_15
INT_R.BYP_ALT1.SW2END0 !22_15 !23_15 !24_15 19_14 25_15
INT_R.BYP_ALT1.VCC_WIRE !30_00 !30_01 !30_03 !30_24 !30_26 !30_27 !30_35 !30_36 !30_38 !30_59 !30_61 !30_62 30_02 30_25 30_37 30_60
INT_R.BYP_ALT1.VCC_WIRE 30_02 30_25 30_37 30_60
INT_R.BYP_ALT1.WL1END0 !23_15 16_15 22_15 24_15 25_15
INT_R.BYP_ALT1.WR1END1 !22_15 17_15 23_15 24_15 25_15
INT_R.BYP_ALT1.WW2END0 !22_15 !23_15 !25_15 18_14 24_15
@ -583,7 +583,7 @@ INT_R.FAN_ALT0.EL1END0 !22_00 17_00 23_00 24_00 25_00
INT_R.FAN_ALT0.ER1END_N3_3 !23_00 16_00 22_00 24_00 25_00
INT_R.FAN_ALT0.FAN_BOUNCE4 !22_00 20_00 23_00 24_00 25_00
INT_R.FAN_ALT0.FAN_BOUNCE6 !23_00 20_00 22_00 24_00 25_00
INT_R.FAN_ALT0.GFAN0 !22_00 !23_00 !24_00 21_00 25_00
INT_R.FAN_ALT0.GFAN0 01_10 01_14 21_00 25_00
INT_R.FAN_ALT0.LOGIC_OUTS0 !23_00 21_00 22_00 24_00 25_00
INT_R.FAN_ALT0.LOGIC_OUTS12 !22_00 21_00 23_00 24_00 25_00
INT_R.FAN_ALT0.LOGIC_OUTS22 !22_00 !23_00 !25_00 21_00 24_00
@ -607,7 +607,7 @@ INT_R.FAN_ALT1.EL1END3 !22_48 17_48 23_48 24_48 25_48
INT_R.FAN_ALT1.ER1END2 !23_48 16_48 22_48 24_48 25_48
INT_R.FAN_ALT1.FAN_BOUNCE3 !22_48 20_48 23_48 24_48 25_48
INT_R.FAN_ALT1.FAN_BOUNCE_S3_4 !23_48 20_48 22_48 24_48 25_48
INT_R.FAN_ALT1.GFAN1 !22_48 !23_48 !24_48 21_48 25_48
INT_R.FAN_ALT1.GFAN1 00_14 00_17 21_48 25_48
INT_R.FAN_ALT1.LOGIC_OUTS11 !22_48 21_48 23_48 24_48 25_48
INT_R.FAN_ALT1.LOGIC_OUTS17 !22_48 !23_48 !25_48 21_48 24_48
INT_R.FAN_ALT1.LOGIC_OUTS7 !23_48 21_48 22_48 24_48 25_48
@ -655,7 +655,7 @@ INT_R.FAN_ALT3.EL1END3 !22_56 16_56 23_56 24_56 25_56
INT_R.FAN_ALT3.ER1END3 !23_56 17_56 22_56 24_56 25_56
INT_R.FAN_ALT3.FAN_BOUNCE_S3_0 !22_56 20_56 23_56 24_56 25_56
INT_R.FAN_ALT3.FAN_BOUNCE_S3_2 !23_56 20_56 22_56 24_56 25_56
INT_R.FAN_ALT3.GFAN1 !22_56 !23_56 !24_56 21_56 25_56
INT_R.FAN_ALT3.GFAN1 00_14 00_17 21_56 25_56
INT_R.FAN_ALT3.LOGIC_OUTS15 !22_56 21_56 23_56 24_56 25_56
INT_R.FAN_ALT3.LOGIC_OUTS21 !22_56 !23_56 !25_56 21_56 24_56
INT_R.FAN_ALT3.LOGIC_OUTS3 !23_56 21_56 22_56 24_56 25_56
@ -696,7 +696,7 @@ INT_R.FAN_ALT4.SW2END0 !22_08 !23_08 !25_08 18_09 24_08
INT_R.FAN_ALT4.WL1END0 !22_08 17_08 23_08 24_08 25_08
INT_R.FAN_ALT4.WR1END0 !23_08 16_08 22_08 24_08 25_08
INT_R.FAN_ALT4.WW2END0 !22_08 !23_08 !24_08 19_09 25_08
INT_R.FAN_ALT5.BYP_BOUNCE1 !22_40 !23_40 !25_40 20_40 24_40
INT_R.FAN_ALT5.BYP_BOUNCE1 20_40 24_40 25_15
INT_R.FAN_ALT5.BYP_BOUNCE5 !22_40 !23_40 !24_40 20_40 25_40
INT_R.FAN_ALT5.EE2END2 !22_40 !23_40 !24_40 16_40 25_40
INT_R.FAN_ALT5.EL1END2 !22_40 16_40 23_40 24_40 25_40
@ -704,7 +704,6 @@ INT_R.FAN_ALT5.ER1END2 !23_40 17_40 22_40 24_40 25_40
INT_R.FAN_ALT5.FAN_BOUNCE1 !22_40 20_40 23_40 24_40 25_40
INT_R.FAN_ALT5.FAN_BOUNCE_S3_0 !23_40 20_40 22_40 24_40 25_40
INT_R.FAN_ALT5.GFAN1 !22_40 !23_40 !24_40 00_20 01_43 21_40 25_40
INT_R.FAN_ALT5.GFAN1 !22_40 !23_40 !24_40 21_40 25_40
INT_R.FAN_ALT5.LOGIC_OUTS10 !22_40 21_40 23_40 24_40 25_40
INT_R.FAN_ALT5.LOGIC_OUTS16 !22_40 !23_40 !25_40 21_40 24_40
INT_R.FAN_ALT5.LOGIC_OUTS6 !23_40 21_40 22_40 24_40 25_40
@ -728,7 +727,6 @@ INT_R.FAN_ALT6.EL1END1 !22_24 16_24 23_24 24_24 25_24
INT_R.FAN_ALT6.ER1END1 !23_24 17_24 22_24 24_24 25_24
INT_R.FAN_ALT6.FAN_BOUNCE1 !22_24 20_24 23_24 24_24 25_24
INT_R.FAN_ALT6.FAN_BOUNCE7 !23_24 20_24 22_24 24_24 25_24
INT_R.FAN_ALT6.GFAN0 !22_24 !23_24 !24_24 00_36 21_24 25_24
INT_R.FAN_ALT6.GFAN0 !22_24 !23_24 !24_24 21_24 25_24
INT_R.FAN_ALT6.LOGIC_OUTS1 !23_24 21_24 22_24 24_24 25_24
INT_R.FAN_ALT6.LOGIC_OUTS13 !22_24 21_24 23_24 24_24 25_24
@ -1992,7 +1990,7 @@ INT_R.LV0.WR1END0 00_02 00_07
INT_R.LV0.WW4END0 00_05 00_07
INT_R.LV18.ER1END0 00_03 00_06
INT_R.LV18.LH0 00_01 01_02
INT_R.LV18.LH12 01_02 01_08
INT_R.LV18.LH12 01_08
INT_R.LV18.LH6 00_06 01_02
INT_R.LV18.LV0 01_00 01_01
INT_R.LV18.NN6END0 00_03 01_00

4
artix7/settings.sh
View File

@ -3,8 +3,10 @@ export XRAY_PART="xc7a50tfgg484-1"
export XRAY_ROI_FRAMES="0x00000000:0xffffffff"
# All CLB's in part, all BRAM's in part, all DSP's in part.
export XRAY_ROI="SLICE_X0Y0:SLICE_X65Y99 SLICE_X0Y100:SLICE_X57Y149 RAMB18_X0Y0:RAMB18_X1Y59 RAMB36_X0Y0:RAMB36_X1Y29 RAMB18_X2Y0:RAMB18_X2Y39 RAMB36_X2Y0:RAMB36_X2Y19 DSP48_X0Y0:DSP48_X1Y59"
export XRAY_ROI_TILEGRID="SLICE_X0Y0:SLICE_X65Y99 SLICE_X0Y100:SLICE_X57Y149 RAMB18_X0Y0:RAMB18_X1Y59 RAMB36_X0Y0:RAMB36_X1Y29 RAMB18_X2Y0:RAMB18_X2Y39 RAMB36_X2Y0:RAMB36_X2Y19 DSP48_X0Y0:DSP48_X1Y59"
# These settings must remain in sync
export XRAY_ROI="SLICE_X0Y100:SLICE_X35Y149 RAMB18_X0Y40:RAMB18_X0Y59 RAMB36_X0Y20:RAMB36_X0Y29 DSP48_X0Y40:DSP48_X0Y59"
# Most of CMT X0Y2.
export XRAY_ROI_GRID_X1="9"
export XRAY_ROI_GRID_X2="58"

899086
artix7/tileconn.json
View File

File diff suppressed because it is too large Load Diff

525
artix7/tilegrid.json
View File

@ -6376,6 +6376,13 @@
},
"BRAM_L_X30Y0": {
"bits": {
"BLOCK_RAM": {
"baseaddr": "0x00C00080",
"frames": 128,
"height": 10,
"offset": 0,
"words": 10
},
"CLB_IO_CLK": {
"baseaddr": "0x00400F00",
"frames": 28,
@ -6397,6 +6404,13 @@
},
"BRAM_L_X30Y10": {
"bits": {
"BLOCK_RAM": {
"baseaddr": "0x00C00080",
"frames": 128,
"height": 10,
"offset": 20,
"words": 10
},
"CLB_IO_CLK": {
"baseaddr": "0x00400F00",
"frames": 28,
@ -6418,6 +6432,13 @@
},
"BRAM_L_X30Y125": {
"bits": {
"BLOCK_RAM": {
"baseaddr": "0x00820080",
"frames": 128,
"height": 10,
"offset": 0,
"words": 10
},
"CLB_IO_CLK": {
"baseaddr": "0x00020F00",
"frames": 28,
@ -6439,6 +6460,13 @@
},
"BRAM_L_X30Y130": {
"bits": {
"BLOCK_RAM": {
"baseaddr": "0x00820080",
"frames": 128,
"height": 10,
"offset": 10,
"words": 10
},
"CLB_IO_CLK": {
"baseaddr": "0x00020F00",
"frames": 28,
@ -6460,6 +6488,13 @@
},
"BRAM_L_X30Y135": {
"bits": {
"BLOCK_RAM": {
"baseaddr": "0x00820080",
"frames": 128,
"height": 10,
"offset": 20,
"words": 10
},
"CLB_IO_CLK": {
"baseaddr": "0x00020F00",
"frames": 28,
@ -6481,6 +6516,13 @@
},
"BRAM_L_X30Y140": {
"bits": {
"BLOCK_RAM": {
"baseaddr": "0x00820080",
"frames": 128,
"height": 10,
"offset": 30,
"words": 10
},
"CLB_IO_CLK": {
"baseaddr": "0x00020F00",
"frames": 28,
@ -6502,6 +6544,13 @@
},
"BRAM_L_X30Y145": {
"bits": {
"BLOCK_RAM": {
"baseaddr": "0x00820080",
"frames": 128,
"height": 10,
"offset": 40,
"words": 10
},
"CLB_IO_CLK": {
"baseaddr": "0x00020F00",
"frames": 28,
@ -6523,6 +6572,13 @@
},
"BRAM_L_X30Y15": {
"bits": {
"BLOCK_RAM": {
"baseaddr": "0x00C00080",
"frames": 128,
"height": 10,
"offset": 30,
"words": 10
},
"CLB_IO_CLK": {
"baseaddr": "0x00400F00",
"frames": 28,
@ -6544,6 +6600,13 @@
},
"BRAM_L_X30Y20": {
"bits": {
"BLOCK_RAM": {
"baseaddr": "0x00C00080",
"frames": 128,
"height": 10,
"offset": 40,
"words": 10
},
"CLB_IO_CLK": {
"baseaddr": "0x00400F00",
"frames": 28,
@ -6565,6 +6628,13 @@
},
"BRAM_L_X30Y25": {
"bits": {
"BLOCK_RAM": {
"baseaddr": "0x00C00080",
"frames": 128,
"height": 10,
"offset": 51,
"words": 10
},
"CLB_IO_CLK": {
"baseaddr": "0x00400F00",
"frames": 28,
@ -6586,6 +6656,13 @@
},
"BRAM_L_X30Y30": {
"bits": {
"BLOCK_RAM": {
"baseaddr": "0x00C00080",
"frames": 128,
"height": 10,
"offset": 61,
"words": 10
},
"CLB_IO_CLK": {
"baseaddr": "0x00400F00",
"frames": 28,
@ -6607,6 +6684,13 @@
},
"BRAM_L_X30Y35": {
"bits": {
"BLOCK_RAM": {
"baseaddr": "0x00C00080",
"frames": 128,
"height": 10,
"offset": 71,
"words": 10
},
"CLB_IO_CLK": {
"baseaddr": "0x00400F00",
"frames": 28,
@ -6628,6 +6712,13 @@
},
"BRAM_L_X30Y40": {
"bits": {
"BLOCK_RAM": {
"baseaddr": "0x00C00080",
"frames": 128,
"height": 10,
"offset": 81,
"words": 10
},
"CLB_IO_CLK": {
"baseaddr": "0x00400F00",
"frames": 28,
@ -6649,6 +6740,13 @@
},
"BRAM_L_X30Y45": {
"bits": {
"BLOCK_RAM": {
"baseaddr": "0x00C00080",
"frames": 128,
"height": 10,
"offset": 91,
"words": 10
},
"CLB_IO_CLK": {
"baseaddr": "0x00400F00",
"frames": 28,
@ -6670,6 +6768,13 @@
},
"BRAM_L_X30Y5": {
"bits": {
"BLOCK_RAM": {
"baseaddr": "0x00C00080",
"frames": 128,
"height": 10,
"offset": 10,
"words": 10
},
"CLB_IO_CLK": {
"baseaddr": "0x00400F00",
"frames": 28,
@ -6691,6 +6796,13 @@
},
"BRAM_L_X30Y50": {
"bits": {
"BLOCK_RAM": {
"baseaddr": "0x00800080",
"frames": 128,
"height": 10,
"offset": 0,
"words": 10
},
"CLB_IO_CLK": {
"baseaddr": "0x00000F00",
"frames": 28,
@ -6712,6 +6824,13 @@
},
"BRAM_L_X30Y55": {
"bits": {
"BLOCK_RAM": {
"baseaddr": "0x00800080",
"frames": 128,
"height": 10,
"offset": 10,
"words": 10
},
"CLB_IO_CLK": {
"baseaddr": "0x00000F00",
"frames": 28,
@ -6733,6 +6852,13 @@
},
"BRAM_L_X30Y60": {
"bits": {
"BLOCK_RAM": {
"baseaddr": "0x00800080",
"frames": 128,
"height": 10,
"offset": 20,
"words": 10
},
"CLB_IO_CLK": {
"baseaddr": "0x00000F00",
"frames": 28,
@ -6754,6 +6880,13 @@
},
"BRAM_L_X30Y65": {
"bits": {
"BLOCK_RAM": {
"baseaddr": "0x00800080",
"frames": 128,
"height": 10,
"offset": 30,
"words": 10
},
"CLB_IO_CLK": {
"baseaddr": "0x00000F00",
"frames": 28,
@ -6775,6 +6908,13 @@
},
"BRAM_L_X30Y70": {
"bits": {
"BLOCK_RAM": {
"baseaddr": "0x00800080",
"frames": 128,
"height": 10,
"offset": 40,
"words": 10
},
"CLB_IO_CLK": {
"baseaddr": "0x00000F00",
"frames": 28,
@ -6796,6 +6936,13 @@
},
"BRAM_L_X30Y75": {
"bits": {
"BLOCK_RAM": {
"baseaddr": "0x00800080",
"frames": 128,
"height": 10,
"offset": 51,
"words": 10
},
"CLB_IO_CLK": {
"baseaddr": "0x00000F00",
"frames": 28,
@ -6817,6 +6964,13 @@
},
"BRAM_L_X30Y80": {
"bits": {
"BLOCK_RAM": {
"baseaddr": "0x00800080",
"frames": 128,
"height": 10,
"offset": 61,
"words": 10
},
"CLB_IO_CLK": {
"baseaddr": "0x00000F00",
"frames": 28,
@ -6838,6 +6992,13 @@
},
"BRAM_L_X30Y85": {
"bits": {
"BLOCK_RAM": {
"baseaddr": "0x00800080",
"frames": 128,
"height": 10,
"offset": 71,
"words": 10
},
"CLB_IO_CLK": {
"baseaddr": "0x00000F00",
"frames": 28,
@ -6859,6 +7020,13 @@
},
"BRAM_L_X30Y90": {
"bits": {
"BLOCK_RAM": {
"baseaddr": "0x00800080",
"frames": 128,
"height": 10,
"offset": 81,
"words": 10
},
"CLB_IO_CLK": {
"baseaddr": "0x00000F00",
"frames": 28,
@ -6880,6 +7048,13 @@
},
"BRAM_L_X30Y95": {
"bits": {
"BLOCK_RAM": {
"baseaddr": "0x00800080",
"frames": 128,
"height": 10,
"offset": 91,
"words": 10
},
"CLB_IO_CLK": {
"baseaddr": "0x00000F00",
"frames": 28,
@ -6901,6 +7076,13 @@
},
"BRAM_L_X6Y0": {
"bits": {
"BLOCK_RAM": {
"baseaddr": "0x00C00000",
"frames": 128,
"height": 10,
"offset": 0,
"words": 10
},
"CLB_IO_CLK": {
"baseaddr": "0x00400300",
"frames": 28,
@ -6922,6 +7104,13 @@
},
"BRAM_L_X6Y10": {
"bits": {
"BLOCK_RAM": {
"baseaddr": "0x00C00000",
"frames": 128,
"height": 10,
"offset": 20,
"words": 10
},
"CLB_IO_CLK": {
"baseaddr": "0x00400300",
"frames": 28,
@ -6943,6 +7132,13 @@
},
"BRAM_L_X6Y100": {
"bits": {
"BLOCK_RAM": {
"baseaddr": "0x00820000",
"frames": 128,
"height": 10,
"offset": 0,
"words": 10
},
"CLB_IO_CLK": {
"baseaddr": "0x00020300",
"frames": 28,
@ -6964,6 +7160,13 @@
},
"BRAM_L_X6Y105": {
"bits": {
"BLOCK_RAM": {
"baseaddr": "0x00820000",
"frames": 128,
"height": 10,
"offset": 10,
"words": 10
},
"CLB_IO_CLK": {
"baseaddr": "0x00020300",
"frames": 28,
@ -6985,6 +7188,13 @@
},
"BRAM_L_X6Y110": {
"bits": {
"BLOCK_RAM": {
"baseaddr": "0x00820000",
"frames": 128,
"height": 10,
"offset": 20,
"words": 10
},
"CLB_IO_CLK": {
"baseaddr": "0x00020300",
"frames": 28,
@ -7006,6 +7216,13 @@
},
"BRAM_L_X6Y115": {
"bits": {
"BLOCK_RAM": {
"baseaddr": "0x00820000",
"frames": 128,
"height": 10,
"offset": 30,
"words": 10
},
"CLB_IO_CLK": {
"baseaddr": "0x00020300",
"frames": 28,
@ -7027,6 +7244,13 @@
},
"BRAM_L_X6Y120": {
"bits": {
"BLOCK_RAM": {
"baseaddr": "0x00820000",
"frames": 128,
"height": 10,
"offset": 40,
"words": 10
},
"CLB_IO_CLK": {
"baseaddr": "0x00020300",
"frames": 28,
@ -7048,6 +7272,13 @@
},
"BRAM_L_X6Y125": {
"bits": {
"BLOCK_RAM": {
"baseaddr": "0x00820000",
"frames": 128,
"height": 10,
"offset": 51,
"words": 10
},
"CLB_IO_CLK": {
"baseaddr": "0x00020300",
"frames": 28,
@ -7069,6 +7300,13 @@
},
"BRAM_L_X6Y130": {
"bits": {
"BLOCK_RAM": {
"baseaddr": "0x00820000",
"frames": 128,
"height": 10,
"offset": 61,
"words": 10
},
"CLB_IO_CLK": {
"baseaddr": "0x00020300",
"frames": 28,
@ -7090,6 +7328,13 @@
},
"BRAM_L_X6Y135": {
"bits": {
"BLOCK_RAM": {
"baseaddr": "0x00820000",
"frames": 128,
"height": 10,
"offset": 71,
"words": 10
},
"CLB_IO_CLK": {
"baseaddr": "0x00020300",
"frames": 28,
@ -7111,6 +7356,13 @@
},
"BRAM_L_X6Y140": {
"bits": {
"BLOCK_RAM": {
"baseaddr": "0x00820000",
"frames": 128,
"height": 10,
"offset": 81,
"words": 10
},
"CLB_IO_CLK": {
"baseaddr": "0x00020300",
"frames": 28,
@ -7132,6 +7384,13 @@
},
"BRAM_L_X6Y145": {
"bits": {
"BLOCK_RAM": {
"baseaddr": "0x00820000",
"frames": 128,
"height": 10,
"offset": 91,
"words": 10
},
"CLB_IO_CLK": {
"baseaddr": "0x00020300",
"frames": 28,
@ -7153,6 +7412,13 @@
},
"BRAM_L_X6Y15": {
"bits": {
"BLOCK_RAM": {
"baseaddr": "0x00C00000",
"frames": 128,
"height": 10,
"offset": 30,
"words": 10
},
"CLB_IO_CLK": {
"baseaddr": "0x00400300",
"frames": 28,
@ -7174,6 +7440,13 @@
},
"BRAM_L_X6Y20": {
"bits": {
"BLOCK_RAM": {
"baseaddr": "0x00C00000",
"frames": 128,
"height": 10,
"offset": 40,
"words": 10
},
"CLB_IO_CLK": {
"baseaddr": "0x00400300",
"frames": 28,
@ -7195,6 +7468,13 @@
},
"BRAM_L_X6Y25": {
"bits": {
"BLOCK_RAM": {
"baseaddr": "0x00C00000",
"frames": 128,
"height": 10,
"offset": 51,
"words": 10
},
"CLB_IO_CLK": {
"baseaddr": "0x00400300",
"frames": 28,
@ -7216,6 +7496,13 @@
},
"BRAM_L_X6Y30": {
"bits": {
"BLOCK_RAM": {
"baseaddr": "0x00C00000",
"frames": 128,
"height": 10,
"offset": 61,
"words": 10
},
"CLB_IO_CLK": {
"baseaddr": "0x00400300",
"frames": 28,
@ -7237,6 +7524,13 @@
},
"BRAM_L_X6Y35": {
"bits": {
"BLOCK_RAM": {
"baseaddr": "0x00C00000",
"frames": 128,
"height": 10,
"offset": 71,
"words": 10
},
"CLB_IO_CLK": {
"baseaddr": "0x00400300",
"frames": 28,
@ -7258,6 +7552,13 @@
},
"BRAM_L_X6Y40": {
"bits": {
"BLOCK_RAM": {
"baseaddr": "0x00C00000",
"frames": 128,
"height": 10,
"offset": 81,
"words": 10
},
"CLB_IO_CLK": {
"baseaddr": "0x00400300",
"frames": 28,
@ -7279,6 +7580,13 @@
},
"BRAM_L_X6Y45": {
"bits": {
"BLOCK_RAM": {
"baseaddr": "0x00C00000",
"frames": 128,
"height": 10,
"offset": 91,
"words": 10
},
"CLB_IO_CLK": {
"baseaddr": "0x00400300",
"frames": 28,
@ -7300,6 +7608,13 @@
},
"BRAM_L_X6Y5": {
"bits": {
"BLOCK_RAM": {
"baseaddr": "0x00C00000",
"frames": 128,
"height": 10,
"offset": 10,
"words": 10
},
"CLB_IO_CLK": {
"baseaddr": "0x00400300",
"frames": 28,
@ -7321,6 +7636,13 @@
},
"BRAM_L_X6Y50": {
"bits": {
"BLOCK_RAM": {
"baseaddr": "0x00800000",
"frames": 128,
"height": 10,
"offset": 0,
"words": 10
},
"CLB_IO_CLK": {
"baseaddr": "0x00000300",
"frames": 28,
@ -7342,6 +7664,13 @@
},
"BRAM_L_X6Y55": {
"bits": {
"BLOCK_RAM": {
"baseaddr": "0x00800000",
"frames": 128,
"height": 10,
"offset": 10,
"words": 10
},
"CLB_IO_CLK": {
"baseaddr": "0x00000300",
"frames": 28,
@ -7363,6 +7692,13 @@
},
"BRAM_L_X6Y60": {
"bits": {
"BLOCK_RAM": {
"baseaddr": "0x00800000",
"frames": 128,
"height": 10,
"offset": 20,
"words": 10
},
"CLB_IO_CLK": {
"baseaddr": "0x00000300",
"frames": 28,
@ -7384,6 +7720,13 @@
},
"BRAM_L_X6Y65": {
"bits": {
"BLOCK_RAM": {
"baseaddr": "0x00800000",
"frames": 128,
"height": 10,
"offset": 30,
"words": 10
},
"CLB_IO_CLK": {
"baseaddr": "0x00000300",
"frames": 28,
@ -7405,6 +7748,13 @@
},
"BRAM_L_X6Y70": {
"bits": {
"BLOCK_RAM": {
"baseaddr": "0x00800000",
"frames": 128,
"height": 10,
"offset": 40,
"words": 10
},
"CLB_IO_CLK": {
"baseaddr": "0x00000300",
"frames": 28,
@ -7426,6 +7776,13 @@
},
"BRAM_L_X6Y75": {
"bits": {
"BLOCK_RAM": {
"baseaddr": "0x00800000",
"frames": 128,
"height": 10,
"offset": 51,
"words": 10
},
"CLB_IO_CLK": {
"baseaddr": "0x00000300",
"frames": 28,
@ -7447,6 +7804,13 @@
},
"BRAM_L_X6Y80": {
"bits": {
"BLOCK_RAM": {
"baseaddr": "0x00800000",
"frames": 128,
"height": 10,
"offset": 61,
"words": 10
},
"CLB_IO_CLK": {
"baseaddr": "0x00000300",
"frames": 28,
@ -7468,6 +7832,13 @@
},
"BRAM_L_X6Y85": {
"bits": {
"BLOCK_RAM": {
"baseaddr": "0x00800000",
"frames": 128,
"height": 10,
"offset": 71,
"words": 10
},
"CLB_IO_CLK": {
"baseaddr": "0x00000300",
"frames": 28,
@ -7489,6 +7860,13 @@
},
"BRAM_L_X6Y90": {
"bits": {
"BLOCK_RAM": {
"baseaddr": "0x00800000",
"frames": 128,
"height": 10,
"offset": 81,
"words": 10
},
"CLB_IO_CLK": {
"baseaddr": "0x00000300",
"frames": 28,
@ -7510,6 +7888,13 @@
},
"BRAM_L_X6Y95": {
"bits": {
"BLOCK_RAM": {
"baseaddr": "0x00800000",
"frames": 128,
"height": 10,
"offset": 91,
"words": 10
},
"CLB_IO_CLK": {
"baseaddr": "0x00000300",
"frames": 28,
@ -7531,6 +7916,13 @@
},
"BRAM_R_X37Y0": {
"bits": {
"BLOCK_RAM": {
"baseaddr": "0x00C00100",
"frames": 128,
"height": 10,
"offset": 0,
"words": 10
},
"CLB_IO_CLK": {
"baseaddr": "0x00401280",
"frames": 28,
@ -7552,6 +7944,13 @@
},
"BRAM_R_X37Y10": {
"bits": {
"BLOCK_RAM": {
"baseaddr": "0x00C00100",
"frames": 128,
"height": 10,
"offset": 20,
"words": 10
},
"CLB_IO_CLK": {
"baseaddr": "0x00401280",
"frames": 28,
@ -7573,6 +7972,13 @@
},
"BRAM_R_X37Y15": {
"bits": {
"BLOCK_RAM": {
"baseaddr": "0x00C00100",
"frames": 128,
"height": 10,
"offset": 30,
"words": 10
},
"CLB_IO_CLK": {
"baseaddr": "0x00401280",
"frames": 28,
@ -7594,6 +8000,13 @@
},
"BRAM_R_X37Y20": {
"bits": {
"BLOCK_RAM": {
"baseaddr": "0x00C00100",
"frames": 128,
"height": 10,
"offset": 40,
"words": 10
},
"CLB_IO_CLK": {
"baseaddr": "0x00401280",
"frames": 28,
@ -7615,6 +8028,13 @@
},
"BRAM_R_X37Y25": {
"bits": {
"BLOCK_RAM": {
"baseaddr": "0x00C00100",
"frames": 128,
"height": 10,
"offset": 51,
"words": 10
},
"CLB_IO_CLK": {
"baseaddr": "0x00401280",
"frames": 28,
@ -7636,6 +8056,13 @@
},
"BRAM_R_X37Y30": {
"bits": {
"BLOCK_RAM": {
"baseaddr": "0x00C00100",
"frames": 128,
"height": 10,
"offset": 61,
"words": 10
},
"CLB_IO_CLK": {
"baseaddr": "0x00401280",
"frames": 28,
@ -7657,6 +8084,13 @@
},
"BRAM_R_X37Y35": {
"bits": {
"BLOCK_RAM": {
"baseaddr": "0x00C00100",
"frames": 128,
"height": 10,
"offset": 71,
"words": 10
},
"CLB_IO_CLK": {
"baseaddr": "0x00401280",
"frames": 28,
@ -7678,6 +8112,13 @@
},
"BRAM_R_X37Y40": {
"bits": {
"BLOCK_RAM": {
"baseaddr": "0x00C00100",
"frames": 128,
"height": 10,
"offset": 81,
"words": 10
},
"CLB_IO_CLK": {
"baseaddr": "0x00401280",
"frames": 28,
@ -7699,6 +8140,13 @@
},
"BRAM_R_X37Y45": {
"bits": {
"BLOCK_RAM": {
"baseaddr": "0x00C00100",
"frames": 128,
"height": 10,
"offset": 91,
"words": 10
},
"CLB_IO_CLK": {
"baseaddr": "0x00401280",
"frames": 28,
@ -7720,6 +8168,13 @@
},
"BRAM_R_X37Y5": {
"bits": {
"BLOCK_RAM": {
"baseaddr": "0x00C00100",
"frames": 128,
"height": 10,
"offset": 10,
"words": 10
},
"CLB_IO_CLK": {
"baseaddr": "0x00401280",
"frames": 28,
@ -7741,6 +8196,13 @@
},
"BRAM_R_X37Y50": {
"bits": {
"BLOCK_RAM": {
"baseaddr": "0x00800100",
"frames": 128,
"height": 10,
"offset": 0,
"words": 10
},
"CLB_IO_CLK": {
"baseaddr": "0x00001280",
"frames": 28,
@ -7762,6 +8224,13 @@
},
"BRAM_R_X37Y55": {
"bits": {
"BLOCK_RAM": {
"baseaddr": "0x00800100",
"frames": 128,
"height": 10,
"offset": 10,
"words": 10
},
"CLB_IO_CLK": {
"baseaddr": "0x00001280",
"frames": 28,
@ -7783,6 +8252,13 @@
},
"BRAM_R_X37Y60": {
"bits": {
"BLOCK_RAM": {
"baseaddr": "0x00800100",
"frames": 128,
"height": 10,
"offset": 20,
"words": 10
},
"CLB_IO_CLK": {
"baseaddr": "0x00001280",
"frames": 28,
@ -7804,6 +8280,13 @@
},
"BRAM_R_X37Y65": {
"bits": {
"BLOCK_RAM": {
"baseaddr": "0x00800100",
"frames": 128,
"height": 10,
"offset": 30,
"words": 10
},
"CLB_IO_CLK": {
"baseaddr": "0x00001280",
"frames": 28,
@ -7825,6 +8308,13 @@
},
"BRAM_R_X37Y70": {
"bits": {
"BLOCK_RAM": {
"baseaddr": "0x00800100",
"frames": 128,
"height": 10,
"offset": 40,
"words": 10
},
"CLB_IO_CLK": {
"baseaddr": "0x00001280",
"frames": 28,
@ -7846,6 +8336,13 @@
},
"BRAM_R_X37Y75": {
"bits": {
"BLOCK_RAM": {
"baseaddr": "0x00800100",
"frames": 128,
"height": 10,
"offset": 51,
"words": 10
},
"CLB_IO_CLK": {
"baseaddr": "0x00001280",
"frames": 28,
@ -7867,6 +8364,13 @@
},
"BRAM_R_X37Y80": {
"bits": {
"BLOCK_RAM": {
"baseaddr": "0x00800100",
"frames": 128,
"height": 10,
"offset": 61,
"words": 10
},
"CLB_IO_CLK": {
"baseaddr": "0x00001280",
"frames": 28,
@ -7888,6 +8392,13 @@
},
"BRAM_R_X37Y85": {
"bits": {
"BLOCK_RAM": {
"baseaddr": "0x00800100",
"frames": 128,
"height": 10,
"offset": 71,
"words": 10
},
"CLB_IO_CLK": {
"baseaddr": "0x00001280",
"frames": 28,
@ -7909,6 +8420,13 @@
},
"BRAM_R_X37Y90": {
"bits": {
"BLOCK_RAM": {
"baseaddr": "0x00800100",
"frames": 128,
"height": 10,
"offset": 81,
"words": 10
},
"CLB_IO_CLK": {
"baseaddr": "0x00001280",
"frames": 28,
@ -7930,6 +8448,13 @@
},
"BRAM_R_X37Y95": {
"bits": {
"BLOCK_RAM": {
"baseaddr": "0x00800100",
"frames": 128,
"height": 10,
"offset": 91,
"words": 10
},
"CLB_IO_CLK": {
"baseaddr": "0x00001280",
"frames": 28,