From 6c02fde2635b0d54397761359375fc8119ef04cf Mon Sep 17 00:00:00 2001 From: regymm <31496626+regymm@users.noreply.github.com> Date: Thu, 23 Apr 2026 22:38:24 +0900 Subject: [PATCH] Added Kintex 7 PCIe segbits/tilegrid and GTX bit fixes --- kintex7/mask_pcie_bot.db | 1711 +++++++ kintex7/segbits_gtx_channel_0.db | 5 +- kintex7/segbits_gtx_channel_1.db | 5 +- kintex7/segbits_gtx_channel_2.db | 5 +- kintex7/segbits_gtx_channel_3.db | 5 +- kintex7/segbits_pcie_bot.db | 1711 +++++++ kintex7/segbits_pcie_bot.origin_info.db | 1711 +++++++ kintex7/segbits_pcie_int_interface_l.db | 27 + ...egbits_pcie_int_interface_l.origin_info.db | 27 + kintex7/segbits_pcie_int_interface_r.db | 34 + ...egbits_pcie_int_interface_r.origin_info.db | 34 + kintex7/xc7k160t/tilegrid.json | 459 +- kintex7/xc7k325t/tilegrid.json | 468 +- kintex7/xc7k480t/tilegrid.json | 4419 +++++++++++++++-- kintex7/xc7k70t/tilegrid.json | 459 +- 15 files changed, 10424 insertions(+), 656 deletions(-) create mode 100644 kintex7/mask_pcie_bot.db create mode 100644 kintex7/segbits_pcie_bot.db create mode 100644 kintex7/segbits_pcie_bot.origin_info.db create mode 100644 kintex7/segbits_pcie_int_interface_l.db create mode 100644 kintex7/segbits_pcie_int_interface_l.origin_info.db create mode 100644 kintex7/segbits_pcie_int_interface_r.db create mode 100644 kintex7/segbits_pcie_int_interface_r.origin_info.db diff --git a/kintex7/mask_pcie_bot.db b/kintex7/mask_pcie_bot.db new file mode 100644 index 0000000..53e4ba4 --- /dev/null +++ b/kintex7/mask_pcie_bot.db @@ -0,0 +1,1711 @@ +bit 28_00 +bit 28_08 +bit 28_09 +bit 28_10 +bit 28_11 +bit 28_12 +bit 28_13 +bit 28_14 +bit 28_15 +bit 28_16 +bit 28_17 +bit 28_18 +bit 28_24 +bit 28_25 +bit 28_26 +bit 28_27 +bit 28_28 +bit 28_29 +bit 28_32 +bit 28_33 +bit 28_34 +bit 28_35 +bit 28_36 +bit 28_37 +bit 28_38 +bit 28_40 +bit 28_41 +bit 28_42 +bit 28_43 +bit 28_44 +bit 28_45 +bit 28_46 +bit 28_47 +bit 28_64 +bit 28_65 +bit 28_66 +bit 28_67 +bit 28_68 +bit 28_72 +bit 28_73 +bit 28_74 +bit 28_75 +bit 28_76 +bit 28_77 +bit 28_78 +bit 28_79 +bit 28_80 +bit 28_81 +bit 28_82 +bit 28_83 +bit 28_84 +bit 28_85 +bit 28_86 +bit 28_87 +bit 28_88 +bit 28_89 +bit 28_90 +bit 28_91 +bit 28_92 +bit 28_93 +bit 28_94 +bit 28_95 +bit 28_96 +bit 28_97 +bit 28_98 +bit 28_99 +bit 28_100 +bit 28_101 +bit 28_102 +bit 28_103 +bit 28_104 +bit 28_105 +bit 28_106 +bit 28_107 +bit 28_108 +bit 28_109 +bit 28_110 +bit 28_111 +bit 28_128 +bit 28_129 +bit 28_130 +bit 28_131 +bit 28_132 +bit 28_133 +bit 28_134 +bit 28_135 +bit 28_136 +bit 28_137 +bit 28_138 +bit 28_139 +bit 28_140 +bit 28_141 +bit 28_142 +bit 28_143 +bit 28_144 +bit 28_145 +bit 28_146 +bit 28_147 +bit 28_148 +bit 28_149 +bit 28_150 +bit 28_151 +bit 28_152 +bit 28_153 +bit 28_154 +bit 28_155 +bit 28_156 +bit 28_157 +bit 28_158 +bit 28_159 +bit 28_160 +bit 28_161 +bit 28_162 +bit 28_163 +bit 28_164 +bit 28_165 +bit 28_166 +bit 28_167 +bit 28_168 +bit 28_169 +bit 28_170 +bit 28_171 +bit 28_172 +bit 28_173 +bit 28_174 +bit 28_175 +bit 28_192 +bit 28_193 +bit 28_194 +bit 28_195 +bit 28_196 +bit 28_197 +bit 28_198 +bit 28_199 +bit 28_200 +bit 28_201 +bit 28_202 +bit 28_203 +bit 28_204 +bit 28_205 +bit 28_206 +bit 28_207 +bit 28_208 +bit 28_209 +bit 28_210 +bit 28_211 +bit 28_212 +bit 28_213 +bit 28_214 +bit 28_215 +bit 28_216 +bit 28_217 +bit 28_218 +bit 28_219 +bit 28_224 +bit 28_225 +bit 28_226 +bit 28_227 +bit 28_228 +bit 28_229 +bit 28_230 +bit 28_231 +bit 28_232 +bit 28_233 +bit 28_234 +bit 28_235 +bit 28_236 +bit 28_237 +bit 28_238 +bit 28_239 +bit 28_256 +bit 28_257 +bit 28_258 +bit 28_259 +bit 28_260 +bit 28_261 +bit 28_262 +bit 28_263 +bit 28_264 +bit 28_265 +bit 28_266 +bit 28_267 +bit 28_268 +bit 28_269 +bit 28_270 +bit 28_271 +bit 28_272 +bit 28_273 +bit 28_274 +bit 28_275 +bit 28_276 +bit 28_277 +bit 28_278 +bit 28_280 +bit 28_281 +bit 28_282 +bit 28_283 +bit 28_284 +bit 28_285 +bit 28_286 +bit 28_288 +bit 28_289 +bit 28_290 +bit 28_291 +bit 28_292 +bit 28_296 +bit 28_297 +bit 28_298 +bit 28_299 +bit 28_300 +bit 28_301 +bit 28_320 +bit 28_321 +bit 28_322 +bit 28_323 +bit 28_324 +bit 28_325 +bit 28_326 +bit 28_327 +bit 28_328 +bit 28_329 +bit 28_330 +bit 28_331 +bit 28_332 +bit 28_333 +bit 28_334 +bit 28_336 +bit 28_337 +bit 28_338 +bit 28_339 +bit 28_340 +bit 28_344 +bit 28_345 +bit 28_346 +bit 28_347 +bit 28_348 +bit 28_352 +bit 28_353 +bit 28_354 +bit 28_355 +bit 28_356 +bit 28_357 +bit 28_358 +bit 28_359 +bit 28_360 +bit 28_361 +bit 28_362 +bit 28_363 +bit 28_364 +bit 28_365 +bit 28_366 +bit 28_367 +bit 28_384 +bit 28_385 +bit 28_386 +bit 28_387 +bit 28_388 +bit 28_389 +bit 28_390 +bit 28_391 +bit 28_392 +bit 28_393 +bit 28_394 +bit 28_395 +bit 28_396 +bit 28_397 +bit 28_398 +bit 28_399 +bit 28_400 +bit 28_401 +bit 28_402 +bit 28_403 +bit 28_404 +bit 28_408 +bit 28_409 +bit 28_410 +bit 28_411 +bit 28_412 +bit 28_416 +bit 28_417 +bit 28_418 +bit 28_419 +bit 28_420 +bit 28_421 +bit 28_424 +bit 28_425 +bit 28_426 +bit 28_427 +bit 28_428 +bit 28_448 +bit 28_449 +bit 28_450 +bit 28_451 +bit 28_452 +bit 28_453 +bit 28_454 +bit 28_455 +bit 28_456 +bit 28_457 +bit 28_458 +bit 28_459 +bit 28_460 +bit 28_461 +bit 28_464 +bit 28_465 +bit 28_466 +bit 28_467 +bit 28_468 +bit 28_469 +bit 28_470 +bit 28_471 +bit 28_472 +bit 28_473 +bit 28_474 +bit 28_475 +bit 28_476 +bit 28_477 +bit 28_478 +bit 28_479 +bit 28_480 +bit 28_481 +bit 28_482 +bit 28_483 +bit 28_484 +bit 28_485 +bit 28_486 +bit 28_487 +bit 28_488 +bit 28_489 +bit 28_490 +bit 28_491 +bit 28_492 +bit 28_493 +bit 28_494 +bit 28_512 +bit 28_513 +bit 28_514 +bit 28_515 +bit 28_516 +bit 28_517 +bit 28_520 +bit 28_521 +bit 28_522 +bit 28_523 +bit 28_524 +bit 28_525 +bit 28_526 +bit 28_527 +bit 28_528 +bit 28_529 +bit 28_530 +bit 28_531 +bit 28_532 +bit 28_533 +bit 28_534 +bit 28_535 +bit 28_536 +bit 28_537 +bit 28_538 +bit 28_539 +bit 28_540 +bit 28_541 +bit 28_542 +bit 28_543 +bit 28_544 +bit 28_545 +bit 28_546 +bit 28_547 +bit 28_548 +bit 28_549 +bit 28_550 +bit 28_552 +bit 28_553 +bit 28_554 +bit 28_555 +bit 28_556 +bit 28_557 +bit 28_558 +bit 28_559 +bit 28_576 +bit 28_577 +bit 28_578 +bit 28_579 +bit 28_580 +bit 28_581 +bit 28_582 +bit 28_583 +bit 28_584 +bit 28_585 +bit 28_586 +bit 28_587 +bit 28_588 +bit 28_589 +bit 28_590 +bit 28_592 +bit 28_593 +bit 28_594 +bit 28_595 +bit 28_596 +bit 28_597 +bit 28_598 +bit 28_599 +bit 28_600 +bit 28_601 +bit 28_602 +bit 28_603 +bit 28_604 +bit 28_605 +bit 28_606 +bit 28_607 +bit 28_608 +bit 28_609 +bit 28_610 +bit 28_611 +bit 28_612 +bit 28_613 +bit 28_614 +bit 28_615 +bit 28_616 +bit 28_617 +bit 28_618 +bit 28_619 +bit 28_640 +bit 28_641 +bit 28_642 +bit 28_643 +bit 28_644 +bit 28_645 +bit 28_648 +bit 28_649 +bit 28_650 +bit 28_651 +bit 28_652 +bit 28_653 +bit 28_654 +bit 28_656 +bit 28_657 +bit 28_658 +bit 28_659 +bit 28_660 +bit 28_661 +bit 28_662 +bit 28_663 +bit 28_664 +bit 28_665 +bit 28_666 +bit 28_667 +bit 28_672 +bit 28_673 +bit 28_674 +bit 28_675 +bit 28_676 +bit 28_677 +bit 28_678 +bit 28_679 +bit 28_680 +bit 28_681 +bit 28_682 +bit 28_683 +bit 28_684 +bit 28_685 +bit 28_686 +bit 28_687 +bit 28_704 +bit 28_705 +bit 28_706 +bit 28_707 +bit 28_708 +bit 28_709 +bit 28_710 +bit 28_711 +bit 28_712 +bit 28_713 +bit 28_714 +bit 28_715 +bit 28_716 +bit 28_717 +bit 28_718 +bit 28_719 +bit 28_720 +bit 28_721 +bit 28_722 +bit 28_723 +bit 28_724 +bit 28_725 +bit 28_726 +bit 28_727 +bit 28_728 +bit 28_729 +bit 28_730 +bit 28_731 +bit 28_732 +bit 28_733 +bit 28_734 +bit 28_735 +bit 28_736 +bit 28_737 +bit 28_738 +bit 28_739 +bit 28_740 +bit 28_741 +bit 28_742 +bit 28_743 +bit 28_744 +bit 28_745 +bit 28_746 +bit 28_747 +bit 28_748 +bit 28_749 +bit 28_750 +bit 28_751 +bit 28_768 +bit 28_769 +bit 28_770 +bit 28_771 +bit 28_772 +bit 28_773 +bit 28_774 +bit 28_775 +bit 28_776 +bit 28_777 +bit 28_778 +bit 28_779 +bit 28_780 +bit 28_781 +bit 28_782 +bit 28_783 +bit 28_784 +bit 28_785 +bit 28_786 +bit 28_787 +bit 28_788 +bit 28_789 +bit 28_790 +bit 28_791 +bit 28_792 +bit 28_793 +bit 28_794 +bit 28_795 +bit 28_796 +bit 28_797 +bit 28_798 +bit 28_799 +bit 28_800 +bit 28_801 +bit 28_802 +bit 28_803 +bit 28_804 +bit 28_805 +bit 28_806 +bit 28_807 +bit 28_808 +bit 28_809 +bit 28_810 +bit 28_811 +bit 28_812 +bit 28_813 +bit 28_814 +bit 28_832 +bit 28_833 +bit 28_834 +bit 28_835 +bit 28_836 +bit 28_837 +bit 28_838 +bit 28_839 +bit 28_840 +bit 28_841 +bit 28_842 +bit 28_843 +bit 28_844 +bit 28_845 +bit 28_846 +bit 28_848 +bit 28_849 +bit 28_850 +bit 28_851 +bit 28_852 +bit 28_853 +bit 28_854 +bit 28_855 +bit 28_856 +bit 28_857 +bit 28_858 +bit 28_859 +bit 28_860 +bit 28_861 +bit 28_864 +bit 28_865 +bit 28_866 +bit 28_867 +bit 28_868 +bit 28_869 +bit 28_872 +bit 28_873 +bit 28_874 +bit 28_875 +bit 28_876 +bit 28_877 +bit 28_878 +bit 28_896 +bit 28_897 +bit 28_898 +bit 28_899 +bit 28_900 +bit 28_901 +bit 28_902 +bit 28_903 +bit 28_904 +bit 28_905 +bit 28_906 +bit 28_907 +bit 28_908 +bit 28_909 +bit 28_910 +bit 28_912 +bit 28_913 +bit 28_914 +bit 28_915 +bit 28_916 +bit 28_917 +bit 28_918 +bit 28_919 +bit 28_920 +bit 28_921 +bit 28_922 +bit 28_923 +bit 28_924 +bit 28_925 +bit 28_926 +bit 28_927 +bit 28_928 +bit 28_929 +bit 28_930 +bit 28_931 +bit 28_932 +bit 28_933 +bit 28_934 +bit 28_935 +bit 28_936 +bit 28_937 +bit 28_938 +bit 28_939 +bit 28_940 +bit 28_941 +bit 28_942 +bit 28_960 +bit 28_961 +bit 28_962 +bit 28_963 +bit 28_964 +bit 28_965 +bit 28_966 +bit 28_968 +bit 28_969 +bit 28_970 +bit 28_971 +bit 28_972 +bit 28_973 +bit 28_974 +bit 28_975 +bit 28_976 +bit 28_984 +bit 28_985 +bit 28_986 +bit 28_987 +bit 28_988 +bit 28_989 +bit 28_990 +bit 28_991 +bit 28_992 +bit 28_1000 +bit 28_1001 +bit 28_1002 +bit 28_1003 +bit 28_1004 +bit 28_1005 +bit 28_1006 +bit 28_1007 +bit 28_1024 +bit 28_1025 +bit 28_1026 +bit 28_1027 +bit 28_1028 +bit 28_1029 +bit 28_1032 +bit 28_1033 +bit 28_1034 +bit 28_1035 +bit 28_1036 +bit 28_1037 +bit 28_1040 +bit 28_1041 +bit 28_1042 +bit 28_1043 +bit 28_1044 +bit 28_1045 +bit 28_1046 +bit 28_1047 +bit 28_1048 +bit 28_1049 +bit 28_1050 +bit 28_1051 +bit 28_1052 +bit 28_1053 +bit 28_1054 +bit 28_1055 +bit 28_1056 +bit 28_1057 +bit 28_1058 +bit 28_1059 +bit 28_1060 +bit 28_1061 +bit 28_1062 +bit 28_1063 +bit 28_1064 +bit 28_1065 +bit 28_1066 +bit 28_1067 +bit 28_1068 +bit 28_1069 +bit 28_1070 +bit 28_1071 +bit 28_1088 +bit 28_1089 +bit 28_1090 +bit 28_1091 +bit 28_1092 +bit 28_1093 +bit 28_1094 +bit 28_1095 +bit 28_1096 +bit 28_1097 +bit 28_1098 +bit 28_1104 +bit 28_1105 +bit 28_1106 +bit 28_1107 +bit 28_1108 +bit 28_1109 +bit 28_1110 +bit 28_1112 +bit 28_1113 +bit 28_1114 +bit 28_1115 +bit 28_1116 +bit 28_1117 +bit 28_1120 +bit 28_1121 +bit 28_1122 +bit 28_1123 +bit 28_1124 +bit 28_1125 +bit 28_1126 +bit 28_1128 +bit 28_1129 +bit 28_1130 +bit 28_1131 +bit 28_1132 +bit 28_1133 +bit 28_1152 +bit 28_1153 +bit 28_1154 +bit 28_1155 +bit 28_1156 +bit 28_1157 +bit 28_1160 +bit 28_1161 +bit 28_1162 +bit 28_1163 +bit 28_1164 +bit 28_1165 +bit 28_1166 +bit 28_1167 +bit 28_1168 +bit 28_1169 +bit 28_1170 +bit 28_1171 +bit 28_1172 +bit 28_1173 +bit 28_1174 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29_236 +bit 29_237 +bit 29_238 +bit 29_239 +bit 29_256 +bit 29_257 +bit 29_258 +bit 29_259 +bit 29_260 +bit 29_261 +bit 29_262 +bit 29_263 +bit 29_264 +bit 29_265 +bit 29_266 +bit 29_267 +bit 29_268 +bit 29_269 +bit 29_270 +bit 29_271 +bit 29_272 +bit 29_273 +bit 29_274 +bit 29_275 +bit 29_276 +bit 29_277 +bit 29_278 +bit 29_280 +bit 29_281 +bit 29_282 +bit 29_283 +bit 29_284 +bit 29_285 +bit 29_286 +bit 29_288 +bit 29_289 +bit 29_290 +bit 29_291 +bit 29_292 +bit 29_296 +bit 29_297 +bit 29_298 +bit 29_299 +bit 29_300 +bit 29_301 +bit 29_320 +bit 29_321 +bit 29_322 +bit 29_323 +bit 29_324 +bit 29_325 +bit 29_326 +bit 29_327 +bit 29_328 +bit 29_329 +bit 29_330 +bit 29_331 +bit 29_332 +bit 29_333 +bit 29_336 +bit 29_337 +bit 29_338 +bit 29_339 +bit 29_340 +bit 29_344 +bit 29_345 +bit 29_346 +bit 29_347 +bit 29_348 +bit 29_352 +bit 29_353 +bit 29_354 +bit 29_355 +bit 29_356 +bit 29_357 +bit 29_358 +bit 29_359 +bit 29_360 +bit 29_361 +bit 29_362 +bit 29_363 +bit 29_364 +bit 29_365 +bit 29_366 +bit 29_367 +bit 29_384 +bit 29_385 +bit 29_386 +bit 29_387 +bit 29_388 +bit 29_389 +bit 29_390 +bit 29_392 +bit 29_393 +bit 29_394 +bit 29_395 +bit 29_396 +bit 29_397 +bit 29_398 +bit 29_399 +bit 29_400 +bit 29_401 +bit 29_402 +bit 29_403 +bit 29_404 +bit 29_408 +bit 29_409 +bit 29_410 +bit 29_411 +bit 29_416 +bit 29_417 +bit 29_418 +bit 29_419 +bit 29_420 +bit 29_421 +bit 29_424 +bit 29_425 +bit 29_426 +bit 29_427 +bit 29_428 +bit 29_448 +bit 29_449 +bit 29_450 +bit 29_451 +bit 29_452 +bit 29_453 +bit 29_454 +bit 29_455 +bit 29_456 +bit 29_457 +bit 29_458 +bit 29_459 +bit 29_460 +bit 29_461 +bit 29_464 +bit 29_465 +bit 29_466 +bit 29_467 +bit 29_468 +bit 29_469 +bit 29_470 +bit 29_471 +bit 29_472 +bit 29_473 +bit 29_474 +bit 29_475 +bit 29_476 +bit 29_477 +bit 29_478 +bit 29_479 +bit 29_480 +bit 29_481 +bit 29_482 +bit 29_483 +bit 29_484 +bit 29_485 +bit 29_486 +bit 29_487 +bit 29_488 +bit 29_489 +bit 29_490 +bit 29_491 +bit 29_492 +bit 29_493 +bit 29_512 +bit 29_513 +bit 29_514 +bit 29_515 +bit 29_516 +bit 29_520 +bit 29_521 +bit 29_522 +bit 29_523 +bit 29_524 +bit 29_525 +bit 29_526 +bit 29_527 +bit 29_528 +bit 29_529 +bit 29_530 +bit 29_531 +bit 29_532 +bit 29_533 +bit 29_534 +bit 29_535 +bit 29_536 +bit 29_537 +bit 29_538 +bit 29_539 +bit 29_540 +bit 29_541 +bit 29_542 +bit 29_543 +bit 29_544 +bit 29_545 +bit 29_546 +bit 29_547 +bit 29_548 +bit 29_549 +bit 29_550 +bit 29_552 +bit 29_553 +bit 29_554 +bit 29_555 +bit 29_556 +bit 29_557 +bit 29_558 +bit 29_559 +bit 29_576 +bit 29_577 +bit 29_578 +bit 29_579 +bit 29_580 +bit 29_581 +bit 29_582 +bit 29_583 +bit 29_584 +bit 29_585 +bit 29_586 +bit 29_587 +bit 29_588 +bit 29_589 +bit 29_590 +bit 29_592 +bit 29_593 +bit 29_594 +bit 29_595 +bit 29_596 +bit 29_597 +bit 29_598 +bit 29_599 +bit 29_600 +bit 29_601 +bit 29_602 +bit 29_603 +bit 29_604 +bit 29_605 +bit 29_606 +bit 29_607 +bit 29_608 +bit 29_609 +bit 29_610 +bit 29_611 +bit 29_612 +bit 29_613 +bit 29_614 +bit 29_615 +bit 29_616 +bit 29_617 +bit 29_618 +bit 29_619 +bit 29_640 +bit 29_641 +bit 29_642 +bit 29_643 +bit 29_644 +bit 29_645 +bit 29_648 +bit 29_649 +bit 29_650 +bit 29_651 +bit 29_652 +bit 29_653 +bit 29_656 +bit 29_657 +bit 29_658 +bit 29_659 +bit 29_660 +bit 29_661 +bit 29_662 +bit 29_663 +bit 29_664 +bit 29_665 +bit 29_666 +bit 29_672 +bit 29_673 +bit 29_674 +bit 29_675 +bit 29_676 +bit 29_677 +bit 29_678 +bit 29_679 +bit 29_680 +bit 29_681 +bit 29_682 +bit 29_683 +bit 29_684 +bit 29_685 +bit 29_686 +bit 29_687 +bit 29_704 +bit 29_705 +bit 29_706 +bit 29_707 +bit 29_708 +bit 29_709 +bit 29_710 +bit 29_711 +bit 29_712 +bit 29_713 +bit 29_714 +bit 29_715 +bit 29_716 +bit 29_717 +bit 29_718 +bit 29_719 +bit 29_720 +bit 29_721 +bit 29_722 +bit 29_723 +bit 29_724 +bit 29_725 +bit 29_726 +bit 29_727 +bit 29_728 +bit 29_729 +bit 29_730 +bit 29_731 +bit 29_732 +bit 29_733 +bit 29_734 +bit 29_735 +bit 29_736 +bit 29_737 +bit 29_738 +bit 29_739 +bit 29_740 +bit 29_741 +bit 29_742 +bit 29_743 +bit 29_744 +bit 29_745 +bit 29_746 +bit 29_747 +bit 29_748 +bit 29_749 +bit 29_750 +bit 29_751 +bit 29_768 +bit 29_769 +bit 29_770 +bit 29_771 +bit 29_772 +bit 29_773 +bit 29_774 +bit 29_775 +bit 29_776 +bit 29_777 +bit 29_778 +bit 29_779 +bit 29_780 +bit 29_781 +bit 29_782 +bit 29_783 +bit 29_784 +bit 29_785 +bit 29_786 +bit 29_787 +bit 29_788 +bit 29_789 +bit 29_790 +bit 29_791 +bit 29_792 +bit 29_793 +bit 29_794 +bit 29_795 +bit 29_796 +bit 29_797 +bit 29_798 +bit 29_799 +bit 29_800 +bit 29_801 +bit 29_802 +bit 29_803 +bit 29_804 +bit 29_805 +bit 29_806 +bit 29_808 +bit 29_809 +bit 29_810 +bit 29_811 +bit 29_812 +bit 29_813 +bit 29_832 +bit 29_833 +bit 29_834 +bit 29_835 +bit 29_836 +bit 29_837 +bit 29_838 +bit 29_840 +bit 29_841 +bit 29_842 +bit 29_843 +bit 29_844 +bit 29_845 +bit 29_846 +bit 29_848 +bit 29_849 +bit 29_850 +bit 29_851 +bit 29_852 +bit 29_853 +bit 29_854 +bit 29_856 +bit 29_857 +bit 29_858 +bit 29_859 +bit 29_860 +bit 29_864 +bit 29_865 +bit 29_866 +bit 29_867 +bit 29_868 +bit 29_869 +bit 29_872 +bit 29_873 +bit 29_874 +bit 29_875 +bit 29_876 +bit 29_877 +bit 29_896 +bit 29_897 +bit 29_898 +bit 29_899 +bit 29_900 +bit 29_901 +bit 29_902 +bit 29_903 +bit 29_904 +bit 29_905 +bit 29_906 +bit 29_907 +bit 29_908 +bit 29_909 +bit 29_912 +bit 29_913 +bit 29_914 +bit 29_915 +bit 29_916 +bit 29_917 +bit 29_918 +bit 29_919 +bit 29_920 +bit 29_921 +bit 29_922 +bit 29_923 +bit 29_924 +bit 29_925 +bit 29_926 +bit 29_927 +bit 29_928 +bit 29_929 +bit 29_930 +bit 29_931 +bit 29_932 +bit 29_933 +bit 29_934 +bit 29_935 +bit 29_936 +bit 29_937 +bit 29_938 +bit 29_939 +bit 29_940 +bit 29_941 +bit 29_942 +bit 29_960 +bit 29_961 +bit 29_962 +bit 29_963 +bit 29_964 +bit 29_965 +bit 29_966 +bit 29_968 +bit 29_969 +bit 29_970 +bit 29_971 +bit 29_972 +bit 29_973 +bit 29_974 +bit 29_975 +bit 29_976 +bit 29_984 +bit 29_985 +bit 29_986 +bit 29_987 +bit 29_988 +bit 29_989 +bit 29_990 +bit 29_991 +bit 29_992 +bit 29_1000 +bit 29_1001 +bit 29_1002 +bit 29_1003 +bit 29_1004 +bit 29_1005 +bit 29_1006 +bit 29_1007 +bit 29_1024 +bit 29_1025 +bit 29_1026 +bit 29_1027 +bit 29_1028 +bit 29_1032 +bit 29_1033 +bit 29_1034 +bit 29_1035 +bit 29_1036 +bit 29_1037 +bit 29_1040 +bit 29_1041 +bit 29_1042 +bit 29_1043 +bit 29_1044 +bit 29_1045 +bit 29_1046 +bit 29_1047 +bit 29_1048 +bit 29_1049 +bit 29_1050 +bit 29_1051 +bit 29_1052 +bit 29_1053 +bit 29_1054 +bit 29_1055 +bit 29_1056 +bit 29_1057 +bit 29_1058 +bit 29_1059 +bit 29_1060 +bit 29_1061 +bit 29_1062 +bit 29_1063 +bit 29_1064 +bit 29_1065 +bit 29_1066 +bit 29_1067 +bit 29_1068 +bit 29_1069 +bit 29_1070 +bit 29_1071 +bit 29_1088 +bit 29_1089 +bit 29_1090 +bit 29_1091 +bit 29_1092 +bit 29_1093 +bit 29_1094 +bit 29_1095 +bit 29_1096 +bit 29_1097 +bit 29_1098 +bit 29_1104 +bit 29_1105 +bit 29_1106 +bit 29_1107 +bit 29_1108 +bit 29_1109 +bit 29_1112 +bit 29_1113 +bit 29_1114 +bit 29_1115 +bit 29_1116 +bit 29_1120 +bit 29_1121 +bit 29_1122 +bit 29_1123 +bit 29_1124 +bit 29_1125 +bit 29_1126 +bit 29_1128 +bit 29_1129 +bit 29_1130 +bit 29_1131 +bit 29_1132 +bit 29_1152 +bit 29_1153 +bit 29_1154 +bit 29_1155 +bit 29_1156 +bit 29_1160 +bit 29_1161 +bit 29_1162 +bit 29_1163 +bit 29_1164 +bit 29_1165 +bit 29_1166 +bit 29_1167 +bit 29_1168 +bit 29_1169 +bit 29_1170 +bit 29_1171 +bit 29_1172 +bit 29_1173 +bit 29_1174 +bit 29_1175 +bit 29_1176 +bit 29_1177 +bit 29_1178 +bit 29_1179 +bit 29_1180 +bit 29_1184 +bit 29_1185 +bit 29_1186 +bit 29_1187 +bit 29_1188 +bit 29_1189 +bit 29_1190 +bit 29_1191 +bit 29_1192 +bit 29_1193 +bit 29_1194 +bit 29_1195 +bit 29_1196 +bit 29_1197 +bit 29_1198 +bit 29_1199 +bit 29_1216 +bit 29_1217 +bit 29_1218 +bit 29_1219 +bit 29_1220 +bit 29_1221 +bit 29_1222 +bit 29_1223 +bit 29_1224 +bit 29_1225 +bit 29_1226 +bit 29_1227 +bit 29_1228 +bit 29_1229 +bit 29_1230 +bit 29_1231 +bit 29_1232 +bit 29_1233 +bit 29_1234 +bit 29_1235 +bit 29_1236 +bit 29_1237 +bit 29_1238 +bit 29_1239 +bit 29_1240 +bit 29_1241 +bit 29_1242 +bit 29_1243 +bit 29_1244 +bit 29_1245 +bit 29_1246 +bit 29_1247 +bit 29_1248 +bit 29_1249 +bit 29_1250 +bit 29_1251 +bit 29_1252 +bit 29_1253 +bit 29_1254 +bit 29_1255 +bit 29_1256 +bit 29_1257 +bit 29_1258 +bit 29_1259 +bit 29_1260 +bit 29_1261 +bit 29_1262 +bit 29_1263 +bit 29_1280 +bit 29_1281 +bit 29_1282 +bit 29_1283 +bit 29_1284 +bit 29_1285 +bit 29_1286 +bit 29_1287 +bit 29_1288 +bit 29_1289 +bit 29_1290 +bit 29_1291 +bit 29_1292 +bit 29_1293 +bit 29_1294 +bit 29_1295 diff --git a/kintex7/segbits_gtx_channel_0.db b/kintex7/segbits_gtx_channel_0.db index 1d2cccd..ba07091 100644 --- a/kintex7/segbits_gtx_channel_0.db +++ b/kintex7/segbits_gtx_channel_0.db @@ -640,13 +640,16 @@ GTX_CHANNEL_0.GTXE2_CHANNEL.FTS_LANE_DESKEW_EN 29_653 GTX_CHANNEL_0.GTXE2_CHANNEL.GEARBOX_MODE[0] 28_224 GTX_CHANNEL_0.GTXE2_CHANNEL.GEARBOX_MODE[1] 29_224 GTX_CHANNEL_0.GTXE2_CHANNEL.GEARBOX_MODE[2] 28_225 +GTX_CHANNEL_0.GTXE2_CHANNEL.GTREFCLK0_USED 31_09 +GTX_CHANNEL_0.GTXE2_CHANNEL.GTREFCLK1_USED 30_10 +GTX_CHANNEL_0.GTXE2_CHANNEL.INV_CPLLLOCKDETCLK 31_00 GTX_CHANNEL_0.GTXE2_CHANNEL.INV_DRPCLK 31_01 GTX_CHANNEL_0.GTXE2_CHANNEL.INV_RXUSRCLK 31_04 GTX_CHANNEL_0.GTXE2_CHANNEL.INV_RXUSRCLK2 30_05 GTX_CHANNEL_0.GTXE2_CHANNEL.INV_TXPHDLYTSTCLK 30_06 GTX_CHANNEL_0.GTXE2_CHANNEL.INV_TXUSRCLK 31_07 GTX_CHANNEL_0.GTXE2_CHANNEL.INV_TXUSRCLK2 30_08 -GTX_CHANNEL_0.GTXE2_CHANNEL.IN_USE 28_00 28_01 28_58 28_62 28_63 28_76 29_01 29_57 30_129 31_00 +GTX_CHANNEL_0.GTXE2_CHANNEL.IN_USE 28_00 28_01 28_58 28_62 28_63 28_76 29_01 29_57 30_129 GTX_CHANNEL_0.GTXE2_CHANNEL.OUTREFCLK_SEL_INV[0] 28_149 GTX_CHANNEL_0.GTXE2_CHANNEL.OUTREFCLK_SEL_INV[1] 29_149 GTX_CHANNEL_0.GTXE2_CHANNEL.PCS_PCIE_EN 28_216 diff --git a/kintex7/segbits_gtx_channel_1.db b/kintex7/segbits_gtx_channel_1.db index c8da2f2..a4b61ad 100644 --- a/kintex7/segbits_gtx_channel_1.db +++ b/kintex7/segbits_gtx_channel_1.db @@ -640,13 +640,16 @@ GTX_CHANNEL_1.GTXE2_CHANNEL.FTS_LANE_DESKEW_EN 29_653 GTX_CHANNEL_1.GTXE2_CHANNEL.GEARBOX_MODE[0] 28_224 GTX_CHANNEL_1.GTXE2_CHANNEL.GEARBOX_MODE[1] 29_224 GTX_CHANNEL_1.GTXE2_CHANNEL.GEARBOX_MODE[2] 28_225 +GTX_CHANNEL_1.GTXE2_CHANNEL.GTREFCLK0_USED 31_09 +GTX_CHANNEL_1.GTXE2_CHANNEL.GTREFCLK1_USED 30_10 +GTX_CHANNEL_1.GTXE2_CHANNEL.INV_CPLLLOCKDETCLK 31_00 GTX_CHANNEL_1.GTXE2_CHANNEL.INV_DRPCLK 31_01 GTX_CHANNEL_1.GTXE2_CHANNEL.INV_RXUSRCLK 31_04 GTX_CHANNEL_1.GTXE2_CHANNEL.INV_RXUSRCLK2 30_05 GTX_CHANNEL_1.GTXE2_CHANNEL.INV_TXPHDLYTSTCLK 30_06 GTX_CHANNEL_1.GTXE2_CHANNEL.INV_TXUSRCLK 31_07 GTX_CHANNEL_1.GTXE2_CHANNEL.INV_TXUSRCLK2 30_08 -GTX_CHANNEL_1.GTXE2_CHANNEL.IN_USE 28_00 28_01 28_58 28_62 28_63 28_76 29_01 29_57 30_129 31_00 +GTX_CHANNEL_1.GTXE2_CHANNEL.IN_USE 28_00 28_01 28_58 28_62 28_63 28_76 29_01 29_57 30_129 GTX_CHANNEL_1.GTXE2_CHANNEL.OUTREFCLK_SEL_INV[0] 28_149 GTX_CHANNEL_1.GTXE2_CHANNEL.OUTREFCLK_SEL_INV[1] 29_149 GTX_CHANNEL_1.GTXE2_CHANNEL.PCS_PCIE_EN 28_216 diff --git a/kintex7/segbits_gtx_channel_2.db b/kintex7/segbits_gtx_channel_2.db index 995fd0b..b3654c0 100644 --- a/kintex7/segbits_gtx_channel_2.db +++ b/kintex7/segbits_gtx_channel_2.db @@ -640,13 +640,16 @@ GTX_CHANNEL_2.GTXE2_CHANNEL.FTS_LANE_DESKEW_EN 29_653 GTX_CHANNEL_2.GTXE2_CHANNEL.GEARBOX_MODE[0] 28_224 GTX_CHANNEL_2.GTXE2_CHANNEL.GEARBOX_MODE[1] 29_224 GTX_CHANNEL_2.GTXE2_CHANNEL.GEARBOX_MODE[2] 28_225 +GTX_CHANNEL_2.GTXE2_CHANNEL.GTREFCLK0_USED 31_09 +GTX_CHANNEL_2.GTXE2_CHANNEL.GTREFCLK1_USED 30_10 +GTX_CHANNEL_2.GTXE2_CHANNEL.INV_CPLLLOCKDETCLK 31_00 GTX_CHANNEL_2.GTXE2_CHANNEL.INV_DRPCLK 31_01 GTX_CHANNEL_2.GTXE2_CHANNEL.INV_RXUSRCLK 31_04 GTX_CHANNEL_2.GTXE2_CHANNEL.INV_RXUSRCLK2 30_05 GTX_CHANNEL_2.GTXE2_CHANNEL.INV_TXPHDLYTSTCLK 30_06 GTX_CHANNEL_2.GTXE2_CHANNEL.INV_TXUSRCLK 31_07 GTX_CHANNEL_2.GTXE2_CHANNEL.INV_TXUSRCLK2 30_08 -GTX_CHANNEL_2.GTXE2_CHANNEL.IN_USE 28_00 28_01 28_58 28_62 28_63 28_76 29_01 29_57 30_129 31_00 +GTX_CHANNEL_2.GTXE2_CHANNEL.IN_USE 28_00 28_01 28_58 28_62 28_63 28_76 29_01 29_57 30_129 GTX_CHANNEL_2.GTXE2_CHANNEL.OUTREFCLK_SEL_INV[0] 28_149 GTX_CHANNEL_2.GTXE2_CHANNEL.OUTREFCLK_SEL_INV[1] 29_149 GTX_CHANNEL_2.GTXE2_CHANNEL.PCS_PCIE_EN 28_216 diff --git a/kintex7/segbits_gtx_channel_3.db b/kintex7/segbits_gtx_channel_3.db index 3311e51..1777995 100644 --- a/kintex7/segbits_gtx_channel_3.db +++ b/kintex7/segbits_gtx_channel_3.db @@ -640,13 +640,16 @@ GTX_CHANNEL_3.GTXE2_CHANNEL.FTS_LANE_DESKEW_EN 29_653 GTX_CHANNEL_3.GTXE2_CHANNEL.GEARBOX_MODE[0] 28_224 GTX_CHANNEL_3.GTXE2_CHANNEL.GEARBOX_MODE[1] 29_224 GTX_CHANNEL_3.GTXE2_CHANNEL.GEARBOX_MODE[2] 28_225 +GTX_CHANNEL_3.GTXE2_CHANNEL.GTREFCLK0_USED 31_09 +GTX_CHANNEL_3.GTXE2_CHANNEL.GTREFCLK1_USED 30_10 +GTX_CHANNEL_3.GTXE2_CHANNEL.INV_CPLLLOCKDETCLK 31_00 GTX_CHANNEL_3.GTXE2_CHANNEL.INV_DRPCLK 31_01 GTX_CHANNEL_3.GTXE2_CHANNEL.INV_RXUSRCLK 31_04 GTX_CHANNEL_3.GTXE2_CHANNEL.INV_RXUSRCLK2 30_05 GTX_CHANNEL_3.GTXE2_CHANNEL.INV_TXPHDLYTSTCLK 30_06 GTX_CHANNEL_3.GTXE2_CHANNEL.INV_TXUSRCLK 31_07 GTX_CHANNEL_3.GTXE2_CHANNEL.INV_TXUSRCLK2 30_08 -GTX_CHANNEL_3.GTXE2_CHANNEL.IN_USE 28_00 28_01 28_58 28_62 28_63 28_76 29_01 29_57 30_129 31_00 +GTX_CHANNEL_3.GTXE2_CHANNEL.IN_USE 28_00 28_01 28_58 28_62 28_63 28_76 29_01 29_57 30_129 GTX_CHANNEL_3.GTXE2_CHANNEL.OUTREFCLK_SEL_INV[0] 28_149 GTX_CHANNEL_3.GTXE2_CHANNEL.OUTREFCLK_SEL_INV[1] 29_149 GTX_CHANNEL_3.GTXE2_CHANNEL.PCS_PCIE_EN 28_216 diff --git a/kintex7/segbits_pcie_bot.db b/kintex7/segbits_pcie_bot.db new file mode 100644 index 0000000..6e03cbf --- /dev/null +++ b/kintex7/segbits_pcie_bot.db @@ -0,0 +1,1711 @@ +PCIE_BOT.PCIE.AER_BASE_PTR[0] 28_24 +PCIE_BOT.PCIE.AER_BASE_PTR[1] 29_24 +PCIE_BOT.PCIE.AER_BASE_PTR[2] 28_25 +PCIE_BOT.PCIE.AER_BASE_PTR[3] 29_25 +PCIE_BOT.PCIE.AER_BASE_PTR[4] 28_26 +PCIE_BOT.PCIE.AER_BASE_PTR[5] 29_26 +PCIE_BOT.PCIE.AER_BASE_PTR[6] 28_27 +PCIE_BOT.PCIE.AER_BASE_PTR[7] 29_27 +PCIE_BOT.PCIE.AER_BASE_PTR[8] 28_28 +PCIE_BOT.PCIE.AER_BASE_PTR[9] 29_28 +PCIE_BOT.PCIE.AER_BASE_PTR[10] 28_29 +PCIE_BOT.PCIE.AER_BASE_PTR[11] 29_29 +PCIE_BOT.PCIE.AER_CAP_ECRC_CHECK_CAPABLE 28_00 +PCIE_BOT.PCIE.AER_CAP_ECRC_GEN_CAPABLE 29_00 +PCIE_BOT.PCIE.AER_CAP_ID[0] 28_08 +PCIE_BOT.PCIE.AER_CAP_ID[1] 29_08 +PCIE_BOT.PCIE.AER_CAP_ID[2] 28_09 +PCIE_BOT.PCIE.AER_CAP_ID[3] 29_09 +PCIE_BOT.PCIE.AER_CAP_ID[4] 28_10 +PCIE_BOT.PCIE.AER_CAP_ID[5] 29_10 +PCIE_BOT.PCIE.AER_CAP_ID[6] 28_11 +PCIE_BOT.PCIE.AER_CAP_ID[7] 29_11 +PCIE_BOT.PCIE.AER_CAP_ID[8] 28_12 +PCIE_BOT.PCIE.AER_CAP_ID[9] 29_12 +PCIE_BOT.PCIE.AER_CAP_ID[10] 28_13 +PCIE_BOT.PCIE.AER_CAP_ID[11] 29_13 +PCIE_BOT.PCIE.AER_CAP_ID[12] 28_14 +PCIE_BOT.PCIE.AER_CAP_ID[13] 29_14 +PCIE_BOT.PCIE.AER_CAP_ID[14] 28_15 +PCIE_BOT.PCIE.AER_CAP_ID[15] 29_15 +PCIE_BOT.PCIE.AER_CAP_MULTIHEADER 28_68 +PCIE_BOT.PCIE.AER_CAP_NEXTPTR[0] 28_32 +PCIE_BOT.PCIE.AER_CAP_NEXTPTR[1] 29_32 +PCIE_BOT.PCIE.AER_CAP_NEXTPTR[2] 28_33 +PCIE_BOT.PCIE.AER_CAP_NEXTPTR[3] 29_33 +PCIE_BOT.PCIE.AER_CAP_NEXTPTR[4] 28_34 +PCIE_BOT.PCIE.AER_CAP_NEXTPTR[5] 29_34 +PCIE_BOT.PCIE.AER_CAP_NEXTPTR[6] 28_35 +PCIE_BOT.PCIE.AER_CAP_NEXTPTR[7] 29_35 +PCIE_BOT.PCIE.AER_CAP_NEXTPTR[8] 28_36 +PCIE_BOT.PCIE.AER_CAP_NEXTPTR[9] 29_36 +PCIE_BOT.PCIE.AER_CAP_NEXTPTR[10] 28_37 +PCIE_BOT.PCIE.AER_CAP_NEXTPTR[11] 29_37 +PCIE_BOT.PCIE.AER_CAP_ON 28_38 +PCIE_BOT.PCIE.AER_CAP_OPTIONAL_ERR_SUPPORT[0] 28_40 +PCIE_BOT.PCIE.AER_CAP_OPTIONAL_ERR_SUPPORT[1] 29_40 +PCIE_BOT.PCIE.AER_CAP_OPTIONAL_ERR_SUPPORT[2] 28_41 +PCIE_BOT.PCIE.AER_CAP_OPTIONAL_ERR_SUPPORT[3] 29_41 +PCIE_BOT.PCIE.AER_CAP_OPTIONAL_ERR_SUPPORT[4] 28_42 +PCIE_BOT.PCIE.AER_CAP_OPTIONAL_ERR_SUPPORT[5] 29_42 +PCIE_BOT.PCIE.AER_CAP_OPTIONAL_ERR_SUPPORT[6] 28_43 +PCIE_BOT.PCIE.AER_CAP_OPTIONAL_ERR_SUPPORT[7] 29_43 +PCIE_BOT.PCIE.AER_CAP_OPTIONAL_ERR_SUPPORT[8] 28_44 +PCIE_BOT.PCIE.AER_CAP_OPTIONAL_ERR_SUPPORT[9] 29_44 +PCIE_BOT.PCIE.AER_CAP_OPTIONAL_ERR_SUPPORT[10] 28_45 +PCIE_BOT.PCIE.AER_CAP_OPTIONAL_ERR_SUPPORT[11] 29_45 +PCIE_BOT.PCIE.AER_CAP_OPTIONAL_ERR_SUPPORT[12] 28_46 +PCIE_BOT.PCIE.AER_CAP_OPTIONAL_ERR_SUPPORT[13] 29_46 +PCIE_BOT.PCIE.AER_CAP_OPTIONAL_ERR_SUPPORT[14] 28_47 +PCIE_BOT.PCIE.AER_CAP_OPTIONAL_ERR_SUPPORT[15] 29_47 +PCIE_BOT.PCIE.AER_CAP_OPTIONAL_ERR_SUPPORT[16] 28_64 +PCIE_BOT.PCIE.AER_CAP_OPTIONAL_ERR_SUPPORT[17] 29_64 +PCIE_BOT.PCIE.AER_CAP_OPTIONAL_ERR_SUPPORT[18] 28_65 +PCIE_BOT.PCIE.AER_CAP_OPTIONAL_ERR_SUPPORT[19] 29_65 +PCIE_BOT.PCIE.AER_CAP_OPTIONAL_ERR_SUPPORT[20] 28_66 +PCIE_BOT.PCIE.AER_CAP_OPTIONAL_ERR_SUPPORT[21] 29_66 +PCIE_BOT.PCIE.AER_CAP_OPTIONAL_ERR_SUPPORT[22] 28_67 +PCIE_BOT.PCIE.AER_CAP_OPTIONAL_ERR_SUPPORT[23] 29_67 +PCIE_BOT.PCIE.AER_CAP_PERMIT_ROOTERR_UPDATE 28_16 +PCIE_BOT.PCIE.AER_CAP_VERSION[0] 29_16 +PCIE_BOT.PCIE.AER_CAP_VERSION[1] 28_17 +PCIE_BOT.PCIE.AER_CAP_VERSION[2] 29_17 +PCIE_BOT.PCIE.AER_CAP_VERSION[3] 28_18 +PCIE_BOT.PCIE.ALLOW_X8_GEN2 28_1056 +PCIE_BOT.PCIE.CAPABILITIES_PTR[0] 28_216 +PCIE_BOT.PCIE.CAPABILITIES_PTR[1] 29_216 +PCIE_BOT.PCIE.CAPABILITIES_PTR[2] 28_217 +PCIE_BOT.PCIE.CAPABILITIES_PTR[3] 29_217 +PCIE_BOT.PCIE.CAPABILITIES_PTR[4] 28_218 +PCIE_BOT.PCIE.CAPABILITIES_PTR[5] 29_218 +PCIE_BOT.PCIE.CAPABILITIES_PTR[6] 28_219 +PCIE_BOT.PCIE.CAPABILITIES_PTR[7] 29_219 +PCIE_BOT.PCIE.CARDBUS_CIS_POINTER[0] 28_224 +PCIE_BOT.PCIE.CARDBUS_CIS_POINTER[1] 29_224 +PCIE_BOT.PCIE.CARDBUS_CIS_POINTER[2] 28_225 +PCIE_BOT.PCIE.CARDBUS_CIS_POINTER[3] 29_225 +PCIE_BOT.PCIE.CARDBUS_CIS_POINTER[4] 28_226 +PCIE_BOT.PCIE.CARDBUS_CIS_POINTER[5] 29_226 +PCIE_BOT.PCIE.CARDBUS_CIS_POINTER[6] 28_227 +PCIE_BOT.PCIE.CARDBUS_CIS_POINTER[7] 29_227 +PCIE_BOT.PCIE.CARDBUS_CIS_POINTER[8] 28_228 +PCIE_BOT.PCIE.CARDBUS_CIS_POINTER[9] 29_228 +PCIE_BOT.PCIE.CARDBUS_CIS_POINTER[10] 28_229 +PCIE_BOT.PCIE.CARDBUS_CIS_POINTER[11] 29_229 +PCIE_BOT.PCIE.CARDBUS_CIS_POINTER[12] 28_230 +PCIE_BOT.PCIE.CARDBUS_CIS_POINTER[13] 29_230 +PCIE_BOT.PCIE.CARDBUS_CIS_POINTER[14] 28_231 +PCIE_BOT.PCIE.CARDBUS_CIS_POINTER[15] 29_231 +PCIE_BOT.PCIE.CARDBUS_CIS_POINTER[16] 28_232 +PCIE_BOT.PCIE.CARDBUS_CIS_POINTER[17] 29_232 +PCIE_BOT.PCIE.CARDBUS_CIS_POINTER[18] 28_233 +PCIE_BOT.PCIE.CARDBUS_CIS_POINTER[19] 29_233 +PCIE_BOT.PCIE.CARDBUS_CIS_POINTER[20] 28_234 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+PCIE_BOT.PCIE.LINK_CAP_L1_EXIT_LATENCY_GEN2[1] 29_395 +PCIE_BOT.PCIE.LINK_CAP_L1_EXIT_LATENCY_GEN2[2] 28_396 +PCIE_BOT.PCIE.LINK_CONTROL_RCB[0] 29_400 +PCIE_BOT.PCIE.LINK_STATUS_SLOT_CLOCK_CONFIG 28_404 +PCIE_BOT.PCIE.LINK_CTRL2_DEEMPHASIS 28_401 +PCIE_BOT.PCIE.LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE 29_401 +PCIE_BOT.PCIE.LINK_CTRL2_TARGET_LINK_SPEED[0] 28_402 +PCIE_BOT.PCIE.LINK_CTRL2_TARGET_LINK_SPEED[1] 29_402 +PCIE_BOT.PCIE.LINK_CTRL2_TARGET_LINK_SPEED[2] 28_403 +PCIE_BOT.PCIE.LINK_CTRL2_TARGET_LINK_SPEED[3] 29_403 +PCIE_BOT.PCIE.LL_ACK_TIMEOUT[0] 28_968 +PCIE_BOT.PCIE.LL_ACK_TIMEOUT[1] 29_968 +PCIE_BOT.PCIE.LL_ACK_TIMEOUT[2] 28_969 +PCIE_BOT.PCIE.LL_ACK_TIMEOUT[3] 29_969 +PCIE_BOT.PCIE.LL_ACK_TIMEOUT[4] 28_970 +PCIE_BOT.PCIE.LL_ACK_TIMEOUT[5] 29_970 +PCIE_BOT.PCIE.LL_ACK_TIMEOUT[6] 28_971 +PCIE_BOT.PCIE.LL_ACK_TIMEOUT[7] 29_971 +PCIE_BOT.PCIE.LL_ACK_TIMEOUT[8] 28_972 +PCIE_BOT.PCIE.LL_ACK_TIMEOUT[9] 29_972 +PCIE_BOT.PCIE.LL_ACK_TIMEOUT[10] 28_973 +PCIE_BOT.PCIE.LL_ACK_TIMEOUT[11] 29_973 +PCIE_BOT.PCIE.LL_ACK_TIMEOUT[12] 28_974 +PCIE_BOT.PCIE.LL_ACK_TIMEOUT[13] 29_974 +PCIE_BOT.PCIE.LL_ACK_TIMEOUT[14] 28_975 +PCIE_BOT.PCIE.LL_ACK_TIMEOUT_EN 29_975 +PCIE_BOT.PCIE.LL_ACK_TIMEOUT_FUNC[0] 28_976 +PCIE_BOT.PCIE.LL_ACK_TIMEOUT_FUNC[1] 29_976 +PCIE_BOT.PCIE.LL_REPLAY_TIMEOUT[0] 28_984 +PCIE_BOT.PCIE.LL_REPLAY_TIMEOUT[1] 29_984 +PCIE_BOT.PCIE.LL_REPLAY_TIMEOUT[2] 28_985 +PCIE_BOT.PCIE.LL_REPLAY_TIMEOUT[3] 29_985 +PCIE_BOT.PCIE.LL_REPLAY_TIMEOUT[4] 28_986 +PCIE_BOT.PCIE.LL_REPLAY_TIMEOUT[5] 29_986 +PCIE_BOT.PCIE.LL_REPLAY_TIMEOUT[6] 28_987 +PCIE_BOT.PCIE.LL_REPLAY_TIMEOUT[7] 29_987 +PCIE_BOT.PCIE.LL_REPLAY_TIMEOUT[8] 28_988 +PCIE_BOT.PCIE.LL_REPLAY_TIMEOUT[9] 29_988 +PCIE_BOT.PCIE.LL_REPLAY_TIMEOUT[10] 28_989 +PCIE_BOT.PCIE.LL_REPLAY_TIMEOUT[11] 29_989 +PCIE_BOT.PCIE.LL_REPLAY_TIMEOUT[12] 28_990 +PCIE_BOT.PCIE.LL_REPLAY_TIMEOUT[13] 29_990 +PCIE_BOT.PCIE.LL_REPLAY_TIMEOUT[14] 28_991 +PCIE_BOT.PCIE.LL_REPLAY_TIMEOUT_EN 29_991 +PCIE_BOT.PCIE.LL_REPLAY_TIMEOUT_FUNC[0] 28_992 +PCIE_BOT.PCIE.LL_REPLAY_TIMEOUT_FUNC[1] 29_992 +PCIE_BOT.PCIE.LTSSM_MAX_LINK_WIDTH[0] 28_1035 +PCIE_BOT.PCIE.LTSSM_MAX_LINK_WIDTH[1] 29_1035 +PCIE_BOT.PCIE.LTSSM_MAX_LINK_WIDTH[2] 28_1036 +PCIE_BOT.PCIE.LTSSM_MAX_LINK_WIDTH[3] 29_1036 +PCIE_BOT.PCIE.LTSSM_MAX_LINK_WIDTH[4] 28_1037 +PCIE_BOT.PCIE.LTSSM_MAX_LINK_WIDTH[5] 29_1037 +PCIE_BOT.PCIE.MPS_FORCE 29_404 +PCIE_BOT.PCIE.MSI_BASE_PTR[0] 28_408 +PCIE_BOT.PCIE.MSI_BASE_PTR[1] 29_408 +PCIE_BOT.PCIE.MSI_BASE_PTR[2] 28_409 +PCIE_BOT.PCIE.MSI_BASE_PTR[3] 29_409 +PCIE_BOT.PCIE.MSI_BASE_PTR[4] 28_410 +PCIE_BOT.PCIE.MSI_BASE_PTR[5] 29_410 +PCIE_BOT.PCIE.MSI_BASE_PTR[6] 28_411 +PCIE_BOT.PCIE.MSI_BASE_PTR[7] 29_411 +PCIE_BOT.PCIE.MSI_CAP_64_BIT_ADDR_CAPABLE 28_412 +PCIE_BOT.PCIE.MSI_CAP_ID[0] 28_416 +PCIE_BOT.PCIE.MSI_CAP_ID[1] 29_416 +PCIE_BOT.PCIE.MSI_CAP_ID[2] 28_417 +PCIE_BOT.PCIE.MSI_CAP_ID[3] 29_417 +PCIE_BOT.PCIE.MSI_CAP_ID[4] 28_418 +PCIE_BOT.PCIE.MSI_CAP_ID[5] 29_418 +PCIE_BOT.PCIE.MSI_CAP_ID[6] 28_419 +PCIE_BOT.PCIE.MSI_CAP_ID[7] 29_419 +PCIE_BOT.PCIE.MSI_CAP_MULTIMSG_EXTENSION[0] 28_420 +PCIE_BOT.PCIE.MSI_CAP_MULTIMSGCAP[0] 29_420 +PCIE_BOT.PCIE.MSI_CAP_MULTIMSGCAP[1] 28_421 +PCIE_BOT.PCIE.MSI_CAP_MULTIMSGCAP[2] 29_421 +PCIE_BOT.PCIE.MSI_CAP_NEXTPTR[0] 28_424 +PCIE_BOT.PCIE.MSI_CAP_NEXTPTR[1] 29_424 +PCIE_BOT.PCIE.MSI_CAP_NEXTPTR[2] 28_425 +PCIE_BOT.PCIE.MSI_CAP_NEXTPTR[3] 29_425 +PCIE_BOT.PCIE.MSI_CAP_NEXTPTR[4] 28_426 +PCIE_BOT.PCIE.MSI_CAP_NEXTPTR[5] 29_426 +PCIE_BOT.PCIE.MSI_CAP_NEXTPTR[6] 28_427 +PCIE_BOT.PCIE.MSI_CAP_NEXTPTR[7] 29_427 +PCIE_BOT.PCIE.MSI_CAP_ON 28_428 +PCIE_BOT.PCIE.MSI_CAP_PER_VECTOR_MASKING_CAPABLE 29_428 +PCIE_BOT.PCIE.MSIX_BASE_PTR[0] 28_448 +PCIE_BOT.PCIE.MSIX_BASE_PTR[1] 29_448 +PCIE_BOT.PCIE.MSIX_BASE_PTR[2] 28_449 +PCIE_BOT.PCIE.MSIX_BASE_PTR[3] 29_449 +PCIE_BOT.PCIE.MSIX_BASE_PTR[4] 28_450 +PCIE_BOT.PCIE.MSIX_BASE_PTR[5] 29_450 +PCIE_BOT.PCIE.MSIX_BASE_PTR[6] 28_451 +PCIE_BOT.PCIE.MSIX_BASE_PTR[7] 29_451 +PCIE_BOT.PCIE.MSIX_CAP_ID[0] 28_452 +PCIE_BOT.PCIE.MSIX_CAP_ID[1] 29_452 +PCIE_BOT.PCIE.MSIX_CAP_ID[2] 28_453 +PCIE_BOT.PCIE.MSIX_CAP_ID[3] 29_453 +PCIE_BOT.PCIE.MSIX_CAP_ID[4] 28_454 +PCIE_BOT.PCIE.MSIX_CAP_ID[5] 29_454 +PCIE_BOT.PCIE.MSIX_CAP_ID[6] 28_455 +PCIE_BOT.PCIE.MSIX_CAP_ID[7] 29_455 +PCIE_BOT.PCIE.MSIX_CAP_NEXTPTR[0] 28_456 +PCIE_BOT.PCIE.MSIX_CAP_NEXTPTR[1] 29_456 +PCIE_BOT.PCIE.MSIX_CAP_NEXTPTR[2] 28_457 +PCIE_BOT.PCIE.MSIX_CAP_NEXTPTR[3] 29_457 +PCIE_BOT.PCIE.MSIX_CAP_NEXTPTR[4] 28_458 +PCIE_BOT.PCIE.MSIX_CAP_NEXTPTR[5] 29_458 +PCIE_BOT.PCIE.MSIX_CAP_NEXTPTR[6] 28_459 +PCIE_BOT.PCIE.MSIX_CAP_NEXTPTR[7] 29_459 +PCIE_BOT.PCIE.MSIX_CAP_ON 28_460 +PCIE_BOT.PCIE.MSIX_CAP_PBA_BIR[0] 29_460 +PCIE_BOT.PCIE.MSIX_CAP_PBA_BIR[1] 28_461 +PCIE_BOT.PCIE.MSIX_CAP_PBA_BIR[2] 29_461 +PCIE_BOT.PCIE.MSIX_CAP_PBA_OFFSET[0] 28_464 +PCIE_BOT.PCIE.MSIX_CAP_PBA_OFFSET[1] 29_464 +PCIE_BOT.PCIE.MSIX_CAP_PBA_OFFSET[2] 28_465 +PCIE_BOT.PCIE.MSIX_CAP_PBA_OFFSET[3] 29_465 +PCIE_BOT.PCIE.MSIX_CAP_PBA_OFFSET[4] 28_466 +PCIE_BOT.PCIE.MSIX_CAP_PBA_OFFSET[5] 29_466 +PCIE_BOT.PCIE.MSIX_CAP_PBA_OFFSET[6] 28_467 +PCIE_BOT.PCIE.MSIX_CAP_PBA_OFFSET[7] 29_467 +PCIE_BOT.PCIE.MSIX_CAP_PBA_OFFSET[8] 28_468 +PCIE_BOT.PCIE.MSIX_CAP_PBA_OFFSET[9] 29_468 +PCIE_BOT.PCIE.MSIX_CAP_PBA_OFFSET[10] 28_469 +PCIE_BOT.PCIE.MSIX_CAP_PBA_OFFSET[11] 29_469 +PCIE_BOT.PCIE.MSIX_CAP_PBA_OFFSET[12] 28_470 +PCIE_BOT.PCIE.MSIX_CAP_PBA_OFFSET[13] 29_470 +PCIE_BOT.PCIE.MSIX_CAP_PBA_OFFSET[14] 28_471 +PCIE_BOT.PCIE.MSIX_CAP_PBA_OFFSET[15] 29_471 +PCIE_BOT.PCIE.MSIX_CAP_PBA_OFFSET[16] 28_472 +PCIE_BOT.PCIE.MSIX_CAP_PBA_OFFSET[17] 29_472 +PCIE_BOT.PCIE.MSIX_CAP_PBA_OFFSET[18] 28_473 +PCIE_BOT.PCIE.MSIX_CAP_PBA_OFFSET[19] 29_473 +PCIE_BOT.PCIE.MSIX_CAP_PBA_OFFSET[20] 28_474 +PCIE_BOT.PCIE.MSIX_CAP_PBA_OFFSET[21] 29_474 +PCIE_BOT.PCIE.MSIX_CAP_PBA_OFFSET[22] 28_475 +PCIE_BOT.PCIE.MSIX_CAP_PBA_OFFSET[23] 29_475 +PCIE_BOT.PCIE.MSIX_CAP_PBA_OFFSET[24] 28_476 +PCIE_BOT.PCIE.MSIX_CAP_PBA_OFFSET[25] 29_476 +PCIE_BOT.PCIE.MSIX_CAP_PBA_OFFSET[26] 28_477 +PCIE_BOT.PCIE.MSIX_CAP_PBA_OFFSET[27] 29_477 +PCIE_BOT.PCIE.MSIX_CAP_PBA_OFFSET[28] 28_478 +PCIE_BOT.PCIE.MSIX_CAP_TABLE_BIR[0] 29_478 +PCIE_BOT.PCIE.MSIX_CAP_TABLE_BIR[1] 28_479 +PCIE_BOT.PCIE.MSIX_CAP_TABLE_BIR[2] 29_479 +PCIE_BOT.PCIE.MSIX_CAP_TABLE_OFFSET[0] 28_480 +PCIE_BOT.PCIE.MSIX_CAP_TABLE_OFFSET[1] 29_480 +PCIE_BOT.PCIE.MSIX_CAP_TABLE_OFFSET[2] 28_481 +PCIE_BOT.PCIE.MSIX_CAP_TABLE_OFFSET[3] 29_481 +PCIE_BOT.PCIE.MSIX_CAP_TABLE_OFFSET[4] 28_482 +PCIE_BOT.PCIE.MSIX_CAP_TABLE_OFFSET[5] 29_482 +PCIE_BOT.PCIE.MSIX_CAP_TABLE_OFFSET[6] 28_483 +PCIE_BOT.PCIE.MSIX_CAP_TABLE_OFFSET[7] 29_483 +PCIE_BOT.PCIE.MSIX_CAP_TABLE_OFFSET[8] 28_484 +PCIE_BOT.PCIE.MSIX_CAP_TABLE_OFFSET[9] 29_484 +PCIE_BOT.PCIE.MSIX_CAP_TABLE_OFFSET[10] 28_485 +PCIE_BOT.PCIE.MSIX_CAP_TABLE_OFFSET[11] 29_485 +PCIE_BOT.PCIE.MSIX_CAP_TABLE_OFFSET[12] 28_486 +PCIE_BOT.PCIE.MSIX_CAP_TABLE_OFFSET[13] 29_486 +PCIE_BOT.PCIE.MSIX_CAP_TABLE_OFFSET[14] 28_487 +PCIE_BOT.PCIE.MSIX_CAP_TABLE_OFFSET[15] 29_487 +PCIE_BOT.PCIE.MSIX_CAP_TABLE_OFFSET[16] 28_488 +PCIE_BOT.PCIE.MSIX_CAP_TABLE_OFFSET[17] 29_488 +PCIE_BOT.PCIE.MSIX_CAP_TABLE_OFFSET[18] 28_489 +PCIE_BOT.PCIE.MSIX_CAP_TABLE_OFFSET[19] 29_489 +PCIE_BOT.PCIE.MSIX_CAP_TABLE_OFFSET[20] 28_490 +PCIE_BOT.PCIE.MSIX_CAP_TABLE_OFFSET[21] 29_490 +PCIE_BOT.PCIE.MSIX_CAP_TABLE_OFFSET[22] 28_491 +PCIE_BOT.PCIE.MSIX_CAP_TABLE_OFFSET[23] 29_491 +PCIE_BOT.PCIE.MSIX_CAP_TABLE_OFFSET[24] 28_492 +PCIE_BOT.PCIE.MSIX_CAP_TABLE_OFFSET[25] 29_492 +PCIE_BOT.PCIE.MSIX_CAP_TABLE_OFFSET[26] 28_493 +PCIE_BOT.PCIE.MSIX_CAP_TABLE_OFFSET[27] 29_493 +PCIE_BOT.PCIE.MSIX_CAP_TABLE_OFFSET[28] 28_494 +PCIE_BOT.PCIE.MSIX_CAP_TABLE_SIZE[0] 28_512 +PCIE_BOT.PCIE.MSIX_CAP_TABLE_SIZE[1] 29_512 +PCIE_BOT.PCIE.MSIX_CAP_TABLE_SIZE[2] 28_513 +PCIE_BOT.PCIE.MSIX_CAP_TABLE_SIZE[3] 29_513 +PCIE_BOT.PCIE.MSIX_CAP_TABLE_SIZE[4] 28_514 +PCIE_BOT.PCIE.MSIX_CAP_TABLE_SIZE[5] 29_514 +PCIE_BOT.PCIE.MSIX_CAP_TABLE_SIZE[6] 28_515 +PCIE_BOT.PCIE.MSIX_CAP_TABLE_SIZE[7] 29_515 +PCIE_BOT.PCIE.MSIX_CAP_TABLE_SIZE[8] 28_516 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+PCIE_BOT.PCIE.N_FTS_GEN1[5] 29_1050 +PCIE_BOT.PCIE.N_FTS_GEN1[6] 28_1051 +PCIE_BOT.PCIE.N_FTS_GEN1[7] 29_1051 +PCIE_BOT.PCIE.N_FTS_GEN2[0] 28_1052 +PCIE_BOT.PCIE.N_FTS_GEN2[1] 29_1052 +PCIE_BOT.PCIE.N_FTS_GEN2[2] 28_1053 +PCIE_BOT.PCIE.N_FTS_GEN2[3] 29_1053 +PCIE_BOT.PCIE.N_FTS_GEN2[4] 28_1054 +PCIE_BOT.PCIE.N_FTS_GEN2[5] 29_1054 +PCIE_BOT.PCIE.N_FTS_GEN2[6] 28_1055 +PCIE_BOT.PCIE.N_FTS_GEN2[7] 29_1055 +PCIE_BOT.PCIE.PCIE_BASE_PTR[0] 28_520 +PCIE_BOT.PCIE.PCIE_BASE_PTR[1] 29_520 +PCIE_BOT.PCIE.PCIE_BASE_PTR[2] 28_521 +PCIE_BOT.PCIE.PCIE_BASE_PTR[3] 29_521 +PCIE_BOT.PCIE.PCIE_BASE_PTR[4] 28_522 +PCIE_BOT.PCIE.PCIE_BASE_PTR[5] 29_522 +PCIE_BOT.PCIE.PCIE_BASE_PTR[6] 28_523 +PCIE_BOT.PCIE.PCIE_BASE_PTR[7] 29_523 +PCIE_BOT.PCIE.PCIE_CAP_CAPABILITY_ID[0] 28_524 +PCIE_BOT.PCIE.PCIE_CAP_CAPABILITY_ID[1] 29_524 +PCIE_BOT.PCIE.PCIE_CAP_CAPABILITY_ID[2] 28_525 +PCIE_BOT.PCIE.PCIE_CAP_CAPABILITY_ID[3] 29_525 +PCIE_BOT.PCIE.PCIE_CAP_CAPABILITY_ID[4] 28_526 +PCIE_BOT.PCIE.PCIE_CAP_CAPABILITY_ID[5] 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+PCIE_BOT.PCIE.VC0_TX_LASTPACKET[1] 28_1164 +PCIE_BOT.PCIE.VC0_TX_LASTPACKET[2] 29_1164 +PCIE_BOT.PCIE.VC0_TX_LASTPACKET[3] 28_1165 +PCIE_BOT.PCIE.VC0_TX_LASTPACKET[4] 29_1165 diff --git a/kintex7/segbits_pcie_bot.origin_info.db b/kintex7/segbits_pcie_bot.origin_info.db new file mode 100644 index 0000000..cc928c4 --- /dev/null +++ b/kintex7/segbits_pcie_bot.origin_info.db @@ -0,0 +1,1711 @@ +PCIE_BOT.PCIE.AER_BASE_PTR[0] origin:061-pcie-conf 28_24 +PCIE_BOT.PCIE.AER_BASE_PTR[1] origin:061-pcie-conf 29_24 +PCIE_BOT.PCIE.AER_BASE_PTR[2] origin:061-pcie-conf 28_25 +PCIE_BOT.PCIE.AER_BASE_PTR[3] origin:061-pcie-conf 29_25 +PCIE_BOT.PCIE.AER_BASE_PTR[4] origin:061-pcie-conf 28_26 +PCIE_BOT.PCIE.AER_BASE_PTR[5] origin:061-pcie-conf 29_26 +PCIE_BOT.PCIE.AER_BASE_PTR[6] origin:061-pcie-conf 28_27 +PCIE_BOT.PCIE.AER_BASE_PTR[7] origin:061-pcie-conf 29_27 +PCIE_BOT.PCIE.AER_BASE_PTR[8] origin:061-pcie-conf 28_28 +PCIE_BOT.PCIE.AER_BASE_PTR[9] origin:061-pcie-conf 29_28 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origin:061-pcie-conf 28_38 +PCIE_BOT.PCIE.AER_CAP_OPTIONAL_ERR_SUPPORT[0] origin:061-pcie-conf 28_40 +PCIE_BOT.PCIE.AER_CAP_OPTIONAL_ERR_SUPPORT[1] origin:061-pcie-conf 29_40 +PCIE_BOT.PCIE.AER_CAP_OPTIONAL_ERR_SUPPORT[2] origin:061-pcie-conf 28_41 +PCIE_BOT.PCIE.AER_CAP_OPTIONAL_ERR_SUPPORT[3] origin:061-pcie-conf 29_41 +PCIE_BOT.PCIE.AER_CAP_OPTIONAL_ERR_SUPPORT[4] origin:061-pcie-conf 28_42 +PCIE_BOT.PCIE.AER_CAP_OPTIONAL_ERR_SUPPORT[5] origin:061-pcie-conf 29_42 +PCIE_BOT.PCIE.AER_CAP_OPTIONAL_ERR_SUPPORT[6] origin:061-pcie-conf 28_43 +PCIE_BOT.PCIE.AER_CAP_OPTIONAL_ERR_SUPPORT[7] origin:061-pcie-conf 29_43 +PCIE_BOT.PCIE.AER_CAP_OPTIONAL_ERR_SUPPORT[8] origin:061-pcie-conf 28_44 +PCIE_BOT.PCIE.AER_CAP_OPTIONAL_ERR_SUPPORT[9] origin:061-pcie-conf 29_44 +PCIE_BOT.PCIE.AER_CAP_OPTIONAL_ERR_SUPPORT[10] origin:061-pcie-conf 28_45 +PCIE_BOT.PCIE.AER_CAP_OPTIONAL_ERR_SUPPORT[11] origin:061-pcie-conf 29_45 +PCIE_BOT.PCIE.AER_CAP_OPTIONAL_ERR_SUPPORT[12] origin:061-pcie-conf 28_46 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origin:061-pcie-conf 28_17 +PCIE_BOT.PCIE.AER_CAP_VERSION[2] origin:061-pcie-conf 29_17 +PCIE_BOT.PCIE.AER_CAP_VERSION[3] origin:061-pcie-conf 28_18 +PCIE_BOT.PCIE.ALLOW_X8_GEN2 origin:061-pcie-conf 28_1056 +PCIE_BOT.PCIE.CAPABILITIES_PTR[0] origin:061-pcie-conf 28_216 +PCIE_BOT.PCIE.CAPABILITIES_PTR[1] origin:061-pcie-conf 29_216 +PCIE_BOT.PCIE.CAPABILITIES_PTR[2] origin:061-pcie-conf 28_217 +PCIE_BOT.PCIE.CAPABILITIES_PTR[3] origin:061-pcie-conf 29_217 +PCIE_BOT.PCIE.CAPABILITIES_PTR[4] origin:061-pcie-conf 28_218 +PCIE_BOT.PCIE.CAPABILITIES_PTR[5] origin:061-pcie-conf 29_218 +PCIE_BOT.PCIE.CAPABILITIES_PTR[6] origin:061-pcie-conf 28_219 +PCIE_BOT.PCIE.CAPABILITIES_PTR[7] origin:061-pcie-conf 29_219 +PCIE_BOT.PCIE.CARDBUS_CIS_POINTER[0] origin:061-pcie-conf 28_224 +PCIE_BOT.PCIE.CARDBUS_CIS_POINTER[1] origin:061-pcie-conf 29_224 +PCIE_BOT.PCIE.CARDBUS_CIS_POINTER[2] origin:061-pcie-conf 28_225 +PCIE_BOT.PCIE.CARDBUS_CIS_POINTER[3] origin:061-pcie-conf 29_225 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origin:061-pcie-conf 29_964 +PCIE_BOT.PCIE.CRM_MODULE_RSTS[3] origin:061-pcie-conf 28_965 +PCIE_BOT.PCIE.CRM_MODULE_RSTS[4] origin:061-pcie-conf 29_965 +PCIE_BOT.PCIE.CRM_MODULE_RSTS[5] origin:061-pcie-conf 28_966 +PCIE_BOT.PCIE.CRM_MODULE_RSTS[6] origin:061-pcie-conf 29_966 +PCIE_BOT.PCIE.DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE origin:061-pcie-conf 28_278 +PCIE_BOT.PCIE.DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE origin:061-pcie-conf 29_278 +PCIE_BOT.PCIE.DEV_CAP_ENDPOINT_L0S_LATENCY[0] origin:061-pcie-conf 28_280 +PCIE_BOT.PCIE.DEV_CAP_ENDPOINT_L0S_LATENCY[1] origin:061-pcie-conf 29_280 +PCIE_BOT.PCIE.DEV_CAP_ENDPOINT_L0S_LATENCY[2] origin:061-pcie-conf 28_281 +PCIE_BOT.PCIE.DEV_CAP_ENDPOINT_L1_LATENCY[0] origin:061-pcie-conf 29_281 +PCIE_BOT.PCIE.DEV_CAP_ENDPOINT_L1_LATENCY[1] origin:061-pcie-conf 28_282 +PCIE_BOT.PCIE.DEV_CAP_ENDPOINT_L1_LATENCY[2] origin:061-pcie-conf 29_282 +PCIE_BOT.PCIE.DEV_CAP_EXT_TAG_SUPPORTED origin:061-pcie-conf 28_283 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28_327 +PCIE_BOT.PCIE.DSN_CAP_ID[15] origin:061-pcie-conf 29_327 +PCIE_BOT.PCIE.DSN_CAP_NEXTPTR[0] origin:061-pcie-conf 28_328 +PCIE_BOT.PCIE.DSN_CAP_NEXTPTR[1] origin:061-pcie-conf 29_328 +PCIE_BOT.PCIE.DSN_CAP_NEXTPTR[2] origin:061-pcie-conf 28_329 +PCIE_BOT.PCIE.DSN_CAP_NEXTPTR[3] origin:061-pcie-conf 29_329 +PCIE_BOT.PCIE.DSN_CAP_NEXTPTR[4] origin:061-pcie-conf 28_330 +PCIE_BOT.PCIE.DSN_CAP_NEXTPTR[5] origin:061-pcie-conf 29_330 +PCIE_BOT.PCIE.DSN_CAP_NEXTPTR[6] origin:061-pcie-conf 28_331 +PCIE_BOT.PCIE.DSN_CAP_NEXTPTR[7] origin:061-pcie-conf 29_331 +PCIE_BOT.PCIE.DSN_CAP_NEXTPTR[8] origin:061-pcie-conf 28_332 +PCIE_BOT.PCIE.DSN_CAP_NEXTPTR[9] origin:061-pcie-conf 29_332 +PCIE_BOT.PCIE.DSN_CAP_NEXTPTR[10] origin:061-pcie-conf 28_333 +PCIE_BOT.PCIE.DSN_CAP_NEXTPTR[11] origin:061-pcie-conf 29_333 +PCIE_BOT.PCIE.DSN_CAP_ON origin:061-pcie-conf 28_334 +PCIE_BOT.PCIE.DSN_CAP_VERSION[0] origin:061-pcie-conf 28_336 +PCIE_BOT.PCIE.DSN_CAP_VERSION[1] origin:061-pcie-conf 29_336 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origin:062-pcie-int-pips 26_18 +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT11.PCIE_INT_INTERFACE_IMUX_DELAY11 origin:062-pcie-int-pips 26_26 +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT12.PCIE_INT_INTERFACE_IMUX_DELAY12 origin:062-pcie-int-pips 26_34 +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT13.PCIE_INT_INTERFACE_IMUX_DELAY13 origin:062-pcie-int-pips 26_42 +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT14.PCIE_INT_INTERFACE_IMUX_DELAY14 origin:062-pcie-int-pips 26_50 +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT15.PCIE_INT_INTERFACE_IMUX_DELAY15 origin:062-pcie-int-pips 26_58 +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT16.PCIE_INT_INTERFACE_IMUX_DELAY16 origin:062-pcie-int-pips 26_03 +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT17.PCIE_INT_INTERFACE_IMUX_DELAY17 origin:062-pcie-int-pips 26_11 +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT18.PCIE_INT_INTERFACE_IMUX_DELAY18 origin:062-pcie-int-pips 26_19 +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT19.PCIE_INT_INTERFACE_IMUX_DELAY19 origin:062-pcie-int-pips 26_27 +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT20.PCIE_INT_INTERFACE_IMUX_DELAY20 origin:062-pcie-int-pips 26_35 +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT21.PCIE_INT_INTERFACE_IMUX_DELAY21 origin:062-pcie-int-pips 26_43 +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT22.PCIE_INT_INTERFACE_IMUX_DELAY22 origin:062-pcie-int-pips 26_51 +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT23.PCIE_INT_INTERFACE_IMUX_DELAY23 origin:062-pcie-int-pips 26_59 +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT24.PCIE_INT_INTERFACE_IMUX_DELAY24 origin:062-pcie-int-pips 27_04 +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT25.PCIE_INT_INTERFACE_IMUX_DELAY25 origin:062-pcie-int-pips 27_12 +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT32.PCIE_INT_INTERFACE_IMUX_DELAY32 origin:062-pcie-int-pips 27_05 +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT33.PCIE_INT_INTERFACE_IMUX_DELAY33 origin:062-pcie-int-pips 27_13 +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT34.PCIE_INT_INTERFACE_IMUX_DELAY34 origin:062-pcie-int-pips 27_21 +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT35.PCIE_INT_INTERFACE_IMUX_DELAY35 origin:062-pcie-int-pips 27_29 +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT36.PCIE_INT_INTERFACE_IMUX_DELAY36 origin:062-pcie-int-pips 27_37 +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT37.PCIE_INT_INTERFACE_IMUX_DELAY37 origin:062-pcie-int-pips 27_45 +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT38.PCIE_INT_INTERFACE_IMUX_DELAY38 origin:062-pcie-int-pips 27_53 +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT39.PCIE_INT_INTERFACE_IMUX_DELAY39 origin:062-pcie-int-pips 27_61 diff --git a/kintex7/xc7k160t/tilegrid.json b/kintex7/xc7k160t/tilegrid.json index 3f8e71f..adf1a29 100644 --- a/kintex7/xc7k160t/tilegrid.json +++ b/kintex7/xc7k160t/tilegrid.json @@ -730340,7 +730340,14 @@ "type": "NULL" }, "PCIE_BOT_X142Y167": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00001B80", + "frames": 36, + "offset": 0, + "words": 101 + } + }, "clock_region": "X1Y3", "grid_x": 142, "grid_y": 93, @@ -730352,7 +730359,14 @@ "type": "PCIE_BOT" }, "PCIE_INT_INTERFACE_L_X58Y150": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00001D00", + "frames": 28, + "offset": 0, + "words": 2 + } + }, "grid_x": 147, "grid_y": 103, "pin_functions": {}, @@ -730361,7 +730375,14 @@ "type": "PCIE_INT_INTERFACE_L" }, "PCIE_INT_INTERFACE_L_X58Y151": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00001D00", + "frames": 28, + "offset": 2, + "words": 2 + } + }, "grid_x": 147, "grid_y": 102, "pin_functions": {}, @@ -730370,7 +730391,14 @@ "type": "PCIE_INT_INTERFACE_L" }, "PCIE_INT_INTERFACE_L_X58Y152": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00001D00", + "frames": 28, + "offset": 4, + "words": 2 + } + }, "grid_x": 147, "grid_y": 101, "pin_functions": {}, @@ -730379,7 +730407,14 @@ "type": "PCIE_INT_INTERFACE_L" }, "PCIE_INT_INTERFACE_L_X58Y153": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00001D00", + "frames": 28, + "offset": 6, + "words": 2 + } + }, "grid_x": 147, "grid_y": 100, "pin_functions": {}, @@ -730388,7 +730423,14 @@ "type": "PCIE_INT_INTERFACE_L" }, "PCIE_INT_INTERFACE_L_X58Y154": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00001D00", + "frames": 28, + "offset": 8, + "words": 2 + } + }, "grid_x": 147, "grid_y": 99, "pin_functions": {}, @@ -730397,7 +730439,14 @@ "type": "PCIE_INT_INTERFACE_L" }, "PCIE_INT_INTERFACE_L_X58Y155": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00001D00", + "frames": 28, + "offset": 10, + "words": 2 + } + }, "grid_x": 147, "grid_y": 98, "pin_functions": {}, @@ -730406,7 +730455,14 @@ "type": "PCIE_INT_INTERFACE_L" }, "PCIE_INT_INTERFACE_L_X58Y156": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00001D00", + "frames": 28, + "offset": 12, + "words": 2 + } + }, "grid_x": 147, "grid_y": 97, "pin_functions": {}, @@ -730415,7 +730471,14 @@ "type": "PCIE_INT_INTERFACE_L" }, "PCIE_INT_INTERFACE_L_X58Y157": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00001D00", + "frames": 28, + "offset": 14, + "words": 2 + } + }, "grid_x": 147, "grid_y": 96, "pin_functions": {}, @@ -730424,7 +730487,14 @@ "type": "PCIE_INT_INTERFACE_L" }, "PCIE_INT_INTERFACE_L_X58Y158": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00001D00", + "frames": 28, + "offset": 16, + "words": 2 + } + }, "grid_x": 147, "grid_y": 95, "pin_functions": {}, @@ -730433,7 +730503,14 @@ "type": "PCIE_INT_INTERFACE_L" }, "PCIE_INT_INTERFACE_L_X58Y159": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00001D00", + "frames": 28, + "offset": 18, + "words": 2 + } + }, "grid_x": 147, "grid_y": 94, "pin_functions": {}, @@ -730442,7 +730519,14 @@ "type": "PCIE_INT_INTERFACE_L" }, "PCIE_INT_INTERFACE_L_X58Y160": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00001D00", + "frames": 28, + "offset": 20, + "words": 2 + } + }, "grid_x": 147, "grid_y": 93, "pin_functions": {}, @@ -730451,7 +730535,14 @@ "type": "PCIE_INT_INTERFACE_L" }, "PCIE_INT_INTERFACE_L_X58Y161": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00001D00", + "frames": 28, + "offset": 22, + "words": 2 + } + }, "grid_x": 147, "grid_y": 92, "pin_functions": {}, @@ -730460,7 +730551,14 @@ "type": "PCIE_INT_INTERFACE_L" }, "PCIE_INT_INTERFACE_L_X58Y162": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00001D00", + "frames": 28, + "offset": 24, + "words": 2 + } + }, "grid_x": 147, "grid_y": 91, "pin_functions": {}, @@ -730469,7 +730567,14 @@ "type": "PCIE_INT_INTERFACE_L" }, "PCIE_INT_INTERFACE_L_X58Y163": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00001D00", + "frames": 28, + "offset": 26, + "words": 2 + } + }, "grid_x": 147, "grid_y": 90, "pin_functions": {}, @@ -730478,7 +730583,14 @@ "type": "PCIE_INT_INTERFACE_L" }, "PCIE_INT_INTERFACE_L_X58Y164": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00001D00", + "frames": 28, + "offset": 28, + "words": 2 + } + }, "grid_x": 147, "grid_y": 89, "pin_functions": {}, @@ -730487,7 +730599,14 @@ "type": "PCIE_INT_INTERFACE_L" }, "PCIE_INT_INTERFACE_L_X58Y165": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00001D00", + "frames": 28, + "offset": 30, + "words": 2 + } + }, "grid_x": 147, "grid_y": 88, "pin_functions": {}, @@ -730496,7 +730615,14 @@ "type": "PCIE_INT_INTERFACE_L" }, "PCIE_INT_INTERFACE_L_X58Y166": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00001D00", + "frames": 28, + "offset": 32, + "words": 2 + } + }, "grid_x": 147, "grid_y": 87, "pin_functions": {}, @@ -730505,7 +730631,14 @@ "type": "PCIE_INT_INTERFACE_L" }, "PCIE_INT_INTERFACE_L_X58Y167": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00001D00", + "frames": 28, + "offset": 34, + "words": 2 + } + }, "grid_x": 147, "grid_y": 86, "pin_functions": {}, @@ -730514,7 +730647,14 @@ "type": "PCIE_INT_INTERFACE_L" }, "PCIE_INT_INTERFACE_L_X58Y168": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00001D00", + "frames": 28, + "offset": 36, + "words": 2 + } + }, "grid_x": 147, "grid_y": 85, "pin_functions": {}, @@ -730523,7 +730663,14 @@ "type": "PCIE_INT_INTERFACE_L" }, "PCIE_INT_INTERFACE_L_X58Y169": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00001D00", + "frames": 28, + "offset": 38, + "words": 2 + } + }, "grid_x": 147, "grid_y": 84, "pin_functions": {}, @@ -730532,7 +730679,14 @@ "type": "PCIE_INT_INTERFACE_L" }, "PCIE_INT_INTERFACE_L_X58Y170": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00001D00", + "frames": 28, + "offset": 40, + "words": 2 + } + }, "grid_x": 147, "grid_y": 83, "pin_functions": {}, @@ -730541,7 +730695,14 @@ "type": "PCIE_INT_INTERFACE_L" }, "PCIE_INT_INTERFACE_L_X58Y171": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00001D00", + "frames": 28, + "offset": 42, + "words": 2 + } + }, "grid_x": 147, "grid_y": 82, "pin_functions": {}, @@ -730550,7 +730711,14 @@ "type": "PCIE_INT_INTERFACE_L" }, "PCIE_INT_INTERFACE_L_X58Y172": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00001D00", + "frames": 28, + "offset": 44, + "words": 2 + } + }, "grid_x": 147, "grid_y": 81, "pin_functions": {}, @@ -730559,7 +730727,14 @@ "type": "PCIE_INT_INTERFACE_L" }, "PCIE_INT_INTERFACE_L_X58Y173": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00001D00", + "frames": 28, + "offset": 46, + "words": 2 + } + }, "grid_x": 147, "grid_y": 80, "pin_functions": {}, @@ -730568,7 +730743,14 @@ "type": "PCIE_INT_INTERFACE_L" }, "PCIE_INT_INTERFACE_L_X58Y174": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00001D00", + "frames": 28, + "offset": 48, + "words": 2 + } + }, "grid_x": 147, "grid_y": 79, "pin_functions": {}, @@ -730577,7 +730759,14 @@ "type": "PCIE_INT_INTERFACE_L" }, "PCIE_INT_INTERFACE_R_X55Y150": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00001B80", + "frames": 28, + "offset": 0, + "words": 2 + } + }, "grid_x": 141, "grid_y": 103, "pin_functions": {}, @@ -730586,7 +730775,14 @@ "type": "PCIE_INT_INTERFACE_R" }, "PCIE_INT_INTERFACE_R_X55Y151": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00001B80", + "frames": 28, + "offset": 2, + "words": 2 + } + }, "grid_x": 141, "grid_y": 102, "pin_functions": {}, @@ -730595,7 +730791,14 @@ "type": "PCIE_INT_INTERFACE_R" }, "PCIE_INT_INTERFACE_R_X55Y152": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00001B80", + "frames": 28, + "offset": 4, + "words": 2 + } + }, "grid_x": 141, "grid_y": 101, "pin_functions": {}, @@ -730604,7 +730807,14 @@ "type": "PCIE_INT_INTERFACE_R" }, "PCIE_INT_INTERFACE_R_X55Y153": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00001B80", + "frames": 28, + "offset": 6, + "words": 2 + } + }, "grid_x": 141, "grid_y": 100, "pin_functions": {}, @@ -730613,7 +730823,14 @@ "type": "PCIE_INT_INTERFACE_R" }, "PCIE_INT_INTERFACE_R_X55Y154": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00001B80", + "frames": 28, + "offset": 8, + "words": 2 + } + }, "grid_x": 141, "grid_y": 99, "pin_functions": {}, @@ -730622,7 +730839,14 @@ "type": "PCIE_INT_INTERFACE_R" }, "PCIE_INT_INTERFACE_R_X55Y155": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00001B80", + "frames": 28, + "offset": 10, + "words": 2 + } + }, "grid_x": 141, "grid_y": 98, "pin_functions": {}, @@ -730631,7 +730855,14 @@ "type": "PCIE_INT_INTERFACE_R" }, "PCIE_INT_INTERFACE_R_X55Y156": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00001B80", + "frames": 28, + "offset": 12, + "words": 2 + } + }, "grid_x": 141, "grid_y": 97, "pin_functions": {}, @@ -730640,7 +730871,14 @@ "type": "PCIE_INT_INTERFACE_R" }, "PCIE_INT_INTERFACE_R_X55Y157": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00001B80", + "frames": 28, + "offset": 14, + "words": 2 + } + }, "grid_x": 141, "grid_y": 96, "pin_functions": {}, @@ -730649,7 +730887,14 @@ "type": "PCIE_INT_INTERFACE_R" }, "PCIE_INT_INTERFACE_R_X55Y158": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00001B80", + "frames": 28, + "offset": 16, + "words": 2 + } + }, "grid_x": 141, "grid_y": 95, "pin_functions": {}, @@ -730658,7 +730903,14 @@ "type": "PCIE_INT_INTERFACE_R" }, "PCIE_INT_INTERFACE_R_X55Y159": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00001B80", + "frames": 28, + "offset": 18, + "words": 2 + } + }, "grid_x": 141, "grid_y": 94, "pin_functions": {}, @@ -730667,7 +730919,14 @@ "type": "PCIE_INT_INTERFACE_R" }, "PCIE_INT_INTERFACE_R_X55Y160": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00001B80", + "frames": 28, + "offset": 20, + "words": 2 + } + }, "grid_x": 141, "grid_y": 93, "pin_functions": {}, @@ -730676,7 +730935,14 @@ "type": "PCIE_INT_INTERFACE_R" }, "PCIE_INT_INTERFACE_R_X55Y161": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00001B80", + "frames": 28, + "offset": 22, + "words": 2 + } + }, "grid_x": 141, "grid_y": 92, "pin_functions": {}, @@ -730685,7 +730951,14 @@ "type": "PCIE_INT_INTERFACE_R" }, "PCIE_INT_INTERFACE_R_X55Y162": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00001B80", + "frames": 28, + "offset": 24, + "words": 2 + } + }, "grid_x": 141, "grid_y": 91, "pin_functions": {}, @@ -730694,7 +730967,14 @@ "type": "PCIE_INT_INTERFACE_R" }, "PCIE_INT_INTERFACE_R_X55Y163": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00001B80", + "frames": 28, + "offset": 26, + "words": 2 + } + }, "grid_x": 141, "grid_y": 90, "pin_functions": {}, @@ -730703,7 +730983,14 @@ "type": "PCIE_INT_INTERFACE_R" }, "PCIE_INT_INTERFACE_R_X55Y164": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00001B80", + "frames": 28, + "offset": 28, + "words": 2 + } + }, "grid_x": 141, "grid_y": 89, "pin_functions": {}, @@ -730712,7 +730999,14 @@ "type": "PCIE_INT_INTERFACE_R" }, "PCIE_INT_INTERFACE_R_X55Y165": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00001B80", + "frames": 28, + "offset": 30, + "words": 2 + } + }, "grid_x": 141, "grid_y": 88, "pin_functions": {}, @@ -730721,7 +731015,14 @@ "type": "PCIE_INT_INTERFACE_R" }, "PCIE_INT_INTERFACE_R_X55Y166": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00001B80", + "frames": 28, + "offset": 32, + "words": 2 + } + }, "grid_x": 141, "grid_y": 87, "pin_functions": {}, @@ -730730,7 +731031,14 @@ "type": "PCIE_INT_INTERFACE_R" }, "PCIE_INT_INTERFACE_R_X55Y167": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00001B80", + "frames": 28, + "offset": 34, + "words": 2 + } + }, "grid_x": 141, "grid_y": 86, "pin_functions": {}, @@ -730739,7 +731047,14 @@ "type": "PCIE_INT_INTERFACE_R" }, "PCIE_INT_INTERFACE_R_X55Y168": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00001B80", + "frames": 28, + "offset": 36, + "words": 2 + } + }, "grid_x": 141, "grid_y": 85, "pin_functions": {}, @@ -730748,7 +731063,14 @@ "type": "PCIE_INT_INTERFACE_R" }, "PCIE_INT_INTERFACE_R_X55Y169": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00001B80", + "frames": 28, + "offset": 38, + "words": 2 + } + }, "grid_x": 141, "grid_y": 84, "pin_functions": {}, @@ -730757,7 +731079,14 @@ "type": "PCIE_INT_INTERFACE_R" }, "PCIE_INT_INTERFACE_R_X55Y170": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00001B80", + "frames": 28, + "offset": 40, + "words": 2 + } + }, "grid_x": 141, "grid_y": 83, "pin_functions": {}, @@ -730766,7 +731095,14 @@ "type": "PCIE_INT_INTERFACE_R" }, "PCIE_INT_INTERFACE_R_X55Y171": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00001B80", + "frames": 28, + "offset": 42, + "words": 2 + } + }, "grid_x": 141, "grid_y": 82, "pin_functions": {}, @@ -730775,7 +731111,14 @@ "type": "PCIE_INT_INTERFACE_R" }, "PCIE_INT_INTERFACE_R_X55Y172": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00001B80", + "frames": 28, + "offset": 44, + "words": 2 + } + }, "grid_x": 141, "grid_y": 81, "pin_functions": {}, @@ -730784,7 +731127,14 @@ "type": "PCIE_INT_INTERFACE_R" }, "PCIE_INT_INTERFACE_R_X55Y173": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00001B80", + "frames": 28, + "offset": 46, + "words": 2 + } + }, "grid_x": 141, "grid_y": 80, "pin_functions": {}, @@ -730793,7 +731143,14 @@ "type": "PCIE_INT_INTERFACE_R" }, "PCIE_INT_INTERFACE_R_X55Y174": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00001B80", + "frames": 28, + "offset": 48, + "words": 2 + } + }, "grid_x": 141, "grid_y": 79, "pin_functions": {}, diff --git a/kintex7/xc7k325t/tilegrid.json b/kintex7/xc7k325t/tilegrid.json index c153faa..f14b902 100644 --- a/kintex7/xc7k325t/tilegrid.json +++ b/kintex7/xc7k325t/tilegrid.json @@ -1330839,7 +1330839,14 @@ "type": "NULL" }, "PCIE_BOT_X189Y167": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00002680", + "frames": 36, + "offset": 0, + "words": 101 + } + }, "clock_region": "X1Y3", "grid_x": 189, "grid_y": 197, @@ -1330851,7 +1330858,14 @@ "type": "PCIE_BOT" }, "PCIE_INT_INTERFACE_L_X80Y150": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00002800", + "frames": 28, + "offset": 0, + "words": 2 + } + }, "grid_x": 194, "grid_y": 207, "pin_functions": {}, @@ -1330860,7 +1330874,14 @@ "type": "PCIE_INT_INTERFACE_L" }, "PCIE_INT_INTERFACE_L_X80Y151": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00002800", + "frames": 28, + "offset": 2, + "words": 2 + } + }, "grid_x": 194, "grid_y": 206, "pin_functions": {}, @@ -1330869,7 +1330890,14 @@ "type": "PCIE_INT_INTERFACE_L" }, "PCIE_INT_INTERFACE_L_X80Y152": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00002800", + "frames": 28, + "offset": 4, + "words": 2 + } + }, "grid_x": 194, "grid_y": 205, "pin_functions": {}, @@ -1330878,7 +1330906,14 @@ "type": "PCIE_INT_INTERFACE_L" }, "PCIE_INT_INTERFACE_L_X80Y153": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00002800", + "frames": 28, + "offset": 6, + "words": 2 + } + }, "grid_x": 194, "grid_y": 204, "pin_functions": {}, @@ -1330887,7 +1330922,14 @@ "type": "PCIE_INT_INTERFACE_L" }, "PCIE_INT_INTERFACE_L_X80Y154": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00002800", + "frames": 28, + "offset": 8, + "words": 2 + } + }, "grid_x": 194, "grid_y": 203, "pin_functions": {}, @@ -1330896,7 +1330938,14 @@ "type": "PCIE_INT_INTERFACE_L" }, "PCIE_INT_INTERFACE_L_X80Y155": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00002800", + "frames": 28, + "offset": 10, + "words": 2 + } + }, "grid_x": 194, "grid_y": 202, "pin_functions": {}, @@ -1330905,7 +1330954,14 @@ "type": "PCIE_INT_INTERFACE_L" }, "PCIE_INT_INTERFACE_L_X80Y156": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00002800", + "frames": 28, + "offset": 12, + "words": 2 + } + }, "grid_x": 194, "grid_y": 201, "pin_functions": {}, @@ -1330914,7 +1330970,14 @@ "type": "PCIE_INT_INTERFACE_L" }, "PCIE_INT_INTERFACE_L_X80Y157": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00002800", + "frames": 28, + "offset": 14, + "words": 2 + } + }, "grid_x": 194, "grid_y": 200, "pin_functions": {}, @@ -1330923,7 +1330986,14 @@ "type": "PCIE_INT_INTERFACE_L" }, "PCIE_INT_INTERFACE_L_X80Y158": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00002800", + "frames": 28, + "offset": 16, + "words": 2 + } + }, "grid_x": 194, "grid_y": 199, "pin_functions": {}, @@ -1330932,7 +1331002,14 @@ "type": "PCIE_INT_INTERFACE_L" }, "PCIE_INT_INTERFACE_L_X80Y159": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00002800", + "frames": 28, + "offset": 18, + "words": 2 + } + }, "grid_x": 194, "grid_y": 198, "pin_functions": {}, @@ -1330941,7 +1331018,14 @@ "type": "PCIE_INT_INTERFACE_L" }, "PCIE_INT_INTERFACE_L_X80Y160": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00002800", + "frames": 28, + "offset": 20, + "words": 2 + } + }, "grid_x": 194, "grid_y": 197, "pin_functions": {}, @@ -1330950,7 +1331034,14 @@ "type": "PCIE_INT_INTERFACE_L" }, "PCIE_INT_INTERFACE_L_X80Y161": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00002800", + "frames": 28, + "offset": 22, + "words": 2 + } + }, "grid_x": 194, "grid_y": 196, "pin_functions": {}, @@ -1330959,7 +1331050,14 @@ "type": "PCIE_INT_INTERFACE_L" }, "PCIE_INT_INTERFACE_L_X80Y162": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00002800", + "frames": 28, + "offset": 24, + "words": 2 + } + }, "grid_x": 194, "grid_y": 195, "pin_functions": {}, @@ -1330968,7 +1331066,14 @@ "type": "PCIE_INT_INTERFACE_L" }, "PCIE_INT_INTERFACE_L_X80Y163": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00002800", + "frames": 28, + "offset": 26, + "words": 2 + } + }, "grid_x": 194, "grid_y": 194, "pin_functions": {}, @@ -1330977,7 +1331082,14 @@ "type": "PCIE_INT_INTERFACE_L" }, "PCIE_INT_INTERFACE_L_X80Y164": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00002800", + "frames": 28, + "offset": 28, + "words": 2 + } + }, "grid_x": 194, "grid_y": 193, "pin_functions": {}, @@ -1330986,7 +1331098,14 @@ "type": "PCIE_INT_INTERFACE_L" }, "PCIE_INT_INTERFACE_L_X80Y165": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00002800", + "frames": 28, + "offset": 30, + "words": 2 + } + }, "grid_x": 194, "grid_y": 192, "pin_functions": {}, @@ -1330995,7 +1331114,14 @@ "type": "PCIE_INT_INTERFACE_L" }, "PCIE_INT_INTERFACE_L_X80Y166": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00002800", + "frames": 28, + "offset": 32, + "words": 2 + } + }, "grid_x": 194, "grid_y": 191, "pin_functions": {}, @@ -1331004,7 +1331130,14 @@ "type": "PCIE_INT_INTERFACE_L" }, "PCIE_INT_INTERFACE_L_X80Y167": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00002800", + "frames": 28, + "offset": 34, + "words": 2 + } + }, "grid_x": 194, "grid_y": 190, "pin_functions": {}, @@ -1331013,7 +1331146,14 @@ "type": "PCIE_INT_INTERFACE_L" }, "PCIE_INT_INTERFACE_L_X80Y168": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00002800", + "frames": 28, + "offset": 36, + "words": 2 + } + }, "grid_x": 194, "grid_y": 189, "pin_functions": {}, @@ -1331022,7 +1331162,14 @@ "type": "PCIE_INT_INTERFACE_L" }, "PCIE_INT_INTERFACE_L_X80Y169": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00002800", + "frames": 28, + "offset": 38, + "words": 2 + } + }, "grid_x": 194, "grid_y": 188, "pin_functions": {}, @@ -1331031,7 +1331178,14 @@ "type": "PCIE_INT_INTERFACE_L" }, "PCIE_INT_INTERFACE_L_X80Y170": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00002800", + "frames": 28, + "offset": 40, + "words": 2 + } + }, "grid_x": 194, "grid_y": 187, "pin_functions": {}, @@ -1331040,7 +1331194,14 @@ "type": "PCIE_INT_INTERFACE_L" }, "PCIE_INT_INTERFACE_L_X80Y171": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00002800", + "frames": 28, + "offset": 42, + "words": 2 + } + }, "grid_x": 194, "grid_y": 186, "pin_functions": {}, @@ -1331049,7 +1331210,14 @@ "type": "PCIE_INT_INTERFACE_L" }, "PCIE_INT_INTERFACE_L_X80Y172": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00002800", + "frames": 28, + "offset": 44, + "words": 2 + } + }, "grid_x": 194, "grid_y": 185, "pin_functions": {}, @@ -1331058,7 +1331226,14 @@ "type": "PCIE_INT_INTERFACE_L" }, "PCIE_INT_INTERFACE_L_X80Y173": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00002800", + "frames": 28, + "offset": 46, + "words": 2 + } + }, "grid_x": 194, "grid_y": 184, "pin_functions": {}, @@ -1331067,7 +1331242,14 @@ "type": "PCIE_INT_INTERFACE_L" }, "PCIE_INT_INTERFACE_L_X80Y174": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00002800", + "frames": 28, + "offset": 48, + "words": 2 + } + }, "grid_x": 194, "grid_y": 183, "pin_functions": {}, @@ -1331076,7 +1331258,14 @@ "type": "PCIE_INT_INTERFACE_L" }, "PCIE_INT_INTERFACE_R_X77Y150": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00002680", + "frames": 28, + "offset": 0, + "words": 2 + } + }, "grid_x": 188, "grid_y": 207, "pin_functions": {}, @@ -1331085,7 +1331274,14 @@ "type": "PCIE_INT_INTERFACE_R" }, "PCIE_INT_INTERFACE_R_X77Y151": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00002680", + "frames": 28, + "offset": 2, + "words": 2 + } + }, "grid_x": 188, "grid_y": 206, "pin_functions": {}, @@ -1331094,7 +1331290,14 @@ "type": "PCIE_INT_INTERFACE_R" }, "PCIE_INT_INTERFACE_R_X77Y152": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00002680", + "frames": 28, + "offset": 4, + "words": 2 + } + }, "grid_x": 188, "grid_y": 205, "pin_functions": {}, @@ -1331103,7 +1331306,14 @@ "type": "PCIE_INT_INTERFACE_R" }, "PCIE_INT_INTERFACE_R_X77Y153": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00002680", + "frames": 28, + "offset": 6, + "words": 2 + } + }, "grid_x": 188, "grid_y": 204, "pin_functions": {}, @@ -1331112,7 +1331322,14 @@ "type": "PCIE_INT_INTERFACE_R" }, "PCIE_INT_INTERFACE_R_X77Y154": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00002680", + "frames": 28, + "offset": 8, + "words": 2 + } + }, "grid_x": 188, "grid_y": 203, "pin_functions": {}, @@ -1331121,7 +1331338,14 @@ "type": "PCIE_INT_INTERFACE_R" }, "PCIE_INT_INTERFACE_R_X77Y155": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00002680", + "frames": 28, + "offset": 10, + "words": 2 + } + }, "grid_x": 188, "grid_y": 202, "pin_functions": {}, @@ -1331130,7 +1331354,14 @@ "type": "PCIE_INT_INTERFACE_R" }, "PCIE_INT_INTERFACE_R_X77Y156": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00002680", + "frames": 28, + "offset": 12, + "words": 2 + } + }, "grid_x": 188, "grid_y": 201, "pin_functions": {}, @@ -1331139,7 +1331370,14 @@ "type": "PCIE_INT_INTERFACE_R" }, "PCIE_INT_INTERFACE_R_X77Y157": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00002680", + "frames": 28, + "offset": 14, + "words": 2 + } + }, "grid_x": 188, "grid_y": 200, "pin_functions": {}, @@ -1331148,7 +1331386,14 @@ "type": "PCIE_INT_INTERFACE_R" }, "PCIE_INT_INTERFACE_R_X77Y158": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00002680", + "frames": 28, + "offset": 16, + "words": 2 + } + }, "grid_x": 188, "grid_y": 199, "pin_functions": {}, @@ -1331157,7 +1331402,14 @@ "type": "PCIE_INT_INTERFACE_R" }, "PCIE_INT_INTERFACE_R_X77Y159": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00002680", + "frames": 28, + "offset": 18, + "words": 2 + } + }, "grid_x": 188, "grid_y": 198, "pin_functions": {}, @@ -1331166,7 +1331418,14 @@ "type": "PCIE_INT_INTERFACE_R" }, "PCIE_INT_INTERFACE_R_X77Y160": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00002680", + "frames": 28, + "offset": 20, + "words": 2 + } + }, "grid_x": 188, "grid_y": 197, "pin_functions": {}, @@ -1331175,7 +1331434,14 @@ "type": "PCIE_INT_INTERFACE_R" }, "PCIE_INT_INTERFACE_R_X77Y161": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00002680", + "frames": 28, + "offset": 22, + "words": 2 + } + }, "grid_x": 188, "grid_y": 196, "pin_functions": {}, @@ -1331184,7 +1331450,14 @@ "type": "PCIE_INT_INTERFACE_R" }, "PCIE_INT_INTERFACE_R_X77Y162": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00002680", + "frames": 28, + "offset": 24, + "words": 2 + } + }, "grid_x": 188, "grid_y": 195, "pin_functions": {}, @@ -1331193,7 +1331466,14 @@ "type": "PCIE_INT_INTERFACE_R" }, "PCIE_INT_INTERFACE_R_X77Y163": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00002680", + "frames": 28, + "offset": 26, + "words": 2 + } + }, "grid_x": 188, "grid_y": 194, "pin_functions": {}, @@ -1331202,7 +1331482,14 @@ "type": "PCIE_INT_INTERFACE_R" }, "PCIE_INT_INTERFACE_R_X77Y164": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00002680", + "frames": 28, + "offset": 28, + "words": 2 + } + }, "grid_x": 188, "grid_y": 193, "pin_functions": {}, @@ -1331211,7 +1331498,14 @@ "type": "PCIE_INT_INTERFACE_R" }, "PCIE_INT_INTERFACE_R_X77Y165": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00002680", + "frames": 28, + "offset": 30, + "words": 2 + } + }, "grid_x": 188, "grid_y": 192, "pin_functions": {}, @@ -1331220,7 +1331514,14 @@ "type": "PCIE_INT_INTERFACE_R" }, "PCIE_INT_INTERFACE_R_X77Y166": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00002680", + "frames": 28, + "offset": 32, + "words": 2 + } + }, "grid_x": 188, "grid_y": 191, "pin_functions": {}, @@ -1331229,7 +1331530,14 @@ "type": "PCIE_INT_INTERFACE_R" }, "PCIE_INT_INTERFACE_R_X77Y167": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00002680", + "frames": 28, + "offset": 34, + "words": 2 + } + }, "grid_x": 188, "grid_y": 190, "pin_functions": {}, @@ -1331238,7 +1331546,14 @@ "type": "PCIE_INT_INTERFACE_R" }, "PCIE_INT_INTERFACE_R_X77Y168": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00002680", + "frames": 28, + "offset": 36, + "words": 2 + } + }, "grid_x": 188, "grid_y": 189, "pin_functions": {}, @@ -1331247,7 +1331562,14 @@ "type": "PCIE_INT_INTERFACE_R" }, "PCIE_INT_INTERFACE_R_X77Y169": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00002680", + "frames": 28, + "offset": 38, + "words": 2 + } + }, "grid_x": 188, "grid_y": 188, "pin_functions": {}, @@ -1331256,7 +1331578,14 @@ "type": "PCIE_INT_INTERFACE_R" }, "PCIE_INT_INTERFACE_R_X77Y170": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00002680", + "frames": 28, + "offset": 40, + "words": 2 + } + }, "grid_x": 188, "grid_y": 187, "pin_functions": {}, @@ -1331265,7 +1331594,14 @@ "type": "PCIE_INT_INTERFACE_R" }, "PCIE_INT_INTERFACE_R_X77Y171": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00002680", + "frames": 28, + "offset": 42, + "words": 2 + } + }, "grid_x": 188, "grid_y": 186, "pin_functions": {}, @@ -1331274,7 +1331610,14 @@ "type": "PCIE_INT_INTERFACE_R" }, "PCIE_INT_INTERFACE_R_X77Y172": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00002680", + "frames": 28, + "offset": 44, + "words": 2 + } + }, "grid_x": 188, "grid_y": 185, "pin_functions": {}, @@ -1331283,7 +1331626,14 @@ "type": "PCIE_INT_INTERFACE_R" }, "PCIE_INT_INTERFACE_R_X77Y173": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00002680", + "frames": 28, + "offset": 46, + "words": 2 + } + }, "grid_x": 188, "grid_y": 184, "pin_functions": {}, @@ -1331292,7 +1331642,14 @@ "type": "PCIE_INT_INTERFACE_R" }, "PCIE_INT_INTERFACE_R_X77Y174": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00002680", + "frames": 28, + "offset": 48, + "words": 2 + } + }, "grid_x": 188, "grid_y": 183, "pin_functions": {}, @@ -1334949,14 +1335306,7 @@ "type": "RIOI" }, "RIOI_X95Y9": { - "bits": { - "CLB_IO_CLK": { - "baseaddr": "0x00442F80", - "frames": 42, - "offset": 18, - "words": 4 - } - }, + "bits": {}, "clock_region": "X1Y0", "grid_x": 235, "grid_y": 354, diff --git a/kintex7/xc7k480t/tilegrid.json b/kintex7/xc7k480t/tilegrid.json index 8c73ec6..d55f9b7 100644 --- a/kintex7/xc7k480t/tilegrid.json +++ b/kintex7/xc7k480t/tilegrid.json @@ -856242,7 +856242,14 @@ "type": "DSP_R" }, "GTX_CHANNEL_0_X309Y6": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00463D80", + "frames": 32, + "offset": 0, + "words": 22 + } + }, "clock_region": "X1Y0", "grid_x": 309, "grid_y": 410, @@ -856263,7 +856270,14 @@ "type": "GTX_CHANNEL_0" }, "GTX_CHANNEL_0_X309Y58": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00443D80", + "frames": 32, + "offset": 0, + "words": 22 + } + }, "clock_region": "X1Y1", "grid_x": 309, "grid_y": 358, @@ -856284,7 +856298,14 @@ "type": "GTX_CHANNEL_0" }, "GTX_CHANNEL_0_X309Y110": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00423D80", + "frames": 32, + "offset": 0, + "words": 22 + } + }, "clock_region": "X1Y2", "grid_x": 309, "grid_y": 306, @@ -856305,7 +856326,14 @@ "type": "GTX_CHANNEL_0" }, "GTX_CHANNEL_0_X309Y162": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00403D80", + "frames": 32, + "offset": 0, + "words": 22 + } + }, "clock_region": "X1Y3", "grid_x": 309, "grid_y": 254, @@ -856326,7 +856354,14 @@ "type": "GTX_CHANNEL_0" }, "GTX_CHANNEL_0_X309Y214": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00003D80", + "frames": 32, + "offset": 0, + "words": 22 + } + }, "clock_region": "X1Y4", "grid_x": 309, "grid_y": 202, @@ -856347,7 +856382,14 @@ "type": "GTX_CHANNEL_0" }, "GTX_CHANNEL_0_X309Y266": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00023D80", + "frames": 32, + "offset": 0, + "words": 22 + } + }, "clock_region": "X1Y5", "grid_x": 309, "grid_y": 150, @@ -856368,7 +856410,14 @@ "type": "GTX_CHANNEL_0" }, "GTX_CHANNEL_0_X309Y318": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00043D80", + "frames": 32, + "offset": 0, + "words": 22 + } + }, "clock_region": "X1Y6", "grid_x": 309, "grid_y": 98, @@ -856389,7 +856438,14 @@ "type": "GTX_CHANNEL_0" }, "GTX_CHANNEL_0_X309Y370": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00063D80", + "frames": 32, + "offset": 0, + "words": 22 + } + }, "clock_region": "X1Y7", "grid_x": 309, "grid_y": 46, @@ -856410,7 +856466,14 @@ "type": "GTX_CHANNEL_0" }, "GTX_CHANNEL_1_X309Y17": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00463D80", + "frames": 32, + "offset": 22, + "words": 22 + } + }, "clock_region": "X1Y0", "grid_x": 309, "grid_y": 399, @@ -856431,7 +856494,14 @@ "type": "GTX_CHANNEL_1" }, "GTX_CHANNEL_1_X309Y69": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00443D80", + "frames": 32, + "offset": 22, + "words": 22 + } + }, "clock_region": "X1Y1", "grid_x": 309, "grid_y": 347, @@ -856452,7 +856522,14 @@ "type": "GTX_CHANNEL_1" }, "GTX_CHANNEL_1_X309Y121": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00423D80", + "frames": 32, + "offset": 22, + "words": 22 + } + }, "clock_region": "X1Y2", "grid_x": 309, "grid_y": 295, @@ -856473,7 +856550,14 @@ "type": "GTX_CHANNEL_1" }, "GTX_CHANNEL_1_X309Y173": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00403D80", + "frames": 32, + "offset": 22, + "words": 22 + } + }, "clock_region": "X1Y3", "grid_x": 309, "grid_y": 243, @@ -856494,7 +856578,14 @@ "type": "GTX_CHANNEL_1" }, "GTX_CHANNEL_1_X309Y225": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00003D80", + "frames": 32, + "offset": 22, + "words": 22 + } + }, "clock_region": "X1Y4", "grid_x": 309, "grid_y": 191, @@ -856515,7 +856606,14 @@ "type": "GTX_CHANNEL_1" }, "GTX_CHANNEL_1_X309Y277": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00023D80", + "frames": 32, + "offset": 22, + "words": 22 + } + }, "clock_region": "X1Y5", "grid_x": 309, "grid_y": 139, @@ -856536,7 +856634,14 @@ "type": "GTX_CHANNEL_1" }, "GTX_CHANNEL_1_X309Y329": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00043D80", + "frames": 32, + "offset": 22, + "words": 22 + } + }, "clock_region": "X1Y6", "grid_x": 309, "grid_y": 87, @@ -856557,7 +856662,14 @@ "type": "GTX_CHANNEL_1" }, "GTX_CHANNEL_1_X309Y381": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00063D80", + "frames": 32, + "offset": 22, + "words": 22 + } + }, "clock_region": "X1Y7", "grid_x": 309, "grid_y": 35, @@ -856578,7 +856690,14 @@ "type": "GTX_CHANNEL_1" }, "GTX_CHANNEL_2_X309Y35": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00463D80", + "frames": 32, + "offset": 57, + "words": 22 + } + }, "clock_region": "X1Y0", "grid_x": 309, "grid_y": 381, @@ -856599,7 +856718,14 @@ "type": "GTX_CHANNEL_2" }, "GTX_CHANNEL_2_X309Y87": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00443D80", + "frames": 32, + "offset": 57, + "words": 22 + } + }, "clock_region": "X1Y1", "grid_x": 309, "grid_y": 329, @@ -856620,7 +856746,14 @@ "type": "GTX_CHANNEL_2" }, "GTX_CHANNEL_2_X309Y139": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00423D80", + "frames": 32, + "offset": 57, + "words": 22 + } + }, "clock_region": "X1Y2", "grid_x": 309, "grid_y": 277, @@ -856641,7 +856774,14 @@ "type": "GTX_CHANNEL_2" }, "GTX_CHANNEL_2_X309Y191": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00403D80", + "frames": 32, + "offset": 57, + "words": 22 + } + }, "clock_region": "X1Y3", "grid_x": 309, "grid_y": 225, @@ -856662,7 +856802,14 @@ "type": "GTX_CHANNEL_2" }, "GTX_CHANNEL_2_X309Y243": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00003D80", + "frames": 32, + "offset": 57, + "words": 22 + } + }, "clock_region": "X1Y4", "grid_x": 309, "grid_y": 173, @@ -856683,7 +856830,14 @@ "type": "GTX_CHANNEL_2" }, "GTX_CHANNEL_2_X309Y295": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00023D80", + "frames": 32, + "offset": 57, + "words": 22 + } + }, "clock_region": "X1Y5", "grid_x": 309, "grid_y": 121, @@ -856704,7 +856858,14 @@ "type": "GTX_CHANNEL_2" }, "GTX_CHANNEL_2_X309Y347": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00043D80", + "frames": 32, + "offset": 57, + "words": 22 + } + }, "clock_region": "X1Y6", "grid_x": 309, "grid_y": 69, @@ -856725,7 +856886,14 @@ "type": "GTX_CHANNEL_2" }, "GTX_CHANNEL_2_X309Y399": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00063D80", + "frames": 32, + "offset": 57, + "words": 22 + } + }, "clock_region": "X1Y7", "grid_x": 309, "grid_y": 17, @@ -856746,7 +856914,14 @@ "type": "GTX_CHANNEL_2" }, "GTX_CHANNEL_3_X309Y46": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00463D80", + "frames": 32, + "offset": 79, + "words": 22 + } + }, "clock_region": "X1Y0", "grid_x": 309, "grid_y": 370, @@ -856767,7 +856942,14 @@ "type": "GTX_CHANNEL_3" }, "GTX_CHANNEL_3_X309Y98": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00443D80", + "frames": 32, + "offset": 79, + "words": 22 + } + }, "clock_region": "X1Y1", "grid_x": 309, "grid_y": 318, @@ -856788,7 +856970,14 @@ "type": "GTX_CHANNEL_3" }, "GTX_CHANNEL_3_X309Y150": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00423D80", + "frames": 32, + "offset": 79, + "words": 22 + } + }, "clock_region": "X1Y2", "grid_x": 309, "grid_y": 266, @@ -856809,7 +856998,14 @@ "type": "GTX_CHANNEL_3" }, "GTX_CHANNEL_3_X309Y202": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00403D80", + "frames": 32, + "offset": 79, + "words": 22 + } + }, "clock_region": "X1Y3", "grid_x": 309, "grid_y": 214, @@ -856830,7 +857026,14 @@ "type": "GTX_CHANNEL_3" }, "GTX_CHANNEL_3_X309Y254": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00003D80", + "frames": 32, + "offset": 79, + "words": 22 + } + }, "clock_region": "X1Y4", "grid_x": 309, "grid_y": 162, @@ -856851,7 +857054,14 @@ "type": "GTX_CHANNEL_3" }, "GTX_CHANNEL_3_X309Y306": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00023D80", + "frames": 32, + "offset": 79, + "words": 22 + } + }, "clock_region": "X1Y5", "grid_x": 309, "grid_y": 110, @@ -856872,7 +857082,14 @@ "type": "GTX_CHANNEL_3" }, "GTX_CHANNEL_3_X309Y358": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00043D80", + "frames": 32, + "offset": 79, + "words": 22 + } + }, "clock_region": "X1Y6", "grid_x": 309, "grid_y": 58, @@ -856893,7 +857110,14 @@ "type": "GTX_CHANNEL_3" }, "GTX_CHANNEL_3_X309Y410": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00063D80", + "frames": 32, + "offset": 79, + "words": 22 + } + }, "clock_region": "X1Y7", "grid_x": 309, "grid_y": 6, @@ -856914,7 +857138,14 @@ "type": "GTX_CHANNEL_3" }, "GTX_COMMON_X309Y23": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00463D80", + "frames": 32, + "offset": 0, + "words": 101 + } + }, "clock_region": "X1Y0", "grid_x": 309, "grid_y": 393, @@ -856937,7 +857168,14 @@ "type": "GTX_COMMON" }, "GTX_COMMON_X309Y75": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00443D80", + "frames": 32, + "offset": 0, + "words": 101 + } + }, "clock_region": "X1Y1", "grid_x": 309, "grid_y": 341, @@ -856960,7 +857198,14 @@ "type": "GTX_COMMON" }, "GTX_COMMON_X309Y127": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00423D80", + "frames": 32, + "offset": 0, + "words": 101 + } + }, "clock_region": "X1Y2", "grid_x": 309, "grid_y": 289, @@ -856983,7 +857228,14 @@ "type": "GTX_COMMON" }, "GTX_COMMON_X309Y179": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00403D80", + "frames": 32, + "offset": 0, + "words": 101 + } + }, "clock_region": "X1Y3", "grid_x": 309, "grid_y": 237, @@ -857006,7 +857258,14 @@ "type": "GTX_COMMON" }, "GTX_COMMON_X309Y231": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00003D80", + "frames": 32, + "offset": 0, + "words": 101 + } + }, "clock_region": "X1Y4", "grid_x": 309, "grid_y": 185, @@ -857029,7 +857288,14 @@ "type": "GTX_COMMON" }, "GTX_COMMON_X309Y283": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00023D80", + "frames": 32, + "offset": 0, + "words": 101 + } + }, "clock_region": "X1Y5", "grid_x": 309, "grid_y": 133, @@ -857052,7 +857318,14 @@ "type": "GTX_COMMON" }, "GTX_COMMON_X309Y335": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00043D80", + "frames": 32, + "offset": 0, + "words": 101 + } + }, "clock_region": "X1Y6", "grid_x": 309, "grid_y": 81, @@ -857075,7 +857348,14 @@ "type": "GTX_COMMON" }, "GTX_COMMON_X309Y387": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00063D80", + "frames": 32, + "offset": 0, + "words": 101 + } + }, "clock_region": "X1Y7", "grid_x": 309, "grid_y": 29, @@ -857098,7 +857378,14 @@ "type": "GTX_COMMON" }, "GTX_INT_INTERFACE_X123Y0": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00463D80", + "frames": 28, + "offset": -2, + "words": 2 + } + }, "grid_x": 306, "grid_y": 415, "pin_functions": {}, @@ -857107,7 +857394,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y1": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00463D80", + "frames": 28, + "offset": 0, + "words": 2 + } + }, "grid_x": 306, "grid_y": 414, "pin_functions": {}, @@ -857116,7 +857410,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y2": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00463D80", + "frames": 28, + "offset": 2, + "words": 2 + } + }, "grid_x": 306, "grid_y": 413, "pin_functions": {}, @@ -857125,7 +857426,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y3": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00463D80", + "frames": 28, + "offset": 4, + "words": 2 + } + }, "grid_x": 306, "grid_y": 412, "pin_functions": {}, @@ -857134,7 +857442,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y4": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00463D80", + "frames": 28, + "offset": 6, + "words": 2 + } + }, "grid_x": 306, "grid_y": 411, "pin_functions": {}, @@ -857143,7 +857458,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y5": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00463D80", + "frames": 28, + "offset": 8, + "words": 2 + } + }, "grid_x": 306, "grid_y": 410, "pin_functions": {}, @@ -857152,7 +857474,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y6": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00463D80", + "frames": 28, + "offset": 10, + "words": 2 + } + }, "grid_x": 306, "grid_y": 409, "pin_functions": {}, @@ -857161,7 +857490,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y7": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00463D80", + "frames": 28, + "offset": 12, + "words": 2 + } + }, "grid_x": 306, "grid_y": 408, "pin_functions": {}, @@ -857170,7 +857506,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y8": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00463D80", + "frames": 28, + "offset": 14, + "words": 2 + } + }, "grid_x": 306, "grid_y": 407, "pin_functions": {}, @@ -857179,7 +857522,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y9": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00463D80", + "frames": 28, + "offset": 16, + "words": 2 + } + }, "grid_x": 306, "grid_y": 406, "pin_functions": {}, @@ -857188,7 +857538,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y10": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00463D80", + "frames": 28, + "offset": 18, + "words": 2 + } + }, "grid_x": 306, "grid_y": 405, "pin_functions": {}, @@ -857197,7 +857554,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y11": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00463D80", + "frames": 28, + "offset": 20, + "words": 2 + } + }, "grid_x": 306, "grid_y": 404, "pin_functions": {}, @@ -857206,7 +857570,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y12": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00463D80", + "frames": 28, + "offset": 22, + "words": 2 + } + }, "grid_x": 306, "grid_y": 403, "pin_functions": {}, @@ -857215,7 +857586,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y13": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00463D80", + "frames": 28, + "offset": 24, + "words": 2 + } + }, "grid_x": 306, "grid_y": 402, "pin_functions": {}, @@ -857224,7 +857602,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y14": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00463D80", + "frames": 28, + "offset": 26, + "words": 2 + } + }, "grid_x": 306, "grid_y": 401, "pin_functions": {}, @@ -857233,7 +857618,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y15": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00463D80", + "frames": 28, + "offset": 28, + "words": 2 + } + }, "grid_x": 306, "grid_y": 400, "pin_functions": {}, @@ -857242,7 +857634,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y16": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00463D80", + "frames": 28, + "offset": 30, + "words": 2 + } + }, "grid_x": 306, "grid_y": 399, "pin_functions": {}, @@ -857251,7 +857650,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y17": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00463D80", + "frames": 28, + "offset": 32, + "words": 2 + } + }, "grid_x": 306, "grid_y": 398, "pin_functions": {}, @@ -857260,7 +857666,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y18": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00463D80", + "frames": 28, + "offset": 34, + "words": 2 + } + }, "grid_x": 306, "grid_y": 397, "pin_functions": {}, @@ -857269,7 +857682,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y19": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00463D80", + "frames": 28, + "offset": 36, + "words": 2 + } + }, "grid_x": 306, "grid_y": 396, "pin_functions": {}, @@ -857278,7 +857698,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y20": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00463D80", + "frames": 28, + "offset": 38, + "words": 2 + } + }, "grid_x": 306, "grid_y": 395, "pin_functions": {}, @@ -857287,7 +857714,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y21": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00463D80", + "frames": 28, + "offset": 40, + "words": 2 + } + }, "grid_x": 306, "grid_y": 394, "pin_functions": {}, @@ -857296,7 +857730,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y22": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00463D80", + "frames": 28, + "offset": 42, + "words": 2 + } + }, "grid_x": 306, "grid_y": 393, "pin_functions": {}, @@ -857305,7 +857746,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y23": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00463D80", + "frames": 28, + "offset": 44, + "words": 2 + } + }, "grid_x": 306, "grid_y": 392, "pin_functions": {}, @@ -857314,7 +857762,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y24": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00463D80", + "frames": 28, + "offset": 46, + "words": 2 + } + }, "grid_x": 306, "grid_y": 391, "pin_functions": {}, @@ -857323,7 +857778,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y25": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00463D80", + "frames": 28, + "offset": 49, + "words": 2 + } + }, "grid_x": 306, "grid_y": 389, "pin_functions": {}, @@ -857332,7 +857794,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y26": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00463D80", + "frames": 28, + "offset": 51, + "words": 2 + } + }, "grid_x": 306, "grid_y": 388, "pin_functions": {}, @@ -857341,7 +857810,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y27": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00463D80", + "frames": 28, + "offset": 53, + "words": 2 + } + }, "grid_x": 306, "grid_y": 387, "pin_functions": {}, @@ -857350,7 +857826,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y28": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00463D80", + "frames": 28, + "offset": 55, + "words": 2 + } + }, "grid_x": 306, "grid_y": 386, "pin_functions": {}, @@ -857359,7 +857842,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y29": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00463D80", + "frames": 28, + "offset": 57, + "words": 2 + } + }, "grid_x": 306, "grid_y": 385, "pin_functions": {}, @@ -857368,7 +857858,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y30": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00463D80", + "frames": 28, + "offset": 59, + "words": 2 + } + }, "grid_x": 306, "grid_y": 384, "pin_functions": {}, @@ -857377,7 +857874,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y31": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00463D80", + "frames": 28, + "offset": 61, + "words": 2 + } + }, "grid_x": 306, "grid_y": 383, "pin_functions": {}, @@ -857386,7 +857890,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y32": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00463D80", + "frames": 28, + "offset": 63, + "words": 2 + } + }, "grid_x": 306, "grid_y": 382, "pin_functions": {}, @@ -857395,7 +857906,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y33": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00463D80", + "frames": 28, + "offset": 65, + "words": 2 + } + }, "grid_x": 306, "grid_y": 381, "pin_functions": {}, @@ -857404,7 +857922,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y34": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00463D80", + "frames": 28, + "offset": 67, + "words": 2 + } + }, "grid_x": 306, "grid_y": 380, "pin_functions": {}, @@ -857413,7 +857938,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y35": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00463D80", + "frames": 28, + "offset": 69, + "words": 2 + } + }, "grid_x": 306, "grid_y": 379, "pin_functions": {}, @@ -857422,7 +857954,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y36": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00463D80", + "frames": 28, + "offset": 71, + "words": 2 + } + }, "grid_x": 306, "grid_y": 378, "pin_functions": {}, @@ -857431,7 +857970,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y37": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00463D80", + "frames": 28, + "offset": 73, + "words": 2 + } + }, "grid_x": 306, "grid_y": 377, "pin_functions": {}, @@ -857440,7 +857986,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y38": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00463D80", + "frames": 28, + "offset": 75, + "words": 2 + } + }, "grid_x": 306, "grid_y": 376, "pin_functions": {}, @@ -857449,7 +858002,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y39": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00463D80", + "frames": 28, + "offset": 77, + "words": 2 + } + }, "grid_x": 306, "grid_y": 375, "pin_functions": {}, @@ -857458,7 +858018,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y40": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00463D80", + "frames": 28, + "offset": 79, + "words": 2 + } + }, "grid_x": 306, "grid_y": 374, "pin_functions": {}, @@ -857467,7 +858034,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y41": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00463D80", + "frames": 28, + "offset": 81, + "words": 2 + } + }, "grid_x": 306, "grid_y": 373, "pin_functions": {}, @@ -857476,7 +858050,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y42": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00463D80", + "frames": 28, + "offset": 83, + "words": 2 + } + }, "grid_x": 306, "grid_y": 372, "pin_functions": {}, @@ -857485,7 +858066,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y43": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00463D80", + "frames": 28, + "offset": 85, + "words": 2 + } + }, "grid_x": 306, "grid_y": 371, "pin_functions": {}, @@ -857494,7 +858082,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y44": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00463D80", + "frames": 28, + "offset": 87, + "words": 2 + } + }, "grid_x": 306, "grid_y": 370, "pin_functions": {}, @@ -857503,7 +858098,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y45": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00463D80", + "frames": 28, + "offset": 89, + "words": 2 + } + }, "grid_x": 306, "grid_y": 369, "pin_functions": {}, @@ -857512,7 +858114,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y46": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00463D80", + "frames": 28, + "offset": 91, + "words": 2 + } + }, "grid_x": 306, "grid_y": 368, "pin_functions": {}, @@ -857521,7 +858130,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y47": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00463D80", + "frames": 28, + "offset": 93, + "words": 2 + } + }, "grid_x": 306, "grid_y": 367, "pin_functions": {}, @@ -857530,7 +858146,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y48": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00463D80", + "frames": 28, + "offset": 95, + "words": 2 + } + }, "grid_x": 306, "grid_y": 366, "pin_functions": {}, @@ -857539,7 +858162,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y49": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00463D80", + "frames": 28, + "offset": 97, + "words": 2 + } + }, "grid_x": 306, "grid_y": 365, "pin_functions": {}, @@ -857548,7 +858178,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y50": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00443D80", + "frames": 28, + "offset": -2, + "words": 2 + } + }, "grid_x": 306, "grid_y": 363, "pin_functions": {}, @@ -857557,7 +858194,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y51": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00443D80", + "frames": 28, + "offset": 0, + "words": 2 + } + }, "grid_x": 306, "grid_y": 362, "pin_functions": {}, @@ -857566,7 +858210,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y52": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00443D80", + "frames": 28, + "offset": 2, + "words": 2 + } + }, "grid_x": 306, "grid_y": 361, "pin_functions": {}, @@ -857575,7 +858226,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y53": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00443D80", + "frames": 28, + "offset": 4, + "words": 2 + } + }, "grid_x": 306, "grid_y": 360, "pin_functions": {}, @@ -857584,7 +858242,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y54": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00443D80", + "frames": 28, + "offset": 6, + "words": 2 + } + }, "grid_x": 306, "grid_y": 359, "pin_functions": {}, @@ -857593,7 +858258,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y55": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00443D80", + "frames": 28, + "offset": 8, + "words": 2 + } + }, "grid_x": 306, "grid_y": 358, "pin_functions": {}, @@ -857602,7 +858274,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y56": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00443D80", + "frames": 28, + "offset": 10, + "words": 2 + } + }, "grid_x": 306, "grid_y": 357, "pin_functions": {}, @@ -857611,7 +858290,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y57": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00443D80", + "frames": 28, + "offset": 12, + "words": 2 + } + }, "grid_x": 306, "grid_y": 356, "pin_functions": {}, @@ -857620,7 +858306,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y58": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00443D80", + "frames": 28, + "offset": 14, + "words": 2 + } + }, "grid_x": 306, "grid_y": 355, "pin_functions": {}, @@ -857629,7 +858322,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y59": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00443D80", + "frames": 28, + "offset": 16, + "words": 2 + } + }, "grid_x": 306, "grid_y": 354, "pin_functions": {}, @@ -857638,7 +858338,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y60": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00443D80", + "frames": 28, + "offset": 18, + "words": 2 + } + }, "grid_x": 306, "grid_y": 353, "pin_functions": {}, @@ -857647,7 +858354,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y61": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00443D80", + "frames": 28, + "offset": 20, + "words": 2 + } + }, "grid_x": 306, "grid_y": 352, "pin_functions": {}, @@ -857656,7 +858370,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y62": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00443D80", + "frames": 28, + "offset": 22, + "words": 2 + } + }, "grid_x": 306, "grid_y": 351, "pin_functions": {}, @@ -857665,7 +858386,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y63": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00443D80", + "frames": 28, + "offset": 24, + "words": 2 + } + }, "grid_x": 306, "grid_y": 350, "pin_functions": {}, @@ -857674,7 +858402,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y64": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00443D80", + "frames": 28, + "offset": 26, + "words": 2 + } + }, "grid_x": 306, "grid_y": 349, "pin_functions": {}, @@ -857683,7 +858418,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y65": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00443D80", + "frames": 28, + "offset": 28, + "words": 2 + } + }, "grid_x": 306, "grid_y": 348, "pin_functions": {}, @@ -857692,7 +858434,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y66": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00443D80", + "frames": 28, + "offset": 30, + "words": 2 + } + }, "grid_x": 306, "grid_y": 347, "pin_functions": {}, @@ -857701,7 +858450,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y67": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00443D80", + "frames": 28, + "offset": 32, + "words": 2 + } + }, "grid_x": 306, "grid_y": 346, "pin_functions": {}, @@ -857710,7 +858466,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y68": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00443D80", + "frames": 28, + "offset": 34, + "words": 2 + } + }, "grid_x": 306, "grid_y": 345, "pin_functions": {}, @@ -857719,7 +858482,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y69": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00443D80", + "frames": 28, + "offset": 36, + "words": 2 + } + }, "grid_x": 306, "grid_y": 344, "pin_functions": {}, @@ -857728,7 +858498,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y70": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00443D80", + "frames": 28, + "offset": 38, + "words": 2 + } + }, "grid_x": 306, "grid_y": 343, "pin_functions": {}, @@ -857737,7 +858514,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y71": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00443D80", + "frames": 28, + "offset": 40, + "words": 2 + } + }, "grid_x": 306, "grid_y": 342, "pin_functions": {}, @@ -857746,7 +858530,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y72": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00443D80", + "frames": 28, + "offset": 42, + "words": 2 + } + }, "grid_x": 306, "grid_y": 341, "pin_functions": {}, @@ -857755,7 +858546,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y73": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00443D80", + "frames": 28, + "offset": 44, + "words": 2 + } + }, "grid_x": 306, "grid_y": 340, "pin_functions": {}, @@ -857764,7 +858562,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y74": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00443D80", + "frames": 28, + "offset": 46, + "words": 2 + } + }, "grid_x": 306, "grid_y": 339, "pin_functions": {}, @@ -857773,7 +858578,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y75": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00443D80", + "frames": 28, + "offset": 49, + "words": 2 + } + }, "grid_x": 306, "grid_y": 337, "pin_functions": {}, @@ -857782,7 +858594,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y76": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00443D80", + "frames": 28, + "offset": 51, + "words": 2 + } + }, "grid_x": 306, "grid_y": 336, "pin_functions": {}, @@ -857791,7 +858610,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y77": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00443D80", + "frames": 28, + "offset": 53, + "words": 2 + } + }, "grid_x": 306, "grid_y": 335, "pin_functions": {}, @@ -857800,7 +858626,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y78": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00443D80", + "frames": 28, + "offset": 55, + "words": 2 + } + }, "grid_x": 306, "grid_y": 334, "pin_functions": {}, @@ -857809,7 +858642,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y79": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00443D80", + "frames": 28, + "offset": 57, + "words": 2 + } + }, "grid_x": 306, "grid_y": 333, "pin_functions": {}, @@ -857818,7 +858658,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y80": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00443D80", + "frames": 28, + "offset": 59, + "words": 2 + } + }, "grid_x": 306, "grid_y": 332, "pin_functions": {}, @@ -857827,7 +858674,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y81": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00443D80", + "frames": 28, + "offset": 61, + "words": 2 + } + }, "grid_x": 306, "grid_y": 331, "pin_functions": {}, @@ -857836,7 +858690,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y82": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00443D80", + "frames": 28, + "offset": 63, + "words": 2 + } + }, "grid_x": 306, "grid_y": 330, "pin_functions": {}, @@ -857845,7 +858706,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y83": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00443D80", + "frames": 28, + "offset": 65, + "words": 2 + } + }, "grid_x": 306, "grid_y": 329, "pin_functions": {}, @@ -857854,7 +858722,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y84": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00443D80", + "frames": 28, + "offset": 67, + "words": 2 + } + }, "grid_x": 306, "grid_y": 328, "pin_functions": {}, @@ -857863,7 +858738,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y85": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00443D80", + "frames": 28, + "offset": 69, + "words": 2 + } + }, "grid_x": 306, "grid_y": 327, "pin_functions": {}, @@ -857872,7 +858754,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y86": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00443D80", + "frames": 28, + "offset": 71, + "words": 2 + } + }, "grid_x": 306, "grid_y": 326, "pin_functions": {}, @@ -857881,7 +858770,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y87": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00443D80", + "frames": 28, + "offset": 73, + "words": 2 + } + }, "grid_x": 306, "grid_y": 325, "pin_functions": {}, @@ -857890,7 +858786,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y88": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00443D80", + "frames": 28, + "offset": 75, + "words": 2 + } + }, "grid_x": 306, "grid_y": 324, "pin_functions": {}, @@ -857899,7 +858802,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y89": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00443D80", + "frames": 28, + "offset": 77, + "words": 2 + } + }, "grid_x": 306, "grid_y": 323, "pin_functions": {}, @@ -857908,7 +858818,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y90": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00443D80", + "frames": 28, + "offset": 79, + "words": 2 + } + }, "grid_x": 306, "grid_y": 322, "pin_functions": {}, @@ -857917,7 +858834,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y91": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00443D80", + "frames": 28, + "offset": 81, + "words": 2 + } + }, "grid_x": 306, "grid_y": 321, "pin_functions": {}, @@ -857926,7 +858850,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y92": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00443D80", + "frames": 28, + "offset": 83, + "words": 2 + } + }, "grid_x": 306, "grid_y": 320, "pin_functions": {}, @@ -857935,7 +858866,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y93": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00443D80", + "frames": 28, + "offset": 85, + "words": 2 + } + }, "grid_x": 306, "grid_y": 319, "pin_functions": {}, @@ -857944,7 +858882,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y94": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00443D80", + "frames": 28, + "offset": 87, + "words": 2 + } + }, "grid_x": 306, "grid_y": 318, "pin_functions": {}, @@ -857953,7 +858898,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y95": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00443D80", + "frames": 28, + "offset": 89, + "words": 2 + } + }, "grid_x": 306, "grid_y": 317, "pin_functions": {}, @@ -857962,7 +858914,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y96": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00443D80", + "frames": 28, + "offset": 91, + "words": 2 + } + }, "grid_x": 306, "grid_y": 316, "pin_functions": {}, @@ -857971,7 +858930,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y97": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00443D80", + "frames": 28, + "offset": 93, + "words": 2 + } + }, "grid_x": 306, "grid_y": 315, "pin_functions": {}, @@ -857980,7 +858946,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y98": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00443D80", + "frames": 28, + "offset": 95, + "words": 2 + } + }, "grid_x": 306, "grid_y": 314, "pin_functions": {}, @@ -857989,7 +858962,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y99": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00443D80", + "frames": 28, + "offset": 97, + "words": 2 + } + }, "grid_x": 306, "grid_y": 313, "pin_functions": {}, @@ -857998,7 +858978,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y100": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00423D80", + "frames": 28, + "offset": -2, + "words": 2 + } + }, "grid_x": 306, "grid_y": 311, "pin_functions": {}, @@ -858007,7 +858994,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y101": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00423D80", + "frames": 28, + "offset": 0, + "words": 2 + } + }, "grid_x": 306, "grid_y": 310, "pin_functions": {}, @@ -858016,7 +859010,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y102": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00423D80", + "frames": 28, + "offset": 2, + "words": 2 + } + }, "grid_x": 306, "grid_y": 309, "pin_functions": {}, @@ -858025,7 +859026,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y103": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00423D80", + "frames": 28, + "offset": 4, + "words": 2 + } + }, "grid_x": 306, "grid_y": 308, "pin_functions": {}, @@ -858034,7 +859042,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y104": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00423D80", + "frames": 28, + "offset": 6, + "words": 2 + } + }, "grid_x": 306, "grid_y": 307, "pin_functions": {}, @@ -858043,7 +859058,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y105": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00423D80", + "frames": 28, + "offset": 8, + "words": 2 + } + }, "grid_x": 306, "grid_y": 306, "pin_functions": {}, @@ -858052,7 +859074,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y106": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00423D80", + "frames": 28, + "offset": 10, + "words": 2 + } + }, "grid_x": 306, "grid_y": 305, "pin_functions": {}, @@ -858061,7 +859090,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y107": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00423D80", + "frames": 28, + "offset": 12, + "words": 2 + } + }, "grid_x": 306, "grid_y": 304, "pin_functions": {}, @@ -858070,7 +859106,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y108": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00423D80", + "frames": 28, + "offset": 14, + "words": 2 + } + }, "grid_x": 306, "grid_y": 303, "pin_functions": {}, @@ -858079,7 +859122,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y109": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00423D80", + "frames": 28, + "offset": 16, + "words": 2 + } + }, "grid_x": 306, "grid_y": 302, "pin_functions": {}, @@ -858088,7 +859138,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y110": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00423D80", + "frames": 28, + "offset": 18, + "words": 2 + } + }, "grid_x": 306, "grid_y": 301, "pin_functions": {}, @@ -858097,7 +859154,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y111": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00423D80", + "frames": 28, + "offset": 20, + "words": 2 + } + }, "grid_x": 306, "grid_y": 300, "pin_functions": {}, @@ -858106,7 +859170,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y112": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00423D80", + "frames": 28, + "offset": 22, + "words": 2 + } + }, "grid_x": 306, "grid_y": 299, "pin_functions": {}, @@ -858115,7 +859186,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y113": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00423D80", + "frames": 28, + "offset": 24, + "words": 2 + } + }, "grid_x": 306, "grid_y": 298, "pin_functions": {}, @@ -858124,7 +859202,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y114": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00423D80", + "frames": 28, + "offset": 26, + "words": 2 + } + }, "grid_x": 306, "grid_y": 297, "pin_functions": {}, @@ -858133,7 +859218,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y115": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00423D80", + "frames": 28, + "offset": 28, + "words": 2 + } + }, "grid_x": 306, "grid_y": 296, "pin_functions": {}, @@ -858142,7 +859234,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y116": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00423D80", + "frames": 28, + "offset": 30, + "words": 2 + } + }, "grid_x": 306, "grid_y": 295, "pin_functions": {}, @@ -858151,7 +859250,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y117": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00423D80", + "frames": 28, + "offset": 32, + "words": 2 + } + }, "grid_x": 306, "grid_y": 294, "pin_functions": {}, @@ -858160,7 +859266,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y118": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00423D80", + "frames": 28, + "offset": 34, + "words": 2 + } + }, "grid_x": 306, "grid_y": 293, "pin_functions": {}, @@ -858169,7 +859282,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y119": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00423D80", + "frames": 28, + "offset": 36, + "words": 2 + } + }, "grid_x": 306, "grid_y": 292, "pin_functions": {}, @@ -858178,7 +859298,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y120": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00423D80", + "frames": 28, + "offset": 38, + "words": 2 + } + }, "grid_x": 306, "grid_y": 291, "pin_functions": {}, @@ -858187,7 +859314,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y121": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00423D80", + "frames": 28, + "offset": 40, + "words": 2 + } + }, "grid_x": 306, "grid_y": 290, "pin_functions": {}, @@ -858196,7 +859330,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y122": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00423D80", + "frames": 28, + "offset": 42, + "words": 2 + } + }, "grid_x": 306, "grid_y": 289, "pin_functions": {}, @@ -858205,7 +859346,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y123": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00423D80", + "frames": 28, + "offset": 44, + "words": 2 + } + }, "grid_x": 306, "grid_y": 288, "pin_functions": {}, @@ -858214,7 +859362,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y124": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00423D80", + "frames": 28, + "offset": 46, + "words": 2 + } + }, "grid_x": 306, "grid_y": 287, "pin_functions": {}, @@ -858223,7 +859378,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y125": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00423D80", + "frames": 28, + "offset": 49, + "words": 2 + } + }, "grid_x": 306, "grid_y": 285, "pin_functions": {}, @@ -858232,7 +859394,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y126": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00423D80", + "frames": 28, + "offset": 51, + "words": 2 + } + }, "grid_x": 306, "grid_y": 284, "pin_functions": {}, @@ -858241,7 +859410,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y127": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00423D80", + "frames": 28, + "offset": 53, + "words": 2 + } + }, "grid_x": 306, "grid_y": 283, "pin_functions": {}, @@ -858250,7 +859426,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y128": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00423D80", + "frames": 28, + "offset": 55, + "words": 2 + } + }, "grid_x": 306, "grid_y": 282, "pin_functions": {}, @@ -858259,7 +859442,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y129": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00423D80", + "frames": 28, + "offset": 57, + "words": 2 + } + }, "grid_x": 306, "grid_y": 281, "pin_functions": {}, @@ -858268,7 +859458,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y130": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00423D80", + "frames": 28, + "offset": 59, + "words": 2 + } + }, "grid_x": 306, "grid_y": 280, "pin_functions": {}, @@ -858277,7 +859474,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y131": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00423D80", + "frames": 28, + "offset": 61, + "words": 2 + } + }, "grid_x": 306, "grid_y": 279, "pin_functions": {}, @@ -858286,7 +859490,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y132": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00423D80", + "frames": 28, + "offset": 63, + "words": 2 + } + }, "grid_x": 306, "grid_y": 278, "pin_functions": {}, @@ -858295,7 +859506,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y133": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00423D80", + "frames": 28, + "offset": 65, + "words": 2 + } + }, "grid_x": 306, "grid_y": 277, "pin_functions": {}, @@ -858304,7 +859522,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y134": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00423D80", + "frames": 28, + "offset": 67, + "words": 2 + } + }, "grid_x": 306, "grid_y": 276, "pin_functions": {}, @@ -858313,7 +859538,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y135": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00423D80", + "frames": 28, + "offset": 69, + "words": 2 + } + }, "grid_x": 306, "grid_y": 275, "pin_functions": {}, @@ -858322,7 +859554,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y136": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00423D80", + "frames": 28, + "offset": 71, + "words": 2 + } + }, "grid_x": 306, "grid_y": 274, "pin_functions": {}, @@ -858331,7 +859570,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y137": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00423D80", + "frames": 28, + "offset": 73, + "words": 2 + } + }, "grid_x": 306, "grid_y": 273, "pin_functions": {}, @@ -858340,7 +859586,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y138": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00423D80", + "frames": 28, + "offset": 75, + "words": 2 + } + }, "grid_x": 306, "grid_y": 272, "pin_functions": {}, @@ -858349,7 +859602,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y139": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00423D80", + "frames": 28, + "offset": 77, + "words": 2 + } + }, "grid_x": 306, "grid_y": 271, "pin_functions": {}, @@ -858358,7 +859618,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y140": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00423D80", + "frames": 28, + "offset": 79, + "words": 2 + } + }, "grid_x": 306, "grid_y": 270, "pin_functions": {}, @@ -858367,7 +859634,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y141": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00423D80", + "frames": 28, + "offset": 81, + "words": 2 + } + }, "grid_x": 306, "grid_y": 269, "pin_functions": {}, @@ -858376,7 +859650,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y142": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00423D80", + "frames": 28, + "offset": 83, + "words": 2 + } + }, "grid_x": 306, "grid_y": 268, "pin_functions": {}, @@ -858385,7 +859666,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y143": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00423D80", + "frames": 28, + "offset": 85, + "words": 2 + } + }, "grid_x": 306, "grid_y": 267, "pin_functions": {}, @@ -858394,7 +859682,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y144": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00423D80", + "frames": 28, + "offset": 87, + "words": 2 + } + }, "grid_x": 306, "grid_y": 266, "pin_functions": {}, @@ -858403,7 +859698,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y145": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00423D80", + "frames": 28, + "offset": 89, + "words": 2 + } + }, "grid_x": 306, "grid_y": 265, "pin_functions": {}, @@ -858412,7 +859714,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y146": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00423D80", + "frames": 28, + "offset": 91, + "words": 2 + } + }, "grid_x": 306, "grid_y": 264, "pin_functions": {}, @@ -858421,7 +859730,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y147": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00423D80", + "frames": 28, + "offset": 93, + "words": 2 + } + }, "grid_x": 306, "grid_y": 263, "pin_functions": {}, @@ -858430,7 +859746,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y148": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00423D80", + "frames": 28, + "offset": 95, + "words": 2 + } + }, "grid_x": 306, "grid_y": 262, "pin_functions": {}, @@ -858439,7 +859762,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y149": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00423D80", + "frames": 28, + "offset": 97, + "words": 2 + } + }, "grid_x": 306, "grid_y": 261, "pin_functions": {}, @@ -858448,7 +859778,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y150": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00403D80", + "frames": 28, + "offset": -2, + "words": 2 + } + }, "grid_x": 306, "grid_y": 259, "pin_functions": {}, @@ -858457,7 +859794,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y151": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00403D80", + "frames": 28, + "offset": 0, + "words": 2 + } + }, "grid_x": 306, "grid_y": 258, "pin_functions": {}, @@ -858466,7 +859810,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y152": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00403D80", + "frames": 28, + "offset": 2, + "words": 2 + } + }, "grid_x": 306, "grid_y": 257, "pin_functions": {}, @@ -858475,7 +859826,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y153": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00403D80", + "frames": 28, + "offset": 4, + "words": 2 + } + }, "grid_x": 306, "grid_y": 256, "pin_functions": {}, @@ -858484,7 +859842,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y154": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00403D80", + "frames": 28, + "offset": 6, + "words": 2 + } + }, "grid_x": 306, "grid_y": 255, "pin_functions": {}, @@ -858493,7 +859858,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y155": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00403D80", + "frames": 28, + "offset": 8, + "words": 2 + } + }, "grid_x": 306, "grid_y": 254, "pin_functions": {}, @@ -858502,7 +859874,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y156": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00403D80", + "frames": 28, + "offset": 10, + "words": 2 + } + }, "grid_x": 306, "grid_y": 253, "pin_functions": {}, @@ -858511,7 +859890,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y157": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00403D80", + "frames": 28, + "offset": 12, + "words": 2 + } + }, "grid_x": 306, "grid_y": 252, "pin_functions": {}, @@ -858520,7 +859906,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y158": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00403D80", + "frames": 28, + "offset": 14, + "words": 2 + } + }, "grid_x": 306, "grid_y": 251, "pin_functions": {}, @@ -858529,7 +859922,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y159": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00403D80", + "frames": 28, + "offset": 16, + "words": 2 + } + }, "grid_x": 306, "grid_y": 250, "pin_functions": {}, @@ -858538,7 +859938,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y160": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00403D80", + "frames": 28, + "offset": 18, + "words": 2 + } + }, "grid_x": 306, "grid_y": 249, "pin_functions": {}, @@ -858547,7 +859954,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y161": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00403D80", + "frames": 28, + "offset": 20, + "words": 2 + } + }, "grid_x": 306, "grid_y": 248, "pin_functions": {}, @@ -858556,7 +859970,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y162": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00403D80", + "frames": 28, + "offset": 22, + "words": 2 + } + }, "grid_x": 306, "grid_y": 247, "pin_functions": {}, @@ -858565,7 +859986,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y163": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00403D80", + "frames": 28, + "offset": 24, + "words": 2 + } + }, "grid_x": 306, "grid_y": 246, "pin_functions": {}, @@ -858574,7 +860002,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y164": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00403D80", + "frames": 28, + "offset": 26, + "words": 2 + } + }, "grid_x": 306, "grid_y": 245, "pin_functions": {}, @@ -858583,7 +860018,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y165": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00403D80", + "frames": 28, + "offset": 28, + "words": 2 + } + }, "grid_x": 306, "grid_y": 244, "pin_functions": {}, @@ -858592,7 +860034,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y166": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00403D80", + "frames": 28, + "offset": 30, + "words": 2 + } + }, "grid_x": 306, "grid_y": 243, "pin_functions": {}, @@ -858601,7 +860050,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y167": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00403D80", + "frames": 28, + "offset": 32, + "words": 2 + } + }, "grid_x": 306, "grid_y": 242, "pin_functions": {}, @@ -858610,7 +860066,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y168": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00403D80", + "frames": 28, + "offset": 34, + "words": 2 + } + }, "grid_x": 306, "grid_y": 241, "pin_functions": {}, @@ -858619,7 +860082,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y169": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00403D80", + "frames": 28, + "offset": 36, + "words": 2 + } + }, "grid_x": 306, "grid_y": 240, "pin_functions": {}, @@ -858628,7 +860098,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y170": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00403D80", + "frames": 28, + "offset": 38, + "words": 2 + } + }, "grid_x": 306, "grid_y": 239, "pin_functions": {}, @@ -858637,7 +860114,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y171": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00403D80", + "frames": 28, + "offset": 40, + "words": 2 + } + }, "grid_x": 306, "grid_y": 238, "pin_functions": {}, @@ -858646,7 +860130,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y172": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00403D80", + "frames": 28, + "offset": 42, + "words": 2 + } + }, "grid_x": 306, "grid_y": 237, "pin_functions": {}, @@ -858655,7 +860146,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y173": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00403D80", + "frames": 28, + "offset": 44, + "words": 2 + } + }, "grid_x": 306, "grid_y": 236, "pin_functions": {}, @@ -858664,7 +860162,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y174": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00403D80", + "frames": 28, + "offset": 46, + "words": 2 + } + }, "grid_x": 306, "grid_y": 235, "pin_functions": {}, @@ -858673,7 +860178,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y175": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00403D80", + "frames": 28, + "offset": 49, + "words": 2 + } + }, "grid_x": 306, "grid_y": 233, "pin_functions": {}, @@ -858682,7 +860194,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y176": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00403D80", + "frames": 28, + "offset": 51, + "words": 2 + } + }, "grid_x": 306, "grid_y": 232, "pin_functions": {}, @@ -858691,7 +860210,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y177": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00403D80", + "frames": 28, + "offset": 53, + "words": 2 + } + }, "grid_x": 306, "grid_y": 231, "pin_functions": {}, @@ -858700,7 +860226,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y178": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00403D80", + "frames": 28, + "offset": 55, + "words": 2 + } + }, "grid_x": 306, "grid_y": 230, "pin_functions": {}, @@ -858709,7 +860242,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y179": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00403D80", + "frames": 28, + "offset": 57, + "words": 2 + } + }, "grid_x": 306, "grid_y": 229, "pin_functions": {}, @@ -858718,7 +860258,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y180": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00403D80", + "frames": 28, + "offset": 59, + "words": 2 + } + }, "grid_x": 306, "grid_y": 228, "pin_functions": {}, @@ -858727,7 +860274,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y181": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00403D80", + "frames": 28, + "offset": 61, + "words": 2 + } + }, "grid_x": 306, "grid_y": 227, "pin_functions": {}, @@ -858736,7 +860290,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y182": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00403D80", + "frames": 28, + "offset": 63, + "words": 2 + } + }, "grid_x": 306, "grid_y": 226, "pin_functions": {}, @@ -858745,7 +860306,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y183": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00403D80", + "frames": 28, + "offset": 65, + "words": 2 + } + }, "grid_x": 306, "grid_y": 225, "pin_functions": {}, @@ -858754,7 +860322,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y184": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00403D80", + "frames": 28, + "offset": 67, + "words": 2 + } + }, "grid_x": 306, "grid_y": 224, "pin_functions": {}, @@ -858763,7 +860338,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y185": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00403D80", + "frames": 28, + "offset": 69, + "words": 2 + } + }, "grid_x": 306, "grid_y": 223, "pin_functions": {}, @@ -858772,7 +860354,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y186": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00403D80", + "frames": 28, + "offset": 71, + "words": 2 + } + }, "grid_x": 306, "grid_y": 222, "pin_functions": {}, @@ -858781,7 +860370,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y187": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00403D80", + "frames": 28, + "offset": 73, + "words": 2 + } + }, "grid_x": 306, "grid_y": 221, "pin_functions": {}, @@ -858790,7 +860386,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y188": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00403D80", + "frames": 28, + "offset": 75, + "words": 2 + } + }, "grid_x": 306, "grid_y": 220, "pin_functions": {}, @@ -858799,7 +860402,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y189": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00403D80", + "frames": 28, + "offset": 77, + "words": 2 + } + }, "grid_x": 306, "grid_y": 219, "pin_functions": {}, @@ -858808,7 +860418,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y190": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00403D80", + "frames": 28, + "offset": 79, + "words": 2 + } + }, "grid_x": 306, "grid_y": 218, "pin_functions": {}, @@ -858817,7 +860434,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y191": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00403D80", + "frames": 28, + "offset": 81, + "words": 2 + } + }, "grid_x": 306, "grid_y": 217, "pin_functions": {}, @@ -858826,7 +860450,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y192": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00403D80", + "frames": 28, + "offset": 83, + "words": 2 + } + }, "grid_x": 306, "grid_y": 216, "pin_functions": {}, @@ -858835,7 +860466,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y193": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00403D80", + "frames": 28, + "offset": 85, + "words": 2 + } + }, "grid_x": 306, "grid_y": 215, "pin_functions": {}, @@ -858844,7 +860482,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y194": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00403D80", + "frames": 28, + "offset": 87, + "words": 2 + } + }, "grid_x": 306, "grid_y": 214, "pin_functions": {}, @@ -858853,7 +860498,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y195": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00403D80", + "frames": 28, + "offset": 89, + "words": 2 + } + }, "grid_x": 306, "grid_y": 213, "pin_functions": {}, @@ -858862,7 +860514,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y196": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00403D80", + "frames": 28, + "offset": 91, + "words": 2 + } + }, "grid_x": 306, "grid_y": 212, "pin_functions": {}, @@ -858871,7 +860530,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y197": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00403D80", + "frames": 28, + "offset": 93, + "words": 2 + } + }, "grid_x": 306, "grid_y": 211, "pin_functions": {}, @@ -858880,7 +860546,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y198": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00403D80", + "frames": 28, + "offset": 95, + "words": 2 + } + }, "grid_x": 306, "grid_y": 210, "pin_functions": {}, @@ -858889,7 +860562,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y199": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00403D80", + "frames": 28, + "offset": 97, + "words": 2 + } + }, "grid_x": 306, "grid_y": 209, "pin_functions": {}, @@ -858898,7 +860578,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y200": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00003D80", + "frames": 28, + "offset": -2, + "words": 2 + } + }, "grid_x": 306, "grid_y": 207, "pin_functions": {}, @@ -858907,7 +860594,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y201": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00003D80", + "frames": 28, + "offset": 0, + "words": 2 + } + }, "grid_x": 306, "grid_y": 206, "pin_functions": {}, @@ -858916,7 +860610,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y202": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00003D80", + "frames": 28, + "offset": 2, + "words": 2 + } + }, "grid_x": 306, "grid_y": 205, "pin_functions": {}, @@ -858925,7 +860626,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y203": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00003D80", + "frames": 28, + "offset": 4, + "words": 2 + } + }, "grid_x": 306, "grid_y": 204, "pin_functions": {}, @@ -858934,7 +860642,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y204": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00003D80", + "frames": 28, + "offset": 6, + "words": 2 + } + }, "grid_x": 306, "grid_y": 203, "pin_functions": {}, @@ -858943,7 +860658,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y205": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00003D80", + "frames": 28, + "offset": 8, + "words": 2 + } + }, "grid_x": 306, "grid_y": 202, "pin_functions": {}, @@ -858952,7 +860674,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y206": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00003D80", + "frames": 28, + "offset": 10, + "words": 2 + } + }, "grid_x": 306, "grid_y": 201, "pin_functions": {}, @@ -858961,7 +860690,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y207": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00003D80", + "frames": 28, + "offset": 12, + "words": 2 + } + }, "grid_x": 306, "grid_y": 200, "pin_functions": {}, @@ -858970,7 +860706,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y208": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00003D80", + "frames": 28, + "offset": 14, + "words": 2 + } + }, "grid_x": 306, "grid_y": 199, "pin_functions": {}, @@ -858979,7 +860722,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y209": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00003D80", + "frames": 28, + "offset": 16, + "words": 2 + } + }, "grid_x": 306, "grid_y": 198, "pin_functions": {}, @@ -858988,7 +860738,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y210": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00003D80", + "frames": 28, + "offset": 18, + "words": 2 + } + }, "grid_x": 306, "grid_y": 197, "pin_functions": {}, @@ -858997,7 +860754,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y211": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00003D80", + "frames": 28, + "offset": 20, + "words": 2 + } + }, "grid_x": 306, "grid_y": 196, "pin_functions": {}, @@ -859006,7 +860770,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y212": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00003D80", + "frames": 28, + "offset": 22, + "words": 2 + } + }, "grid_x": 306, "grid_y": 195, "pin_functions": {}, @@ -859015,7 +860786,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y213": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00003D80", + "frames": 28, + "offset": 24, + "words": 2 + } + }, "grid_x": 306, "grid_y": 194, "pin_functions": {}, @@ -859024,7 +860802,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y214": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00003D80", + "frames": 28, + "offset": 26, + "words": 2 + } + }, "grid_x": 306, "grid_y": 193, "pin_functions": {}, @@ -859033,7 +860818,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y215": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00003D80", + "frames": 28, + "offset": 28, + "words": 2 + } + }, "grid_x": 306, "grid_y": 192, "pin_functions": {}, @@ -859042,7 +860834,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y216": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00003D80", + "frames": 28, + "offset": 30, + "words": 2 + } + }, "grid_x": 306, "grid_y": 191, "pin_functions": {}, @@ -859051,7 +860850,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y217": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00003D80", + "frames": 28, + "offset": 32, + "words": 2 + } + }, "grid_x": 306, "grid_y": 190, "pin_functions": {}, @@ -859060,7 +860866,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y218": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00003D80", + "frames": 28, + "offset": 34, + "words": 2 + } + }, "grid_x": 306, "grid_y": 189, "pin_functions": {}, @@ -859069,7 +860882,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y219": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00003D80", + "frames": 28, + "offset": 36, + "words": 2 + } + }, "grid_x": 306, "grid_y": 188, "pin_functions": {}, @@ -859078,7 +860898,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y220": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00003D80", + "frames": 28, + "offset": 38, + "words": 2 + } + }, "grid_x": 306, "grid_y": 187, "pin_functions": {}, @@ -859087,7 +860914,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y221": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00003D80", + "frames": 28, + "offset": 40, + "words": 2 + } + }, "grid_x": 306, "grid_y": 186, "pin_functions": {}, @@ -859096,7 +860930,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y222": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00003D80", + "frames": 28, + "offset": 42, + "words": 2 + } + }, "grid_x": 306, "grid_y": 185, "pin_functions": {}, @@ -859105,7 +860946,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y223": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00003D80", + "frames": 28, + "offset": 44, + "words": 2 + } + }, "grid_x": 306, "grid_y": 184, "pin_functions": {}, @@ -859114,7 +860962,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y224": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00003D80", + "frames": 28, + "offset": 46, + "words": 2 + } + }, "grid_x": 306, "grid_y": 183, "pin_functions": {}, @@ -859123,7 +860978,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y225": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00003D80", + "frames": 28, + "offset": 49, + "words": 2 + } + }, "grid_x": 306, "grid_y": 181, "pin_functions": {}, @@ -859132,7 +860994,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y226": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00003D80", + "frames": 28, + "offset": 51, + "words": 2 + } + }, "grid_x": 306, "grid_y": 180, "pin_functions": {}, @@ -859141,7 +861010,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y227": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00003D80", + "frames": 28, + "offset": 53, + "words": 2 + } + }, "grid_x": 306, "grid_y": 179, "pin_functions": {}, @@ -859150,7 +861026,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y228": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00003D80", + "frames": 28, + "offset": 55, + "words": 2 + } + }, "grid_x": 306, "grid_y": 178, "pin_functions": {}, @@ -859159,7 +861042,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y229": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00003D80", + "frames": 28, + "offset": 57, + "words": 2 + } + }, "grid_x": 306, "grid_y": 177, "pin_functions": {}, @@ -859168,7 +861058,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y230": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00003D80", + "frames": 28, + "offset": 59, + "words": 2 + } + }, "grid_x": 306, "grid_y": 176, "pin_functions": {}, @@ -859177,7 +861074,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y231": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00003D80", + "frames": 28, + "offset": 61, + "words": 2 + } + }, "grid_x": 306, "grid_y": 175, "pin_functions": {}, @@ -859186,7 +861090,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y232": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00003D80", + "frames": 28, + "offset": 63, + "words": 2 + } + }, "grid_x": 306, "grid_y": 174, "pin_functions": {}, @@ -859195,7 +861106,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y233": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00003D80", + "frames": 28, + "offset": 65, + "words": 2 + } + }, "grid_x": 306, "grid_y": 173, "pin_functions": {}, @@ -859204,7 +861122,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y234": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00003D80", + "frames": 28, + "offset": 67, + "words": 2 + } + }, "grid_x": 306, "grid_y": 172, "pin_functions": {}, @@ -859213,7 +861138,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y235": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00003D80", + "frames": 28, + "offset": 69, + "words": 2 + } + }, "grid_x": 306, "grid_y": 171, "pin_functions": {}, @@ -859222,7 +861154,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y236": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00003D80", + "frames": 28, + "offset": 71, + "words": 2 + } + }, "grid_x": 306, "grid_y": 170, "pin_functions": {}, @@ -859231,7 +861170,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y237": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00003D80", + "frames": 28, + "offset": 73, + "words": 2 + } + }, "grid_x": 306, "grid_y": 169, "pin_functions": {}, @@ -859240,7 +861186,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y238": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00003D80", + "frames": 28, + "offset": 75, + "words": 2 + } + }, "grid_x": 306, "grid_y": 168, "pin_functions": {}, @@ -859249,7 +861202,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y239": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00003D80", + "frames": 28, + "offset": 77, + "words": 2 + } + }, "grid_x": 306, "grid_y": 167, "pin_functions": {}, @@ -859258,7 +861218,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y240": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00003D80", + "frames": 28, + "offset": 79, + "words": 2 + } + }, "grid_x": 306, "grid_y": 166, "pin_functions": {}, @@ -859267,7 +861234,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y241": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00003D80", + "frames": 28, + "offset": 81, + "words": 2 + } + }, "grid_x": 306, "grid_y": 165, "pin_functions": {}, @@ -859276,7 +861250,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y242": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00003D80", + "frames": 28, + "offset": 83, + "words": 2 + } + }, "grid_x": 306, "grid_y": 164, "pin_functions": {}, @@ -859285,7 +861266,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y243": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00003D80", + "frames": 28, + "offset": 85, + "words": 2 + } + }, "grid_x": 306, "grid_y": 163, "pin_functions": {}, @@ -859294,7 +861282,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y244": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00003D80", + "frames": 28, + "offset": 87, + "words": 2 + } + }, "grid_x": 306, "grid_y": 162, "pin_functions": {}, @@ -859303,7 +861298,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y245": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00003D80", + "frames": 28, + "offset": 89, + "words": 2 + } + }, "grid_x": 306, "grid_y": 161, "pin_functions": {}, @@ -859312,7 +861314,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y246": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00003D80", + "frames": 28, + "offset": 91, + "words": 2 + } + }, "grid_x": 306, "grid_y": 160, "pin_functions": {}, @@ -859321,7 +861330,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y247": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00003D80", + "frames": 28, + "offset": 93, + "words": 2 + } + }, "grid_x": 306, "grid_y": 159, "pin_functions": {}, @@ -859330,7 +861346,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y248": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00003D80", + "frames": 28, + "offset": 95, + "words": 2 + } + }, "grid_x": 306, "grid_y": 158, "pin_functions": {}, @@ -859339,7 +861362,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y249": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00003D80", + "frames": 28, + "offset": 97, + "words": 2 + } + }, "grid_x": 306, "grid_y": 157, "pin_functions": {}, @@ -859348,7 +861378,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y250": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00023D80", + "frames": 28, + "offset": -2, + "words": 2 + } + }, "grid_x": 306, "grid_y": 155, "pin_functions": {}, @@ -859357,7 +861394,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y251": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00023D80", + "frames": 28, + "offset": 0, + "words": 2 + } + }, "grid_x": 306, "grid_y": 154, "pin_functions": {}, @@ -859366,7 +861410,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y252": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00023D80", + "frames": 28, + "offset": 2, + "words": 2 + } + }, "grid_x": 306, "grid_y": 153, "pin_functions": {}, @@ -859375,7 +861426,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y253": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00023D80", + "frames": 28, + "offset": 4, + "words": 2 + } + }, "grid_x": 306, "grid_y": 152, "pin_functions": {}, @@ -859384,7 +861442,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y254": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00023D80", + "frames": 28, + "offset": 6, + "words": 2 + } + }, "grid_x": 306, "grid_y": 151, "pin_functions": {}, @@ -859393,7 +861458,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y255": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00023D80", + "frames": 28, + "offset": 8, + "words": 2 + } + }, "grid_x": 306, "grid_y": 150, "pin_functions": {}, @@ -859402,7 +861474,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y256": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00023D80", + "frames": 28, + "offset": 10, + "words": 2 + } + }, "grid_x": 306, "grid_y": 149, "pin_functions": {}, @@ -859411,7 +861490,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y257": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00023D80", + "frames": 28, + "offset": 12, + "words": 2 + } + }, "grid_x": 306, "grid_y": 148, "pin_functions": {}, @@ -859420,7 +861506,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y258": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00023D80", + "frames": 28, + "offset": 14, + "words": 2 + } + }, "grid_x": 306, "grid_y": 147, "pin_functions": {}, @@ -859429,7 +861522,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y259": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00023D80", + "frames": 28, + "offset": 16, + "words": 2 + } + }, "grid_x": 306, "grid_y": 146, "pin_functions": {}, @@ -859438,7 +861538,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y260": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00023D80", + "frames": 28, + "offset": 18, + "words": 2 + } + }, "grid_x": 306, "grid_y": 145, "pin_functions": {}, @@ -859447,7 +861554,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y261": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00023D80", + "frames": 28, + "offset": 20, + "words": 2 + } + }, "grid_x": 306, "grid_y": 144, "pin_functions": {}, @@ -859456,7 +861570,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y262": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00023D80", + "frames": 28, + "offset": 22, + "words": 2 + } + }, "grid_x": 306, "grid_y": 143, "pin_functions": {}, @@ -859465,7 +861586,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y263": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00023D80", + "frames": 28, + "offset": 24, + "words": 2 + } + }, "grid_x": 306, "grid_y": 142, "pin_functions": {}, @@ -859474,7 +861602,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y264": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00023D80", + "frames": 28, + "offset": 26, + "words": 2 + } + }, "grid_x": 306, "grid_y": 141, "pin_functions": {}, @@ -859483,7 +861618,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y265": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00023D80", + "frames": 28, + "offset": 28, + "words": 2 + } + }, "grid_x": 306, "grid_y": 140, "pin_functions": {}, @@ -859492,7 +861634,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y266": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00023D80", + "frames": 28, + "offset": 30, + "words": 2 + } + }, "grid_x": 306, "grid_y": 139, "pin_functions": {}, @@ -859501,7 +861650,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y267": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00023D80", + "frames": 28, + "offset": 32, + "words": 2 + } + }, "grid_x": 306, "grid_y": 138, "pin_functions": {}, @@ -859510,7 +861666,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y268": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00023D80", + "frames": 28, + "offset": 34, + "words": 2 + } + }, "grid_x": 306, "grid_y": 137, "pin_functions": {}, @@ -859519,7 +861682,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y269": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00023D80", + "frames": 28, + "offset": 36, + "words": 2 + } + }, "grid_x": 306, "grid_y": 136, "pin_functions": {}, @@ -859528,7 +861698,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y270": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00023D80", + "frames": 28, + "offset": 38, + "words": 2 + } + }, "grid_x": 306, "grid_y": 135, "pin_functions": {}, @@ -859537,7 +861714,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y271": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00023D80", + "frames": 28, + "offset": 40, + "words": 2 + } + }, "grid_x": 306, "grid_y": 134, "pin_functions": {}, @@ -859546,7 +861730,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y272": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00023D80", + "frames": 28, + "offset": 42, + "words": 2 + } + }, "grid_x": 306, "grid_y": 133, "pin_functions": {}, @@ -859555,7 +861746,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y273": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00023D80", + "frames": 28, + "offset": 44, + "words": 2 + } + }, "grid_x": 306, "grid_y": 132, "pin_functions": {}, @@ -859564,7 +861762,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y274": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00023D80", + "frames": 28, + "offset": 46, + "words": 2 + } + }, "grid_x": 306, "grid_y": 131, "pin_functions": {}, @@ -859573,7 +861778,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y275": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00023D80", + "frames": 28, + "offset": 49, + "words": 2 + } + }, "grid_x": 306, "grid_y": 129, "pin_functions": {}, @@ -859582,7 +861794,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y276": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00023D80", + "frames": 28, + "offset": 51, + "words": 2 + } + }, "grid_x": 306, "grid_y": 128, "pin_functions": {}, @@ -859591,7 +861810,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y277": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00023D80", + "frames": 28, + "offset": 53, + "words": 2 + } + }, "grid_x": 306, "grid_y": 127, "pin_functions": {}, @@ -859600,7 +861826,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y278": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00023D80", + "frames": 28, + "offset": 55, + "words": 2 + } + }, "grid_x": 306, "grid_y": 126, "pin_functions": {}, @@ -859609,7 +861842,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y279": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00023D80", + "frames": 28, + "offset": 57, + "words": 2 + } + }, "grid_x": 306, "grid_y": 125, "pin_functions": {}, @@ -859618,7 +861858,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y280": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00023D80", + "frames": 28, + "offset": 59, + "words": 2 + } + }, "grid_x": 306, "grid_y": 124, "pin_functions": {}, @@ -859627,7 +861874,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y281": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00023D80", + "frames": 28, + "offset": 61, + "words": 2 + } + }, "grid_x": 306, "grid_y": 123, "pin_functions": {}, @@ -859636,7 +861890,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y282": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00023D80", + "frames": 28, + "offset": 63, + "words": 2 + } + }, "grid_x": 306, "grid_y": 122, "pin_functions": {}, @@ -859645,7 +861906,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y283": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00023D80", + "frames": 28, + "offset": 65, + "words": 2 + } + }, "grid_x": 306, "grid_y": 121, "pin_functions": {}, @@ -859654,7 +861922,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y284": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00023D80", + "frames": 28, + "offset": 67, + "words": 2 + } + }, "grid_x": 306, "grid_y": 120, "pin_functions": {}, @@ -859663,7 +861938,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y285": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00023D80", + "frames": 28, + "offset": 69, + "words": 2 + } + }, "grid_x": 306, "grid_y": 119, "pin_functions": {}, @@ -859672,7 +861954,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y286": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00023D80", + "frames": 28, + "offset": 71, + "words": 2 + } + }, "grid_x": 306, "grid_y": 118, "pin_functions": {}, @@ -859681,7 +861970,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y287": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00023D80", + "frames": 28, + "offset": 73, + "words": 2 + } + }, "grid_x": 306, "grid_y": 117, "pin_functions": {}, @@ -859690,7 +861986,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y288": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00023D80", + "frames": 28, + "offset": 75, + "words": 2 + } + }, "grid_x": 306, "grid_y": 116, "pin_functions": {}, @@ -859699,7 +862002,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y289": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00023D80", + "frames": 28, + "offset": 77, + "words": 2 + } + }, "grid_x": 306, "grid_y": 115, "pin_functions": {}, @@ -859708,7 +862018,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y290": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00023D80", + "frames": 28, + "offset": 79, + "words": 2 + } + }, "grid_x": 306, "grid_y": 114, "pin_functions": {}, @@ -859717,7 +862034,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y291": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00023D80", + "frames": 28, + "offset": 81, + "words": 2 + } + }, "grid_x": 306, "grid_y": 113, "pin_functions": {}, @@ -859726,7 +862050,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y292": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00023D80", + "frames": 28, + "offset": 83, + "words": 2 + } + }, "grid_x": 306, "grid_y": 112, "pin_functions": {}, @@ -859735,7 +862066,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y293": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00023D80", + "frames": 28, + "offset": 85, + "words": 2 + } + }, "grid_x": 306, "grid_y": 111, "pin_functions": {}, @@ -859744,7 +862082,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y294": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00023D80", + "frames": 28, + "offset": 87, + "words": 2 + } + }, "grid_x": 306, "grid_y": 110, "pin_functions": {}, @@ -859753,7 +862098,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y295": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00023D80", + "frames": 28, + "offset": 89, + "words": 2 + } + }, "grid_x": 306, "grid_y": 109, "pin_functions": {}, @@ -859762,7 +862114,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y296": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00023D80", + "frames": 28, + "offset": 91, + "words": 2 + } + }, "grid_x": 306, "grid_y": 108, "pin_functions": {}, @@ -859771,7 +862130,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y297": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00023D80", + "frames": 28, + "offset": 93, + "words": 2 + } + }, "grid_x": 306, "grid_y": 107, "pin_functions": {}, @@ -859780,7 +862146,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y298": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00023D80", + "frames": 28, + "offset": 95, + "words": 2 + } + }, "grid_x": 306, "grid_y": 106, "pin_functions": {}, @@ -859789,7 +862162,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y299": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00023D80", + "frames": 28, + "offset": 97, + "words": 2 + } + }, "grid_x": 306, "grid_y": 105, "pin_functions": {}, @@ -859798,7 +862178,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y300": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00043D80", + "frames": 28, + "offset": -2, + "words": 2 + } + }, "grid_x": 306, "grid_y": 103, "pin_functions": {}, @@ -859807,7 +862194,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y301": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00043D80", + "frames": 28, + "offset": 0, + "words": 2 + } + }, "grid_x": 306, "grid_y": 102, "pin_functions": {}, @@ -859816,7 +862210,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y302": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00043D80", + "frames": 28, + "offset": 2, + "words": 2 + } + }, "grid_x": 306, "grid_y": 101, "pin_functions": {}, @@ -859825,7 +862226,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y303": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00043D80", + "frames": 28, + "offset": 4, + "words": 2 + } + }, "grid_x": 306, "grid_y": 100, "pin_functions": {}, @@ -859834,7 +862242,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y304": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00043D80", + "frames": 28, + "offset": 6, + "words": 2 + } + }, "grid_x": 306, "grid_y": 99, "pin_functions": {}, @@ -859843,7 +862258,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y305": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00043D80", + "frames": 28, + "offset": 8, + "words": 2 + } + }, "grid_x": 306, "grid_y": 98, "pin_functions": {}, @@ -859852,7 +862274,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y306": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00043D80", + "frames": 28, + "offset": 10, + "words": 2 + } + }, "grid_x": 306, "grid_y": 97, "pin_functions": {}, @@ -859861,7 +862290,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y307": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00043D80", + "frames": 28, + "offset": 12, + "words": 2 + } + }, "grid_x": 306, "grid_y": 96, "pin_functions": {}, @@ -859870,7 +862306,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y308": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00043D80", + "frames": 28, + "offset": 14, + "words": 2 + } + }, "grid_x": 306, "grid_y": 95, "pin_functions": {}, @@ -859879,7 +862322,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y309": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00043D80", + "frames": 28, + "offset": 16, + "words": 2 + } + }, "grid_x": 306, "grid_y": 94, "pin_functions": {}, @@ -859888,7 +862338,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y310": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00043D80", + "frames": 28, + "offset": 18, + "words": 2 + } + }, "grid_x": 306, "grid_y": 93, "pin_functions": {}, @@ -859897,7 +862354,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y311": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00043D80", + "frames": 28, + "offset": 20, + "words": 2 + } + }, "grid_x": 306, "grid_y": 92, "pin_functions": {}, @@ -859906,7 +862370,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y312": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00043D80", + "frames": 28, + "offset": 22, + "words": 2 + } + }, "grid_x": 306, "grid_y": 91, "pin_functions": {}, @@ -859915,7 +862386,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y313": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00043D80", + "frames": 28, + "offset": 24, + "words": 2 + } + }, "grid_x": 306, "grid_y": 90, "pin_functions": {}, @@ -859924,7 +862402,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y314": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00043D80", + "frames": 28, + "offset": 26, + "words": 2 + } + }, "grid_x": 306, "grid_y": 89, "pin_functions": {}, @@ -859933,7 +862418,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y315": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00043D80", + "frames": 28, + "offset": 28, + "words": 2 + } + }, "grid_x": 306, "grid_y": 88, "pin_functions": {}, @@ -859942,7 +862434,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y316": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00043D80", + "frames": 28, + "offset": 30, + "words": 2 + } + }, "grid_x": 306, "grid_y": 87, "pin_functions": {}, @@ -859951,7 +862450,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y317": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00043D80", + "frames": 28, + "offset": 32, + "words": 2 + } + }, "grid_x": 306, "grid_y": 86, "pin_functions": {}, @@ -859960,7 +862466,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y318": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00043D80", + "frames": 28, + "offset": 34, + "words": 2 + } + }, "grid_x": 306, "grid_y": 85, "pin_functions": {}, @@ -859969,7 +862482,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y319": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00043D80", + "frames": 28, + "offset": 36, + "words": 2 + } + }, "grid_x": 306, "grid_y": 84, "pin_functions": {}, @@ -859978,7 +862498,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y320": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00043D80", + "frames": 28, + "offset": 38, + "words": 2 + } + }, "grid_x": 306, "grid_y": 83, "pin_functions": {}, @@ -859987,7 +862514,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y321": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00043D80", + "frames": 28, + "offset": 40, + "words": 2 + } + }, "grid_x": 306, "grid_y": 82, "pin_functions": {}, @@ -859996,7 +862530,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y322": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00043D80", + "frames": 28, + "offset": 42, + "words": 2 + } + }, "grid_x": 306, "grid_y": 81, "pin_functions": {}, @@ -860005,7 +862546,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y323": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00043D80", + "frames": 28, + "offset": 44, + "words": 2 + } + }, "grid_x": 306, "grid_y": 80, "pin_functions": {}, @@ -860014,7 +862562,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y324": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00043D80", + "frames": 28, + "offset": 46, + "words": 2 + } + }, "grid_x": 306, "grid_y": 79, "pin_functions": {}, @@ -860023,7 +862578,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y325": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00043D80", + "frames": 28, + "offset": 49, + "words": 2 + } + }, "grid_x": 306, "grid_y": 77, "pin_functions": {}, @@ -860032,7 +862594,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y326": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00043D80", + "frames": 28, + "offset": 51, + "words": 2 + } + }, "grid_x": 306, "grid_y": 76, "pin_functions": {}, @@ -860041,7 +862610,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y327": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00043D80", + "frames": 28, + "offset": 53, + "words": 2 + } + }, "grid_x": 306, "grid_y": 75, "pin_functions": {}, @@ -860050,7 +862626,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y328": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00043D80", + "frames": 28, + "offset": 55, + "words": 2 + } + }, "grid_x": 306, "grid_y": 74, "pin_functions": {}, @@ -860059,7 +862642,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y329": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00043D80", + "frames": 28, + "offset": 57, + "words": 2 + } + }, "grid_x": 306, "grid_y": 73, "pin_functions": {}, @@ -860068,7 +862658,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y330": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00043D80", + "frames": 28, + "offset": 59, + "words": 2 + } + }, "grid_x": 306, "grid_y": 72, "pin_functions": {}, @@ -860077,7 +862674,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y331": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00043D80", + "frames": 28, + "offset": 61, + "words": 2 + } + }, "grid_x": 306, "grid_y": 71, "pin_functions": {}, @@ -860086,7 +862690,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y332": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00043D80", + "frames": 28, + "offset": 63, + "words": 2 + } + }, "grid_x": 306, "grid_y": 70, "pin_functions": {}, @@ -860095,7 +862706,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y333": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00043D80", + "frames": 28, + "offset": 65, + "words": 2 + } + }, "grid_x": 306, "grid_y": 69, "pin_functions": {}, @@ -860104,7 +862722,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y334": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00043D80", + "frames": 28, + "offset": 67, + "words": 2 + } + }, "grid_x": 306, "grid_y": 68, "pin_functions": {}, @@ -860113,7 +862738,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y335": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00043D80", + "frames": 28, + "offset": 69, + "words": 2 + } + }, "grid_x": 306, "grid_y": 67, "pin_functions": {}, @@ -860122,7 +862754,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y336": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00043D80", + "frames": 28, + "offset": 71, + "words": 2 + } + }, "grid_x": 306, "grid_y": 66, "pin_functions": {}, @@ -860131,7 +862770,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y337": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00043D80", + "frames": 28, + "offset": 73, + "words": 2 + } + }, "grid_x": 306, "grid_y": 65, "pin_functions": {}, @@ -860140,7 +862786,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y338": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00043D80", + "frames": 28, + "offset": 75, + "words": 2 + } + }, "grid_x": 306, "grid_y": 64, "pin_functions": {}, @@ -860149,7 +862802,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y339": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00043D80", + "frames": 28, + "offset": 77, + "words": 2 + } + }, "grid_x": 306, "grid_y": 63, "pin_functions": {}, @@ -860158,7 +862818,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y340": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00043D80", + "frames": 28, + "offset": 79, + "words": 2 + } + }, "grid_x": 306, "grid_y": 62, "pin_functions": {}, @@ -860167,7 +862834,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y341": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00043D80", + "frames": 28, + "offset": 81, + "words": 2 + } + }, "grid_x": 306, "grid_y": 61, "pin_functions": {}, @@ -860176,7 +862850,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y342": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00043D80", + "frames": 28, + "offset": 83, + "words": 2 + } + }, "grid_x": 306, "grid_y": 60, "pin_functions": {}, @@ -860185,7 +862866,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y343": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00043D80", + "frames": 28, + "offset": 85, + "words": 2 + } + }, "grid_x": 306, "grid_y": 59, "pin_functions": {}, @@ -860194,7 +862882,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y344": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00043D80", + "frames": 28, + "offset": 87, + "words": 2 + } + }, "grid_x": 306, "grid_y": 58, "pin_functions": {}, @@ -860203,7 +862898,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y345": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00043D80", + "frames": 28, + "offset": 89, + "words": 2 + } + }, "grid_x": 306, "grid_y": 57, "pin_functions": {}, @@ -860212,7 +862914,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y346": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00043D80", + "frames": 28, + "offset": 91, + "words": 2 + } + }, "grid_x": 306, "grid_y": 56, "pin_functions": {}, @@ -860221,7 +862930,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y347": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00043D80", + "frames": 28, + "offset": 93, + "words": 2 + } + }, "grid_x": 306, "grid_y": 55, "pin_functions": {}, @@ -860230,7 +862946,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y348": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00043D80", + "frames": 28, + "offset": 95, + "words": 2 + } + }, "grid_x": 306, "grid_y": 54, "pin_functions": {}, @@ -860239,7 +862962,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y349": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00043D80", + "frames": 28, + "offset": 97, + "words": 2 + } + }, "grid_x": 306, "grid_y": 53, "pin_functions": {}, @@ -860248,7 +862978,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y350": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00063D80", + "frames": 28, + "offset": -2, + "words": 2 + } + }, "grid_x": 306, "grid_y": 51, "pin_functions": {}, @@ -860257,7 +862994,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y351": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00063D80", + "frames": 28, + "offset": 0, + "words": 2 + } + }, "grid_x": 306, "grid_y": 50, "pin_functions": {}, @@ -860266,7 +863010,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y352": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00063D80", + "frames": 28, + "offset": 2, + "words": 2 + } + }, "grid_x": 306, "grid_y": 49, "pin_functions": {}, @@ -860275,7 +863026,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y353": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00063D80", + "frames": 28, + "offset": 4, + "words": 2 + } + }, "grid_x": 306, "grid_y": 48, "pin_functions": {}, @@ -860284,7 +863042,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y354": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00063D80", + "frames": 28, + "offset": 6, + "words": 2 + } + }, "grid_x": 306, "grid_y": 47, "pin_functions": {}, @@ -860293,7 +863058,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y355": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00063D80", + "frames": 28, + "offset": 8, + "words": 2 + } + }, "grid_x": 306, "grid_y": 46, "pin_functions": {}, @@ -860302,7 +863074,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y356": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00063D80", + "frames": 28, + "offset": 10, + "words": 2 + } + }, "grid_x": 306, "grid_y": 45, "pin_functions": {}, @@ -860311,7 +863090,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y357": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00063D80", + "frames": 28, + "offset": 12, + "words": 2 + } + }, "grid_x": 306, "grid_y": 44, "pin_functions": {}, @@ -860320,7 +863106,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y358": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00063D80", + "frames": 28, + "offset": 14, + "words": 2 + } + }, "grid_x": 306, "grid_y": 43, "pin_functions": {}, @@ -860329,7 +863122,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y359": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00063D80", + "frames": 28, + "offset": 16, + "words": 2 + } + }, "grid_x": 306, "grid_y": 42, "pin_functions": {}, @@ -860338,7 +863138,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y360": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00063D80", + "frames": 28, + "offset": 18, + "words": 2 + } + }, "grid_x": 306, "grid_y": 41, "pin_functions": {}, @@ -860347,7 +863154,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y361": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00063D80", + "frames": 28, + "offset": 20, + "words": 2 + } + }, "grid_x": 306, "grid_y": 40, "pin_functions": {}, @@ -860356,7 +863170,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y362": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00063D80", + "frames": 28, + "offset": 22, + "words": 2 + } + }, "grid_x": 306, "grid_y": 39, "pin_functions": {}, @@ -860365,7 +863186,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y363": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00063D80", + "frames": 28, + "offset": 24, + "words": 2 + } + }, "grid_x": 306, "grid_y": 38, "pin_functions": {}, @@ -860374,7 +863202,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y364": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00063D80", + "frames": 28, + "offset": 26, + "words": 2 + } + }, "grid_x": 306, "grid_y": 37, "pin_functions": {}, @@ -860383,7 +863218,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y365": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00063D80", + "frames": 28, + "offset": 28, + "words": 2 + } + }, "grid_x": 306, "grid_y": 36, "pin_functions": {}, @@ -860392,7 +863234,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y366": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00063D80", + "frames": 28, + "offset": 30, + "words": 2 + } + }, "grid_x": 306, "grid_y": 35, "pin_functions": {}, @@ -860401,7 +863250,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y367": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00063D80", + "frames": 28, + "offset": 32, + "words": 2 + } + }, "grid_x": 306, "grid_y": 34, "pin_functions": {}, @@ -860410,7 +863266,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y368": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00063D80", + "frames": 28, + "offset": 34, + "words": 2 + } + }, "grid_x": 306, "grid_y": 33, "pin_functions": {}, @@ -860419,7 +863282,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y369": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00063D80", + "frames": 28, + "offset": 36, + "words": 2 + } + }, "grid_x": 306, "grid_y": 32, "pin_functions": {}, @@ -860428,7 +863298,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y370": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00063D80", + "frames": 28, + "offset": 38, + "words": 2 + } + }, "grid_x": 306, "grid_y": 31, "pin_functions": {}, @@ -860437,7 +863314,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y371": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00063D80", + "frames": 28, + "offset": 40, + "words": 2 + } + }, "grid_x": 306, "grid_y": 30, "pin_functions": {}, @@ -860446,7 +863330,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y372": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00063D80", + "frames": 28, + "offset": 42, + "words": 2 + } + }, "grid_x": 306, "grid_y": 29, "pin_functions": {}, @@ -860455,7 +863346,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y373": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00063D80", + "frames": 28, + "offset": 44, + "words": 2 + } + }, "grid_x": 306, "grid_y": 28, "pin_functions": {}, @@ -860464,7 +863362,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y374": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00063D80", + "frames": 28, + "offset": 46, + "words": 2 + } + }, "grid_x": 306, "grid_y": 27, "pin_functions": {}, @@ -860473,7 +863378,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y375": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00063D80", + "frames": 28, + "offset": 49, + "words": 2 + } + }, "grid_x": 306, "grid_y": 25, "pin_functions": {}, @@ -860482,7 +863394,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y376": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00063D80", + "frames": 28, + "offset": 51, + "words": 2 + } + }, "grid_x": 306, "grid_y": 24, "pin_functions": {}, @@ -860491,7 +863410,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y377": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00063D80", + "frames": 28, + "offset": 53, + "words": 2 + } + }, "grid_x": 306, "grid_y": 23, "pin_functions": {}, @@ -860500,7 +863426,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y378": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00063D80", + "frames": 28, + "offset": 55, + "words": 2 + } + }, "grid_x": 306, "grid_y": 22, "pin_functions": {}, @@ -860509,7 +863442,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y379": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00063D80", + "frames": 28, + "offset": 57, + "words": 2 + } + }, "grid_x": 306, "grid_y": 21, "pin_functions": {}, @@ -860518,7 +863458,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y380": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00063D80", + "frames": 28, + "offset": 59, + "words": 2 + } + }, "grid_x": 306, "grid_y": 20, "pin_functions": {}, @@ -860527,7 +863474,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y381": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00063D80", + "frames": 28, + "offset": 61, + "words": 2 + } + }, "grid_x": 306, "grid_y": 19, "pin_functions": {}, @@ -860536,7 +863490,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y382": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00063D80", + "frames": 28, + "offset": 63, + "words": 2 + } + }, "grid_x": 306, "grid_y": 18, "pin_functions": {}, @@ -860545,7 +863506,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y383": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00063D80", + "frames": 28, + "offset": 65, + "words": 2 + } + }, "grid_x": 306, "grid_y": 17, "pin_functions": {}, @@ -860554,7 +863522,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y384": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00063D80", + "frames": 28, + "offset": 67, + "words": 2 + } + }, "grid_x": 306, "grid_y": 16, "pin_functions": {}, @@ -860563,7 +863538,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y385": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00063D80", + "frames": 28, + "offset": 69, + "words": 2 + } + }, "grid_x": 306, "grid_y": 15, "pin_functions": {}, @@ -860572,7 +863554,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y386": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00063D80", + "frames": 28, + "offset": 71, + "words": 2 + } + }, "grid_x": 306, "grid_y": 14, "pin_functions": {}, @@ -860581,7 +863570,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y387": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00063D80", + "frames": 28, + "offset": 73, + "words": 2 + } + }, "grid_x": 306, "grid_y": 13, "pin_functions": {}, @@ -860590,7 +863586,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y388": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00063D80", + "frames": 28, + "offset": 75, + "words": 2 + } + }, "grid_x": 306, "grid_y": 12, "pin_functions": {}, @@ -860599,7 +863602,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y389": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00063D80", + "frames": 28, + "offset": 77, + "words": 2 + } + }, "grid_x": 306, "grid_y": 11, "pin_functions": {}, @@ -860608,7 +863618,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y390": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00063D80", + "frames": 28, + "offset": 79, + "words": 2 + } + }, "grid_x": 306, "grid_y": 10, "pin_functions": {}, @@ -860617,7 +863634,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y391": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00063D80", + "frames": 28, + "offset": 81, + "words": 2 + } + }, "grid_x": 306, "grid_y": 9, "pin_functions": {}, @@ -860626,7 +863650,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y392": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00063D80", + "frames": 28, + "offset": 83, + "words": 2 + } + }, "grid_x": 306, "grid_y": 8, "pin_functions": {}, @@ -860635,7 +863666,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y393": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00063D80", + "frames": 28, + "offset": 85, + "words": 2 + } + }, "grid_x": 306, "grid_y": 7, "pin_functions": {}, @@ -860644,7 +863682,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y394": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00063D80", + "frames": 28, + "offset": 87, + "words": 2 + } + }, "grid_x": 306, "grid_y": 6, "pin_functions": {}, @@ -860653,7 +863698,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y395": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00063D80", + "frames": 28, + "offset": 89, + "words": 2 + } + }, "grid_x": 306, "grid_y": 5, "pin_functions": {}, @@ -860662,7 +863714,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y396": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00063D80", + "frames": 28, + "offset": 91, + "words": 2 + } + }, "grid_x": 306, "grid_y": 4, "pin_functions": {}, @@ -860671,7 +863730,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y397": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00063D80", + "frames": 28, + "offset": 93, + "words": 2 + } + }, "grid_x": 306, "grid_y": 3, "pin_functions": {}, @@ -860680,7 +863746,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y398": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00063D80", + "frames": 28, + "offset": 95, + "words": 2 + } + }, "grid_x": 306, "grid_y": 2, "pin_functions": {}, @@ -860689,7 +863762,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X123Y399": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00063D80", + "frames": 28, + "offset": 97, + "words": 2 + } + }, "grid_x": 306, "grid_y": 1, "pin_functions": {}, @@ -2056315,7 +2059395,14 @@ "type": "NULL" }, "PCIE_BOT_X279Y219": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00003780", + "frames": 36, + "offset": 0, + "words": 101 + } + }, "clock_region": "X1Y4", "grid_x": 279, "grid_y": 197, @@ -2056327,7 +2059414,14 @@ "type": "PCIE_BOT" }, "PCIE_INT_INTERFACE_L_X114Y200": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00003900", + "frames": 28, + "offset": 0, + "words": 2 + } + }, "grid_x": 284, "grid_y": 207, "pin_functions": {}, @@ -2056336,7 +2059430,14 @@ "type": "PCIE_INT_INTERFACE_L" }, "PCIE_INT_INTERFACE_L_X114Y201": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00003900", + "frames": 28, + "offset": 2, + "words": 2 + } + }, "grid_x": 284, "grid_y": 206, "pin_functions": {}, @@ -2056345,7 +2059446,14 @@ "type": "PCIE_INT_INTERFACE_L" }, "PCIE_INT_INTERFACE_L_X114Y202": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00003900", + "frames": 28, + "offset": 4, + "words": 2 + } + }, "grid_x": 284, "grid_y": 205, "pin_functions": {}, @@ -2056354,7 +2059462,14 @@ "type": "PCIE_INT_INTERFACE_L" }, "PCIE_INT_INTERFACE_L_X114Y203": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00003900", + "frames": 28, + "offset": 6, + "words": 2 + } + }, "grid_x": 284, "grid_y": 204, "pin_functions": {}, @@ -2056363,7 +2059478,14 @@ "type": "PCIE_INT_INTERFACE_L" }, "PCIE_INT_INTERFACE_L_X114Y204": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00003900", + "frames": 28, + "offset": 8, + "words": 2 + } + }, "grid_x": 284, "grid_y": 203, "pin_functions": {}, @@ -2056372,7 +2059494,14 @@ "type": "PCIE_INT_INTERFACE_L" }, "PCIE_INT_INTERFACE_L_X114Y205": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00003900", + "frames": 28, + "offset": 10, + "words": 2 + } + }, "grid_x": 284, "grid_y": 202, "pin_functions": {}, @@ -2056381,7 +2059510,14 @@ "type": "PCIE_INT_INTERFACE_L" }, "PCIE_INT_INTERFACE_L_X114Y206": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00003900", + "frames": 28, + "offset": 12, + "words": 2 + } + }, "grid_x": 284, "grid_y": 201, "pin_functions": {}, @@ -2056390,7 +2059526,14 @@ "type": "PCIE_INT_INTERFACE_L" }, "PCIE_INT_INTERFACE_L_X114Y207": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00003900", + "frames": 28, + "offset": 14, + "words": 2 + } + }, "grid_x": 284, "grid_y": 200, "pin_functions": {}, @@ -2056399,7 +2059542,14 @@ "type": "PCIE_INT_INTERFACE_L" }, "PCIE_INT_INTERFACE_L_X114Y208": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00003900", + "frames": 28, + "offset": 16, + "words": 2 + } + }, "grid_x": 284, "grid_y": 199, "pin_functions": {}, @@ -2056408,7 +2059558,14 @@ "type": "PCIE_INT_INTERFACE_L" }, "PCIE_INT_INTERFACE_L_X114Y209": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00003900", + "frames": 28, + "offset": 18, + "words": 2 + } + }, "grid_x": 284, "grid_y": 198, "pin_functions": {}, @@ -2056417,7 +2059574,14 @@ "type": "PCIE_INT_INTERFACE_L" }, "PCIE_INT_INTERFACE_L_X114Y210": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00003900", + "frames": 28, + "offset": 20, + "words": 2 + } + }, "grid_x": 284, "grid_y": 197, "pin_functions": {}, @@ -2056426,7 +2059590,14 @@ "type": "PCIE_INT_INTERFACE_L" }, "PCIE_INT_INTERFACE_L_X114Y211": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00003900", + "frames": 28, + "offset": 22, + "words": 2 + } + }, "grid_x": 284, "grid_y": 196, "pin_functions": {}, @@ -2056435,7 +2059606,14 @@ "type": "PCIE_INT_INTERFACE_L" }, "PCIE_INT_INTERFACE_L_X114Y212": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00003900", + "frames": 28, + "offset": 24, + "words": 2 + } + }, "grid_x": 284, "grid_y": 195, "pin_functions": {}, @@ -2056444,7 +2059622,14 @@ "type": "PCIE_INT_INTERFACE_L" }, "PCIE_INT_INTERFACE_L_X114Y213": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00003900", + "frames": 28, + "offset": 26, + "words": 2 + } + }, "grid_x": 284, "grid_y": 194, "pin_functions": {}, @@ -2056453,7 +2059638,14 @@ "type": "PCIE_INT_INTERFACE_L" }, "PCIE_INT_INTERFACE_L_X114Y214": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00003900", + "frames": 28, + "offset": 28, + "words": 2 + } + }, "grid_x": 284, "grid_y": 193, "pin_functions": {}, @@ -2056462,7 +2059654,14 @@ "type": "PCIE_INT_INTERFACE_L" }, "PCIE_INT_INTERFACE_L_X114Y215": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00003900", + "frames": 28, + "offset": 30, + "words": 2 + } + }, "grid_x": 284, "grid_y": 192, "pin_functions": {}, @@ -2056471,7 +2059670,14 @@ "type": "PCIE_INT_INTERFACE_L" }, "PCIE_INT_INTERFACE_L_X114Y216": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00003900", + "frames": 28, + "offset": 32, + "words": 2 + } + }, "grid_x": 284, "grid_y": 191, "pin_functions": {}, @@ -2056480,7 +2059686,14 @@ "type": "PCIE_INT_INTERFACE_L" }, "PCIE_INT_INTERFACE_L_X114Y217": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00003900", + "frames": 28, + "offset": 34, + "words": 2 + } + }, "grid_x": 284, "grid_y": 190, "pin_functions": {}, @@ -2056489,7 +2059702,14 @@ "type": "PCIE_INT_INTERFACE_L" }, "PCIE_INT_INTERFACE_L_X114Y218": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00003900", + "frames": 28, + "offset": 36, + "words": 2 + } + }, "grid_x": 284, "grid_y": 189, "pin_functions": {}, @@ -2056498,7 +2059718,14 @@ "type": "PCIE_INT_INTERFACE_L" }, "PCIE_INT_INTERFACE_L_X114Y219": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00003900", + "frames": 28, + "offset": 38, + "words": 2 + } + }, "grid_x": 284, "grid_y": 188, "pin_functions": {}, @@ -2056507,7 +2059734,14 @@ "type": "PCIE_INT_INTERFACE_L" }, "PCIE_INT_INTERFACE_L_X114Y220": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00003900", + "frames": 28, + "offset": 40, + "words": 2 + } + }, "grid_x": 284, "grid_y": 187, "pin_functions": {}, @@ -2056516,7 +2059750,14 @@ "type": "PCIE_INT_INTERFACE_L" }, "PCIE_INT_INTERFACE_L_X114Y221": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00003900", + "frames": 28, + "offset": 42, + "words": 2 + } + }, "grid_x": 284, "grid_y": 186, "pin_functions": {}, @@ -2056525,7 +2059766,14 @@ "type": "PCIE_INT_INTERFACE_L" }, "PCIE_INT_INTERFACE_L_X114Y222": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00003900", + "frames": 28, + "offset": 44, + "words": 2 + } + }, "grid_x": 284, "grid_y": 185, "pin_functions": {}, @@ -2056534,7 +2059782,14 @@ "type": "PCIE_INT_INTERFACE_L" }, "PCIE_INT_INTERFACE_L_X114Y223": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00003900", + "frames": 28, + "offset": 46, + "words": 2 + } + }, "grid_x": 284, "grid_y": 184, "pin_functions": {}, @@ -2056543,7 +2059798,14 @@ "type": "PCIE_INT_INTERFACE_L" }, "PCIE_INT_INTERFACE_L_X114Y224": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00003900", + "frames": 28, + "offset": 48, + "words": 2 + } + }, "grid_x": 284, "grid_y": 183, "pin_functions": {}, @@ -2056552,7 +2059814,14 @@ "type": "PCIE_INT_INTERFACE_L" }, "PCIE_INT_INTERFACE_R_X111Y200": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00003780", + "frames": 28, + "offset": 0, + "words": 2 + } + }, "grid_x": 278, "grid_y": 207, "pin_functions": {}, @@ -2056561,7 +2059830,14 @@ "type": "PCIE_INT_INTERFACE_R" }, "PCIE_INT_INTERFACE_R_X111Y201": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00003780", + "frames": 28, + "offset": 2, + "words": 2 + } + }, "grid_x": 278, "grid_y": 206, "pin_functions": {}, @@ -2056570,7 +2059846,14 @@ "type": "PCIE_INT_INTERFACE_R" }, "PCIE_INT_INTERFACE_R_X111Y202": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00003780", + "frames": 28, + "offset": 4, + "words": 2 + } + }, "grid_x": 278, "grid_y": 205, "pin_functions": {}, @@ -2056579,7 +2059862,14 @@ "type": "PCIE_INT_INTERFACE_R" }, "PCIE_INT_INTERFACE_R_X111Y203": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00003780", + "frames": 28, + "offset": 6, + "words": 2 + } + }, "grid_x": 278, "grid_y": 204, "pin_functions": {}, @@ -2056588,7 +2059878,14 @@ "type": "PCIE_INT_INTERFACE_R" }, "PCIE_INT_INTERFACE_R_X111Y204": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00003780", + "frames": 28, + "offset": 8, + "words": 2 + } + }, "grid_x": 278, "grid_y": 203, "pin_functions": {}, @@ -2056597,7 +2059894,14 @@ "type": "PCIE_INT_INTERFACE_R" }, "PCIE_INT_INTERFACE_R_X111Y205": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00003780", + "frames": 28, + "offset": 10, + "words": 2 + } + }, "grid_x": 278, "grid_y": 202, "pin_functions": {}, @@ -2056606,7 +2059910,14 @@ "type": "PCIE_INT_INTERFACE_R" }, "PCIE_INT_INTERFACE_R_X111Y206": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00003780", + "frames": 28, + "offset": 12, + "words": 2 + } + }, "grid_x": 278, "grid_y": 201, "pin_functions": {}, @@ -2056615,7 +2059926,14 @@ "type": "PCIE_INT_INTERFACE_R" }, "PCIE_INT_INTERFACE_R_X111Y207": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00003780", + "frames": 28, + "offset": 14, + "words": 2 + } + }, "grid_x": 278, "grid_y": 200, "pin_functions": {}, @@ -2056624,7 +2059942,14 @@ "type": "PCIE_INT_INTERFACE_R" }, "PCIE_INT_INTERFACE_R_X111Y208": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00003780", + "frames": 28, + "offset": 16, + "words": 2 + } + }, "grid_x": 278, "grid_y": 199, "pin_functions": {}, @@ -2056633,7 +2059958,14 @@ "type": "PCIE_INT_INTERFACE_R" }, "PCIE_INT_INTERFACE_R_X111Y209": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00003780", + "frames": 28, + "offset": 18, + "words": 2 + } + }, "grid_x": 278, "grid_y": 198, "pin_functions": {}, @@ -2056642,7 +2059974,14 @@ "type": "PCIE_INT_INTERFACE_R" }, "PCIE_INT_INTERFACE_R_X111Y210": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00003780", + "frames": 28, + "offset": 20, + "words": 2 + } + }, "grid_x": 278, "grid_y": 197, "pin_functions": {}, @@ -2056651,7 +2059990,14 @@ "type": "PCIE_INT_INTERFACE_R" }, "PCIE_INT_INTERFACE_R_X111Y211": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00003780", + "frames": 28, + "offset": 22, + "words": 2 + } + }, "grid_x": 278, "grid_y": 196, "pin_functions": {}, @@ -2056660,7 +2060006,14 @@ "type": "PCIE_INT_INTERFACE_R" }, "PCIE_INT_INTERFACE_R_X111Y212": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00003780", + "frames": 28, + "offset": 24, + "words": 2 + } + }, "grid_x": 278, "grid_y": 195, "pin_functions": {}, @@ -2056669,7 +2060022,14 @@ "type": "PCIE_INT_INTERFACE_R" }, "PCIE_INT_INTERFACE_R_X111Y213": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00003780", + "frames": 28, + "offset": 26, + "words": 2 + } + }, "grid_x": 278, "grid_y": 194, "pin_functions": {}, @@ -2056678,7 +2060038,14 @@ "type": "PCIE_INT_INTERFACE_R" }, "PCIE_INT_INTERFACE_R_X111Y214": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00003780", + "frames": 28, + "offset": 28, + "words": 2 + } + }, "grid_x": 278, "grid_y": 193, "pin_functions": {}, @@ -2056687,7 +2060054,14 @@ "type": "PCIE_INT_INTERFACE_R" }, "PCIE_INT_INTERFACE_R_X111Y215": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00003780", + "frames": 28, + "offset": 30, + "words": 2 + } + }, "grid_x": 278, "grid_y": 192, "pin_functions": {}, @@ -2056696,7 +2060070,14 @@ "type": "PCIE_INT_INTERFACE_R" }, "PCIE_INT_INTERFACE_R_X111Y216": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00003780", + "frames": 28, + "offset": 32, + "words": 2 + } + }, "grid_x": 278, "grid_y": 191, "pin_functions": {}, @@ -2056705,7 +2060086,14 @@ "type": "PCIE_INT_INTERFACE_R" }, "PCIE_INT_INTERFACE_R_X111Y217": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00003780", + "frames": 28, + "offset": 34, + "words": 2 + } + }, "grid_x": 278, "grid_y": 190, "pin_functions": {}, @@ -2056714,7 +2060102,14 @@ "type": "PCIE_INT_INTERFACE_R" }, "PCIE_INT_INTERFACE_R_X111Y218": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00003780", + "frames": 28, + "offset": 36, + "words": 2 + } + }, "grid_x": 278, "grid_y": 189, "pin_functions": {}, @@ -2056723,7 +2060118,14 @@ "type": "PCIE_INT_INTERFACE_R" }, "PCIE_INT_INTERFACE_R_X111Y219": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00003780", + "frames": 28, + "offset": 38, + "words": 2 + } + }, "grid_x": 278, "grid_y": 188, "pin_functions": {}, @@ -2056732,7 +2060134,14 @@ "type": "PCIE_INT_INTERFACE_R" }, "PCIE_INT_INTERFACE_R_X111Y220": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00003780", + "frames": 28, + "offset": 40, + "words": 2 + } + }, "grid_x": 278, "grid_y": 187, "pin_functions": {}, @@ -2056741,7 +2060150,14 @@ "type": "PCIE_INT_INTERFACE_R" }, "PCIE_INT_INTERFACE_R_X111Y221": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00003780", + "frames": 28, + "offset": 42, + "words": 2 + } + }, "grid_x": 278, "grid_y": 186, "pin_functions": {}, @@ -2056750,7 +2060166,14 @@ "type": "PCIE_INT_INTERFACE_R" }, "PCIE_INT_INTERFACE_R_X111Y222": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00003780", + "frames": 28, + "offset": 44, + "words": 2 + } + }, "grid_x": 278, "grid_y": 185, "pin_functions": {}, @@ -2056759,7 +2060182,14 @@ "type": "PCIE_INT_INTERFACE_R" }, "PCIE_INT_INTERFACE_R_X111Y223": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00003780", + "frames": 28, + "offset": 46, + "words": 2 + } + }, "grid_x": 278, "grid_y": 184, "pin_functions": {}, @@ -2056768,7 +2060198,14 @@ "type": "PCIE_INT_INTERFACE_R" }, "PCIE_INT_INTERFACE_R_X111Y224": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00003780", + "frames": 28, + "offset": 48, + "words": 2 + } + }, "grid_x": 278, "grid_y": 183, "pin_functions": {}, diff --git a/kintex7/xc7k70t/tilegrid.json b/kintex7/xc7k70t/tilegrid.json index ab54768..35e70c9 100644 --- a/kintex7/xc7k70t/tilegrid.json +++ b/kintex7/xc7k70t/tilegrid.json @@ -338034,7 +338034,14 @@ "type": "NULL" }, "PCIE_BOT_X73Y115": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00000D80", + "frames": 36, + "offset": 0, + "words": 101 + } + }, "clock_region": "X1Y2", "grid_x": 73, "grid_y": 93, @@ -338046,7 +338053,14 @@ "type": "PCIE_BOT" }, "PCIE_INT_INTERFACE_L_X30Y100": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00000F00", + "frames": 28, + "offset": 0, + "words": 2 + } + }, "grid_x": 78, "grid_y": 103, "pin_functions": {}, @@ -338055,7 +338069,14 @@ "type": "PCIE_INT_INTERFACE_L" }, "PCIE_INT_INTERFACE_L_X30Y101": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00000F00", + "frames": 28, + "offset": 2, + "words": 2 + } + }, "grid_x": 78, "grid_y": 102, "pin_functions": {}, @@ -338064,7 +338085,14 @@ "type": "PCIE_INT_INTERFACE_L" }, "PCIE_INT_INTERFACE_L_X30Y102": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00000F00", + "frames": 28, + "offset": 4, + "words": 2 + } + }, "grid_x": 78, "grid_y": 101, "pin_functions": {}, @@ -338073,7 +338101,14 @@ "type": "PCIE_INT_INTERFACE_L" }, "PCIE_INT_INTERFACE_L_X30Y103": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00000F00", + "frames": 28, + "offset": 6, + "words": 2 + } + }, "grid_x": 78, "grid_y": 100, "pin_functions": {}, @@ -338082,7 +338117,14 @@ "type": "PCIE_INT_INTERFACE_L" }, "PCIE_INT_INTERFACE_L_X30Y104": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00000F00", + "frames": 28, + "offset": 8, + "words": 2 + } + }, "grid_x": 78, "grid_y": 99, "pin_functions": {}, @@ -338091,7 +338133,14 @@ "type": "PCIE_INT_INTERFACE_L" }, "PCIE_INT_INTERFACE_L_X30Y105": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00000F00", + "frames": 28, + "offset": 10, + "words": 2 + } + }, "grid_x": 78, "grid_y": 98, "pin_functions": {}, @@ -338100,7 +338149,14 @@ "type": "PCIE_INT_INTERFACE_L" }, "PCIE_INT_INTERFACE_L_X30Y106": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00000F00", + "frames": 28, + "offset": 12, + "words": 2 + } + }, "grid_x": 78, "grid_y": 97, "pin_functions": {}, @@ -338109,7 +338165,14 @@ "type": "PCIE_INT_INTERFACE_L" }, "PCIE_INT_INTERFACE_L_X30Y107": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00000F00", + "frames": 28, + "offset": 14, + "words": 2 + } + }, "grid_x": 78, "grid_y": 96, "pin_functions": {}, @@ -338118,7 +338181,14 @@ "type": "PCIE_INT_INTERFACE_L" }, "PCIE_INT_INTERFACE_L_X30Y108": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00000F00", + "frames": 28, + "offset": 16, + "words": 2 + } + }, "grid_x": 78, "grid_y": 95, "pin_functions": {}, @@ -338127,7 +338197,14 @@ "type": "PCIE_INT_INTERFACE_L" }, "PCIE_INT_INTERFACE_L_X30Y109": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00000F00", + "frames": 28, + "offset": 18, + "words": 2 + } + }, "grid_x": 78, "grid_y": 94, "pin_functions": {}, @@ -338136,7 +338213,14 @@ "type": "PCIE_INT_INTERFACE_L" }, "PCIE_INT_INTERFACE_L_X30Y110": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00000F00", + "frames": 28, + "offset": 20, + "words": 2 + } + }, "grid_x": 78, "grid_y": 93, "pin_functions": {}, @@ -338145,7 +338229,14 @@ "type": "PCIE_INT_INTERFACE_L" }, "PCIE_INT_INTERFACE_L_X30Y111": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00000F00", + "frames": 28, + "offset": 22, + "words": 2 + } + }, "grid_x": 78, "grid_y": 92, "pin_functions": {}, @@ -338154,7 +338245,14 @@ "type": "PCIE_INT_INTERFACE_L" }, "PCIE_INT_INTERFACE_L_X30Y112": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00000F00", + "frames": 28, + "offset": 24, + "words": 2 + } + }, "grid_x": 78, "grid_y": 91, "pin_functions": {}, @@ -338163,7 +338261,14 @@ "type": "PCIE_INT_INTERFACE_L" }, "PCIE_INT_INTERFACE_L_X30Y113": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00000F00", + "frames": 28, + "offset": 26, + "words": 2 + } + }, "grid_x": 78, "grid_y": 90, "pin_functions": {}, @@ -338172,7 +338277,14 @@ "type": "PCIE_INT_INTERFACE_L" }, "PCIE_INT_INTERFACE_L_X30Y114": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00000F00", + "frames": 28, + "offset": 28, + "words": 2 + } + }, "grid_x": 78, "grid_y": 89, "pin_functions": {}, @@ -338181,7 +338293,14 @@ "type": "PCIE_INT_INTERFACE_L" }, "PCIE_INT_INTERFACE_L_X30Y115": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00000F00", + "frames": 28, + "offset": 30, + "words": 2 + } + }, "grid_x": 78, "grid_y": 88, "pin_functions": {}, @@ -338190,7 +338309,14 @@ "type": "PCIE_INT_INTERFACE_L" }, "PCIE_INT_INTERFACE_L_X30Y116": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00000F00", + "frames": 28, + "offset": 32, + "words": 2 + } + }, "grid_x": 78, "grid_y": 87, "pin_functions": {}, @@ -338199,7 +338325,14 @@ "type": "PCIE_INT_INTERFACE_L" }, "PCIE_INT_INTERFACE_L_X30Y117": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00000F00", + "frames": 28, + "offset": 34, + "words": 2 + } + }, "grid_x": 78, "grid_y": 86, "pin_functions": {}, @@ -338208,7 +338341,14 @@ "type": "PCIE_INT_INTERFACE_L" }, "PCIE_INT_INTERFACE_L_X30Y118": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00000F00", + "frames": 28, + "offset": 36, + "words": 2 + } + }, "grid_x": 78, "grid_y": 85, "pin_functions": {}, @@ -338217,7 +338357,14 @@ "type": "PCIE_INT_INTERFACE_L" }, "PCIE_INT_INTERFACE_L_X30Y119": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00000F00", + "frames": 28, + "offset": 38, + "words": 2 + } + }, "grid_x": 78, "grid_y": 84, "pin_functions": {}, @@ -338226,7 +338373,14 @@ "type": "PCIE_INT_INTERFACE_L" }, "PCIE_INT_INTERFACE_L_X30Y120": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00000F00", + "frames": 28, + "offset": 40, + "words": 2 + } + }, "grid_x": 78, "grid_y": 83, "pin_functions": {}, @@ -338235,7 +338389,14 @@ "type": "PCIE_INT_INTERFACE_L" }, "PCIE_INT_INTERFACE_L_X30Y121": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00000F00", + "frames": 28, + "offset": 42, + "words": 2 + } + }, "grid_x": 78, "grid_y": 82, "pin_functions": {}, @@ -338244,7 +338405,14 @@ "type": "PCIE_INT_INTERFACE_L" }, "PCIE_INT_INTERFACE_L_X30Y122": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00000F00", + "frames": 28, + "offset": 44, + "words": 2 + } + }, "grid_x": 78, "grid_y": 81, "pin_functions": {}, @@ -338253,7 +338421,14 @@ "type": "PCIE_INT_INTERFACE_L" }, "PCIE_INT_INTERFACE_L_X30Y123": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00000F00", + "frames": 28, + "offset": 46, + "words": 2 + } + }, "grid_x": 78, "grid_y": 80, "pin_functions": {}, @@ -338262,7 +338437,14 @@ "type": "PCIE_INT_INTERFACE_L" }, "PCIE_INT_INTERFACE_L_X30Y124": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00000F00", + "frames": 28, + "offset": 48, + "words": 2 + } + }, "grid_x": 78, "grid_y": 79, "pin_functions": {}, @@ -338271,7 +338453,14 @@ "type": "PCIE_INT_INTERFACE_L" }, "PCIE_INT_INTERFACE_R_X27Y100": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00000D80", + "frames": 28, + "offset": 0, + "words": 2 + } + }, "grid_x": 72, "grid_y": 103, "pin_functions": {}, @@ -338280,7 +338469,14 @@ "type": "PCIE_INT_INTERFACE_R" }, "PCIE_INT_INTERFACE_R_X27Y101": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00000D80", + "frames": 28, + "offset": 2, + "words": 2 + } + }, "grid_x": 72, "grid_y": 102, "pin_functions": {}, @@ -338289,7 +338485,14 @@ "type": "PCIE_INT_INTERFACE_R" }, "PCIE_INT_INTERFACE_R_X27Y102": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00000D80", + "frames": 28, + "offset": 4, + "words": 2 + } + }, "grid_x": 72, "grid_y": 101, "pin_functions": {}, @@ -338298,7 +338501,14 @@ "type": "PCIE_INT_INTERFACE_R" }, "PCIE_INT_INTERFACE_R_X27Y103": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00000D80", + "frames": 28, + "offset": 6, + "words": 2 + } + }, "grid_x": 72, "grid_y": 100, "pin_functions": {}, @@ -338307,7 +338517,14 @@ "type": "PCIE_INT_INTERFACE_R" }, "PCIE_INT_INTERFACE_R_X27Y104": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00000D80", + "frames": 28, + "offset": 8, + "words": 2 + } + }, "grid_x": 72, "grid_y": 99, "pin_functions": {}, @@ -338316,7 +338533,14 @@ "type": "PCIE_INT_INTERFACE_R" }, "PCIE_INT_INTERFACE_R_X27Y105": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00000D80", + "frames": 28, + "offset": 10, + "words": 2 + } + }, "grid_x": 72, "grid_y": 98, "pin_functions": {}, @@ -338325,7 +338549,14 @@ "type": "PCIE_INT_INTERFACE_R" }, "PCIE_INT_INTERFACE_R_X27Y106": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00000D80", + "frames": 28, + "offset": 12, + "words": 2 + } + }, "grid_x": 72, "grid_y": 97, "pin_functions": {}, @@ -338334,7 +338565,14 @@ "type": "PCIE_INT_INTERFACE_R" }, "PCIE_INT_INTERFACE_R_X27Y107": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00000D80", + "frames": 28, + "offset": 14, + "words": 2 + } + }, "grid_x": 72, "grid_y": 96, "pin_functions": {}, @@ -338343,7 +338581,14 @@ "type": "PCIE_INT_INTERFACE_R" }, "PCIE_INT_INTERFACE_R_X27Y108": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00000D80", + "frames": 28, + "offset": 16, + "words": 2 + } + }, "grid_x": 72, "grid_y": 95, "pin_functions": {}, @@ -338352,7 +338597,14 @@ "type": "PCIE_INT_INTERFACE_R" }, "PCIE_INT_INTERFACE_R_X27Y109": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00000D80", + "frames": 28, + "offset": 18, + "words": 2 + } + }, "grid_x": 72, "grid_y": 94, "pin_functions": {}, @@ -338361,7 +338613,14 @@ "type": "PCIE_INT_INTERFACE_R" }, "PCIE_INT_INTERFACE_R_X27Y110": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00000D80", + "frames": 28, + "offset": 20, + "words": 2 + } + }, "grid_x": 72, "grid_y": 93, "pin_functions": {}, @@ -338370,7 +338629,14 @@ "type": "PCIE_INT_INTERFACE_R" }, "PCIE_INT_INTERFACE_R_X27Y111": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00000D80", + "frames": 28, + "offset": 22, + "words": 2 + } + }, "grid_x": 72, "grid_y": 92, "pin_functions": {}, @@ -338379,7 +338645,14 @@ "type": "PCIE_INT_INTERFACE_R" }, "PCIE_INT_INTERFACE_R_X27Y112": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00000D80", + "frames": 28, + "offset": 24, + "words": 2 + } + }, "grid_x": 72, "grid_y": 91, "pin_functions": {}, @@ -338388,7 +338661,14 @@ "type": "PCIE_INT_INTERFACE_R" }, "PCIE_INT_INTERFACE_R_X27Y113": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00000D80", + "frames": 28, + "offset": 26, + "words": 2 + } + }, "grid_x": 72, "grid_y": 90, "pin_functions": {}, @@ -338397,7 +338677,14 @@ "type": "PCIE_INT_INTERFACE_R" }, "PCIE_INT_INTERFACE_R_X27Y114": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00000D80", + "frames": 28, + "offset": 28, + "words": 2 + } + }, "grid_x": 72, "grid_y": 89, "pin_functions": {}, @@ -338406,7 +338693,14 @@ "type": "PCIE_INT_INTERFACE_R" }, "PCIE_INT_INTERFACE_R_X27Y115": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00000D80", + "frames": 28, + "offset": 30, + "words": 2 + } + }, "grid_x": 72, "grid_y": 88, "pin_functions": {}, @@ -338415,7 +338709,14 @@ "type": "PCIE_INT_INTERFACE_R" }, "PCIE_INT_INTERFACE_R_X27Y116": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00000D80", + "frames": 28, + "offset": 32, + "words": 2 + } + }, "grid_x": 72, "grid_y": 87, "pin_functions": {}, @@ -338424,7 +338725,14 @@ "type": "PCIE_INT_INTERFACE_R" }, "PCIE_INT_INTERFACE_R_X27Y117": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00000D80", + "frames": 28, + "offset": 34, + "words": 2 + } + }, "grid_x": 72, "grid_y": 86, "pin_functions": {}, @@ -338433,7 +338741,14 @@ "type": "PCIE_INT_INTERFACE_R" }, "PCIE_INT_INTERFACE_R_X27Y118": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00000D80", + "frames": 28, + "offset": 36, + "words": 2 + } + }, "grid_x": 72, "grid_y": 85, "pin_functions": {}, @@ -338442,7 +338757,14 @@ "type": "PCIE_INT_INTERFACE_R" }, "PCIE_INT_INTERFACE_R_X27Y119": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00000D80", + "frames": 28, + "offset": 38, + "words": 2 + } + }, "grid_x": 72, "grid_y": 84, "pin_functions": {}, @@ -338451,7 +338773,14 @@ "type": "PCIE_INT_INTERFACE_R" }, "PCIE_INT_INTERFACE_R_X27Y120": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00000D80", + "frames": 28, + "offset": 40, + "words": 2 + } + }, "grid_x": 72, "grid_y": 83, "pin_functions": {}, @@ -338460,7 +338789,14 @@ "type": "PCIE_INT_INTERFACE_R" }, "PCIE_INT_INTERFACE_R_X27Y121": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00000D80", + "frames": 28, + "offset": 42, + "words": 2 + } + }, "grid_x": 72, "grid_y": 82, "pin_functions": {}, @@ -338469,7 +338805,14 @@ "type": "PCIE_INT_INTERFACE_R" }, "PCIE_INT_INTERFACE_R_X27Y122": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00000D80", + "frames": 28, + "offset": 44, + "words": 2 + } + }, "grid_x": 72, "grid_y": 81, "pin_functions": {}, @@ -338478,7 +338821,14 @@ "type": "PCIE_INT_INTERFACE_R" }, "PCIE_INT_INTERFACE_R_X27Y123": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00000D80", + "frames": 28, + "offset": 46, + "words": 2 + } + }, "grid_x": 72, "grid_y": 80, "pin_functions": {}, @@ -338487,7 +338837,14 @@ "type": "PCIE_INT_INTERFACE_R" }, "PCIE_INT_INTERFACE_R_X27Y124": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00000D80", + "frames": 28, + "offset": 48, + "words": 2 + } + }, "grid_x": 72, "grid_y": 79, "pin_functions": {},